1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2019 Intel Corporation. All rights rsvd. */
6 #include <linux/sbitmap.h>
7 #include <linux/dmaengine.h>
8 #include <linux/percpu-rwsem.h>
9 #include <linux/wait.h>
10 #include <linux/cdev.h>
11 #include <linux/idr.h>
12 #include <linux/pci.h>
13 #include <linux/bitmap.h>
14 #include <linux/perf_event.h>
15 #include <linux/iommu.h>
16 #include <uapi/linux/idxd.h>
17 #include "registers.h"
19 #define IDXD_DRIVER_VERSION "1.00"
21 extern struct kmem_cache *idxd_desc_pool;
22 extern bool tc_override;
40 struct device conf_dev;
41 enum idxd_dev_type type;
44 #define IDXD_REG_TIMEOUT 50
45 #define IDXD_DRAIN_TIMEOUT 5000
48 IDXD_TYPE_UNKNOWN = -1,
54 #define IDXD_NAME_SIZE 128
55 #define IDXD_PMU_EVENT_MAX 64
57 #define IDXD_ENQCMDS_RETRIES 32
58 #define IDXD_ENQCMDS_MAX_RETRIES 64
60 struct idxd_device_driver {
62 enum idxd_dev_type *type;
63 int (*probe)(struct idxd_dev *idxd_dev);
64 void (*remove)(struct idxd_dev *idxd_dev);
65 struct device_driver drv;
68 extern struct idxd_device_driver dsa_drv;
69 extern struct idxd_device_driver idxd_drv;
70 extern struct idxd_device_driver idxd_dmaengine_drv;
71 extern struct idxd_device_driver idxd_user_drv;
73 #define INVALID_INT_HANDLE -1
74 struct idxd_irq_entry {
77 struct llist_head pending_llist;
78 struct list_head work_list;
80 * Lock to protect access between irq thread process descriptor
81 * and irq thread processing error descriptor.
89 struct idxd_dev idxd_dev;
90 struct idxd_device *idxd;
100 int desc_progress_limit;
101 int batch_progress_limit;
105 struct idxd_device *idxd;
107 struct perf_event *event_list[IDXD_PMU_EVENT_MAX];
110 DECLARE_BITMAP(used_mask, IDXD_PMU_EVENT_MAX);
113 char name[IDXD_NAME_SIZE];
118 int n_event_categories;
120 bool per_counter_caps_supported;
121 unsigned long supported_event_categories;
123 unsigned long supported_filters;
126 struct hlist_node cpuhp_node;
129 #define IDXD_MAX_PRIORITY 0xf
138 IDXD_WQ_DISABLED = 0,
143 WQ_FLAG_DEDICATED = 0,
144 WQ_FLAG_BLOCK_ON_FAULT,
158 struct idxd_dev idxd_dev;
162 #define IDXD_ALLOCATED_BATCH_SIZE 128U
163 #define WQ_NAME_SIZE 1024
164 #define WQ_TYPE_SIZE 10
166 #define WQ_DEFAULT_QUEUE_DEPTH 16
167 #define WQ_DEFAULT_MAX_XFER SZ_2M
168 #define WQ_DEFAULT_MAX_BATCH 32
172 IDXD_OP_NONBLOCK = 1,
175 enum idxd_complete_type {
176 IDXD_COMPLETE_NORMAL = 0,
178 IDXD_COMPLETE_DEV_FAIL,
181 struct idxd_dma_chan {
182 struct dma_chan chan;
187 void __iomem *portal;
189 unsigned int enqcmds_retries;
190 struct percpu_ref wq_active;
191 struct completion wq_dead;
192 struct completion wq_resurrect;
193 struct idxd_dev idxd_dev;
194 struct idxd_cdev *idxd_cdev;
195 struct wait_queue_head err_queue;
196 struct workqueue_struct *wq;
197 struct idxd_device *idxd;
199 struct idxd_irq_entry ie;
200 enum idxd_wq_type type;
201 struct idxd_group *group;
203 struct mutex wq_lock; /* mutex for workqueue */
207 enum idxd_wq_state state;
210 unsigned long *opcap_bmap;
212 struct dsa_hw_desc **hw_descs;
215 struct dsa_completion_record *compls;
216 struct iax_completion_record *iax_compls;
218 dma_addr_t compls_addr;
220 struct idxd_desc **descs;
221 struct sbitmap_queue sbq;
222 struct idxd_dma_chan *idxd_chan;
223 char name[WQ_NAME_SIZE + 1];
227 /* Lock to protect upasid_xa access. */
228 struct mutex uc_lock;
229 struct xarray upasid_xa;
233 struct idxd_dev idxd_dev;
235 struct idxd_group *group;
236 struct idxd_device *idxd;
239 /* shadow registers */
242 union gen_cap_reg gen_cap;
243 union wq_cap_reg wq_cap;
244 union group_cap_reg group_cap;
245 union engine_cap_reg engine_cap;
248 union iaa_cap_reg iaa_cap;
251 enum idxd_device_state {
252 IDXD_DEV_HALTED = -1,
253 IDXD_DEV_DISABLED = 0,
257 enum idxd_device_flag {
258 IDXD_FLAG_CONFIGURABLE = 0,
259 IDXD_FLAG_CMD_RUNNING,
260 IDXD_FLAG_PASID_ENABLED,
261 IDXD_FLAG_USER_PASID_ENABLED,
264 struct idxd_dma_dev {
265 struct idxd_device *idxd;
266 struct dma_device dma;
269 struct idxd_driver_data {
270 const char *name_prefix;
272 struct device_type *dev_type;
281 /* Lock to protect event log access. */
285 /* Total size of event log = number of entries * entry size. */
286 unsigned int log_size;
287 /* The number of entries in the event log. */
291 bool batch_fail[IDXD_MAX_BATCH_IDENT];
294 struct idxd_evl_fault {
295 struct work_struct work;
299 /* make this last member always */
300 struct __evl_entry entry[];
304 struct idxd_dev idxd_dev;
305 struct idxd_driver_data *data;
306 struct list_head list;
308 enum idxd_device_state state;
313 struct idxd_irq_entry ie; /* misc irq, msix 0 */
315 struct pci_dev *pdev;
316 void __iomem *reg_base;
318 spinlock_t dev_lock; /* spinlock for device */
319 spinlock_t cmd_lock; /* spinlock for device commands */
320 struct completion *cmd_done;
321 struct idxd_group **groups;
322 struct idxd_wq **wqs;
323 struct idxd_engine **engines;
325 struct iommu_sva *sva;
330 bool request_int_handles;
332 u32 msix_perm_offset;
345 int nr_rdbufs; /* non-reserved read buffers */
346 unsigned int wqcfg_size;
347 unsigned long *wq_enable_map;
349 union sw_err_reg sw_err;
350 wait_queue_head_t cmd_waitq;
352 struct idxd_dma_dev *idxd_dma;
353 struct workqueue_struct *wq;
354 struct work_struct work;
356 struct idxd_pmu *idxd_pmu;
358 unsigned long *opcap_bmap;
359 struct idxd_evl *evl;
360 struct kmem_cache *evl_cache;
362 struct dentry *dbgfs_dir;
363 struct dentry *dbgfs_evl_file;
366 static inline unsigned int evl_ent_size(struct idxd_device *idxd)
368 return idxd->hw.gen_cap.evl_support ?
369 (32 * (1 << idxd->hw.gen_cap.evl_support)) : 0;
372 static inline unsigned int evl_size(struct idxd_device *idxd)
374 return idxd->evl->size * evl_ent_size(idxd);
377 /* IDXD software descriptor */
380 struct dsa_hw_desc *hw;
381 struct iax_hw_desc *iax_hw;
385 struct dsa_completion_record *completion;
386 struct iax_completion_record *iax_completion;
388 dma_addr_t compl_dma;
389 struct dma_async_tx_descriptor txd;
390 struct llist_node llnode;
391 struct list_head list;
398 * This is software defined error for the completion status. We overload the error code
399 * that will never appear in completion status and only SWERR register.
401 enum idxd_completion_status {
402 IDXD_COMP_DESC_ABORT = 0xff,
405 #define idxd_confdev(idxd) &idxd->idxd_dev.conf_dev
406 #define wq_confdev(wq) &wq->idxd_dev.conf_dev
407 #define engine_confdev(engine) &engine->idxd_dev.conf_dev
408 #define group_confdev(group) &group->idxd_dev.conf_dev
409 #define cdev_dev(cdev) &cdev->idxd_dev.conf_dev
410 #define user_ctx_dev(ctx) (&(ctx)->idxd_dev.conf_dev)
412 #define confdev_to_idxd_dev(dev) container_of(dev, struct idxd_dev, conf_dev)
413 #define idxd_dev_to_idxd(idxd_dev) container_of(idxd_dev, struct idxd_device, idxd_dev)
414 #define idxd_dev_to_wq(idxd_dev) container_of(idxd_dev, struct idxd_wq, idxd_dev)
416 static inline struct idxd_device *confdev_to_idxd(struct device *dev)
418 struct idxd_dev *idxd_dev = confdev_to_idxd_dev(dev);
420 return idxd_dev_to_idxd(idxd_dev);
423 static inline struct idxd_wq *confdev_to_wq(struct device *dev)
425 struct idxd_dev *idxd_dev = confdev_to_idxd_dev(dev);
427 return idxd_dev_to_wq(idxd_dev);
430 static inline struct idxd_engine *confdev_to_engine(struct device *dev)
432 struct idxd_dev *idxd_dev = confdev_to_idxd_dev(dev);
434 return container_of(idxd_dev, struct idxd_engine, idxd_dev);
437 static inline struct idxd_group *confdev_to_group(struct device *dev)
439 struct idxd_dev *idxd_dev = confdev_to_idxd_dev(dev);
441 return container_of(idxd_dev, struct idxd_group, idxd_dev);
444 static inline struct idxd_cdev *dev_to_cdev(struct device *dev)
446 struct idxd_dev *idxd_dev = confdev_to_idxd_dev(dev);
448 return container_of(idxd_dev, struct idxd_cdev, idxd_dev);
451 static inline void idxd_dev_set_type(struct idxd_dev *idev, int type)
453 if (type >= IDXD_DEV_MAX_TYPE) {
454 idev->type = IDXD_DEV_NONE;
461 static inline struct idxd_irq_entry *idxd_get_ie(struct idxd_device *idxd, int idx)
463 return (idx == 0) ? &idxd->ie : &idxd->wqs[idx - 1]->ie;
466 static inline struct idxd_wq *ie_to_wq(struct idxd_irq_entry *ie)
468 return container_of(ie, struct idxd_wq, ie);
471 static inline struct idxd_device *ie_to_idxd(struct idxd_irq_entry *ie)
473 return container_of(ie, struct idxd_device, ie);
476 static inline void idxd_set_user_intr(struct idxd_device *idxd, bool enable)
478 union gencfg_reg reg;
480 reg.bits = ioread32(idxd->reg_base + IDXD_GENCFG_OFFSET);
481 reg.user_int_en = enable;
482 iowrite32(reg.bits, idxd->reg_base + IDXD_GENCFG_OFFSET);
485 extern struct bus_type dsa_bus_type;
487 extern bool support_enqcmd;
488 extern struct ida idxd_ida;
489 extern struct device_type dsa_device_type;
490 extern struct device_type iax_device_type;
491 extern struct device_type idxd_wq_device_type;
492 extern struct device_type idxd_engine_device_type;
493 extern struct device_type idxd_group_device_type;
495 static inline bool is_dsa_dev(struct idxd_dev *idxd_dev)
497 return idxd_dev->type == IDXD_DEV_DSA;
500 static inline bool is_iax_dev(struct idxd_dev *idxd_dev)
502 return idxd_dev->type == IDXD_DEV_IAX;
505 static inline bool is_idxd_dev(struct idxd_dev *idxd_dev)
507 return is_dsa_dev(idxd_dev) || is_iax_dev(idxd_dev);
510 static inline bool is_idxd_wq_dev(struct idxd_dev *idxd_dev)
512 return idxd_dev->type == IDXD_DEV_WQ;
515 static inline bool is_idxd_wq_dmaengine(struct idxd_wq *wq)
517 if (wq->type == IDXD_WQT_KERNEL && strcmp(wq->name, "dmaengine") == 0)
522 static inline bool is_idxd_wq_user(struct idxd_wq *wq)
524 return wq->type == IDXD_WQT_USER;
527 static inline bool is_idxd_wq_kernel(struct idxd_wq *wq)
529 return wq->type == IDXD_WQT_KERNEL;
532 static inline bool wq_dedicated(struct idxd_wq *wq)
534 return test_bit(WQ_FLAG_DEDICATED, &wq->flags);
537 static inline bool wq_shared(struct idxd_wq *wq)
539 return !test_bit(WQ_FLAG_DEDICATED, &wq->flags);
542 static inline bool device_pasid_enabled(struct idxd_device *idxd)
544 return test_bit(IDXD_FLAG_PASID_ENABLED, &idxd->flags);
547 static inline bool device_user_pasid_enabled(struct idxd_device *idxd)
549 return test_bit(IDXD_FLAG_USER_PASID_ENABLED, &idxd->flags);
552 static inline bool wq_pasid_enabled(struct idxd_wq *wq)
554 return (is_idxd_wq_kernel(wq) && device_pasid_enabled(wq->idxd)) ||
555 (is_idxd_wq_user(wq) && device_user_pasid_enabled(wq->idxd));
558 static inline bool wq_shared_supported(struct idxd_wq *wq)
560 return (support_enqcmd && wq_pasid_enabled(wq));
563 enum idxd_portal_prot {
564 IDXD_PORTAL_UNLIMITED = 0,
568 enum idxd_interrupt_type {
573 static inline int idxd_get_wq_portal_offset(enum idxd_portal_prot prot)
575 return prot * 0x1000;
578 static inline int idxd_get_wq_portal_full_offset(int wq_id,
579 enum idxd_portal_prot prot)
581 return ((wq_id * 4) << PAGE_SHIFT) + idxd_get_wq_portal_offset(prot);
584 #define IDXD_PORTAL_MASK (PAGE_SIZE - 1)
587 * Even though this function can be accessed by multiple threads, it is safe to use.
588 * At worst the address gets used more than once before it gets incremented. We don't
589 * hit a threshold until iops becomes many million times a second. So the occasional
590 * reuse of the same address is tolerable compare to using an atomic variable. This is
591 * safe on a system that has atomic load/store for 32bit integers. Given that this is an
592 * Intel iEP device, that should not be a problem.
594 static inline void __iomem *idxd_wq_portal_addr(struct idxd_wq *wq)
596 int ofs = wq->portal_offset;
598 wq->portal_offset = (ofs + sizeof(struct dsa_raw_desc)) & IDXD_PORTAL_MASK;
599 return wq->portal + ofs;
602 static inline void idxd_wq_get(struct idxd_wq *wq)
607 static inline void idxd_wq_put(struct idxd_wq *wq)
612 static inline int idxd_wq_refcount(struct idxd_wq *wq)
614 return wq->client_count;
618 * Intel IAA does not support batch processing.
619 * The max batch size of device, max batch size of wq and
620 * max batch shift of wqcfg should be always 0 on IAA.
622 static inline void idxd_set_max_batch_size(int idxd_type, struct idxd_device *idxd,
625 if (idxd_type == IDXD_TYPE_IAX)
626 idxd->max_batch_size = 0;
628 idxd->max_batch_size = max_batch_size;
631 static inline void idxd_wq_set_max_batch_size(int idxd_type, struct idxd_wq *wq,
634 if (idxd_type == IDXD_TYPE_IAX)
635 wq->max_batch_size = 0;
637 wq->max_batch_size = max_batch_size;
640 static inline void idxd_wqcfg_set_max_batch_shift(int idxd_type, union wqcfg *wqcfg,
643 if (idxd_type == IDXD_TYPE_IAX)
644 wqcfg->max_batch_shift = 0;
646 wqcfg->max_batch_shift = max_batch_shift;
649 int __must_check __idxd_driver_register(struct idxd_device_driver *idxd_drv,
650 struct module *module, const char *mod_name);
651 #define idxd_driver_register(driver) \
652 __idxd_driver_register(driver, THIS_MODULE, KBUILD_MODNAME)
654 void idxd_driver_unregister(struct idxd_device_driver *idxd_drv);
656 #define module_idxd_driver(__idxd_driver) \
657 module_driver(__idxd_driver, idxd_driver_register, idxd_driver_unregister)
659 int idxd_register_bus_type(void);
660 void idxd_unregister_bus_type(void);
661 int idxd_register_devices(struct idxd_device *idxd);
662 void idxd_unregister_devices(struct idxd_device *idxd);
663 void idxd_wqs_quiesce(struct idxd_device *idxd);
664 bool idxd_queue_int_handle_resubmit(struct idxd_desc *desc);
665 void multi_u64_to_bmap(unsigned long *bmap, u64 *val, int count);
667 /* device interrupt control */
668 irqreturn_t idxd_misc_thread(int vec, void *data);
669 irqreturn_t idxd_wq_thread(int irq, void *data);
670 void idxd_mask_error_interrupts(struct idxd_device *idxd);
671 void idxd_unmask_error_interrupts(struct idxd_device *idxd);
674 int idxd_device_drv_probe(struct idxd_dev *idxd_dev);
675 void idxd_device_drv_remove(struct idxd_dev *idxd_dev);
676 int drv_enable_wq(struct idxd_wq *wq);
677 void drv_disable_wq(struct idxd_wq *wq);
678 int idxd_device_init_reset(struct idxd_device *idxd);
679 int idxd_device_enable(struct idxd_device *idxd);
680 int idxd_device_disable(struct idxd_device *idxd);
681 void idxd_device_reset(struct idxd_device *idxd);
682 void idxd_device_clear_state(struct idxd_device *idxd);
683 int idxd_device_config(struct idxd_device *idxd);
684 void idxd_device_drain_pasid(struct idxd_device *idxd, int pasid);
685 int idxd_device_load_config(struct idxd_device *idxd);
686 int idxd_device_request_int_handle(struct idxd_device *idxd, int idx, int *handle,
687 enum idxd_interrupt_type irq_type);
688 int idxd_device_release_int_handle(struct idxd_device *idxd, int handle,
689 enum idxd_interrupt_type irq_type);
691 /* work queue control */
692 void idxd_wqs_unmap_portal(struct idxd_device *idxd);
693 int idxd_wq_alloc_resources(struct idxd_wq *wq);
694 void idxd_wq_free_resources(struct idxd_wq *wq);
695 int idxd_wq_enable(struct idxd_wq *wq);
696 int idxd_wq_disable(struct idxd_wq *wq, bool reset_config);
697 void idxd_wq_drain(struct idxd_wq *wq);
698 void idxd_wq_reset(struct idxd_wq *wq);
699 int idxd_wq_map_portal(struct idxd_wq *wq);
700 void idxd_wq_unmap_portal(struct idxd_wq *wq);
701 int idxd_wq_set_pasid(struct idxd_wq *wq, int pasid);
702 int idxd_wq_disable_pasid(struct idxd_wq *wq);
703 void __idxd_wq_quiesce(struct idxd_wq *wq);
704 void idxd_wq_quiesce(struct idxd_wq *wq);
705 int idxd_wq_init_percpu_ref(struct idxd_wq *wq);
706 void idxd_wq_free_irq(struct idxd_wq *wq);
707 int idxd_wq_request_irq(struct idxd_wq *wq);
710 int idxd_submit_desc(struct idxd_wq *wq, struct idxd_desc *desc);
711 struct idxd_desc *idxd_alloc_desc(struct idxd_wq *wq, enum idxd_op_type optype);
712 void idxd_free_desc(struct idxd_wq *wq, struct idxd_desc *desc);
713 int idxd_enqcmds(struct idxd_wq *wq, void __iomem *portal, const void *desc);
716 int idxd_register_dma_device(struct idxd_device *idxd);
717 void idxd_unregister_dma_device(struct idxd_device *idxd);
718 void idxd_dma_complete_txd(struct idxd_desc *desc,
719 enum idxd_complete_type comp_type, bool free_desc);
722 int idxd_cdev_register(void);
723 void idxd_cdev_remove(void);
724 int idxd_cdev_get_major(struct idxd_device *idxd);
725 int idxd_wq_add_cdev(struct idxd_wq *wq);
726 void idxd_wq_del_cdev(struct idxd_wq *wq);
727 int idxd_copy_cr(struct idxd_wq *wq, ioasid_t pasid, unsigned long addr,
729 void idxd_user_counter_increment(struct idxd_wq *wq, u32 pasid, int index);
732 #if IS_ENABLED(CONFIG_INTEL_IDXD_PERFMON)
733 int perfmon_pmu_init(struct idxd_device *idxd);
734 void perfmon_pmu_remove(struct idxd_device *idxd);
735 void perfmon_counter_overflow(struct idxd_device *idxd);
736 void perfmon_init(void);
737 void perfmon_exit(void);
739 static inline int perfmon_pmu_init(struct idxd_device *idxd) { return 0; }
740 static inline void perfmon_pmu_remove(struct idxd_device *idxd) {}
741 static inline void perfmon_counter_overflow(struct idxd_device *idxd) {}
742 static inline void perfmon_init(void) {}
743 static inline void perfmon_exit(void) {}
747 int idxd_device_init_debugfs(struct idxd_device *idxd);
748 void idxd_device_remove_debugfs(struct idxd_device *idxd);
749 int idxd_init_debugfs(void);
750 void idxd_remove_debugfs(void);