drivers/dma/imx-dma.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 //
   3 // drivers/dma/imx-dma.c
   4 //
   5 // This file contains a driver for the Freescale i.MX DMA engine
   6 // found on i.MX1/21/27
   7 //
   8 // Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
   9 // Copyright 2012 Javier Martin, Vista Silicon <javier.martin@vista-silicon.com>
  10
  11 #include <linux/err.h>
  12 #include <linux/init.h>
  13 #include <linux/types.h>
  14 #include <linux/mm.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/spinlock.h>
  17 #include <linux/device.h>
  18 #include <linux/dma-mapping.h>
  19 #include <linux/slab.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/clk.h>
  22 #include <linux/dmaengine.h>
  23 #include <linux/module.h>
  24 #include <linux/of_device.h>
  25 #include <linux/of_dma.h>
  26
  27 #include <asm/irq.h>
  28 #include <linux/platform_data/dma-imx.h>
  29
  30 #include "dmaengine.h"
  31 #define IMXDMA_MAX_CHAN_DESCRIPTORS     16
  32 #define IMX_DMA_CHANNELS  16
  33
  34 #define IMX_DMA_2D_SLOTS        2
  35 #define IMX_DMA_2D_SLOT_A       0
  36 #define IMX_DMA_2D_SLOT_B       1
  37
  38 #define IMX_DMA_LENGTH_LOOP     ((unsigned int)-1)
  39 #define IMX_DMA_MEMSIZE_32      (0 << 4)
  40 #define IMX_DMA_MEMSIZE_8       (1 << 4)
  41 #define IMX_DMA_MEMSIZE_16      (2 << 4)
  42 #define IMX_DMA_TYPE_LINEAR     (0 << 10)
  43 #define IMX_DMA_TYPE_2D         (1 << 10)
  44 #define IMX_DMA_TYPE_FIFO       (2 << 10)
  45
  46 #define IMX_DMA_ERR_BURST     (1 << 0)
  47 #define IMX_DMA_ERR_REQUEST   (1 << 1)
  48 #define IMX_DMA_ERR_TRANSFER  (1 << 2)
  49 #define IMX_DMA_ERR_BUFFER    (1 << 3)
  50 #define IMX_DMA_ERR_TIMEOUT   (1 << 4)
  51
  52 #define DMA_DCR     0x00                /* Control Register */
  53 #define DMA_DISR    0x04                /* Interrupt status Register */
  54 #define DMA_DIMR    0x08                /* Interrupt mask Register */
  55 #define DMA_DBTOSR  0x0c                /* Burst timeout status Register */
  56 #define DMA_DRTOSR  0x10                /* Request timeout Register */
  57 #define DMA_DSESR   0x14                /* Transfer Error Status Register */
  58 #define DMA_DBOSR   0x18                /* Buffer overflow status Register */
  59 #define DMA_DBTOCR  0x1c                /* Burst timeout control Register */
  60 #define DMA_WSRA    0x40                /* W-Size Register A */
  61 #define DMA_XSRA    0x44                /* X-Size Register A */
  62 #define DMA_YSRA    0x48                /* Y-Size Register A */
  63 #define DMA_WSRB    0x4c                /* W-Size Register B */
  64 #define DMA_XSRB    0x50                /* X-Size Register B */
  65 #define DMA_YSRB    0x54                /* Y-Size Register B */
  66 #define DMA_SAR(x)  (0x80 + ((x) << 6)) /* Source Address Registers */
  67 #define DMA_DAR(x)  (0x84 + ((x) << 6)) /* Destination Address Registers */
  68 #define DMA_CNTR(x) (0x88 + ((x) << 6)) /* Count Registers */
  69 #define DMA_CCR(x)  (0x8c + ((x) << 6)) /* Control Registers */
  70 #define DMA_RSSR(x) (0x90 + ((x) << 6)) /* Request source select Registers */
  71 #define DMA_BLR(x)  (0x94 + ((x) << 6)) /* Burst length Registers */
  72 #define DMA_RTOR(x) (0x98 + ((x) << 6)) /* Request timeout Registers */
  73 #define DMA_BUCR(x) (0x98 + ((x) << 6)) /* Bus Utilization Registers */
  74 #define DMA_CCNR(x) (0x9C + ((x) << 6)) /* Channel counter Registers */
  75
  76 #define DCR_DRST           (1<<1)
  77 #define DCR_DEN            (1<<0)
  78 #define DBTOCR_EN          (1<<15)
  79 #define DBTOCR_CNT(x)      ((x) & 0x7fff)
  80 #define CNTR_CNT(x)        ((x) & 0xffffff)
  81 #define CCR_ACRPT          (1<<14)
  82 #define CCR_DMOD_LINEAR    (0x0 << 12)
  83 #define CCR_DMOD_2D        (0x1 << 12)
  84 #define CCR_DMOD_FIFO      (0x2 << 12)
  85 #define CCR_DMOD_EOBFIFO   (0x3 << 12)
  86 #define CCR_SMOD_LINEAR    (0x0 << 10)
  87 #define CCR_SMOD_2D        (0x1 << 10)
  88 #define CCR_SMOD_FIFO      (0x2 << 10)
  89 #define CCR_SMOD_EOBFIFO   (0x3 << 10)
  90 #define CCR_MDIR_DEC       (1<<9)
  91 #define CCR_MSEL_B         (1<<8)
  92 #define CCR_DSIZ_32        (0x0 << 6)
  93 #define CCR_DSIZ_8         (0x1 << 6)
  94 #define CCR_DSIZ_16        (0x2 << 6)
  95 #define CCR_SSIZ_32        (0x0 << 4)
  96 #define CCR_SSIZ_8         (0x1 << 4)
  97 #define CCR_SSIZ_16        (0x2 << 4)
  98 #define CCR_REN            (1<<3)
  99 #define CCR_RPT            (1<<2)
 100 #define CCR_FRC            (1<<1)
 101 #define CCR_CEN            (1<<0)
 102 #define RTOR_EN            (1<<15)
 103 #define RTOR_CLK           (1<<14)
 104 #define RTOR_PSC           (1<<13)
 105
 106 enum  imxdma_prep_type {
 107         IMXDMA_DESC_MEMCPY,
 108         IMXDMA_DESC_INTERLEAVED,
 109         IMXDMA_DESC_SLAVE_SG,
 110         IMXDMA_DESC_CYCLIC,
 111 };
 112
 113 struct imx_dma_2d_config {
 114         u16             xsr;
 115         u16             ysr;
 116         u16             wsr;
 117         int             count;
 118 };
 119
 120 struct imxdma_desc {
 121         struct list_head                node;
 122         struct dma_async_tx_descriptor  desc;
 123         enum dma_status                 status;
 124         dma_addr_t                      src;
 125         dma_addr_t                      dest;
 126         size_t                          len;
 127         enum dma_transfer_direction     direction;
 128         enum imxdma_prep_type           type;
 129         /* For memcpy and interleaved */
 130         unsigned int                    config_port;
 131         unsigned int                    config_mem;
 132         /* For interleaved transfers */
 133         unsigned int                    x;
 134         unsigned int                    y;
 135         unsigned int                    w;
 136         /* For slave sg and cyclic */
 137         struct scatterlist              *sg;
 138         unsigned int                    sgcount;
 139 };
 140
 141 struct imxdma_channel {
 142         int                             hw_chaining;
 143         struct timer_list               watchdog;
 144         struct imxdma_engine            *imxdma;
 145         unsigned int                    channel;
 146
 147         struct tasklet_struct           dma_tasklet;
 148         struct list_head                ld_free;
 149         struct list_head                ld_queue;
 150         struct list_head                ld_active;
 151         int                             descs_allocated;
 152         enum dma_slave_buswidth         word_size;
 153         dma_addr_t                      per_address;
 154         u32                             watermark_level;
 155         struct dma_chan                 chan;
 156         struct dma_async_tx_descriptor  desc;
 157         enum dma_status                 status;
 158         int                             dma_request;
 159         struct scatterlist              *sg_list;
 160         u32                             ccr_from_device;
 161         u32                             ccr_to_device;
 162         bool                            enabled_2d;
 163         int                             slot_2d;
 164         unsigned int                    irq;
 165         struct dma_slave_config         config;
 166 };
 167
 168 enum imx_dma_type {
 169         IMX1_DMA,
 170         IMX21_DMA,
 171         IMX27_DMA,
 172 };
 173
 174 struct imxdma_engine {
 175         struct device                   *dev;
 176         struct device_dma_parameters    dma_parms;
 177         struct dma_device               dma_device;
 178         void __iomem                    *base;
 179         struct clk                      *dma_ahb;
 180         struct clk                      *dma_ipg;
 181         spinlock_t                      lock;
 182         struct imx_dma_2d_config        slots_2d[IMX_DMA_2D_SLOTS];
 183         struct imxdma_channel           channel[IMX_DMA_CHANNELS];
 184         enum imx_dma_type               devtype;
 185         unsigned int                    irq;
 186         unsigned int                    irq_err;
 187
 188 };
 189
 190 struct imxdma_filter_data {
 191         struct imxdma_engine    *imxdma;
 192         int                      request;
 193 };
 194
 195 static const struct platform_device_id imx_dma_devtype[] = {
 196         {
 197                 .name = "imx1-dma",
 198                 .driver_data = IMX1_DMA,
 199         }, {
 200                 .name = "imx21-dma",
 201                 .driver_data = IMX21_DMA,
 202         }, {
 203                 .name = "imx27-dma",
 204                 .driver_data = IMX27_DMA,
 205         }, {
 206                 /* sentinel */
 207         }
 208 };
 209 MODULE_DEVICE_TABLE(platform, imx_dma_devtype);
 210
 211 static const struct of_device_id imx_dma_of_dev_id[] = {
 212         {
 213                 .compatible = "fsl,imx1-dma",
 214                 .data = &imx_dma_devtype[IMX1_DMA],
 215         }, {
 216                 .compatible = "fsl,imx21-dma",
 217                 .data = &imx_dma_devtype[IMX21_DMA],
 218         }, {
 219                 .compatible = "fsl,imx27-dma",
 220                 .data = &imx_dma_devtype[IMX27_DMA],
 221         }, {
 222                 /* sentinel */
 223         }
 224 };
 225 MODULE_DEVICE_TABLE(of, imx_dma_of_dev_id);
 226
 227 static inline int is_imx1_dma(struct imxdma_engine *imxdma)
 228 {
 229         return imxdma->devtype == IMX1_DMA;
 230 }
 231
 232 static inline int is_imx27_dma(struct imxdma_engine *imxdma)
 233 {
 234         return imxdma->devtype == IMX27_DMA;
 235 }
 236
 237 static struct imxdma_channel *to_imxdma_chan(struct dma_chan *chan)
 238 {
 239         return container_of(chan, struct imxdma_channel, chan);
 240 }
 241
 242 static inline bool imxdma_chan_is_doing_cyclic(struct imxdma_channel *imxdmac)
 243 {
 244         struct imxdma_desc *desc;
 245
 246         if (!list_empty(&imxdmac->ld_active)) {
 247                 desc = list_first_entry(&imxdmac->ld_active, struct imxdma_desc,
 248                                         node);
 249                 if (desc->type == IMXDMA_DESC_CYCLIC)
 250                         return true;
 251         }
 252         return false;
 253 }
 254
 255
 256
 257 static void imx_dmav1_writel(struct imxdma_engine *imxdma, unsigned val,
 258                              unsigned offset)
 259 {
 260         __raw_writel(val, imxdma->base + offset);
 261 }
 262
 263 static unsigned imx_dmav1_readl(struct imxdma_engine *imxdma, unsigned offset)
 264 {
 265         return __raw_readl(imxdma->base + offset);
 266 }
 267
 268 static int imxdma_hw_chain(struct imxdma_channel *imxdmac)
 269 {
 270         struct imxdma_engine *imxdma = imxdmac->imxdma;
 271
 272         if (is_imx27_dma(imxdma))
 273                 return imxdmac->hw_chaining;
 274         else
 275                 return 0;
 276 }
 277
 278 /*
 279  * imxdma_sg_next - prepare next chunk for scatter-gather DMA emulation
 280  */
 281 static inline int imxdma_sg_next(struct imxdma_desc *d)
 282 {
 283         struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
 284         struct imxdma_engine *imxdma = imxdmac->imxdma;
 285         struct scatterlist *sg = d->sg;
 286         unsigned long now;
 287
 288         now = min(d->len, sg_dma_len(sg));
 289         if (d->len != IMX_DMA_LENGTH_LOOP)
 290                 d->len -= now;
 291
 292         if (d->direction == DMA_DEV_TO_MEM)
 293                 imx_dmav1_writel(imxdma, sg->dma_address,
 294                                  DMA_DAR(imxdmac->channel));
 295         else
 296                 imx_dmav1_writel(imxdma, sg->dma_address,
 297                                  DMA_SAR(imxdmac->channel));
 298
 299         imx_dmav1_writel(imxdma, now, DMA_CNTR(imxdmac->channel));
 300
 301         dev_dbg(imxdma->dev, " %s channel: %d dst 0x%08x, src 0x%08x, "
 302                 "size 0x%08x\n", __func__, imxdmac->channel,
 303                  imx_dmav1_readl(imxdma, DMA_DAR(imxdmac->channel)),
 304                  imx_dmav1_readl(imxdma, DMA_SAR(imxdmac->channel)),
 305                  imx_dmav1_readl(imxdma, DMA_CNTR(imxdmac->channel)));
 306
 307         return now;
 308 }
 309
 310 static void imxdma_enable_hw(struct imxdma_desc *d)
 311 {
 312         struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
 313         struct imxdma_engine *imxdma = imxdmac->imxdma;
 314         int channel = imxdmac->channel;
 315         unsigned long flags;
 316
 317         dev_dbg(imxdma->dev, "%s channel %d\n", __func__, channel);
 318
 319         local_irq_save(flags);
 320
 321         imx_dmav1_writel(imxdma, 1 << channel, DMA_DISR);
 322         imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_DIMR) &
 323                          ~(1 << channel), DMA_DIMR);
 324         imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_CCR(channel)) |
 325                          CCR_CEN | CCR_ACRPT, DMA_CCR(channel));
 326
 327         if (!is_imx1_dma(imxdma) &&
 328                         d->sg && imxdma_hw_chain(imxdmac)) {
 329                 d->sg = sg_next(d->sg);
 330                 if (d->sg) {
 331                         u32 tmp;
 332                         imxdma_sg_next(d);
 333                         tmp = imx_dmav1_readl(imxdma, DMA_CCR(channel));
 334                         imx_dmav1_writel(imxdma, tmp | CCR_RPT | CCR_ACRPT,
 335                                          DMA_CCR(channel));
 336                 }
 337         }
 338
 339         local_irq_restore(flags);
 340 }
 341
 342 static void imxdma_disable_hw(struct imxdma_channel *imxdmac)
 343 {
 344         struct imxdma_engine *imxdma = imxdmac->imxdma;
 345         int channel = imxdmac->channel;
 346         unsigned long flags;
 347
 348         dev_dbg(imxdma->dev, "%s channel %d\n", __func__, channel);
 349
 350         if (imxdma_hw_chain(imxdmac))
 351                 del_timer(&imxdmac->watchdog);
 352
 353         local_irq_save(flags);
 354         imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_DIMR) |
 355                          (1 << channel), DMA_DIMR);
 356         imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_CCR(channel)) &
 357                          ~CCR_CEN, DMA_CCR(channel));
 358         imx_dmav1_writel(imxdma, 1 << channel, DMA_DISR);
 359         local_irq_restore(flags);
 360 }
 361
 362 static void imxdma_watchdog(struct timer_list *t)
 363 {
 364         struct imxdma_channel *imxdmac = from_timer(imxdmac, t, watchdog);
 365         struct imxdma_engine *imxdma = imxdmac->imxdma;
 366         int channel = imxdmac->channel;
 367
 368         imx_dmav1_writel(imxdma, 0, DMA_CCR(channel));
 369
 370         /* Tasklet watchdog error handler */
 371         tasklet_schedule(&imxdmac->dma_tasklet);
 372         dev_dbg(imxdma->dev, "channel %d: watchdog timeout!\n",
 373                 imxdmac->channel);
 374 }
 375
 376 static irqreturn_t imxdma_err_handler(int irq, void *dev_id)
 377 {
 378         struct imxdma_engine *imxdma = dev_id;
 379         unsigned int err_mask;
 380         int i, disr;
 381         int errcode;
 382
 383         disr = imx_dmav1_readl(imxdma, DMA_DISR);
 384
 385         err_mask = imx_dmav1_readl(imxdma, DMA_DBTOSR) |
 386                    imx_dmav1_readl(imxdma, DMA_DRTOSR) |
 387                    imx_dmav1_readl(imxdma, DMA_DSESR)  |
 388                    imx_dmav1_readl(imxdma, DMA_DBOSR);
 389
 390         if (!err_mask)
 391                 return IRQ_HANDLED;
 392
 393         imx_dmav1_writel(imxdma, disr & err_mask, DMA_DISR);
 394
 395         for (i = 0; i < IMX_DMA_CHANNELS; i++) {
 396                 if (!(err_mask & (1 << i)))
 397                         continue;
 398                 errcode = 0;
 399
 400                 if (imx_dmav1_readl(imxdma, DMA_DBTOSR) & (1 << i)) {
 401                         imx_dmav1_writel(imxdma, 1 << i, DMA_DBTOSR);
 402                         errcode |= IMX_DMA_ERR_BURST;
 403                 }
 404                 if (imx_dmav1_readl(imxdma, DMA_DRTOSR) & (1 << i)) {
 405                         imx_dmav1_writel(imxdma, 1 << i, DMA_DRTOSR);
 406                         errcode |= IMX_DMA_ERR_REQUEST;
 407                 }
 408                 if (imx_dmav1_readl(imxdma, DMA_DSESR) & (1 << i)) {
 409                         imx_dmav1_writel(imxdma, 1 << i, DMA_DSESR);
 410                         errcode |= IMX_DMA_ERR_TRANSFER;
 411                 }
 412                 if (imx_dmav1_readl(imxdma, DMA_DBOSR) & (1 << i)) {
 413                         imx_dmav1_writel(imxdma, 1 << i, DMA_DBOSR);
 414                         errcode |= IMX_DMA_ERR_BUFFER;
 415                 }
 416                 /* Tasklet error handler */
 417                 tasklet_schedule(&imxdma->channel[i].dma_tasklet);
 418
 419                 dev_warn(imxdma->dev,
 420                          "DMA timeout on channel %d -%s%s%s%s\n", i,
 421                          errcode & IMX_DMA_ERR_BURST ?    " burst" : "",
 422                          errcode & IMX_DMA_ERR_REQUEST ?  " request" : "",
 423                          errcode & IMX_DMA_ERR_TRANSFER ? " transfer" : "",
 424                          errcode & IMX_DMA_ERR_BUFFER ?   " buffer" : "");
 425         }
 426         return IRQ_HANDLED;
 427 }
 428
 429 static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
 430 {
 431         struct imxdma_engine *imxdma = imxdmac->imxdma;
 432         int chno = imxdmac->channel;
 433         struct imxdma_desc *desc;
 434         unsigned long flags;
 435
 436         spin_lock_irqsave(&imxdma->lock, flags);
 437         if (list_empty(&imxdmac->ld_active)) {
 438                 spin_unlock_irqrestore(&imxdma->lock, flags);
 439                 goto out;
 440         }
 441
 442         desc = list_first_entry(&imxdmac->ld_active,
 443                                 struct imxdma_desc,
 444                                 node);
 445         spin_unlock_irqrestore(&imxdma->lock, flags);
 446
 447         if (desc->sg) {
 448                 u32 tmp;
 449                 desc->sg = sg_next(desc->sg);
 450
 451                 if (desc->sg) {
 452                         imxdma_sg_next(desc);
 453
 454                         tmp = imx_dmav1_readl(imxdma, DMA_CCR(chno));
 455
 456                         if (imxdma_hw_chain(imxdmac)) {
 457                                 /* FIXME: The timeout should probably be
 458                                  * configurable
 459                                  */
 460                                 mod_timer(&imxdmac->watchdog,
 461                                         jiffies + msecs_to_jiffies(500));
 462
 463                                 tmp |= CCR_CEN | CCR_RPT | CCR_ACRPT;
 464                                 imx_dmav1_writel(imxdma, tmp, DMA_CCR(chno));
 465                         } else {
 466                                 imx_dmav1_writel(imxdma, tmp & ~CCR_CEN,
 467                                                  DMA_CCR(chno));
 468                                 tmp |= CCR_CEN;
 469                         }
 470
 471                         imx_dmav1_writel(imxdma, tmp, DMA_CCR(chno));
 472
 473                         if (imxdma_chan_is_doing_cyclic(imxdmac))
 474                                 /* Tasklet progression */
 475                                 tasklet_schedule(&imxdmac->dma_tasklet);
 476
 477                         return;
 478                 }
 479
 480                 if (imxdma_hw_chain(imxdmac)) {
 481                         del_timer(&imxdmac->watchdog);
 482                         return;
 483                 }
 484         }
 485
 486 out:
 487         imx_dmav1_writel(imxdma, 0, DMA_CCR(chno));
 488         /* Tasklet irq */
 489         tasklet_schedule(&imxdmac->dma_tasklet);
 490 }
 491
 492 static irqreturn_t dma_irq_handler(int irq, void *dev_id)
 493 {
 494         struct imxdma_engine *imxdma = dev_id;
 495         int i, disr;
 496
 497         if (!is_imx1_dma(imxdma))
 498                 imxdma_err_handler(irq, dev_id);
 499
 500         disr = imx_dmav1_readl(imxdma, DMA_DISR);
 501
 502         dev_dbg(imxdma->dev, "%s called, disr=0x%08x\n", __func__, disr);
 503
 504         imx_dmav1_writel(imxdma, disr, DMA_DISR);
 505         for (i = 0; i < IMX_DMA_CHANNELS; i++) {
 506                 if (disr & (1 << i))
 507                         dma_irq_handle_channel(&imxdma->channel[i]);
 508         }
 509
 510         return IRQ_HANDLED;
 511 }
 512
 513 static int imxdma_xfer_desc(struct imxdma_desc *d)
 514 {
 515         struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
 516         struct imxdma_engine *imxdma = imxdmac->imxdma;
 517         int slot = -1;
 518         int i;
 519
 520         /* Configure and enable */
 521         switch (d->type) {
 522         case IMXDMA_DESC_INTERLEAVED:
 523                 /* Try to get a free 2D slot */
 524                 for (i = 0; i < IMX_DMA_2D_SLOTS; i++) {
 525                         if ((imxdma->slots_2d[i].count > 0) &&
 526                         ((imxdma->slots_2d[i].xsr != d->x) ||
 527                         (imxdma->slots_2d[i].ysr != d->y) ||
 528                         (imxdma->slots_2d[i].wsr != d->w)))
 529                                 continue;
 530                         slot = i;
 531                         break;
 532                 }
 533                 if (slot < 0)
 534                         return -EBUSY;
 535
 536                 imxdma->slots_2d[slot].xsr = d->x;
 537                 imxdma->slots_2d[slot].ysr = d->y;
 538                 imxdma->slots_2d[slot].wsr = d->w;
 539                 imxdma->slots_2d[slot].count++;
 540
 541                 imxdmac->slot_2d = slot;
 542                 imxdmac->enabled_2d = true;
 543
 544                 if (slot == IMX_DMA_2D_SLOT_A) {
 545                         d->config_mem &= ~CCR_MSEL_B;
 546                         d->config_port &= ~CCR_MSEL_B;
 547                         imx_dmav1_writel(imxdma, d->x, DMA_XSRA);
 548                         imx_dmav1_writel(imxdma, d->y, DMA_YSRA);
 549                         imx_dmav1_writel(imxdma, d->w, DMA_WSRA);
 550                 } else {
 551                         d->config_mem |= CCR_MSEL_B;
 552                         d->config_port |= CCR_MSEL_B;
 553                         imx_dmav1_writel(imxdma, d->x, DMA_XSRB);
 554                         imx_dmav1_writel(imxdma, d->y, DMA_YSRB);
 555                         imx_dmav1_writel(imxdma, d->w, DMA_WSRB);
 556                 }
 557                 /*
 558                  * We fall-through here intentionally, since a 2D transfer is
 559                  * similar to MEMCPY just adding the 2D slot configuration.
 560                  */
 561         case IMXDMA_DESC_MEMCPY:
 562                 imx_dmav1_writel(imxdma, d->src, DMA_SAR(imxdmac->channel));
 563                 imx_dmav1_writel(imxdma, d->dest, DMA_DAR(imxdmac->channel));
 564                 imx_dmav1_writel(imxdma, d->config_mem | (d->config_port << 2),
 565                          DMA_CCR(imxdmac->channel));
 566
 567                 imx_dmav1_writel(imxdma, d->len, DMA_CNTR(imxdmac->channel));
 568
 569                 dev_dbg(imxdma->dev,
 570                         "%s channel: %d dest=0x%08llx src=0x%08llx dma_length=%zu\n",
 571                         __func__, imxdmac->channel,
 572                         (unsigned long long)d->dest,
 573                         (unsigned long long)d->src, d->len);
 574
 575                 break;
 576         /* Cyclic transfer is the same as slave_sg with special sg configuration. */
 577         case IMXDMA_DESC_CYCLIC:
 578         case IMXDMA_DESC_SLAVE_SG:
 579                 if (d->direction == DMA_DEV_TO_MEM) {
 580                         imx_dmav1_writel(imxdma, imxdmac->per_address,
 581                                          DMA_SAR(imxdmac->channel));
 582                         imx_dmav1_writel(imxdma, imxdmac->ccr_from_device,
 583                                          DMA_CCR(imxdmac->channel));
 584
 585                         dev_dbg(imxdma->dev,
 586                                 "%s channel: %d sg=%p sgcount=%d total length=%zu dev_addr=0x%08llx (dev2mem)\n",
 587                                 __func__, imxdmac->channel,
 588                                 d->sg, d->sgcount, d->len,
 589                                 (unsigned long long)imxdmac->per_address);
 590                 } else if (d->direction == DMA_MEM_TO_DEV) {
 591                         imx_dmav1_writel(imxdma, imxdmac->per_address,
 592                                          DMA_DAR(imxdmac->channel));
 593                         imx_dmav1_writel(imxdma, imxdmac->ccr_to_device,
 594                                          DMA_CCR(imxdmac->channel));
 595
 596                         dev_dbg(imxdma->dev,
 597                                 "%s channel: %d sg=%p sgcount=%d total length=%zu dev_addr=0x%08llx (mem2dev)\n",
 598                                 __func__, imxdmac->channel,
 599                                 d->sg, d->sgcount, d->len,
 600                                 (unsigned long long)imxdmac->per_address);
 601                 } else {
 602                         dev_err(imxdma->dev, "%s channel: %d bad dma mode\n",
 603                                 __func__, imxdmac->channel);
 604                         return -EINVAL;
 605                 }
 606
 607                 imxdma_sg_next(d);
 608
 609                 break;
 610         default:
 611                 return -EINVAL;
 612         }
 613         imxdma_enable_hw(d);
 614         return 0;
 615 }
 616
 617 static void imxdma_tasklet(unsigned long data)
 618 {
 619         struct imxdma_channel *imxdmac = (void *)data;
 620         struct imxdma_engine *imxdma = imxdmac->imxdma;
 621         struct imxdma_desc *desc, *next_desc;
 622         unsigned long flags;
 623
 624         spin_lock_irqsave(&imxdma->lock, flags);
 625
 626         if (list_empty(&imxdmac->ld_active)) {
 627                 /* Someone might have called terminate all */
 628                 spin_unlock_irqrestore(&imxdma->lock, flags);
 629                 return;
 630         }
 631         desc = list_first_entry(&imxdmac->ld_active, struct imxdma_desc, node);
 632
 633         /* If we are dealing with a cyclic descriptor, keep it on ld_active
 634          * and dont mark the descriptor as complete.
 635          * Only in non-cyclic cases it would be marked as complete
 636          */
 637         if (imxdma_chan_is_doing_cyclic(imxdmac))
 638                 goto out;
 639         else
 640                 dma_cookie_complete(&desc->desc);
 641
 642         /* Free 2D slot if it was an interleaved transfer */
 643         if (imxdmac->enabled_2d) {
 644                 imxdma->slots_2d[imxdmac->slot_2d].count--;
 645                 imxdmac->enabled_2d = false;
 646         }
 647
 648         list_move_tail(imxdmac->ld_active.next, &imxdmac->ld_free);
 649
 650         if (!list_empty(&imxdmac->ld_queue)) {
 651                 next_desc = list_first_entry(&imxdmac->ld_queue,
 652                                              struct imxdma_desc, node);
 653                 list_move_tail(imxdmac->ld_queue.next, &imxdmac->ld_active);
 654                 if (imxdma_xfer_desc(next_desc) < 0)
 655                         dev_warn(imxdma->dev, "%s: channel: %d couldn't xfer desc\n",
 656                                  __func__, imxdmac->channel);
 657         }
 658 out:
 659         spin_unlock_irqrestore(&imxdma->lock, flags);
 660
 661         dmaengine_desc_get_callback_invoke(&desc->desc, NULL);
 662 }
 663
 664 static int imxdma_terminate_all(struct dma_chan *chan)
 665 {
 666         struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
 667         struct imxdma_engine *imxdma = imxdmac->imxdma;
 668         unsigned long flags;
 669
 670         imxdma_disable_hw(imxdmac);
 671
 672         spin_lock_irqsave(&imxdma->lock, flags);
 673         list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free);
 674         list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free);
 675         spin_unlock_irqrestore(&imxdma->lock, flags);
 676         return 0;
 677 }
 678
 679 static int imxdma_config_write(struct dma_chan *chan,
 680                                struct dma_slave_config *dmaengine_cfg,
 681                                enum dma_transfer_direction direction)
 682 {
 683         struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
 684         struct imxdma_engine *imxdma = imxdmac->imxdma;
 685         unsigned int mode = 0;
 686
 687         if (direction == DMA_DEV_TO_MEM) {
 688                 imxdmac->per_address = dmaengine_cfg->src_addr;
 689                 imxdmac->watermark_level = dmaengine_cfg->src_maxburst;
 690                 imxdmac->word_size = dmaengine_cfg->src_addr_width;
 691         } else {
 692                 imxdmac->per_address = dmaengine_cfg->dst_addr;
 693                 imxdmac->watermark_level = dmaengine_cfg->dst_maxburst;
 694                 imxdmac->word_size = dmaengine_cfg->dst_addr_width;
 695         }
 696
 697         switch (imxdmac->word_size) {
 698         case DMA_SLAVE_BUSWIDTH_1_BYTE:
 699                 mode = IMX_DMA_MEMSIZE_8;
 700                 break;
 701         case DMA_SLAVE_BUSWIDTH_2_BYTES:
 702                 mode = IMX_DMA_MEMSIZE_16;
 703                 break;
 704         default:
 705         case DMA_SLAVE_BUSWIDTH_4_BYTES:
 706                 mode = IMX_DMA_MEMSIZE_32;
 707                 break;
 708         }
 709
 710         imxdmac->hw_chaining = 0;
 711
 712         imxdmac->ccr_from_device = (mode | IMX_DMA_TYPE_FIFO) |
 713                 ((IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) << 2) |
 714                 CCR_REN;
 715         imxdmac->ccr_to_device =
 716                 (IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) |
 717                 ((mode | IMX_DMA_TYPE_FIFO) << 2) | CCR_REN;
 718         imx_dmav1_writel(imxdma, imxdmac->dma_request,
 719                          DMA_RSSR(imxdmac->channel));
 720
 721         /* Set burst length */
 722         imx_dmav1_writel(imxdma, imxdmac->watermark_level *
 723                          imxdmac->word_size, DMA_BLR(imxdmac->channel));
 724
 725         return 0;
 726 }
 727
 728 static int imxdma_config(struct dma_chan *chan,
 729                          struct dma_slave_config *dmaengine_cfg)
 730 {
 731         struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
 732
 733         memcpy(&imxdmac->config, dmaengine_cfg, sizeof(*dmaengine_cfg));
 734
 735         return 0;
 736 }
 737
 738 static enum dma_status imxdma_tx_status(struct dma_chan *chan,
 739                                             dma_cookie_t cookie,
 740                                             struct dma_tx_state *txstate)
 741 {
 742         return dma_cookie_status(chan, cookie, txstate);
 743 }
 744
 745 static dma_cookie_t imxdma_tx_submit(struct dma_async_tx_descriptor *tx)
 746 {
 747         struct imxdma_channel *imxdmac = to_imxdma_chan(tx->chan);
 748         struct imxdma_engine *imxdma = imxdmac->imxdma;
 749         dma_cookie_t cookie;
 750         unsigned long flags;
 751
 752         spin_lock_irqsave(&imxdma->lock, flags);
 753         list_move_tail(imxdmac->ld_free.next, &imxdmac->ld_queue);
 754         cookie = dma_cookie_assign(tx);
 755         spin_unlock_irqrestore(&imxdma->lock, flags);
 756
 757         return cookie;
 758 }
 759
 760 static int imxdma_alloc_chan_resources(struct dma_chan *chan)
 761 {
 762         struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
 763         struct imx_dma_data *data = chan->private;
 764
 765         if (data != NULL)
 766                 imxdmac->dma_request = data->dma_request;
 767
 768         while (imxdmac->descs_allocated < IMXDMA_MAX_CHAN_DESCRIPTORS) {
 769                 struct imxdma_desc *desc;
 770
 771                 desc = kzalloc(sizeof(*desc), GFP_KERNEL);
 772                 if (!desc)
 773                         break;
 774                 memset(&desc->desc, 0, sizeof(struct dma_async_tx_descriptor));
 775                 dma_async_tx_descriptor_init(&desc->desc, chan);
 776                 desc->desc.tx_submit = imxdma_tx_submit;
 777                 /* txd.flags will be overwritten in prep funcs */
 778                 desc->desc.flags = DMA_CTRL_ACK;
 779                 desc->status = DMA_COMPLETE;
 780
 781                 list_add_tail(&desc->node, &imxdmac->ld_free);
 782                 imxdmac->descs_allocated++;
 783         }
 784
 785         if (!imxdmac->descs_allocated)
 786                 return -ENOMEM;
 787
 788         return imxdmac->descs_allocated;
 789 }
 790
 791 static void imxdma_free_chan_resources(struct dma_chan *chan)
 792 {
 793         struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
 794         struct imxdma_engine *imxdma = imxdmac->imxdma;
 795         struct imxdma_desc *desc, *_desc;
 796         unsigned long flags;
 797
 798         spin_lock_irqsave(&imxdma->lock, flags);
 799
 800         imxdma_disable_hw(imxdmac);
 801         list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free);
 802         list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free);
 803
 804         spin_unlock_irqrestore(&imxdma->lock, flags);
 805
 806         list_for_each_entry_safe(desc, _desc, &imxdmac->ld_free, node) {
 807                 kfree(desc);
 808                 imxdmac->descs_allocated--;
 809         }
 810         INIT_LIST_HEAD(&imxdmac->ld_free);
 811
 812         kfree(imxdmac->sg_list);
 813         imxdmac->sg_list = NULL;
 814 }
 815
 816 static struct dma_async_tx_descriptor *imxdma_prep_slave_sg(
 817                 struct dma_chan *chan, struct scatterlist *sgl,
 818                 unsigned int sg_len, enum dma_transfer_direction direction,
 819                 unsigned long flags, void *context)
 820 {
 821         struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
 822         struct scatterlist *sg;
 823         int i, dma_length = 0;
 824         struct imxdma_desc *desc;
 825
 826         if (list_empty(&imxdmac->ld_free) ||
 827             imxdma_chan_is_doing_cyclic(imxdmac))
 828                 return NULL;
 829
 830         desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
 831
 832         for_each_sg(sgl, sg, sg_len, i) {
 833                 dma_length += sg_dma_len(sg);
 834         }
 835
 836         switch (imxdmac->word_size) {
 837         case DMA_SLAVE_BUSWIDTH_4_BYTES:
 838                 if (sg_dma_len(sgl) & 3 || sgl->dma_address & 3)
 839                         return NULL;
 840                 break;
 841         case DMA_SLAVE_BUSWIDTH_2_BYTES:
 842                 if (sg_dma_len(sgl) & 1 || sgl->dma_address & 1)
 843                         return NULL;
 844                 break;
 845         case DMA_SLAVE_BUSWIDTH_1_BYTE:
 846                 break;
 847         default:
 848                 return NULL;
 849         }
 850
 851         desc->type = IMXDMA_DESC_SLAVE_SG;
 852         desc->sg = sgl;
 853         desc->sgcount = sg_len;
 854         desc->len = dma_length;
 855         desc->direction = direction;
 856         if (direction == DMA_DEV_TO_MEM) {
 857                 desc->src = imxdmac->per_address;
 858         } else {
 859                 desc->dest = imxdmac->per_address;
 860         }
 861         desc->desc.callback = NULL;
 862         desc->desc.callback_param = NULL;
 863
 864         return &desc->desc;
 865 }
 866
 867 static struct dma_async_tx_descriptor *imxdma_prep_dma_cyclic(
 868                 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
 869                 size_t period_len, enum dma_transfer_direction direction,
 870                 unsigned long flags)
 871 {
 872         struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
 873         struct imxdma_engine *imxdma = imxdmac->imxdma;
 874         struct imxdma_desc *desc;
 875         int i;
 876         unsigned int periods = buf_len / period_len;
 877
 878         dev_dbg(imxdma->dev, "%s channel: %d buf_len=%zu period_len=%zu\n",
 879                         __func__, imxdmac->channel, buf_len, period_len);
 880
 881         if (list_empty(&imxdmac->ld_free) ||
 882             imxdma_chan_is_doing_cyclic(imxdmac))
 883                 return NULL;
 884
 885         desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
 886
 887         kfree(imxdmac->sg_list);
 888
 889         imxdmac->sg_list = kcalloc(periods + 1,
 890                         sizeof(struct scatterlist), GFP_ATOMIC);
 891         if (!imxdmac->sg_list)
 892                 return NULL;
 893
 894         sg_init_table(imxdmac->sg_list, periods);
 895
 896         for (i = 0; i < periods; i++) {
 897                 sg_assign_page(&imxdmac->sg_list[i], NULL);
 898                 imxdmac->sg_list[i].offset = 0;
 899                 imxdmac->sg_list[i].dma_address = dma_addr;
 900                 sg_dma_len(&imxdmac->sg_list[i]) = period_len;
 901                 dma_addr += period_len;
 902         }
 903
 904         /* close the loop */
 905         sg_chain(imxdmac->sg_list, periods + 1, imxdmac->sg_list);
 906
 907         desc->type = IMXDMA_DESC_CYCLIC;
 908         desc->sg = imxdmac->sg_list;
 909         desc->sgcount = periods;
 910         desc->len = IMX_DMA_LENGTH_LOOP;
 911         desc->direction = direction;
 912         if (direction == DMA_DEV_TO_MEM) {
 913                 desc->src = imxdmac->per_address;
 914         } else {
 915                 desc->dest = imxdmac->per_address;
 916         }
 917         desc->desc.callback = NULL;
 918         desc->desc.callback_param = NULL;
 919
 920         imxdma_config_write(chan, &imxdmac->config, direction);
 921
 922         return &desc->desc;
 923 }
 924
 925 static struct dma_async_tx_descriptor *imxdma_prep_dma_memcpy(
 926         struct dma_chan *chan, dma_addr_t dest,
 927         dma_addr_t src, size_t len, unsigned long flags)
 928 {
 929         struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
 930         struct imxdma_engine *imxdma = imxdmac->imxdma;
 931         struct imxdma_desc *desc;
 932
 933         dev_dbg(imxdma->dev, "%s channel: %d src=0x%llx dst=0x%llx len=%zu\n",
 934                 __func__, imxdmac->channel, (unsigned long long)src,
 935                 (unsigned long long)dest, len);
 936
 937         if (list_empty(&imxdmac->ld_free) ||
 938             imxdma_chan_is_doing_cyclic(imxdmac))
 939                 return NULL;
 940
 941         desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
 942
 943         desc->type = IMXDMA_DESC_MEMCPY;
 944         desc->src = src;
 945         desc->dest = dest;
 946         desc->len = len;
 947         desc->direction = DMA_MEM_TO_MEM;
 948         desc->config_port = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR;
 949         desc->config_mem = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR;
 950         desc->desc.callback = NULL;
 951         desc->desc.callback_param = NULL;
 952
 953         return &desc->desc;
 954 }
 955
 956 static struct dma_async_tx_descriptor *imxdma_prep_dma_interleaved(
 957         struct dma_chan *chan, struct dma_interleaved_template *xt,
 958         unsigned long flags)
 959 {
 960         struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
 961         struct imxdma_engine *imxdma = imxdmac->imxdma;
 962         struct imxdma_desc *desc;
 963
 964         dev_dbg(imxdma->dev, "%s channel: %d src_start=0x%llx dst_start=0x%llx\n"
 965                 "   src_sgl=%s dst_sgl=%s numf=%zu frame_size=%zu\n", __func__,
 966                 imxdmac->channel, (unsigned long long)xt->src_start,
 967                 (unsigned long long) xt->dst_start,
 968                 xt->src_sgl ? "true" : "false", xt->dst_sgl ? "true" : "false",
 969                 xt->numf, xt->frame_size);
 970
 971         if (list_empty(&imxdmac->ld_free) ||
 972             imxdma_chan_is_doing_cyclic(imxdmac))
 973                 return NULL;
 974
 975         if (xt->frame_size != 1 || xt->numf <= 0 || xt->dir != DMA_MEM_TO_MEM)
 976                 return NULL;
 977
 978         desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
 979
 980         desc->type = IMXDMA_DESC_INTERLEAVED;
 981         desc->src = xt->src_start;
 982         desc->dest = xt->dst_start;
 983         desc->x = xt->sgl[0].size;
 984         desc->y = xt->numf;
 985         desc->w = xt->sgl[0].icg + desc->x;
 986         desc->len = desc->x * desc->y;
 987         desc->direction = DMA_MEM_TO_MEM;
 988         desc->config_port = IMX_DMA_MEMSIZE_32;
 989         desc->config_mem = IMX_DMA_MEMSIZE_32;
 990         if (xt->src_sgl)
 991                 desc->config_mem |= IMX_DMA_TYPE_2D;
 992         if (xt->dst_sgl)
 993                 desc->config_port |= IMX_DMA_TYPE_2D;
 994         desc->desc.callback = NULL;
 995         desc->desc.callback_param = NULL;
 996
 997         return &desc->desc;
 998 }
 999
1000 static void imxdma_issue_pending(struct dma_chan *chan)
1001 {
1002         struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
1003         struct imxdma_engine *imxdma = imxdmac->imxdma;
1004         struct imxdma_desc *desc;
1005         unsigned long flags;
1006
1007         spin_lock_irqsave(&imxdma->lock, flags);
1008         if (list_empty(&imxdmac->ld_active) &&
1009             !list_empty(&imxdmac->ld_queue)) {
1010                 desc = list_first_entry(&imxdmac->ld_queue,
1011                                         struct imxdma_desc, node);
1012
1013                 if (imxdma_xfer_desc(desc) < 0) {
1014                         dev_warn(imxdma->dev,
1015                                  "%s: channel: %d couldn't issue DMA xfer\n",
1016                                  __func__, imxdmac->channel);
1017                 } else {
1018                         list_move_tail(imxdmac->ld_queue.next,
1019                                        &imxdmac->ld_active);
1020                 }
1021         }
1022         spin_unlock_irqrestore(&imxdma->lock, flags);
1023 }
1024
1025 static bool imxdma_filter_fn(struct dma_chan *chan, void *param)
1026 {
1027         struct imxdma_filter_data *fdata = param;
1028         struct imxdma_channel *imxdma_chan = to_imxdma_chan(chan);
1029
1030         if (chan->device->dev != fdata->imxdma->dev)
1031                 return false;
1032
1033         imxdma_chan->dma_request = fdata->request;
1034         chan->private = NULL;
1035
1036         return true;
1037 }
1038
1039 static struct dma_chan *imxdma_xlate(struct of_phandle_args *dma_spec,
1040                                                 struct of_dma *ofdma)
1041 {
1042         int count = dma_spec->args_count;
1043         struct imxdma_engine *imxdma = ofdma->of_dma_data;
1044         struct imxdma_filter_data fdata = {
1045                 .imxdma = imxdma,
1046         };
1047
1048         if (count != 1)
1049                 return NULL;
1050
1051         fdata.request = dma_spec->args[0];
1052
1053         return dma_request_channel(imxdma->dma_device.cap_mask,
1054                                         imxdma_filter_fn, &fdata);
1055 }
1056
1057 static int __init imxdma_probe(struct platform_device *pdev)
1058 {
1059         struct imxdma_engine *imxdma;
1060         struct resource *res;
1061         const struct of_device_id *of_id;
1062         int ret, i;
1063         int irq, irq_err;
1064
1065         of_id = of_match_device(imx_dma_of_dev_id, &pdev->dev);
1066         if (of_id)
1067                 pdev->id_entry = of_id->data;
1068
1069         imxdma = devm_kzalloc(&pdev->dev, sizeof(*imxdma), GFP_KERNEL);
1070         if (!imxdma)
1071                 return -ENOMEM;
1072
1073         imxdma->dev = &pdev->dev;
1074         imxdma->devtype = pdev->id_entry->driver_data;
1075
1076         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1077         imxdma->base = devm_ioremap_resource(&pdev->dev, res);
1078         if (IS_ERR(imxdma->base))
1079                 return PTR_ERR(imxdma->base);
1080
1081         irq = platform_get_irq(pdev, 0);
1082         if (irq < 0)
1083                 return irq;
1084
1085         imxdma->dma_ipg = devm_clk_get(&pdev->dev, "ipg");
1086         if (IS_ERR(imxdma->dma_ipg))
1087                 return PTR_ERR(imxdma->dma_ipg);
1088
1089         imxdma->dma_ahb = devm_clk_get(&pdev->dev, "ahb");
1090         if (IS_ERR(imxdma->dma_ahb))
1091                 return PTR_ERR(imxdma->dma_ahb);
1092
1093         ret = clk_prepare_enable(imxdma->dma_ipg);
1094         if (ret)
1095                 return ret;
1096         ret = clk_prepare_enable(imxdma->dma_ahb);
1097         if (ret)
1098                 goto disable_dma_ipg_clk;
1099
1100         /* reset DMA module */
1101         imx_dmav1_writel(imxdma, DCR_DRST, DMA_DCR);
1102
1103         if (is_imx1_dma(imxdma)) {
1104                 ret = devm_request_irq(&pdev->dev, irq,
1105                                        dma_irq_handler, 0, "DMA", imxdma);
1106                 if (ret) {
1107                         dev_warn(imxdma->dev, "Can't register IRQ for DMA\n");
1108                         goto disable_dma_ahb_clk;
1109                 }
1110                 imxdma->irq = irq;
1111
1112                 irq_err = platform_get_irq(pdev, 1);
1113                 if (irq_err < 0) {
1114                         ret = irq_err;
1115                         goto disable_dma_ahb_clk;
1116                 }
1117
1118                 ret = devm_request_irq(&pdev->dev, irq_err,
1119                                        imxdma_err_handler, 0, "DMA", imxdma);
1120                 if (ret) {
1121                         dev_warn(imxdma->dev, "Can't register ERRIRQ for DMA\n");
1122                         goto disable_dma_ahb_clk;
1123                 }
1124                 imxdma->irq_err = irq_err;
1125         }
1126
1127         /* enable DMA module */
1128         imx_dmav1_writel(imxdma, DCR_DEN, DMA_DCR);
1129
1130         /* clear all interrupts */
1131         imx_dmav1_writel(imxdma, (1 << IMX_DMA_CHANNELS) - 1, DMA_DISR);
1132
1133         /* disable interrupts */
1134         imx_dmav1_writel(imxdma, (1 << IMX_DMA_CHANNELS) - 1, DMA_DIMR);
1135
1136         INIT_LIST_HEAD(&imxdma->dma_device.channels);
1137
1138         dma_cap_set(DMA_SLAVE, imxdma->dma_device.cap_mask);
1139         dma_cap_set(DMA_CYCLIC, imxdma->dma_device.cap_mask);
1140         dma_cap_set(DMA_MEMCPY, imxdma->dma_device.cap_mask);
1141         dma_cap_set(DMA_INTERLEAVE, imxdma->dma_device.cap_mask);
1142
1143         /* Initialize 2D global parameters */
1144         for (i = 0; i < IMX_DMA_2D_SLOTS; i++)
1145                 imxdma->slots_2d[i].count = 0;
1146
1147         spin_lock_init(&imxdma->lock);
1148
1149         /* Initialize channel parameters */
1150         for (i = 0; i < IMX_DMA_CHANNELS; i++) {
1151                 struct imxdma_channel *imxdmac = &imxdma->channel[i];
1152
1153                 if (!is_imx1_dma(imxdma)) {
1154                         ret = devm_request_irq(&pdev->dev, irq + i,
1155                                         dma_irq_handler, 0, "DMA", imxdma);
1156                         if (ret) {
1157                                 dev_warn(imxdma->dev, "Can't register IRQ %d "
1158                                          "for DMA channel %d\n",
1159                                          irq + i, i);
1160                                 goto disable_dma_ahb_clk;
1161                         }
1162
1163                         imxdmac->irq = irq + i;
1164                         timer_setup(&imxdmac->watchdog, imxdma_watchdog, 0);
1165                 }
1166
1167                 imxdmac->imxdma = imxdma;
1168
1169                 INIT_LIST_HEAD(&imxdmac->ld_queue);
1170                 INIT_LIST_HEAD(&imxdmac->ld_free);
1171                 INIT_LIST_HEAD(&imxdmac->ld_active);
1172
1173                 tasklet_init(&imxdmac->dma_tasklet, imxdma_tasklet,
1174                              (unsigned long)imxdmac);
1175                 imxdmac->chan.device = &imxdma->dma_device;
1176                 dma_cookie_init(&imxdmac->chan);
1177                 imxdmac->channel = i;
1178
1179                 /* Add the channel to the DMAC list */
1180                 list_add_tail(&imxdmac->chan.device_node,
1181                               &imxdma->dma_device.channels);
1182         }
1183
1184         imxdma->dma_device.dev = &pdev->dev;
1185
1186         imxdma->dma_device.device_alloc_chan_resources = imxdma_alloc_chan_resources;
1187         imxdma->dma_device.device_free_chan_resources = imxdma_free_chan_resources;
1188         imxdma->dma_device.device_tx_status = imxdma_tx_status;
1189         imxdma->dma_device.device_prep_slave_sg = imxdma_prep_slave_sg;
1190         imxdma->dma_device.device_prep_dma_cyclic = imxdma_prep_dma_cyclic;
1191         imxdma->dma_device.device_prep_dma_memcpy = imxdma_prep_dma_memcpy;
1192         imxdma->dma_device.device_prep_interleaved_dma = imxdma_prep_dma_interleaved;
1193         imxdma->dma_device.device_config = imxdma_config;
1194         imxdma->dma_device.device_terminate_all = imxdma_terminate_all;
1195         imxdma->dma_device.device_issue_pending = imxdma_issue_pending;
1196
1197         platform_set_drvdata(pdev, imxdma);
1198
1199         imxdma->dma_device.copy_align = DMAENGINE_ALIGN_4_BYTES;
1200         imxdma->dma_device.dev->dma_parms = &imxdma->dma_parms;
1201         dma_set_max_seg_size(imxdma->dma_device.dev, 0xffffff);
1202
1203         ret = dma_async_device_register(&imxdma->dma_device);
1204         if (ret) {
1205                 dev_err(&pdev->dev, "unable to register\n");
1206                 goto disable_dma_ahb_clk;
1207         }
1208
1209         if (pdev->dev.of_node) {
1210                 ret = of_dma_controller_register(pdev->dev.of_node,
1211                                 imxdma_xlate, imxdma);
1212                 if (ret) {
1213                         dev_err(&pdev->dev, "unable to register of_dma_controller\n");
1214                         goto err_of_dma_controller;
1215                 }
1216         }
1217
1218         return 0;
1219
1220 err_of_dma_controller:
1221         dma_async_device_unregister(&imxdma->dma_device);
1222 disable_dma_ahb_clk:
1223         clk_disable_unprepare(imxdma->dma_ahb);
1224 disable_dma_ipg_clk:
1225         clk_disable_unprepare(imxdma->dma_ipg);
1226         return ret;
1227 }
1228
1229 static void imxdma_free_irq(struct platform_device *pdev, struct imxdma_engine *imxdma)
1230 {
1231         int i;
1232
1233         if (is_imx1_dma(imxdma)) {
1234                 disable_irq(imxdma->irq);
1235                 disable_irq(imxdma->irq_err);
1236         }
1237
1238         for (i = 0; i < IMX_DMA_CHANNELS; i++) {
1239                 struct imxdma_channel *imxdmac = &imxdma->channel[i];
1240
1241                 if (!is_imx1_dma(imxdma))
1242                         disable_irq(imxdmac->irq);
1243
1244                 tasklet_kill(&imxdmac->dma_tasklet);
1245         }
1246 }
1247
1248 static int imxdma_remove(struct platform_device *pdev)
1249 {
1250         struct imxdma_engine *imxdma = platform_get_drvdata(pdev);
1251
1252         imxdma_free_irq(pdev, imxdma);
1253
1254         dma_async_device_unregister(&imxdma->dma_device);
1255
1256         if (pdev->dev.of_node)
1257                 of_dma_controller_free(pdev->dev.of_node);
1258
1259         clk_disable_unprepare(imxdma->dma_ipg);
1260         clk_disable_unprepare(imxdma->dma_ahb);
1261
1262         return 0;
1263 }
1264
1265 static struct platform_driver imxdma_driver = {
1266         .driver         = {
1267                 .name   = "imx-dma",
1268                 .of_match_table = imx_dma_of_dev_id,
1269         },
1270         .id_table       = imx_dma_devtype,
1271         .remove         = imxdma_remove,
1272 };
1273
1274 static int __init imxdma_module_init(void)
1275 {
1276         return platform_driver_probe(&imxdma_driver, imxdma_probe);
1277 }
1278 subsys_initcall(imxdma_module_init);
1279
1280 MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>");
1281 MODULE_DESCRIPTION("i.MX dma driver");
1282 MODULE_LICENSE("GPL");