drivers/dma/stm32-dma.c

   1 /*
   2  * Driver for STM32 DMA controller
   3  *
   4  * Inspired by dma-jz4740.c and tegra20-apb-dma.c
   5  *
   6  * Copyright (C) M'boumba Cedric Madianga 2015
   7  * Author: M'boumba Cedric Madianga <cedric.madianga@gmail.com>
   8  *         Pierre-Yves Mordret <pierre-yves.mordret@st.com>
   9  *
  10  * License terms:  GNU General Public License (GPL), version 2
  11  */
  12
  13 #include <linux/clk.h>
  14 #include <linux/delay.h>
  15 #include <linux/dmaengine.h>
  16 #include <linux/dma-mapping.h>
  17 #include <linux/err.h>
  18 #include <linux/init.h>
  19 #include <linux/jiffies.h>
  20 #include <linux/list.h>
  21 #include <linux/module.h>
  22 #include <linux/of.h>
  23 #include <linux/of_device.h>
  24 #include <linux/of_dma.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/pm_runtime.h>
  27 #include <linux/reset.h>
  28 #include <linux/sched.h>
  29 #include <linux/slab.h>
  30
  31 #include "virt-dma.h"
  32
  33 #define STM32_DMA_LISR                  0x0000 /* DMA Low Int Status Reg */
  34 #define STM32_DMA_HISR                  0x0004 /* DMA High Int Status Reg */
  35 #define STM32_DMA_LIFCR                 0x0008 /* DMA Low Int Flag Clear Reg */
  36 #define STM32_DMA_HIFCR                 0x000c /* DMA High Int Flag Clear Reg */
  37 #define STM32_DMA_TCI                   BIT(5) /* Transfer Complete Interrupt */
  38 #define STM32_DMA_HTI                   BIT(4) /* Half Transfer Interrupt */
  39 #define STM32_DMA_TEI                   BIT(3) /* Transfer Error Interrupt */
  40 #define STM32_DMA_DMEI                  BIT(2) /* Direct Mode Error Interrupt */
  41 #define STM32_DMA_FEI                   BIT(0) /* FIFO Error Interrupt */
  42 #define STM32_DMA_MASKI                 (STM32_DMA_TCI \
  43                                          | STM32_DMA_TEI \
  44                                          | STM32_DMA_DMEI \
  45                                          | STM32_DMA_FEI)
  46
  47 /* DMA Stream x Configuration Register */
  48 #define STM32_DMA_SCR(x)                (0x0010 + 0x18 * (x)) /* x = 0..7 */
  49 #define STM32_DMA_SCR_REQ(n)            ((n & 0x7) << 25)
  50 #define STM32_DMA_SCR_MBURST_MASK       GENMASK(24, 23)
  51 #define STM32_DMA_SCR_MBURST(n)         ((n & 0x3) << 23)
  52 #define STM32_DMA_SCR_PBURST_MASK       GENMASK(22, 21)
  53 #define STM32_DMA_SCR_PBURST(n)         ((n & 0x3) << 21)
  54 #define STM32_DMA_SCR_PL_MASK           GENMASK(17, 16)
  55 #define STM32_DMA_SCR_PL(n)             ((n & 0x3) << 16)
  56 #define STM32_DMA_SCR_MSIZE_MASK        GENMASK(14, 13)
  57 #define STM32_DMA_SCR_MSIZE(n)          ((n & 0x3) << 13)
  58 #define STM32_DMA_SCR_PSIZE_MASK        GENMASK(12, 11)
  59 #define STM32_DMA_SCR_PSIZE(n)          ((n & 0x3) << 11)
  60 #define STM32_DMA_SCR_PSIZE_GET(n)      ((n & STM32_DMA_SCR_PSIZE_MASK) >> 11)
  61 #define STM32_DMA_SCR_DIR_MASK          GENMASK(7, 6)
  62 #define STM32_DMA_SCR_DIR(n)            ((n & 0x3) << 6)
  63 #define STM32_DMA_SCR_CT                BIT(19) /* Target in double buffer */
  64 #define STM32_DMA_SCR_DBM               BIT(18) /* Double Buffer Mode */
  65 #define STM32_DMA_SCR_PINCOS            BIT(15) /* Peripheral inc offset size */
  66 #define STM32_DMA_SCR_MINC              BIT(10) /* Memory increment mode */
  67 #define STM32_DMA_SCR_PINC              BIT(9) /* Peripheral increment mode */
  68 #define STM32_DMA_SCR_CIRC              BIT(8) /* Circular mode */
  69 #define STM32_DMA_SCR_PFCTRL            BIT(5) /* Peripheral Flow Controller */
  70 #define STM32_DMA_SCR_TCIE              BIT(4) /* Transfer Complete Int Enable
  71                                                 */
  72 #define STM32_DMA_SCR_TEIE              BIT(2) /* Transfer Error Int Enable */
  73 #define STM32_DMA_SCR_DMEIE             BIT(1) /* Direct Mode Err Int Enable */
  74 #define STM32_DMA_SCR_EN                BIT(0) /* Stream Enable */
  75 #define STM32_DMA_SCR_CFG_MASK          (STM32_DMA_SCR_PINC \
  76                                         | STM32_DMA_SCR_MINC \
  77                                         | STM32_DMA_SCR_PINCOS \
  78                                         | STM32_DMA_SCR_PL_MASK)
  79 #define STM32_DMA_SCR_IRQ_MASK          (STM32_DMA_SCR_TCIE \
  80                                         | STM32_DMA_SCR_TEIE \
  81                                         | STM32_DMA_SCR_DMEIE)
  82
  83 /* DMA Stream x number of data register */
  84 #define STM32_DMA_SNDTR(x)              (0x0014 + 0x18 * (x))
  85
  86 /* DMA stream peripheral address register */
  87 #define STM32_DMA_SPAR(x)               (0x0018 + 0x18 * (x))
  88
  89 /* DMA stream x memory 0 address register */
  90 #define STM32_DMA_SM0AR(x)              (0x001c + 0x18 * (x))
  91
  92 /* DMA stream x memory 1 address register */
  93 #define STM32_DMA_SM1AR(x)              (0x0020 + 0x18 * (x))
  94
  95 /* DMA stream x FIFO control register */
  96 #define STM32_DMA_SFCR(x)               (0x0024 + 0x18 * (x))
  97 #define STM32_DMA_SFCR_FTH_MASK         GENMASK(1, 0)
  98 #define STM32_DMA_SFCR_FTH(n)           (n & STM32_DMA_SFCR_FTH_MASK)
  99 #define STM32_DMA_SFCR_FEIE             BIT(7) /* FIFO error interrupt enable */
 100 #define STM32_DMA_SFCR_DMDIS            BIT(2) /* Direct mode disable */
 101 #define STM32_DMA_SFCR_MASK             (STM32_DMA_SFCR_FEIE \
 102                                         | STM32_DMA_SFCR_DMDIS)
 103
 104 /* DMA direction */
 105 #define STM32_DMA_DEV_TO_MEM            0x00
 106 #define STM32_DMA_MEM_TO_DEV            0x01
 107 #define STM32_DMA_MEM_TO_MEM            0x02
 108
 109 /* DMA priority level */
 110 #define STM32_DMA_PRIORITY_LOW          0x00
 111 #define STM32_DMA_PRIORITY_MEDIUM       0x01
 112 #define STM32_DMA_PRIORITY_HIGH         0x02
 113 #define STM32_DMA_PRIORITY_VERY_HIGH    0x03
 114
 115 /* DMA FIFO threshold selection */
 116 #define STM32_DMA_FIFO_THRESHOLD_1QUARTERFULL           0x00
 117 #define STM32_DMA_FIFO_THRESHOLD_HALFFULL               0x01
 118 #define STM32_DMA_FIFO_THRESHOLD_3QUARTERSFULL          0x02
 119 #define STM32_DMA_FIFO_THRESHOLD_FULL                   0x03
 120
 121 #define STM32_DMA_MAX_DATA_ITEMS        0xffff
 122 /*
 123  * Valid transfer starts from @0 to @0xFFFE leading to unaligned scatter
 124  * gather at boundary. Thus it's safer to round down this value on FIFO
 125  * size (16 Bytes)
 126  */
 127 #define STM32_DMA_ALIGNED_MAX_DATA_ITEMS        \
 128         ALIGN_DOWN(STM32_DMA_MAX_DATA_ITEMS, 16)
 129 #define STM32_DMA_MAX_CHANNELS          0x08
 130 #define STM32_DMA_MAX_REQUEST_ID        0x08
 131 #define STM32_DMA_MAX_DATA_PARAM        0x03
 132 #define STM32_DMA_FIFO_SIZE             16      /* FIFO is 16 bytes */
 133 #define STM32_DMA_MIN_BURST             4
 134 #define STM32_DMA_MAX_BURST             16
 135
 136 /* DMA Features */
 137 #define STM32_DMA_THRESHOLD_FTR_MASK    GENMASK(1, 0)
 138 #define STM32_DMA_THRESHOLD_FTR_GET(n)  ((n) & STM32_DMA_THRESHOLD_FTR_MASK)
 139
 140 enum stm32_dma_width {
 141         STM32_DMA_BYTE,
 142         STM32_DMA_HALF_WORD,
 143         STM32_DMA_WORD,
 144 };
 145
 146 enum stm32_dma_burst_size {
 147         STM32_DMA_BURST_SINGLE,
 148         STM32_DMA_BURST_INCR4,
 149         STM32_DMA_BURST_INCR8,
 150         STM32_DMA_BURST_INCR16,
 151 };
 152
 153 /**
 154  * struct stm32_dma_cfg - STM32 DMA custom configuration
 155  * @channel_id: channel ID
 156  * @request_line: DMA request
 157  * @stream_config: 32bit mask specifying the DMA channel configuration
 158  * @features: 32bit mask specifying the DMA Feature list
 159  */
 160 struct stm32_dma_cfg {
 161         u32 channel_id;
 162         u32 request_line;
 163         u32 stream_config;
 164         u32 features;
 165 };
 166
 167 struct stm32_dma_chan_reg {
 168         u32 dma_lisr;
 169         u32 dma_hisr;
 170         u32 dma_lifcr;
 171         u32 dma_hifcr;
 172         u32 dma_scr;
 173         u32 dma_sndtr;
 174         u32 dma_spar;
 175         u32 dma_sm0ar;
 176         u32 dma_sm1ar;
 177         u32 dma_sfcr;
 178 };
 179
 180 struct stm32_dma_sg_req {
 181         u32 len;
 182         struct stm32_dma_chan_reg chan_reg;
 183 };
 184
 185 struct stm32_dma_desc {
 186         struct virt_dma_desc vdesc;
 187         bool cyclic;
 188         u32 num_sgs;
 189         struct stm32_dma_sg_req sg_req[];
 190 };
 191
 192 struct stm32_dma_chan {
 193         struct virt_dma_chan vchan;
 194         bool config_init;
 195         bool busy;
 196         u32 id;
 197         u32 irq;
 198         struct stm32_dma_desc *desc;
 199         u32 next_sg;
 200         struct dma_slave_config dma_sconfig;
 201         struct stm32_dma_chan_reg chan_reg;
 202         u32 threshold;
 203         u32 mem_burst;
 204         u32 mem_width;
 205 };
 206
 207 struct stm32_dma_device {
 208         struct dma_device ddev;
 209         void __iomem *base;
 210         struct clk *clk;
 211         struct reset_control *rst;
 212         bool mem2mem;
 213         struct stm32_dma_chan chan[STM32_DMA_MAX_CHANNELS];
 214 };
 215
 216 static struct stm32_dma_device *stm32_dma_get_dev(struct stm32_dma_chan *chan)
 217 {
 218         return container_of(chan->vchan.chan.device, struct stm32_dma_device,
 219                             ddev);
 220 }
 221
 222 static struct stm32_dma_chan *to_stm32_dma_chan(struct dma_chan *c)
 223 {
 224         return container_of(c, struct stm32_dma_chan, vchan.chan);
 225 }
 226
 227 static struct stm32_dma_desc *to_stm32_dma_desc(struct virt_dma_desc *vdesc)
 228 {
 229         return container_of(vdesc, struct stm32_dma_desc, vdesc);
 230 }
 231
 232 static struct device *chan2dev(struct stm32_dma_chan *chan)
 233 {
 234         return &chan->vchan.chan.dev->device;
 235 }
 236
 237 static u32 stm32_dma_read(struct stm32_dma_device *dmadev, u32 reg)
 238 {
 239         return readl_relaxed(dmadev->base + reg);
 240 }
 241
 242 static void stm32_dma_write(struct stm32_dma_device *dmadev, u32 reg, u32 val)
 243 {
 244         writel_relaxed(val, dmadev->base + reg);
 245 }
 246
 247 static struct stm32_dma_desc *stm32_dma_alloc_desc(u32 num_sgs)
 248 {
 249         return kzalloc(sizeof(struct stm32_dma_desc) +
 250                        sizeof(struct stm32_dma_sg_req) * num_sgs, GFP_NOWAIT);
 251 }
 252
 253 static int stm32_dma_get_width(struct stm32_dma_chan *chan,
 254                                enum dma_slave_buswidth width)
 255 {
 256         switch (width) {
 257         case DMA_SLAVE_BUSWIDTH_1_BYTE:
 258                 return STM32_DMA_BYTE;
 259         case DMA_SLAVE_BUSWIDTH_2_BYTES:
 260                 return STM32_DMA_HALF_WORD;
 261         case DMA_SLAVE_BUSWIDTH_4_BYTES:
 262                 return STM32_DMA_WORD;
 263         default:
 264                 dev_err(chan2dev(chan), "Dma bus width not supported\n");
 265                 return -EINVAL;
 266         }
 267 }
 268
 269 static enum dma_slave_buswidth stm32_dma_get_max_width(u32 buf_len,
 270                                                        u32 threshold)
 271 {
 272         enum dma_slave_buswidth max_width;
 273
 274         if (threshold == STM32_DMA_FIFO_THRESHOLD_FULL)
 275                 max_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 276         else
 277                 max_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
 278
 279         while ((buf_len < max_width  || buf_len % max_width) &&
 280                max_width > DMA_SLAVE_BUSWIDTH_1_BYTE)
 281                 max_width = max_width >> 1;
 282
 283         return max_width;
 284 }
 285
 286 static bool stm32_dma_fifo_threshold_is_allowed(u32 burst, u32 threshold,
 287                                                 enum dma_slave_buswidth width)
 288 {
 289         u32 remaining;
 290
 291         if (width != DMA_SLAVE_BUSWIDTH_UNDEFINED) {
 292                 if (burst != 0) {
 293                         /*
 294                          * If number of beats fit in several whole bursts
 295                          * this configuration is allowed.
 296                          */
 297                         remaining = ((STM32_DMA_FIFO_SIZE / width) *
 298                                      (threshold + 1) / 4) % burst;
 299
 300                         if (remaining == 0)
 301                                 return true;
 302                 } else {
 303                         return true;
 304                 }
 305         }
 306
 307         return false;
 308 }
 309
 310 static bool stm32_dma_is_burst_possible(u32 buf_len, u32 threshold)
 311 {
 312         /*
 313          * Buffer or period length has to be aligned on FIFO depth.
 314          * Otherwise bytes may be stuck within FIFO at buffer or period
 315          * length.
 316          */
 317         return ((buf_len % ((threshold + 1) * 4)) == 0);
 318 }
 319
 320 static u32 stm32_dma_get_best_burst(u32 buf_len, u32 max_burst, u32 threshold,
 321                                     enum dma_slave_buswidth width)
 322 {
 323         u32 best_burst = max_burst;
 324
 325         if (best_burst == 1 || !stm32_dma_is_burst_possible(buf_len, threshold))
 326                 return 0;
 327
 328         while ((buf_len < best_burst * width && best_burst > 1) ||
 329                !stm32_dma_fifo_threshold_is_allowed(best_burst, threshold,
 330                                                     width)) {
 331                 if (best_burst > STM32_DMA_MIN_BURST)
 332                         best_burst = best_burst >> 1;
 333                 else
 334                         best_burst = 0;
 335         }
 336
 337         return best_burst;
 338 }
 339
 340 static int stm32_dma_get_burst(struct stm32_dma_chan *chan, u32 maxburst)
 341 {
 342         switch (maxburst) {
 343         case 0:
 344         case 1:
 345                 return STM32_DMA_BURST_SINGLE;
 346         case 4:
 347                 return STM32_DMA_BURST_INCR4;
 348         case 8:
 349                 return STM32_DMA_BURST_INCR8;
 350         case 16:
 351                 return STM32_DMA_BURST_INCR16;
 352         default:
 353                 dev_err(chan2dev(chan), "Dma burst size not supported\n");
 354                 return -EINVAL;
 355         }
 356 }
 357
 358 static void stm32_dma_set_fifo_config(struct stm32_dma_chan *chan,
 359                                       u32 src_burst, u32 dst_burst)
 360 {
 361         chan->chan_reg.dma_sfcr &= ~STM32_DMA_SFCR_MASK;
 362         chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_DMEIE;
 363
 364         if (!src_burst && !dst_burst) {
 365                 /* Using direct mode */
 366                 chan->chan_reg.dma_scr |= STM32_DMA_SCR_DMEIE;
 367         } else {
 368                 /* Using FIFO mode */
 369                 chan->chan_reg.dma_sfcr |= STM32_DMA_SFCR_MASK;
 370         }
 371 }
 372
 373 static int stm32_dma_slave_config(struct dma_chan *c,
 374                                   struct dma_slave_config *config)
 375 {
 376         struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
 377
 378         memcpy(&chan->dma_sconfig, config, sizeof(*config));
 379
 380         chan->config_init = true;
 381
 382         return 0;
 383 }
 384
 385 static u32 stm32_dma_irq_status(struct stm32_dma_chan *chan)
 386 {
 387         struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
 388         u32 flags, dma_isr;
 389
 390         /*
 391          * Read "flags" from DMA_xISR register corresponding to the selected
 392          * DMA channel at the correct bit offset inside that register.
 393          *
 394          * If (ch % 4) is 2 or 3, left shift the mask by 16 bits.
 395          * If (ch % 4) is 1 or 3, additionally left shift the mask by 6 bits.
 396          */
 397
 398         if (chan->id & 4)
 399                 dma_isr = stm32_dma_read(dmadev, STM32_DMA_HISR);
 400         else
 401                 dma_isr = stm32_dma_read(dmadev, STM32_DMA_LISR);
 402
 403         flags = dma_isr >> (((chan->id & 2) << 3) | ((chan->id & 1) * 6));
 404
 405         return flags & STM32_DMA_MASKI;
 406 }
 407
 408 static void stm32_dma_irq_clear(struct stm32_dma_chan *chan, u32 flags)
 409 {
 410         struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
 411         u32 dma_ifcr;
 412
 413         /*
 414          * Write "flags" to the DMA_xIFCR register corresponding to the selected
 415          * DMA channel at the correct bit offset inside that register.
 416          *
 417          * If (ch % 4) is 2 or 3, left shift the mask by 16 bits.
 418          * If (ch % 4) is 1 or 3, additionally left shift the mask by 6 bits.
 419          */
 420         flags &= STM32_DMA_MASKI;
 421         dma_ifcr = flags << (((chan->id & 2) << 3) | ((chan->id & 1) * 6));
 422
 423         if (chan->id & 4)
 424                 stm32_dma_write(dmadev, STM32_DMA_HIFCR, dma_ifcr);
 425         else
 426                 stm32_dma_write(dmadev, STM32_DMA_LIFCR, dma_ifcr);
 427 }
 428
 429 static int stm32_dma_disable_chan(struct stm32_dma_chan *chan)
 430 {
 431         struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
 432         unsigned long timeout = jiffies + msecs_to_jiffies(5000);
 433         u32 dma_scr, id;
 434
 435         id = chan->id;
 436         dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(id));
 437
 438         if (dma_scr & STM32_DMA_SCR_EN) {
 439                 dma_scr &= ~STM32_DMA_SCR_EN;
 440                 stm32_dma_write(dmadev, STM32_DMA_SCR(id), dma_scr);
 441
 442                 do {
 443                         dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(id));
 444                         dma_scr &= STM32_DMA_SCR_EN;
 445                         if (!dma_scr)
 446                                 break;
 447
 448                         if (time_after_eq(jiffies, timeout)) {
 449                                 dev_err(chan2dev(chan), "%s: timeout!\n",
 450                                         __func__);
 451                                 return -EBUSY;
 452                         }
 453                         cond_resched();
 454                 } while (1);
 455         }
 456
 457         return 0;
 458 }
 459
 460 static void stm32_dma_stop(struct stm32_dma_chan *chan)
 461 {
 462         struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
 463         u32 dma_scr, dma_sfcr, status;
 464         int ret;
 465
 466         /* Disable interrupts */
 467         dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id));
 468         dma_scr &= ~STM32_DMA_SCR_IRQ_MASK;
 469         stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), dma_scr);
 470         dma_sfcr = stm32_dma_read(dmadev, STM32_DMA_SFCR(chan->id));
 471         dma_sfcr &= ~STM32_DMA_SFCR_FEIE;
 472         stm32_dma_write(dmadev, STM32_DMA_SFCR(chan->id), dma_sfcr);
 473
 474         /* Disable DMA */
 475         ret = stm32_dma_disable_chan(chan);
 476         if (ret < 0)
 477                 return;
 478
 479         /* Clear interrupt status if it is there */
 480         status = stm32_dma_irq_status(chan);
 481         if (status) {
 482                 dev_dbg(chan2dev(chan), "%s(): clearing interrupt: 0x%08x\n",
 483                         __func__, status);
 484                 stm32_dma_irq_clear(chan, status);
 485         }
 486
 487         chan->busy = false;
 488 }
 489
 490 static int stm32_dma_terminate_all(struct dma_chan *c)
 491 {
 492         struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
 493         unsigned long flags;
 494         LIST_HEAD(head);
 495
 496         spin_lock_irqsave(&chan->vchan.lock, flags);
 497
 498         if (chan->busy) {
 499                 stm32_dma_stop(chan);
 500                 chan->desc = NULL;
 501         }
 502
 503         vchan_get_all_descriptors(&chan->vchan, &head);
 504         spin_unlock_irqrestore(&chan->vchan.lock, flags);
 505         vchan_dma_desc_free_list(&chan->vchan, &head);
 506
 507         return 0;
 508 }
 509
 510 static void stm32_dma_synchronize(struct dma_chan *c)
 511 {
 512         struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
 513
 514         vchan_synchronize(&chan->vchan);
 515 }
 516
 517 static void stm32_dma_dump_reg(struct stm32_dma_chan *chan)
 518 {
 519         struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
 520         u32 scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id));
 521         u32 ndtr = stm32_dma_read(dmadev, STM32_DMA_SNDTR(chan->id));
 522         u32 spar = stm32_dma_read(dmadev, STM32_DMA_SPAR(chan->id));
 523         u32 sm0ar = stm32_dma_read(dmadev, STM32_DMA_SM0AR(chan->id));
 524         u32 sm1ar = stm32_dma_read(dmadev, STM32_DMA_SM1AR(chan->id));
 525         u32 sfcr = stm32_dma_read(dmadev, STM32_DMA_SFCR(chan->id));
 526
 527         dev_dbg(chan2dev(chan), "SCR:   0x%08x\n", scr);
 528         dev_dbg(chan2dev(chan), "NDTR:  0x%08x\n", ndtr);
 529         dev_dbg(chan2dev(chan), "SPAR:  0x%08x\n", spar);
 530         dev_dbg(chan2dev(chan), "SM0AR: 0x%08x\n", sm0ar);
 531         dev_dbg(chan2dev(chan), "SM1AR: 0x%08x\n", sm1ar);
 532         dev_dbg(chan2dev(chan), "SFCR:  0x%08x\n", sfcr);
 533 }
 534
 535 static void stm32_dma_configure_next_sg(struct stm32_dma_chan *chan);
 536
 537 static void stm32_dma_start_transfer(struct stm32_dma_chan *chan)
 538 {
 539         struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
 540         struct virt_dma_desc *vdesc;
 541         struct stm32_dma_sg_req *sg_req;
 542         struct stm32_dma_chan_reg *reg;
 543         u32 status;
 544         int ret;
 545
 546         ret = stm32_dma_disable_chan(chan);
 547         if (ret < 0)
 548                 return;
 549
 550         if (!chan->desc) {
 551                 vdesc = vchan_next_desc(&chan->vchan);
 552                 if (!vdesc)
 553                         return;
 554
 555                 chan->desc = to_stm32_dma_desc(vdesc);
 556                 chan->next_sg = 0;
 557         }
 558
 559         if (chan->next_sg == chan->desc->num_sgs)
 560                 chan->next_sg = 0;
 561
 562         sg_req = &chan->desc->sg_req[chan->next_sg];
 563         reg = &sg_req->chan_reg;
 564
 565         stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), reg->dma_scr);
 566         stm32_dma_write(dmadev, STM32_DMA_SPAR(chan->id), reg->dma_spar);
 567         stm32_dma_write(dmadev, STM32_DMA_SM0AR(chan->id), reg->dma_sm0ar);
 568         stm32_dma_write(dmadev, STM32_DMA_SFCR(chan->id), reg->dma_sfcr);
 569         stm32_dma_write(dmadev, STM32_DMA_SM1AR(chan->id), reg->dma_sm1ar);
 570         stm32_dma_write(dmadev, STM32_DMA_SNDTR(chan->id), reg->dma_sndtr);
 571
 572         chan->next_sg++;
 573
 574         /* Clear interrupt status if it is there */
 575         status = stm32_dma_irq_status(chan);
 576         if (status)
 577                 stm32_dma_irq_clear(chan, status);
 578
 579         if (chan->desc->cyclic)
 580                 stm32_dma_configure_next_sg(chan);
 581
 582         stm32_dma_dump_reg(chan);
 583
 584         /* Start DMA */
 585         reg->dma_scr |= STM32_DMA_SCR_EN;
 586         stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), reg->dma_scr);
 587
 588         chan->busy = true;
 589
 590         dev_dbg(chan2dev(chan), "vchan %pK: started\n", &chan->vchan);
 591 }
 592
 593 static void stm32_dma_configure_next_sg(struct stm32_dma_chan *chan)
 594 {
 595         struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
 596         struct stm32_dma_sg_req *sg_req;
 597         u32 dma_scr, dma_sm0ar, dma_sm1ar, id;
 598
 599         id = chan->id;
 600         dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(id));
 601
 602         if (dma_scr & STM32_DMA_SCR_DBM) {
 603                 if (chan->next_sg == chan->desc->num_sgs)
 604                         chan->next_sg = 0;
 605
 606                 sg_req = &chan->desc->sg_req[chan->next_sg];
 607
 608                 if (dma_scr & STM32_DMA_SCR_CT) {
 609                         dma_sm0ar = sg_req->chan_reg.dma_sm0ar;
 610                         stm32_dma_write(dmadev, STM32_DMA_SM0AR(id), dma_sm0ar);
 611                         dev_dbg(chan2dev(chan), "CT=1 <=> SM0AR: 0x%08x\n",
 612                                 stm32_dma_read(dmadev, STM32_DMA_SM0AR(id)));
 613                 } else {
 614                         dma_sm1ar = sg_req->chan_reg.dma_sm1ar;
 615                         stm32_dma_write(dmadev, STM32_DMA_SM1AR(id), dma_sm1ar);
 616                         dev_dbg(chan2dev(chan), "CT=0 <=> SM1AR: 0x%08x\n",
 617                                 stm32_dma_read(dmadev, STM32_DMA_SM1AR(id)));
 618                 }
 619         }
 620 }
 621
 622 static void stm32_dma_handle_chan_done(struct stm32_dma_chan *chan)
 623 {
 624         if (chan->desc) {
 625                 if (chan->desc->cyclic) {
 626                         vchan_cyclic_callback(&chan->desc->vdesc);
 627                         chan->next_sg++;
 628                         stm32_dma_configure_next_sg(chan);
 629                 } else {
 630                         chan->busy = false;
 631                         if (chan->next_sg == chan->desc->num_sgs) {
 632                                 list_del(&chan->desc->vdesc.node);
 633                                 vchan_cookie_complete(&chan->desc->vdesc);
 634                                 chan->desc = NULL;
 635                         }
 636                         stm32_dma_start_transfer(chan);
 637                 }
 638         }
 639 }
 640
 641 static irqreturn_t stm32_dma_chan_irq(int irq, void *devid)
 642 {
 643         struct stm32_dma_chan *chan = devid;
 644         struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
 645         u32 status, scr, sfcr;
 646
 647         spin_lock(&chan->vchan.lock);
 648
 649         status = stm32_dma_irq_status(chan);
 650         scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id));
 651         sfcr = stm32_dma_read(dmadev, STM32_DMA_SFCR(chan->id));
 652
 653         if (status & STM32_DMA_TCI) {
 654                 stm32_dma_irq_clear(chan, STM32_DMA_TCI);
 655                 if (scr & STM32_DMA_SCR_TCIE)
 656                         stm32_dma_handle_chan_done(chan);
 657                 status &= ~STM32_DMA_TCI;
 658         }
 659         if (status & STM32_DMA_HTI) {
 660                 stm32_dma_irq_clear(chan, STM32_DMA_HTI);
 661                 status &= ~STM32_DMA_HTI;
 662         }
 663         if (status & STM32_DMA_FEI) {
 664                 stm32_dma_irq_clear(chan, STM32_DMA_FEI);
 665                 status &= ~STM32_DMA_FEI;
 666                 if (sfcr & STM32_DMA_SFCR_FEIE) {
 667                         if (!(scr & STM32_DMA_SCR_EN))
 668                                 dev_err(chan2dev(chan), "FIFO Error\n");
 669                         else
 670                                 dev_dbg(chan2dev(chan), "FIFO over/underrun\n");
 671                 }
 672         }
 673         if (status) {
 674                 stm32_dma_irq_clear(chan, status);
 675                 dev_err(chan2dev(chan), "DMA error: status=0x%08x\n", status);
 676                 if (!(scr & STM32_DMA_SCR_EN))
 677                         dev_err(chan2dev(chan), "chan disabled by HW\n");
 678         }
 679
 680         spin_unlock(&chan->vchan.lock);
 681
 682         return IRQ_HANDLED;
 683 }
 684
 685 static void stm32_dma_issue_pending(struct dma_chan *c)
 686 {
 687         struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
 688         unsigned long flags;
 689
 690         spin_lock_irqsave(&chan->vchan.lock, flags);
 691         if (vchan_issue_pending(&chan->vchan) && !chan->desc && !chan->busy) {
 692                 dev_dbg(chan2dev(chan), "vchan %pK: issued\n", &chan->vchan);
 693                 stm32_dma_start_transfer(chan);
 694
 695         }
 696         spin_unlock_irqrestore(&chan->vchan.lock, flags);
 697 }
 698
 699 static int stm32_dma_set_xfer_param(struct stm32_dma_chan *chan,
 700                                     enum dma_transfer_direction direction,
 701                                     enum dma_slave_buswidth *buswidth,
 702                                     u32 buf_len)
 703 {
 704         enum dma_slave_buswidth src_addr_width, dst_addr_width;
 705         int src_bus_width, dst_bus_width;
 706         int src_burst_size, dst_burst_size;
 707         u32 src_maxburst, dst_maxburst, src_best_burst, dst_best_burst;
 708         u32 dma_scr, threshold;
 709
 710         src_addr_width = chan->dma_sconfig.src_addr_width;
 711         dst_addr_width = chan->dma_sconfig.dst_addr_width;
 712         src_maxburst = chan->dma_sconfig.src_maxburst;
 713         dst_maxburst = chan->dma_sconfig.dst_maxburst;
 714         threshold = chan->threshold;
 715
 716         switch (direction) {
 717         case DMA_MEM_TO_DEV:
 718                 /* Set device data size */
 719                 dst_bus_width = stm32_dma_get_width(chan, dst_addr_width);
 720                 if (dst_bus_width < 0)
 721                         return dst_bus_width;
 722
 723                 /* Set device burst size */
 724                 dst_best_burst = stm32_dma_get_best_burst(buf_len,
 725                                                           dst_maxburst,
 726                                                           threshold,
 727                                                           dst_addr_width);
 728
 729                 dst_burst_size = stm32_dma_get_burst(chan, dst_best_burst);
 730                 if (dst_burst_size < 0)
 731                         return dst_burst_size;
 732
 733                 /* Set memory data size */
 734                 src_addr_width = stm32_dma_get_max_width(buf_len, threshold);
 735                 chan->mem_width = src_addr_width;
 736                 src_bus_width = stm32_dma_get_width(chan, src_addr_width);
 737                 if (src_bus_width < 0)
 738                         return src_bus_width;
 739
 740                 /* Set memory burst size */
 741                 src_maxburst = STM32_DMA_MAX_BURST;
 742                 src_best_burst = stm32_dma_get_best_burst(buf_len,
 743                                                           src_maxburst,
 744                                                           threshold,
 745                                                           src_addr_width);
 746                 src_burst_size = stm32_dma_get_burst(chan, src_best_burst);
 747                 if (src_burst_size < 0)
 748                         return src_burst_size;
 749
 750                 dma_scr = STM32_DMA_SCR_DIR(STM32_DMA_MEM_TO_DEV) |
 751                         STM32_DMA_SCR_PSIZE(dst_bus_width) |
 752                         STM32_DMA_SCR_MSIZE(src_bus_width) |
 753                         STM32_DMA_SCR_PBURST(dst_burst_size) |
 754                         STM32_DMA_SCR_MBURST(src_burst_size);
 755
 756                 /* Set FIFO threshold */
 757                 chan->chan_reg.dma_sfcr &= ~STM32_DMA_SFCR_FTH_MASK;
 758                 chan->chan_reg.dma_sfcr |= STM32_DMA_SFCR_FTH(threshold);
 759
 760                 /* Set peripheral address */
 761                 chan->chan_reg.dma_spar = chan->dma_sconfig.dst_addr;
 762                 *buswidth = dst_addr_width;
 763                 break;
 764
 765         case DMA_DEV_TO_MEM:
 766                 /* Set device data size */
 767                 src_bus_width = stm32_dma_get_width(chan, src_addr_width);
 768                 if (src_bus_width < 0)
 769                         return src_bus_width;
 770
 771                 /* Set device burst size */
 772                 src_best_burst = stm32_dma_get_best_burst(buf_len,
 773                                                           src_maxburst,
 774                                                           threshold,
 775                                                           src_addr_width);
 776                 chan->mem_burst = src_best_burst;
 777                 src_burst_size = stm32_dma_get_burst(chan, src_best_burst);
 778                 if (src_burst_size < 0)
 779                         return src_burst_size;
 780
 781                 /* Set memory data size */
 782                 dst_addr_width = stm32_dma_get_max_width(buf_len, threshold);
 783                 chan->mem_width = dst_addr_width;
 784                 dst_bus_width = stm32_dma_get_width(chan, dst_addr_width);
 785                 if (dst_bus_width < 0)
 786                         return dst_bus_width;
 787
 788                 /* Set memory burst size */
 789                 dst_maxburst = STM32_DMA_MAX_BURST;
 790                 dst_best_burst = stm32_dma_get_best_burst(buf_len,
 791                                                           dst_maxburst,
 792                                                           threshold,
 793                                                           dst_addr_width);
 794                 chan->mem_burst = dst_best_burst;
 795                 dst_burst_size = stm32_dma_get_burst(chan, dst_best_burst);
 796                 if (dst_burst_size < 0)
 797                         return dst_burst_size;
 798
 799                 dma_scr = STM32_DMA_SCR_DIR(STM32_DMA_DEV_TO_MEM) |
 800                         STM32_DMA_SCR_PSIZE(src_bus_width) |
 801                         STM32_DMA_SCR_MSIZE(dst_bus_width) |
 802                         STM32_DMA_SCR_PBURST(src_burst_size) |
 803                         STM32_DMA_SCR_MBURST(dst_burst_size);
 804
 805                 /* Set FIFO threshold */
 806                 chan->chan_reg.dma_sfcr &= ~STM32_DMA_SFCR_FTH_MASK;
 807                 chan->chan_reg.dma_sfcr |= STM32_DMA_SFCR_FTH(threshold);
 808
 809                 /* Set peripheral address */
 810                 chan->chan_reg.dma_spar = chan->dma_sconfig.src_addr;
 811                 *buswidth = chan->dma_sconfig.src_addr_width;
 812                 break;
 813
 814         default:
 815                 dev_err(chan2dev(chan), "Dma direction is not supported\n");
 816                 return -EINVAL;
 817         }
 818
 819         stm32_dma_set_fifo_config(chan, src_best_burst, dst_best_burst);
 820
 821         /* Set DMA control register */
 822         chan->chan_reg.dma_scr &= ~(STM32_DMA_SCR_DIR_MASK |
 823                         STM32_DMA_SCR_PSIZE_MASK | STM32_DMA_SCR_MSIZE_MASK |
 824                         STM32_DMA_SCR_PBURST_MASK | STM32_DMA_SCR_MBURST_MASK);
 825         chan->chan_reg.dma_scr |= dma_scr;
 826
 827         return 0;
 828 }
 829
 830 static void stm32_dma_clear_reg(struct stm32_dma_chan_reg *regs)
 831 {
 832         memset(regs, 0, sizeof(struct stm32_dma_chan_reg));
 833 }
 834
 835 static struct dma_async_tx_descriptor *stm32_dma_prep_slave_sg(
 836         struct dma_chan *c, struct scatterlist *sgl,
 837         u32 sg_len, enum dma_transfer_direction direction,
 838         unsigned long flags, void *context)
 839 {
 840         struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
 841         struct stm32_dma_desc *desc;
 842         struct scatterlist *sg;
 843         enum dma_slave_buswidth buswidth;
 844         u32 nb_data_items;
 845         int i, ret;
 846
 847         if (!chan->config_init) {
 848                 dev_err(chan2dev(chan), "dma channel is not configured\n");
 849                 return NULL;
 850         }
 851
 852         if (sg_len < 1) {
 853                 dev_err(chan2dev(chan), "Invalid segment length %d\n", sg_len);
 854                 return NULL;
 855         }
 856
 857         desc = stm32_dma_alloc_desc(sg_len);
 858         if (!desc)
 859                 return NULL;
 860
 861         /* Set peripheral flow controller */
 862         if (chan->dma_sconfig.device_fc)
 863                 chan->chan_reg.dma_scr |= STM32_DMA_SCR_PFCTRL;
 864         else
 865                 chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_PFCTRL;
 866
 867         for_each_sg(sgl, sg, sg_len, i) {
 868                 ret = stm32_dma_set_xfer_param(chan, direction, &buswidth,
 869                                                sg_dma_len(sg));
 870                 if (ret < 0)
 871                         goto err;
 872
 873                 desc->sg_req[i].len = sg_dma_len(sg);
 874
 875                 nb_data_items = desc->sg_req[i].len / buswidth;
 876                 if (nb_data_items > STM32_DMA_ALIGNED_MAX_DATA_ITEMS) {
 877                         dev_err(chan2dev(chan), "nb items not supported\n");
 878                         goto err;
 879                 }
 880
 881                 stm32_dma_clear_reg(&desc->sg_req[i].chan_reg);
 882                 desc->sg_req[i].chan_reg.dma_scr = chan->chan_reg.dma_scr;
 883                 desc->sg_req[i].chan_reg.dma_sfcr = chan->chan_reg.dma_sfcr;
 884                 desc->sg_req[i].chan_reg.dma_spar = chan->chan_reg.dma_spar;
 885                 desc->sg_req[i].chan_reg.dma_sm0ar = sg_dma_address(sg);
 886                 desc->sg_req[i].chan_reg.dma_sm1ar = sg_dma_address(sg);
 887                 desc->sg_req[i].chan_reg.dma_sndtr = nb_data_items;
 888         }
 889
 890         desc->num_sgs = sg_len;
 891         desc->cyclic = false;
 892
 893         return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
 894
 895 err:
 896         kfree(desc);
 897         return NULL;
 898 }
 899
 900 static struct dma_async_tx_descriptor *stm32_dma_prep_dma_cyclic(
 901         struct dma_chan *c, dma_addr_t buf_addr, size_t buf_len,
 902         size_t period_len, enum dma_transfer_direction direction,
 903         unsigned long flags)
 904 {
 905         struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
 906         struct stm32_dma_desc *desc;
 907         enum dma_slave_buswidth buswidth;
 908         u32 num_periods, nb_data_items;
 909         int i, ret;
 910
 911         if (!buf_len || !period_len) {
 912                 dev_err(chan2dev(chan), "Invalid buffer/period len\n");
 913                 return NULL;
 914         }
 915
 916         if (!chan->config_init) {
 917                 dev_err(chan2dev(chan), "dma channel is not configured\n");
 918                 return NULL;
 919         }
 920
 921         if (buf_len % period_len) {
 922                 dev_err(chan2dev(chan), "buf_len not multiple of period_len\n");
 923                 return NULL;
 924         }
 925
 926         /*
 927          * We allow to take more number of requests till DMA is
 928          * not started. The driver will loop over all requests.
 929          * Once DMA is started then new requests can be queued only after
 930          * terminating the DMA.
 931          */
 932         if (chan->busy) {
 933                 dev_err(chan2dev(chan), "Request not allowed when dma busy\n");
 934                 return NULL;
 935         }
 936
 937         ret = stm32_dma_set_xfer_param(chan, direction, &buswidth, period_len);
 938         if (ret < 0)
 939                 return NULL;
 940
 941         nb_data_items = period_len / buswidth;
 942         if (nb_data_items > STM32_DMA_ALIGNED_MAX_DATA_ITEMS) {
 943                 dev_err(chan2dev(chan), "number of items not supported\n");
 944                 return NULL;
 945         }
 946
 947         /*  Enable Circular mode or double buffer mode */
 948         if (buf_len == period_len)
 949                 chan->chan_reg.dma_scr |= STM32_DMA_SCR_CIRC;
 950         else
 951                 chan->chan_reg.dma_scr |= STM32_DMA_SCR_DBM;
 952
 953         /* Clear periph ctrl if client set it */
 954         chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_PFCTRL;
 955
 956         num_periods = buf_len / period_len;
 957
 958         desc = stm32_dma_alloc_desc(num_periods);
 959         if (!desc)
 960                 return NULL;
 961
 962         for (i = 0; i < num_periods; i++) {
 963                 desc->sg_req[i].len = period_len;
 964
 965                 stm32_dma_clear_reg(&desc->sg_req[i].chan_reg);
 966                 desc->sg_req[i].chan_reg.dma_scr = chan->chan_reg.dma_scr;
 967                 desc->sg_req[i].chan_reg.dma_sfcr = chan->chan_reg.dma_sfcr;
 968                 desc->sg_req[i].chan_reg.dma_spar = chan->chan_reg.dma_spar;
 969                 desc->sg_req[i].chan_reg.dma_sm0ar = buf_addr;
 970                 desc->sg_req[i].chan_reg.dma_sm1ar = buf_addr;
 971                 desc->sg_req[i].chan_reg.dma_sndtr = nb_data_items;
 972                 buf_addr += period_len;
 973         }
 974
 975         desc->num_sgs = num_periods;
 976         desc->cyclic = true;
 977
 978         return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
 979 }
 980
 981 static struct dma_async_tx_descriptor *stm32_dma_prep_dma_memcpy(
 982         struct dma_chan *c, dma_addr_t dest,
 983         dma_addr_t src, size_t len, unsigned long flags)
 984 {
 985         struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
 986         enum dma_slave_buswidth max_width;
 987         struct stm32_dma_desc *desc;
 988         size_t xfer_count, offset;
 989         u32 num_sgs, best_burst, dma_burst, threshold;
 990         int i;
 991
 992         num_sgs = DIV_ROUND_UP(len, STM32_DMA_ALIGNED_MAX_DATA_ITEMS);
 993         desc = stm32_dma_alloc_desc(num_sgs);
 994         if (!desc)
 995                 return NULL;
 996
 997         threshold = chan->threshold;
 998
 999         for (offset = 0, i = 0; offset < len; offset += xfer_count, i++) {
1000                 xfer_count = min_t(size_t, len - offset,
1001                                    STM32_DMA_ALIGNED_MAX_DATA_ITEMS);
1002
1003                 /* Compute best burst size */
1004                 max_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1005                 best_burst = stm32_dma_get_best_burst(len, STM32_DMA_MAX_BURST,
1006                                                       threshold, max_width);
1007                 dma_burst = stm32_dma_get_burst(chan, best_burst);
1008
1009                 stm32_dma_clear_reg(&desc->sg_req[i].chan_reg);
1010                 desc->sg_req[i].chan_reg.dma_scr =
1011                         STM32_DMA_SCR_DIR(STM32_DMA_MEM_TO_MEM) |
1012                         STM32_DMA_SCR_PBURST(dma_burst) |
1013                         STM32_DMA_SCR_MBURST(dma_burst) |
1014                         STM32_DMA_SCR_MINC |
1015                         STM32_DMA_SCR_PINC |
1016                         STM32_DMA_SCR_TCIE |
1017                         STM32_DMA_SCR_TEIE;
1018                 desc->sg_req[i].chan_reg.dma_sfcr |= STM32_DMA_SFCR_MASK;
1019                 desc->sg_req[i].chan_reg.dma_sfcr |=
1020                         STM32_DMA_SFCR_FTH(threshold);
1021                 desc->sg_req[i].chan_reg.dma_spar = src + offset;
1022                 desc->sg_req[i].chan_reg.dma_sm0ar = dest + offset;
1023                 desc->sg_req[i].chan_reg.dma_sndtr = xfer_count;
1024                 desc->sg_req[i].len = xfer_count;
1025         }
1026
1027         desc->num_sgs = num_sgs;
1028         desc->cyclic = false;
1029
1030         return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
1031 }
1032
1033 static u32 stm32_dma_get_remaining_bytes(struct stm32_dma_chan *chan)
1034 {
1035         u32 dma_scr, width, ndtr;
1036         struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
1037
1038         dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id));
1039         width = STM32_DMA_SCR_PSIZE_GET(dma_scr);
1040         ndtr = stm32_dma_read(dmadev, STM32_DMA_SNDTR(chan->id));
1041
1042         return ndtr << width;
1043 }
1044
1045 static size_t stm32_dma_desc_residue(struct stm32_dma_chan *chan,
1046                                      struct stm32_dma_desc *desc,
1047                                      u32 next_sg)
1048 {
1049         u32 modulo, burst_size;
1050         u32 residue = 0;
1051         int i;
1052
1053         /*
1054          * In cyclic mode, for the last period, residue = remaining bytes from
1055          * NDTR
1056          */
1057         if (chan->desc->cyclic && next_sg == 0) {
1058                 residue = stm32_dma_get_remaining_bytes(chan);
1059                 goto end;
1060         }
1061
1062         /*
1063          * For all other periods in cyclic mode, and in sg mode,
1064          * residue = remaining bytes from NDTR + remaining periods/sg to be
1065          * transferred
1066          */
1067         for (i = next_sg; i < desc->num_sgs; i++)
1068                 residue += desc->sg_req[i].len;
1069         residue += stm32_dma_get_remaining_bytes(chan);
1070
1071 end:
1072         if (!chan->mem_burst)
1073                 return residue;
1074
1075         burst_size = chan->mem_burst * chan->mem_width;
1076         modulo = residue % burst_size;
1077         if (modulo)
1078                 residue = residue - modulo + burst_size;
1079
1080         return residue;
1081 }
1082
1083 static enum dma_status stm32_dma_tx_status(struct dma_chan *c,
1084                                            dma_cookie_t cookie,
1085                                            struct dma_tx_state *state)
1086 {
1087         struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
1088         struct virt_dma_desc *vdesc;
1089         enum dma_status status;
1090         unsigned long flags;
1091         u32 residue = 0;
1092
1093         status = dma_cookie_status(c, cookie, state);
1094         if (status == DMA_COMPLETE || !state)
1095                 return status;
1096
1097         spin_lock_irqsave(&chan->vchan.lock, flags);
1098         vdesc = vchan_find_desc(&chan->vchan, cookie);
1099         if (chan->desc && cookie == chan->desc->vdesc.tx.cookie)
1100                 residue = stm32_dma_desc_residue(chan, chan->desc,
1101                                                  chan->next_sg);
1102         else if (vdesc)
1103                 residue = stm32_dma_desc_residue(chan,
1104                                                  to_stm32_dma_desc(vdesc), 0);
1105         dma_set_residue(state, residue);
1106
1107         spin_unlock_irqrestore(&chan->vchan.lock, flags);
1108
1109         return status;
1110 }
1111
1112 static int stm32_dma_alloc_chan_resources(struct dma_chan *c)
1113 {
1114         struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
1115         struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
1116         int ret;
1117
1118         chan->config_init = false;
1119
1120         ret = pm_runtime_get_sync(dmadev->ddev.dev);
1121         if (ret < 0)
1122                 return ret;
1123
1124         ret = stm32_dma_disable_chan(chan);
1125         if (ret < 0)
1126                 pm_runtime_put(dmadev->ddev.dev);
1127
1128         return ret;
1129 }
1130
1131 static void stm32_dma_free_chan_resources(struct dma_chan *c)
1132 {
1133         struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
1134         struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
1135         unsigned long flags;
1136
1137         dev_dbg(chan2dev(chan), "Freeing channel %d\n", chan->id);
1138
1139         if (chan->busy) {
1140                 spin_lock_irqsave(&chan->vchan.lock, flags);
1141                 stm32_dma_stop(chan);
1142                 chan->desc = NULL;
1143                 spin_unlock_irqrestore(&chan->vchan.lock, flags);
1144         }
1145
1146         pm_runtime_put(dmadev->ddev.dev);
1147
1148         vchan_free_chan_resources(to_virt_chan(c));
1149 }
1150
1151 static void stm32_dma_desc_free(struct virt_dma_desc *vdesc)
1152 {
1153         kfree(container_of(vdesc, struct stm32_dma_desc, vdesc));
1154 }
1155
1156 static void stm32_dma_set_config(struct stm32_dma_chan *chan,
1157                                  struct stm32_dma_cfg *cfg)
1158 {
1159         stm32_dma_clear_reg(&chan->chan_reg);
1160
1161         chan->chan_reg.dma_scr = cfg->stream_config & STM32_DMA_SCR_CFG_MASK;
1162         chan->chan_reg.dma_scr |= STM32_DMA_SCR_REQ(cfg->request_line);
1163
1164         /* Enable Interrupts  */
1165         chan->chan_reg.dma_scr |= STM32_DMA_SCR_TEIE | STM32_DMA_SCR_TCIE;
1166
1167         chan->threshold = STM32_DMA_THRESHOLD_FTR_GET(cfg->features);
1168 }
1169
1170 static struct dma_chan *stm32_dma_of_xlate(struct of_phandle_args *dma_spec,
1171                                            struct of_dma *ofdma)
1172 {
1173         struct stm32_dma_device *dmadev = ofdma->of_dma_data;
1174         struct device *dev = dmadev->ddev.dev;
1175         struct stm32_dma_cfg cfg;
1176         struct stm32_dma_chan *chan;
1177         struct dma_chan *c;
1178
1179         if (dma_spec->args_count < 4) {
1180                 dev_err(dev, "Bad number of cells\n");
1181                 return NULL;
1182         }
1183
1184         cfg.channel_id = dma_spec->args[0];
1185         cfg.request_line = dma_spec->args[1];
1186         cfg.stream_config = dma_spec->args[2];
1187         cfg.features = dma_spec->args[3];
1188
1189         if (cfg.channel_id >= STM32_DMA_MAX_CHANNELS ||
1190             cfg.request_line >= STM32_DMA_MAX_REQUEST_ID) {
1191                 dev_err(dev, "Bad channel and/or request id\n");
1192                 return NULL;
1193         }
1194
1195         chan = &dmadev->chan[cfg.channel_id];
1196
1197         c = dma_get_slave_channel(&chan->vchan.chan);
1198         if (!c) {
1199                 dev_err(dev, "No more channels available\n");
1200                 return NULL;
1201         }
1202
1203         stm32_dma_set_config(chan, &cfg);
1204
1205         return c;
1206 }
1207
1208 static const struct of_device_id stm32_dma_of_match[] = {
1209         { .compatible = "st,stm32-dma", },
1210         { /* sentinel */ },
1211 };
1212 MODULE_DEVICE_TABLE(of, stm32_dma_of_match);
1213
1214 static int stm32_dma_probe(struct platform_device *pdev)
1215 {
1216         struct stm32_dma_chan *chan;
1217         struct stm32_dma_device *dmadev;
1218         struct dma_device *dd;
1219         const struct of_device_id *match;
1220         struct resource *res;
1221         int i, ret;
1222
1223         match = of_match_device(stm32_dma_of_match, &pdev->dev);
1224         if (!match) {
1225                 dev_err(&pdev->dev, "Error: No device match found\n");
1226                 return -ENODEV;
1227         }
1228
1229         dmadev = devm_kzalloc(&pdev->dev, sizeof(*dmadev), GFP_KERNEL);
1230         if (!dmadev)
1231                 return -ENOMEM;
1232
1233         dd = &dmadev->ddev;
1234
1235         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1236         dmadev->base = devm_ioremap_resource(&pdev->dev, res);
1237         if (IS_ERR(dmadev->base))
1238                 return PTR_ERR(dmadev->base);
1239
1240         dmadev->clk = devm_clk_get(&pdev->dev, NULL);
1241         if (IS_ERR(dmadev->clk)) {
1242                 dev_err(&pdev->dev, "Error: Missing controller clock\n");
1243                 return PTR_ERR(dmadev->clk);
1244         }
1245
1246         ret = clk_prepare_enable(dmadev->clk);
1247         if (ret < 0) {
1248                 dev_err(&pdev->dev, "clk_prep_enable error: %d\n", ret);
1249                 return ret;
1250         }
1251
1252         dmadev->mem2mem = of_property_read_bool(pdev->dev.of_node,
1253                                                 "st,mem2mem");
1254
1255         dmadev->rst = devm_reset_control_get(&pdev->dev, NULL);
1256         if (!IS_ERR(dmadev->rst)) {
1257                 reset_control_assert(dmadev->rst);
1258                 udelay(2);
1259                 reset_control_deassert(dmadev->rst);
1260         }
1261
1262         dma_cap_set(DMA_SLAVE, dd->cap_mask);
1263         dma_cap_set(DMA_PRIVATE, dd->cap_mask);
1264         dma_cap_set(DMA_CYCLIC, dd->cap_mask);
1265         dd->device_alloc_chan_resources = stm32_dma_alloc_chan_resources;
1266         dd->device_free_chan_resources = stm32_dma_free_chan_resources;
1267         dd->device_tx_status = stm32_dma_tx_status;
1268         dd->device_issue_pending = stm32_dma_issue_pending;
1269         dd->device_prep_slave_sg = stm32_dma_prep_slave_sg;
1270         dd->device_prep_dma_cyclic = stm32_dma_prep_dma_cyclic;
1271         dd->device_config = stm32_dma_slave_config;
1272         dd->device_terminate_all = stm32_dma_terminate_all;
1273         dd->device_synchronize = stm32_dma_synchronize;
1274         dd->src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
1275                 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
1276                 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
1277         dd->dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
1278                 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
1279                 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
1280         dd->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
1281         dd->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
1282         dd->max_burst = STM32_DMA_MAX_BURST;
1283         dd->dev = &pdev->dev;
1284         INIT_LIST_HEAD(&dd->channels);
1285
1286         if (dmadev->mem2mem) {
1287                 dma_cap_set(DMA_MEMCPY, dd->cap_mask);
1288                 dd->device_prep_dma_memcpy = stm32_dma_prep_dma_memcpy;
1289                 dd->directions |= BIT(DMA_MEM_TO_MEM);
1290         }
1291
1292         for (i = 0; i < STM32_DMA_MAX_CHANNELS; i++) {
1293                 chan = &dmadev->chan[i];
1294                 chan->id = i;
1295                 chan->vchan.desc_free = stm32_dma_desc_free;
1296                 vchan_init(&chan->vchan, dd);
1297         }
1298
1299         ret = dma_async_device_register(dd);
1300         if (ret)
1301                 goto clk_free;
1302
1303         for (i = 0; i < STM32_DMA_MAX_CHANNELS; i++) {
1304                 chan = &dmadev->chan[i];
1305                 res = platform_get_resource(pdev, IORESOURCE_IRQ, i);
1306                 if (!res) {
1307                         ret = -EINVAL;
1308                         dev_err(&pdev->dev, "No irq resource for chan %d\n", i);
1309                         goto err_unregister;
1310                 }
1311                 chan->irq = res->start;
1312                 ret = devm_request_irq(&pdev->dev, chan->irq,
1313                                        stm32_dma_chan_irq, 0,
1314                                        dev_name(chan2dev(chan)), chan);
1315                 if (ret) {
1316                         dev_err(&pdev->dev,
1317                                 "request_irq failed with err %d channel %d\n",
1318                                 ret, i);
1319                         goto err_unregister;
1320                 }
1321         }
1322
1323         ret = of_dma_controller_register(pdev->dev.of_node,
1324                                          stm32_dma_of_xlate, dmadev);
1325         if (ret < 0) {
1326                 dev_err(&pdev->dev,
1327                         "STM32 DMA DMA OF registration failed %d\n", ret);
1328                 goto err_unregister;
1329         }
1330
1331         platform_set_drvdata(pdev, dmadev);
1332
1333         pm_runtime_set_active(&pdev->dev);
1334         pm_runtime_enable(&pdev->dev);
1335         pm_runtime_get_noresume(&pdev->dev);
1336         pm_runtime_put(&pdev->dev);
1337
1338         dev_info(&pdev->dev, "STM32 DMA driver registered\n");
1339
1340         return 0;
1341
1342 err_unregister:
1343         dma_async_device_unregister(dd);
1344 clk_free:
1345         clk_disable_unprepare(dmadev->clk);
1346
1347         return ret;
1348 }
1349
1350 #ifdef CONFIG_PM
1351 static int stm32_dma_runtime_suspend(struct device *dev)
1352 {
1353         struct stm32_dma_device *dmadev = dev_get_drvdata(dev);
1354
1355         clk_disable_unprepare(dmadev->clk);
1356
1357         return 0;
1358 }
1359
1360 static int stm32_dma_runtime_resume(struct device *dev)
1361 {
1362         struct stm32_dma_device *dmadev = dev_get_drvdata(dev);
1363         int ret;
1364
1365         ret = clk_prepare_enable(dmadev->clk);
1366         if (ret) {
1367                 dev_err(dev, "failed to prepare_enable clock\n");
1368                 return ret;
1369         }
1370
1371         return 0;
1372 }
1373 #endif
1374
1375 static const struct dev_pm_ops stm32_dma_pm_ops = {
1376         SET_RUNTIME_PM_OPS(stm32_dma_runtime_suspend,
1377                            stm32_dma_runtime_resume, NULL)
1378 };
1379
1380 static struct platform_driver stm32_dma_driver = {
1381         .driver = {
1382                 .name = "stm32-dma",
1383                 .of_match_table = stm32_dma_of_match,
1384                 .pm = &stm32_dma_pm_ops,
1385         },
1386 };
1387
1388 static int __init stm32_dma_init(void)
1389 {
1390         return platform_driver_probe(&stm32_dma_driver, stm32_dma_probe);
1391 }
1392 subsys_initcall(stm32_dma_init);