drivers/gpio/gpio-omap.c

   1 /*
   2  * Support functions for OMAP GPIO
   3  *
   4  * Copyright (C) 2003-2005 Nokia Corporation
   5  * Written by Juha Yrjölä <juha.yrjola@nokia.com>
   6  *
   7  * Copyright (C) 2009 Texas Instruments
   8  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  */
  14
  15 #include <linux/init.h>
  16 #include <linux/module.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/syscore_ops.h>
  19 #include <linux/err.h>
  20 #include <linux/clk.h>
  21 #include <linux/io.h>
  22 #include <linux/device.h>
  23 #include <linux/pm_runtime.h>
  24 #include <linux/pm.h>
  25 #include <linux/of.h>
  26 #include <linux/of_device.h>
  27 #include <linux/gpio.h>
  28 #include <linux/bitops.h>
  29 #include <linux/platform_data/gpio-omap.h>
  30
  31 #define OFF_MODE        1
  32
  33 static LIST_HEAD(omap_gpio_list);
  34
  35 struct gpio_regs {
  36         u32 irqenable1;
  37         u32 irqenable2;
  38         u32 wake_en;
  39         u32 ctrl;
  40         u32 oe;
  41         u32 leveldetect0;
  42         u32 leveldetect1;
  43         u32 risingdetect;
  44         u32 fallingdetect;
  45         u32 dataout;
  46         u32 debounce;
  47         u32 debounce_en;
  48 };
  49
  50 struct gpio_bank {
  51         struct list_head node;
  52         void __iomem *base;
  53         u16 irq;
  54         u32 non_wakeup_gpios;
  55         u32 enabled_non_wakeup_gpios;
  56         struct gpio_regs context;
  57         u32 saved_datain;
  58         u32 level_mask;
  59         u32 toggle_mask;
  60         spinlock_t lock;
  61         struct gpio_chip chip;
  62         struct clk *dbck;
  63         u32 mod_usage;
  64         u32 irq_usage;
  65         u32 dbck_enable_mask;
  66         bool dbck_enabled;
  67         struct device *dev;
  68         bool is_mpuio;
  69         bool dbck_flag;
  70         bool loses_context;
  71         bool context_valid;
  72         int stride;
  73         u32 width;
  74         int context_loss_count;
  75         int power_mode;
  76         bool workaround_enabled;
  77
  78         void (*set_dataout)(struct gpio_bank *bank, unsigned gpio, int enable);
  79         int (*get_context_loss_count)(struct device *dev);
  80
  81         struct omap_gpio_reg_offs *regs;
  82 };
  83
  84 #define GPIO_MOD_CTRL_BIT       BIT(0)
  85
  86 #define BANK_USED(bank) (bank->mod_usage || bank->irq_usage)
  87 #define LINE_USED(line, offset) (line & (BIT(offset)))
  88
  89 static void omap_gpio_unmask_irq(struct irq_data *d);
  90
  91 static inline struct gpio_bank *omap_irq_data_get_bank(struct irq_data *d)
  92 {
  93         struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
  94         return container_of(chip, struct gpio_bank, chip);
  95 }
  96
  97 static void omap_set_gpio_direction(struct gpio_bank *bank, int gpio,
  98                                     int is_input)
  99 {
 100         void __iomem *reg = bank->base;
 101         u32 l;
 102
 103         reg += bank->regs->direction;
 104         l = readl_relaxed(reg);
 105         if (is_input)
 106                 l |= BIT(gpio);
 107         else
 108                 l &= ~(BIT(gpio));
 109         writel_relaxed(l, reg);
 110         bank->context.oe = l;
 111 }
 112
 113
 114 /* set data out value using dedicate set/clear register */
 115 static void omap_set_gpio_dataout_reg(struct gpio_bank *bank, unsigned offset,
 116                                       int enable)
 117 {
 118         void __iomem *reg = bank->base;
 119         u32 l = BIT(offset);
 120
 121         if (enable) {
 122                 reg += bank->regs->set_dataout;
 123                 bank->context.dataout |= l;
 124         } else {
 125                 reg += bank->regs->clr_dataout;
 126                 bank->context.dataout &= ~l;
 127         }
 128
 129         writel_relaxed(l, reg);
 130 }
 131
 132 /* set data out value using mask register */
 133 static void omap_set_gpio_dataout_mask(struct gpio_bank *bank, unsigned offset,
 134                                        int enable)
 135 {
 136         void __iomem *reg = bank->base + bank->regs->dataout;
 137         u32 gpio_bit = BIT(offset);
 138         u32 l;
 139
 140         l = readl_relaxed(reg);
 141         if (enable)
 142                 l |= gpio_bit;
 143         else
 144                 l &= ~gpio_bit;
 145         writel_relaxed(l, reg);
 146         bank->context.dataout = l;
 147 }
 148
 149 static int omap_get_gpio_datain(struct gpio_bank *bank, int offset)
 150 {
 151         void __iomem *reg = bank->base + bank->regs->datain;
 152
 153         return (readl_relaxed(reg) & (BIT(offset))) != 0;
 154 }
 155
 156 static int omap_get_gpio_dataout(struct gpio_bank *bank, int offset)
 157 {
 158         void __iomem *reg = bank->base + bank->regs->dataout;
 159
 160         return (readl_relaxed(reg) & (BIT(offset))) != 0;
 161 }
 162
 163 static inline void omap_gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set)
 164 {
 165         int l = readl_relaxed(base + reg);
 166
 167         if (set)
 168                 l |= mask;
 169         else
 170                 l &= ~mask;
 171
 172         writel_relaxed(l, base + reg);
 173 }
 174
 175 static inline void omap_gpio_dbck_enable(struct gpio_bank *bank)
 176 {
 177         if (bank->dbck_enable_mask && !bank->dbck_enabled) {
 178                 clk_prepare_enable(bank->dbck);
 179                 bank->dbck_enabled = true;
 180
 181                 writel_relaxed(bank->dbck_enable_mask,
 182                              bank->base + bank->regs->debounce_en);
 183         }
 184 }
 185
 186 static inline void omap_gpio_dbck_disable(struct gpio_bank *bank)
 187 {
 188         if (bank->dbck_enable_mask && bank->dbck_enabled) {
 189                 /*
 190                  * Disable debounce before cutting it's clock. If debounce is
 191                  * enabled but the clock is not, GPIO module seems to be unable
 192                  * to detect events and generate interrupts at least on OMAP3.
 193                  */
 194                 writel_relaxed(0, bank->base + bank->regs->debounce_en);
 195
 196                 clk_disable_unprepare(bank->dbck);
 197                 bank->dbck_enabled = false;
 198         }
 199 }
 200
 201 /**
 202  * omap2_set_gpio_debounce - low level gpio debounce time
 203  * @bank: the gpio bank we're acting upon
 204  * @offset: the gpio number on this @bank
 205  * @debounce: debounce time to use
 206  *
 207  * OMAP's debounce time is in 31us steps so we need
 208  * to convert and round up to the closest unit.
 209  */
 210 static void omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned offset,
 211                                     unsigned debounce)
 212 {
 213         void __iomem            *reg;
 214         u32                     val;
 215         u32                     l;
 216
 217         if (!bank->dbck_flag)
 218                 return;
 219
 220         if (debounce < 32)
 221                 debounce = 0x01;
 222         else if (debounce > 7936)
 223                 debounce = 0xff;
 224         else
 225                 debounce = (debounce / 0x1f) - 1;
 226
 227         l = BIT(offset);
 228
 229         clk_prepare_enable(bank->dbck);
 230         reg = bank->base + bank->regs->debounce;
 231         writel_relaxed(debounce, reg);
 232
 233         reg = bank->base + bank->regs->debounce_en;
 234         val = readl_relaxed(reg);
 235
 236         if (debounce)
 237                 val |= l;
 238         else
 239                 val &= ~l;
 240         bank->dbck_enable_mask = val;
 241
 242         writel_relaxed(val, reg);
 243         clk_disable_unprepare(bank->dbck);
 244         /*
 245          * Enable debounce clock per module.
 246          * This call is mandatory because in omap_gpio_request() when
 247          * *_runtime_get_sync() is called,  _gpio_dbck_enable() within
 248          * runtime callbck fails to turn on dbck because dbck_enable_mask
 249          * used within _gpio_dbck_enable() is still not initialized at
 250          * that point. Therefore we have to enable dbck here.
 251          */
 252         omap_gpio_dbck_enable(bank);
 253         if (bank->dbck_enable_mask) {
 254                 bank->context.debounce = debounce;
 255                 bank->context.debounce_en = val;
 256         }
 257 }
 258
 259 /**
 260  * omap_clear_gpio_debounce - clear debounce settings for a gpio
 261  * @bank: the gpio bank we're acting upon
 262  * @offset: the gpio number on this @bank
 263  *
 264  * If a gpio is using debounce, then clear the debounce enable bit and if
 265  * this is the only gpio in this bank using debounce, then clear the debounce
 266  * time too. The debounce clock will also be disabled when calling this function
 267  * if this is the only gpio in the bank using debounce.
 268  */
 269 static void omap_clear_gpio_debounce(struct gpio_bank *bank, unsigned offset)
 270 {
 271         u32 gpio_bit = BIT(offset);
 272
 273         if (!bank->dbck_flag)
 274                 return;
 275
 276         if (!(bank->dbck_enable_mask & gpio_bit))
 277                 return;
 278
 279         bank->dbck_enable_mask &= ~gpio_bit;
 280         bank->context.debounce_en &= ~gpio_bit;
 281         writel_relaxed(bank->context.debounce_en,
 282                      bank->base + bank->regs->debounce_en);
 283
 284         if (!bank->dbck_enable_mask) {
 285                 bank->context.debounce = 0;
 286                 writel_relaxed(bank->context.debounce, bank->base +
 287                              bank->regs->debounce);
 288                 clk_disable_unprepare(bank->dbck);
 289                 bank->dbck_enabled = false;
 290         }
 291 }
 292
 293 static inline void omap_set_gpio_trigger(struct gpio_bank *bank, int gpio,
 294                                                 unsigned trigger)
 295 {
 296         void __iomem *base = bank->base;
 297         u32 gpio_bit = BIT(gpio);
 298
 299         omap_gpio_rmw(base, bank->regs->leveldetect0, gpio_bit,
 300                       trigger & IRQ_TYPE_LEVEL_LOW);
 301         omap_gpio_rmw(base, bank->regs->leveldetect1, gpio_bit,
 302                       trigger & IRQ_TYPE_LEVEL_HIGH);
 303         omap_gpio_rmw(base, bank->regs->risingdetect, gpio_bit,
 304                       trigger & IRQ_TYPE_EDGE_RISING);
 305         omap_gpio_rmw(base, bank->regs->fallingdetect, gpio_bit,
 306                       trigger & IRQ_TYPE_EDGE_FALLING);
 307
 308         bank->context.leveldetect0 =
 309                         readl_relaxed(bank->base + bank->regs->leveldetect0);
 310         bank->context.leveldetect1 =
 311                         readl_relaxed(bank->base + bank->regs->leveldetect1);
 312         bank->context.risingdetect =
 313                         readl_relaxed(bank->base + bank->regs->risingdetect);
 314         bank->context.fallingdetect =
 315                         readl_relaxed(bank->base + bank->regs->fallingdetect);
 316
 317         if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
 318                 omap_gpio_rmw(base, bank->regs->wkup_en, gpio_bit, trigger != 0);
 319                 bank->context.wake_en =
 320                         readl_relaxed(bank->base + bank->regs->wkup_en);
 321         }
 322
 323         /* This part needs to be executed always for OMAP{34xx, 44xx} */
 324         if (!bank->regs->irqctrl) {
 325                 /* On omap24xx proceed only when valid GPIO bit is set */
 326                 if (bank->non_wakeup_gpios) {
 327                         if (!(bank->non_wakeup_gpios & gpio_bit))
 328                                 goto exit;
 329                 }
 330
 331                 /*
 332                  * Log the edge gpio and manually trigger the IRQ
 333                  * after resume if the input level changes
 334                  * to avoid irq lost during PER RET/OFF mode
 335                  * Applies for omap2 non-wakeup gpio and all omap3 gpios
 336                  */
 337                 if (trigger & IRQ_TYPE_EDGE_BOTH)
 338                         bank->enabled_non_wakeup_gpios |= gpio_bit;
 339                 else
 340                         bank->enabled_non_wakeup_gpios &= ~gpio_bit;
 341         }
 342
 343 exit:
 344         bank->level_mask =
 345                 readl_relaxed(bank->base + bank->regs->leveldetect0) |
 346                 readl_relaxed(bank->base + bank->regs->leveldetect1);
 347 }
 348
 349 #ifdef CONFIG_ARCH_OMAP1
 350 /*
 351  * This only applies to chips that can't do both rising and falling edge
 352  * detection at once.  For all other chips, this function is a noop.
 353  */
 354 static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
 355 {
 356         void __iomem *reg = bank->base;
 357         u32 l = 0;
 358
 359         if (!bank->regs->irqctrl)
 360                 return;
 361
 362         reg += bank->regs->irqctrl;
 363
 364         l = readl_relaxed(reg);
 365         if ((l >> gpio) & 1)
 366                 l &= ~(BIT(gpio));
 367         else
 368                 l |= BIT(gpio);
 369
 370         writel_relaxed(l, reg);
 371 }
 372 #else
 373 static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {}
 374 #endif
 375
 376 static int omap_set_gpio_triggering(struct gpio_bank *bank, int gpio,
 377                                     unsigned trigger)
 378 {
 379         void __iomem *reg = bank->base;
 380         void __iomem *base = bank->base;
 381         u32 l = 0;
 382
 383         if (bank->regs->leveldetect0 && bank->regs->wkup_en) {
 384                 omap_set_gpio_trigger(bank, gpio, trigger);
 385         } else if (bank->regs->irqctrl) {
 386                 reg += bank->regs->irqctrl;
 387
 388                 l = readl_relaxed(reg);
 389                 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
 390                         bank->toggle_mask |= BIT(gpio);
 391                 if (trigger & IRQ_TYPE_EDGE_RISING)
 392                         l |= BIT(gpio);
 393                 else if (trigger & IRQ_TYPE_EDGE_FALLING)
 394                         l &= ~(BIT(gpio));
 395                 else
 396                         return -EINVAL;
 397
 398                 writel_relaxed(l, reg);
 399         } else if (bank->regs->edgectrl1) {
 400                 if (gpio & 0x08)
 401                         reg += bank->regs->edgectrl2;
 402                 else
 403                         reg += bank->regs->edgectrl1;
 404
 405                 gpio &= 0x07;
 406                 l = readl_relaxed(reg);
 407                 l &= ~(3 << (gpio << 1));
 408                 if (trigger & IRQ_TYPE_EDGE_RISING)
 409                         l |= 2 << (gpio << 1);
 410                 if (trigger & IRQ_TYPE_EDGE_FALLING)
 411                         l |= BIT(gpio << 1);
 412
 413                 /* Enable wake-up during idle for dynamic tick */
 414                 omap_gpio_rmw(base, bank->regs->wkup_en, BIT(gpio), trigger);
 415                 bank->context.wake_en =
 416                         readl_relaxed(bank->base + bank->regs->wkup_en);
 417                 writel_relaxed(l, reg);
 418         }
 419         return 0;
 420 }
 421
 422 static void omap_enable_gpio_module(struct gpio_bank *bank, unsigned offset)
 423 {
 424         if (bank->regs->pinctrl) {
 425                 void __iomem *reg = bank->base + bank->regs->pinctrl;
 426
 427                 /* Claim the pin for MPU */
 428                 writel_relaxed(readl_relaxed(reg) | (BIT(offset)), reg);
 429         }
 430
 431         if (bank->regs->ctrl && !BANK_USED(bank)) {
 432                 void __iomem *reg = bank->base + bank->regs->ctrl;
 433                 u32 ctrl;
 434
 435                 ctrl = readl_relaxed(reg);
 436                 /* Module is enabled, clocks are not gated */
 437                 ctrl &= ~GPIO_MOD_CTRL_BIT;
 438                 writel_relaxed(ctrl, reg);
 439                 bank->context.ctrl = ctrl;
 440         }
 441 }
 442
 443 static void omap_disable_gpio_module(struct gpio_bank *bank, unsigned offset)
 444 {
 445         void __iomem *base = bank->base;
 446
 447         if (bank->regs->wkup_en &&
 448             !LINE_USED(bank->mod_usage, offset) &&
 449             !LINE_USED(bank->irq_usage, offset)) {
 450                 /* Disable wake-up during idle for dynamic tick */
 451                 omap_gpio_rmw(base, bank->regs->wkup_en, BIT(offset), 0);
 452                 bank->context.wake_en =
 453                         readl_relaxed(bank->base + bank->regs->wkup_en);
 454         }
 455
 456         if (bank->regs->ctrl && !BANK_USED(bank)) {
 457                 void __iomem *reg = bank->base + bank->regs->ctrl;
 458                 u32 ctrl;
 459
 460                 ctrl = readl_relaxed(reg);
 461                 /* Module is disabled, clocks are gated */
 462                 ctrl |= GPIO_MOD_CTRL_BIT;
 463                 writel_relaxed(ctrl, reg);
 464                 bank->context.ctrl = ctrl;
 465         }
 466 }
 467
 468 static int omap_gpio_is_input(struct gpio_bank *bank, unsigned offset)
 469 {
 470         void __iomem *reg = bank->base + bank->regs->direction;
 471
 472         return readl_relaxed(reg) & BIT(offset);
 473 }
 474
 475 static void omap_gpio_init_irq(struct gpio_bank *bank, unsigned offset)
 476 {
 477         if (!LINE_USED(bank->mod_usage, offset)) {
 478                 omap_enable_gpio_module(bank, offset);
 479                 omap_set_gpio_direction(bank, offset, 1);
 480         }
 481         bank->irq_usage |= BIT(offset);
 482 }
 483
 484 static int omap_gpio_irq_type(struct irq_data *d, unsigned type)
 485 {
 486         struct gpio_bank *bank = omap_irq_data_get_bank(d);
 487         int retval;
 488         unsigned long flags;
 489         unsigned offset = d->hwirq;
 490
 491         if (!BANK_USED(bank))
 492                 pm_runtime_get_sync(bank->dev);
 493
 494         if (type & ~IRQ_TYPE_SENSE_MASK)
 495                 return -EINVAL;
 496
 497         if (!bank->regs->leveldetect0 &&
 498                 (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
 499                 return -EINVAL;
 500
 501         spin_lock_irqsave(&bank->lock, flags);
 502         retval = omap_set_gpio_triggering(bank, offset, type);
 503         omap_gpio_init_irq(bank, offset);
 504         if (!omap_gpio_is_input(bank, offset)) {
 505                 spin_unlock_irqrestore(&bank->lock, flags);
 506                 return -EINVAL;
 507         }
 508         spin_unlock_irqrestore(&bank->lock, flags);
 509
 510         if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
 511                 __irq_set_handler_locked(d->irq, handle_level_irq);
 512         else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
 513                 __irq_set_handler_locked(d->irq, handle_edge_irq);
 514
 515         return retval;
 516 }
 517
 518 static void omap_clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
 519 {
 520         void __iomem *reg = bank->base;
 521
 522         reg += bank->regs->irqstatus;
 523         writel_relaxed(gpio_mask, reg);
 524
 525         /* Workaround for clearing DSP GPIO interrupts to allow retention */
 526         if (bank->regs->irqstatus2) {
 527                 reg = bank->base + bank->regs->irqstatus2;
 528                 writel_relaxed(gpio_mask, reg);
 529         }
 530
 531         /* Flush posted write for the irq status to avoid spurious interrupts */
 532         readl_relaxed(reg);
 533 }
 534
 535 static inline void omap_clear_gpio_irqstatus(struct gpio_bank *bank,
 536                                              unsigned offset)
 537 {
 538         omap_clear_gpio_irqbank(bank, BIT(offset));
 539 }
 540
 541 static u32 omap_get_gpio_irqbank_mask(struct gpio_bank *bank)
 542 {
 543         void __iomem *reg = bank->base;
 544         u32 l;
 545         u32 mask = (BIT(bank->width)) - 1;
 546
 547         reg += bank->regs->irqenable;
 548         l = readl_relaxed(reg);
 549         if (bank->regs->irqenable_inv)
 550                 l = ~l;
 551         l &= mask;
 552         return l;
 553 }
 554
 555 static void omap_enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
 556 {
 557         void __iomem *reg = bank->base;
 558         u32 l;
 559
 560         if (bank->regs->set_irqenable) {
 561                 reg += bank->regs->set_irqenable;
 562                 l = gpio_mask;
 563                 bank->context.irqenable1 |= gpio_mask;
 564         } else {
 565                 reg += bank->regs->irqenable;
 566                 l = readl_relaxed(reg);
 567                 if (bank->regs->irqenable_inv)
 568                         l &= ~gpio_mask;
 569                 else
 570                         l |= gpio_mask;
 571                 bank->context.irqenable1 = l;
 572         }
 573
 574         writel_relaxed(l, reg);
 575 }
 576
 577 static void omap_disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
 578 {
 579         void __iomem *reg = bank->base;
 580         u32 l;
 581
 582         if (bank->regs->clr_irqenable) {
 583                 reg += bank->regs->clr_irqenable;
 584                 l = gpio_mask;
 585                 bank->context.irqenable1 &= ~gpio_mask;
 586         } else {
 587                 reg += bank->regs->irqenable;
 588                 l = readl_relaxed(reg);
 589                 if (bank->regs->irqenable_inv)
 590                         l |= gpio_mask;
 591                 else
 592                         l &= ~gpio_mask;
 593                 bank->context.irqenable1 = l;
 594         }
 595
 596         writel_relaxed(l, reg);
 597 }
 598
 599 static inline void omap_set_gpio_irqenable(struct gpio_bank *bank,
 600                                            unsigned offset, int enable)
 601 {
 602         if (enable)
 603                 omap_enable_gpio_irqbank(bank, BIT(offset));
 604         else
 605                 omap_disable_gpio_irqbank(bank, BIT(offset));
 606 }
 607
 608 /*
 609  * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
 610  * 1510 does not seem to have a wake-up register. If JTAG is connected
 611  * to the target, system will wake up always on GPIO events. While
 612  * system is running all registered GPIO interrupts need to have wake-up
 613  * enabled. When system is suspended, only selected GPIO interrupts need
 614  * to have wake-up enabled.
 615  */
 616 static int omap_set_gpio_wakeup(struct gpio_bank *bank, unsigned offset,
 617                                 int enable)
 618 {
 619         u32 gpio_bit = BIT(offset);
 620         unsigned long flags;
 621
 622         if (bank->non_wakeup_gpios & gpio_bit) {
 623                 dev_err(bank->dev,
 624                         "Unable to modify wakeup on non-wakeup GPIO%d\n",
 625                         offset);
 626                 return -EINVAL;
 627         }
 628
 629         spin_lock_irqsave(&bank->lock, flags);
 630         if (enable)
 631                 bank->context.wake_en |= gpio_bit;
 632         else
 633                 bank->context.wake_en &= ~gpio_bit;
 634
 635         writel_relaxed(bank->context.wake_en, bank->base + bank->regs->wkup_en);
 636         spin_unlock_irqrestore(&bank->lock, flags);
 637
 638         return 0;
 639 }
 640
 641 static void omap_reset_gpio(struct gpio_bank *bank, unsigned offset)
 642 {
 643         omap_set_gpio_direction(bank, offset, 1);
 644         omap_set_gpio_irqenable(bank, offset, 0);
 645         omap_clear_gpio_irqstatus(bank, offset);
 646         omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
 647         omap_clear_gpio_debounce(bank, offset);
 648 }
 649
 650 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
 651 static int omap_gpio_wake_enable(struct irq_data *d, unsigned int enable)
 652 {
 653         struct gpio_bank *bank = omap_irq_data_get_bank(d);
 654         unsigned offset = d->hwirq;
 655
 656         return omap_set_gpio_wakeup(bank, offset, enable);
 657 }
 658
 659 static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
 660 {
 661         struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
 662         unsigned long flags;
 663
 664         /*
 665          * If this is the first gpio_request for the bank,
 666          * enable the bank module.
 667          */
 668         if (!BANK_USED(bank))
 669                 pm_runtime_get_sync(bank->dev);
 670
 671         spin_lock_irqsave(&bank->lock, flags);
 672         /* Set trigger to none. You need to enable the desired trigger with
 673          * request_irq() or set_irq_type(). Only do this if the IRQ line has
 674          * not already been requested.
 675          */
 676         if (!LINE_USED(bank->irq_usage, offset)) {
 677                 omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
 678                 omap_enable_gpio_module(bank, offset);
 679         }
 680         bank->mod_usage |= BIT(offset);
 681         spin_unlock_irqrestore(&bank->lock, flags);
 682
 683         return 0;
 684 }
 685
 686 static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
 687 {
 688         struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
 689         unsigned long flags;
 690
 691         spin_lock_irqsave(&bank->lock, flags);
 692         bank->mod_usage &= ~(BIT(offset));
 693         if (!LINE_USED(bank->irq_usage, offset)) {
 694                 omap_set_gpio_direction(bank, offset, 1);
 695                 omap_clear_gpio_debounce(bank, offset);
 696         }
 697         omap_disable_gpio_module(bank, offset);
 698         spin_unlock_irqrestore(&bank->lock, flags);
 699
 700         /*
 701          * If this is the last gpio to be freed in the bank,
 702          * disable the bank module.
 703          */
 704         if (!BANK_USED(bank))
 705                 pm_runtime_put(bank->dev);
 706 }
 707
 708 /*
 709  * We need to unmask the GPIO bank interrupt as soon as possible to
 710  * avoid missing GPIO interrupts for other lines in the bank.
 711  * Then we need to mask-read-clear-unmask the triggered GPIO lines
 712  * in the bank to avoid missing nested interrupts for a GPIO line.
 713  * If we wait to unmask individual GPIO lines in the bank after the
 714  * line's interrupt handler has been run, we may miss some nested
 715  * interrupts.
 716  */
 717 static void omap_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 718 {
 719         void __iomem *isr_reg = NULL;
 720         u32 isr;
 721         unsigned int bit;
 722         struct gpio_bank *bank;
 723         int unmasked = 0;
 724         struct irq_chip *irqchip = irq_desc_get_chip(desc);
 725         struct gpio_chip *chip = irq_get_handler_data(irq);
 726
 727         chained_irq_enter(irqchip, desc);
 728
 729         bank = container_of(chip, struct gpio_bank, chip);
 730         isr_reg = bank->base + bank->regs->irqstatus;
 731         pm_runtime_get_sync(bank->dev);
 732
 733         if (WARN_ON(!isr_reg))
 734                 goto exit;
 735
 736         while (1) {
 737                 u32 isr_saved, level_mask = 0;
 738                 u32 enabled;
 739
 740                 enabled = omap_get_gpio_irqbank_mask(bank);
 741                 isr_saved = isr = readl_relaxed(isr_reg) & enabled;
 742
 743                 if (bank->level_mask)
 744                         level_mask = bank->level_mask & enabled;
 745
 746                 /* clear edge sensitive interrupts before handler(s) are
 747                 called so that we don't miss any interrupt occurred while
 748                 executing them */
 749                 omap_disable_gpio_irqbank(bank, isr_saved & ~level_mask);
 750                 omap_clear_gpio_irqbank(bank, isr_saved & ~level_mask);
 751                 omap_enable_gpio_irqbank(bank, isr_saved & ~level_mask);
 752
 753                 /* if there is only edge sensitive GPIO pin interrupts
 754                 configured, we could unmask GPIO bank interrupt immediately */
 755                 if (!level_mask && !unmasked) {
 756                         unmasked = 1;
 757                         chained_irq_exit(irqchip, desc);
 758                 }
 759
 760                 if (!isr)
 761                         break;
 762
 763                 while (isr) {
 764                         bit = __ffs(isr);
 765                         isr &= ~(BIT(bit));
 766
 767                         /*
 768                          * Some chips can't respond to both rising and falling
 769                          * at the same time.  If this irq was requested with
 770                          * both flags, we need to flip the ICR data for the IRQ
 771                          * to respond to the IRQ for the opposite direction.
 772                          * This will be indicated in the bank toggle_mask.
 773                          */
 774                         if (bank->toggle_mask & (BIT(bit)))
 775                                 omap_toggle_gpio_edge_triggering(bank, bit);
 776
 777                         generic_handle_irq(irq_find_mapping(bank->chip.irqdomain,
 778                                                             bit));
 779                 }
 780         }
 781         /* if bank has any level sensitive GPIO pin interrupt
 782         configured, we must unmask the bank interrupt only after
 783         handler(s) are executed in order to avoid spurious bank
 784         interrupt */
 785 exit:
 786         if (!unmasked)
 787                 chained_irq_exit(irqchip, desc);
 788         pm_runtime_put(bank->dev);
 789 }
 790
 791 static unsigned int omap_gpio_irq_startup(struct irq_data *d)
 792 {
 793         struct gpio_bank *bank = omap_irq_data_get_bank(d);
 794         unsigned long flags;
 795         unsigned offset = d->hwirq;
 796
 797         if (!BANK_USED(bank))
 798                 pm_runtime_get_sync(bank->dev);
 799
 800         spin_lock_irqsave(&bank->lock, flags);
 801         omap_gpio_init_irq(bank, offset);
 802         spin_unlock_irqrestore(&bank->lock, flags);
 803         omap_gpio_unmask_irq(d);
 804
 805         return 0;
 806 }
 807
 808 static void omap_gpio_irq_shutdown(struct irq_data *d)
 809 {
 810         struct gpio_bank *bank = omap_irq_data_get_bank(d);
 811         unsigned long flags;
 812         unsigned offset = d->hwirq;
 813
 814         spin_lock_irqsave(&bank->lock, flags);
 815         bank->irq_usage &= ~(BIT(offset));
 816         omap_disable_gpio_module(bank, offset);
 817         omap_reset_gpio(bank, offset);
 818         spin_unlock_irqrestore(&bank->lock, flags);
 819
 820         /*
 821          * If this is the last IRQ to be freed in the bank,
 822          * disable the bank module.
 823          */
 824         if (!BANK_USED(bank))
 825                 pm_runtime_put(bank->dev);
 826 }
 827
 828 static void omap_gpio_ack_irq(struct irq_data *d)
 829 {
 830         struct gpio_bank *bank = omap_irq_data_get_bank(d);
 831         unsigned offset = d->hwirq;
 832
 833         omap_clear_gpio_irqstatus(bank, offset);
 834 }
 835
 836 static void omap_gpio_mask_irq(struct irq_data *d)
 837 {
 838         struct gpio_bank *bank = omap_irq_data_get_bank(d);
 839         unsigned offset = d->hwirq;
 840         unsigned long flags;
 841
 842         spin_lock_irqsave(&bank->lock, flags);
 843         omap_set_gpio_irqenable(bank, offset, 0);
 844         omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
 845         spin_unlock_irqrestore(&bank->lock, flags);
 846 }
 847
 848 static void omap_gpio_unmask_irq(struct irq_data *d)
 849 {
 850         struct gpio_bank *bank = omap_irq_data_get_bank(d);
 851         unsigned offset = d->hwirq;
 852         u32 trigger = irqd_get_trigger_type(d);
 853         unsigned long flags;
 854
 855         spin_lock_irqsave(&bank->lock, flags);
 856         if (trigger)
 857                 omap_set_gpio_triggering(bank, offset, trigger);
 858
 859         /* For level-triggered GPIOs, the clearing must be done after
 860          * the HW source is cleared, thus after the handler has run */
 861         if (bank->level_mask & BIT(offset)) {
 862                 omap_set_gpio_irqenable(bank, offset, 0);
 863                 omap_clear_gpio_irqstatus(bank, offset);
 864         }
 865
 866         omap_set_gpio_irqenable(bank, offset, 1);
 867         spin_unlock_irqrestore(&bank->lock, flags);
 868 }
 869
 870 /*---------------------------------------------------------------------*/
 871
 872 static int omap_mpuio_suspend_noirq(struct device *dev)
 873 {
 874         struct platform_device *pdev = to_platform_device(dev);
 875         struct gpio_bank        *bank = platform_get_drvdata(pdev);
 876         void __iomem            *mask_reg = bank->base +
 877                                         OMAP_MPUIO_GPIO_MASKIT / bank->stride;
 878         unsigned long           flags;
 879
 880         spin_lock_irqsave(&bank->lock, flags);
 881         writel_relaxed(0xffff & ~bank->context.wake_en, mask_reg);
 882         spin_unlock_irqrestore(&bank->lock, flags);
 883
 884         return 0;
 885 }
 886
 887 static int omap_mpuio_resume_noirq(struct device *dev)
 888 {
 889         struct platform_device *pdev = to_platform_device(dev);
 890         struct gpio_bank        *bank = platform_get_drvdata(pdev);
 891         void __iomem            *mask_reg = bank->base +
 892                                         OMAP_MPUIO_GPIO_MASKIT / bank->stride;
 893         unsigned long           flags;
 894
 895         spin_lock_irqsave(&bank->lock, flags);
 896         writel_relaxed(bank->context.wake_en, mask_reg);
 897         spin_unlock_irqrestore(&bank->lock, flags);
 898
 899         return 0;
 900 }
 901
 902 static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
 903         .suspend_noirq = omap_mpuio_suspend_noirq,
 904         .resume_noirq = omap_mpuio_resume_noirq,
 905 };
 906
 907 /* use platform_driver for this. */
 908 static struct platform_driver omap_mpuio_driver = {
 909         .driver         = {
 910                 .name   = "mpuio",
 911                 .pm     = &omap_mpuio_dev_pm_ops,
 912         },
 913 };
 914
 915 static struct platform_device omap_mpuio_device = {
 916         .name           = "mpuio",
 917         .id             = -1,
 918         .dev = {
 919                 .driver = &omap_mpuio_driver.driver,
 920         }
 921         /* could list the /proc/iomem resources */
 922 };
 923
 924 static inline void omap_mpuio_init(struct gpio_bank *bank)
 925 {
 926         platform_set_drvdata(&omap_mpuio_device, bank);
 927
 928         if (platform_driver_register(&omap_mpuio_driver) == 0)
 929                 (void) platform_device_register(&omap_mpuio_device);
 930 }
 931
 932 /*---------------------------------------------------------------------*/
 933
 934 static int omap_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
 935 {
 936         struct gpio_bank *bank;
 937         unsigned long flags;
 938         void __iomem *reg;
 939         int dir;
 940
 941         bank = container_of(chip, struct gpio_bank, chip);
 942         reg = bank->base + bank->regs->direction;
 943         spin_lock_irqsave(&bank->lock, flags);
 944         dir = !!(readl_relaxed(reg) & BIT(offset));
 945         spin_unlock_irqrestore(&bank->lock, flags);
 946         return dir;
 947 }
 948
 949 static int omap_gpio_input(struct gpio_chip *chip, unsigned offset)
 950 {
 951         struct gpio_bank *bank;
 952         unsigned long flags;
 953
 954         bank = container_of(chip, struct gpio_bank, chip);
 955         spin_lock_irqsave(&bank->lock, flags);
 956         omap_set_gpio_direction(bank, offset, 1);
 957         spin_unlock_irqrestore(&bank->lock, flags);
 958         return 0;
 959 }
 960
 961 static int omap_gpio_get(struct gpio_chip *chip, unsigned offset)
 962 {
 963         struct gpio_bank *bank;
 964
 965         bank = container_of(chip, struct gpio_bank, chip);
 966
 967         if (omap_gpio_is_input(bank, offset))
 968                 return omap_get_gpio_datain(bank, offset);
 969         else
 970                 return omap_get_gpio_dataout(bank, offset);
 971 }
 972
 973 static int omap_gpio_output(struct gpio_chip *chip, unsigned offset, int value)
 974 {
 975         struct gpio_bank *bank;
 976         unsigned long flags;
 977
 978         bank = container_of(chip, struct gpio_bank, chip);
 979         spin_lock_irqsave(&bank->lock, flags);
 980         bank->set_dataout(bank, offset, value);
 981         omap_set_gpio_direction(bank, offset, 0);
 982         spin_unlock_irqrestore(&bank->lock, flags);
 983         return 0;
 984 }
 985
 986 static int omap_gpio_debounce(struct gpio_chip *chip, unsigned offset,
 987                               unsigned debounce)
 988 {
 989         struct gpio_bank *bank;
 990         unsigned long flags;
 991
 992         bank = container_of(chip, struct gpio_bank, chip);
 993
 994         spin_lock_irqsave(&bank->lock, flags);
 995         omap2_set_gpio_debounce(bank, offset, debounce);
 996         spin_unlock_irqrestore(&bank->lock, flags);
 997
 998         return 0;
 999 }
1000
1001 static void omap_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1002 {
1003         struct gpio_bank *bank;
1004         unsigned long flags;
1005
1006         bank = container_of(chip, struct gpio_bank, chip);
1007         spin_lock_irqsave(&bank->lock, flags);
1008         bank->set_dataout(bank, offset, value);
1009         spin_unlock_irqrestore(&bank->lock, flags);
1010 }
1011
1012 /*---------------------------------------------------------------------*/
1013
1014 static void __init omap_gpio_show_rev(struct gpio_bank *bank)
1015 {
1016         static bool called;
1017         u32 rev;
1018
1019         if (called || bank->regs->revision == USHRT_MAX)
1020                 return;
1021
1022         rev = readw_relaxed(bank->base + bank->regs->revision);
1023         pr_info("OMAP GPIO hardware version %d.%d\n",
1024                 (rev >> 4) & 0x0f, rev & 0x0f);
1025
1026         called = true;
1027 }
1028
1029 static void omap_gpio_mod_init(struct gpio_bank *bank)
1030 {
1031         void __iomem *base = bank->base;
1032         u32 l = 0xffffffff;
1033
1034         if (bank->width == 16)
1035                 l = 0xffff;
1036
1037         if (bank->is_mpuio) {
1038                 writel_relaxed(l, bank->base + bank->regs->irqenable);
1039                 return;
1040         }
1041
1042         omap_gpio_rmw(base, bank->regs->irqenable, l,
1043                       bank->regs->irqenable_inv);
1044         omap_gpio_rmw(base, bank->regs->irqstatus, l,
1045                       !bank->regs->irqenable_inv);
1046         if (bank->regs->debounce_en)
1047                 writel_relaxed(0, base + bank->regs->debounce_en);
1048
1049         /* Save OE default value (0xffffffff) in the context */
1050         bank->context.oe = readl_relaxed(bank->base + bank->regs->direction);
1051          /* Initialize interface clk ungated, module enabled */
1052         if (bank->regs->ctrl)
1053                 writel_relaxed(0, base + bank->regs->ctrl);
1054
1055         bank->dbck = clk_get(bank->dev, "dbclk");
1056         if (IS_ERR(bank->dbck))
1057                 dev_err(bank->dev, "Could not get gpio dbck\n");
1058 }
1059
1060 static int omap_gpio_chip_init(struct gpio_bank *bank, struct irq_chip *irqc)
1061 {
1062         static int gpio;
1063         int irq_base = 0;
1064         int ret;
1065
1066         /*
1067          * REVISIT eventually switch from OMAP-specific gpio structs
1068          * over to the generic ones
1069          */
1070         bank->chip.request = omap_gpio_request;
1071         bank->chip.free = omap_gpio_free;
1072         bank->chip.get_direction = omap_gpio_get_direction;
1073         bank->chip.direction_input = omap_gpio_input;
1074         bank->chip.get = omap_gpio_get;
1075         bank->chip.direction_output = omap_gpio_output;
1076         bank->chip.set_debounce = omap_gpio_debounce;
1077         bank->chip.set = omap_gpio_set;
1078         if (bank->is_mpuio) {
1079                 bank->chip.label = "mpuio";
1080                 if (bank->regs->wkup_en)
1081                         bank->chip.dev = &omap_mpuio_device.dev;
1082                 bank->chip.base = OMAP_MPUIO(0);
1083         } else {
1084                 bank->chip.label = "gpio";
1085                 bank->chip.base = gpio;
1086                 gpio += bank->width;
1087         }
1088         bank->chip.ngpio = bank->width;
1089
1090         ret = gpiochip_add(&bank->chip);
1091         if (ret) {
1092                 dev_err(bank->dev, "Could not register gpio chip %d\n", ret);
1093                 return ret;
1094         }
1095
1096 #ifdef CONFIG_ARCH_OMAP1
1097         /*
1098          * REVISIT: Once we have OMAP1 supporting SPARSE_IRQ, we can drop
1099          * irq_alloc_descs() since a base IRQ offset will no longer be needed.
1100          */
1101         irq_base = irq_alloc_descs(-1, 0, bank->width, 0);
1102         if (irq_base < 0) {
1103                 dev_err(bank->dev, "Couldn't allocate IRQ numbers\n");
1104                 return -ENODEV;
1105         }
1106 #endif
1107
1108         /* MPUIO is a bit different, reading IRQ status clears it */
1109         if (bank->is_mpuio) {
1110                 irqc->irq_ack = dummy_irq_chip.irq_ack;
1111                 irqc->irq_mask = irq_gc_mask_set_bit;
1112                 irqc->irq_unmask = irq_gc_mask_clr_bit;
1113                 if (!bank->regs->wkup_en)
1114                         irqc->irq_set_wake = NULL;
1115         }
1116
1117         ret = gpiochip_irqchip_add(&bank->chip, irqc,
1118                                    irq_base, omap_gpio_irq_handler,
1119                                    IRQ_TYPE_NONE);
1120
1121         if (ret) {
1122                 dev_err(bank->dev, "Couldn't add irqchip to gpiochip %d\n", ret);
1123                 gpiochip_remove(&bank->chip);
1124                 return -ENODEV;
1125         }
1126
1127         gpiochip_set_chained_irqchip(&bank->chip, irqc,
1128                                      bank->irq, omap_gpio_irq_handler);
1129
1130         return 0;
1131 }
1132
1133 static const struct of_device_id omap_gpio_match[];
1134
1135 static int omap_gpio_probe(struct platform_device *pdev)
1136 {
1137         struct device *dev = &pdev->dev;
1138         struct device_node *node = dev->of_node;
1139         const struct of_device_id *match;
1140         const struct omap_gpio_platform_data *pdata;
1141         struct resource *res;
1142         struct gpio_bank *bank;
1143         struct irq_chip *irqc;
1144         int ret;
1145
1146         match = of_match_device(of_match_ptr(omap_gpio_match), dev);
1147
1148         pdata = match ? match->data : dev_get_platdata(dev);
1149         if (!pdata)
1150                 return -EINVAL;
1151
1152         bank = devm_kzalloc(dev, sizeof(struct gpio_bank), GFP_KERNEL);
1153         if (!bank) {
1154                 dev_err(dev, "Memory alloc failed\n");
1155                 return -ENOMEM;
1156         }
1157
1158         irqc = devm_kzalloc(dev, sizeof(*irqc), GFP_KERNEL);
1159         if (!irqc)
1160                 return -ENOMEM;
1161
1162         irqc->irq_startup = omap_gpio_irq_startup,
1163         irqc->irq_shutdown = omap_gpio_irq_shutdown,
1164         irqc->irq_ack = omap_gpio_ack_irq,
1165         irqc->irq_mask = omap_gpio_mask_irq,
1166         irqc->irq_unmask = omap_gpio_unmask_irq,
1167         irqc->irq_set_type = omap_gpio_irq_type,
1168         irqc->irq_set_wake = omap_gpio_wake_enable,
1169         irqc->name = dev_name(&pdev->dev);
1170
1171         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1172         if (unlikely(!res)) {
1173                 dev_err(dev, "Invalid IRQ resource\n");
1174                 return -ENODEV;
1175         }
1176
1177         bank->irq = res->start;
1178         bank->dev = dev;
1179         bank->chip.dev = dev;
1180         bank->dbck_flag = pdata->dbck_flag;
1181         bank->stride = pdata->bank_stride;
1182         bank->width = pdata->bank_width;
1183         bank->is_mpuio = pdata->is_mpuio;
1184         bank->non_wakeup_gpios = pdata->non_wakeup_gpios;
1185         bank->regs = pdata->regs;
1186 #ifdef CONFIG_OF_GPIO
1187         bank->chip.of_node = of_node_get(node);
1188 #endif
1189         if (node) {
1190                 if (!of_property_read_bool(node, "ti,gpio-always-on"))
1191                         bank->loses_context = true;
1192         } else {
1193                 bank->loses_context = pdata->loses_context;
1194
1195                 if (bank->loses_context)
1196                         bank->get_context_loss_count =
1197                                 pdata->get_context_loss_count;
1198         }
1199
1200         if (bank->regs->set_dataout && bank->regs->clr_dataout)
1201                 bank->set_dataout = omap_set_gpio_dataout_reg;
1202         else
1203                 bank->set_dataout = omap_set_gpio_dataout_mask;
1204
1205         spin_lock_init(&bank->lock);
1206
1207         /* Static mapping, never released */
1208         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1209         bank->base = devm_ioremap_resource(dev, res);
1210         if (IS_ERR(bank->base)) {
1211                 irq_domain_remove(bank->chip.irqdomain);
1212                 return PTR_ERR(bank->base);
1213         }
1214
1215         platform_set_drvdata(pdev, bank);
1216
1217         pm_runtime_enable(bank->dev);
1218         pm_runtime_irq_safe(bank->dev);
1219         pm_runtime_get_sync(bank->dev);
1220
1221         if (bank->is_mpuio)
1222                 omap_mpuio_init(bank);
1223
1224         omap_gpio_mod_init(bank);
1225
1226         ret = omap_gpio_chip_init(bank, irqc);
1227         if (ret)
1228                 return ret;
1229
1230         omap_gpio_show_rev(bank);
1231
1232         pm_runtime_put(bank->dev);
1233
1234         list_add_tail(&bank->node, &omap_gpio_list);
1235
1236         return 0;
1237 }
1238
1239 static int omap_gpio_remove(struct platform_device *pdev)
1240 {
1241         struct gpio_bank *bank = platform_get_drvdata(pdev);
1242
1243         list_del(&bank->node);
1244         gpiochip_remove(&bank->chip);
1245         pm_runtime_disable(bank->dev);
1246
1247         return 0;
1248 }
1249
1250 #ifdef CONFIG_ARCH_OMAP2PLUS
1251
1252 #if defined(CONFIG_PM)
1253 static void omap_gpio_restore_context(struct gpio_bank *bank);
1254
1255 static int omap_gpio_runtime_suspend(struct device *dev)
1256 {
1257         struct platform_device *pdev = to_platform_device(dev);
1258         struct gpio_bank *bank = platform_get_drvdata(pdev);
1259         u32 l1 = 0, l2 = 0;
1260         unsigned long flags;
1261         u32 wake_low, wake_hi;
1262
1263         spin_lock_irqsave(&bank->lock, flags);
1264
1265         /*
1266          * Only edges can generate a wakeup event to the PRCM.
1267          *
1268          * Therefore, ensure any wake-up capable GPIOs have
1269          * edge-detection enabled before going idle to ensure a wakeup
1270          * to the PRCM is generated on a GPIO transition. (c.f. 34xx
1271          * NDA TRM 25.5.3.1)
1272          *
1273          * The normal values will be restored upon ->runtime_resume()
1274          * by writing back the values saved in bank->context.
1275          */
1276         wake_low = bank->context.leveldetect0 & bank->context.wake_en;
1277         if (wake_low)
1278                 writel_relaxed(wake_low | bank->context.fallingdetect,
1279                              bank->base + bank->regs->fallingdetect);
1280         wake_hi = bank->context.leveldetect1 & bank->context.wake_en;
1281         if (wake_hi)
1282                 writel_relaxed(wake_hi | bank->context.risingdetect,
1283                              bank->base + bank->regs->risingdetect);
1284
1285         if (!bank->enabled_non_wakeup_gpios)
1286                 goto update_gpio_context_count;
1287
1288         if (bank->power_mode != OFF_MODE) {
1289                 bank->power_mode = 0;
1290                 goto update_gpio_context_count;
1291         }
1292         /*
1293          * If going to OFF, remove triggering for all
1294          * non-wakeup GPIOs.  Otherwise spurious IRQs will be
1295          * generated.  See OMAP2420 Errata item 1.101.
1296          */
1297         bank->saved_datain = readl_relaxed(bank->base +
1298                                                 bank->regs->datain);
1299         l1 = bank->context.fallingdetect;
1300         l2 = bank->context.risingdetect;
1301
1302         l1 &= ~bank->enabled_non_wakeup_gpios;
1303         l2 &= ~bank->enabled_non_wakeup_gpios;
1304
1305         writel_relaxed(l1, bank->base + bank->regs->fallingdetect);
1306         writel_relaxed(l2, bank->base + bank->regs->risingdetect);
1307
1308         bank->workaround_enabled = true;
1309
1310 update_gpio_context_count:
1311         if (bank->get_context_loss_count)
1312                 bank->context_loss_count =
1313                                 bank->get_context_loss_count(bank->dev);
1314
1315         omap_gpio_dbck_disable(bank);
1316         spin_unlock_irqrestore(&bank->lock, flags);
1317
1318         return 0;
1319 }
1320
1321 static void omap_gpio_init_context(struct gpio_bank *p);
1322
1323 static int omap_gpio_runtime_resume(struct device *dev)
1324 {
1325         struct platform_device *pdev = to_platform_device(dev);
1326         struct gpio_bank *bank = platform_get_drvdata(pdev);
1327         u32 l = 0, gen, gen0, gen1;
1328         unsigned long flags;
1329         int c;
1330
1331         spin_lock_irqsave(&bank->lock, flags);
1332
1333         /*
1334          * On the first resume during the probe, the context has not
1335          * been initialised and so initialise it now. Also initialise
1336          * the context loss count.
1337          */
1338         if (bank->loses_context && !bank->context_valid) {
1339                 omap_gpio_init_context(bank);
1340
1341                 if (bank->get_context_loss_count)
1342                         bank->context_loss_count =
1343                                 bank->get_context_loss_count(bank->dev);
1344         }
1345
1346         omap_gpio_dbck_enable(bank);
1347
1348         /*
1349          * In ->runtime_suspend(), level-triggered, wakeup-enabled
1350          * GPIOs were set to edge trigger also in order to be able to
1351          * generate a PRCM wakeup.  Here we restore the
1352          * pre-runtime_suspend() values for edge triggering.
1353          */
1354         writel_relaxed(bank->context.fallingdetect,
1355                      bank->base + bank->regs->fallingdetect);
1356         writel_relaxed(bank->context.risingdetect,
1357                      bank->base + bank->regs->risingdetect);
1358
1359         if (bank->loses_context) {
1360                 if (!bank->get_context_loss_count) {
1361                         omap_gpio_restore_context(bank);
1362                 } else {
1363                         c = bank->get_context_loss_count(bank->dev);
1364                         if (c != bank->context_loss_count) {
1365                                 omap_gpio_restore_context(bank);
1366                         } else {
1367                                 spin_unlock_irqrestore(&bank->lock, flags);
1368                                 return 0;
1369                         }
1370                 }
1371         }
1372
1373         if (!bank->workaround_enabled) {
1374                 spin_unlock_irqrestore(&bank->lock, flags);
1375                 return 0;
1376         }
1377
1378         l = readl_relaxed(bank->base + bank->regs->datain);
1379
1380         /*
1381          * Check if any of the non-wakeup interrupt GPIOs have changed
1382          * state.  If so, generate an IRQ by software.  This is
1383          * horribly racy, but it's the best we can do to work around
1384          * this silicon bug.
1385          */
1386         l ^= bank->saved_datain;
1387         l &= bank->enabled_non_wakeup_gpios;
1388
1389         /*
1390          * No need to generate IRQs for the rising edge for gpio IRQs
1391          * configured with falling edge only; and vice versa.
1392          */
1393         gen0 = l & bank->context.fallingdetect;
1394         gen0 &= bank->saved_datain;
1395
1396         gen1 = l & bank->context.risingdetect;
1397         gen1 &= ~(bank->saved_datain);
1398
1399         /* FIXME: Consider GPIO IRQs with level detections properly! */
1400         gen = l & (~(bank->context.fallingdetect) &
1401                                          ~(bank->context.risingdetect));
1402         /* Consider all GPIO IRQs needed to be updated */
1403         gen |= gen0 | gen1;
1404
1405         if (gen) {
1406                 u32 old0, old1;
1407
1408                 old0 = readl_relaxed(bank->base + bank->regs->leveldetect0);
1409                 old1 = readl_relaxed(bank->base + bank->regs->leveldetect1);
1410
1411                 if (!bank->regs->irqstatus_raw0) {
1412                         writel_relaxed(old0 | gen, bank->base +
1413                                                 bank->regs->leveldetect0);
1414                         writel_relaxed(old1 | gen, bank->base +
1415                                                 bank->regs->leveldetect1);
1416                 }
1417
1418                 if (bank->regs->irqstatus_raw0) {
1419                         writel_relaxed(old0 | l, bank->base +
1420                                                 bank->regs->leveldetect0);
1421                         writel_relaxed(old1 | l, bank->base +
1422                                                 bank->regs->leveldetect1);
1423                 }
1424                 writel_relaxed(old0, bank->base + bank->regs->leveldetect0);
1425                 writel_relaxed(old1, bank->base + bank->regs->leveldetect1);
1426         }
1427
1428         bank->workaround_enabled = false;
1429         spin_unlock_irqrestore(&bank->lock, flags);
1430
1431         return 0;
1432 }
1433 #endif /* CONFIG_PM */
1434
1435 #if IS_BUILTIN(CONFIG_GPIO_OMAP)
1436 void omap2_gpio_prepare_for_idle(int pwr_mode)
1437 {
1438         struct gpio_bank *bank;
1439
1440         list_for_each_entry(bank, &omap_gpio_list, node) {
1441                 if (!BANK_USED(bank) || !bank->loses_context)
1442                         continue;
1443
1444                 bank->power_mode = pwr_mode;
1445
1446                 pm_runtime_put_sync_suspend(bank->dev);
1447         }
1448 }
1449
1450 void omap2_gpio_resume_after_idle(void)
1451 {
1452         struct gpio_bank *bank;
1453
1454         list_for_each_entry(bank, &omap_gpio_list, node) {
1455                 if (!BANK_USED(bank) || !bank->loses_context)
1456                         continue;
1457
1458                 pm_runtime_get_sync(bank->dev);
1459         }
1460 }
1461 #endif
1462
1463 #if defined(CONFIG_PM)
1464 static void omap_gpio_init_context(struct gpio_bank *p)
1465 {
1466         struct omap_gpio_reg_offs *regs = p->regs;
1467         void __iomem *base = p->base;
1468
1469         p->context.ctrl         = readl_relaxed(base + regs->ctrl);
1470         p->context.oe           = readl_relaxed(base + regs->direction);
1471         p->context.wake_en      = readl_relaxed(base + regs->wkup_en);
1472         p->context.leveldetect0 = readl_relaxed(base + regs->leveldetect0);
1473         p->context.leveldetect1 = readl_relaxed(base + regs->leveldetect1);
1474         p->context.risingdetect = readl_relaxed(base + regs->risingdetect);
1475         p->context.fallingdetect = readl_relaxed(base + regs->fallingdetect);
1476         p->context.irqenable1   = readl_relaxed(base + regs->irqenable);
1477         p->context.irqenable2   = readl_relaxed(base + regs->irqenable2);
1478
1479         if (regs->set_dataout && p->regs->clr_dataout)
1480                 p->context.dataout = readl_relaxed(base + regs->set_dataout);
1481         else
1482                 p->context.dataout = readl_relaxed(base + regs->dataout);
1483
1484         p->context_valid = true;
1485 }
1486
1487 static void omap_gpio_restore_context(struct gpio_bank *bank)
1488 {
1489         writel_relaxed(bank->context.wake_en,
1490                                 bank->base + bank->regs->wkup_en);
1491         writel_relaxed(bank->context.ctrl, bank->base + bank->regs->ctrl);
1492         writel_relaxed(bank->context.leveldetect0,
1493                                 bank->base + bank->regs->leveldetect0);
1494         writel_relaxed(bank->context.leveldetect1,
1495                                 bank->base + bank->regs->leveldetect1);
1496         writel_relaxed(bank->context.risingdetect,
1497                                 bank->base + bank->regs->risingdetect);
1498         writel_relaxed(bank->context.fallingdetect,
1499                                 bank->base + bank->regs->fallingdetect);
1500         if (bank->regs->set_dataout && bank->regs->clr_dataout)
1501                 writel_relaxed(bank->context.dataout,
1502                                 bank->base + bank->regs->set_dataout);
1503         else
1504                 writel_relaxed(bank->context.dataout,
1505                                 bank->base + bank->regs->dataout);
1506         writel_relaxed(bank->context.oe, bank->base + bank->regs->direction);
1507
1508         if (bank->dbck_enable_mask) {
1509                 writel_relaxed(bank->context.debounce, bank->base +
1510                                         bank->regs->debounce);
1511                 writel_relaxed(bank->context.debounce_en,
1512                                         bank->base + bank->regs->debounce_en);
1513         }
1514
1515         writel_relaxed(bank->context.irqenable1,
1516                                 bank->base + bank->regs->irqenable);
1517         writel_relaxed(bank->context.irqenable2,
1518                                 bank->base + bank->regs->irqenable2);
1519 }
1520 #endif /* CONFIG_PM */
1521 #else
1522 #define omap_gpio_runtime_suspend NULL
1523 #define omap_gpio_runtime_resume NULL
1524 static inline void omap_gpio_init_context(struct gpio_bank *p) {}
1525 #endif
1526
1527 static const struct dev_pm_ops gpio_pm_ops = {
1528         SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume,
1529                                                                         NULL)
1530 };
1531
1532 #if defined(CONFIG_OF)
1533 static struct omap_gpio_reg_offs omap2_gpio_regs = {
1534         .revision =             OMAP24XX_GPIO_REVISION,
1535         .direction =            OMAP24XX_GPIO_OE,
1536         .datain =               OMAP24XX_GPIO_DATAIN,
1537         .dataout =              OMAP24XX_GPIO_DATAOUT,
1538         .set_dataout =          OMAP24XX_GPIO_SETDATAOUT,
1539         .clr_dataout =          OMAP24XX_GPIO_CLEARDATAOUT,
1540         .irqstatus =            OMAP24XX_GPIO_IRQSTATUS1,
1541         .irqstatus2 =           OMAP24XX_GPIO_IRQSTATUS2,
1542         .irqenable =            OMAP24XX_GPIO_IRQENABLE1,
1543         .irqenable2 =           OMAP24XX_GPIO_IRQENABLE2,
1544         .set_irqenable =        OMAP24XX_GPIO_SETIRQENABLE1,
1545         .clr_irqenable =        OMAP24XX_GPIO_CLEARIRQENABLE1,
1546         .debounce =             OMAP24XX_GPIO_DEBOUNCE_VAL,
1547         .debounce_en =          OMAP24XX_GPIO_DEBOUNCE_EN,
1548         .ctrl =                 OMAP24XX_GPIO_CTRL,
1549         .wkup_en =              OMAP24XX_GPIO_WAKE_EN,
1550         .leveldetect0 =         OMAP24XX_GPIO_LEVELDETECT0,
1551         .leveldetect1 =         OMAP24XX_GPIO_LEVELDETECT1,
1552         .risingdetect =         OMAP24XX_GPIO_RISINGDETECT,
1553         .fallingdetect =        OMAP24XX_GPIO_FALLINGDETECT,
1554 };
1555
1556 static struct omap_gpio_reg_offs omap4_gpio_regs = {
1557         .revision =             OMAP4_GPIO_REVISION,
1558         .direction =            OMAP4_GPIO_OE,
1559         .datain =               OMAP4_GPIO_DATAIN,
1560         .dataout =              OMAP4_GPIO_DATAOUT,
1561         .set_dataout =          OMAP4_GPIO_SETDATAOUT,
1562         .clr_dataout =          OMAP4_GPIO_CLEARDATAOUT,
1563         .irqstatus =            OMAP4_GPIO_IRQSTATUS0,
1564         .irqstatus2 =           OMAP4_GPIO_IRQSTATUS1,
1565         .irqenable =            OMAP4_GPIO_IRQSTATUSSET0,
1566         .irqenable2 =           OMAP4_GPIO_IRQSTATUSSET1,
1567         .set_irqenable =        OMAP4_GPIO_IRQSTATUSSET0,
1568         .clr_irqenable =        OMAP4_GPIO_IRQSTATUSCLR0,
1569         .debounce =             OMAP4_GPIO_DEBOUNCINGTIME,
1570         .debounce_en =          OMAP4_GPIO_DEBOUNCENABLE,
1571         .ctrl =                 OMAP4_GPIO_CTRL,
1572         .wkup_en =              OMAP4_GPIO_IRQWAKEN0,
1573         .leveldetect0 =         OMAP4_GPIO_LEVELDETECT0,
1574         .leveldetect1 =         OMAP4_GPIO_LEVELDETECT1,
1575         .risingdetect =         OMAP4_GPIO_RISINGDETECT,
1576         .fallingdetect =        OMAP4_GPIO_FALLINGDETECT,
1577 };
1578
1579 static const struct omap_gpio_platform_data omap2_pdata = {
1580         .regs = &omap2_gpio_regs,
1581         .bank_width = 32,
1582         .dbck_flag = false,
1583 };
1584
1585 static const struct omap_gpio_platform_data omap3_pdata = {
1586         .regs = &omap2_gpio_regs,
1587         .bank_width = 32,
1588         .dbck_flag = true,
1589 };
1590
1591 static const struct omap_gpio_platform_data omap4_pdata = {
1592         .regs = &omap4_gpio_regs,
1593         .bank_width = 32,
1594         .dbck_flag = true,
1595 };
1596
1597 static const struct of_device_id omap_gpio_match[] = {
1598         {
1599                 .compatible = "ti,omap4-gpio",
1600                 .data = &omap4_pdata,
1601         },
1602         {
1603                 .compatible = "ti,omap3-gpio",
1604                 .data = &omap3_pdata,
1605         },
1606         {
1607                 .compatible = "ti,omap2-gpio",
1608                 .data = &omap2_pdata,
1609         },
1610         { },
1611 };
1612 MODULE_DEVICE_TABLE(of, omap_gpio_match);
1613 #endif
1614
1615 static struct platform_driver omap_gpio_driver = {
1616         .probe          = omap_gpio_probe,
1617         .remove         = omap_gpio_remove,
1618         .driver         = {
1619                 .name   = "omap_gpio",
1620                 .pm     = &gpio_pm_ops,
1621                 .of_match_table = of_match_ptr(omap_gpio_match),
1622         },
1623 };
1624
1625 /*
1626  * gpio driver register needs to be done before
1627  * machine_init functions access gpio APIs.
1628  * Hence omap_gpio_drv_reg() is a postcore_initcall.
1629  */
1630 static int __init omap_gpio_drv_reg(void)
1631 {
1632         return platform_driver_register(&omap_gpio_driver);
1633 }
1634 postcore_initcall(omap_gpio_drv_reg);
1635
1636 static void __exit omap_gpio_exit(void)
1637 {
1638         platform_driver_unregister(&omap_gpio_driver);
1639 }
1640 module_exit(omap_gpio_exit);
1641
1642 MODULE_DESCRIPTION("omap gpio driver");
1643 MODULE_ALIAS("platform:gpio-omap");
1644 MODULE_LICENSE("GPL v2");