2 * Renesas R-Car GPIO Support
4 * Copyright (C) 2014 Renesas Electronics Corporation
5 * Copyright (C) 2013 Magnus Damm
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/err.h>
18 #include <linux/gpio.h>
19 #include <linux/init.h>
20 #include <linux/interrupt.h>
22 #include <linux/ioport.h>
23 #include <linux/irq.h>
24 #include <linux/module.h>
26 #include <linux/of_device.h>
27 #include <linux/pinctrl/consumer.h>
28 #include <linux/platform_device.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/spinlock.h>
31 #include <linux/slab.h>
33 struct gpio_rcar_bank_info {
43 struct gpio_rcar_priv {
46 struct platform_device *pdev;
47 struct gpio_chip gpio_chip;
48 struct irq_chip irq_chip;
49 unsigned int irq_parent;
51 bool has_both_edge_trigger;
52 struct gpio_rcar_bank_info bank_info;
55 #define IOINTSEL 0x00 /* General IO/Interrupt Switching Register */
56 #define INOUTSEL 0x04 /* General Input/Output Switching Register */
57 #define OUTDT 0x08 /* General Output Register */
58 #define INDT 0x0c /* General Input Register */
59 #define INTDT 0x10 /* Interrupt Display Register */
60 #define INTCLR 0x14 /* Interrupt Clear Register */
61 #define INTMSK 0x18 /* Interrupt Mask Register */
62 #define MSKCLR 0x1c /* Interrupt Mask Clear Register */
63 #define POSNEG 0x20 /* Positive/Negative Logic Select Register */
64 #define EDGLEVEL 0x24 /* Edge/level Select Register */
65 #define FILONOFF 0x28 /* Chattering Prevention On/Off Register */
66 #define BOTHEDGE 0x4c /* One Edge/Both Edge Select Register */
68 #define RCAR_MAX_GPIO_PER_BANK 32
70 static inline u32 gpio_rcar_read(struct gpio_rcar_priv *p, int offs)
72 return ioread32(p->base + offs);
75 static inline void gpio_rcar_write(struct gpio_rcar_priv *p, int offs,
78 iowrite32(value, p->base + offs);
81 static void gpio_rcar_modify_bit(struct gpio_rcar_priv *p, int offs,
84 u32 tmp = gpio_rcar_read(p, offs);
91 gpio_rcar_write(p, offs, tmp);
94 static void gpio_rcar_irq_disable(struct irq_data *d)
96 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
97 struct gpio_rcar_priv *p = gpiochip_get_data(gc);
99 gpio_rcar_write(p, INTMSK, ~BIT(irqd_to_hwirq(d)));
102 static void gpio_rcar_irq_enable(struct irq_data *d)
104 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
105 struct gpio_rcar_priv *p = gpiochip_get_data(gc);
107 gpio_rcar_write(p, MSKCLR, BIT(irqd_to_hwirq(d)));
110 static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p,
112 bool active_high_rising_edge,
118 /* follow steps in the GPIO documentation for
119 * "Setting Edge-Sensitive Interrupt Input Mode" and
120 * "Setting Level-Sensitive Interrupt Input Mode"
123 spin_lock_irqsave(&p->lock, flags);
125 /* Configure postive or negative logic in POSNEG */
126 gpio_rcar_modify_bit(p, POSNEG, hwirq, !active_high_rising_edge);
128 /* Configure edge or level trigger in EDGLEVEL */
129 gpio_rcar_modify_bit(p, EDGLEVEL, hwirq, !level_trigger);
131 /* Select one edge or both edges in BOTHEDGE */
132 if (p->has_both_edge_trigger)
133 gpio_rcar_modify_bit(p, BOTHEDGE, hwirq, both);
135 /* Select "Interrupt Input Mode" in IOINTSEL */
136 gpio_rcar_modify_bit(p, IOINTSEL, hwirq, true);
138 /* Write INTCLR in case of edge trigger */
140 gpio_rcar_write(p, INTCLR, BIT(hwirq));
142 spin_unlock_irqrestore(&p->lock, flags);
145 static int gpio_rcar_irq_set_type(struct irq_data *d, unsigned int type)
147 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
148 struct gpio_rcar_priv *p = gpiochip_get_data(gc);
149 unsigned int hwirq = irqd_to_hwirq(d);
151 dev_dbg(&p->pdev->dev, "sense irq = %d, type = %d\n", hwirq, type);
153 switch (type & IRQ_TYPE_SENSE_MASK) {
154 case IRQ_TYPE_LEVEL_HIGH:
155 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true,
158 case IRQ_TYPE_LEVEL_LOW:
159 gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true,
162 case IRQ_TYPE_EDGE_RISING:
163 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
166 case IRQ_TYPE_EDGE_FALLING:
167 gpio_rcar_config_interrupt_input_mode(p, hwirq, false, false,
170 case IRQ_TYPE_EDGE_BOTH:
171 if (!p->has_both_edge_trigger)
173 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
182 static int gpio_rcar_irq_set_wake(struct irq_data *d, unsigned int on)
184 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
185 struct gpio_rcar_priv *p = gpiochip_get_data(gc);
189 error = irq_set_irq_wake(p->irq_parent, on);
191 dev_dbg(&p->pdev->dev,
192 "irq %u doesn't support irq_set_wake\n",
199 atomic_inc(&p->wakeup_path);
201 atomic_dec(&p->wakeup_path);
206 static irqreturn_t gpio_rcar_irq_handler(int irq, void *dev_id)
208 struct gpio_rcar_priv *p = dev_id;
210 unsigned int offset, irqs_handled = 0;
212 while ((pending = gpio_rcar_read(p, INTDT) &
213 gpio_rcar_read(p, INTMSK))) {
214 offset = __ffs(pending);
215 gpio_rcar_write(p, INTCLR, BIT(offset));
216 generic_handle_irq(irq_find_mapping(p->gpio_chip.irq.domain,
221 return irqs_handled ? IRQ_HANDLED : IRQ_NONE;
224 static void gpio_rcar_config_general_input_output_mode(struct gpio_chip *chip,
228 struct gpio_rcar_priv *p = gpiochip_get_data(chip);
231 /* follow steps in the GPIO documentation for
232 * "Setting General Output Mode" and
233 * "Setting General Input Mode"
236 spin_lock_irqsave(&p->lock, flags);
238 /* Configure postive logic in POSNEG */
239 gpio_rcar_modify_bit(p, POSNEG, gpio, false);
241 /* Select "General Input/Output Mode" in IOINTSEL */
242 gpio_rcar_modify_bit(p, IOINTSEL, gpio, false);
244 /* Select Input Mode or Output Mode in INOUTSEL */
245 gpio_rcar_modify_bit(p, INOUTSEL, gpio, output);
247 spin_unlock_irqrestore(&p->lock, flags);
250 static int gpio_rcar_request(struct gpio_chip *chip, unsigned offset)
252 struct gpio_rcar_priv *p = gpiochip_get_data(chip);
255 error = pm_runtime_get_sync(&p->pdev->dev);
259 error = pinctrl_gpio_request(chip->base + offset);
261 pm_runtime_put(&p->pdev->dev);
266 static void gpio_rcar_free(struct gpio_chip *chip, unsigned offset)
268 struct gpio_rcar_priv *p = gpiochip_get_data(chip);
270 pinctrl_gpio_free(chip->base + offset);
273 * Set the GPIO as an input to ensure that the next GPIO request won't
274 * drive the GPIO pin as an output.
276 gpio_rcar_config_general_input_output_mode(chip, offset, false);
278 pm_runtime_put(&p->pdev->dev);
281 static int gpio_rcar_direction_input(struct gpio_chip *chip, unsigned offset)
283 gpio_rcar_config_general_input_output_mode(chip, offset, false);
287 static int gpio_rcar_get(struct gpio_chip *chip, unsigned offset)
289 u32 bit = BIT(offset);
291 /* testing on r8a7790 shows that INDT does not show correct pin state
292 * when configured as output, so use OUTDT in case of output pins */
293 if (gpio_rcar_read(gpiochip_get_data(chip), INOUTSEL) & bit)
294 return !!(gpio_rcar_read(gpiochip_get_data(chip), OUTDT) & bit);
296 return !!(gpio_rcar_read(gpiochip_get_data(chip), INDT) & bit);
299 static void gpio_rcar_set(struct gpio_chip *chip, unsigned offset, int value)
301 struct gpio_rcar_priv *p = gpiochip_get_data(chip);
304 spin_lock_irqsave(&p->lock, flags);
305 gpio_rcar_modify_bit(p, OUTDT, offset, value);
306 spin_unlock_irqrestore(&p->lock, flags);
309 static void gpio_rcar_set_multiple(struct gpio_chip *chip, unsigned long *mask,
312 struct gpio_rcar_priv *p = gpiochip_get_data(chip);
316 bankmask = mask[0] & GENMASK(chip->ngpio - 1, 0);
320 spin_lock_irqsave(&p->lock, flags);
321 val = gpio_rcar_read(p, OUTDT);
323 val |= (bankmask & bits[0]);
324 gpio_rcar_write(p, OUTDT, val);
325 spin_unlock_irqrestore(&p->lock, flags);
328 static int gpio_rcar_direction_output(struct gpio_chip *chip, unsigned offset,
331 /* write GPIO value to output before selecting output mode of pin */
332 gpio_rcar_set(chip, offset, value);
333 gpio_rcar_config_general_input_output_mode(chip, offset, true);
337 struct gpio_rcar_info {
338 bool has_both_edge_trigger;
341 static const struct gpio_rcar_info gpio_rcar_info_gen1 = {
342 .has_both_edge_trigger = false,
345 static const struct gpio_rcar_info gpio_rcar_info_gen2 = {
346 .has_both_edge_trigger = true,
349 static const struct of_device_id gpio_rcar_of_table[] = {
351 .compatible = "renesas,gpio-r8a7743",
352 /* RZ/G1 GPIO is identical to R-Car Gen2. */
353 .data = &gpio_rcar_info_gen2,
355 .compatible = "renesas,gpio-r8a7790",
356 .data = &gpio_rcar_info_gen2,
358 .compatible = "renesas,gpio-r8a7791",
359 .data = &gpio_rcar_info_gen2,
361 .compatible = "renesas,gpio-r8a7792",
362 .data = &gpio_rcar_info_gen2,
364 .compatible = "renesas,gpio-r8a7793",
365 .data = &gpio_rcar_info_gen2,
367 .compatible = "renesas,gpio-r8a7794",
368 .data = &gpio_rcar_info_gen2,
370 .compatible = "renesas,gpio-r8a7795",
371 /* Gen3 GPIO is identical to Gen2. */
372 .data = &gpio_rcar_info_gen2,
374 .compatible = "renesas,gpio-r8a7796",
375 /* Gen3 GPIO is identical to Gen2. */
376 .data = &gpio_rcar_info_gen2,
378 .compatible = "renesas,rcar-gen1-gpio",
379 .data = &gpio_rcar_info_gen1,
381 .compatible = "renesas,rcar-gen2-gpio",
382 .data = &gpio_rcar_info_gen2,
384 .compatible = "renesas,rcar-gen3-gpio",
385 /* Gen3 GPIO is identical to Gen2. */
386 .data = &gpio_rcar_info_gen2,
388 .compatible = "renesas,gpio-rcar",
389 .data = &gpio_rcar_info_gen1,
395 MODULE_DEVICE_TABLE(of, gpio_rcar_of_table);
397 static int gpio_rcar_parse_dt(struct gpio_rcar_priv *p, unsigned int *npins)
399 struct device_node *np = p->pdev->dev.of_node;
400 const struct gpio_rcar_info *info;
401 struct of_phandle_args args;
404 info = of_device_get_match_data(&p->pdev->dev);
406 ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &args);
407 *npins = ret == 0 ? args.args[2] : RCAR_MAX_GPIO_PER_BANK;
408 p->has_both_edge_trigger = info->has_both_edge_trigger;
410 if (*npins == 0 || *npins > RCAR_MAX_GPIO_PER_BANK) {
411 dev_warn(&p->pdev->dev,
412 "Invalid number of gpio lines %u, using %u\n", *npins,
413 RCAR_MAX_GPIO_PER_BANK);
414 *npins = RCAR_MAX_GPIO_PER_BANK;
420 static int gpio_rcar_probe(struct platform_device *pdev)
422 struct gpio_rcar_priv *p;
423 struct resource *io, *irq;
424 struct gpio_chip *gpio_chip;
425 struct irq_chip *irq_chip;
426 struct device *dev = &pdev->dev;
427 const char *name = dev_name(dev);
431 p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
436 spin_lock_init(&p->lock);
438 /* Get device configuration from DT node */
439 ret = gpio_rcar_parse_dt(p, &npins);
443 platform_set_drvdata(pdev, p);
445 pm_runtime_enable(dev);
447 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
449 dev_err(dev, "missing IRQ\n");
454 io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
455 p->base = devm_ioremap_resource(dev, io);
456 if (IS_ERR(p->base)) {
457 ret = PTR_ERR(p->base);
461 gpio_chip = &p->gpio_chip;
462 gpio_chip->request = gpio_rcar_request;
463 gpio_chip->free = gpio_rcar_free;
464 gpio_chip->direction_input = gpio_rcar_direction_input;
465 gpio_chip->get = gpio_rcar_get;
466 gpio_chip->direction_output = gpio_rcar_direction_output;
467 gpio_chip->set = gpio_rcar_set;
468 gpio_chip->set_multiple = gpio_rcar_set_multiple;
469 gpio_chip->label = name;
470 gpio_chip->parent = dev;
471 gpio_chip->owner = THIS_MODULE;
472 gpio_chip->base = -1;
473 gpio_chip->ngpio = npins;
475 irq_chip = &p->irq_chip;
476 irq_chip->name = name;
477 irq_chip->parent_device = dev;
478 irq_chip->irq_mask = gpio_rcar_irq_disable;
479 irq_chip->irq_unmask = gpio_rcar_irq_enable;
480 irq_chip->irq_set_type = gpio_rcar_irq_set_type;
481 irq_chip->irq_set_wake = gpio_rcar_irq_set_wake;
482 irq_chip->flags = IRQCHIP_SET_TYPE_MASKED | IRQCHIP_MASK_ON_SUSPEND;
484 ret = gpiochip_add_data(gpio_chip, p);
486 dev_err(dev, "failed to add GPIO controller\n");
490 ret = gpiochip_irqchip_add(gpio_chip, irq_chip, 0, handle_level_irq,
493 dev_err(dev, "cannot add irqchip\n");
497 p->irq_parent = irq->start;
498 if (devm_request_irq(dev, irq->start, gpio_rcar_irq_handler,
499 IRQF_SHARED, name, p)) {
500 dev_err(dev, "failed to request IRQ\n");
505 dev_info(dev, "driving %d GPIOs\n", npins);
510 gpiochip_remove(gpio_chip);
512 pm_runtime_disable(dev);
516 static int gpio_rcar_remove(struct platform_device *pdev)
518 struct gpio_rcar_priv *p = platform_get_drvdata(pdev);
520 gpiochip_remove(&p->gpio_chip);
522 pm_runtime_disable(&pdev->dev);
526 #ifdef CONFIG_PM_SLEEP
527 static int gpio_rcar_suspend(struct device *dev)
529 struct gpio_rcar_priv *p = dev_get_drvdata(dev);
531 p->bank_info.iointsel = gpio_rcar_read(p, IOINTSEL);
532 p->bank_info.inoutsel = gpio_rcar_read(p, INOUTSEL);
533 p->bank_info.outdt = gpio_rcar_read(p, OUTDT);
534 p->bank_info.intmsk = gpio_rcar_read(p, INTMSK);
535 p->bank_info.posneg = gpio_rcar_read(p, POSNEG);
536 p->bank_info.edglevel = gpio_rcar_read(p, EDGLEVEL);
537 if (p->has_both_edge_trigger)
538 p->bank_info.bothedge = gpio_rcar_read(p, BOTHEDGE);
540 if (atomic_read(&p->wakeup_path))
541 device_set_wakeup_path(dev);
546 static int gpio_rcar_resume(struct device *dev)
548 struct gpio_rcar_priv *p = dev_get_drvdata(dev);
552 for (offset = 0; offset < p->gpio_chip.ngpio; offset++) {
555 if (!(p->bank_info.iointsel & mask)) {
556 if (p->bank_info.inoutsel & mask)
557 gpio_rcar_direction_output(
558 &p->gpio_chip, offset,
559 !!(p->bank_info.outdt & mask));
561 gpio_rcar_direction_input(&p->gpio_chip,
565 gpio_rcar_config_interrupt_input_mode(
568 !(p->bank_info.posneg & mask),
569 !(p->bank_info.edglevel & mask),
570 !!(p->bank_info.bothedge & mask));
572 if (p->bank_info.intmsk & mask)
573 gpio_rcar_write(p, MSKCLR, mask);
579 #endif /* CONFIG_PM_SLEEP*/
581 static SIMPLE_DEV_PM_OPS(gpio_rcar_pm_ops, gpio_rcar_suspend, gpio_rcar_resume);
583 static struct platform_driver gpio_rcar_device_driver = {
584 .probe = gpio_rcar_probe,
585 .remove = gpio_rcar_remove,
588 .pm = &gpio_rcar_pm_ops,
589 .of_match_table = of_match_ptr(gpio_rcar_of_table),
593 module_platform_driver(gpio_rcar_device_driver);
595 MODULE_AUTHOR("Magnus Damm");
596 MODULE_DESCRIPTION("Renesas R-Car GPIO Driver");
597 MODULE_LICENSE("GPL v2");