drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c

   1 /*
   2  * Copyright 2008 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Jerome Glisse <glisse@freedesktop.org>
  26  */
  27
  28 #include <linux/file.h>
  29 #include <linux/pagemap.h>
  30 #include <linux/sync_file.h>
  31 #include <linux/dma-buf.h>
  32
  33 #include <drm/amdgpu_drm.h>
  34 #include <drm/drm_syncobj.h>
  35 #include "amdgpu.h"
  36 #include "amdgpu_trace.h"
  37 #include "amdgpu_gmc.h"
  38 #include "amdgpu_gem.h"
  39 #include "amdgpu_ras.h"
  40
  41 static int amdgpu_cs_user_fence_chunk(struct amdgpu_cs_parser *p,
  42                                       struct drm_amdgpu_cs_chunk_fence *data,
  43                                       uint32_t *offset)
  44 {
  45         struct drm_gem_object *gobj;
  46         struct amdgpu_bo *bo;
  47         unsigned long size;
  48         int r;
  49
  50         gobj = drm_gem_object_lookup(p->filp, data->handle);
  51         if (gobj == NULL)
  52                 return -EINVAL;
  53
  54         bo = amdgpu_bo_ref(gem_to_amdgpu_bo(gobj));
  55         p->uf_entry.priority = 0;
  56         p->uf_entry.tv.bo = &bo->tbo;
  57         /* One for TTM and one for the CS job */
  58         p->uf_entry.tv.num_shared = 2;
  59
  60         drm_gem_object_put(gobj);
  61
  62         size = amdgpu_bo_size(bo);
  63         if (size != PAGE_SIZE || (data->offset + 8) > size) {
  64                 r = -EINVAL;
  65                 goto error_unref;
  66         }
  67
  68         if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) {
  69                 r = -EINVAL;
  70                 goto error_unref;
  71         }
  72
  73         *offset = data->offset;
  74
  75         return 0;
  76
  77 error_unref:
  78         amdgpu_bo_unref(&bo);
  79         return r;
  80 }
  81
  82 static int amdgpu_cs_bo_handles_chunk(struct amdgpu_cs_parser *p,
  83                                       struct drm_amdgpu_bo_list_in *data)
  84 {
  85         int r;
  86         struct drm_amdgpu_bo_list_entry *info = NULL;
  87
  88         r = amdgpu_bo_create_list_entry_array(data, &info);
  89         if (r)
  90                 return r;
  91
  92         r = amdgpu_bo_list_create(p->adev, p->filp, info, data->bo_number,
  93                                   &p->bo_list);
  94         if (r)
  95                 goto error_free;
  96
  97         kvfree(info);
  98         return 0;
  99
 100 error_free:
 101         kvfree(info);
 102
 103         return r;
 104 }
 105
 106 static int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, union drm_amdgpu_cs *cs)
 107 {
 108         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 109         struct amdgpu_vm *vm = &fpriv->vm;
 110         uint64_t *chunk_array_user;
 111         uint64_t *chunk_array;
 112         unsigned size, num_ibs = 0;
 113         uint32_t uf_offset = 0;
 114         int i;
 115         int ret;
 116
 117         if (cs->in.num_chunks == 0)
 118                 return 0;
 119
 120         chunk_array = kvmalloc_array(cs->in.num_chunks, sizeof(uint64_t), GFP_KERNEL);
 121         if (!chunk_array)
 122                 return -ENOMEM;
 123
 124         p->ctx = amdgpu_ctx_get(fpriv, cs->in.ctx_id);
 125         if (!p->ctx) {
 126                 ret = -EINVAL;
 127                 goto free_chunk;
 128         }
 129
 130         mutex_lock(&p->ctx->lock);
 131
 132         /* skip guilty context job */
 133         if (atomic_read(&p->ctx->guilty) == 1) {
 134                 ret = -ECANCELED;
 135                 goto free_chunk;
 136         }
 137
 138         /* get chunks */
 139         chunk_array_user = u64_to_user_ptr(cs->in.chunks);
 140         if (copy_from_user(chunk_array, chunk_array_user,
 141                            sizeof(uint64_t)*cs->in.num_chunks)) {
 142                 ret = -EFAULT;
 143                 goto free_chunk;
 144         }
 145
 146         p->nchunks = cs->in.num_chunks;
 147         p->chunks = kvmalloc_array(p->nchunks, sizeof(struct amdgpu_cs_chunk),
 148                             GFP_KERNEL);
 149         if (!p->chunks) {
 150                 ret = -ENOMEM;
 151                 goto free_chunk;
 152         }
 153
 154         for (i = 0; i < p->nchunks; i++) {
 155                 struct drm_amdgpu_cs_chunk __user **chunk_ptr = NULL;
 156                 struct drm_amdgpu_cs_chunk user_chunk;
 157                 uint32_t __user *cdata;
 158
 159                 chunk_ptr = u64_to_user_ptr(chunk_array[i]);
 160                 if (copy_from_user(&user_chunk, chunk_ptr,
 161                                        sizeof(struct drm_amdgpu_cs_chunk))) {
 162                         ret = -EFAULT;
 163                         i--;
 164                         goto free_partial_kdata;
 165                 }
 166                 p->chunks[i].chunk_id = user_chunk.chunk_id;
 167                 p->chunks[i].length_dw = user_chunk.length_dw;
 168
 169                 size = p->chunks[i].length_dw;
 170                 cdata = u64_to_user_ptr(user_chunk.chunk_data);
 171
 172                 p->chunks[i].kdata = kvmalloc_array(size, sizeof(uint32_t), GFP_KERNEL);
 173                 if (p->chunks[i].kdata == NULL) {
 174                         ret = -ENOMEM;
 175                         i--;
 176                         goto free_partial_kdata;
 177                 }
 178                 size *= sizeof(uint32_t);
 179                 if (copy_from_user(p->chunks[i].kdata, cdata, size)) {
 180                         ret = -EFAULT;
 181                         goto free_partial_kdata;
 182                 }
 183
 184                 switch (p->chunks[i].chunk_id) {
 185                 case AMDGPU_CHUNK_ID_IB:
 186                         ++num_ibs;
 187                         break;
 188
 189                 case AMDGPU_CHUNK_ID_FENCE:
 190                         size = sizeof(struct drm_amdgpu_cs_chunk_fence);
 191                         if (p->chunks[i].length_dw * sizeof(uint32_t) < size) {
 192                                 ret = -EINVAL;
 193                                 goto free_partial_kdata;
 194                         }
 195
 196                         ret = amdgpu_cs_user_fence_chunk(p, p->chunks[i].kdata,
 197                                                          &uf_offset);
 198                         if (ret)
 199                                 goto free_partial_kdata;
 200
 201                         break;
 202
 203                 case AMDGPU_CHUNK_ID_BO_HANDLES:
 204                         size = sizeof(struct drm_amdgpu_bo_list_in);
 205                         if (p->chunks[i].length_dw * sizeof(uint32_t) < size) {
 206                                 ret = -EINVAL;
 207                                 goto free_partial_kdata;
 208                         }
 209
 210                         ret = amdgpu_cs_bo_handles_chunk(p, p->chunks[i].kdata);
 211                         if (ret)
 212                                 goto free_partial_kdata;
 213
 214                         break;
 215
 216                 case AMDGPU_CHUNK_ID_DEPENDENCIES:
 217                 case AMDGPU_CHUNK_ID_SYNCOBJ_IN:
 218                 case AMDGPU_CHUNK_ID_SYNCOBJ_OUT:
 219                 case AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES:
 220                 case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT:
 221                 case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL:
 222                         break;
 223
 224                 default:
 225                         ret = -EINVAL;
 226                         goto free_partial_kdata;
 227                 }
 228         }
 229
 230         ret = amdgpu_job_alloc(p->adev, num_ibs, &p->job, vm);
 231         if (ret)
 232                 goto free_all_kdata;
 233
 234         if (p->ctx->vram_lost_counter != p->job->vram_lost_counter) {
 235                 ret = -ECANCELED;
 236                 goto free_all_kdata;
 237         }
 238
 239         if (p->uf_entry.tv.bo)
 240                 p->job->uf_addr = uf_offset;
 241         kvfree(chunk_array);
 242
 243         /* Use this opportunity to fill in task info for the vm */
 244         amdgpu_vm_set_task_info(vm);
 245
 246         return 0;
 247
 248 free_all_kdata:
 249         i = p->nchunks - 1;
 250 free_partial_kdata:
 251         for (; i >= 0; i--)
 252                 kvfree(p->chunks[i].kdata);
 253         kvfree(p->chunks);
 254         p->chunks = NULL;
 255         p->nchunks = 0;
 256 free_chunk:
 257         kvfree(chunk_array);
 258
 259         return ret;
 260 }
 261
 262 /* Convert microseconds to bytes. */
 263 static u64 us_to_bytes(struct amdgpu_device *adev, s64 us)
 264 {
 265         if (us <= 0 || !adev->mm_stats.log2_max_MBps)
 266                 return 0;
 267
 268         /* Since accum_us is incremented by a million per second, just
 269          * multiply it by the number of MB/s to get the number of bytes.
 270          */
 271         return us << adev->mm_stats.log2_max_MBps;
 272 }
 273
 274 static s64 bytes_to_us(struct amdgpu_device *adev, u64 bytes)
 275 {
 276         if (!adev->mm_stats.log2_max_MBps)
 277                 return 0;
 278
 279         return bytes >> adev->mm_stats.log2_max_MBps;
 280 }
 281
 282 /* Returns how many bytes TTM can move right now. If no bytes can be moved,
 283  * it returns 0. If it returns non-zero, it's OK to move at least one buffer,
 284  * which means it can go over the threshold once. If that happens, the driver
 285  * will be in debt and no other buffer migrations can be done until that debt
 286  * is repaid.
 287  *
 288  * This approach allows moving a buffer of any size (it's important to allow
 289  * that).
 290  *
 291  * The currency is simply time in microseconds and it increases as the clock
 292  * ticks. The accumulated microseconds (us) are converted to bytes and
 293  * returned.
 294  */
 295 static void amdgpu_cs_get_threshold_for_moves(struct amdgpu_device *adev,
 296                                               u64 *max_bytes,
 297                                               u64 *max_vis_bytes)
 298 {
 299         s64 time_us, increment_us;
 300         u64 free_vram, total_vram, used_vram;
 301         /* Allow a maximum of 200 accumulated ms. This is basically per-IB
 302          * throttling.
 303          *
 304          * It means that in order to get full max MBps, at least 5 IBs per
 305          * second must be submitted and not more than 200ms apart from each
 306          * other.
 307          */
 308         const s64 us_upper_bound = 200000;
 309
 310         if (!adev->mm_stats.log2_max_MBps) {
 311                 *max_bytes = 0;
 312                 *max_vis_bytes = 0;
 313                 return;
 314         }
 315
 316         total_vram = adev->gmc.real_vram_size - atomic64_read(&adev->vram_pin_size);
 317         used_vram = amdgpu_vram_mgr_usage(&adev->mman.vram_mgr);
 318         free_vram = used_vram >= total_vram ? 0 : total_vram - used_vram;
 319
 320         spin_lock(&adev->mm_stats.lock);
 321
 322         /* Increase the amount of accumulated us. */
 323         time_us = ktime_to_us(ktime_get());
 324         increment_us = time_us - adev->mm_stats.last_update_us;
 325         adev->mm_stats.last_update_us = time_us;
 326         adev->mm_stats.accum_us = min(adev->mm_stats.accum_us + increment_us,
 327                                       us_upper_bound);
 328
 329         /* This prevents the short period of low performance when the VRAM
 330          * usage is low and the driver is in debt or doesn't have enough
 331          * accumulated us to fill VRAM quickly.
 332          *
 333          * The situation can occur in these cases:
 334          * - a lot of VRAM is freed by userspace
 335          * - the presence of a big buffer causes a lot of evictions
 336          *   (solution: split buffers into smaller ones)
 337          *
 338          * If 128 MB or 1/8th of VRAM is free, start filling it now by setting
 339          * accum_us to a positive number.
 340          */
 341         if (free_vram >= 128 * 1024 * 1024 || free_vram >= total_vram / 8) {
 342                 s64 min_us;
 343
 344                 /* Be more aggresive on dGPUs. Try to fill a portion of free
 345                  * VRAM now.
 346                  */
 347                 if (!(adev->flags & AMD_IS_APU))
 348                         min_us = bytes_to_us(adev, free_vram / 4);
 349                 else
 350                         min_us = 0; /* Reset accum_us on APUs. */
 351
 352                 adev->mm_stats.accum_us = max(min_us, adev->mm_stats.accum_us);
 353         }
 354
 355         /* This is set to 0 if the driver is in debt to disallow (optional)
 356          * buffer moves.
 357          */
 358         *max_bytes = us_to_bytes(adev, adev->mm_stats.accum_us);
 359
 360         /* Do the same for visible VRAM if half of it is free */
 361         if (!amdgpu_gmc_vram_full_visible(&adev->gmc)) {
 362                 u64 total_vis_vram = adev->gmc.visible_vram_size;
 363                 u64 used_vis_vram =
 364                   amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr);
 365
 366                 if (used_vis_vram < total_vis_vram) {
 367                         u64 free_vis_vram = total_vis_vram - used_vis_vram;
 368                         adev->mm_stats.accum_us_vis = min(adev->mm_stats.accum_us_vis +
 369                                                           increment_us, us_upper_bound);
 370
 371                         if (free_vis_vram >= total_vis_vram / 2)
 372                                 adev->mm_stats.accum_us_vis =
 373                                         max(bytes_to_us(adev, free_vis_vram / 2),
 374                                             adev->mm_stats.accum_us_vis);
 375                 }
 376
 377                 *max_vis_bytes = us_to_bytes(adev, adev->mm_stats.accum_us_vis);
 378         } else {
 379                 *max_vis_bytes = 0;
 380         }
 381
 382         spin_unlock(&adev->mm_stats.lock);
 383 }
 384
 385 /* Report how many bytes have really been moved for the last command
 386  * submission. This can result in a debt that can stop buffer migrations
 387  * temporarily.
 388  */
 389 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
 390                                   u64 num_vis_bytes)
 391 {
 392         spin_lock(&adev->mm_stats.lock);
 393         adev->mm_stats.accum_us -= bytes_to_us(adev, num_bytes);
 394         adev->mm_stats.accum_us_vis -= bytes_to_us(adev, num_vis_bytes);
 395         spin_unlock(&adev->mm_stats.lock);
 396 }
 397
 398 static int amdgpu_cs_bo_validate(void *param, struct amdgpu_bo *bo)
 399 {
 400         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 401         struct amdgpu_cs_parser *p = param;
 402         struct ttm_operation_ctx ctx = {
 403                 .interruptible = true,
 404                 .no_wait_gpu = false,
 405                 .resv = bo->tbo.base.resv
 406         };
 407         uint32_t domain;
 408         int r;
 409
 410         if (bo->tbo.pin_count)
 411                 return 0;
 412
 413         /* Don't move this buffer if we have depleted our allowance
 414          * to move it. Don't move anything if the threshold is zero.
 415          */
 416         if (p->bytes_moved < p->bytes_moved_threshold &&
 417             (!bo->tbo.base.dma_buf ||
 418             list_empty(&bo->tbo.base.dma_buf->attachments))) {
 419                 if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
 420                     (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)) {
 421                         /* And don't move a CPU_ACCESS_REQUIRED BO to limited
 422                          * visible VRAM if we've depleted our allowance to do
 423                          * that.
 424                          */
 425                         if (p->bytes_moved_vis < p->bytes_moved_vis_threshold)
 426                                 domain = bo->preferred_domains;
 427                         else
 428                                 domain = bo->allowed_domains;
 429                 } else {
 430                         domain = bo->preferred_domains;
 431                 }
 432         } else {
 433                 domain = bo->allowed_domains;
 434         }
 435
 436 retry:
 437         amdgpu_bo_placement_from_domain(bo, domain);
 438         r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 439
 440         p->bytes_moved += ctx.bytes_moved;
 441         if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
 442             amdgpu_bo_in_cpu_visible_vram(bo))
 443                 p->bytes_moved_vis += ctx.bytes_moved;
 444
 445         if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) {
 446                 domain = bo->allowed_domains;
 447                 goto retry;
 448         }
 449
 450         return r;
 451 }
 452
 453 static int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p,
 454                             struct list_head *validated)
 455 {
 456         struct ttm_operation_ctx ctx = { true, false };
 457         struct amdgpu_bo_list_entry *lobj;
 458         int r;
 459
 460         list_for_each_entry(lobj, validated, tv.head) {
 461                 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(lobj->tv.bo);
 462                 struct mm_struct *usermm;
 463
 464                 usermm = amdgpu_ttm_tt_get_usermm(bo->tbo.ttm);
 465                 if (usermm && usermm != current->mm)
 466                         return -EPERM;
 467
 468                 if (amdgpu_ttm_tt_is_userptr(bo->tbo.ttm) &&
 469                     lobj->user_invalidated && lobj->user_pages) {
 470                         amdgpu_bo_placement_from_domain(bo,
 471                                                         AMDGPU_GEM_DOMAIN_CPU);
 472                         r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 473                         if (r)
 474                                 return r;
 475
 476                         amdgpu_ttm_tt_set_user_pages(bo->tbo.ttm,
 477                                                      lobj->user_pages);
 478                 }
 479
 480                 r = amdgpu_cs_bo_validate(p, bo);
 481                 if (r)
 482                         return r;
 483
 484                 kvfree(lobj->user_pages);
 485                 lobj->user_pages = NULL;
 486         }
 487         return 0;
 488 }
 489
 490 static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p,
 491                                 union drm_amdgpu_cs *cs)
 492 {
 493         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 494         struct amdgpu_vm *vm = &fpriv->vm;
 495         struct amdgpu_bo_list_entry *e;
 496         struct list_head duplicates;
 497         struct amdgpu_bo *gds;
 498         struct amdgpu_bo *gws;
 499         struct amdgpu_bo *oa;
 500         int r;
 501
 502         INIT_LIST_HEAD(&p->validated);
 503
 504         /* p->bo_list could already be assigned if AMDGPU_CHUNK_ID_BO_HANDLES is present */
 505         if (cs->in.bo_list_handle) {
 506                 if (p->bo_list)
 507                         return -EINVAL;
 508
 509                 r = amdgpu_bo_list_get(fpriv, cs->in.bo_list_handle,
 510                                        &p->bo_list);
 511                 if (r)
 512                         return r;
 513         } else if (!p->bo_list) {
 514                 /* Create a empty bo_list when no handle is provided */
 515                 r = amdgpu_bo_list_create(p->adev, p->filp, NULL, 0,
 516                                           &p->bo_list);
 517                 if (r)
 518                         return r;
 519         }
 520
 521         /* One for TTM and one for the CS job */
 522         amdgpu_bo_list_for_each_entry(e, p->bo_list)
 523                 e->tv.num_shared = 2;
 524
 525         amdgpu_bo_list_get_list(p->bo_list, &p->validated);
 526
 527         INIT_LIST_HEAD(&duplicates);
 528         amdgpu_vm_get_pd_bo(&fpriv->vm, &p->validated, &p->vm_pd);
 529
 530         if (p->uf_entry.tv.bo && !ttm_to_amdgpu_bo(p->uf_entry.tv.bo)->parent)
 531                 list_add(&p->uf_entry.tv.head, &p->validated);
 532
 533         /* Get userptr backing pages. If pages are updated after registered
 534          * in amdgpu_gem_userptr_ioctl(), amdgpu_cs_list_validate() will do
 535          * amdgpu_ttm_backend_bind() to flush and invalidate new pages
 536          */
 537         amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) {
 538                 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
 539                 bool userpage_invalidated = false;
 540                 int i;
 541
 542                 e->user_pages = kvmalloc_array(bo->tbo.ttm->num_pages,
 543                                         sizeof(struct page *),
 544                                         GFP_KERNEL | __GFP_ZERO);
 545                 if (!e->user_pages) {
 546                         DRM_ERROR("kvmalloc_array failure\n");
 547                         return -ENOMEM;
 548                 }
 549
 550                 r = amdgpu_ttm_tt_get_user_pages(bo, e->user_pages);
 551                 if (r) {
 552                         kvfree(e->user_pages);
 553                         e->user_pages = NULL;
 554                         return r;
 555                 }
 556
 557                 for (i = 0; i < bo->tbo.ttm->num_pages; i++) {
 558                         if (bo->tbo.ttm->pages[i] != e->user_pages[i]) {
 559                                 userpage_invalidated = true;
 560                                 break;
 561                         }
 562                 }
 563                 e->user_invalidated = userpage_invalidated;
 564         }
 565
 566         r = ttm_eu_reserve_buffers(&p->ticket, &p->validated, true,
 567                                    &duplicates);
 568         if (unlikely(r != 0)) {
 569                 if (r != -ERESTARTSYS)
 570                         DRM_ERROR("ttm_eu_reserve_buffers failed.\n");
 571                 goto out;
 572         }
 573
 574         amdgpu_bo_list_for_each_entry(e, p->bo_list) {
 575                 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
 576
 577                 e->bo_va = amdgpu_vm_bo_find(vm, bo);
 578
 579                 if (bo->tbo.base.dma_buf && !amdgpu_bo_explicit_sync(bo)) {
 580                         e->chain = dma_fence_chain_alloc();
 581                         if (!e->chain) {
 582                                 r = -ENOMEM;
 583                                 goto error_validate;
 584                         }
 585                 }
 586         }
 587
 588         amdgpu_cs_get_threshold_for_moves(p->adev, &p->bytes_moved_threshold,
 589                                           &p->bytes_moved_vis_threshold);
 590         p->bytes_moved = 0;
 591         p->bytes_moved_vis = 0;
 592
 593         r = amdgpu_vm_validate_pt_bos(p->adev, &fpriv->vm,
 594                                       amdgpu_cs_bo_validate, p);
 595         if (r) {
 596                 DRM_ERROR("amdgpu_vm_validate_pt_bos() failed.\n");
 597                 goto error_validate;
 598         }
 599
 600         r = amdgpu_cs_list_validate(p, &duplicates);
 601         if (r)
 602                 goto error_validate;
 603
 604         r = amdgpu_cs_list_validate(p, &p->validated);
 605         if (r)
 606                 goto error_validate;
 607
 608         amdgpu_cs_report_moved_bytes(p->adev, p->bytes_moved,
 609                                      p->bytes_moved_vis);
 610
 611         gds = p->bo_list->gds_obj;
 612         gws = p->bo_list->gws_obj;
 613         oa = p->bo_list->oa_obj;
 614
 615         if (gds) {
 616                 p->job->gds_base = amdgpu_bo_gpu_offset(gds) >> PAGE_SHIFT;
 617                 p->job->gds_size = amdgpu_bo_size(gds) >> PAGE_SHIFT;
 618         }
 619         if (gws) {
 620                 p->job->gws_base = amdgpu_bo_gpu_offset(gws) >> PAGE_SHIFT;
 621                 p->job->gws_size = amdgpu_bo_size(gws) >> PAGE_SHIFT;
 622         }
 623         if (oa) {
 624                 p->job->oa_base = amdgpu_bo_gpu_offset(oa) >> PAGE_SHIFT;
 625                 p->job->oa_size = amdgpu_bo_size(oa) >> PAGE_SHIFT;
 626         }
 627
 628         if (!r && p->uf_entry.tv.bo) {
 629                 struct amdgpu_bo *uf = ttm_to_amdgpu_bo(p->uf_entry.tv.bo);
 630
 631                 r = amdgpu_ttm_alloc_gart(&uf->tbo);
 632                 p->job->uf_addr += amdgpu_bo_gpu_offset(uf);
 633         }
 634
 635 error_validate:
 636         if (r) {
 637                 amdgpu_bo_list_for_each_entry(e, p->bo_list) {
 638                         dma_fence_chain_free(e->chain);
 639                         e->chain = NULL;
 640                 }
 641                 ttm_eu_backoff_reservation(&p->ticket, &p->validated);
 642         }
 643 out:
 644         return r;
 645 }
 646
 647 static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p)
 648 {
 649         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 650         struct amdgpu_bo_list_entry *e;
 651         int r;
 652
 653         list_for_each_entry(e, &p->validated, tv.head) {
 654                 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
 655                 struct dma_resv *resv = bo->tbo.base.resv;
 656                 enum amdgpu_sync_mode sync_mode;
 657
 658                 sync_mode = amdgpu_bo_explicit_sync(bo) ?
 659                         AMDGPU_SYNC_EXPLICIT : AMDGPU_SYNC_NE_OWNER;
 660                 r = amdgpu_sync_resv(p->adev, &p->job->sync, resv, sync_mode,
 661                                      &fpriv->vm);
 662                 if (r)
 663                         return r;
 664         }
 665         return 0;
 666 }
 667
 668 /**
 669  * amdgpu_cs_parser_fini() - clean parser states
 670  * @parser:     parser structure holding parsing context.
 671  * @error:      error number
 672  * @backoff:    indicator to backoff the reservation
 673  *
 674  * If error is set then unvalidate buffer, otherwise just free memory
 675  * used by parsing context.
 676  **/
 677 static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error,
 678                                   bool backoff)
 679 {
 680         unsigned i;
 681
 682         if (error && backoff) {
 683                 struct amdgpu_bo_list_entry *e;
 684
 685                 amdgpu_bo_list_for_each_entry(e, parser->bo_list) {
 686                         dma_fence_chain_free(e->chain);
 687                         e->chain = NULL;
 688                 }
 689
 690                 ttm_eu_backoff_reservation(&parser->ticket,
 691                                            &parser->validated);
 692         }
 693
 694         for (i = 0; i < parser->num_post_deps; i++) {
 695                 drm_syncobj_put(parser->post_deps[i].syncobj);
 696                 kfree(parser->post_deps[i].chain);
 697         }
 698         kfree(parser->post_deps);
 699
 700         dma_fence_put(parser->fence);
 701
 702         if (parser->ctx) {
 703                 mutex_unlock(&parser->ctx->lock);
 704                 amdgpu_ctx_put(parser->ctx);
 705         }
 706         if (parser->bo_list)
 707                 amdgpu_bo_list_put(parser->bo_list);
 708
 709         for (i = 0; i < parser->nchunks; i++)
 710                 kvfree(parser->chunks[i].kdata);
 711         kvfree(parser->chunks);
 712         if (parser->job)
 713                 amdgpu_job_free(parser->job);
 714         if (parser->uf_entry.tv.bo) {
 715                 struct amdgpu_bo *uf = ttm_to_amdgpu_bo(parser->uf_entry.tv.bo);
 716
 717                 amdgpu_bo_unref(&uf);
 718         }
 719 }
 720
 721 static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser *p)
 722 {
 723         struct amdgpu_ring *ring = to_amdgpu_ring(p->entity->rq->sched);
 724         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 725         struct amdgpu_device *adev = p->adev;
 726         struct amdgpu_vm *vm = &fpriv->vm;
 727         struct amdgpu_bo_list_entry *e;
 728         struct amdgpu_bo_va *bo_va;
 729         struct amdgpu_bo *bo;
 730         int r;
 731
 732         /* Only for UVD/VCE VM emulation */
 733         if (ring->funcs->parse_cs || ring->funcs->patch_cs_in_place) {
 734                 unsigned i, j;
 735
 736                 for (i = 0, j = 0; i < p->nchunks && j < p->job->num_ibs; i++) {
 737                         struct drm_amdgpu_cs_chunk_ib *chunk_ib;
 738                         struct amdgpu_bo_va_mapping *m;
 739                         struct amdgpu_bo *aobj = NULL;
 740                         struct amdgpu_cs_chunk *chunk;
 741                         uint64_t offset, va_start;
 742                         struct amdgpu_ib *ib;
 743                         uint8_t *kptr;
 744
 745                         chunk = &p->chunks[i];
 746                         ib = &p->job->ibs[j];
 747                         chunk_ib = chunk->kdata;
 748
 749                         if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB)
 750                                 continue;
 751
 752                         va_start = chunk_ib->va_start & AMDGPU_GMC_HOLE_MASK;
 753                         r = amdgpu_cs_find_mapping(p, va_start, &aobj, &m);
 754                         if (r) {
 755                                 DRM_ERROR("IB va_start is invalid\n");
 756                                 return r;
 757                         }
 758
 759                         if ((va_start + chunk_ib->ib_bytes) >
 760                             (m->last + 1) * AMDGPU_GPU_PAGE_SIZE) {
 761                                 DRM_ERROR("IB va_start+ib_bytes is invalid\n");
 762                                 return -EINVAL;
 763                         }
 764
 765                         /* the IB should be reserved at this point */
 766                         r = amdgpu_bo_kmap(aobj, (void **)&kptr);
 767                         if (r) {
 768                                 return r;
 769                         }
 770
 771                         offset = m->start * AMDGPU_GPU_PAGE_SIZE;
 772                         kptr += va_start - offset;
 773
 774                         if (ring->funcs->parse_cs) {
 775                                 memcpy(ib->ptr, kptr, chunk_ib->ib_bytes);
 776                                 amdgpu_bo_kunmap(aobj);
 777
 778                                 r = amdgpu_ring_parse_cs(ring, p, j);
 779                                 if (r)
 780                                         return r;
 781                         } else {
 782                                 ib->ptr = (uint32_t *)kptr;
 783                                 r = amdgpu_ring_patch_cs_in_place(ring, p, j);
 784                                 amdgpu_bo_kunmap(aobj);
 785                                 if (r)
 786                                         return r;
 787                         }
 788
 789                         j++;
 790                 }
 791         }
 792
 793         if (!p->job->vm)
 794                 return amdgpu_cs_sync_rings(p);
 795
 796
 797         r = amdgpu_vm_clear_freed(adev, vm, NULL);
 798         if (r)
 799                 return r;
 800
 801         r = amdgpu_vm_bo_update(adev, fpriv->prt_va, false, NULL);
 802         if (r)
 803                 return r;
 804
 805         r = amdgpu_sync_vm_fence(&p->job->sync, fpriv->prt_va->last_pt_update);
 806         if (r)
 807                 return r;
 808
 809         if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) {
 810                 bo_va = fpriv->csa_va;
 811                 BUG_ON(!bo_va);
 812                 r = amdgpu_vm_bo_update(adev, bo_va, false, NULL);
 813                 if (r)
 814                         return r;
 815
 816                 r = amdgpu_sync_vm_fence(&p->job->sync, bo_va->last_pt_update);
 817                 if (r)
 818                         return r;
 819         }
 820
 821         amdgpu_bo_list_for_each_entry(e, p->bo_list) {
 822                 /* ignore duplicates */
 823                 bo = ttm_to_amdgpu_bo(e->tv.bo);
 824                 if (!bo)
 825                         continue;
 826
 827                 bo_va = e->bo_va;
 828                 if (bo_va == NULL)
 829                         continue;
 830
 831                 r = amdgpu_vm_bo_update(adev, bo_va, false, NULL);
 832                 if (r)
 833                         return r;
 834
 835                 r = amdgpu_sync_vm_fence(&p->job->sync, bo_va->last_pt_update);
 836                 if (r)
 837                         return r;
 838         }
 839
 840         r = amdgpu_vm_handle_moved(adev, vm);
 841         if (r)
 842                 return r;
 843
 844         r = amdgpu_vm_update_pdes(adev, vm, false);
 845         if (r)
 846                 return r;
 847
 848         r = amdgpu_sync_vm_fence(&p->job->sync, vm->last_update);
 849         if (r)
 850                 return r;
 851
 852         p->job->vm_pd_addr = amdgpu_gmc_pd_addr(vm->root.bo);
 853
 854         if (amdgpu_vm_debug) {
 855                 /* Invalidate all BOs to test for userspace bugs */
 856                 amdgpu_bo_list_for_each_entry(e, p->bo_list) {
 857                         struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
 858
 859                         /* ignore duplicates */
 860                         if (!bo)
 861                                 continue;
 862
 863                         amdgpu_vm_bo_invalidate(adev, bo, false);
 864                 }
 865         }
 866
 867         return amdgpu_cs_sync_rings(p);
 868 }
 869
 870 static int amdgpu_cs_ib_fill(struct amdgpu_device *adev,
 871                              struct amdgpu_cs_parser *parser)
 872 {
 873         struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
 874         struct amdgpu_vm *vm = &fpriv->vm;
 875         int r, ce_preempt = 0, de_preempt = 0;
 876         struct amdgpu_ring *ring;
 877         int i, j;
 878
 879         for (i = 0, j = 0; i < parser->nchunks && j < parser->job->num_ibs; i++) {
 880                 struct amdgpu_cs_chunk *chunk;
 881                 struct amdgpu_ib *ib;
 882                 struct drm_amdgpu_cs_chunk_ib *chunk_ib;
 883                 struct drm_sched_entity *entity;
 884
 885                 chunk = &parser->chunks[i];
 886                 ib = &parser->job->ibs[j];
 887                 chunk_ib = (struct drm_amdgpu_cs_chunk_ib *)chunk->kdata;
 888
 889                 if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB)
 890                         continue;
 891
 892                 if (chunk_ib->ip_type == AMDGPU_HW_IP_GFX &&
 893                     (amdgpu_mcbp || amdgpu_sriov_vf(adev))) {
 894                         if (chunk_ib->flags & AMDGPU_IB_FLAG_PREEMPT) {
 895                                 if (chunk_ib->flags & AMDGPU_IB_FLAG_CE)
 896                                         ce_preempt++;
 897                                 else
 898                                         de_preempt++;
 899                         }
 900
 901                         /* each GFX command submit allows 0 or 1 IB preemptible for CE & DE */
 902                         if (ce_preempt > 1 || de_preempt > 1)
 903                                 return -EINVAL;
 904                 }
 905
 906                 r = amdgpu_ctx_get_entity(parser->ctx, chunk_ib->ip_type,
 907                                           chunk_ib->ip_instance, chunk_ib->ring,
 908                                           &entity);
 909                 if (r)
 910                         return r;
 911
 912                 if (chunk_ib->flags & AMDGPU_IB_FLAG_PREAMBLE)
 913                         parser->job->preamble_status |=
 914                                 AMDGPU_PREAMBLE_IB_PRESENT;
 915
 916                 if (parser->entity && parser->entity != entity)
 917                         return -EINVAL;
 918
 919                 /* Return if there is no run queue associated with this entity.
 920                  * Possibly because of disabled HW IP*/
 921                 if (entity->rq == NULL)
 922                         return -EINVAL;
 923
 924                 parser->entity = entity;
 925
 926                 ring = to_amdgpu_ring(entity->rq->sched);
 927                 r =  amdgpu_ib_get(adev, vm, ring->funcs->parse_cs ?
 928                                    chunk_ib->ib_bytes : 0,
 929                                    AMDGPU_IB_POOL_DELAYED, ib);
 930                 if (r) {
 931                         DRM_ERROR("Failed to get ib !\n");
 932                         return r;
 933                 }
 934
 935                 ib->gpu_addr = chunk_ib->va_start;
 936                 ib->length_dw = chunk_ib->ib_bytes / 4;
 937                 ib->flags = chunk_ib->flags;
 938
 939                 j++;
 940         }
 941
 942         /* MM engine doesn't support user fences */
 943         ring = to_amdgpu_ring(parser->entity->rq->sched);
 944         if (parser->job->uf_addr && ring->funcs->no_user_fence)
 945                 return -EINVAL;
 946
 947         return amdgpu_ctx_wait_prev_fence(parser->ctx, parser->entity);
 948 }
 949
 950 static int amdgpu_cs_process_fence_dep(struct amdgpu_cs_parser *p,
 951                                        struct amdgpu_cs_chunk *chunk)
 952 {
 953         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 954         unsigned num_deps;
 955         int i, r;
 956         struct drm_amdgpu_cs_chunk_dep *deps;
 957
 958         deps = (struct drm_amdgpu_cs_chunk_dep *)chunk->kdata;
 959         num_deps = chunk->length_dw * 4 /
 960                 sizeof(struct drm_amdgpu_cs_chunk_dep);
 961
 962         for (i = 0; i < num_deps; ++i) {
 963                 struct amdgpu_ctx *ctx;
 964                 struct drm_sched_entity *entity;
 965                 struct dma_fence *fence;
 966
 967                 ctx = amdgpu_ctx_get(fpriv, deps[i].ctx_id);
 968                 if (ctx == NULL)
 969                         return -EINVAL;
 970
 971                 r = amdgpu_ctx_get_entity(ctx, deps[i].ip_type,
 972                                           deps[i].ip_instance,
 973                                           deps[i].ring, &entity);
 974                 if (r) {
 975                         amdgpu_ctx_put(ctx);
 976                         return r;
 977                 }
 978
 979                 fence = amdgpu_ctx_get_fence(ctx, entity, deps[i].handle);
 980                 amdgpu_ctx_put(ctx);
 981
 982                 if (IS_ERR(fence))
 983                         return PTR_ERR(fence);
 984                 else if (!fence)
 985                         continue;
 986
 987                 if (chunk->chunk_id == AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES) {
 988                         struct drm_sched_fence *s_fence;
 989                         struct dma_fence *old = fence;
 990
 991                         s_fence = to_drm_sched_fence(fence);
 992                         fence = dma_fence_get(&s_fence->scheduled);
 993                         dma_fence_put(old);
 994                 }
 995
 996                 r = amdgpu_sync_fence(&p->job->sync, fence);
 997                 dma_fence_put(fence);
 998                 if (r)
 999                         return r;
1000         }
1001         return 0;
1002 }
1003
1004 static int amdgpu_syncobj_lookup_and_add_to_sync(struct amdgpu_cs_parser *p,
1005                                                  uint32_t handle, u64 point,
1006                                                  u64 flags)
1007 {
1008         struct dma_fence *fence;
1009         int r;
1010
1011         r = drm_syncobj_find_fence(p->filp, handle, point, flags, &fence);
1012         if (r) {
1013                 DRM_ERROR("syncobj %u failed to find fence @ %llu (%d)!\n",
1014                           handle, point, r);
1015                 return r;
1016         }
1017
1018         r = amdgpu_sync_fence(&p->job->sync, fence);
1019         dma_fence_put(fence);
1020
1021         return r;
1022 }
1023
1024 static int amdgpu_cs_process_syncobj_in_dep(struct amdgpu_cs_parser *p,
1025                                             struct amdgpu_cs_chunk *chunk)
1026 {
1027         struct drm_amdgpu_cs_chunk_sem *deps;
1028         unsigned num_deps;
1029         int i, r;
1030
1031         deps = (struct drm_amdgpu_cs_chunk_sem *)chunk->kdata;
1032         num_deps = chunk->length_dw * 4 /
1033                 sizeof(struct drm_amdgpu_cs_chunk_sem);
1034         for (i = 0; i < num_deps; ++i) {
1035                 r = amdgpu_syncobj_lookup_and_add_to_sync(p, deps[i].handle,
1036                                                           0, 0);
1037                 if (r)
1038                         return r;
1039         }
1040
1041         return 0;
1042 }
1043
1044
1045 static int amdgpu_cs_process_syncobj_timeline_in_dep(struct amdgpu_cs_parser *p,
1046                                                      struct amdgpu_cs_chunk *chunk)
1047 {
1048         struct drm_amdgpu_cs_chunk_syncobj *syncobj_deps;
1049         unsigned num_deps;
1050         int i, r;
1051
1052         syncobj_deps = (struct drm_amdgpu_cs_chunk_syncobj *)chunk->kdata;
1053         num_deps = chunk->length_dw * 4 /
1054                 sizeof(struct drm_amdgpu_cs_chunk_syncobj);
1055         for (i = 0; i < num_deps; ++i) {
1056                 r = amdgpu_syncobj_lookup_and_add_to_sync(p,
1057                                                           syncobj_deps[i].handle,
1058                                                           syncobj_deps[i].point,
1059                                                           syncobj_deps[i].flags);
1060                 if (r)
1061                         return r;
1062         }
1063
1064         return 0;
1065 }
1066
1067 static int amdgpu_cs_process_syncobj_out_dep(struct amdgpu_cs_parser *p,
1068                                              struct amdgpu_cs_chunk *chunk)
1069 {
1070         struct drm_amdgpu_cs_chunk_sem *deps;
1071         unsigned num_deps;
1072         int i;
1073
1074         deps = (struct drm_amdgpu_cs_chunk_sem *)chunk->kdata;
1075         num_deps = chunk->length_dw * 4 /
1076                 sizeof(struct drm_amdgpu_cs_chunk_sem);
1077
1078         if (p->post_deps)
1079                 return -EINVAL;
1080
1081         p->post_deps = kmalloc_array(num_deps, sizeof(*p->post_deps),
1082                                      GFP_KERNEL);
1083         p->num_post_deps = 0;
1084
1085         if (!p->post_deps)
1086                 return -ENOMEM;
1087
1088
1089         for (i = 0; i < num_deps; ++i) {
1090                 p->post_deps[i].syncobj =
1091                         drm_syncobj_find(p->filp, deps[i].handle);
1092                 if (!p->post_deps[i].syncobj)
1093                         return -EINVAL;
1094                 p->post_deps[i].chain = NULL;
1095                 p->post_deps[i].point = 0;
1096                 p->num_post_deps++;
1097         }
1098
1099         return 0;
1100 }
1101
1102
1103 static int amdgpu_cs_process_syncobj_timeline_out_dep(struct amdgpu_cs_parser *p,
1104                                                       struct amdgpu_cs_chunk *chunk)
1105 {
1106         struct drm_amdgpu_cs_chunk_syncobj *syncobj_deps;
1107         unsigned num_deps;
1108         int i;
1109
1110         syncobj_deps = (struct drm_amdgpu_cs_chunk_syncobj *)chunk->kdata;
1111         num_deps = chunk->length_dw * 4 /
1112                 sizeof(struct drm_amdgpu_cs_chunk_syncobj);
1113
1114         if (p->post_deps)
1115                 return -EINVAL;
1116
1117         p->post_deps = kmalloc_array(num_deps, sizeof(*p->post_deps),
1118                                      GFP_KERNEL);
1119         p->num_post_deps = 0;
1120
1121         if (!p->post_deps)
1122                 return -ENOMEM;
1123
1124         for (i = 0; i < num_deps; ++i) {
1125                 struct amdgpu_cs_post_dep *dep = &p->post_deps[i];
1126
1127                 dep->chain = NULL;
1128                 if (syncobj_deps[i].point) {
1129                         dep->chain = dma_fence_chain_alloc();
1130                         if (!dep->chain)
1131                                 return -ENOMEM;
1132                 }
1133
1134                 dep->syncobj = drm_syncobj_find(p->filp,
1135                                                 syncobj_deps[i].handle);
1136                 if (!dep->syncobj) {
1137                         dma_fence_chain_free(dep->chain);
1138                         return -EINVAL;
1139                 }
1140                 dep->point = syncobj_deps[i].point;
1141                 p->num_post_deps++;
1142         }
1143
1144         return 0;
1145 }
1146
1147 static int amdgpu_cs_dependencies(struct amdgpu_device *adev,
1148                                   struct amdgpu_cs_parser *p)
1149 {
1150         int i, r;
1151
1152         for (i = 0; i < p->nchunks; ++i) {
1153                 struct amdgpu_cs_chunk *chunk;
1154
1155                 chunk = &p->chunks[i];
1156
1157                 switch (chunk->chunk_id) {
1158                 case AMDGPU_CHUNK_ID_DEPENDENCIES:
1159                 case AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES:
1160                         r = amdgpu_cs_process_fence_dep(p, chunk);
1161                         if (r)
1162                                 return r;
1163                         break;
1164                 case AMDGPU_CHUNK_ID_SYNCOBJ_IN:
1165                         r = amdgpu_cs_process_syncobj_in_dep(p, chunk);
1166                         if (r)
1167                                 return r;
1168                         break;
1169                 case AMDGPU_CHUNK_ID_SYNCOBJ_OUT:
1170                         r = amdgpu_cs_process_syncobj_out_dep(p, chunk);
1171                         if (r)
1172                                 return r;
1173                         break;
1174                 case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT:
1175                         r = amdgpu_cs_process_syncobj_timeline_in_dep(p, chunk);
1176                         if (r)
1177                                 return r;
1178                         break;
1179                 case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL:
1180                         r = amdgpu_cs_process_syncobj_timeline_out_dep(p, chunk);
1181                         if (r)
1182                                 return r;
1183                         break;
1184                 }
1185         }
1186
1187         return 0;
1188 }
1189
1190 static void amdgpu_cs_post_dependencies(struct amdgpu_cs_parser *p)
1191 {
1192         int i;
1193
1194         for (i = 0; i < p->num_post_deps; ++i) {
1195                 if (p->post_deps[i].chain && p->post_deps[i].point) {
1196                         drm_syncobj_add_point(p->post_deps[i].syncobj,
1197                                               p->post_deps[i].chain,
1198                                               p->fence, p->post_deps[i].point);
1199                         p->post_deps[i].chain = NULL;
1200                 } else {
1201                         drm_syncobj_replace_fence(p->post_deps[i].syncobj,
1202                                                   p->fence);
1203                 }
1204         }
1205 }
1206
1207 static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
1208                             union drm_amdgpu_cs *cs)
1209 {
1210         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
1211         struct drm_sched_entity *entity = p->entity;
1212         struct amdgpu_bo_list_entry *e;
1213         struct amdgpu_job *job;
1214         uint64_t seq;
1215         int r;
1216
1217         job = p->job;
1218         p->job = NULL;
1219
1220         r = drm_sched_job_init(&job->base, entity, &fpriv->vm);
1221         if (r)
1222                 goto error_unlock;
1223
1224         drm_sched_job_arm(&job->base);
1225
1226         /* No memory allocation is allowed while holding the notifier lock.
1227          * The lock is held until amdgpu_cs_submit is finished and fence is
1228          * added to BOs.
1229          */
1230         mutex_lock(&p->adev->notifier_lock);
1231
1232         /* If userptr are invalidated after amdgpu_cs_parser_bos(), return
1233          * -EAGAIN, drmIoctl in libdrm will restart the amdgpu_cs_ioctl.
1234          */
1235         amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) {
1236                 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
1237
1238                 r |= !amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm);
1239         }
1240         if (r) {
1241                 r = -EAGAIN;
1242                 goto error_abort;
1243         }
1244
1245         p->fence = dma_fence_get(&job->base.s_fence->finished);
1246
1247         amdgpu_ctx_add_fence(p->ctx, entity, p->fence, &seq);
1248         amdgpu_cs_post_dependencies(p);
1249
1250         if ((job->preamble_status & AMDGPU_PREAMBLE_IB_PRESENT) &&
1251             !p->ctx->preamble_presented) {
1252                 job->preamble_status |= AMDGPU_PREAMBLE_IB_PRESENT_FIRST;
1253                 p->ctx->preamble_presented = true;
1254         }
1255
1256         cs->out.handle = seq;
1257         job->uf_sequence = seq;
1258
1259         amdgpu_job_free_resources(job);
1260
1261         trace_amdgpu_cs_ioctl(job);
1262         amdgpu_vm_bo_trace_cs(&fpriv->vm, &p->ticket);
1263         drm_sched_entity_push_job(&job->base);
1264
1265         amdgpu_vm_move_to_lru_tail(p->adev, &fpriv->vm);
1266
1267         amdgpu_bo_list_for_each_entry(e, p->bo_list) {
1268                 struct dma_resv *resv = e->tv.bo->base.resv;
1269                 struct dma_fence_chain *chain = e->chain;
1270
1271                 if (!chain)
1272                         continue;
1273
1274                 /*
1275                  * Work around dma_resv shortcommings by wrapping up the
1276                  * submission in a dma_fence_chain and add it as exclusive
1277                  * fence.
1278                  */
1279                 dma_fence_chain_init(chain, dma_resv_excl_fence(resv),
1280                                      dma_fence_get(p->fence), 1);
1281
1282                 rcu_assign_pointer(resv->fence_excl, &chain->base);
1283                 e->chain = NULL;
1284         }
1285
1286         ttm_eu_fence_buffer_objects(&p->ticket, &p->validated, p->fence);
1287         mutex_unlock(&p->adev->notifier_lock);
1288
1289         return 0;
1290
1291 error_abort:
1292         drm_sched_job_cleanup(&job->base);
1293         mutex_unlock(&p->adev->notifier_lock);
1294
1295 error_unlock:
1296         amdgpu_job_free(job);
1297         return r;
1298 }
1299
1300 static void trace_amdgpu_cs_ibs(struct amdgpu_cs_parser *parser)
1301 {
1302         int i;
1303
1304         if (!trace_amdgpu_cs_enabled())
1305                 return;
1306
1307         for (i = 0; i < parser->job->num_ibs; i++)
1308                 trace_amdgpu_cs(parser, i);
1309 }
1310
1311 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
1312 {
1313         struct amdgpu_device *adev = drm_to_adev(dev);
1314         union drm_amdgpu_cs *cs = data;
1315         struct amdgpu_cs_parser parser = {};
1316         bool reserved_buffers = false;
1317         int r;
1318
1319         if (amdgpu_ras_intr_triggered())
1320                 return -EHWPOISON;
1321
1322         if (!adev->accel_working)
1323                 return -EBUSY;
1324
1325         parser.adev = adev;
1326         parser.filp = filp;
1327
1328         r = amdgpu_cs_parser_init(&parser, data);
1329         if (r) {
1330                 if (printk_ratelimit())
1331                         DRM_ERROR("Failed to initialize parser %d!\n", r);
1332                 goto out;
1333         }
1334
1335         r = amdgpu_cs_ib_fill(adev, &parser);
1336         if (r)
1337                 goto out;
1338
1339         r = amdgpu_cs_dependencies(adev, &parser);
1340         if (r) {
1341                 DRM_ERROR("Failed in the dependencies handling %d!\n", r);
1342                 goto out;
1343         }
1344
1345         r = amdgpu_cs_parser_bos(&parser, data);
1346         if (r) {
1347                 if (r == -ENOMEM)
1348                         DRM_ERROR("Not enough memory for command submission!\n");
1349                 else if (r != -ERESTARTSYS && r != -EAGAIN)
1350                         DRM_ERROR("Failed to process the buffer list %d!\n", r);
1351                 goto out;
1352         }
1353
1354         reserved_buffers = true;
1355
1356         trace_amdgpu_cs_ibs(&parser);
1357
1358         r = amdgpu_cs_vm_handling(&parser);
1359         if (r)
1360                 goto out;
1361
1362         r = amdgpu_cs_submit(&parser, cs);
1363
1364 out:
1365         amdgpu_cs_parser_fini(&parser, r, reserved_buffers);
1366
1367         return r;
1368 }
1369
1370 /**
1371  * amdgpu_cs_wait_ioctl - wait for a command submission to finish
1372  *
1373  * @dev: drm device
1374  * @data: data from userspace
1375  * @filp: file private
1376  *
1377  * Wait for the command submission identified by handle to finish.
1378  */
1379 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data,
1380                          struct drm_file *filp)
1381 {
1382         union drm_amdgpu_wait_cs *wait = data;
1383         unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout);
1384         struct drm_sched_entity *entity;
1385         struct amdgpu_ctx *ctx;
1386         struct dma_fence *fence;
1387         long r;
1388
1389         ctx = amdgpu_ctx_get(filp->driver_priv, wait->in.ctx_id);
1390         if (ctx == NULL)
1391                 return -EINVAL;
1392
1393         r = amdgpu_ctx_get_entity(ctx, wait->in.ip_type, wait->in.ip_instance,
1394                                   wait->in.ring, &entity);
1395         if (r) {
1396                 amdgpu_ctx_put(ctx);
1397                 return r;
1398         }
1399
1400         fence = amdgpu_ctx_get_fence(ctx, entity, wait->in.handle);
1401         if (IS_ERR(fence))
1402                 r = PTR_ERR(fence);
1403         else if (fence) {
1404                 r = dma_fence_wait_timeout(fence, true, timeout);
1405                 if (r > 0 && fence->error)
1406                         r = fence->error;
1407                 dma_fence_put(fence);
1408         } else
1409                 r = 1;
1410
1411         amdgpu_ctx_put(ctx);
1412         if (r < 0)
1413                 return r;
1414
1415         memset(wait, 0, sizeof(*wait));
1416         wait->out.status = (r == 0);
1417
1418         return 0;
1419 }
1420
1421 /**
1422  * amdgpu_cs_get_fence - helper to get fence from drm_amdgpu_fence
1423  *
1424  * @adev: amdgpu device
1425  * @filp: file private
1426  * @user: drm_amdgpu_fence copied from user space
1427  */
1428 static struct dma_fence *amdgpu_cs_get_fence(struct amdgpu_device *adev,
1429                                              struct drm_file *filp,
1430                                              struct drm_amdgpu_fence *user)
1431 {
1432         struct drm_sched_entity *entity;
1433         struct amdgpu_ctx *ctx;
1434         struct dma_fence *fence;
1435         int r;
1436
1437         ctx = amdgpu_ctx_get(filp->driver_priv, user->ctx_id);
1438         if (ctx == NULL)
1439                 return ERR_PTR(-EINVAL);
1440
1441         r = amdgpu_ctx_get_entity(ctx, user->ip_type, user->ip_instance,
1442                                   user->ring, &entity);
1443         if (r) {
1444                 amdgpu_ctx_put(ctx);
1445                 return ERR_PTR(r);
1446         }
1447
1448         fence = amdgpu_ctx_get_fence(ctx, entity, user->seq_no);
1449         amdgpu_ctx_put(ctx);
1450
1451         return fence;
1452 }
1453
1454 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
1455                                     struct drm_file *filp)
1456 {
1457         struct amdgpu_device *adev = drm_to_adev(dev);
1458         union drm_amdgpu_fence_to_handle *info = data;
1459         struct dma_fence *fence;
1460         struct drm_syncobj *syncobj;
1461         struct sync_file *sync_file;
1462         int fd, r;
1463
1464         fence = amdgpu_cs_get_fence(adev, filp, &info->in.fence);
1465         if (IS_ERR(fence))
1466                 return PTR_ERR(fence);
1467
1468         if (!fence)
1469                 fence = dma_fence_get_stub();
1470
1471         switch (info->in.what) {
1472         case AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ:
1473                 r = drm_syncobj_create(&syncobj, 0, fence);
1474                 dma_fence_put(fence);
1475                 if (r)
1476                         return r;
1477                 r = drm_syncobj_get_handle(filp, syncobj, &info->out.handle);
1478                 drm_syncobj_put(syncobj);
1479                 return r;
1480
1481         case AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD:
1482                 r = drm_syncobj_create(&syncobj, 0, fence);
1483                 dma_fence_put(fence);
1484                 if (r)
1485                         return r;
1486                 r = drm_syncobj_get_fd(syncobj, (int *)&info->out.handle);
1487                 drm_syncobj_put(syncobj);
1488                 return r;
1489
1490         case AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD:
1491                 fd = get_unused_fd_flags(O_CLOEXEC);
1492                 if (fd < 0) {
1493                         dma_fence_put(fence);
1494                         return fd;
1495                 }
1496
1497                 sync_file = sync_file_create(fence);
1498                 dma_fence_put(fence);
1499                 if (!sync_file) {
1500                         put_unused_fd(fd);
1501                         return -ENOMEM;
1502                 }
1503
1504                 fd_install(fd, sync_file->file);
1505                 info->out.handle = fd;
1506                 return 0;
1507
1508         default:
1509                 return -EINVAL;
1510         }
1511 }
1512
1513 /**
1514  * amdgpu_cs_wait_all_fences - wait on all fences to signal
1515  *
1516  * @adev: amdgpu device
1517  * @filp: file private
1518  * @wait: wait parameters
1519  * @fences: array of drm_amdgpu_fence
1520  */
1521 static int amdgpu_cs_wait_all_fences(struct amdgpu_device *adev,
1522                                      struct drm_file *filp,
1523                                      union drm_amdgpu_wait_fences *wait,
1524                                      struct drm_amdgpu_fence *fences)
1525 {
1526         uint32_t fence_count = wait->in.fence_count;
1527         unsigned int i;
1528         long r = 1;
1529
1530         for (i = 0; i < fence_count; i++) {
1531                 struct dma_fence *fence;
1532                 unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout_ns);
1533
1534                 fence = amdgpu_cs_get_fence(adev, filp, &fences[i]);
1535                 if (IS_ERR(fence))
1536                         return PTR_ERR(fence);
1537                 else if (!fence)
1538                         continue;
1539
1540                 r = dma_fence_wait_timeout(fence, true, timeout);
1541                 dma_fence_put(fence);
1542                 if (r < 0)
1543                         return r;
1544
1545                 if (r == 0)
1546                         break;
1547
1548                 if (fence->error)
1549                         return fence->error;
1550         }
1551
1552         memset(wait, 0, sizeof(*wait));
1553         wait->out.status = (r > 0);
1554
1555         return 0;
1556 }
1557
1558 /**
1559  * amdgpu_cs_wait_any_fence - wait on any fence to signal
1560  *
1561  * @adev: amdgpu device
1562  * @filp: file private
1563  * @wait: wait parameters
1564  * @fences: array of drm_amdgpu_fence
1565  */
1566 static int amdgpu_cs_wait_any_fence(struct amdgpu_device *adev,
1567                                     struct drm_file *filp,
1568                                     union drm_amdgpu_wait_fences *wait,
1569                                     struct drm_amdgpu_fence *fences)
1570 {
1571         unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout_ns);
1572         uint32_t fence_count = wait->in.fence_count;
1573         uint32_t first = ~0;
1574         struct dma_fence **array;
1575         unsigned int i;
1576         long r;
1577
1578         /* Prepare the fence array */
1579         array = kcalloc(fence_count, sizeof(struct dma_fence *), GFP_KERNEL);
1580
1581         if (array == NULL)
1582                 return -ENOMEM;
1583
1584         for (i = 0; i < fence_count; i++) {
1585                 struct dma_fence *fence;
1586
1587                 fence = amdgpu_cs_get_fence(adev, filp, &fences[i]);
1588                 if (IS_ERR(fence)) {
1589                         r = PTR_ERR(fence);
1590                         goto err_free_fence_array;
1591                 } else if (fence) {
1592                         array[i] = fence;
1593                 } else { /* NULL, the fence has been already signaled */
1594                         r = 1;
1595                         first = i;
1596                         goto out;
1597                 }
1598         }
1599
1600         r = dma_fence_wait_any_timeout(array, fence_count, true, timeout,
1601                                        &first);
1602         if (r < 0)
1603                 goto err_free_fence_array;
1604
1605 out:
1606         memset(wait, 0, sizeof(*wait));
1607         wait->out.status = (r > 0);
1608         wait->out.first_signaled = first;
1609
1610         if (first < fence_count && array[first])
1611                 r = array[first]->error;
1612         else
1613                 r = 0;
1614
1615 err_free_fence_array:
1616         for (i = 0; i < fence_count; i++)
1617                 dma_fence_put(array[i]);
1618         kfree(array);
1619
1620         return r;
1621 }
1622
1623 /**
1624  * amdgpu_cs_wait_fences_ioctl - wait for multiple command submissions to finish
1625  *
1626  * @dev: drm device
1627  * @data: data from userspace
1628  * @filp: file private
1629  */
1630 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
1631                                 struct drm_file *filp)
1632 {
1633         struct amdgpu_device *adev = drm_to_adev(dev);
1634         union drm_amdgpu_wait_fences *wait = data;
1635         uint32_t fence_count = wait->in.fence_count;
1636         struct drm_amdgpu_fence *fences_user;
1637         struct drm_amdgpu_fence *fences;
1638         int r;
1639
1640         /* Get the fences from userspace */
1641         fences = kmalloc_array(fence_count, sizeof(struct drm_amdgpu_fence),
1642                         GFP_KERNEL);
1643         if (fences == NULL)
1644                 return -ENOMEM;
1645
1646         fences_user = u64_to_user_ptr(wait->in.fences);
1647         if (copy_from_user(fences, fences_user,
1648                 sizeof(struct drm_amdgpu_fence) * fence_count)) {
1649                 r = -EFAULT;
1650                 goto err_free_fences;
1651         }
1652
1653         if (wait->in.wait_all)
1654                 r = amdgpu_cs_wait_all_fences(adev, filp, wait, fences);
1655         else
1656                 r = amdgpu_cs_wait_any_fence(adev, filp, wait, fences);
1657
1658 err_free_fences:
1659         kfree(fences);
1660
1661         return r;
1662 }
1663
1664 /**
1665  * amdgpu_cs_find_mapping - find bo_va for VM address
1666  *
1667  * @parser: command submission parser context
1668  * @addr: VM address
1669  * @bo: resulting BO of the mapping found
1670  * @map: Placeholder to return found BO mapping
1671  *
1672  * Search the buffer objects in the command submission context for a certain
1673  * virtual memory address. Returns allocation structure when found, NULL
1674  * otherwise.
1675  */
1676 int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
1677                            uint64_t addr, struct amdgpu_bo **bo,
1678                            struct amdgpu_bo_va_mapping **map)
1679 {
1680         struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
1681         struct ttm_operation_ctx ctx = { false, false };
1682         struct amdgpu_vm *vm = &fpriv->vm;
1683         struct amdgpu_bo_va_mapping *mapping;
1684         int r;
1685
1686         addr /= AMDGPU_GPU_PAGE_SIZE;
1687
1688         mapping = amdgpu_vm_bo_lookup_mapping(vm, addr);
1689         if (!mapping || !mapping->bo_va || !mapping->bo_va->base.bo)
1690                 return -EINVAL;
1691
1692         *bo = mapping->bo_va->base.bo;
1693         *map = mapping;
1694
1695         /* Double check that the BO is reserved by this CS */
1696         if (dma_resv_locking_ctx((*bo)->tbo.base.resv) != &parser->ticket)
1697                 return -EINVAL;
1698
1699         if (!((*bo)->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)) {
1700                 (*bo)->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
1701                 amdgpu_bo_placement_from_domain(*bo, (*bo)->allowed_domains);
1702                 r = ttm_bo_validate(&(*bo)->tbo, &(*bo)->placement, &ctx);
1703                 if (r)
1704                         return r;
1705         }
1706
1707         return amdgpu_ttm_alloc_gart(&(*bo)->tbo);
1708 }