2 * Copyright 2018 Advanced Micro Devices, Inc.
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11 * the following conditions:
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21 * The above copyright notice and this permission notice (including the
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26 #ifndef __AMDGPU_GMC_H__
27 #define __AMDGPU_GMC_H__
29 #include <linux/types.h>
31 #include "amdgpu_irq.h"
33 /* VA hole for 48bit addresses on Vega10 */
34 #define AMDGPU_GMC_HOLE_START 0x0000800000000000ULL
35 #define AMDGPU_GMC_HOLE_END 0xffff800000000000ULL
38 * Hardware is programmed as if the hole doesn't exists with start and end
41 * This mask is used to remove the upper 16bits of the VA and so come up with
42 * the linear addr value.
44 #define AMDGPU_GMC_HOLE_MASK 0x0000ffffffffffffULL
49 * VMHUB structures, functions & helpers
52 uint32_t ctx0_ptb_addr_lo32;
53 uint32_t ctx0_ptb_addr_hi32;
54 uint32_t vm_inv_eng0_req;
55 uint32_t vm_inv_eng0_ack;
56 uint32_t vm_context0_cntl;
57 uint32_t vm_l2_pro_fault_status;
58 uint32_t vm_l2_pro_fault_cntl;
62 * GPU MC structures, functions & helpers
64 struct amdgpu_gmc_funcs {
65 /* flush the vm tlb via mmio */
66 void (*flush_gpu_tlb)(struct amdgpu_device *adev,
67 uint32_t vmid, uint32_t flush_type);
68 /* flush the vm tlb via ring */
69 uint64_t (*emit_flush_gpu_tlb)(struct amdgpu_ring *ring, unsigned vmid,
71 /* Change the VMID -> PASID mapping */
72 void (*emit_pasid_mapping)(struct amdgpu_ring *ring, unsigned vmid,
74 /* write pte/pde updates using the cpu */
75 int (*set_pte_pde)(struct amdgpu_device *adev,
76 void *cpu_pt_addr, /* cpu addr of page table */
77 uint32_t gpu_page_idx, /* pte/pde to update */
78 uint64_t addr, /* addr to write into pte/pde */
79 uint64_t flags); /* access flags */
80 /* enable/disable PRT support */
81 void (*set_prt)(struct amdgpu_device *adev, bool enable);
82 /* set pte flags based per asic */
83 uint64_t (*get_vm_pte_flags)(struct amdgpu_device *adev,
85 /* get the pde for a given mc addr */
86 void (*get_vm_pde)(struct amdgpu_device *adev, int level,
87 u64 *dst, u64 *flags);
94 /* fixed per family */
95 u64 node_segment_size;
96 /* physical node (0-3) */
97 unsigned physical_node_id;
98 /* number of nodes (0-4) */
99 unsigned num_physical_nodes;
100 /* gpu list in the same hive */
101 struct list_head head;
105 resource_size_t aper_size;
106 resource_size_t aper_base;
107 /* for some chips with <= 32MB we need to lie
108 * about vram size near mc fb location */
110 u64 visible_vram_size;
119 /* FB region , it's same as local vram region in single GPU, in XGMI
120 * configuration, this region covers all GPUs in the same hive ,
121 * each GPU in the hive has the same view of this FB region .
122 * GPU0's vram starts at offset (0 * segment size) ,
123 * GPU1 starts at offset (1 * segment size), etc.
131 const struct firmware *fw; /* MC firmware */
133 struct amdgpu_irq_src vm_fault;
135 uint32_t srbm_soft_reset;
137 uint64_t stolen_size;
139 u64 shared_aperture_start;
140 u64 shared_aperture_end;
141 u64 private_aperture_start;
142 u64 private_aperture_end;
143 /* protects concurrent invalidation */
144 spinlock_t invalidate_lock;
145 bool translate_further;
146 struct kfd_vm_fault_info *vm_fault_info;
147 atomic_t vm_fault_info_updated;
149 const struct amdgpu_gmc_funcs *gmc_funcs;
151 struct amdgpu_xgmi xgmi;
154 #define amdgpu_gmc_flush_gpu_tlb(adev, vmid, type) (adev)->gmc.gmc_funcs->flush_gpu_tlb((adev), (vmid), (type))
155 #define amdgpu_gmc_emit_flush_gpu_tlb(r, vmid, addr) (r)->adev->gmc.gmc_funcs->emit_flush_gpu_tlb((r), (vmid), (addr))
156 #define amdgpu_gmc_emit_pasid_mapping(r, vmid, pasid) (r)->adev->gmc.gmc_funcs->emit_pasid_mapping((r), (vmid), (pasid))
157 #define amdgpu_gmc_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gmc.gmc_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
158 #define amdgpu_gmc_get_vm_pde(adev, level, dst, flags) (adev)->gmc.gmc_funcs->get_vm_pde((adev), (level), (dst), (flags))
159 #define amdgpu_gmc_get_pte_flags(adev, flags) (adev)->gmc.gmc_funcs->get_vm_pte_flags((adev),(flags))
162 * amdgpu_gmc_vram_full_visible - Check if full VRAM is visible through the BAR
164 * @adev: amdgpu_device pointer
167 * True if full VRAM is visible through the BAR
169 static inline bool amdgpu_gmc_vram_full_visible(struct amdgpu_gmc *gmc)
171 WARN_ON(gmc->real_vram_size < gmc->visible_vram_size);
173 return (gmc->real_vram_size == gmc->visible_vram_size);
177 * amdgpu_gmc_sign_extend - sign extend the given gmc address
179 * @addr: address to extend
181 static inline uint64_t amdgpu_gmc_sign_extend(uint64_t addr)
183 if (addr >= AMDGPU_GMC_HOLE_START)
184 addr |= AMDGPU_GMC_HOLE_END;
189 void amdgpu_gmc_get_pde_for_bo(struct amdgpu_bo *bo, int level,
190 uint64_t *addr, uint64_t *flags);
191 uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo);
192 uint64_t amdgpu_gmc_agp_addr(struct ttm_buffer_object *bo);
193 void amdgpu_gmc_vram_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc,
195 void amdgpu_gmc_gart_location(struct amdgpu_device *adev,
196 struct amdgpu_gmc *mc);
197 void amdgpu_gmc_agp_location(struct amdgpu_device *adev,
198 struct amdgpu_gmc *mc);