drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Author: Huang Rui
  23  *
  24  */
  25
  26 #include <linux/firmware.h>
  27 #include "drmP.h"
  28 #include "amdgpu.h"
  29 #include "amdgpu_psp.h"
  30 #include "amdgpu_ucode.h"
  31 #include "soc15_common.h"
  32 #include "psp_v3_1.h"
  33
  34 static void psp_set_funcs(struct amdgpu_device *adev);
  35
  36 static int psp_early_init(void *handle)
  37 {
  38         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  39
  40         psp_set_funcs(adev);
  41
  42         return 0;
  43 }
  44
  45 static int psp_sw_init(void *handle)
  46 {
  47         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  48         struct psp_context *psp = &adev->psp;
  49         int ret;
  50
  51         switch (adev->asic_type) {
  52         case CHIP_VEGA10:
  53                 psp->init_microcode = psp_v3_1_init_microcode;
  54                 psp->bootloader_load_sysdrv = psp_v3_1_bootloader_load_sysdrv;
  55                 psp->bootloader_load_sos = psp_v3_1_bootloader_load_sos;
  56                 psp->prep_cmd_buf = psp_v3_1_prep_cmd_buf;
  57                 psp->ring_init = psp_v3_1_ring_init;
  58                 psp->cmd_submit = psp_v3_1_cmd_submit;
  59                 psp->compare_sram_data = psp_v3_1_compare_sram_data;
  60                 psp->smu_reload_quirk = psp_v3_1_smu_reload_quirk;
  61                 break;
  62         default:
  63                 return -EINVAL;
  64         }
  65
  66         psp->adev = adev;
  67
  68         ret = psp_init_microcode(psp);
  69         if (ret) {
  70                 DRM_ERROR("Failed to load psp firmware!\n");
  71                 return ret;
  72         }
  73
  74         return 0;
  75 }
  76
  77 static int psp_sw_fini(void *handle)
  78 {
  79         return 0;
  80 }
  81
  82 int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
  83                  uint32_t reg_val, uint32_t mask, bool check_changed)
  84 {
  85         uint32_t val;
  86         int i;
  87         struct amdgpu_device *adev = psp->adev;
  88
  89         val = RREG32(reg_index);
  90
  91         for (i = 0; i < adev->usec_timeout; i++) {
  92                 if (check_changed) {
  93                         if (val != reg_val)
  94                                 return 0;
  95                 } else {
  96                         if ((val & mask) == reg_val)
  97                                 return 0;
  98                 }
  99                 udelay(1);
 100         }
 101
 102         return -ETIME;
 103 }
 104
 105 static int
 106 psp_cmd_submit_buf(struct psp_context *psp,
 107                    struct amdgpu_firmware_info *ucode,
 108                    struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr,
 109                    int index)
 110 {
 111         int ret;
 112         struct amdgpu_bo *cmd_buf_bo;
 113         uint64_t cmd_buf_mc_addr;
 114         struct psp_gfx_cmd_resp *cmd_buf_mem;
 115         struct amdgpu_device *adev = psp->adev;
 116
 117         ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE,
 118                                       AMDGPU_GEM_DOMAIN_VRAM,
 119                                       &cmd_buf_bo, &cmd_buf_mc_addr,
 120                                       (void **)&cmd_buf_mem);
 121         if (ret)
 122                 return ret;
 123
 124         memset(cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE);
 125
 126         memcpy(cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp));
 127
 128         ret = psp_cmd_submit(psp, ucode, cmd_buf_mc_addr,
 129                              fence_mc_addr, index);
 130
 131         while (*((unsigned int *)psp->fence_buf) != index) {
 132                 msleep(1);
 133         }
 134
 135         amdgpu_bo_free_kernel(&cmd_buf_bo,
 136                               &cmd_buf_mc_addr,
 137                               (void **)&cmd_buf_mem);
 138
 139         return ret;
 140 }
 141
 142 static void psp_prep_tmr_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 143                                  uint64_t tmr_mc, uint32_t size)
 144 {
 145         cmd->cmd_id = GFX_CMD_ID_SETUP_TMR;
 146         cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = (uint32_t)tmr_mc;
 147         cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = (uint32_t)(tmr_mc >> 32);
 148         cmd->cmd.cmd_setup_tmr.buf_size = size;
 149 }
 150
 151 /* Set up Trusted Memory Region */
 152 static int psp_tmr_init(struct psp_context *psp)
 153 {
 154         int ret;
 155
 156         /*
 157          * Allocate 3M memory aligned to 1M from Frame Buffer (local
 158          * physical).
 159          *
 160          * Note: this memory need be reserved till the driver
 161          * uninitializes.
 162          */
 163         ret = amdgpu_bo_create_kernel(psp->adev, 0x300000, 0x100000,
 164                                       AMDGPU_GEM_DOMAIN_VRAM,
 165                                       &psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf);
 166
 167         return ret;
 168 }
 169
 170 static int psp_tmr_load(struct psp_context *psp)
 171 {
 172         int ret;
 173         struct psp_gfx_cmd_resp *cmd;
 174
 175         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 176         if (!cmd)
 177                 return -ENOMEM;
 178
 179         psp_prep_tmr_cmd_buf(cmd, psp->tmr_mc_addr, 0x300000);
 180
 181         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 182                                  psp->fence_buf_mc_addr, 1);
 183         if (ret)
 184                 goto failed;
 185
 186         kfree(cmd);
 187
 188         return 0;
 189
 190 failed:
 191         kfree(cmd);
 192         return ret;
 193 }
 194
 195 static void psp_prep_asd_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 196                                  uint64_t asd_mc, uint64_t asd_mc_shared,
 197                                  uint32_t size, uint32_t shared_size)
 198 {
 199         cmd->cmd_id = GFX_CMD_ID_LOAD_ASD;
 200         cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(asd_mc);
 201         cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(asd_mc);
 202         cmd->cmd.cmd_load_ta.app_len = size;
 203
 204         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(asd_mc_shared);
 205         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(asd_mc_shared);
 206         cmd->cmd.cmd_load_ta.cmd_buf_len = shared_size;
 207 }
 208
 209 static int psp_asd_load(struct psp_context *psp)
 210 {
 211         int ret;
 212         struct amdgpu_bo *asd_shared_bo;
 213         uint64_t asd_shared_mc_addr;
 214         void *asd_shared_buf;
 215         struct psp_gfx_cmd_resp *cmd;
 216
 217         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 218         if (!cmd)
 219                 return -ENOMEM;
 220
 221         /*
 222          * Allocate 16k memory aligned to 4k from Frame Buffer (local
 223          * physical) for shared ASD <-> Driver
 224          */
 225         ret = amdgpu_bo_create_kernel(psp->adev, PSP_ASD_SHARED_MEM_SIZE, PAGE_SIZE,
 226                                       AMDGPU_GEM_DOMAIN_VRAM,
 227                                       &asd_shared_bo, &asd_shared_mc_addr, &asd_shared_buf);
 228         if (ret)
 229                 goto failed;
 230
 231         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 232         memcpy(psp->fw_pri_buf, psp->asd_start_addr, psp->asd_ucode_size);
 233
 234         psp_prep_asd_cmd_buf(cmd, psp->fw_pri_mc_addr, asd_shared_mc_addr,
 235                              psp->asd_ucode_size, PSP_ASD_SHARED_MEM_SIZE);
 236
 237         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 238                                  psp->fence_buf_mc_addr, 2);
 239         if (ret)
 240                 goto failed_mem;
 241
 242         amdgpu_bo_free_kernel(&asd_shared_bo, &asd_shared_mc_addr, &asd_shared_buf);
 243         kfree(cmd);
 244
 245         return 0;
 246
 247 failed_mem:
 248         amdgpu_bo_free_kernel(&asd_shared_bo, &asd_shared_mc_addr, &asd_shared_buf);
 249 failed:
 250         kfree(cmd);
 251         return ret;
 252 }
 253
 254 static int psp_load_fw(struct amdgpu_device *adev)
 255 {
 256         int ret;
 257         struct psp_gfx_cmd_resp *cmd;
 258         int i;
 259         struct amdgpu_firmware_info *ucode;
 260         struct psp_context *psp = &adev->psp;
 261
 262         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 263         if (!cmd)
 264                 return -ENOMEM;
 265
 266         ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG,
 267                                       AMDGPU_GEM_DOMAIN_GTT,
 268                                       &psp->fw_pri_bo,
 269                                       &psp->fw_pri_mc_addr,
 270                                       &psp->fw_pri_buf);
 271         if (ret)
 272                 goto failed;
 273
 274         ret = psp_bootloader_load_sysdrv(psp);
 275         if (ret)
 276                 goto failed_mem1;
 277
 278         ret = psp_bootloader_load_sos(psp);
 279         if (ret)
 280                 goto failed_mem1;
 281
 282         ret = psp_ring_init(psp, PSP_RING_TYPE__KM);
 283         if (ret)
 284                 goto failed_mem1;
 285
 286         ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE,
 287                                       AMDGPU_GEM_DOMAIN_VRAM,
 288                                       &psp->fence_buf_bo,
 289                                       &psp->fence_buf_mc_addr,
 290                                       &psp->fence_buf);
 291         if (ret)
 292                 goto failed_mem1;
 293
 294         memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE);
 295
 296         ret = psp_tmr_init(psp);
 297         if (ret)
 298                 goto failed_mem;
 299
 300         ret = psp_tmr_load(psp);
 301         if (ret)
 302                 goto failed_mem;
 303
 304         ret = psp_asd_load(psp);
 305         if (ret)
 306                 goto failed_mem;
 307
 308         for (i = 0; i < adev->firmware.max_ucodes; i++) {
 309                 ucode = &adev->firmware.ucode[i];
 310                 if (!ucode->fw)
 311                         continue;
 312
 313                 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
 314                     psp_smu_reload_quirk(psp))
 315                         continue;
 316
 317                 ret = psp_prep_cmd_buf(ucode, cmd);
 318                 if (ret)
 319                         goto failed_mem;
 320
 321                 ret = psp_cmd_submit_buf(psp, ucode, cmd,
 322                                          psp->fence_buf_mc_addr, i + 3);
 323                 if (ret)
 324                         goto failed_mem;
 325
 326 #if 0
 327                 /* check if firmware loaded sucessfully */
 328                 if (!amdgpu_psp_check_fw_loading_status(adev, i))
 329                         return -EINVAL;
 330 #endif
 331         }
 332
 333         amdgpu_bo_free_kernel(&psp->fence_buf_bo,
 334                               &psp->fence_buf_mc_addr, &psp->fence_buf);
 335         kfree(cmd);
 336
 337         return 0;
 338
 339 failed_mem:
 340         amdgpu_bo_free_kernel(&psp->fence_buf_bo,
 341                               &psp->fence_buf_mc_addr, &psp->fence_buf);
 342 failed_mem1:
 343         amdgpu_bo_free_kernel(&psp->fw_pri_bo,
 344                               &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
 345 failed:
 346         kfree(cmd);
 347         return ret;
 348 }
 349
 350 static int psp_hw_init(void *handle)
 351 {
 352         int ret;
 353         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 354
 355
 356         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
 357                 return 0;
 358
 359         mutex_lock(&adev->firmware.mutex);
 360         /*
 361          * This sequence is just used on hw_init only once, no need on
 362          * resume.
 363          */
 364         ret = amdgpu_ucode_init_bo(adev);
 365         if (ret)
 366                 goto failed;
 367
 368         ret = psp_load_fw(adev);
 369         if (ret) {
 370                 DRM_ERROR("PSP firmware loading failed\n");
 371                 goto failed;
 372         }
 373
 374         mutex_unlock(&adev->firmware.mutex);
 375         return 0;
 376
 377 failed:
 378         adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT;
 379         mutex_unlock(&adev->firmware.mutex);
 380         return -EINVAL;
 381 }
 382
 383 static int psp_hw_fini(void *handle)
 384 {
 385         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 386         struct psp_context *psp = &adev->psp;
 387
 388         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)
 389                 amdgpu_ucode_fini_bo(adev);
 390
 391         if (psp->tmr_buf)
 392                 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf);
 393
 394         if (psp->fw_pri_buf)
 395                 amdgpu_bo_free_kernel(&psp->fw_pri_bo,
 396                                       &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
 397
 398         return 0;
 399 }
 400
 401 static int psp_suspend(void *handle)
 402 {
 403         return 0;
 404 }
 405
 406 static int psp_resume(void *handle)
 407 {
 408         int ret;
 409         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 410
 411         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
 412                 return 0;
 413
 414         mutex_lock(&adev->firmware.mutex);
 415
 416         ret = psp_load_fw(adev);
 417         if (ret)
 418                 DRM_ERROR("PSP resume failed\n");
 419
 420         mutex_unlock(&adev->firmware.mutex);
 421
 422         return ret;
 423 }
 424
 425 static bool psp_check_fw_loading_status(struct amdgpu_device *adev,
 426                                         enum AMDGPU_UCODE_ID ucode_type)
 427 {
 428         struct amdgpu_firmware_info *ucode = NULL;
 429
 430         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
 431                 DRM_INFO("firmware is not loaded by PSP\n");
 432                 return true;
 433         }
 434
 435         if (!adev->firmware.fw_size)
 436                 return false;
 437
 438         ucode = &adev->firmware.ucode[ucode_type];
 439         if (!ucode->fw || !ucode->ucode_size)
 440                 return false;
 441
 442         return psp_compare_sram_data(&adev->psp, ucode, ucode_type);
 443 }
 444
 445 static int psp_set_clockgating_state(void *handle,
 446                                      enum amd_clockgating_state state)
 447 {
 448         return 0;
 449 }
 450
 451 static int psp_set_powergating_state(void *handle,
 452                                      enum amd_powergating_state state)
 453 {
 454         return 0;
 455 }
 456
 457 const struct amd_ip_funcs psp_ip_funcs = {
 458         .name = "psp",
 459         .early_init = psp_early_init,
 460         .late_init = NULL,
 461         .sw_init = psp_sw_init,
 462         .sw_fini = psp_sw_fini,
 463         .hw_init = psp_hw_init,
 464         .hw_fini = psp_hw_fini,
 465         .suspend = psp_suspend,
 466         .resume = psp_resume,
 467         .is_idle = NULL,
 468         .wait_for_idle = NULL,
 469         .soft_reset = NULL,
 470         .set_clockgating_state = psp_set_clockgating_state,
 471         .set_powergating_state = psp_set_powergating_state,
 472 };
 473
 474 static const struct amdgpu_psp_funcs psp_funcs = {
 475         .check_fw_loading_status = psp_check_fw_loading_status,
 476 };
 477
 478 static void psp_set_funcs(struct amdgpu_device *adev)
 479 {
 480         if (NULL == adev->firmware.funcs)
 481                 adev->firmware.funcs = &psp_funcs;
 482 }
 483
 484 const struct amdgpu_ip_block_version psp_v3_1_ip_block =
 485 {
 486         .type = AMD_IP_BLOCK_TYPE_PSP,
 487         .major = 3,
 488         .minor = 1,
 489         .rev = 0,
 490         .funcs = &psp_ip_funcs,
 491 };