drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  *
  23  */
  24 #ifndef _AMDGPU_RAS_H
  25 #define _AMDGPU_RAS_H
  26
  27 #include <linux/debugfs.h>
  28 #include <linux/list.h>
  29 #include "ta_ras_if.h"
  30 #include "amdgpu_ras_eeprom.h"
  31
  32 struct amdgpu_iv_entry;
  33
  34 #define AMDGPU_RAS_FLAG_INIT_BY_VBIOS           (0x1 << 0)
  35
  36 enum amdgpu_ras_block {
  37         AMDGPU_RAS_BLOCK__UMC = 0,
  38         AMDGPU_RAS_BLOCK__SDMA,
  39         AMDGPU_RAS_BLOCK__GFX,
  40         AMDGPU_RAS_BLOCK__MMHUB,
  41         AMDGPU_RAS_BLOCK__ATHUB,
  42         AMDGPU_RAS_BLOCK__PCIE_BIF,
  43         AMDGPU_RAS_BLOCK__HDP,
  44         AMDGPU_RAS_BLOCK__XGMI_WAFL,
  45         AMDGPU_RAS_BLOCK__DF,
  46         AMDGPU_RAS_BLOCK__SMN,
  47         AMDGPU_RAS_BLOCK__SEM,
  48         AMDGPU_RAS_BLOCK__MP0,
  49         AMDGPU_RAS_BLOCK__MP1,
  50         AMDGPU_RAS_BLOCK__FUSE,
  51         AMDGPU_RAS_BLOCK__MCA,
  52
  53         AMDGPU_RAS_BLOCK__LAST
  54 };
  55
  56 enum amdgpu_ras_mca_block {
  57         AMDGPU_RAS_MCA_BLOCK__MP0 = 0,
  58         AMDGPU_RAS_MCA_BLOCK__MP1,
  59         AMDGPU_RAS_MCA_BLOCK__MPIO,
  60         AMDGPU_RAS_MCA_BLOCK__IOHC,
  61
  62         AMDGPU_RAS_MCA_BLOCK__LAST
  63 };
  64
  65 #define AMDGPU_RAS_BLOCK_COUNT  AMDGPU_RAS_BLOCK__LAST
  66 #define AMDGPU_RAS_MCA_BLOCK_COUNT      AMDGPU_RAS_MCA_BLOCK__LAST
  67 #define AMDGPU_RAS_BLOCK_MASK   ((1ULL << AMDGPU_RAS_BLOCK_COUNT) - 1)
  68
  69 enum amdgpu_ras_gfx_subblock {
  70         /* CPC */
  71         AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_START = 0,
  72         AMDGPU_RAS_BLOCK__GFX_CPC_SCRATCH =
  73                 AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_START,
  74         AMDGPU_RAS_BLOCK__GFX_CPC_UCODE,
  75         AMDGPU_RAS_BLOCK__GFX_DC_STATE_ME1,
  76         AMDGPU_RAS_BLOCK__GFX_DC_CSINVOC_ME1,
  77         AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME1,
  78         AMDGPU_RAS_BLOCK__GFX_DC_STATE_ME2,
  79         AMDGPU_RAS_BLOCK__GFX_DC_CSINVOC_ME2,
  80         AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME2,
  81         AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_END =
  82                 AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME2,
  83         /* CPF */
  84         AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_START,
  85         AMDGPU_RAS_BLOCK__GFX_CPF_ROQ_ME2 =
  86                 AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_START,
  87         AMDGPU_RAS_BLOCK__GFX_CPF_ROQ_ME1,
  88         AMDGPU_RAS_BLOCK__GFX_CPF_TAG,
  89         AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_END = AMDGPU_RAS_BLOCK__GFX_CPF_TAG,
  90         /* CPG */
  91         AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_START,
  92         AMDGPU_RAS_BLOCK__GFX_CPG_DMA_ROQ =
  93                 AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_START,
  94         AMDGPU_RAS_BLOCK__GFX_CPG_DMA_TAG,
  95         AMDGPU_RAS_BLOCK__GFX_CPG_TAG,
  96         AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_END = AMDGPU_RAS_BLOCK__GFX_CPG_TAG,
  97         /* GDS */
  98         AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_START,
  99         AMDGPU_RAS_BLOCK__GFX_GDS_MEM = AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_START,
 100         AMDGPU_RAS_BLOCK__GFX_GDS_INPUT_QUEUE,
 101         AMDGPU_RAS_BLOCK__GFX_GDS_OA_PHY_CMD_RAM_MEM,
 102         AMDGPU_RAS_BLOCK__GFX_GDS_OA_PHY_DATA_RAM_MEM,
 103         AMDGPU_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM,
 104         AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_END =
 105                 AMDGPU_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM,
 106         /* SPI */
 107         AMDGPU_RAS_BLOCK__GFX_SPI_SR_MEM,
 108         /* SQ */
 109         AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_START,
 110         AMDGPU_RAS_BLOCK__GFX_SQ_SGPR = AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_START,
 111         AMDGPU_RAS_BLOCK__GFX_SQ_LDS_D,
 112         AMDGPU_RAS_BLOCK__GFX_SQ_LDS_I,
 113         AMDGPU_RAS_BLOCK__GFX_SQ_VGPR,
 114         AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_END = AMDGPU_RAS_BLOCK__GFX_SQ_VGPR,
 115         /* SQC (3 ranges) */
 116         AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_START,
 117         /* SQC range 0 */
 118         AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_START =
 119                 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_START,
 120         AMDGPU_RAS_BLOCK__GFX_SQC_INST_UTCL1_LFIFO =
 121                 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_START,
 122         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU0_WRITE_DATA_BUF,
 123         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU0_UTCL1_LFIFO,
 124         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU1_WRITE_DATA_BUF,
 125         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU1_UTCL1_LFIFO,
 126         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_WRITE_DATA_BUF,
 127         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO,
 128         AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_END =
 129                 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO,
 130         /* SQC range 1 */
 131         AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_START,
 132         AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_TAG_RAM =
 133                 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_START,
 134         AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO,
 135         AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_MISS_FIFO,
 136         AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_BANK_RAM,
 137         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_TAG_RAM,
 138         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_HIT_FIFO,
 139         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_MISS_FIFO,
 140         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM,
 141         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM,
 142         AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_END =
 143                 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM,
 144         /* SQC range 2 */
 145         AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_START,
 146         AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_TAG_RAM =
 147                 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_START,
 148         AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO,
 149         AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_MISS_FIFO,
 150         AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_BANK_RAM,
 151         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_TAG_RAM,
 152         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_HIT_FIFO,
 153         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_MISS_FIFO,
 154         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM,
 155         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM,
 156         AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_END =
 157                 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM,
 158         AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_END =
 159                 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_END,
 160         /* TA */
 161         AMDGPU_RAS_BLOCK__GFX_TA_INDEX_START,
 162         AMDGPU_RAS_BLOCK__GFX_TA_FS_DFIFO =
 163                 AMDGPU_RAS_BLOCK__GFX_TA_INDEX_START,
 164         AMDGPU_RAS_BLOCK__GFX_TA_FS_AFIFO,
 165         AMDGPU_RAS_BLOCK__GFX_TA_FL_LFIFO,
 166         AMDGPU_RAS_BLOCK__GFX_TA_FX_LFIFO,
 167         AMDGPU_RAS_BLOCK__GFX_TA_FS_CFIFO,
 168         AMDGPU_RAS_BLOCK__GFX_TA_INDEX_END = AMDGPU_RAS_BLOCK__GFX_TA_FS_CFIFO,
 169         /* TCA */
 170         AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_START,
 171         AMDGPU_RAS_BLOCK__GFX_TCA_HOLE_FIFO =
 172                 AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_START,
 173         AMDGPU_RAS_BLOCK__GFX_TCA_REQ_FIFO,
 174         AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_END =
 175                 AMDGPU_RAS_BLOCK__GFX_TCA_REQ_FIFO,
 176         /* TCC (5 sub-ranges) */
 177         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_START,
 178         /* TCC range 0 */
 179         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_START =
 180                 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_START,
 181         AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA =
 182                 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_START,
 183         AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_0_1,
 184         AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_0,
 185         AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_1,
 186         AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_0,
 187         AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_1,
 188         AMDGPU_RAS_BLOCK__GFX_TCC_HIGH_RATE_TAG,
 189         AMDGPU_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG,
 190         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_END =
 191                 AMDGPU_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG,
 192         /* TCC range 1 */
 193         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_START,
 194         AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_DEC =
 195                 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_START,
 196         AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER,
 197         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_END =
 198                 AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER,
 199         /* TCC range 2 */
 200         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_START,
 201         AMDGPU_RAS_BLOCK__GFX_TCC_RETURN_DATA =
 202                 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_START,
 203         AMDGPU_RAS_BLOCK__GFX_TCC_RETURN_CONTROL,
 204         AMDGPU_RAS_BLOCK__GFX_TCC_UC_ATOMIC_FIFO,
 205         AMDGPU_RAS_BLOCK__GFX_TCC_WRITE_RETURN,
 206         AMDGPU_RAS_BLOCK__GFX_TCC_WRITE_CACHE_READ,
 207         AMDGPU_RAS_BLOCK__GFX_TCC_SRC_FIFO,
 208         AMDGPU_RAS_BLOCK__GFX_TCC_SRC_FIFO_NEXT_RAM,
 209         AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO,
 210         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_END =
 211                 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO,
 212         /* TCC range 3 */
 213         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_START,
 214         AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO =
 215                 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_START,
 216         AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM,
 217         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_END =
 218                 AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM,
 219         /* TCC range 4 */
 220         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_START,
 221         AMDGPU_RAS_BLOCK__GFX_TCC_WRRET_TAG_WRITE_RETURN =
 222                 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_START,
 223         AMDGPU_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER,
 224         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_END =
 225                 AMDGPU_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER,
 226         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_END =
 227                 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_END,
 228         /* TCI */
 229         AMDGPU_RAS_BLOCK__GFX_TCI_WRITE_RAM,
 230         /* TCP */
 231         AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_START,
 232         AMDGPU_RAS_BLOCK__GFX_TCP_CACHE_RAM =
 233                 AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_START,
 234         AMDGPU_RAS_BLOCK__GFX_TCP_LFIFO_RAM,
 235         AMDGPU_RAS_BLOCK__GFX_TCP_CMD_FIFO,
 236         AMDGPU_RAS_BLOCK__GFX_TCP_VM_FIFO,
 237         AMDGPU_RAS_BLOCK__GFX_TCP_DB_RAM,
 238         AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO0,
 239         AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1,
 240         AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_END =
 241                 AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1,
 242         /* TD */
 243         AMDGPU_RAS_BLOCK__GFX_TD_INDEX_START,
 244         AMDGPU_RAS_BLOCK__GFX_TD_SS_FIFO_LO =
 245                 AMDGPU_RAS_BLOCK__GFX_TD_INDEX_START,
 246         AMDGPU_RAS_BLOCK__GFX_TD_SS_FIFO_HI,
 247         AMDGPU_RAS_BLOCK__GFX_TD_CS_FIFO,
 248         AMDGPU_RAS_BLOCK__GFX_TD_INDEX_END = AMDGPU_RAS_BLOCK__GFX_TD_CS_FIFO,
 249         /* EA (3 sub-ranges) */
 250         AMDGPU_RAS_BLOCK__GFX_EA_INDEX_START,
 251         /* EA range 0 */
 252         AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_START =
 253                 AMDGPU_RAS_BLOCK__GFX_EA_INDEX_START,
 254         AMDGPU_RAS_BLOCK__GFX_EA_DRAMRD_CMDMEM =
 255                 AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_START,
 256         AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_CMDMEM,
 257         AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_DATAMEM,
 258         AMDGPU_RAS_BLOCK__GFX_EA_RRET_TAGMEM,
 259         AMDGPU_RAS_BLOCK__GFX_EA_WRET_TAGMEM,
 260         AMDGPU_RAS_BLOCK__GFX_EA_GMIRD_CMDMEM,
 261         AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_CMDMEM,
 262         AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM,
 263         AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_END =
 264                 AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM,
 265         /* EA range 1 */
 266         AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_START,
 267         AMDGPU_RAS_BLOCK__GFX_EA_DRAMRD_PAGEMEM =
 268                 AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_START,
 269         AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_PAGEMEM,
 270         AMDGPU_RAS_BLOCK__GFX_EA_IORD_CMDMEM,
 271         AMDGPU_RAS_BLOCK__GFX_EA_IOWR_CMDMEM,
 272         AMDGPU_RAS_BLOCK__GFX_EA_IOWR_DATAMEM,
 273         AMDGPU_RAS_BLOCK__GFX_EA_GMIRD_PAGEMEM,
 274         AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM,
 275         AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_END =
 276                 AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM,
 277         /* EA range 2 */
 278         AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_START,
 279         AMDGPU_RAS_BLOCK__GFX_EA_MAM_D0MEM =
 280                 AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_START,
 281         AMDGPU_RAS_BLOCK__GFX_EA_MAM_D1MEM,
 282         AMDGPU_RAS_BLOCK__GFX_EA_MAM_D2MEM,
 283         AMDGPU_RAS_BLOCK__GFX_EA_MAM_D3MEM,
 284         AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_END =
 285                 AMDGPU_RAS_BLOCK__GFX_EA_MAM_D3MEM,
 286         AMDGPU_RAS_BLOCK__GFX_EA_INDEX_END =
 287                 AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_END,
 288         /* UTC VM L2 bank */
 289         AMDGPU_RAS_BLOCK__UTC_VML2_BANK_CACHE,
 290         /* UTC VM walker */
 291         AMDGPU_RAS_BLOCK__UTC_VML2_WALKER,
 292         /* UTC ATC L2 2MB cache */
 293         AMDGPU_RAS_BLOCK__UTC_ATCL2_CACHE_2M_BANK,
 294         /* UTC ATC L2 4KB cache */
 295         AMDGPU_RAS_BLOCK__UTC_ATCL2_CACHE_4K_BANK,
 296         AMDGPU_RAS_BLOCK__GFX_MAX
 297 };
 298
 299 enum amdgpu_ras_error_type {
 300         AMDGPU_RAS_ERROR__NONE                                                  = 0,
 301         AMDGPU_RAS_ERROR__PARITY                                                = 1,
 302         AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE                                    = 2,
 303         AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE                                   = 4,
 304         AMDGPU_RAS_ERROR__POISON                                                = 8,
 305 };
 306
 307 enum amdgpu_ras_ret {
 308         AMDGPU_RAS_SUCCESS = 0,
 309         AMDGPU_RAS_FAIL,
 310         AMDGPU_RAS_UE,
 311         AMDGPU_RAS_CE,
 312         AMDGPU_RAS_PT,
 313 };
 314
 315 struct ras_common_if {
 316         enum amdgpu_ras_block block;
 317         enum amdgpu_ras_error_type type;
 318         uint32_t sub_block_index;
 319         char name[32];
 320 };
 321
 322 #define MAX_UMC_CHANNEL_NUM 32
 323
 324 struct ecc_info_per_ch {
 325         uint16_t ce_count_lo_chip;
 326         uint16_t ce_count_hi_chip;
 327         uint64_t mca_umc_status;
 328         uint64_t mca_umc_addr;
 329 };
 330
 331 struct umc_ecc_info {
 332         struct ecc_info_per_ch ecc[MAX_UMC_CHANNEL_NUM];
 333 };
 334
 335 struct amdgpu_ras {
 336         /* ras infrastructure */
 337         /* for ras itself. */
 338         uint32_t features;
 339         struct list_head head;
 340         /* sysfs */
 341         struct device_attribute features_attr;
 342         struct bin_attribute badpages_attr;
 343         struct dentry *de_ras_eeprom_table;
 344         /* block array */
 345         struct ras_manager *objs;
 346
 347         /* gpu recovery */
 348         struct work_struct recovery_work;
 349         atomic_t in_recovery;
 350         struct amdgpu_device *adev;
 351         /* error handler data */
 352         struct ras_err_handler_data *eh_data;
 353         struct mutex recovery_lock;
 354
 355         uint32_t flags;
 356         bool reboot;
 357         struct amdgpu_ras_eeprom_control eeprom_control;
 358
 359         bool error_query_ready;
 360
 361         /* bad page count threshold */
 362         uint32_t bad_page_cnt_threshold;
 363
 364         /* disable ras error count harvest in recovery */
 365         bool disable_ras_err_cnt_harvest;
 366
 367         /* is poison mode supported */
 368         bool poison_supported;
 369
 370         /* RAS count errors delayed work */
 371         struct delayed_work ras_counte_delay_work;
 372         atomic_t ras_ue_count;
 373         atomic_t ras_ce_count;
 374
 375         /* record umc error info queried from smu */
 376         struct umc_ecc_info umc_ecc;
 377 };
 378
 379 struct ras_fs_data {
 380         char sysfs_name[32];
 381         char debugfs_name[32];
 382 };
 383
 384 struct ras_err_data {
 385         unsigned long ue_count;
 386         unsigned long ce_count;
 387         unsigned long err_addr_cnt;
 388         struct eeprom_table_record *err_addr;
 389 };
 390
 391 struct ras_err_handler_data {
 392         /* point to bad page records array */
 393         struct eeprom_table_record *bps;
 394         /* the count of entries */
 395         int count;
 396         /* the space can place new entries */
 397         int space_left;
 398 };
 399
 400 typedef int (*ras_ih_cb)(struct amdgpu_device *adev,
 401                 void *err_data,
 402                 struct amdgpu_iv_entry *entry);
 403
 404 struct ras_ih_data {
 405         /* interrupt bottom half */
 406         struct work_struct ih_work;
 407         int inuse;
 408         /* IP callback */
 409         ras_ih_cb cb;
 410         /* full of entries */
 411         unsigned char *ring;
 412         unsigned int ring_size;
 413         unsigned int element_size;
 414         unsigned int aligned_element_size;
 415         unsigned int rptr;
 416         unsigned int wptr;
 417 };
 418
 419 struct ras_manager {
 420         struct ras_common_if head;
 421         /* reference count */
 422         int use;
 423         /* ras block link */
 424         struct list_head node;
 425         /* the device */
 426         struct amdgpu_device *adev;
 427         /* sysfs */
 428         struct device_attribute sysfs_attr;
 429         int attr_inuse;
 430
 431         /* fs node name */
 432         struct ras_fs_data fs_data;
 433
 434         /* IH data */
 435         struct ras_ih_data ih_data;
 436
 437         struct ras_err_data err_data;
 438 };
 439
 440 struct ras_badpage {
 441         unsigned int bp;
 442         unsigned int size;
 443         unsigned int flags;
 444 };
 445
 446 /* interfaces for IP */
 447 struct ras_fs_if {
 448         struct ras_common_if head;
 449         const char* sysfs_name;
 450         char debugfs_name[32];
 451 };
 452
 453 struct ras_query_if {
 454         struct ras_common_if head;
 455         unsigned long ue_count;
 456         unsigned long ce_count;
 457 };
 458
 459 struct ras_inject_if {
 460         struct ras_common_if head;
 461         uint64_t address;
 462         uint64_t value;
 463 };
 464
 465 struct ras_cure_if {
 466         struct ras_common_if head;
 467         uint64_t address;
 468 };
 469
 470 struct ras_ih_if {
 471         struct ras_common_if head;
 472         ras_ih_cb cb;
 473 };
 474
 475 struct ras_dispatch_if {
 476         struct ras_common_if head;
 477         struct amdgpu_iv_entry *entry;
 478 };
 479
 480 struct ras_debug_if {
 481         union {
 482                 struct ras_common_if head;
 483                 struct ras_inject_if inject;
 484         };
 485         int op;
 486 };
 487
 488 struct amdgpu_ras_block_object {
 489         struct ras_common_if  ras_comm;
 490
 491         int (*ras_block_match)(struct amdgpu_ras_block_object *block_obj,
 492                                 enum amdgpu_ras_block block, uint32_t sub_block_index);
 493         int (*ras_late_init)(struct amdgpu_device *adev, struct ras_common_if *ras_block);
 494         void (*ras_fini)(struct amdgpu_device *adev);
 495         ras_ih_cb ras_cb;
 496         const struct amdgpu_ras_block_hw_ops *hw_ops;
 497 };
 498
 499 struct amdgpu_ras_block_hw_ops {
 500         int  (*ras_error_inject)(struct amdgpu_device *adev, void *inject_if);
 501         void (*query_ras_error_count)(struct amdgpu_device *adev, void *ras_error_status);
 502         void (*query_ras_error_status)(struct amdgpu_device *adev);
 503         void (*query_ras_error_address)(struct amdgpu_device *adev, void *ras_error_status);
 504         void (*reset_ras_error_count)(struct amdgpu_device *adev);
 505         void (*reset_ras_error_status)(struct amdgpu_device *adev);
 506 };
 507
 508 /* work flow
 509  * vbios
 510  * 1: ras feature enable (enabled by default)
 511  * psp
 512  * 2: ras framework init (in ip_init)
 513  * IP
 514  * 3: IH add
 515  * 4: debugfs/sysfs create
 516  * 5: query/inject
 517  * 6: debugfs/sysfs remove
 518  * 7: IH remove
 519  * 8: feature disable
 520  */
 521
 522
 523 int amdgpu_ras_recovery_init(struct amdgpu_device *adev);
 524
 525 void amdgpu_ras_resume(struct amdgpu_device *adev);
 526 void amdgpu_ras_suspend(struct amdgpu_device *adev);
 527
 528 int amdgpu_ras_query_error_count(struct amdgpu_device *adev,
 529                                  unsigned long *ce_count,
 530                                  unsigned long *ue_count);
 531
 532 /* error handling functions */
 533 int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
 534                 struct eeprom_table_record *bps, int pages);
 535
 536 int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev);
 537
 538 static inline enum ta_ras_block
 539 amdgpu_ras_block_to_ta(enum amdgpu_ras_block block) {
 540         switch (block) {
 541         case AMDGPU_RAS_BLOCK__UMC:
 542                 return TA_RAS_BLOCK__UMC;
 543         case AMDGPU_RAS_BLOCK__SDMA:
 544                 return TA_RAS_BLOCK__SDMA;
 545         case AMDGPU_RAS_BLOCK__GFX:
 546                 return TA_RAS_BLOCK__GFX;
 547         case AMDGPU_RAS_BLOCK__MMHUB:
 548                 return TA_RAS_BLOCK__MMHUB;
 549         case AMDGPU_RAS_BLOCK__ATHUB:
 550                 return TA_RAS_BLOCK__ATHUB;
 551         case AMDGPU_RAS_BLOCK__PCIE_BIF:
 552                 return TA_RAS_BLOCK__PCIE_BIF;
 553         case AMDGPU_RAS_BLOCK__HDP:
 554                 return TA_RAS_BLOCK__HDP;
 555         case AMDGPU_RAS_BLOCK__XGMI_WAFL:
 556                 return TA_RAS_BLOCK__XGMI_WAFL;
 557         case AMDGPU_RAS_BLOCK__DF:
 558                 return TA_RAS_BLOCK__DF;
 559         case AMDGPU_RAS_BLOCK__SMN:
 560                 return TA_RAS_BLOCK__SMN;
 561         case AMDGPU_RAS_BLOCK__SEM:
 562                 return TA_RAS_BLOCK__SEM;
 563         case AMDGPU_RAS_BLOCK__MP0:
 564                 return TA_RAS_BLOCK__MP0;
 565         case AMDGPU_RAS_BLOCK__MP1:
 566                 return TA_RAS_BLOCK__MP1;
 567         case AMDGPU_RAS_BLOCK__FUSE:
 568                 return TA_RAS_BLOCK__FUSE;
 569         case AMDGPU_RAS_BLOCK__MCA:
 570                 return TA_RAS_BLOCK__MCA;
 571         default:
 572                 WARN_ONCE(1, "RAS ERROR: unexpected block id %d\n", block);
 573                 return TA_RAS_BLOCK__UMC;
 574         }
 575 }
 576
 577 static inline enum ta_ras_error_type
 578 amdgpu_ras_error_to_ta(enum amdgpu_ras_error_type error) {
 579         switch (error) {
 580         case AMDGPU_RAS_ERROR__NONE:
 581                 return TA_RAS_ERROR__NONE;
 582         case AMDGPU_RAS_ERROR__PARITY:
 583                 return TA_RAS_ERROR__PARITY;
 584         case AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE:
 585                 return TA_RAS_ERROR__SINGLE_CORRECTABLE;
 586         case AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE:
 587                 return TA_RAS_ERROR__MULTI_UNCORRECTABLE;
 588         case AMDGPU_RAS_ERROR__POISON:
 589                 return TA_RAS_ERROR__POISON;
 590         default:
 591                 WARN_ONCE(1, "RAS ERROR: unexpected error type %d\n", error);
 592                 return TA_RAS_ERROR__NONE;
 593         }
 594 }
 595
 596 /* called in ip_init and ip_fini */
 597 int amdgpu_ras_init(struct amdgpu_device *adev);
 598 int amdgpu_ras_fini(struct amdgpu_device *adev);
 599 int amdgpu_ras_pre_fini(struct amdgpu_device *adev);
 600
 601 int amdgpu_ras_block_late_init(struct amdgpu_device *adev,
 602                         struct ras_common_if *ras_block);
 603
 604 void amdgpu_ras_block_late_fini(struct amdgpu_device *adev,
 605                           struct ras_common_if *ras_block);
 606
 607 int amdgpu_ras_feature_enable(struct amdgpu_device *adev,
 608                 struct ras_common_if *head, bool enable);
 609
 610 int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev,
 611                 struct ras_common_if *head, bool enable);
 612
 613 int amdgpu_ras_sysfs_create(struct amdgpu_device *adev,
 614                 struct ras_common_if *head);
 615
 616 int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev,
 617                 struct ras_common_if *head);
 618
 619 void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev);
 620
 621 int amdgpu_ras_query_error_status(struct amdgpu_device *adev,
 622                 struct ras_query_if *info);
 623
 624 int amdgpu_ras_reset_error_status(struct amdgpu_device *adev,
 625                 enum amdgpu_ras_block block);
 626
 627 int amdgpu_ras_error_inject(struct amdgpu_device *adev,
 628                 struct ras_inject_if *info);
 629
 630 int amdgpu_ras_interrupt_add_handler(struct amdgpu_device *adev,
 631                 struct ras_common_if *head);
 632
 633 int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev,
 634                 struct ras_common_if *head);
 635
 636 int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev,
 637                 struct ras_dispatch_if *info);
 638
 639 struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev,
 640                 struct ras_common_if *head);
 641
 642 extern atomic_t amdgpu_ras_in_intr;
 643
 644 static inline bool amdgpu_ras_intr_triggered(void)
 645 {
 646         return !!atomic_read(&amdgpu_ras_in_intr);
 647 }
 648
 649 static inline void amdgpu_ras_intr_cleared(void)
 650 {
 651         atomic_set(&amdgpu_ras_in_intr, 0);
 652 }
 653
 654 void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev);
 655
 656 void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready);
 657
 658 bool amdgpu_ras_need_emergency_restart(struct amdgpu_device *adev);
 659
 660 void amdgpu_release_ras_context(struct amdgpu_device *adev);
 661
 662 int amdgpu_persistent_edc_harvesting_supported(struct amdgpu_device *adev);
 663
 664 const char *get_ras_block_str(struct ras_common_if *ras_block);
 665
 666 bool amdgpu_ras_is_poison_mode_supported(struct amdgpu_device *adev);
 667
 668 int amdgpu_ras_is_supported(struct amdgpu_device *adev, unsigned int block);
 669
 670 int amdgpu_ras_reset_gpu(struct amdgpu_device *adev);
 671
 672 struct amdgpu_ras* amdgpu_ras_get_context(struct amdgpu_device *adev);
 673
 674 int amdgpu_ras_set_context(struct amdgpu_device *adev, struct amdgpu_ras *ras_con);
 675
 676 int amdgpu_ras_register_ras_block(struct amdgpu_device *adev,
 677                                 struct amdgpu_ras_block_object *ras_block_obj);
 678 #endif