drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <glisse@freedesktop.org>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32
  33 #include <linux/dma-mapping.h>
  34 #include <linux/iommu.h>
  35 #include <linux/hmm.h>
  36 #include <linux/pagemap.h>
  37 #include <linux/sched/task.h>
  38 #include <linux/seq_file.h>
  39 #include <linux/slab.h>
  40 #include <linux/swap.h>
  41 #include <linux/swiotlb.h>
  42
  43 #include <drm/ttm/ttm_bo_api.h>
  44 #include <drm/ttm/ttm_bo_driver.h>
  45 #include <drm/ttm/ttm_placement.h>
  46 #include <drm/ttm/ttm_module.h>
  47 #include <drm/ttm/ttm_page_alloc.h>
  48
  49 #include <drm/drm_debugfs.h>
  50 #include <drm/amdgpu_drm.h>
  51
  52 #include "amdgpu.h"
  53 #include "amdgpu_object.h"
  54 #include "amdgpu_trace.h"
  55 #include "amdgpu_amdkfd.h"
  56 #include "amdgpu_sdma.h"
  57 #include "amdgpu_ras.h"
  58 #include "bif/bif_4_1_d.h"
  59
  60 static int amdgpu_map_buffer(struct ttm_buffer_object *bo,
  61                              struct ttm_mem_reg *mem, unsigned num_pages,
  62                              uint64_t offset, unsigned window,
  63                              struct amdgpu_ring *ring,
  64                              uint64_t *addr);
  65
  66 static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev);
  67 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev);
  68
  69 static int amdgpu_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
  70 {
  71         return 0;
  72 }
  73
  74 /**
  75  * amdgpu_init_mem_type - Initialize a memory manager for a specific type of
  76  * memory request.
  77  *
  78  * @bdev: The TTM BO device object (contains a reference to amdgpu_device)
  79  * @type: The type of memory requested
  80  * @man: The memory type manager for each domain
  81  *
  82  * This is called by ttm_bo_init_mm() when a buffer object is being
  83  * initialized.
  84  */
  85 static int amdgpu_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
  86                                 struct ttm_mem_type_manager *man)
  87 {
  88         struct amdgpu_device *adev;
  89
  90         adev = amdgpu_ttm_adev(bdev);
  91
  92         switch (type) {
  93         case TTM_PL_SYSTEM:
  94                 /* System memory */
  95                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
  96                 man->available_caching = TTM_PL_MASK_CACHING;
  97                 man->default_caching = TTM_PL_FLAG_CACHED;
  98                 break;
  99         case TTM_PL_TT:
 100                 /* GTT memory  */
 101                 man->func = &amdgpu_gtt_mgr_func;
 102                 man->gpu_offset = adev->gmc.gart_start;
 103                 man->available_caching = TTM_PL_MASK_CACHING;
 104                 man->default_caching = TTM_PL_FLAG_CACHED;
 105                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
 106                 break;
 107         case TTM_PL_VRAM:
 108                 /* "On-card" video ram */
 109                 man->func = &amdgpu_vram_mgr_func;
 110                 man->gpu_offset = adev->gmc.vram_start;
 111                 man->flags = TTM_MEMTYPE_FLAG_FIXED |
 112                              TTM_MEMTYPE_FLAG_MAPPABLE;
 113                 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
 114                 man->default_caching = TTM_PL_FLAG_WC;
 115                 break;
 116         case AMDGPU_PL_GDS:
 117         case AMDGPU_PL_GWS:
 118         case AMDGPU_PL_OA:
 119                 /* On-chip GDS memory*/
 120                 man->func = &ttm_bo_manager_func;
 121                 man->gpu_offset = 0;
 122                 man->flags = TTM_MEMTYPE_FLAG_FIXED | TTM_MEMTYPE_FLAG_CMA;
 123                 man->available_caching = TTM_PL_FLAG_UNCACHED;
 124                 man->default_caching = TTM_PL_FLAG_UNCACHED;
 125                 break;
 126         default:
 127                 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
 128                 return -EINVAL;
 129         }
 130         return 0;
 131 }
 132
 133 /**
 134  * amdgpu_evict_flags - Compute placement flags
 135  *
 136  * @bo: The buffer object to evict
 137  * @placement: Possible destination(s) for evicted BO
 138  *
 139  * Fill in placement data when ttm_bo_evict() is called
 140  */
 141 static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
 142                                 struct ttm_placement *placement)
 143 {
 144         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 145         struct amdgpu_bo *abo;
 146         static const struct ttm_place placements = {
 147                 .fpfn = 0,
 148                 .lpfn = 0,
 149                 .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM
 150         };
 151
 152         /* Don't handle scatter gather BOs */
 153         if (bo->type == ttm_bo_type_sg) {
 154                 placement->num_placement = 0;
 155                 placement->num_busy_placement = 0;
 156                 return;
 157         }
 158
 159         /* Object isn't an AMDGPU object so ignore */
 160         if (!amdgpu_bo_is_amdgpu_bo(bo)) {
 161                 placement->placement = &placements;
 162                 placement->busy_placement = &placements;
 163                 placement->num_placement = 1;
 164                 placement->num_busy_placement = 1;
 165                 return;
 166         }
 167
 168         abo = ttm_to_amdgpu_bo(bo);
 169         switch (bo->mem.mem_type) {
 170         case AMDGPU_PL_GDS:
 171         case AMDGPU_PL_GWS:
 172         case AMDGPU_PL_OA:
 173                 placement->num_placement = 0;
 174                 placement->num_busy_placement = 0;
 175                 return;
 176
 177         case TTM_PL_VRAM:
 178                 if (!adev->mman.buffer_funcs_enabled) {
 179                         /* Move to system memory */
 180                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 181                 } else if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
 182                            !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) &&
 183                            amdgpu_bo_in_cpu_visible_vram(abo)) {
 184
 185                         /* Try evicting to the CPU inaccessible part of VRAM
 186                          * first, but only set GTT as busy placement, so this
 187                          * BO will be evicted to GTT rather than causing other
 188                          * BOs to be evicted from VRAM
 189                          */
 190                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
 191                                                          AMDGPU_GEM_DOMAIN_GTT);
 192                         abo->placements[0].fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;
 193                         abo->placements[0].lpfn = 0;
 194                         abo->placement.busy_placement = &abo->placements[1];
 195                         abo->placement.num_busy_placement = 1;
 196                 } else {
 197                         /* Move to GTT memory */
 198                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT);
 199                 }
 200                 break;
 201         case TTM_PL_TT:
 202         default:
 203                 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 204                 break;
 205         }
 206         *placement = abo->placement;
 207 }
 208
 209 /**
 210  * amdgpu_verify_access - Verify access for a mmap call
 211  *
 212  * @bo: The buffer object to map
 213  * @filp: The file pointer from the process performing the mmap
 214  *
 215  * This is called by ttm_bo_mmap() to verify whether a process
 216  * has the right to mmap a BO to their process space.
 217  */
 218 static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp)
 219 {
 220         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
 221
 222         /*
 223          * Don't verify access for KFD BOs. They don't have a GEM
 224          * object associated with them.
 225          */
 226         if (abo->kfd_bo)
 227                 return 0;
 228
 229         if (amdgpu_ttm_tt_get_usermm(bo->ttm))
 230                 return -EPERM;
 231         return drm_vma_node_verify_access(&abo->tbo.base.vma_node,
 232                                           filp->private_data);
 233 }
 234
 235 /**
 236  * amdgpu_move_null - Register memory for a buffer object
 237  *
 238  * @bo: The bo to assign the memory to
 239  * @new_mem: The memory to be assigned.
 240  *
 241  * Assign the memory from new_mem to the memory of the buffer object bo.
 242  */
 243 static void amdgpu_move_null(struct ttm_buffer_object *bo,
 244                              struct ttm_mem_reg *new_mem)
 245 {
 246         struct ttm_mem_reg *old_mem = &bo->mem;
 247
 248         BUG_ON(old_mem->mm_node != NULL);
 249         *old_mem = *new_mem;
 250         new_mem->mm_node = NULL;
 251 }
 252
 253 /**
 254  * amdgpu_mm_node_addr - Compute the GPU relative offset of a GTT buffer.
 255  *
 256  * @bo: The bo to assign the memory to.
 257  * @mm_node: Memory manager node for drm allocator.
 258  * @mem: The region where the bo resides.
 259  *
 260  */
 261 static uint64_t amdgpu_mm_node_addr(struct ttm_buffer_object *bo,
 262                                     struct drm_mm_node *mm_node,
 263                                     struct ttm_mem_reg *mem)
 264 {
 265         uint64_t addr = 0;
 266
 267         if (mm_node->start != AMDGPU_BO_INVALID_OFFSET) {
 268                 addr = mm_node->start << PAGE_SHIFT;
 269                 addr += bo->bdev->man[mem->mem_type].gpu_offset;
 270         }
 271         return addr;
 272 }
 273
 274 /**
 275  * amdgpu_find_mm_node - Helper function finds the drm_mm_node corresponding to
 276  * @offset. It also modifies the offset to be within the drm_mm_node returned
 277  *
 278  * @mem: The region where the bo resides.
 279  * @offset: The offset that drm_mm_node is used for finding.
 280  *
 281  */
 282 static struct drm_mm_node *amdgpu_find_mm_node(struct ttm_mem_reg *mem,
 283                                                unsigned long *offset)
 284 {
 285         struct drm_mm_node *mm_node = mem->mm_node;
 286
 287         while (*offset >= (mm_node->size << PAGE_SHIFT)) {
 288                 *offset -= (mm_node->size << PAGE_SHIFT);
 289                 ++mm_node;
 290         }
 291         return mm_node;
 292 }
 293
 294 /**
 295  * amdgpu_copy_ttm_mem_to_mem - Helper function for copy
 296  *
 297  * The function copies @size bytes from {src->mem + src->offset} to
 298  * {dst->mem + dst->offset}. src->bo and dst->bo could be same BO for a
 299  * move and different for a BO to BO copy.
 300  *
 301  * @f: Returns the last fence if multiple jobs are submitted.
 302  */
 303 int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
 304                                struct amdgpu_copy_mem *src,
 305                                struct amdgpu_copy_mem *dst,
 306                                uint64_t size,
 307                                struct dma_resv *resv,
 308                                struct dma_fence **f)
 309 {
 310         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
 311         struct drm_mm_node *src_mm, *dst_mm;
 312         uint64_t src_node_start, dst_node_start, src_node_size,
 313                  dst_node_size, src_page_offset, dst_page_offset;
 314         struct dma_fence *fence = NULL;
 315         int r = 0;
 316         const uint64_t GTT_MAX_BYTES = (AMDGPU_GTT_MAX_TRANSFER_SIZE *
 317                                         AMDGPU_GPU_PAGE_SIZE);
 318
 319         if (!adev->mman.buffer_funcs_enabled) {
 320                 DRM_ERROR("Trying to move memory with ring turned off.\n");
 321                 return -EINVAL;
 322         }
 323
 324         src_mm = amdgpu_find_mm_node(src->mem, &src->offset);
 325         src_node_start = amdgpu_mm_node_addr(src->bo, src_mm, src->mem) +
 326                                              src->offset;
 327         src_node_size = (src_mm->size << PAGE_SHIFT) - src->offset;
 328         src_page_offset = src_node_start & (PAGE_SIZE - 1);
 329
 330         dst_mm = amdgpu_find_mm_node(dst->mem, &dst->offset);
 331         dst_node_start = amdgpu_mm_node_addr(dst->bo, dst_mm, dst->mem) +
 332                                              dst->offset;
 333         dst_node_size = (dst_mm->size << PAGE_SHIFT) - dst->offset;
 334         dst_page_offset = dst_node_start & (PAGE_SIZE - 1);
 335
 336         mutex_lock(&adev->mman.gtt_window_lock);
 337
 338         while (size) {
 339                 unsigned long cur_size;
 340                 uint64_t from = src_node_start, to = dst_node_start;
 341                 struct dma_fence *next;
 342
 343                 /* Copy size cannot exceed GTT_MAX_BYTES. So if src or dst
 344                  * begins at an offset, then adjust the size accordingly
 345                  */
 346                 cur_size = min3(min(src_node_size, dst_node_size), size,
 347                                 GTT_MAX_BYTES);
 348                 if (cur_size + src_page_offset > GTT_MAX_BYTES ||
 349                     cur_size + dst_page_offset > GTT_MAX_BYTES)
 350                         cur_size -= max(src_page_offset, dst_page_offset);
 351
 352                 /* Map only what needs to be accessed. Map src to window 0 and
 353                  * dst to window 1
 354                  */
 355                 if (src->mem->start == AMDGPU_BO_INVALID_OFFSET) {
 356                         r = amdgpu_map_buffer(src->bo, src->mem,
 357                                         PFN_UP(cur_size + src_page_offset),
 358                                         src_node_start, 0, ring,
 359                                         &from);
 360                         if (r)
 361                                 goto error;
 362                         /* Adjust the offset because amdgpu_map_buffer returns
 363                          * start of mapped page
 364                          */
 365                         from += src_page_offset;
 366                 }
 367
 368                 if (dst->mem->start == AMDGPU_BO_INVALID_OFFSET) {
 369                         r = amdgpu_map_buffer(dst->bo, dst->mem,
 370                                         PFN_UP(cur_size + dst_page_offset),
 371                                         dst_node_start, 1, ring,
 372                                         &to);
 373                         if (r)
 374                                 goto error;
 375                         to += dst_page_offset;
 376                 }
 377
 378                 r = amdgpu_copy_buffer(ring, from, to, cur_size,
 379                                        resv, &next, false, true);
 380                 if (r)
 381                         goto error;
 382
 383                 dma_fence_put(fence);
 384                 fence = next;
 385
 386                 size -= cur_size;
 387                 if (!size)
 388                         break;
 389
 390                 src_node_size -= cur_size;
 391                 if (!src_node_size) {
 392                         src_node_start = amdgpu_mm_node_addr(src->bo, ++src_mm,
 393                                                              src->mem);
 394                         src_node_size = (src_mm->size << PAGE_SHIFT);
 395                         src_page_offset = 0;
 396                 } else {
 397                         src_node_start += cur_size;
 398                         src_page_offset = src_node_start & (PAGE_SIZE - 1);
 399                 }
 400                 dst_node_size -= cur_size;
 401                 if (!dst_node_size) {
 402                         dst_node_start = amdgpu_mm_node_addr(dst->bo, ++dst_mm,
 403                                                              dst->mem);
 404                         dst_node_size = (dst_mm->size << PAGE_SHIFT);
 405                         dst_page_offset = 0;
 406                 } else {
 407                         dst_node_start += cur_size;
 408                         dst_page_offset = dst_node_start & (PAGE_SIZE - 1);
 409                 }
 410         }
 411 error:
 412         mutex_unlock(&adev->mman.gtt_window_lock);
 413         if (f)
 414                 *f = dma_fence_get(fence);
 415         dma_fence_put(fence);
 416         return r;
 417 }
 418
 419 /**
 420  * amdgpu_move_blit - Copy an entire buffer to another buffer
 421  *
 422  * This is a helper called by amdgpu_bo_move() and amdgpu_move_vram_ram() to
 423  * help move buffers to and from VRAM.
 424  */
 425 static int amdgpu_move_blit(struct ttm_buffer_object *bo,
 426                             bool evict, bool no_wait_gpu,
 427                             struct ttm_mem_reg *new_mem,
 428                             struct ttm_mem_reg *old_mem)
 429 {
 430         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 431         struct amdgpu_copy_mem src, dst;
 432         struct dma_fence *fence = NULL;
 433         int r;
 434
 435         src.bo = bo;
 436         dst.bo = bo;
 437         src.mem = old_mem;
 438         dst.mem = new_mem;
 439         src.offset = 0;
 440         dst.offset = 0;
 441
 442         r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst,
 443                                        new_mem->num_pages << PAGE_SHIFT,
 444                                        bo->base.resv, &fence);
 445         if (r)
 446                 goto error;
 447
 448         /* clear the space being freed */
 449         if (old_mem->mem_type == TTM_PL_VRAM &&
 450             (ttm_to_amdgpu_bo(bo)->flags &
 451              AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) {
 452                 struct dma_fence *wipe_fence = NULL;
 453
 454                 r = amdgpu_fill_buffer(ttm_to_amdgpu_bo(bo), AMDGPU_POISON,
 455                                        NULL, &wipe_fence);
 456                 if (r) {
 457                         goto error;
 458                 } else if (wipe_fence) {
 459                         dma_fence_put(fence);
 460                         fence = wipe_fence;
 461                 }
 462         }
 463
 464         /* Always block for VM page tables before committing the new location */
 465         if (bo->type == ttm_bo_type_kernel)
 466                 r = ttm_bo_move_accel_cleanup(bo, fence, true, new_mem);
 467         else
 468                 r = ttm_bo_pipeline_move(bo, fence, evict, new_mem);
 469         dma_fence_put(fence);
 470         return r;
 471
 472 error:
 473         if (fence)
 474                 dma_fence_wait(fence, false);
 475         dma_fence_put(fence);
 476         return r;
 477 }
 478
 479 /**
 480  * amdgpu_move_vram_ram - Copy VRAM buffer to RAM buffer
 481  *
 482  * Called by amdgpu_bo_move().
 483  */
 484 static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo, bool evict,
 485                                 struct ttm_operation_ctx *ctx,
 486                                 struct ttm_mem_reg *new_mem)
 487 {
 488         struct amdgpu_device *adev;
 489         struct ttm_mem_reg *old_mem = &bo->mem;
 490         struct ttm_mem_reg tmp_mem;
 491         struct ttm_place placements;
 492         struct ttm_placement placement;
 493         int r;
 494
 495         adev = amdgpu_ttm_adev(bo->bdev);
 496
 497         /* create space/pages for new_mem in GTT space */
 498         tmp_mem = *new_mem;
 499         tmp_mem.mm_node = NULL;
 500         placement.num_placement = 1;
 501         placement.placement = &placements;
 502         placement.num_busy_placement = 1;
 503         placement.busy_placement = &placements;
 504         placements.fpfn = 0;
 505         placements.lpfn = 0;
 506         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 507         r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx);
 508         if (unlikely(r)) {
 509                 pr_err("Failed to find GTT space for blit from VRAM\n");
 510                 return r;
 511         }
 512
 513         /* set caching flags */
 514         r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
 515         if (unlikely(r)) {
 516                 goto out_cleanup;
 517         }
 518
 519         /* Bind the memory to the GTT space */
 520         r = ttm_tt_bind(bo->ttm, &tmp_mem, ctx);
 521         if (unlikely(r)) {
 522                 goto out_cleanup;
 523         }
 524
 525         /* blit VRAM to GTT */
 526         r = amdgpu_move_blit(bo, evict, ctx->no_wait_gpu, &tmp_mem, old_mem);
 527         if (unlikely(r)) {
 528                 goto out_cleanup;
 529         }
 530
 531         /* move BO (in tmp_mem) to new_mem */
 532         r = ttm_bo_move_ttm(bo, ctx, new_mem);
 533 out_cleanup:
 534         ttm_bo_mem_put(bo, &tmp_mem);
 535         return r;
 536 }
 537
 538 /**
 539  * amdgpu_move_ram_vram - Copy buffer from RAM to VRAM
 540  *
 541  * Called by amdgpu_bo_move().
 542  */
 543 static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo, bool evict,
 544                                 struct ttm_operation_ctx *ctx,
 545                                 struct ttm_mem_reg *new_mem)
 546 {
 547         struct amdgpu_device *adev;
 548         struct ttm_mem_reg *old_mem = &bo->mem;
 549         struct ttm_mem_reg tmp_mem;
 550         struct ttm_placement placement;
 551         struct ttm_place placements;
 552         int r;
 553
 554         adev = amdgpu_ttm_adev(bo->bdev);
 555
 556         /* make space in GTT for old_mem buffer */
 557         tmp_mem = *new_mem;
 558         tmp_mem.mm_node = NULL;
 559         placement.num_placement = 1;
 560         placement.placement = &placements;
 561         placement.num_busy_placement = 1;
 562         placement.busy_placement = &placements;
 563         placements.fpfn = 0;
 564         placements.lpfn = 0;
 565         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 566         r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx);
 567         if (unlikely(r)) {
 568                 pr_err("Failed to find GTT space for blit to VRAM\n");
 569                 return r;
 570         }
 571
 572         /* move/bind old memory to GTT space */
 573         r = ttm_bo_move_ttm(bo, ctx, &tmp_mem);
 574         if (unlikely(r)) {
 575                 goto out_cleanup;
 576         }
 577
 578         /* copy to VRAM */
 579         r = amdgpu_move_blit(bo, evict, ctx->no_wait_gpu, new_mem, old_mem);
 580         if (unlikely(r)) {
 581                 goto out_cleanup;
 582         }
 583 out_cleanup:
 584         ttm_bo_mem_put(bo, &tmp_mem);
 585         return r;
 586 }
 587
 588 /**
 589  * amdgpu_mem_visible - Check that memory can be accessed by ttm_bo_move_memcpy
 590  *
 591  * Called by amdgpu_bo_move()
 592  */
 593 static bool amdgpu_mem_visible(struct amdgpu_device *adev,
 594                                struct ttm_mem_reg *mem)
 595 {
 596         struct drm_mm_node *nodes = mem->mm_node;
 597
 598         if (mem->mem_type == TTM_PL_SYSTEM ||
 599             mem->mem_type == TTM_PL_TT)
 600                 return true;
 601         if (mem->mem_type != TTM_PL_VRAM)
 602                 return false;
 603
 604         /* ttm_mem_reg_ioremap only supports contiguous memory */
 605         if (nodes->size != mem->num_pages)
 606                 return false;
 607
 608         return ((nodes->start + nodes->size) << PAGE_SHIFT)
 609                 <= adev->gmc.visible_vram_size;
 610 }
 611
 612 /**
 613  * amdgpu_bo_move - Move a buffer object to a new memory location
 614  *
 615  * Called by ttm_bo_handle_move_mem()
 616  */
 617 static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict,
 618                           struct ttm_operation_ctx *ctx,
 619                           struct ttm_mem_reg *new_mem)
 620 {
 621         struct amdgpu_device *adev;
 622         struct amdgpu_bo *abo;
 623         struct ttm_mem_reg *old_mem = &bo->mem;
 624         int r;
 625
 626         /* Can't move a pinned BO */
 627         abo = ttm_to_amdgpu_bo(bo);
 628         if (WARN_ON_ONCE(abo->pin_count > 0))
 629                 return -EINVAL;
 630
 631         adev = amdgpu_ttm_adev(bo->bdev);
 632
 633         if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
 634                 amdgpu_move_null(bo, new_mem);
 635                 return 0;
 636         }
 637         if ((old_mem->mem_type == TTM_PL_TT &&
 638              new_mem->mem_type == TTM_PL_SYSTEM) ||
 639             (old_mem->mem_type == TTM_PL_SYSTEM &&
 640              new_mem->mem_type == TTM_PL_TT)) {
 641                 /* bind is enough */
 642                 amdgpu_move_null(bo, new_mem);
 643                 return 0;
 644         }
 645         if (old_mem->mem_type == AMDGPU_PL_GDS ||
 646             old_mem->mem_type == AMDGPU_PL_GWS ||
 647             old_mem->mem_type == AMDGPU_PL_OA ||
 648             new_mem->mem_type == AMDGPU_PL_GDS ||
 649             new_mem->mem_type == AMDGPU_PL_GWS ||
 650             new_mem->mem_type == AMDGPU_PL_OA) {
 651                 /* Nothing to save here */
 652                 amdgpu_move_null(bo, new_mem);
 653                 return 0;
 654         }
 655
 656         if (!adev->mman.buffer_funcs_enabled) {
 657                 r = -ENODEV;
 658                 goto memcpy;
 659         }
 660
 661         if (old_mem->mem_type == TTM_PL_VRAM &&
 662             new_mem->mem_type == TTM_PL_SYSTEM) {
 663                 r = amdgpu_move_vram_ram(bo, evict, ctx, new_mem);
 664         } else if (old_mem->mem_type == TTM_PL_SYSTEM &&
 665                    new_mem->mem_type == TTM_PL_VRAM) {
 666                 r = amdgpu_move_ram_vram(bo, evict, ctx, new_mem);
 667         } else {
 668                 r = amdgpu_move_blit(bo, evict, ctx->no_wait_gpu,
 669                                      new_mem, old_mem);
 670         }
 671
 672         if (r) {
 673 memcpy:
 674                 /* Check that all memory is CPU accessible */
 675                 if (!amdgpu_mem_visible(adev, old_mem) ||
 676                     !amdgpu_mem_visible(adev, new_mem)) {
 677                         pr_err("Move buffer fallback to memcpy unavailable\n");
 678                         return r;
 679                 }
 680
 681                 r = ttm_bo_move_memcpy(bo, ctx, new_mem);
 682                 if (r)
 683                         return r;
 684         }
 685
 686         if (bo->type == ttm_bo_type_device &&
 687             new_mem->mem_type == TTM_PL_VRAM &&
 688             old_mem->mem_type != TTM_PL_VRAM) {
 689                 /* amdgpu_bo_fault_reserve_notify will re-set this if the CPU
 690                  * accesses the BO after it's moved.
 691                  */
 692                 abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 693         }
 694
 695         /* update statistics */
 696         atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &adev->num_bytes_moved);
 697         return 0;
 698 }
 699
 700 /**
 701  * amdgpu_ttm_io_mem_reserve - Reserve a block of memory during a fault
 702  *
 703  * Called by ttm_mem_io_reserve() ultimately via ttm_bo_vm_fault()
 704  */
 705 static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 706 {
 707         struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
 708         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 709         struct drm_mm_node *mm_node = mem->mm_node;
 710
 711         mem->bus.addr = NULL;
 712         mem->bus.offset = 0;
 713         mem->bus.size = mem->num_pages << PAGE_SHIFT;
 714         mem->bus.base = 0;
 715         mem->bus.is_iomem = false;
 716         if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
 717                 return -EINVAL;
 718         switch (mem->mem_type) {
 719         case TTM_PL_SYSTEM:
 720                 /* system memory */
 721                 return 0;
 722         case TTM_PL_TT:
 723                 break;
 724         case TTM_PL_VRAM:
 725                 mem->bus.offset = mem->start << PAGE_SHIFT;
 726                 /* check if it's visible */
 727                 if ((mem->bus.offset + mem->bus.size) > adev->gmc.visible_vram_size)
 728                         return -EINVAL;
 729                 /* Only physically contiguous buffers apply. In a contiguous
 730                  * buffer, size of the first mm_node would match the number of
 731                  * pages in ttm_mem_reg.
 732                  */
 733                 if (adev->mman.aper_base_kaddr &&
 734                     (mm_node->size == mem->num_pages))
 735                         mem->bus.addr = (u8 *)adev->mman.aper_base_kaddr +
 736                                         mem->bus.offset;
 737
 738                 mem->bus.base = adev->gmc.aper_base;
 739                 mem->bus.is_iomem = true;
 740                 break;
 741         default:
 742                 return -EINVAL;
 743         }
 744         return 0;
 745 }
 746
 747 static void amdgpu_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 748 {
 749 }
 750
 751 static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo,
 752                                            unsigned long page_offset)
 753 {
 754         struct drm_mm_node *mm;
 755         unsigned long offset = (page_offset << PAGE_SHIFT);
 756
 757         mm = amdgpu_find_mm_node(&bo->mem, &offset);
 758         return (bo->mem.bus.base >> PAGE_SHIFT) + mm->start +
 759                 (offset >> PAGE_SHIFT);
 760 }
 761
 762 /*
 763  * TTM backend functions.
 764  */
 765 struct amdgpu_ttm_tt {
 766         struct ttm_dma_tt       ttm;
 767         u64                     offset;
 768         uint64_t                userptr;
 769         struct task_struct      *usertask;
 770         uint32_t                userflags;
 771 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
 772         struct hmm_range        *range;
 773 #endif
 774 };
 775
 776 /**
 777  * amdgpu_ttm_tt_get_user_pages - get device accessible pages that back user
 778  * memory and start HMM tracking CPU page table update
 779  *
 780  * Calling function must call amdgpu_ttm_tt_userptr_range_done() once and only
 781  * once afterwards to stop HMM tracking
 782  */
 783 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
 784
 785 #define MAX_RETRY_HMM_RANGE_FAULT       16
 786
 787 int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages)
 788 {
 789         struct hmm_mirror *mirror = bo->mn ? &bo->mn->mirror : NULL;
 790         struct ttm_tt *ttm = bo->tbo.ttm;
 791         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 792         struct mm_struct *mm = gtt->usertask->mm;
 793         unsigned long start = gtt->userptr;
 794         struct vm_area_struct *vma;
 795         struct hmm_range *range;
 796         unsigned long i;
 797         uint64_t *pfns;
 798         int r = 0;
 799
 800         if (!mm) /* Happens during process shutdown */
 801                 return -ESRCH;
 802
 803         if (unlikely(!mirror)) {
 804                 DRM_DEBUG_DRIVER("Failed to get hmm_mirror\n");
 805                 r = -EFAULT;
 806                 goto out;
 807         }
 808
 809         vma = find_vma(mm, start);
 810         if (unlikely(!vma || start < vma->vm_start)) {
 811                 r = -EFAULT;
 812                 goto out;
 813         }
 814         if (unlikely((gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) &&
 815                 vma->vm_file)) {
 816                 r = -EPERM;
 817                 goto out;
 818         }
 819
 820         range = kzalloc(sizeof(*range), GFP_KERNEL);
 821         if (unlikely(!range)) {
 822                 r = -ENOMEM;
 823                 goto out;
 824         }
 825
 826         pfns = kvmalloc_array(ttm->num_pages, sizeof(*pfns), GFP_KERNEL);
 827         if (unlikely(!pfns)) {
 828                 r = -ENOMEM;
 829                 goto out_free_ranges;
 830         }
 831
 832         amdgpu_hmm_init_range(range);
 833         range->default_flags = range->flags[HMM_PFN_VALID];
 834         range->default_flags |= amdgpu_ttm_tt_is_readonly(ttm) ?
 835                                 0 : range->flags[HMM_PFN_WRITE];
 836         range->pfn_flags_mask = 0;
 837         range->pfns = pfns;
 838         range->start = start;
 839         range->end = start + ttm->num_pages * PAGE_SIZE;
 840
 841         hmm_range_register(range, mirror);
 842
 843         /*
 844          * Just wait for range to be valid, safe to ignore return value as we
 845          * will use the return value of hmm_range_fault() below under the
 846          * mmap_sem to ascertain the validity of the range.
 847          */
 848         hmm_range_wait_until_valid(range, HMM_RANGE_DEFAULT_TIMEOUT);
 849
 850         down_read(&mm->mmap_sem);
 851         r = hmm_range_fault(range, 0);
 852         up_read(&mm->mmap_sem);
 853
 854         if (unlikely(r < 0))
 855                 goto out_free_pfns;
 856
 857         for (i = 0; i < ttm->num_pages; i++) {
 858                 pages[i] = hmm_device_entry_to_page(range, pfns[i]);
 859                 if (unlikely(!pages[i])) {
 860                         pr_err("Page fault failed for pfn[%lu] = 0x%llx\n",
 861                                i, pfns[i]);
 862                         r = -ENOMEM;
 863
 864                         goto out_free_pfns;
 865                 }
 866         }
 867
 868         gtt->range = range;
 869
 870         return 0;
 871
 872 out_free_pfns:
 873         hmm_range_unregister(range);
 874         kvfree(pfns);
 875 out_free_ranges:
 876         kfree(range);
 877 out:
 878         return r;
 879 }
 880
 881 /**
 882  * amdgpu_ttm_tt_userptr_range_done - stop HMM track the CPU page table change
 883  * Check if the pages backing this ttm range have been invalidated
 884  *
 885  * Returns: true if pages are still valid
 886  */
 887 bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm)
 888 {
 889         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 890         bool r = false;
 891
 892         if (!gtt || !gtt->userptr)
 893                 return false;
 894
 895         DRM_DEBUG_DRIVER("user_pages_done 0x%llx pages 0x%lx\n",
 896                 gtt->userptr, ttm->num_pages);
 897
 898         WARN_ONCE(!gtt->range || !gtt->range->pfns,
 899                 "No user pages to check\n");
 900
 901         if (gtt->range) {
 902                 r = hmm_range_valid(gtt->range);
 903                 hmm_range_unregister(gtt->range);
 904
 905                 kvfree(gtt->range->pfns);
 906                 kfree(gtt->range);
 907                 gtt->range = NULL;
 908         }
 909
 910         return r;
 911 }
 912 #endif
 913
 914 /**
 915  * amdgpu_ttm_tt_set_user_pages - Copy pages in, putting old pages as necessary.
 916  *
 917  * Called by amdgpu_cs_list_validate(). This creates the page list
 918  * that backs user memory and will ultimately be mapped into the device
 919  * address space.
 920  */
 921 void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages)
 922 {
 923         unsigned long i;
 924
 925         for (i = 0; i < ttm->num_pages; ++i)
 926                 ttm->pages[i] = pages ? pages[i] : NULL;
 927 }
 928
 929 /**
 930  * amdgpu_ttm_tt_pin_userptr -  prepare the sg table with the user pages
 931  *
 932  * Called by amdgpu_ttm_backend_bind()
 933  **/
 934 static int amdgpu_ttm_tt_pin_userptr(struct ttm_tt *ttm)
 935 {
 936         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
 937         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 938         unsigned nents;
 939         int r;
 940
 941         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 942         enum dma_data_direction direction = write ?
 943                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 944
 945         /* Allocate an SG array and squash pages into it */
 946         r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
 947                                       ttm->num_pages << PAGE_SHIFT,
 948                                       GFP_KERNEL);
 949         if (r)
 950                 goto release_sg;
 951
 952         /* Map SG to device */
 953         r = -ENOMEM;
 954         nents = dma_map_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
 955         if (nents != ttm->sg->nents)
 956                 goto release_sg;
 957
 958         /* convert SG to linear array of pages and dma addresses */
 959         drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
 960                                          gtt->ttm.dma_address, ttm->num_pages);
 961
 962         return 0;
 963
 964 release_sg:
 965         kfree(ttm->sg);
 966         return r;
 967 }
 968
 969 /**
 970  * amdgpu_ttm_tt_unpin_userptr - Unpin and unmap userptr pages
 971  */
 972 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_tt *ttm)
 973 {
 974         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
 975         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 976
 977         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 978         enum dma_data_direction direction = write ?
 979                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 980
 981         /* double check that we don't free the table twice */
 982         if (!ttm->sg->sgl)
 983                 return;
 984
 985         /* unmap the pages mapped to the device */
 986         dma_unmap_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
 987
 988         sg_free_table(ttm->sg);
 989
 990 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
 991         if (gtt->range &&
 992             ttm->pages[0] == hmm_device_entry_to_page(gtt->range,
 993                                                       gtt->range->pfns[0]))
 994                 WARN_ONCE(1, "Missing get_user_page_done\n");
 995 #endif
 996 }
 997
 998 int amdgpu_ttm_gart_bind(struct amdgpu_device *adev,
 999                                 struct ttm_buffer_object *tbo,
1000                                 uint64_t flags)
1001 {
1002         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(tbo);
1003         struct ttm_tt *ttm = tbo->ttm;
1004         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1005         int r;
1006
1007         if (abo->flags & AMDGPU_GEM_CREATE_MQD_GFX9) {
1008                 uint64_t page_idx = 1;
1009
1010                 r = amdgpu_gart_bind(adev, gtt->offset, page_idx,
1011                                 ttm->pages, gtt->ttm.dma_address, flags);
1012                 if (r)
1013                         goto gart_bind_fail;
1014
1015                 /* Patch mtype of the second part BO */
1016                 flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK;
1017                 flags |= AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_NC);
1018
1019                 r = amdgpu_gart_bind(adev,
1020                                 gtt->offset + (page_idx << PAGE_SHIFT),
1021                                 ttm->num_pages - page_idx,
1022                                 &ttm->pages[page_idx],
1023                                 &(gtt->ttm.dma_address[page_idx]), flags);
1024         } else {
1025                 r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
1026                                      ttm->pages, gtt->ttm.dma_address, flags);
1027         }
1028
1029 gart_bind_fail:
1030         if (r)
1031                 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
1032                           ttm->num_pages, gtt->offset);
1033
1034         return r;
1035 }
1036
1037 /**
1038  * amdgpu_ttm_backend_bind - Bind GTT memory
1039  *
1040  * Called by ttm_tt_bind() on behalf of ttm_bo_handle_move_mem().
1041  * This handles binding GTT memory to the device address space.
1042  */
1043 static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm,
1044                                    struct ttm_mem_reg *bo_mem)
1045 {
1046         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
1047         struct amdgpu_ttm_tt *gtt = (void*)ttm;
1048         uint64_t flags;
1049         int r = 0;
1050
1051         if (gtt->userptr) {
1052                 r = amdgpu_ttm_tt_pin_userptr(ttm);
1053                 if (r) {
1054                         DRM_ERROR("failed to pin userptr\n");
1055                         return r;
1056                 }
1057         }
1058         if (!ttm->num_pages) {
1059                 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
1060                      ttm->num_pages, bo_mem, ttm);
1061         }
1062
1063         if (bo_mem->mem_type == AMDGPU_PL_GDS ||
1064             bo_mem->mem_type == AMDGPU_PL_GWS ||
1065             bo_mem->mem_type == AMDGPU_PL_OA)
1066                 return -EINVAL;
1067
1068         if (!amdgpu_gtt_mgr_has_gart_addr(bo_mem)) {
1069                 gtt->offset = AMDGPU_BO_INVALID_OFFSET;
1070                 return 0;
1071         }
1072
1073         /* compute PTE flags relevant to this BO memory */
1074         flags = amdgpu_ttm_tt_pte_flags(adev, ttm, bo_mem);
1075
1076         /* bind pages into GART page tables */
1077         gtt->offset = (u64)bo_mem->start << PAGE_SHIFT;
1078         r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
1079                 ttm->pages, gtt->ttm.dma_address, flags);
1080
1081         if (r)
1082                 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
1083                           ttm->num_pages, gtt->offset);
1084         return r;
1085 }
1086
1087 /**
1088  * amdgpu_ttm_alloc_gart - Allocate GART memory for buffer object
1089  */
1090 int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
1091 {
1092         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
1093         struct ttm_operation_ctx ctx = { false, false };
1094         struct amdgpu_ttm_tt *gtt = (void*)bo->ttm;
1095         struct ttm_mem_reg tmp;
1096         struct ttm_placement placement;
1097         struct ttm_place placements;
1098         uint64_t addr, flags;
1099         int r;
1100
1101         if (bo->mem.start != AMDGPU_BO_INVALID_OFFSET)
1102                 return 0;
1103
1104         addr = amdgpu_gmc_agp_addr(bo);
1105         if (addr != AMDGPU_BO_INVALID_OFFSET) {
1106                 bo->mem.start = addr >> PAGE_SHIFT;
1107         } else {
1108
1109                 /* allocate GART space */
1110                 tmp = bo->mem;
1111                 tmp.mm_node = NULL;
1112                 placement.num_placement = 1;
1113                 placement.placement = &placements;
1114                 placement.num_busy_placement = 1;
1115                 placement.busy_placement = &placements;
1116                 placements.fpfn = 0;
1117                 placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT;
1118                 placements.flags = (bo->mem.placement & ~TTM_PL_MASK_MEM) |
1119                         TTM_PL_FLAG_TT;
1120
1121                 r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx);
1122                 if (unlikely(r))
1123                         return r;
1124
1125                 /* compute PTE flags for this buffer object */
1126                 flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, &tmp);
1127
1128                 /* Bind pages */
1129                 gtt->offset = (u64)tmp.start << PAGE_SHIFT;
1130                 r = amdgpu_ttm_gart_bind(adev, bo, flags);
1131                 if (unlikely(r)) {
1132                         ttm_bo_mem_put(bo, &tmp);
1133                         return r;
1134                 }
1135
1136                 ttm_bo_mem_put(bo, &bo->mem);
1137                 bo->mem = tmp;
1138         }
1139
1140         bo->offset = (bo->mem.start << PAGE_SHIFT) +
1141                 bo->bdev->man[bo->mem.mem_type].gpu_offset;
1142
1143         return 0;
1144 }
1145
1146 /**
1147  * amdgpu_ttm_recover_gart - Rebind GTT pages
1148  *
1149  * Called by amdgpu_gtt_mgr_recover() from amdgpu_device_reset() to
1150  * rebind GTT pages during a GPU reset.
1151  */
1152 int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo)
1153 {
1154         struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
1155         uint64_t flags;
1156         int r;
1157
1158         if (!tbo->ttm)
1159                 return 0;
1160
1161         flags = amdgpu_ttm_tt_pte_flags(adev, tbo->ttm, &tbo->mem);
1162         r = amdgpu_ttm_gart_bind(adev, tbo, flags);
1163
1164         return r;
1165 }
1166
1167 /**
1168  * amdgpu_ttm_backend_unbind - Unbind GTT mapped pages
1169  *
1170  * Called by ttm_tt_unbind() on behalf of ttm_bo_move_ttm() and
1171  * ttm_tt_destroy().
1172  */
1173 static int amdgpu_ttm_backend_unbind(struct ttm_tt *ttm)
1174 {
1175         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
1176         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1177         int r;
1178
1179         /* if the pages have userptr pinning then clear that first */
1180         if (gtt->userptr)
1181                 amdgpu_ttm_tt_unpin_userptr(ttm);
1182
1183         if (gtt->offset == AMDGPU_BO_INVALID_OFFSET)
1184                 return 0;
1185
1186         /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
1187         r = amdgpu_gart_unbind(adev, gtt->offset, ttm->num_pages);
1188         if (r)
1189                 DRM_ERROR("failed to unbind %lu pages at 0x%08llX\n",
1190                           gtt->ttm.ttm.num_pages, gtt->offset);
1191         return r;
1192 }
1193
1194 static void amdgpu_ttm_backend_destroy(struct ttm_tt *ttm)
1195 {
1196         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1197
1198         if (gtt->usertask)
1199                 put_task_struct(gtt->usertask);
1200
1201         ttm_dma_tt_fini(&gtt->ttm);
1202         kfree(gtt);
1203 }
1204
1205 static struct ttm_backend_func amdgpu_backend_func = {
1206         .bind = &amdgpu_ttm_backend_bind,
1207         .unbind = &amdgpu_ttm_backend_unbind,
1208         .destroy = &amdgpu_ttm_backend_destroy,
1209 };
1210
1211 /**
1212  * amdgpu_ttm_tt_create - Create a ttm_tt object for a given BO
1213  *
1214  * @bo: The buffer object to create a GTT ttm_tt object around
1215  *
1216  * Called by ttm_tt_create().
1217  */
1218 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_buffer_object *bo,
1219                                            uint32_t page_flags)
1220 {
1221         struct amdgpu_device *adev;
1222         struct amdgpu_ttm_tt *gtt;
1223
1224         adev = amdgpu_ttm_adev(bo->bdev);
1225
1226         gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
1227         if (gtt == NULL) {
1228                 return NULL;
1229         }
1230         gtt->ttm.ttm.func = &amdgpu_backend_func;
1231
1232         /* allocate space for the uninitialized page entries */
1233         if (ttm_sg_tt_init(&gtt->ttm, bo, page_flags)) {
1234                 kfree(gtt);
1235                 return NULL;
1236         }
1237         return &gtt->ttm.ttm;
1238 }
1239
1240 /**
1241  * amdgpu_ttm_tt_populate - Map GTT pages visible to the device
1242  *
1243  * Map the pages of a ttm_tt object to an address space visible
1244  * to the underlying device.
1245  */
1246 static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm,
1247                         struct ttm_operation_ctx *ctx)
1248 {
1249         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
1250         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1251         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1252
1253         /* user pages are bound by amdgpu_ttm_tt_pin_userptr() */
1254         if (gtt && gtt->userptr) {
1255                 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
1256                 if (!ttm->sg)
1257                         return -ENOMEM;
1258
1259                 ttm->page_flags |= TTM_PAGE_FLAG_SG;
1260                 ttm->state = tt_unbound;
1261                 return 0;
1262         }
1263
1264         if (slave && ttm->sg) {
1265                 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
1266                                                  gtt->ttm.dma_address,
1267                                                  ttm->num_pages);
1268                 ttm->state = tt_unbound;
1269                 return 0;
1270         }
1271
1272 #ifdef CONFIG_SWIOTLB
1273         if (adev->need_swiotlb && swiotlb_nr_tbl()) {
1274                 return ttm_dma_populate(&gtt->ttm, adev->dev, ctx);
1275         }
1276 #endif
1277
1278         /* fall back to generic helper to populate the page array
1279          * and map them to the device */
1280         return ttm_populate_and_map_pages(adev->dev, &gtt->ttm, ctx);
1281 }
1282
1283 /**
1284  * amdgpu_ttm_tt_unpopulate - unmap GTT pages and unpopulate page arrays
1285  *
1286  * Unmaps pages of a ttm_tt object from the device address space and
1287  * unpopulates the page array backing it.
1288  */
1289 static void amdgpu_ttm_tt_unpopulate(struct ttm_tt *ttm)
1290 {
1291         struct amdgpu_device *adev;
1292         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1293         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1294
1295         if (gtt && gtt->userptr) {
1296                 amdgpu_ttm_tt_set_user_pages(ttm, NULL);
1297                 kfree(ttm->sg);
1298                 ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
1299                 return;
1300         }
1301
1302         if (slave)
1303                 return;
1304
1305         adev = amdgpu_ttm_adev(ttm->bdev);
1306
1307 #ifdef CONFIG_SWIOTLB
1308         if (adev->need_swiotlb && swiotlb_nr_tbl()) {
1309                 ttm_dma_unpopulate(&gtt->ttm, adev->dev);
1310                 return;
1311         }
1312 #endif
1313
1314         /* fall back to generic helper to unmap and unpopulate array */
1315         ttm_unmap_and_unpopulate_pages(adev->dev, &gtt->ttm);
1316 }
1317
1318 /**
1319  * amdgpu_ttm_tt_set_userptr - Initialize userptr GTT ttm_tt for the current
1320  * task
1321  *
1322  * @ttm: The ttm_tt object to bind this userptr object to
1323  * @addr:  The address in the current tasks VM space to use
1324  * @flags: Requirements of userptr object.
1325  *
1326  * Called by amdgpu_gem_userptr_ioctl() to bind userptr pages
1327  * to current task
1328  */
1329 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
1330                               uint32_t flags)
1331 {
1332         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1333
1334         if (gtt == NULL)
1335                 return -EINVAL;
1336
1337         gtt->userptr = addr;
1338         gtt->userflags = flags;
1339
1340         if (gtt->usertask)
1341                 put_task_struct(gtt->usertask);
1342         gtt->usertask = current->group_leader;
1343         get_task_struct(gtt->usertask);
1344
1345         return 0;
1346 }
1347
1348 /**
1349  * amdgpu_ttm_tt_get_usermm - Return memory manager for ttm_tt object
1350  */
1351 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
1352 {
1353         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1354
1355         if (gtt == NULL)
1356                 return NULL;
1357
1358         if (gtt->usertask == NULL)
1359                 return NULL;
1360
1361         return gtt->usertask->mm;
1362 }
1363
1364 /**
1365  * amdgpu_ttm_tt_affect_userptr - Determine if a ttm_tt object lays inside an
1366  * address range for the current task.
1367  *
1368  */
1369 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
1370                                   unsigned long end)
1371 {
1372         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1373         unsigned long size;
1374
1375         if (gtt == NULL || !gtt->userptr)
1376                 return false;
1377
1378         /* Return false if no part of the ttm_tt object lies within
1379          * the range
1380          */
1381         size = (unsigned long)gtt->ttm.ttm.num_pages * PAGE_SIZE;
1382         if (gtt->userptr > end || gtt->userptr + size <= start)
1383                 return false;
1384
1385         return true;
1386 }
1387
1388 /**
1389  * amdgpu_ttm_tt_is_userptr - Have the pages backing by userptr?
1390  */
1391 bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm)
1392 {
1393         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1394
1395         if (gtt == NULL || !gtt->userptr)
1396                 return false;
1397
1398         return true;
1399 }
1400
1401 /**
1402  * amdgpu_ttm_tt_is_readonly - Is the ttm_tt object read only?
1403  */
1404 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
1405 {
1406         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1407
1408         if (gtt == NULL)
1409                 return false;
1410
1411         return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1412 }
1413
1414 /**
1415  * amdgpu_ttm_tt_pde_flags - Compute PDE flags for ttm_tt object
1416  *
1417  * @ttm: The ttm_tt object to compute the flags for
1418  * @mem: The memory registry backing this ttm_tt object
1419  *
1420  * Figure out the flags to use for a VM PDE (Page Directory Entry).
1421  */
1422 uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_mem_reg *mem)
1423 {
1424         uint64_t flags = 0;
1425
1426         if (mem && mem->mem_type != TTM_PL_SYSTEM)
1427                 flags |= AMDGPU_PTE_VALID;
1428
1429         if (mem && mem->mem_type == TTM_PL_TT) {
1430                 flags |= AMDGPU_PTE_SYSTEM;
1431
1432                 if (ttm->caching_state == tt_cached)
1433                         flags |= AMDGPU_PTE_SNOOPED;
1434         }
1435
1436         return flags;
1437 }
1438
1439 /**
1440  * amdgpu_ttm_tt_pte_flags - Compute PTE flags for ttm_tt object
1441  *
1442  * @ttm: The ttm_tt object to compute the flags for
1443  * @mem: The memory registry backing this ttm_tt object
1444
1445  * Figure out the flags to use for a VM PTE (Page Table Entry).
1446  */
1447 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
1448                                  struct ttm_mem_reg *mem)
1449 {
1450         uint64_t flags = amdgpu_ttm_tt_pde_flags(ttm, mem);
1451
1452         flags |= adev->gart.gart_pte_flags;
1453         flags |= AMDGPU_PTE_READABLE;
1454
1455         if (!amdgpu_ttm_tt_is_readonly(ttm))
1456                 flags |= AMDGPU_PTE_WRITEABLE;
1457
1458         return flags;
1459 }
1460
1461 /**
1462  * amdgpu_ttm_bo_eviction_valuable - Check to see if we can evict a buffer
1463  * object.
1464  *
1465  * Return true if eviction is sensible. Called by ttm_mem_evict_first() on
1466  * behalf of ttm_bo_mem_force_space() which tries to evict buffer objects until
1467  * it can find space for a new object and by ttm_bo_force_list_clean() which is
1468  * used to clean out a memory space.
1469  */
1470 static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
1471                                             const struct ttm_place *place)
1472 {
1473         unsigned long num_pages = bo->mem.num_pages;
1474         struct drm_mm_node *node = bo->mem.mm_node;
1475         struct dma_resv_list *flist;
1476         struct dma_fence *f;
1477         int i;
1478
1479         /* Don't evict VM page tables while they are busy, otherwise we can't
1480          * cleanly handle page faults.
1481          */
1482         if (bo->type == ttm_bo_type_kernel &&
1483             !dma_resv_test_signaled_rcu(bo->base.resv, true))
1484                 return false;
1485
1486         /* If bo is a KFD BO, check if the bo belongs to the current process.
1487          * If true, then return false as any KFD process needs all its BOs to
1488          * be resident to run successfully
1489          */
1490         flist = dma_resv_get_list(bo->base.resv);
1491         if (flist) {
1492                 for (i = 0; i < flist->shared_count; ++i) {
1493                         f = rcu_dereference_protected(flist->shared[i],
1494                                 dma_resv_held(bo->base.resv));
1495                         if (amdkfd_fence_check_mm(f, current->mm))
1496                                 return false;
1497                 }
1498         }
1499
1500         switch (bo->mem.mem_type) {
1501         case TTM_PL_TT:
1502                 return true;
1503
1504         case TTM_PL_VRAM:
1505                 /* Check each drm MM node individually */
1506                 while (num_pages) {
1507                         if (place->fpfn < (node->start + node->size) &&
1508                             !(place->lpfn && place->lpfn <= node->start))
1509                                 return true;
1510
1511                         num_pages -= node->size;
1512                         ++node;
1513                 }
1514                 return false;
1515
1516         default:
1517                 break;
1518         }
1519
1520         return ttm_bo_eviction_valuable(bo, place);
1521 }
1522
1523 /**
1524  * amdgpu_ttm_access_memory - Read or Write memory that backs a buffer object.
1525  *
1526  * @bo:  The buffer object to read/write
1527  * @offset:  Offset into buffer object
1528  * @buf:  Secondary buffer to write/read from
1529  * @len: Length in bytes of access
1530  * @write:  true if writing
1531  *
1532  * This is used to access VRAM that backs a buffer object via MMIO
1533  * access for debugging purposes.
1534  */
1535 static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo,
1536                                     unsigned long offset,
1537                                     void *buf, int len, int write)
1538 {
1539         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1540         struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
1541         struct drm_mm_node *nodes;
1542         uint32_t value = 0;
1543         int ret = 0;
1544         uint64_t pos;
1545         unsigned long flags;
1546
1547         if (bo->mem.mem_type != TTM_PL_VRAM)
1548                 return -EIO;
1549
1550         nodes = amdgpu_find_mm_node(&abo->tbo.mem, &offset);
1551         pos = (nodes->start << PAGE_SHIFT) + offset;
1552
1553         while (len && pos < adev->gmc.mc_vram_size) {
1554                 uint64_t aligned_pos = pos & ~(uint64_t)3;
1555                 uint32_t bytes = 4 - (pos & 3);
1556                 uint32_t shift = (pos & 3) * 8;
1557                 uint32_t mask = 0xffffffff << shift;
1558
1559                 if (len < bytes) {
1560                         mask &= 0xffffffff >> (bytes - len) * 8;
1561                         bytes = len;
1562                 }
1563
1564                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
1565                 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)aligned_pos) | 0x80000000);
1566                 WREG32_NO_KIQ(mmMM_INDEX_HI, aligned_pos >> 31);
1567                 if (!write || mask != 0xffffffff)
1568                         value = RREG32_NO_KIQ(mmMM_DATA);
1569                 if (write) {
1570                         value &= ~mask;
1571                         value |= (*(uint32_t *)buf << shift) & mask;
1572                         WREG32_NO_KIQ(mmMM_DATA, value);
1573                 }
1574                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
1575                 if (!write) {
1576                         value = (value & mask) >> shift;
1577                         memcpy(buf, &value, bytes);
1578                 }
1579
1580                 ret += bytes;
1581                 buf = (uint8_t *)buf + bytes;
1582                 pos += bytes;
1583                 len -= bytes;
1584                 if (pos >= (nodes->start + nodes->size) << PAGE_SHIFT) {
1585                         ++nodes;
1586                         pos = (nodes->start << PAGE_SHIFT);
1587                 }
1588         }
1589
1590         return ret;
1591 }
1592
1593 static struct ttm_bo_driver amdgpu_bo_driver = {
1594         .ttm_tt_create = &amdgpu_ttm_tt_create,
1595         .ttm_tt_populate = &amdgpu_ttm_tt_populate,
1596         .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate,
1597         .invalidate_caches = &amdgpu_invalidate_caches,
1598         .init_mem_type = &amdgpu_init_mem_type,
1599         .eviction_valuable = amdgpu_ttm_bo_eviction_valuable,
1600         .evict_flags = &amdgpu_evict_flags,
1601         .move = &amdgpu_bo_move,
1602         .verify_access = &amdgpu_verify_access,
1603         .move_notify = &amdgpu_bo_move_notify,
1604         .release_notify = &amdgpu_bo_release_notify,
1605         .fault_reserve_notify = &amdgpu_bo_fault_reserve_notify,
1606         .io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
1607         .io_mem_free = &amdgpu_ttm_io_mem_free,
1608         .io_mem_pfn = amdgpu_ttm_io_mem_pfn,
1609         .access_memory = &amdgpu_ttm_access_memory,
1610         .del_from_lru_notify = &amdgpu_vm_del_from_lru_notify
1611 };
1612
1613 /*
1614  * Firmware Reservation functions
1615  */
1616 /**
1617  * amdgpu_ttm_fw_reserve_vram_fini - free fw reserved vram
1618  *
1619  * @adev: amdgpu_device pointer
1620  *
1621  * free fw reserved vram if it has been reserved.
1622  */
1623 static void amdgpu_ttm_fw_reserve_vram_fini(struct amdgpu_device *adev)
1624 {
1625         amdgpu_bo_free_kernel(&adev->fw_vram_usage.reserved_bo,
1626                 NULL, &adev->fw_vram_usage.va);
1627 }
1628
1629 /**
1630  * amdgpu_ttm_fw_reserve_vram_init - create bo vram reservation from fw
1631  *
1632  * @adev: amdgpu_device pointer
1633  *
1634  * create bo vram reservation from fw.
1635  */
1636 static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev)
1637 {
1638         uint64_t vram_size = adev->gmc.visible_vram_size;
1639
1640         adev->fw_vram_usage.va = NULL;
1641         adev->fw_vram_usage.reserved_bo = NULL;
1642
1643         if (adev->fw_vram_usage.size == 0 ||
1644             adev->fw_vram_usage.size > vram_size)
1645                 return 0;
1646
1647         return amdgpu_bo_create_kernel_at(adev,
1648                                           adev->fw_vram_usage.start_offset,
1649                                           adev->fw_vram_usage.size,
1650                                           AMDGPU_GEM_DOMAIN_VRAM,
1651                                           &adev->fw_vram_usage.reserved_bo,
1652                                           &adev->fw_vram_usage.va);
1653 }
1654
1655 /**
1656  * amdgpu_ttm_init - Init the memory management (ttm) as well as various
1657  * gtt/vram related fields.
1658  *
1659  * This initializes all of the memory space pools that the TTM layer
1660  * will need such as the GTT space (system memory mapped to the device),
1661  * VRAM (on-board memory), and on-chip memories (GDS, GWS, OA) which
1662  * can be mapped per VMID.
1663  */
1664 int amdgpu_ttm_init(struct amdgpu_device *adev)
1665 {
1666         uint64_t gtt_size;
1667         int r;
1668         u64 vis_vram_limit;
1669         void *stolen_vga_buf;
1670
1671         mutex_init(&adev->mman.gtt_window_lock);
1672
1673         /* No others user of address space so set it to 0 */
1674         r = ttm_bo_device_init(&adev->mman.bdev,
1675                                &amdgpu_bo_driver,
1676                                adev->ddev->anon_inode->i_mapping,
1677                                adev->ddev->vma_offset_manager,
1678                                dma_addressing_limited(adev->dev));
1679         if (r) {
1680                 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
1681                 return r;
1682         }
1683         adev->mman.initialized = true;
1684
1685         /* We opt to avoid OOM on system pages allocations */
1686         adev->mman.bdev.no_retry = true;
1687
1688         /* Initialize VRAM pool with all of VRAM divided into pages */
1689         r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_VRAM,
1690                                 adev->gmc.real_vram_size >> PAGE_SHIFT);
1691         if (r) {
1692                 DRM_ERROR("Failed initializing VRAM heap.\n");
1693                 return r;
1694         }
1695
1696         /* Reduce size of CPU-visible VRAM if requested */
1697         vis_vram_limit = (u64)amdgpu_vis_vram_limit * 1024 * 1024;
1698         if (amdgpu_vis_vram_limit > 0 &&
1699             vis_vram_limit <= adev->gmc.visible_vram_size)
1700                 adev->gmc.visible_vram_size = vis_vram_limit;
1701
1702         /* Change the size here instead of the init above so only lpfn is affected */
1703         amdgpu_ttm_set_buffer_funcs_status(adev, false);
1704 #ifdef CONFIG_64BIT
1705         adev->mman.aper_base_kaddr = ioremap_wc(adev->gmc.aper_base,
1706                                                 adev->gmc.visible_vram_size);
1707 #endif
1708
1709         /*
1710          * retired pages will be loaded from eeprom and reserved here,
1711          * it should be called after ttm init since new bo may be created,
1712          * recovery_init may fail, but it can free all resources allocated by
1713          * itself and its failure should not stop amdgpu init process.
1714          *
1715          * Note: theoretically, this should be called before all vram allocations
1716          * to protect retired page from abusing
1717          */
1718         amdgpu_ras_recovery_init(adev);
1719
1720         /*
1721          *The reserved vram for firmware must be pinned to the specified
1722          *place on the VRAM, so reserve it early.
1723          */
1724         r = amdgpu_ttm_fw_reserve_vram_init(adev);
1725         if (r) {
1726                 return r;
1727         }
1728
1729         /* allocate memory as required for VGA
1730          * This is used for VGA emulation and pre-OS scanout buffers to
1731          * avoid display artifacts while transitioning between pre-OS
1732          * and driver.  */
1733         r = amdgpu_bo_create_kernel(adev, adev->gmc.stolen_size, PAGE_SIZE,
1734                                     AMDGPU_GEM_DOMAIN_VRAM,
1735                                     &adev->stolen_vga_memory,
1736                                     NULL, &stolen_vga_buf);
1737         if (r)
1738                 return r;
1739         DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
1740                  (unsigned) (adev->gmc.real_vram_size / (1024 * 1024)));
1741
1742         /* Compute GTT size, either bsaed on 3/4th the size of RAM size
1743          * or whatever the user passed on module init */
1744         if (amdgpu_gtt_size == -1) {
1745                 struct sysinfo si;
1746
1747                 si_meminfo(&si);
1748                 gtt_size = min(max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),
1749                                adev->gmc.mc_vram_size),
1750                                ((uint64_t)si.totalram * si.mem_unit * 3/4));
1751         }
1752         else
1753                 gtt_size = (uint64_t)amdgpu_gtt_size << 20;
1754
1755         /* Initialize GTT memory pool */
1756         r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_TT, gtt_size >> PAGE_SHIFT);
1757         if (r) {
1758                 DRM_ERROR("Failed initializing GTT heap.\n");
1759                 return r;
1760         }
1761         DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
1762                  (unsigned)(gtt_size / (1024 * 1024)));
1763
1764         /* Initialize various on-chip memory pools */
1765         r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GDS,
1766                            adev->gds.gds_size);
1767         if (r) {
1768                 DRM_ERROR("Failed initializing GDS heap.\n");
1769                 return r;
1770         }
1771
1772         r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GWS,
1773                            adev->gds.gws_size);
1774         if (r) {
1775                 DRM_ERROR("Failed initializing gws heap.\n");
1776                 return r;
1777         }
1778
1779         r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_OA,
1780                            adev->gds.oa_size);
1781         if (r) {
1782                 DRM_ERROR("Failed initializing oa heap.\n");
1783                 return r;
1784         }
1785
1786         /* Register debugfs entries for amdgpu_ttm */
1787         r = amdgpu_ttm_debugfs_init(adev);
1788         if (r) {
1789                 DRM_ERROR("Failed to init debugfs\n");
1790                 return r;
1791         }
1792         return 0;
1793 }
1794
1795 /**
1796  * amdgpu_ttm_late_init - Handle any late initialization for amdgpu_ttm
1797  */
1798 void amdgpu_ttm_late_init(struct amdgpu_device *adev)
1799 {
1800         void *stolen_vga_buf;
1801         /* return the VGA stolen memory (if any) back to VRAM */
1802         amdgpu_bo_free_kernel(&adev->stolen_vga_memory, NULL, &stolen_vga_buf);
1803 }
1804
1805 /**
1806  * amdgpu_ttm_fini - De-initialize the TTM memory pools
1807  */
1808 void amdgpu_ttm_fini(struct amdgpu_device *adev)
1809 {
1810         if (!adev->mman.initialized)
1811                 return;
1812
1813         amdgpu_ttm_debugfs_fini(adev);
1814         amdgpu_ttm_fw_reserve_vram_fini(adev);
1815         if (adev->mman.aper_base_kaddr)
1816                 iounmap(adev->mman.aper_base_kaddr);
1817         adev->mman.aper_base_kaddr = NULL;
1818
1819         ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_VRAM);
1820         ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_TT);
1821         ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GDS);
1822         ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GWS);
1823         ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_OA);
1824         ttm_bo_device_release(&adev->mman.bdev);
1825         adev->mman.initialized = false;
1826         DRM_INFO("amdgpu: ttm finalized\n");
1827 }
1828
1829 /**
1830  * amdgpu_ttm_set_buffer_funcs_status - enable/disable use of buffer functions
1831  *
1832  * @adev: amdgpu_device pointer
1833  * @enable: true when we can use buffer functions.
1834  *
1835  * Enable/disable use of buffer functions during suspend/resume. This should
1836  * only be called at bootup or when userspace isn't running.
1837  */
1838 void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
1839 {
1840         struct ttm_mem_type_manager *man = &adev->mman.bdev.man[TTM_PL_VRAM];
1841         uint64_t size;
1842         int r;
1843
1844         if (!adev->mman.initialized || adev->in_gpu_reset ||
1845             adev->mman.buffer_funcs_enabled == enable)
1846                 return;
1847
1848         if (enable) {
1849                 struct amdgpu_ring *ring;
1850                 struct drm_sched_rq *rq;
1851
1852                 ring = adev->mman.buffer_funcs_ring;
1853                 rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_KERNEL];
1854                 r = drm_sched_entity_init(&adev->mman.entity, &rq, 1, NULL);
1855                 if (r) {
1856                         DRM_ERROR("Failed setting up TTM BO move entity (%d)\n",
1857                                   r);
1858                         return;
1859                 }
1860         } else {
1861                 drm_sched_entity_destroy(&adev->mman.entity);
1862                 dma_fence_put(man->move);
1863                 man->move = NULL;
1864         }
1865
1866         /* this just adjusts TTM size idea, which sets lpfn to the correct value */
1867         if (enable)
1868                 size = adev->gmc.real_vram_size;
1869         else
1870                 size = adev->gmc.visible_vram_size;
1871         man->size = size >> PAGE_SHIFT;
1872         adev->mman.buffer_funcs_enabled = enable;
1873 }
1874
1875 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma)
1876 {
1877         struct drm_file *file_priv = filp->private_data;
1878         struct amdgpu_device *adev = file_priv->minor->dev->dev_private;
1879
1880         if (adev == NULL)
1881                 return -EINVAL;
1882
1883         return ttm_bo_mmap(filp, vma, &adev->mman.bdev);
1884 }
1885
1886 static int amdgpu_map_buffer(struct ttm_buffer_object *bo,
1887                              struct ttm_mem_reg *mem, unsigned num_pages,
1888                              uint64_t offset, unsigned window,
1889                              struct amdgpu_ring *ring,
1890                              uint64_t *addr)
1891 {
1892         struct amdgpu_ttm_tt *gtt = (void *)bo->ttm;
1893         struct amdgpu_device *adev = ring->adev;
1894         struct ttm_tt *ttm = bo->ttm;
1895         struct amdgpu_job *job;
1896         unsigned num_dw, num_bytes;
1897         dma_addr_t *dma_address;
1898         struct dma_fence *fence;
1899         uint64_t src_addr, dst_addr;
1900         uint64_t flags;
1901         int r;
1902
1903         BUG_ON(adev->mman.buffer_funcs->copy_max_bytes <
1904                AMDGPU_GTT_MAX_TRANSFER_SIZE * 8);
1905
1906         *addr = adev->gmc.gart_start;
1907         *addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE *
1908                 AMDGPU_GPU_PAGE_SIZE;
1909
1910         num_dw = adev->mman.buffer_funcs->copy_num_dw;
1911         while (num_dw & 0x7)
1912                 num_dw++;
1913
1914         num_bytes = num_pages * 8;
1915
1916         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4 + num_bytes, &job);
1917         if (r)
1918                 return r;
1919
1920         src_addr = num_dw * 4;
1921         src_addr += job->ibs[0].gpu_addr;
1922
1923         dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
1924         dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8;
1925         amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr,
1926                                 dst_addr, num_bytes);
1927
1928         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
1929         WARN_ON(job->ibs[0].length_dw > num_dw);
1930
1931         dma_address = &gtt->ttm.dma_address[offset >> PAGE_SHIFT];
1932         flags = amdgpu_ttm_tt_pte_flags(adev, ttm, mem);
1933         r = amdgpu_gart_map(adev, 0, num_pages, dma_address, flags,
1934                             &job->ibs[0].ptr[num_dw]);
1935         if (r)
1936                 goto error_free;
1937
1938         r = amdgpu_job_submit(job, &adev->mman.entity,
1939                               AMDGPU_FENCE_OWNER_UNDEFINED, &fence);
1940         if (r)
1941                 goto error_free;
1942
1943         dma_fence_put(fence);
1944
1945         return r;
1946
1947 error_free:
1948         amdgpu_job_free(job);
1949         return r;
1950 }
1951
1952 int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
1953                        uint64_t dst_offset, uint32_t byte_count,
1954                        struct dma_resv *resv,
1955                        struct dma_fence **fence, bool direct_submit,
1956                        bool vm_needs_flush)
1957 {
1958         struct amdgpu_device *adev = ring->adev;
1959         struct amdgpu_job *job;
1960
1961         uint32_t max_bytes;
1962         unsigned num_loops, num_dw;
1963         unsigned i;
1964         int r;
1965
1966         if (direct_submit && !ring->sched.ready) {
1967                 DRM_ERROR("Trying to move memory with ring turned off.\n");
1968                 return -EINVAL;
1969         }
1970
1971         max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
1972         num_loops = DIV_ROUND_UP(byte_count, max_bytes);
1973         num_dw = num_loops * adev->mman.buffer_funcs->copy_num_dw;
1974
1975         /* for IB padding */
1976         while (num_dw & 0x7)
1977                 num_dw++;
1978
1979         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job);
1980         if (r)
1981                 return r;
1982
1983         if (vm_needs_flush) {
1984                 job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo);
1985                 job->vm_needs_flush = true;
1986         }
1987         if (resv) {
1988                 r = amdgpu_sync_resv(adev, &job->sync, resv,
1989                                      AMDGPU_FENCE_OWNER_UNDEFINED,
1990                                      false);
1991                 if (r) {
1992                         DRM_ERROR("sync failed (%d).\n", r);
1993                         goto error_free;
1994                 }
1995         }
1996
1997         for (i = 0; i < num_loops; i++) {
1998                 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
1999
2000                 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset,
2001                                         dst_offset, cur_size_in_bytes);
2002
2003                 src_offset += cur_size_in_bytes;
2004                 dst_offset += cur_size_in_bytes;
2005                 byte_count -= cur_size_in_bytes;
2006         }
2007
2008         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2009         WARN_ON(job->ibs[0].length_dw > num_dw);
2010         if (direct_submit)
2011                 r = amdgpu_job_submit_direct(job, ring, fence);
2012         else
2013                 r = amdgpu_job_submit(job, &adev->mman.entity,
2014                                       AMDGPU_FENCE_OWNER_UNDEFINED, fence);
2015         if (r)
2016                 goto error_free;
2017
2018         return r;
2019
2020 error_free:
2021         amdgpu_job_free(job);
2022         DRM_ERROR("Error scheduling IBs (%d)\n", r);
2023         return r;
2024 }
2025
2026 int amdgpu_fill_buffer(struct amdgpu_bo *bo,
2027                        uint32_t src_data,
2028                        struct dma_resv *resv,
2029                        struct dma_fence **fence)
2030 {
2031         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
2032         uint32_t max_bytes = adev->mman.buffer_funcs->fill_max_bytes;
2033         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
2034
2035         struct drm_mm_node *mm_node;
2036         unsigned long num_pages;
2037         unsigned int num_loops, num_dw;
2038
2039         struct amdgpu_job *job;
2040         int r;
2041
2042         if (!adev->mman.buffer_funcs_enabled) {
2043                 DRM_ERROR("Trying to clear memory with ring turned off.\n");
2044                 return -EINVAL;
2045         }
2046
2047         if (bo->tbo.mem.mem_type == TTM_PL_TT) {
2048                 r = amdgpu_ttm_alloc_gart(&bo->tbo);
2049                 if (r)
2050                         return r;
2051         }
2052
2053         num_pages = bo->tbo.num_pages;
2054         mm_node = bo->tbo.mem.mm_node;
2055         num_loops = 0;
2056         while (num_pages) {
2057                 uint64_t byte_count = mm_node->size << PAGE_SHIFT;
2058
2059                 num_loops += DIV_ROUND_UP_ULL(byte_count, max_bytes);
2060                 num_pages -= mm_node->size;
2061                 ++mm_node;
2062         }
2063         num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw;
2064
2065         /* for IB padding */
2066         num_dw += 64;
2067
2068         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job);
2069         if (r)
2070                 return r;
2071
2072         if (resv) {
2073                 r = amdgpu_sync_resv(adev, &job->sync, resv,
2074                                      AMDGPU_FENCE_OWNER_UNDEFINED, false);
2075                 if (r) {
2076                         DRM_ERROR("sync failed (%d).\n", r);
2077                         goto error_free;
2078                 }
2079         }
2080
2081         num_pages = bo->tbo.num_pages;
2082         mm_node = bo->tbo.mem.mm_node;
2083
2084         while (num_pages) {
2085                 uint64_t byte_count = mm_node->size << PAGE_SHIFT;
2086                 uint64_t dst_addr;
2087
2088                 dst_addr = amdgpu_mm_node_addr(&bo->tbo, mm_node, &bo->tbo.mem);
2089                 while (byte_count) {
2090                         uint32_t cur_size_in_bytes = min_t(uint64_t, byte_count,
2091                                                            max_bytes);
2092
2093                         amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data,
2094                                                 dst_addr, cur_size_in_bytes);
2095
2096                         dst_addr += cur_size_in_bytes;
2097                         byte_count -= cur_size_in_bytes;
2098                 }
2099
2100                 num_pages -= mm_node->size;
2101                 ++mm_node;
2102         }
2103
2104         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2105         WARN_ON(job->ibs[0].length_dw > num_dw);
2106         r = amdgpu_job_submit(job, &adev->mman.entity,
2107                               AMDGPU_FENCE_OWNER_UNDEFINED, fence);
2108         if (r)
2109                 goto error_free;
2110
2111         return 0;
2112
2113 error_free:
2114         amdgpu_job_free(job);
2115         return r;
2116 }
2117
2118 #if defined(CONFIG_DEBUG_FS)
2119
2120 static int amdgpu_mm_dump_table(struct seq_file *m, void *data)
2121 {
2122         struct drm_info_node *node = (struct drm_info_node *)m->private;
2123         unsigned ttm_pl = (uintptr_t)node->info_ent->data;
2124         struct drm_device *dev = node->minor->dev;
2125         struct amdgpu_device *adev = dev->dev_private;
2126         struct ttm_mem_type_manager *man = &adev->mman.bdev.man[ttm_pl];
2127         struct drm_printer p = drm_seq_file_printer(m);
2128
2129         man->func->debug(man, &p);
2130         return 0;
2131 }
2132
2133 static const struct drm_info_list amdgpu_ttm_debugfs_list[] = {
2134         {"amdgpu_vram_mm", amdgpu_mm_dump_table, 0, (void *)TTM_PL_VRAM},
2135         {"amdgpu_gtt_mm", amdgpu_mm_dump_table, 0, (void *)TTM_PL_TT},
2136         {"amdgpu_gds_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_GDS},
2137         {"amdgpu_gws_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_GWS},
2138         {"amdgpu_oa_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_OA},
2139         {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL},
2140 #ifdef CONFIG_SWIOTLB
2141         {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL}
2142 #endif
2143 };
2144
2145 /**
2146  * amdgpu_ttm_vram_read - Linear read access to VRAM
2147  *
2148  * Accesses VRAM via MMIO for debugging purposes.
2149  */
2150 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
2151                                     size_t size, loff_t *pos)
2152 {
2153         struct amdgpu_device *adev = file_inode(f)->i_private;
2154         ssize_t result = 0;
2155         int r;
2156
2157         if (size & 0x3 || *pos & 0x3)
2158                 return -EINVAL;
2159
2160         if (*pos >= adev->gmc.mc_vram_size)
2161                 return -ENXIO;
2162
2163         while (size) {
2164                 unsigned long flags;
2165                 uint32_t value;
2166
2167                 if (*pos >= adev->gmc.mc_vram_size)
2168                         return result;
2169
2170                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
2171                 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
2172                 WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31);
2173                 value = RREG32_NO_KIQ(mmMM_DATA);
2174                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
2175
2176                 r = put_user(value, (uint32_t *)buf);
2177                 if (r)
2178                         return r;
2179
2180                 result += 4;
2181                 buf += 4;
2182                 *pos += 4;
2183                 size -= 4;
2184         }
2185
2186         return result;
2187 }
2188
2189 /**
2190  * amdgpu_ttm_vram_write - Linear write access to VRAM
2191  *
2192  * Accesses VRAM via MMIO for debugging purposes.
2193  */
2194 static ssize_t amdgpu_ttm_vram_write(struct file *f, const char __user *buf,
2195                                     size_t size, loff_t *pos)
2196 {
2197         struct amdgpu_device *adev = file_inode(f)->i_private;
2198         ssize_t result = 0;
2199         int r;
2200
2201         if (size & 0x3 || *pos & 0x3)
2202                 return -EINVAL;
2203
2204         if (*pos >= adev->gmc.mc_vram_size)
2205                 return -ENXIO;
2206
2207         while (size) {
2208                 unsigned long flags;
2209                 uint32_t value;
2210
2211                 if (*pos >= adev->gmc.mc_vram_size)
2212                         return result;
2213
2214                 r = get_user(value, (uint32_t *)buf);
2215                 if (r)
2216                         return r;
2217
2218                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
2219                 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
2220                 WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31);
2221                 WREG32_NO_KIQ(mmMM_DATA, value);
2222                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
2223
2224                 result += 4;
2225                 buf += 4;
2226                 *pos += 4;
2227                 size -= 4;
2228         }
2229
2230         return result;
2231 }
2232
2233 static const struct file_operations amdgpu_ttm_vram_fops = {
2234         .owner = THIS_MODULE,
2235         .read = amdgpu_ttm_vram_read,
2236         .write = amdgpu_ttm_vram_write,
2237         .llseek = default_llseek,
2238 };
2239
2240 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
2241
2242 /**
2243  * amdgpu_ttm_gtt_read - Linear read access to GTT memory
2244  */
2245 static ssize_t amdgpu_ttm_gtt_read(struct file *f, char __user *buf,
2246                                    size_t size, loff_t *pos)
2247 {
2248         struct amdgpu_device *adev = file_inode(f)->i_private;
2249         ssize_t result = 0;
2250         int r;
2251
2252         while (size) {
2253                 loff_t p = *pos / PAGE_SIZE;
2254                 unsigned off = *pos & ~PAGE_MASK;
2255                 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off);
2256                 struct page *page;
2257                 void *ptr;
2258
2259                 if (p >= adev->gart.num_cpu_pages)
2260                         return result;
2261
2262                 page = adev->gart.pages[p];
2263                 if (page) {
2264                         ptr = kmap(page);
2265                         ptr += off;
2266
2267                         r = copy_to_user(buf, ptr, cur_size);
2268                         kunmap(adev->gart.pages[p]);
2269                 } else
2270                         r = clear_user(buf, cur_size);
2271
2272                 if (r)
2273                         return -EFAULT;
2274
2275                 result += cur_size;
2276                 buf += cur_size;
2277                 *pos += cur_size;
2278                 size -= cur_size;
2279         }
2280
2281         return result;
2282 }
2283
2284 static const struct file_operations amdgpu_ttm_gtt_fops = {
2285         .owner = THIS_MODULE,
2286         .read = amdgpu_ttm_gtt_read,
2287         .llseek = default_llseek
2288 };
2289
2290 #endif
2291
2292 /**
2293  * amdgpu_iomem_read - Virtual read access to GPU mapped memory
2294  *
2295  * This function is used to read memory that has been mapped to the
2296  * GPU and the known addresses are not physical addresses but instead
2297  * bus addresses (e.g., what you'd put in an IB or ring buffer).
2298  */
2299 static ssize_t amdgpu_iomem_read(struct file *f, char __user *buf,
2300                                  size_t size, loff_t *pos)
2301 {
2302         struct amdgpu_device *adev = file_inode(f)->i_private;
2303         struct iommu_domain *dom;
2304         ssize_t result = 0;
2305         int r;
2306
2307         /* retrieve the IOMMU domain if any for this device */
2308         dom = iommu_get_domain_for_dev(adev->dev);
2309
2310         while (size) {
2311                 phys_addr_t addr = *pos & PAGE_MASK;
2312                 loff_t off = *pos & ~PAGE_MASK;
2313                 size_t bytes = PAGE_SIZE - off;
2314                 unsigned long pfn;
2315                 struct page *p;
2316                 void *ptr;
2317
2318                 bytes = bytes < size ? bytes : size;
2319
2320                 /* Translate the bus address to a physical address.  If
2321                  * the domain is NULL it means there is no IOMMU active
2322                  * and the address translation is the identity
2323                  */
2324                 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2325
2326                 pfn = addr >> PAGE_SHIFT;
2327                 if (!pfn_valid(pfn))
2328                         return -EPERM;
2329
2330                 p = pfn_to_page(pfn);
2331                 if (p->mapping != adev->mman.bdev.dev_mapping)
2332                         return -EPERM;
2333
2334                 ptr = kmap(p);
2335                 r = copy_to_user(buf, ptr + off, bytes);
2336                 kunmap(p);
2337                 if (r)
2338                         return -EFAULT;
2339
2340                 size -= bytes;
2341                 *pos += bytes;
2342                 result += bytes;
2343         }
2344
2345         return result;
2346 }
2347
2348 /**
2349  * amdgpu_iomem_write - Virtual write access to GPU mapped memory
2350  *
2351  * This function is used to write memory that has been mapped to the
2352  * GPU and the known addresses are not physical addresses but instead
2353  * bus addresses (e.g., what you'd put in an IB or ring buffer).
2354  */
2355 static ssize_t amdgpu_iomem_write(struct file *f, const char __user *buf,
2356                                  size_t size, loff_t *pos)
2357 {
2358         struct amdgpu_device *adev = file_inode(f)->i_private;
2359         struct iommu_domain *dom;
2360         ssize_t result = 0;
2361         int r;
2362
2363         dom = iommu_get_domain_for_dev(adev->dev);
2364
2365         while (size) {
2366                 phys_addr_t addr = *pos & PAGE_MASK;
2367                 loff_t off = *pos & ~PAGE_MASK;
2368                 size_t bytes = PAGE_SIZE - off;
2369                 unsigned long pfn;
2370                 struct page *p;
2371                 void *ptr;
2372
2373                 bytes = bytes < size ? bytes : size;
2374
2375                 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2376
2377                 pfn = addr >> PAGE_SHIFT;
2378                 if (!pfn_valid(pfn))
2379                         return -EPERM;
2380
2381                 p = pfn_to_page(pfn);
2382                 if (p->mapping != adev->mman.bdev.dev_mapping)
2383                         return -EPERM;
2384
2385                 ptr = kmap(p);
2386                 r = copy_from_user(ptr + off, buf, bytes);
2387                 kunmap(p);
2388                 if (r)
2389                         return -EFAULT;
2390
2391                 size -= bytes;
2392                 *pos += bytes;
2393                 result += bytes;
2394         }
2395
2396         return result;
2397 }
2398
2399 static const struct file_operations amdgpu_ttm_iomem_fops = {
2400         .owner = THIS_MODULE,
2401         .read = amdgpu_iomem_read,
2402         .write = amdgpu_iomem_write,
2403         .llseek = default_llseek
2404 };
2405
2406 static const struct {
2407         char *name;
2408         const struct file_operations *fops;
2409         int domain;
2410 } ttm_debugfs_entries[] = {
2411         { "amdgpu_vram", &amdgpu_ttm_vram_fops, TTM_PL_VRAM },
2412 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
2413         { "amdgpu_gtt", &amdgpu_ttm_gtt_fops, TTM_PL_TT },
2414 #endif
2415         { "amdgpu_iomem", &amdgpu_ttm_iomem_fops, TTM_PL_SYSTEM },
2416 };
2417
2418 #endif
2419
2420 static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
2421 {
2422 #if defined(CONFIG_DEBUG_FS)
2423         unsigned count;
2424
2425         struct drm_minor *minor = adev->ddev->primary;
2426         struct dentry *ent, *root = minor->debugfs_root;
2427
2428         for (count = 0; count < ARRAY_SIZE(ttm_debugfs_entries); count++) {
2429                 ent = debugfs_create_file(
2430                                 ttm_debugfs_entries[count].name,
2431                                 S_IFREG | S_IRUGO, root,
2432                                 adev,
2433                                 ttm_debugfs_entries[count].fops);
2434                 if (IS_ERR(ent))
2435                         return PTR_ERR(ent);
2436                 if (ttm_debugfs_entries[count].domain == TTM_PL_VRAM)
2437                         i_size_write(ent->d_inode, adev->gmc.mc_vram_size);
2438                 else if (ttm_debugfs_entries[count].domain == TTM_PL_TT)
2439                         i_size_write(ent->d_inode, adev->gmc.gart_size);
2440                 adev->mman.debugfs_entries[count] = ent;
2441         }
2442
2443         count = ARRAY_SIZE(amdgpu_ttm_debugfs_list);
2444
2445 #ifdef CONFIG_SWIOTLB
2446         if (!(adev->need_swiotlb && swiotlb_nr_tbl()))
2447                 --count;
2448 #endif
2449
2450         return amdgpu_debugfs_add_files(adev, amdgpu_ttm_debugfs_list, count);
2451 #else
2452         return 0;
2453 #endif
2454 }
2455
2456 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev)
2457 {
2458 #if defined(CONFIG_DEBUG_FS)
2459         unsigned i;
2460
2461         for (i = 0; i < ARRAY_SIZE(ttm_debugfs_entries); i++)
2462                 debugfs_remove(adev->mman.debugfs_entries[i]);
2463 #endif
2464 }