drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <glisse@freedesktop.org>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32 #include <ttm/ttm_bo_api.h>
  33 #include <ttm/ttm_bo_driver.h>
  34 #include <ttm/ttm_placement.h>
  35 #include <ttm/ttm_module.h>
  36 #include <ttm/ttm_page_alloc.h>
  37 #include <drm/drmP.h>
  38 #include <drm/amdgpu_drm.h>
  39 #include <linux/seq_file.h>
  40 #include <linux/slab.h>
  41 #include <linux/swiotlb.h>
  42 #include <linux/swap.h>
  43 #include <linux/pagemap.h>
  44 #include <linux/debugfs.h>
  45 #include "amdgpu.h"
  46 #include "bif/bif_4_1_d.h"
  47
  48 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
  49
  50 static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev);
  51 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev);
  52
  53
  54 /*
  55  * Global memory.
  56  */
  57 static int amdgpu_ttm_mem_global_init(struct drm_global_reference *ref)
  58 {
  59         return ttm_mem_global_init(ref->object);
  60 }
  61
  62 static void amdgpu_ttm_mem_global_release(struct drm_global_reference *ref)
  63 {
  64         ttm_mem_global_release(ref->object);
  65 }
  66
  67 static int amdgpu_ttm_global_init(struct amdgpu_device *adev)
  68 {
  69         struct drm_global_reference *global_ref;
  70         struct amdgpu_ring *ring;
  71         struct amd_sched_rq *rq;
  72         int r;
  73
  74         adev->mman.mem_global_referenced = false;
  75         global_ref = &adev->mman.mem_global_ref;
  76         global_ref->global_type = DRM_GLOBAL_TTM_MEM;
  77         global_ref->size = sizeof(struct ttm_mem_global);
  78         global_ref->init = &amdgpu_ttm_mem_global_init;
  79         global_ref->release = &amdgpu_ttm_mem_global_release;
  80         r = drm_global_item_ref(global_ref);
  81         if (r) {
  82                 DRM_ERROR("Failed setting up TTM memory accounting "
  83                           "subsystem.\n");
  84                 goto error_mem;
  85         }
  86
  87         adev->mman.bo_global_ref.mem_glob =
  88                 adev->mman.mem_global_ref.object;
  89         global_ref = &adev->mman.bo_global_ref.ref;
  90         global_ref->global_type = DRM_GLOBAL_TTM_BO;
  91         global_ref->size = sizeof(struct ttm_bo_global);
  92         global_ref->init = &ttm_bo_global_init;
  93         global_ref->release = &ttm_bo_global_release;
  94         r = drm_global_item_ref(global_ref);
  95         if (r) {
  96                 DRM_ERROR("Failed setting up TTM BO subsystem.\n");
  97                 goto error_bo;
  98         }
  99
 100         ring = adev->mman.buffer_funcs_ring;
 101         rq = &ring->sched.sched_rq[AMD_SCHED_PRIORITY_KERNEL];
 102         r = amd_sched_entity_init(&ring->sched, &adev->mman.entity,
 103                                   rq, amdgpu_sched_jobs);
 104         if (r) {
 105                 DRM_ERROR("Failed setting up TTM BO move run queue.\n");
 106                 goto error_entity;
 107         }
 108
 109         adev->mman.mem_global_referenced = true;
 110
 111         return 0;
 112
 113 error_entity:
 114         drm_global_item_unref(&adev->mman.bo_global_ref.ref);
 115 error_bo:
 116         drm_global_item_unref(&adev->mman.mem_global_ref);
 117 error_mem:
 118         return r;
 119 }
 120
 121 static void amdgpu_ttm_global_fini(struct amdgpu_device *adev)
 122 {
 123         if (adev->mman.mem_global_referenced) {
 124                 amd_sched_entity_fini(adev->mman.entity.sched,
 125                                       &adev->mman.entity);
 126                 drm_global_item_unref(&adev->mman.bo_global_ref.ref);
 127                 drm_global_item_unref(&adev->mman.mem_global_ref);
 128                 adev->mman.mem_global_referenced = false;
 129         }
 130 }
 131
 132 static int amdgpu_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
 133 {
 134         return 0;
 135 }
 136
 137 static int amdgpu_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
 138                                 struct ttm_mem_type_manager *man)
 139 {
 140         struct amdgpu_device *adev;
 141
 142         adev = amdgpu_ttm_adev(bdev);
 143
 144         switch (type) {
 145         case TTM_PL_SYSTEM:
 146                 /* System memory */
 147                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
 148                 man->available_caching = TTM_PL_MASK_CACHING;
 149                 man->default_caching = TTM_PL_FLAG_CACHED;
 150                 break;
 151         case TTM_PL_TT:
 152                 man->func = &amdgpu_gtt_mgr_func;
 153                 man->gpu_offset = adev->mc.gtt_start;
 154                 man->available_caching = TTM_PL_MASK_CACHING;
 155                 man->default_caching = TTM_PL_FLAG_CACHED;
 156                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
 157                 break;
 158         case TTM_PL_VRAM:
 159                 /* "On-card" video ram */
 160                 man->func = &amdgpu_vram_mgr_func;
 161                 man->gpu_offset = adev->mc.vram_start;
 162                 man->flags = TTM_MEMTYPE_FLAG_FIXED |
 163                              TTM_MEMTYPE_FLAG_MAPPABLE;
 164                 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
 165                 man->default_caching = TTM_PL_FLAG_WC;
 166                 break;
 167         case AMDGPU_PL_GDS:
 168         case AMDGPU_PL_GWS:
 169         case AMDGPU_PL_OA:
 170                 /* On-chip GDS memory*/
 171                 man->func = &ttm_bo_manager_func;
 172                 man->gpu_offset = 0;
 173                 man->flags = TTM_MEMTYPE_FLAG_FIXED | TTM_MEMTYPE_FLAG_CMA;
 174                 man->available_caching = TTM_PL_FLAG_UNCACHED;
 175                 man->default_caching = TTM_PL_FLAG_UNCACHED;
 176                 break;
 177         default:
 178                 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
 179                 return -EINVAL;
 180         }
 181         return 0;
 182 }
 183
 184 static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
 185                                 struct ttm_placement *placement)
 186 {
 187         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 188         struct amdgpu_bo *abo;
 189         static struct ttm_place placements = {
 190                 .fpfn = 0,
 191                 .lpfn = 0,
 192                 .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM
 193         };
 194         unsigned i;
 195
 196         if (!amdgpu_ttm_bo_is_amdgpu_bo(bo)) {
 197                 placement->placement = &placements;
 198                 placement->busy_placement = &placements;
 199                 placement->num_placement = 1;
 200                 placement->num_busy_placement = 1;
 201                 return;
 202         }
 203         abo = container_of(bo, struct amdgpu_bo, tbo);
 204         switch (bo->mem.mem_type) {
 205         case TTM_PL_VRAM:
 206                 if (adev->mman.buffer_funcs_ring->ready == false) {
 207                         amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 208                 } else {
 209                         amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT);
 210                         for (i = 0; i < abo->placement.num_placement; ++i) {
 211                                 if (!(abo->placements[i].flags &
 212                                       TTM_PL_FLAG_TT))
 213                                         continue;
 214
 215                                 if (abo->placements[i].lpfn)
 216                                         continue;
 217
 218                                 /* set an upper limit to force directly
 219                                  * allocating address space for the BO.
 220                                  */
 221                                 abo->placements[i].lpfn =
 222                                         adev->mc.gtt_size >> PAGE_SHIFT;
 223                         }
 224                 }
 225                 break;
 226         case TTM_PL_TT:
 227         default:
 228                 amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 229         }
 230         *placement = abo->placement;
 231 }
 232
 233 static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp)
 234 {
 235         struct amdgpu_bo *abo = container_of(bo, struct amdgpu_bo, tbo);
 236
 237         if (amdgpu_ttm_tt_get_usermm(bo->ttm))
 238                 return -EPERM;
 239         return drm_vma_node_verify_access(&abo->gem_base.vma_node,
 240                                           filp->private_data);
 241 }
 242
 243 static void amdgpu_move_null(struct ttm_buffer_object *bo,
 244                              struct ttm_mem_reg *new_mem)
 245 {
 246         struct ttm_mem_reg *old_mem = &bo->mem;
 247
 248         BUG_ON(old_mem->mm_node != NULL);
 249         *old_mem = *new_mem;
 250         new_mem->mm_node = NULL;
 251 }
 252
 253 static int amdgpu_mm_node_addr(struct ttm_buffer_object *bo,
 254                                struct drm_mm_node *mm_node,
 255                                struct ttm_mem_reg *mem,
 256                                uint64_t *addr)
 257 {
 258         int r;
 259
 260         switch (mem->mem_type) {
 261         case TTM_PL_TT:
 262                 r = amdgpu_ttm_bind(bo, mem);
 263                 if (r)
 264                         return r;
 265
 266         case TTM_PL_VRAM:
 267                 *addr = mm_node->start << PAGE_SHIFT;
 268                 *addr += bo->bdev->man[mem->mem_type].gpu_offset;
 269                 break;
 270         default:
 271                 DRM_ERROR("Unknown placement %d\n", mem->mem_type);
 272                 return -EINVAL;
 273         }
 274
 275         return 0;
 276 }
 277
 278 static int amdgpu_move_blit(struct ttm_buffer_object *bo,
 279                             bool evict, bool no_wait_gpu,
 280                             struct ttm_mem_reg *new_mem,
 281                             struct ttm_mem_reg *old_mem)
 282 {
 283         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 284         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
 285
 286         struct drm_mm_node *old_mm, *new_mm;
 287         uint64_t old_start, old_size, new_start, new_size;
 288         unsigned long num_pages;
 289         struct dma_fence *fence = NULL;
 290         int r;
 291
 292         BUILD_BUG_ON((PAGE_SIZE % AMDGPU_GPU_PAGE_SIZE) != 0);
 293
 294         if (!ring->ready) {
 295                 DRM_ERROR("Trying to move memory with ring turned off.\n");
 296                 return -EINVAL;
 297         }
 298
 299         old_mm = old_mem->mm_node;
 300         r = amdgpu_mm_node_addr(bo, old_mm, old_mem, &old_start);
 301         if (r)
 302                 return r;
 303         old_size = old_mm->size;
 304
 305
 306         new_mm = new_mem->mm_node;
 307         r = amdgpu_mm_node_addr(bo, new_mm, new_mem, &new_start);
 308         if (r)
 309                 return r;
 310         new_size = new_mm->size;
 311
 312         num_pages = new_mem->num_pages;
 313         while (num_pages) {
 314                 unsigned long cur_pages = min(old_size, new_size);
 315                 struct dma_fence *next;
 316
 317                 r = amdgpu_copy_buffer(ring, old_start, new_start,
 318                                        cur_pages * PAGE_SIZE,
 319                                        bo->resv, &next, false);
 320                 if (r)
 321                         goto error;
 322
 323                 dma_fence_put(fence);
 324                 fence = next;
 325
 326                 num_pages -= cur_pages;
 327                 if (!num_pages)
 328                         break;
 329
 330                 old_size -= cur_pages;
 331                 if (!old_size) {
 332                         r = amdgpu_mm_node_addr(bo, ++old_mm, old_mem,
 333                                                 &old_start);
 334                         if (r)
 335                                 goto error;
 336                         old_size = old_mm->size;
 337                 } else {
 338                         old_start += cur_pages * PAGE_SIZE;
 339                 }
 340
 341                 new_size -= cur_pages;
 342                 if (!new_size) {
 343                         r = amdgpu_mm_node_addr(bo, ++new_mm, new_mem,
 344                                                 &new_start);
 345                         if (r)
 346                                 goto error;
 347
 348                         new_size = new_mm->size;
 349                 } else {
 350                         new_start += cur_pages * PAGE_SIZE;
 351                 }
 352         }
 353
 354         r = ttm_bo_pipeline_move(bo, fence, evict, new_mem);
 355         dma_fence_put(fence);
 356         return r;
 357
 358 error:
 359         if (fence)
 360                 dma_fence_wait(fence, false);
 361         dma_fence_put(fence);
 362         return r;
 363 }
 364
 365 static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo,
 366                                 bool evict, bool interruptible,
 367                                 bool no_wait_gpu,
 368                                 struct ttm_mem_reg *new_mem)
 369 {
 370         struct amdgpu_device *adev;
 371         struct ttm_mem_reg *old_mem = &bo->mem;
 372         struct ttm_mem_reg tmp_mem;
 373         struct ttm_place placements;
 374         struct ttm_placement placement;
 375         int r;
 376
 377         adev = amdgpu_ttm_adev(bo->bdev);
 378         tmp_mem = *new_mem;
 379         tmp_mem.mm_node = NULL;
 380         placement.num_placement = 1;
 381         placement.placement = &placements;
 382         placement.num_busy_placement = 1;
 383         placement.busy_placement = &placements;
 384         placements.fpfn = 0;
 385         placements.lpfn = adev->mc.gtt_size >> PAGE_SHIFT;
 386         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 387         r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
 388                              interruptible, no_wait_gpu);
 389         if (unlikely(r)) {
 390                 return r;
 391         }
 392
 393         r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
 394         if (unlikely(r)) {
 395                 goto out_cleanup;
 396         }
 397
 398         r = ttm_tt_bind(bo->ttm, &tmp_mem);
 399         if (unlikely(r)) {
 400                 goto out_cleanup;
 401         }
 402         r = amdgpu_move_blit(bo, true, no_wait_gpu, &tmp_mem, old_mem);
 403         if (unlikely(r)) {
 404                 goto out_cleanup;
 405         }
 406         r = ttm_bo_move_ttm(bo, interruptible, no_wait_gpu, new_mem);
 407 out_cleanup:
 408         ttm_bo_mem_put(bo, &tmp_mem);
 409         return r;
 410 }
 411
 412 static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo,
 413                                 bool evict, bool interruptible,
 414                                 bool no_wait_gpu,
 415                                 struct ttm_mem_reg *new_mem)
 416 {
 417         struct amdgpu_device *adev;
 418         struct ttm_mem_reg *old_mem = &bo->mem;
 419         struct ttm_mem_reg tmp_mem;
 420         struct ttm_placement placement;
 421         struct ttm_place placements;
 422         int r;
 423
 424         adev = amdgpu_ttm_adev(bo->bdev);
 425         tmp_mem = *new_mem;
 426         tmp_mem.mm_node = NULL;
 427         placement.num_placement = 1;
 428         placement.placement = &placements;
 429         placement.num_busy_placement = 1;
 430         placement.busy_placement = &placements;
 431         placements.fpfn = 0;
 432         placements.lpfn = adev->mc.gtt_size >> PAGE_SHIFT;
 433         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 434         r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
 435                              interruptible, no_wait_gpu);
 436         if (unlikely(r)) {
 437                 return r;
 438         }
 439         r = ttm_bo_move_ttm(bo, interruptible, no_wait_gpu, &tmp_mem);
 440         if (unlikely(r)) {
 441                 goto out_cleanup;
 442         }
 443         r = amdgpu_move_blit(bo, true, no_wait_gpu, new_mem, old_mem);
 444         if (unlikely(r)) {
 445                 goto out_cleanup;
 446         }
 447 out_cleanup:
 448         ttm_bo_mem_put(bo, &tmp_mem);
 449         return r;
 450 }
 451
 452 static int amdgpu_bo_move(struct ttm_buffer_object *bo,
 453                         bool evict, bool interruptible,
 454                         bool no_wait_gpu,
 455                         struct ttm_mem_reg *new_mem)
 456 {
 457         struct amdgpu_device *adev;
 458         struct amdgpu_bo *abo;
 459         struct ttm_mem_reg *old_mem = &bo->mem;
 460         int r;
 461
 462         /* Can't move a pinned BO */
 463         abo = container_of(bo, struct amdgpu_bo, tbo);
 464         if (WARN_ON_ONCE(abo->pin_count > 0))
 465                 return -EINVAL;
 466
 467         adev = amdgpu_ttm_adev(bo->bdev);
 468
 469         if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
 470                 amdgpu_move_null(bo, new_mem);
 471                 return 0;
 472         }
 473         if ((old_mem->mem_type == TTM_PL_TT &&
 474              new_mem->mem_type == TTM_PL_SYSTEM) ||
 475             (old_mem->mem_type == TTM_PL_SYSTEM &&
 476              new_mem->mem_type == TTM_PL_TT)) {
 477                 /* bind is enough */
 478                 amdgpu_move_null(bo, new_mem);
 479                 return 0;
 480         }
 481         if (adev->mman.buffer_funcs == NULL ||
 482             adev->mman.buffer_funcs_ring == NULL ||
 483             !adev->mman.buffer_funcs_ring->ready) {
 484                 /* use memcpy */
 485                 goto memcpy;
 486         }
 487
 488         if (old_mem->mem_type == TTM_PL_VRAM &&
 489             new_mem->mem_type == TTM_PL_SYSTEM) {
 490                 r = amdgpu_move_vram_ram(bo, evict, interruptible,
 491                                         no_wait_gpu, new_mem);
 492         } else if (old_mem->mem_type == TTM_PL_SYSTEM &&
 493                    new_mem->mem_type == TTM_PL_VRAM) {
 494                 r = amdgpu_move_ram_vram(bo, evict, interruptible,
 495                                             no_wait_gpu, new_mem);
 496         } else {
 497                 r = amdgpu_move_blit(bo, evict, no_wait_gpu, new_mem, old_mem);
 498         }
 499
 500         if (r) {
 501 memcpy:
 502                 r = ttm_bo_move_memcpy(bo, interruptible, no_wait_gpu, new_mem);
 503                 if (r) {
 504                         return r;
 505                 }
 506         }
 507
 508         /* update statistics */
 509         atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &adev->num_bytes_moved);
 510         return 0;
 511 }
 512
 513 static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 514 {
 515         struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
 516         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 517
 518         mem->bus.addr = NULL;
 519         mem->bus.offset = 0;
 520         mem->bus.size = mem->num_pages << PAGE_SHIFT;
 521         mem->bus.base = 0;
 522         mem->bus.is_iomem = false;
 523         if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
 524                 return -EINVAL;
 525         switch (mem->mem_type) {
 526         case TTM_PL_SYSTEM:
 527                 /* system memory */
 528                 return 0;
 529         case TTM_PL_TT:
 530                 break;
 531         case TTM_PL_VRAM:
 532                 mem->bus.offset = mem->start << PAGE_SHIFT;
 533                 /* check if it's visible */
 534                 if ((mem->bus.offset + mem->bus.size) > adev->mc.visible_vram_size)
 535                         return -EINVAL;
 536                 mem->bus.base = adev->mc.aper_base;
 537                 mem->bus.is_iomem = true;
 538 #ifdef __alpha__
 539                 /*
 540                  * Alpha: use bus.addr to hold the ioremap() return,
 541                  * so we can modify bus.base below.
 542                  */
 543                 if (mem->placement & TTM_PL_FLAG_WC)
 544                         mem->bus.addr =
 545                                 ioremap_wc(mem->bus.base + mem->bus.offset,
 546                                            mem->bus.size);
 547                 else
 548                         mem->bus.addr =
 549                                 ioremap_nocache(mem->bus.base + mem->bus.offset,
 550                                                 mem->bus.size);
 551
 552                 /*
 553                  * Alpha: Use just the bus offset plus
 554                  * the hose/domain memory base for bus.base.
 555                  * It then can be used to build PTEs for VRAM
 556                  * access, as done in ttm_bo_vm_fault().
 557                  */
 558                 mem->bus.base = (mem->bus.base & 0x0ffffffffUL) +
 559                         adev->ddev->hose->dense_mem_base;
 560 #endif
 561                 break;
 562         default:
 563                 return -EINVAL;
 564         }
 565         return 0;
 566 }
 567
 568 static void amdgpu_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 569 {
 570 }
 571
 572 /*
 573  * TTM backend functions.
 574  */
 575 struct amdgpu_ttm_gup_task_list {
 576         struct list_head        list;
 577         struct task_struct      *task;
 578 };
 579
 580 struct amdgpu_ttm_tt {
 581         struct ttm_dma_tt       ttm;
 582         struct amdgpu_device    *adev;
 583         u64                     offset;
 584         uint64_t                userptr;
 585         struct mm_struct        *usermm;
 586         uint32_t                userflags;
 587         spinlock_t              guptasklock;
 588         struct list_head        guptasks;
 589         atomic_t                mmu_invalidations;
 590         struct list_head        list;
 591 };
 592
 593 int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages)
 594 {
 595         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 596         unsigned int flags = 0;
 597         unsigned pinned = 0;
 598         int r;
 599
 600         if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY))
 601                 flags |= FOLL_WRITE;
 602
 603         if (gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) {
 604                 /* check that we only use anonymous memory
 605                    to prevent problems with writeback */
 606                 unsigned long end = gtt->userptr + ttm->num_pages * PAGE_SIZE;
 607                 struct vm_area_struct *vma;
 608
 609                 vma = find_vma(gtt->usermm, gtt->userptr);
 610                 if (!vma || vma->vm_file || vma->vm_end < end)
 611                         return -EPERM;
 612         }
 613
 614         do {
 615                 unsigned num_pages = ttm->num_pages - pinned;
 616                 uint64_t userptr = gtt->userptr + pinned * PAGE_SIZE;
 617                 struct page **p = pages + pinned;
 618                 struct amdgpu_ttm_gup_task_list guptask;
 619
 620                 guptask.task = current;
 621                 spin_lock(&gtt->guptasklock);
 622                 list_add(&guptask.list, &gtt->guptasks);
 623                 spin_unlock(&gtt->guptasklock);
 624
 625                 r = get_user_pages(userptr, num_pages, flags, p, NULL);
 626
 627                 spin_lock(&gtt->guptasklock);
 628                 list_del(&guptask.list);
 629                 spin_unlock(&gtt->guptasklock);
 630
 631                 if (r < 0)
 632                         goto release_pages;
 633
 634                 pinned += r;
 635
 636         } while (pinned < ttm->num_pages);
 637
 638         return 0;
 639
 640 release_pages:
 641         release_pages(pages, pinned, 0);
 642         return r;
 643 }
 644
 645 /* prepare the sg table with the user pages */
 646 static int amdgpu_ttm_tt_pin_userptr(struct ttm_tt *ttm)
 647 {
 648         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
 649         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 650         unsigned nents;
 651         int r;
 652
 653         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 654         enum dma_data_direction direction = write ?
 655                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 656
 657         r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
 658                                       ttm->num_pages << PAGE_SHIFT,
 659                                       GFP_KERNEL);
 660         if (r)
 661                 goto release_sg;
 662
 663         r = -ENOMEM;
 664         nents = dma_map_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
 665         if (nents != ttm->sg->nents)
 666                 goto release_sg;
 667
 668         drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
 669                                          gtt->ttm.dma_address, ttm->num_pages);
 670
 671         return 0;
 672
 673 release_sg:
 674         kfree(ttm->sg);
 675         return r;
 676 }
 677
 678 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_tt *ttm)
 679 {
 680         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
 681         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 682         struct sg_page_iter sg_iter;
 683
 684         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 685         enum dma_data_direction direction = write ?
 686                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 687
 688         /* double check that we don't free the table twice */
 689         if (!ttm->sg->sgl)
 690                 return;
 691
 692         /* free the sg table and pages again */
 693         dma_unmap_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
 694
 695         for_each_sg_page(ttm->sg->sgl, &sg_iter, ttm->sg->nents, 0) {
 696                 struct page *page = sg_page_iter_page(&sg_iter);
 697                 if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY))
 698                         set_page_dirty(page);
 699
 700                 mark_page_accessed(page);
 701                 put_page(page);
 702         }
 703
 704         sg_free_table(ttm->sg);
 705 }
 706
 707 static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm,
 708                                    struct ttm_mem_reg *bo_mem)
 709 {
 710         struct amdgpu_ttm_tt *gtt = (void*)ttm;
 711         int r;
 712
 713         if (gtt->userptr) {
 714                 r = amdgpu_ttm_tt_pin_userptr(ttm);
 715                 if (r) {
 716                         DRM_ERROR("failed to pin userptr\n");
 717                         return r;
 718                 }
 719         }
 720         if (!ttm->num_pages) {
 721                 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
 722                      ttm->num_pages, bo_mem, ttm);
 723         }
 724
 725         if (bo_mem->mem_type == AMDGPU_PL_GDS ||
 726             bo_mem->mem_type == AMDGPU_PL_GWS ||
 727             bo_mem->mem_type == AMDGPU_PL_OA)
 728                 return -EINVAL;
 729
 730         return 0;
 731 }
 732
 733 bool amdgpu_ttm_is_bound(struct ttm_tt *ttm)
 734 {
 735         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 736
 737         return gtt && !list_empty(&gtt->list);
 738 }
 739
 740 int amdgpu_ttm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *bo_mem)
 741 {
 742         struct ttm_tt *ttm = bo->ttm;
 743         struct amdgpu_ttm_tt *gtt = (void *)bo->ttm;
 744         uint32_t flags;
 745         int r;
 746
 747         if (!ttm || amdgpu_ttm_is_bound(ttm))
 748                 return 0;
 749
 750         r = amdgpu_gtt_mgr_alloc(&bo->bdev->man[TTM_PL_TT], bo,
 751                                  NULL, bo_mem);
 752         if (r) {
 753                 DRM_ERROR("Failed to allocate GTT address space (%d)\n", r);
 754                 return r;
 755         }
 756
 757         flags = amdgpu_ttm_tt_pte_flags(gtt->adev, ttm, bo_mem);
 758         gtt->offset = (u64)bo_mem->start << PAGE_SHIFT;
 759         r = amdgpu_gart_bind(gtt->adev, gtt->offset, ttm->num_pages,
 760                 ttm->pages, gtt->ttm.dma_address, flags);
 761
 762         if (r) {
 763                 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
 764                           ttm->num_pages, gtt->offset);
 765                 return r;
 766         }
 767         spin_lock(&gtt->adev->gtt_list_lock);
 768         list_add_tail(&gtt->list, &gtt->adev->gtt_list);
 769         spin_unlock(&gtt->adev->gtt_list_lock);
 770         return 0;
 771 }
 772
 773 int amdgpu_ttm_recover_gart(struct amdgpu_device *adev)
 774 {
 775         struct amdgpu_ttm_tt *gtt, *tmp;
 776         struct ttm_mem_reg bo_mem;
 777         uint32_t flags;
 778         int r;
 779
 780         bo_mem.mem_type = TTM_PL_TT;
 781         spin_lock(&adev->gtt_list_lock);
 782         list_for_each_entry_safe(gtt, tmp, &adev->gtt_list, list) {
 783                 flags = amdgpu_ttm_tt_pte_flags(gtt->adev, &gtt->ttm.ttm, &bo_mem);
 784                 r = amdgpu_gart_bind(adev, gtt->offset, gtt->ttm.ttm.num_pages,
 785                                      gtt->ttm.ttm.pages, gtt->ttm.dma_address,
 786                                      flags);
 787                 if (r) {
 788                         spin_unlock(&adev->gtt_list_lock);
 789                         DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
 790                                   gtt->ttm.ttm.num_pages, gtt->offset);
 791                         return r;
 792                 }
 793         }
 794         spin_unlock(&adev->gtt_list_lock);
 795         return 0;
 796 }
 797
 798 static int amdgpu_ttm_backend_unbind(struct ttm_tt *ttm)
 799 {
 800         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 801
 802         if (gtt->userptr)
 803                 amdgpu_ttm_tt_unpin_userptr(ttm);
 804
 805         if (!amdgpu_ttm_is_bound(ttm))
 806                 return 0;
 807
 808         /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
 809         if (gtt->adev->gart.ready)
 810                 amdgpu_gart_unbind(gtt->adev, gtt->offset, ttm->num_pages);
 811
 812         spin_lock(&gtt->adev->gtt_list_lock);
 813         list_del_init(&gtt->list);
 814         spin_unlock(&gtt->adev->gtt_list_lock);
 815
 816         return 0;
 817 }
 818
 819 static void amdgpu_ttm_backend_destroy(struct ttm_tt *ttm)
 820 {
 821         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 822
 823         ttm_dma_tt_fini(&gtt->ttm);
 824         kfree(gtt);
 825 }
 826
 827 static struct ttm_backend_func amdgpu_backend_func = {
 828         .bind = &amdgpu_ttm_backend_bind,
 829         .unbind = &amdgpu_ttm_backend_unbind,
 830         .destroy = &amdgpu_ttm_backend_destroy,
 831 };
 832
 833 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_bo_device *bdev,
 834                                     unsigned long size, uint32_t page_flags,
 835                                     struct page *dummy_read_page)
 836 {
 837         struct amdgpu_device *adev;
 838         struct amdgpu_ttm_tt *gtt;
 839
 840         adev = amdgpu_ttm_adev(bdev);
 841
 842         gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
 843         if (gtt == NULL) {
 844                 return NULL;
 845         }
 846         gtt->ttm.ttm.func = &amdgpu_backend_func;
 847         gtt->adev = adev;
 848         if (ttm_dma_tt_init(&gtt->ttm, bdev, size, page_flags, dummy_read_page)) {
 849                 kfree(gtt);
 850                 return NULL;
 851         }
 852         INIT_LIST_HEAD(&gtt->list);
 853         return &gtt->ttm.ttm;
 854 }
 855
 856 static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm)
 857 {
 858         struct amdgpu_device *adev;
 859         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 860         unsigned i;
 861         int r;
 862         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
 863
 864         if (ttm->state != tt_unpopulated)
 865                 return 0;
 866
 867         if (gtt && gtt->userptr) {
 868                 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
 869                 if (!ttm->sg)
 870                         return -ENOMEM;
 871
 872                 ttm->page_flags |= TTM_PAGE_FLAG_SG;
 873                 ttm->state = tt_unbound;
 874                 return 0;
 875         }
 876
 877         if (slave && ttm->sg) {
 878                 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
 879                                                  gtt->ttm.dma_address, ttm->num_pages);
 880                 ttm->state = tt_unbound;
 881                 return 0;
 882         }
 883
 884         adev = amdgpu_ttm_adev(ttm->bdev);
 885
 886 #ifdef CONFIG_SWIOTLB
 887         if (swiotlb_nr_tbl()) {
 888                 return ttm_dma_populate(&gtt->ttm, adev->dev);
 889         }
 890 #endif
 891
 892         r = ttm_pool_populate(ttm);
 893         if (r) {
 894                 return r;
 895         }
 896
 897         for (i = 0; i < ttm->num_pages; i++) {
 898                 gtt->ttm.dma_address[i] = pci_map_page(adev->pdev, ttm->pages[i],
 899                                                        0, PAGE_SIZE,
 900                                                        PCI_DMA_BIDIRECTIONAL);
 901                 if (pci_dma_mapping_error(adev->pdev, gtt->ttm.dma_address[i])) {
 902                         while (i--) {
 903                                 pci_unmap_page(adev->pdev, gtt->ttm.dma_address[i],
 904                                                PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 905                                 gtt->ttm.dma_address[i] = 0;
 906                         }
 907                         ttm_pool_unpopulate(ttm);
 908                         return -EFAULT;
 909                 }
 910         }
 911         return 0;
 912 }
 913
 914 static void amdgpu_ttm_tt_unpopulate(struct ttm_tt *ttm)
 915 {
 916         struct amdgpu_device *adev;
 917         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 918         unsigned i;
 919         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
 920
 921         if (gtt && gtt->userptr) {
 922                 kfree(ttm->sg);
 923                 ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
 924                 return;
 925         }
 926
 927         if (slave)
 928                 return;
 929
 930         adev = amdgpu_ttm_adev(ttm->bdev);
 931
 932 #ifdef CONFIG_SWIOTLB
 933         if (swiotlb_nr_tbl()) {
 934                 ttm_dma_unpopulate(&gtt->ttm, adev->dev);
 935                 return;
 936         }
 937 #endif
 938
 939         for (i = 0; i < ttm->num_pages; i++) {
 940                 if (gtt->ttm.dma_address[i]) {
 941                         pci_unmap_page(adev->pdev, gtt->ttm.dma_address[i],
 942                                        PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 943                 }
 944         }
 945
 946         ttm_pool_unpopulate(ttm);
 947 }
 948
 949 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
 950                               uint32_t flags)
 951 {
 952         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 953
 954         if (gtt == NULL)
 955                 return -EINVAL;
 956
 957         gtt->userptr = addr;
 958         gtt->usermm = current->mm;
 959         gtt->userflags = flags;
 960         spin_lock_init(&gtt->guptasklock);
 961         INIT_LIST_HEAD(&gtt->guptasks);
 962         atomic_set(&gtt->mmu_invalidations, 0);
 963
 964         return 0;
 965 }
 966
 967 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
 968 {
 969         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 970
 971         if (gtt == NULL)
 972                 return NULL;
 973
 974         return gtt->usermm;
 975 }
 976
 977 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
 978                                   unsigned long end)
 979 {
 980         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 981         struct amdgpu_ttm_gup_task_list *entry;
 982         unsigned long size;
 983
 984         if (gtt == NULL || !gtt->userptr)
 985                 return false;
 986
 987         size = (unsigned long)gtt->ttm.ttm.num_pages * PAGE_SIZE;
 988         if (gtt->userptr > end || gtt->userptr + size <= start)
 989                 return false;
 990
 991         spin_lock(&gtt->guptasklock);
 992         list_for_each_entry(entry, &gtt->guptasks, list) {
 993                 if (entry->task == current) {
 994                         spin_unlock(&gtt->guptasklock);
 995                         return false;
 996                 }
 997         }
 998         spin_unlock(&gtt->guptasklock);
 999
1000         atomic_inc(&gtt->mmu_invalidations);
1001
1002         return true;
1003 }
1004
1005 bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
1006                                        int *last_invalidated)
1007 {
1008         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1009         int prev_invalidated = *last_invalidated;
1010
1011         *last_invalidated = atomic_read(&gtt->mmu_invalidations);
1012         return prev_invalidated != *last_invalidated;
1013 }
1014
1015 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
1016 {
1017         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1018
1019         if (gtt == NULL)
1020                 return false;
1021
1022         return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1023 }
1024
1025 uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
1026                                  struct ttm_mem_reg *mem)
1027 {
1028         uint32_t flags = 0;
1029
1030         if (mem && mem->mem_type != TTM_PL_SYSTEM)
1031                 flags |= AMDGPU_PTE_VALID;
1032
1033         if (mem && mem->mem_type == TTM_PL_TT) {
1034                 flags |= AMDGPU_PTE_SYSTEM;
1035
1036                 if (ttm->caching_state == tt_cached)
1037                         flags |= AMDGPU_PTE_SNOOPED;
1038         }
1039
1040         if (adev->asic_type >= CHIP_TONGA)
1041                 flags |= AMDGPU_PTE_EXECUTABLE;
1042
1043         flags |= AMDGPU_PTE_READABLE;
1044
1045         if (!amdgpu_ttm_tt_is_readonly(ttm))
1046                 flags |= AMDGPU_PTE_WRITEABLE;
1047
1048         return flags;
1049 }
1050
1051 static void amdgpu_ttm_lru_removal(struct ttm_buffer_object *tbo)
1052 {
1053         struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
1054         unsigned i, j;
1055
1056         for (i = 0; i < AMDGPU_TTM_LRU_SIZE; ++i) {
1057                 struct amdgpu_mman_lru *lru = &adev->mman.log2_size[i];
1058
1059                 for (j = 0; j < TTM_NUM_MEM_TYPES; ++j)
1060                         if (&tbo->lru == lru->lru[j])
1061                                 lru->lru[j] = tbo->lru.prev;
1062
1063                 if (&tbo->swap == lru->swap_lru)
1064                         lru->swap_lru = tbo->swap.prev;
1065         }
1066 }
1067
1068 static struct amdgpu_mman_lru *amdgpu_ttm_lru(struct ttm_buffer_object *tbo)
1069 {
1070         struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
1071         unsigned log2_size = min(ilog2(tbo->num_pages),
1072                                  AMDGPU_TTM_LRU_SIZE - 1);
1073
1074         return &adev->mman.log2_size[log2_size];
1075 }
1076
1077 static struct list_head *amdgpu_ttm_lru_tail(struct ttm_buffer_object *tbo)
1078 {
1079         struct amdgpu_mman_lru *lru = amdgpu_ttm_lru(tbo);
1080         struct list_head *res = lru->lru[tbo->mem.mem_type];
1081
1082         lru->lru[tbo->mem.mem_type] = &tbo->lru;
1083         while ((++lru)->lru[tbo->mem.mem_type] == res)
1084                 lru->lru[tbo->mem.mem_type] = &tbo->lru;
1085
1086         return res;
1087 }
1088
1089 static struct list_head *amdgpu_ttm_swap_lru_tail(struct ttm_buffer_object *tbo)
1090 {
1091         struct amdgpu_mman_lru *lru = amdgpu_ttm_lru(tbo);
1092         struct list_head *res = lru->swap_lru;
1093
1094         lru->swap_lru = &tbo->swap;
1095         while ((++lru)->swap_lru == res)
1096                 lru->swap_lru = &tbo->swap;
1097
1098         return res;
1099 }
1100
1101 static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
1102                                             const struct ttm_place *place)
1103 {
1104         if (bo->mem.mem_type == TTM_PL_VRAM &&
1105             bo->mem.start == AMDGPU_BO_INVALID_OFFSET) {
1106                 unsigned long num_pages = bo->mem.num_pages;
1107                 struct drm_mm_node *node = bo->mem.mm_node;
1108
1109                 /* Check each drm MM node individually */
1110                 while (num_pages) {
1111                         if (place->fpfn < (node->start + node->size) &&
1112                             !(place->lpfn && place->lpfn <= node->start))
1113                                 return true;
1114
1115                         num_pages -= node->size;
1116                         ++node;
1117                 }
1118
1119                 return false;
1120         }
1121
1122         return ttm_bo_eviction_valuable(bo, place);
1123 }
1124
1125 static struct ttm_bo_driver amdgpu_bo_driver = {
1126         .ttm_tt_create = &amdgpu_ttm_tt_create,
1127         .ttm_tt_populate = &amdgpu_ttm_tt_populate,
1128         .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate,
1129         .invalidate_caches = &amdgpu_invalidate_caches,
1130         .init_mem_type = &amdgpu_init_mem_type,
1131         .eviction_valuable = amdgpu_ttm_bo_eviction_valuable,
1132         .evict_flags = &amdgpu_evict_flags,
1133         .move = &amdgpu_bo_move,
1134         .verify_access = &amdgpu_verify_access,
1135         .move_notify = &amdgpu_bo_move_notify,
1136         .fault_reserve_notify = &amdgpu_bo_fault_reserve_notify,
1137         .io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
1138         .io_mem_free = &amdgpu_ttm_io_mem_free,
1139         .lru_removal = &amdgpu_ttm_lru_removal,
1140         .lru_tail = &amdgpu_ttm_lru_tail,
1141         .swap_lru_tail = &amdgpu_ttm_swap_lru_tail,
1142 };
1143
1144 int amdgpu_ttm_init(struct amdgpu_device *adev)
1145 {
1146         unsigned i, j;
1147         int r;
1148
1149         r = amdgpu_ttm_global_init(adev);
1150         if (r) {
1151                 return r;
1152         }
1153         /* No others user of address space so set it to 0 */
1154         r = ttm_bo_device_init(&adev->mman.bdev,
1155                                adev->mman.bo_global_ref.ref.object,
1156                                &amdgpu_bo_driver,
1157                                adev->ddev->anon_inode->i_mapping,
1158                                DRM_FILE_PAGE_OFFSET,
1159                                adev->need_dma32);
1160         if (r) {
1161                 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
1162                 return r;
1163         }
1164
1165         for (i = 0; i < AMDGPU_TTM_LRU_SIZE; ++i) {
1166                 struct amdgpu_mman_lru *lru = &adev->mman.log2_size[i];
1167
1168                 for (j = 0; j < TTM_NUM_MEM_TYPES; ++j)
1169                         lru->lru[j] = &adev->mman.bdev.man[j].lru;
1170                 lru->swap_lru = &adev->mman.bdev.glob->swap_lru;
1171         }
1172
1173         for (j = 0; j < TTM_NUM_MEM_TYPES; ++j)
1174                 adev->mman.guard.lru[j] = NULL;
1175         adev->mman.guard.swap_lru = NULL;
1176
1177         adev->mman.initialized = true;
1178         r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_VRAM,
1179                                 adev->mc.real_vram_size >> PAGE_SHIFT);
1180         if (r) {
1181                 DRM_ERROR("Failed initializing VRAM heap.\n");
1182                 return r;
1183         }
1184         /* Change the size here instead of the init above so only lpfn is affected */
1185         amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
1186
1187         r = amdgpu_bo_create(adev, 256 * 1024, PAGE_SIZE, true,
1188                              AMDGPU_GEM_DOMAIN_VRAM,
1189                              AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
1190                              AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
1191                              NULL, NULL, &adev->stollen_vga_memory);
1192         if (r) {
1193                 return r;
1194         }
1195         r = amdgpu_bo_reserve(adev->stollen_vga_memory, false);
1196         if (r)
1197                 return r;
1198         r = amdgpu_bo_pin(adev->stollen_vga_memory, AMDGPU_GEM_DOMAIN_VRAM, NULL);
1199         amdgpu_bo_unreserve(adev->stollen_vga_memory);
1200         if (r) {
1201                 amdgpu_bo_unref(&adev->stollen_vga_memory);
1202                 return r;
1203         }
1204         DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
1205                  (unsigned) (adev->mc.real_vram_size / (1024 * 1024)));
1206         r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_TT,
1207                                 adev->mc.gtt_size >> PAGE_SHIFT);
1208         if (r) {
1209                 DRM_ERROR("Failed initializing GTT heap.\n");
1210                 return r;
1211         }
1212         DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
1213                  (unsigned)(adev->mc.gtt_size / (1024 * 1024)));
1214
1215         adev->gds.mem.total_size = adev->gds.mem.total_size << AMDGPU_GDS_SHIFT;
1216         adev->gds.mem.gfx_partition_size = adev->gds.mem.gfx_partition_size << AMDGPU_GDS_SHIFT;
1217         adev->gds.mem.cs_partition_size = adev->gds.mem.cs_partition_size << AMDGPU_GDS_SHIFT;
1218         adev->gds.gws.total_size = adev->gds.gws.total_size << AMDGPU_GWS_SHIFT;
1219         adev->gds.gws.gfx_partition_size = adev->gds.gws.gfx_partition_size << AMDGPU_GWS_SHIFT;
1220         adev->gds.gws.cs_partition_size = adev->gds.gws.cs_partition_size << AMDGPU_GWS_SHIFT;
1221         adev->gds.oa.total_size = adev->gds.oa.total_size << AMDGPU_OA_SHIFT;
1222         adev->gds.oa.gfx_partition_size = adev->gds.oa.gfx_partition_size << AMDGPU_OA_SHIFT;
1223         adev->gds.oa.cs_partition_size = adev->gds.oa.cs_partition_size << AMDGPU_OA_SHIFT;
1224         /* GDS Memory */
1225         r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GDS,
1226                                 adev->gds.mem.total_size >> PAGE_SHIFT);
1227         if (r) {
1228                 DRM_ERROR("Failed initializing GDS heap.\n");
1229                 return r;
1230         }
1231
1232         /* GWS */
1233         r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GWS,
1234                                 adev->gds.gws.total_size >> PAGE_SHIFT);
1235         if (r) {
1236                 DRM_ERROR("Failed initializing gws heap.\n");
1237                 return r;
1238         }
1239
1240         /* OA */
1241         r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_OA,
1242                                 adev->gds.oa.total_size >> PAGE_SHIFT);
1243         if (r) {
1244                 DRM_ERROR("Failed initializing oa heap.\n");
1245                 return r;
1246         }
1247
1248         r = amdgpu_ttm_debugfs_init(adev);
1249         if (r) {
1250                 DRM_ERROR("Failed to init debugfs\n");
1251                 return r;
1252         }
1253         return 0;
1254 }
1255
1256 void amdgpu_ttm_fini(struct amdgpu_device *adev)
1257 {
1258         int r;
1259
1260         if (!adev->mman.initialized)
1261                 return;
1262         amdgpu_ttm_debugfs_fini(adev);
1263         if (adev->stollen_vga_memory) {
1264                 r = amdgpu_bo_reserve(adev->stollen_vga_memory, false);
1265                 if (r == 0) {
1266                         amdgpu_bo_unpin(adev->stollen_vga_memory);
1267                         amdgpu_bo_unreserve(adev->stollen_vga_memory);
1268                 }
1269                 amdgpu_bo_unref(&adev->stollen_vga_memory);
1270         }
1271         ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_VRAM);
1272         ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_TT);
1273         ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GDS);
1274         ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GWS);
1275         ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_OA);
1276         ttm_bo_device_release(&adev->mman.bdev);
1277         amdgpu_gart_fini(adev);
1278         amdgpu_ttm_global_fini(adev);
1279         adev->mman.initialized = false;
1280         DRM_INFO("amdgpu: ttm finalized\n");
1281 }
1282
1283 /* this should only be called at bootup or when userspace
1284  * isn't running */
1285 void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size)
1286 {
1287         struct ttm_mem_type_manager *man;
1288
1289         if (!adev->mman.initialized)
1290                 return;
1291
1292         man = &adev->mman.bdev.man[TTM_PL_VRAM];
1293         /* this just adjusts TTM size idea, which sets lpfn to the correct value */
1294         man->size = size >> PAGE_SHIFT;
1295 }
1296
1297 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma)
1298 {
1299         struct drm_file *file_priv;
1300         struct amdgpu_device *adev;
1301
1302         if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET))
1303                 return -EINVAL;
1304
1305         file_priv = filp->private_data;
1306         adev = file_priv->minor->dev->dev_private;
1307         if (adev == NULL)
1308                 return -EINVAL;
1309
1310         return ttm_bo_mmap(filp, vma, &adev->mman.bdev);
1311 }
1312
1313 int amdgpu_copy_buffer(struct amdgpu_ring *ring,
1314                        uint64_t src_offset,
1315                        uint64_t dst_offset,
1316                        uint32_t byte_count,
1317                        struct reservation_object *resv,
1318                        struct dma_fence **fence, bool direct_submit)
1319 {
1320         struct amdgpu_device *adev = ring->adev;
1321         struct amdgpu_job *job;
1322
1323         uint32_t max_bytes;
1324         unsigned num_loops, num_dw;
1325         unsigned i;
1326         int r;
1327
1328         max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
1329         num_loops = DIV_ROUND_UP(byte_count, max_bytes);
1330         num_dw = num_loops * adev->mman.buffer_funcs->copy_num_dw;
1331
1332         /* for IB padding */
1333         while (num_dw & 0x7)
1334                 num_dw++;
1335
1336         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job);
1337         if (r)
1338                 return r;
1339
1340         if (resv) {
1341                 r = amdgpu_sync_resv(adev, &job->sync, resv,
1342                                      AMDGPU_FENCE_OWNER_UNDEFINED);
1343                 if (r) {
1344                         DRM_ERROR("sync failed (%d).\n", r);
1345                         goto error_free;
1346                 }
1347         }
1348
1349         for (i = 0; i < num_loops; i++) {
1350                 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
1351
1352                 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset,
1353                                         dst_offset, cur_size_in_bytes);
1354
1355                 src_offset += cur_size_in_bytes;
1356                 dst_offset += cur_size_in_bytes;
1357                 byte_count -= cur_size_in_bytes;
1358         }
1359
1360         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
1361         WARN_ON(job->ibs[0].length_dw > num_dw);
1362         if (direct_submit) {
1363                 r = amdgpu_ib_schedule(ring, job->num_ibs, job->ibs,
1364                                        NULL, NULL, fence);
1365                 job->fence = dma_fence_get(*fence);
1366                 if (r)
1367                         DRM_ERROR("Error scheduling IBs (%d)\n", r);
1368                 amdgpu_job_free(job);
1369         } else {
1370                 r = amdgpu_job_submit(job, ring, &adev->mman.entity,
1371                                       AMDGPU_FENCE_OWNER_UNDEFINED, fence);
1372                 if (r)
1373                         goto error_free;
1374         }
1375
1376         return r;
1377
1378 error_free:
1379         amdgpu_job_free(job);
1380         return r;
1381 }
1382
1383 int amdgpu_fill_buffer(struct amdgpu_bo *bo,
1384                        uint32_t src_data,
1385                        struct reservation_object *resv,
1386                        struct dma_fence **fence)
1387 {
1388         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
1389         uint32_t max_bytes = adev->mman.buffer_funcs->fill_max_bytes;
1390         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
1391
1392         struct drm_mm_node *mm_node;
1393         unsigned long num_pages;
1394         unsigned int num_loops, num_dw;
1395
1396         struct amdgpu_job *job;
1397         int r;
1398
1399         if (!ring->ready) {
1400                 DRM_ERROR("Trying to clear memory with ring turned off.\n");
1401                 return -EINVAL;
1402         }
1403
1404         num_pages = bo->tbo.num_pages;
1405         mm_node = bo->tbo.mem.mm_node;
1406         num_loops = 0;
1407         while (num_pages) {
1408                 uint32_t byte_count = mm_node->size << PAGE_SHIFT;
1409
1410                 num_loops += DIV_ROUND_UP(byte_count, max_bytes);
1411                 num_pages -= mm_node->size;
1412                 ++mm_node;
1413         }
1414         num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw;
1415
1416         /* for IB padding */
1417         num_dw += 64;
1418
1419         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job);
1420         if (r)
1421                 return r;
1422
1423         if (resv) {
1424                 r = amdgpu_sync_resv(adev, &job->sync, resv,
1425                                      AMDGPU_FENCE_OWNER_UNDEFINED);
1426                 if (r) {
1427                         DRM_ERROR("sync failed (%d).\n", r);
1428                         goto error_free;
1429                 }
1430         }
1431
1432         num_pages = bo->tbo.num_pages;
1433         mm_node = bo->tbo.mem.mm_node;
1434
1435         while (num_pages) {
1436                 uint32_t byte_count = mm_node->size << PAGE_SHIFT;
1437                 uint64_t dst_addr;
1438
1439                 r = amdgpu_mm_node_addr(&bo->tbo, mm_node,
1440                                         &bo->tbo.mem, &dst_addr);
1441                 if (r)
1442                         return r;
1443
1444                 while (byte_count) {
1445                         uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
1446
1447                         amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data,
1448                                                 dst_addr, cur_size_in_bytes);
1449
1450                         dst_addr += cur_size_in_bytes;
1451                         byte_count -= cur_size_in_bytes;
1452                 }
1453
1454                 num_pages -= mm_node->size;
1455                 ++mm_node;
1456         }
1457
1458         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
1459         WARN_ON(job->ibs[0].length_dw > num_dw);
1460         r = amdgpu_job_submit(job, ring, &adev->mman.entity,
1461                               AMDGPU_FENCE_OWNER_UNDEFINED, fence);
1462         if (r)
1463                 goto error_free;
1464
1465         return 0;
1466
1467 error_free:
1468         amdgpu_job_free(job);
1469         return r;
1470 }
1471
1472 #if defined(CONFIG_DEBUG_FS)
1473
1474 static int amdgpu_mm_dump_table(struct seq_file *m, void *data)
1475 {
1476         struct drm_info_node *node = (struct drm_info_node *)m->private;
1477         unsigned ttm_pl = *(int *)node->info_ent->data;
1478         struct drm_device *dev = node->minor->dev;
1479         struct amdgpu_device *adev = dev->dev_private;
1480         struct drm_mm *mm = (struct drm_mm *)adev->mman.bdev.man[ttm_pl].priv;
1481         struct ttm_bo_global *glob = adev->mman.bdev.glob;
1482         struct drm_printer p = drm_seq_file_printer(m);
1483
1484         spin_lock(&glob->lru_lock);
1485         drm_mm_print(mm, &p);
1486         spin_unlock(&glob->lru_lock);
1487         if (ttm_pl == TTM_PL_VRAM)
1488                 seq_printf(m, "man size:%llu pages, ram usage:%lluMB, vis usage:%lluMB\n",
1489                            adev->mman.bdev.man[ttm_pl].size,
1490                            (u64)atomic64_read(&adev->vram_usage) >> 20,
1491                            (u64)atomic64_read(&adev->vram_vis_usage) >> 20);
1492         return 0;
1493 }
1494
1495 static int ttm_pl_vram = TTM_PL_VRAM;
1496 static int ttm_pl_tt = TTM_PL_TT;
1497
1498 static const struct drm_info_list amdgpu_ttm_debugfs_list[] = {
1499         {"amdgpu_vram_mm", amdgpu_mm_dump_table, 0, &ttm_pl_vram},
1500         {"amdgpu_gtt_mm", amdgpu_mm_dump_table, 0, &ttm_pl_tt},
1501         {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL},
1502 #ifdef CONFIG_SWIOTLB
1503         {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL}
1504 #endif
1505 };
1506
1507 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
1508                                     size_t size, loff_t *pos)
1509 {
1510         struct amdgpu_device *adev = file_inode(f)->i_private;
1511         ssize_t result = 0;
1512         int r;
1513
1514         if (size & 0x3 || *pos & 0x3)
1515                 return -EINVAL;
1516
1517         while (size) {
1518                 unsigned long flags;
1519                 uint32_t value;
1520
1521                 if (*pos >= adev->mc.mc_vram_size)
1522                         return result;
1523
1524                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
1525                 WREG32(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
1526                 WREG32(mmMM_INDEX_HI, *pos >> 31);
1527                 value = RREG32(mmMM_DATA);
1528                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
1529
1530                 r = put_user(value, (uint32_t *)buf);
1531                 if (r)
1532                         return r;
1533
1534                 result += 4;
1535                 buf += 4;
1536                 *pos += 4;
1537                 size -= 4;
1538         }
1539
1540         return result;
1541 }
1542
1543 static const struct file_operations amdgpu_ttm_vram_fops = {
1544         .owner = THIS_MODULE,
1545         .read = amdgpu_ttm_vram_read,
1546         .llseek = default_llseek
1547 };
1548
1549 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
1550
1551 static ssize_t amdgpu_ttm_gtt_read(struct file *f, char __user *buf,
1552                                    size_t size, loff_t *pos)
1553 {
1554         struct amdgpu_device *adev = file_inode(f)->i_private;
1555         ssize_t result = 0;
1556         int r;
1557
1558         while (size) {
1559                 loff_t p = *pos / PAGE_SIZE;
1560                 unsigned off = *pos & ~PAGE_MASK;
1561                 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off);
1562                 struct page *page;
1563                 void *ptr;
1564
1565                 if (p >= adev->gart.num_cpu_pages)
1566                         return result;
1567
1568                 page = adev->gart.pages[p];
1569                 if (page) {
1570                         ptr = kmap(page);
1571                         ptr += off;
1572
1573                         r = copy_to_user(buf, ptr, cur_size);
1574                         kunmap(adev->gart.pages[p]);
1575                 } else
1576                         r = clear_user(buf, cur_size);
1577
1578                 if (r)
1579                         return -EFAULT;
1580
1581                 result += cur_size;
1582                 buf += cur_size;
1583                 *pos += cur_size;
1584                 size -= cur_size;
1585         }
1586
1587         return result;
1588 }
1589
1590 static const struct file_operations amdgpu_ttm_gtt_fops = {
1591         .owner = THIS_MODULE,
1592         .read = amdgpu_ttm_gtt_read,
1593         .llseek = default_llseek
1594 };
1595
1596 #endif
1597
1598 #endif
1599
1600 static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
1601 {
1602 #if defined(CONFIG_DEBUG_FS)
1603         unsigned count;
1604
1605         struct drm_minor *minor = adev->ddev->primary;
1606         struct dentry *ent, *root = minor->debugfs_root;
1607
1608         ent = debugfs_create_file("amdgpu_vram", S_IFREG | S_IRUGO, root,
1609                                   adev, &amdgpu_ttm_vram_fops);
1610         if (IS_ERR(ent))
1611                 return PTR_ERR(ent);
1612         i_size_write(ent->d_inode, adev->mc.mc_vram_size);
1613         adev->mman.vram = ent;
1614
1615 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
1616         ent = debugfs_create_file("amdgpu_gtt", S_IFREG | S_IRUGO, root,
1617                                   adev, &amdgpu_ttm_gtt_fops);
1618         if (IS_ERR(ent))
1619                 return PTR_ERR(ent);
1620         i_size_write(ent->d_inode, adev->mc.gtt_size);
1621         adev->mman.gtt = ent;
1622
1623 #endif
1624         count = ARRAY_SIZE(amdgpu_ttm_debugfs_list);
1625
1626 #ifdef CONFIG_SWIOTLB
1627         if (!swiotlb_nr_tbl())
1628                 --count;
1629 #endif
1630
1631         return amdgpu_debugfs_add_files(adev, amdgpu_ttm_debugfs_list, count);
1632 #else
1633
1634         return 0;
1635 #endif
1636 }
1637
1638 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev)
1639 {
1640 #if defined(CONFIG_DEBUG_FS)
1641
1642         debugfs_remove(adev->mman.vram);
1643         adev->mman.vram = NULL;
1644
1645 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
1646         debugfs_remove(adev->mman.gtt);
1647         adev->mman.gtt = NULL;
1648 #endif
1649
1650 #endif
1651 }