drivers/gpu/drm/amd/amdgpu/dce_v11_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include "drmP.h"
  24 #include "amdgpu.h"
  25 #include "amdgpu_pm.h"
  26 #include "amdgpu_i2c.h"
  27 #include "vid.h"
  28 #include "atom.h"
  29 #include "amdgpu_atombios.h"
  30 #include "atombios_crtc.h"
  31 #include "atombios_encoders.h"
  32 #include "amdgpu_pll.h"
  33 #include "amdgpu_connectors.h"
  34
  35 #include "dce/dce_11_0_d.h"
  36 #include "dce/dce_11_0_sh_mask.h"
  37 #include "dce/dce_11_0_enum.h"
  38 #include "oss/oss_3_0_d.h"
  39 #include "oss/oss_3_0_sh_mask.h"
  40 #include "gmc/gmc_8_1_d.h"
  41 #include "gmc/gmc_8_1_sh_mask.h"
  42
  43 static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev);
  44 static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev);
  45
  46 static const u32 crtc_offsets[] =
  47 {
  48         CRTC0_REGISTER_OFFSET,
  49         CRTC1_REGISTER_OFFSET,
  50         CRTC2_REGISTER_OFFSET,
  51         CRTC3_REGISTER_OFFSET,
  52         CRTC4_REGISTER_OFFSET,
  53         CRTC5_REGISTER_OFFSET,
  54         CRTC6_REGISTER_OFFSET
  55 };
  56
  57 static const u32 hpd_offsets[] =
  58 {
  59         HPD0_REGISTER_OFFSET,
  60         HPD1_REGISTER_OFFSET,
  61         HPD2_REGISTER_OFFSET,
  62         HPD3_REGISTER_OFFSET,
  63         HPD4_REGISTER_OFFSET,
  64         HPD5_REGISTER_OFFSET
  65 };
  66
  67 static const uint32_t dig_offsets[] = {
  68         DIG0_REGISTER_OFFSET,
  69         DIG1_REGISTER_OFFSET,
  70         DIG2_REGISTER_OFFSET,
  71         DIG3_REGISTER_OFFSET,
  72         DIG4_REGISTER_OFFSET,
  73         DIG5_REGISTER_OFFSET,
  74         DIG6_REGISTER_OFFSET,
  75         DIG7_REGISTER_OFFSET,
  76         DIG8_REGISTER_OFFSET
  77 };
  78
  79 static const struct {
  80         uint32_t        reg;
  81         uint32_t        vblank;
  82         uint32_t        vline;
  83         uint32_t        hpd;
  84
  85 } interrupt_status_offsets[] = { {
  86         .reg = mmDISP_INTERRUPT_STATUS,
  87         .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
  88         .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
  89         .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
  90 }, {
  91         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
  92         .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
  93         .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
  94         .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
  95 }, {
  96         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
  97         .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
  98         .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
  99         .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
 100 }, {
 101         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
 102         .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
 103         .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
 104         .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
 105 }, {
 106         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
 107         .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
 108         .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
 109         .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
 110 }, {
 111         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
 112         .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
 113         .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
 114         .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
 115 } };
 116
 117 static const u32 cz_golden_settings_a11[] =
 118 {
 119         mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000,
 120         mmFBC_MISC, 0x1f311fff, 0x14300000,
 121 };
 122
 123 static const u32 cz_mgcg_cgcg_init[] =
 124 {
 125         mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
 126         mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
 127 };
 128
 129 static const u32 stoney_golden_settings_a11[] =
 130 {
 131         mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000,
 132         mmFBC_MISC, 0x1f311fff, 0x14302000,
 133 };
 134
 135 static const u32 polaris11_golden_settings_a11[] =
 136 {
 137         mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
 138         mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
 139         mmFBC_DEBUG1, 0xffffffff, 0x00000008,
 140         mmFBC_MISC, 0x9f313fff, 0x14302008,
 141         mmHDMI_CONTROL, 0x313f031f, 0x00000011,
 142 };
 143
 144 static const u32 polaris10_golden_settings_a11[] =
 145 {
 146         mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
 147         mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
 148         mmFBC_MISC, 0x9f313fff, 0x14302008,
 149         mmHDMI_CONTROL, 0x313f031f, 0x00000011,
 150 };
 151
 152 static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev)
 153 {
 154         switch (adev->asic_type) {
 155         case CHIP_CARRIZO:
 156                 amdgpu_program_register_sequence(adev,
 157                                                  cz_mgcg_cgcg_init,
 158                                                  (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
 159                 amdgpu_program_register_sequence(adev,
 160                                                  cz_golden_settings_a11,
 161                                                  (const u32)ARRAY_SIZE(cz_golden_settings_a11));
 162                 break;
 163         case CHIP_STONEY:
 164                 amdgpu_program_register_sequence(adev,
 165                                                  stoney_golden_settings_a11,
 166                                                  (const u32)ARRAY_SIZE(stoney_golden_settings_a11));
 167                 break;
 168         case CHIP_POLARIS11:
 169                 amdgpu_program_register_sequence(adev,
 170                                                  polaris11_golden_settings_a11,
 171                                                  (const u32)ARRAY_SIZE(polaris11_golden_settings_a11));
 172                 break;
 173         case CHIP_POLARIS10:
 174                 amdgpu_program_register_sequence(adev,
 175                                                  polaris10_golden_settings_a11,
 176                                                  (const u32)ARRAY_SIZE(polaris10_golden_settings_a11));
 177                 break;
 178         default:
 179                 break;
 180         }
 181 }
 182
 183 static u32 dce_v11_0_audio_endpt_rreg(struct amdgpu_device *adev,
 184                                      u32 block_offset, u32 reg)
 185 {
 186         unsigned long flags;
 187         u32 r;
 188
 189         spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
 190         WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
 191         r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
 192         spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
 193
 194         return r;
 195 }
 196
 197 static void dce_v11_0_audio_endpt_wreg(struct amdgpu_device *adev,
 198                                       u32 block_offset, u32 reg, u32 v)
 199 {
 200         unsigned long flags;
 201
 202         spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
 203         WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
 204         WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
 205         spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
 206 }
 207
 208 static bool dce_v11_0_is_in_vblank(struct amdgpu_device *adev, int crtc)
 209 {
 210         if (RREG32(mmCRTC_STATUS + crtc_offsets[crtc]) &
 211                         CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK)
 212                 return true;
 213         else
 214                 return false;
 215 }
 216
 217 static bool dce_v11_0_is_counter_moving(struct amdgpu_device *adev, int crtc)
 218 {
 219         u32 pos1, pos2;
 220
 221         pos1 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
 222         pos2 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
 223
 224         if (pos1 != pos2)
 225                 return true;
 226         else
 227                 return false;
 228 }
 229
 230 /**
 231  * dce_v11_0_vblank_wait - vblank wait asic callback.
 232  *
 233  * @adev: amdgpu_device pointer
 234  * @crtc: crtc to wait for vblank on
 235  *
 236  * Wait for vblank on the requested crtc (evergreen+).
 237  */
 238 static void dce_v11_0_vblank_wait(struct amdgpu_device *adev, int crtc)
 239 {
 240         unsigned i = 100;
 241
 242         if (crtc < 0 || crtc >= adev->mode_info.num_crtc)
 243                 return;
 244
 245         if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK))
 246                 return;
 247
 248         /* depending on when we hit vblank, we may be close to active; if so,
 249          * wait for another frame.
 250          */
 251         while (dce_v11_0_is_in_vblank(adev, crtc)) {
 252                 if (i++ == 100) {
 253                         i = 0;
 254                         if (!dce_v11_0_is_counter_moving(adev, crtc))
 255                                 break;
 256                 }
 257         }
 258
 259         while (!dce_v11_0_is_in_vblank(adev, crtc)) {
 260                 if (i++ == 100) {
 261                         i = 0;
 262                         if (!dce_v11_0_is_counter_moving(adev, crtc))
 263                                 break;
 264                 }
 265         }
 266 }
 267
 268 static u32 dce_v11_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
 269 {
 270         if (crtc < 0 || crtc >= adev->mode_info.num_crtc)
 271                 return 0;
 272         else
 273                 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
 274 }
 275
 276 static void dce_v11_0_pageflip_interrupt_init(struct amdgpu_device *adev)
 277 {
 278         unsigned i;
 279
 280         /* Enable pflip interrupts */
 281         for (i = 0; i < adev->mode_info.num_crtc; i++)
 282                 amdgpu_irq_get(adev, &adev->pageflip_irq, i);
 283 }
 284
 285 static void dce_v11_0_pageflip_interrupt_fini(struct amdgpu_device *adev)
 286 {
 287         unsigned i;
 288
 289         /* Disable pflip interrupts */
 290         for (i = 0; i < adev->mode_info.num_crtc; i++)
 291                 amdgpu_irq_put(adev, &adev->pageflip_irq, i);
 292 }
 293
 294 /**
 295  * dce_v11_0_page_flip - pageflip callback.
 296  *
 297  * @adev: amdgpu_device pointer
 298  * @crtc_id: crtc to cleanup pageflip on
 299  * @crtc_base: new address of the crtc (GPU MC address)
 300  *
 301  * Triggers the actual pageflip by updating the primary
 302  * surface base address.
 303  */
 304 static void dce_v11_0_page_flip(struct amdgpu_device *adev,
 305                                 int crtc_id, u64 crtc_base, bool async)
 306 {
 307         struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
 308         u32 tmp;
 309
 310         /* flip immediate for async, default is vsync */
 311         tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
 312         tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
 313                             GRPH_SURFACE_UPDATE_IMMEDIATE_EN, async ? 1 : 0);
 314         WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
 315         /* update the scanout addresses */
 316         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
 317                upper_32_bits(crtc_base));
 318         /* writing to the low address triggers the update */
 319         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
 320                lower_32_bits(crtc_base));
 321         /* post the write */
 322         RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
 323 }
 324
 325 static int dce_v11_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
 326                                         u32 *vbl, u32 *position)
 327 {
 328         if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
 329                 return -EINVAL;
 330
 331         *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
 332         *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
 333
 334         return 0;
 335 }
 336
 337 /**
 338  * dce_v11_0_hpd_sense - hpd sense callback.
 339  *
 340  * @adev: amdgpu_device pointer
 341  * @hpd: hpd (hotplug detect) pin
 342  *
 343  * Checks if a digital monitor is connected (evergreen+).
 344  * Returns true if connected, false if not connected.
 345  */
 346 static bool dce_v11_0_hpd_sense(struct amdgpu_device *adev,
 347                                enum amdgpu_hpd_id hpd)
 348 {
 349         int idx;
 350         bool connected = false;
 351
 352         switch (hpd) {
 353         case AMDGPU_HPD_1:
 354                 idx = 0;
 355                 break;
 356         case AMDGPU_HPD_2:
 357                 idx = 1;
 358                 break;
 359         case AMDGPU_HPD_3:
 360                 idx = 2;
 361                 break;
 362         case AMDGPU_HPD_4:
 363                 idx = 3;
 364                 break;
 365         case AMDGPU_HPD_5:
 366                 idx = 4;
 367                 break;
 368         case AMDGPU_HPD_6:
 369                 idx = 5;
 370                 break;
 371         default:
 372                 return connected;
 373         }
 374
 375         if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[idx]) &
 376             DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK)
 377                 connected = true;
 378
 379         return connected;
 380 }
 381
 382 /**
 383  * dce_v11_0_hpd_set_polarity - hpd set polarity callback.
 384  *
 385  * @adev: amdgpu_device pointer
 386  * @hpd: hpd (hotplug detect) pin
 387  *
 388  * Set the polarity of the hpd pin (evergreen+).
 389  */
 390 static void dce_v11_0_hpd_set_polarity(struct amdgpu_device *adev,
 391                                       enum amdgpu_hpd_id hpd)
 392 {
 393         u32 tmp;
 394         bool connected = dce_v11_0_hpd_sense(adev, hpd);
 395         int idx;
 396
 397         switch (hpd) {
 398         case AMDGPU_HPD_1:
 399                 idx = 0;
 400                 break;
 401         case AMDGPU_HPD_2:
 402                 idx = 1;
 403                 break;
 404         case AMDGPU_HPD_3:
 405                 idx = 2;
 406                 break;
 407         case AMDGPU_HPD_4:
 408                 idx = 3;
 409                 break;
 410         case AMDGPU_HPD_5:
 411                 idx = 4;
 412                 break;
 413         case AMDGPU_HPD_6:
 414                 idx = 5;
 415                 break;
 416         default:
 417                 return;
 418         }
 419
 420         tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx]);
 421         if (connected)
 422                 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0);
 423         else
 424                 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1);
 425         WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx], tmp);
 426 }
 427
 428 /**
 429  * dce_v11_0_hpd_init - hpd setup callback.
 430  *
 431  * @adev: amdgpu_device pointer
 432  *
 433  * Setup the hpd pins used by the card (evergreen+).
 434  * Enable the pin, set the polarity, and enable the hpd interrupts.
 435  */
 436 static void dce_v11_0_hpd_init(struct amdgpu_device *adev)
 437 {
 438         struct drm_device *dev = adev->ddev;
 439         struct drm_connector *connector;
 440         u32 tmp;
 441         int idx;
 442
 443         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 444                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 445
 446                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
 447                     connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
 448                         /* don't try to enable hpd on eDP or LVDS avoid breaking the
 449                          * aux dp channel on imac and help (but not completely fix)
 450                          * https://bugzilla.redhat.com/show_bug.cgi?id=726143
 451                          * also avoid interrupt storms during dpms.
 452                          */
 453                         continue;
 454                 }
 455
 456                 switch (amdgpu_connector->hpd.hpd) {
 457                 case AMDGPU_HPD_1:
 458                         idx = 0;
 459                         break;
 460                 case AMDGPU_HPD_2:
 461                         idx = 1;
 462                         break;
 463                 case AMDGPU_HPD_3:
 464                         idx = 2;
 465                         break;
 466                 case AMDGPU_HPD_4:
 467                         idx = 3;
 468                         break;
 469                 case AMDGPU_HPD_5:
 470                         idx = 4;
 471                         break;
 472                 case AMDGPU_HPD_6:
 473                         idx = 5;
 474                         break;
 475                 default:
 476                         continue;
 477                 }
 478
 479                 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]);
 480                 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1);
 481                 WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp);
 482
 483                 tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx]);
 484                 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
 485                                     DC_HPD_CONNECT_INT_DELAY,
 486                                     AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS);
 487                 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
 488                                     DC_HPD_DISCONNECT_INT_DELAY,
 489                                     AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS);
 490                 WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx], tmp);
 491
 492                 dce_v11_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
 493                 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
 494         }
 495 }
 496
 497 /**
 498  * dce_v11_0_hpd_fini - hpd tear down callback.
 499  *
 500  * @adev: amdgpu_device pointer
 501  *
 502  * Tear down the hpd pins used by the card (evergreen+).
 503  * Disable the hpd interrupts.
 504  */
 505 static void dce_v11_0_hpd_fini(struct amdgpu_device *adev)
 506 {
 507         struct drm_device *dev = adev->ddev;
 508         struct drm_connector *connector;
 509         u32 tmp;
 510         int idx;
 511
 512         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 513                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 514
 515                 switch (amdgpu_connector->hpd.hpd) {
 516                 case AMDGPU_HPD_1:
 517                         idx = 0;
 518                         break;
 519                 case AMDGPU_HPD_2:
 520                         idx = 1;
 521                         break;
 522                 case AMDGPU_HPD_3:
 523                         idx = 2;
 524                         break;
 525                 case AMDGPU_HPD_4:
 526                         idx = 3;
 527                         break;
 528                 case AMDGPU_HPD_5:
 529                         idx = 4;
 530                         break;
 531                 case AMDGPU_HPD_6:
 532                         idx = 5;
 533                         break;
 534                 default:
 535                         continue;
 536                 }
 537
 538                 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]);
 539                 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0);
 540                 WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp);
 541
 542                 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
 543         }
 544 }
 545
 546 static u32 dce_v11_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
 547 {
 548         return mmDC_GPIO_HPD_A;
 549 }
 550
 551 static bool dce_v11_0_is_display_hung(struct amdgpu_device *adev)
 552 {
 553         u32 crtc_hung = 0;
 554         u32 crtc_status[6];
 555         u32 i, j, tmp;
 556
 557         for (i = 0; i < adev->mode_info.num_crtc; i++) {
 558                 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
 559                 if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) {
 560                         crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
 561                         crtc_hung |= (1 << i);
 562                 }
 563         }
 564
 565         for (j = 0; j < 10; j++) {
 566                 for (i = 0; i < adev->mode_info.num_crtc; i++) {
 567                         if (crtc_hung & (1 << i)) {
 568                                 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
 569                                 if (tmp != crtc_status[i])
 570                                         crtc_hung &= ~(1 << i);
 571                         }
 572                 }
 573                 if (crtc_hung == 0)
 574                         return false;
 575                 udelay(100);
 576         }
 577
 578         return true;
 579 }
 580
 581 static void dce_v11_0_stop_mc_access(struct amdgpu_device *adev,
 582                                      struct amdgpu_mode_mc_save *save)
 583 {
 584         u32 crtc_enabled, tmp;
 585         int i;
 586
 587         save->vga_render_control = RREG32(mmVGA_RENDER_CONTROL);
 588         save->vga_hdp_control = RREG32(mmVGA_HDP_CONTROL);
 589
 590         /* disable VGA render */
 591         tmp = RREG32(mmVGA_RENDER_CONTROL);
 592         tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
 593         WREG32(mmVGA_RENDER_CONTROL, tmp);
 594
 595         /* blank the display controllers */
 596         for (i = 0; i < adev->mode_info.num_crtc; i++) {
 597                 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
 598                                              CRTC_CONTROL, CRTC_MASTER_EN);
 599                 if (crtc_enabled) {
 600 #if 1
 601                         save->crtc_enabled[i] = true;
 602                         tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
 603                         if (REG_GET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN) == 0) {
 604                                 /*it is correct only for RGB ; black is 0*/
 605                                 WREG32(mmCRTC_BLANK_DATA_COLOR + crtc_offsets[i], 0);
 606                                 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 1);
 607                                 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
 608                         }
 609 #else
 610                         /* XXX this is a hack to avoid strange behavior with EFI on certain systems */
 611                         WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
 612                         tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
 613                         tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
 614                         WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
 615                         WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
 616                         save->crtc_enabled[i] = false;
 617                         /* ***** */
 618 #endif
 619                 } else {
 620                         save->crtc_enabled[i] = false;
 621                 }
 622         }
 623 }
 624
 625 static void dce_v11_0_resume_mc_access(struct amdgpu_device *adev,
 626                                        struct amdgpu_mode_mc_save *save)
 627 {
 628         u32 tmp;
 629         int i;
 630
 631         /* update crtc base addresses */
 632         for (i = 0; i < adev->mode_info.num_crtc; i++) {
 633                 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
 634                        upper_32_bits(adev->mc.vram_start));
 635                 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
 636                        (u32)adev->mc.vram_start);
 637
 638                 if (save->crtc_enabled[i]) {
 639                         tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
 640                         tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 0);
 641                         WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
 642                 }
 643         }
 644
 645         WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start));
 646         WREG32(mmVGA_MEMORY_BASE_ADDRESS, lower_32_bits(adev->mc.vram_start));
 647
 648         /* Unlock vga access */
 649         WREG32(mmVGA_HDP_CONTROL, save->vga_hdp_control);
 650         mdelay(1);
 651         WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control);
 652 }
 653
 654 static void dce_v11_0_set_vga_render_state(struct amdgpu_device *adev,
 655                                            bool render)
 656 {
 657         u32 tmp;
 658
 659         /* Lockout access through VGA aperture*/
 660         tmp = RREG32(mmVGA_HDP_CONTROL);
 661         if (render)
 662                 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);
 663         else
 664                 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
 665         WREG32(mmVGA_HDP_CONTROL, tmp);
 666
 667         /* disable VGA render */
 668         tmp = RREG32(mmVGA_RENDER_CONTROL);
 669         if (render)
 670                 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);
 671         else
 672                 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
 673         WREG32(mmVGA_RENDER_CONTROL, tmp);
 674 }
 675
 676 static void dce_v11_0_program_fmt(struct drm_encoder *encoder)
 677 {
 678         struct drm_device *dev = encoder->dev;
 679         struct amdgpu_device *adev = dev->dev_private;
 680         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 681         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
 682         struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
 683         int bpc = 0;
 684         u32 tmp = 0;
 685         enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
 686
 687         if (connector) {
 688                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 689                 bpc = amdgpu_connector_get_monitor_bpc(connector);
 690                 dither = amdgpu_connector->dither;
 691         }
 692
 693         /* LVDS/eDP FMT is set up by atom */
 694         if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
 695                 return;
 696
 697         /* not needed for analog */
 698         if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
 699             (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
 700                 return;
 701
 702         if (bpc == 0)
 703                 return;
 704
 705         switch (bpc) {
 706         case 6:
 707                 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
 708                         /* XXX sort out optimal dither settings */
 709                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
 710                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
 711                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
 712                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0);
 713                 } else {
 714                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
 715                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0);
 716                 }
 717                 break;
 718         case 8:
 719                 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
 720                         /* XXX sort out optimal dither settings */
 721                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
 722                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
 723                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
 724                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
 725                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1);
 726                 } else {
 727                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
 728                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1);
 729                 }
 730                 break;
 731         case 10:
 732                 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
 733                         /* XXX sort out optimal dither settings */
 734                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
 735                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
 736                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
 737                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
 738                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2);
 739                 } else {
 740                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
 741                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2);
 742                 }
 743                 break;
 744         default:
 745                 /* not needed */
 746                 break;
 747         }
 748
 749         WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
 750 }
 751
 752
 753 /* display watermark setup */
 754 /**
 755  * dce_v11_0_line_buffer_adjust - Set up the line buffer
 756  *
 757  * @adev: amdgpu_device pointer
 758  * @amdgpu_crtc: the selected display controller
 759  * @mode: the current display mode on the selected display
 760  * controller
 761  *
 762  * Setup up the line buffer allocation for
 763  * the selected display controller (CIK).
 764  * Returns the line buffer size in pixels.
 765  */
 766 static u32 dce_v11_0_line_buffer_adjust(struct amdgpu_device *adev,
 767                                        struct amdgpu_crtc *amdgpu_crtc,
 768                                        struct drm_display_mode *mode)
 769 {
 770         u32 tmp, buffer_alloc, i, mem_cfg;
 771         u32 pipe_offset = amdgpu_crtc->crtc_id;
 772         /*
 773          * Line Buffer Setup
 774          * There are 6 line buffers, one for each display controllers.
 775          * There are 3 partitions per LB. Select the number of partitions
 776          * to enable based on the display width.  For display widths larger
 777          * than 4096, you need use to use 2 display controllers and combine
 778          * them using the stereo blender.
 779          */
 780         if (amdgpu_crtc->base.enabled && mode) {
 781                 if (mode->crtc_hdisplay < 1920) {
 782                         mem_cfg = 1;
 783                         buffer_alloc = 2;
 784                 } else if (mode->crtc_hdisplay < 2560) {
 785                         mem_cfg = 2;
 786                         buffer_alloc = 2;
 787                 } else if (mode->crtc_hdisplay < 4096) {
 788                         mem_cfg = 0;
 789                         buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
 790                 } else {
 791                         DRM_DEBUG_KMS("Mode too big for LB!\n");
 792                         mem_cfg = 0;
 793                         buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
 794                 }
 795         } else {
 796                 mem_cfg = 1;
 797                 buffer_alloc = 0;
 798         }
 799
 800         tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset);
 801         tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg);
 802         WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp);
 803
 804         tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
 805         tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc);
 806         WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp);
 807
 808         for (i = 0; i < adev->usec_timeout; i++) {
 809                 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
 810                 if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED))
 811                         break;
 812                 udelay(1);
 813         }
 814
 815         if (amdgpu_crtc->base.enabled && mode) {
 816                 switch (mem_cfg) {
 817                 case 0:
 818                 default:
 819                         return 4096 * 2;
 820                 case 1:
 821                         return 1920 * 2;
 822                 case 2:
 823                         return 2560 * 2;
 824                 }
 825         }
 826
 827         /* controller not enabled, so no lb used */
 828         return 0;
 829 }
 830
 831 /**
 832  * cik_get_number_of_dram_channels - get the number of dram channels
 833  *
 834  * @adev: amdgpu_device pointer
 835  *
 836  * Look up the number of video ram channels (CIK).
 837  * Used for display watermark bandwidth calculations
 838  * Returns the number of dram channels
 839  */
 840 static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev)
 841 {
 842         u32 tmp = RREG32(mmMC_SHARED_CHMAP);
 843
 844         switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
 845         case 0:
 846         default:
 847                 return 1;
 848         case 1:
 849                 return 2;
 850         case 2:
 851                 return 4;
 852         case 3:
 853                 return 8;
 854         case 4:
 855                 return 3;
 856         case 5:
 857                 return 6;
 858         case 6:
 859                 return 10;
 860         case 7:
 861                 return 12;
 862         case 8:
 863                 return 16;
 864         }
 865 }
 866
 867 struct dce10_wm_params {
 868         u32 dram_channels; /* number of dram channels */
 869         u32 yclk;          /* bandwidth per dram data pin in kHz */
 870         u32 sclk;          /* engine clock in kHz */
 871         u32 disp_clk;      /* display clock in kHz */
 872         u32 src_width;     /* viewport width */
 873         u32 active_time;   /* active display time in ns */
 874         u32 blank_time;    /* blank time in ns */
 875         bool interlaced;    /* mode is interlaced */
 876         fixed20_12 vsc;    /* vertical scale ratio */
 877         u32 num_heads;     /* number of active crtcs */
 878         u32 bytes_per_pixel; /* bytes per pixel display + overlay */
 879         u32 lb_size;       /* line buffer allocated to pipe */
 880         u32 vtaps;         /* vertical scaler taps */
 881 };
 882
 883 /**
 884  * dce_v11_0_dram_bandwidth - get the dram bandwidth
 885  *
 886  * @wm: watermark calculation data
 887  *
 888  * Calculate the raw dram bandwidth (CIK).
 889  * Used for display watermark bandwidth calculations
 890  * Returns the dram bandwidth in MBytes/s
 891  */
 892 static u32 dce_v11_0_dram_bandwidth(struct dce10_wm_params *wm)
 893 {
 894         /* Calculate raw DRAM Bandwidth */
 895         fixed20_12 dram_efficiency; /* 0.7 */
 896         fixed20_12 yclk, dram_channels, bandwidth;
 897         fixed20_12 a;
 898
 899         a.full = dfixed_const(1000);
 900         yclk.full = dfixed_const(wm->yclk);
 901         yclk.full = dfixed_div(yclk, a);
 902         dram_channels.full = dfixed_const(wm->dram_channels * 4);
 903         a.full = dfixed_const(10);
 904         dram_efficiency.full = dfixed_const(7);
 905         dram_efficiency.full = dfixed_div(dram_efficiency, a);
 906         bandwidth.full = dfixed_mul(dram_channels, yclk);
 907         bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
 908
 909         return dfixed_trunc(bandwidth);
 910 }
 911
 912 /**
 913  * dce_v11_0_dram_bandwidth_for_display - get the dram bandwidth for display
 914  *
 915  * @wm: watermark calculation data
 916  *
 917  * Calculate the dram bandwidth used for display (CIK).
 918  * Used for display watermark bandwidth calculations
 919  * Returns the dram bandwidth for display in MBytes/s
 920  */
 921 static u32 dce_v11_0_dram_bandwidth_for_display(struct dce10_wm_params *wm)
 922 {
 923         /* Calculate DRAM Bandwidth and the part allocated to display. */
 924         fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
 925         fixed20_12 yclk, dram_channels, bandwidth;
 926         fixed20_12 a;
 927
 928         a.full = dfixed_const(1000);
 929         yclk.full = dfixed_const(wm->yclk);
 930         yclk.full = dfixed_div(yclk, a);
 931         dram_channels.full = dfixed_const(wm->dram_channels * 4);
 932         a.full = dfixed_const(10);
 933         disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
 934         disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
 935         bandwidth.full = dfixed_mul(dram_channels, yclk);
 936         bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
 937
 938         return dfixed_trunc(bandwidth);
 939 }
 940
 941 /**
 942  * dce_v11_0_data_return_bandwidth - get the data return bandwidth
 943  *
 944  * @wm: watermark calculation data
 945  *
 946  * Calculate the data return bandwidth used for display (CIK).
 947  * Used for display watermark bandwidth calculations
 948  * Returns the data return bandwidth in MBytes/s
 949  */
 950 static u32 dce_v11_0_data_return_bandwidth(struct dce10_wm_params *wm)
 951 {
 952         /* Calculate the display Data return Bandwidth */
 953         fixed20_12 return_efficiency; /* 0.8 */
 954         fixed20_12 sclk, bandwidth;
 955         fixed20_12 a;
 956
 957         a.full = dfixed_const(1000);
 958         sclk.full = dfixed_const(wm->sclk);
 959         sclk.full = dfixed_div(sclk, a);
 960         a.full = dfixed_const(10);
 961         return_efficiency.full = dfixed_const(8);
 962         return_efficiency.full = dfixed_div(return_efficiency, a);
 963         a.full = dfixed_const(32);
 964         bandwidth.full = dfixed_mul(a, sclk);
 965         bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
 966
 967         return dfixed_trunc(bandwidth);
 968 }
 969
 970 /**
 971  * dce_v11_0_dmif_request_bandwidth - get the dmif bandwidth
 972  *
 973  * @wm: watermark calculation data
 974  *
 975  * Calculate the dmif bandwidth used for display (CIK).
 976  * Used for display watermark bandwidth calculations
 977  * Returns the dmif bandwidth in MBytes/s
 978  */
 979 static u32 dce_v11_0_dmif_request_bandwidth(struct dce10_wm_params *wm)
 980 {
 981         /* Calculate the DMIF Request Bandwidth */
 982         fixed20_12 disp_clk_request_efficiency; /* 0.8 */
 983         fixed20_12 disp_clk, bandwidth;
 984         fixed20_12 a, b;
 985
 986         a.full = dfixed_const(1000);
 987         disp_clk.full = dfixed_const(wm->disp_clk);
 988         disp_clk.full = dfixed_div(disp_clk, a);
 989         a.full = dfixed_const(32);
 990         b.full = dfixed_mul(a, disp_clk);
 991
 992         a.full = dfixed_const(10);
 993         disp_clk_request_efficiency.full = dfixed_const(8);
 994         disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
 995
 996         bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
 997
 998         return dfixed_trunc(bandwidth);
 999 }
1000
1001 /**
1002  * dce_v11_0_available_bandwidth - get the min available bandwidth
1003  *
1004  * @wm: watermark calculation data
1005  *
1006  * Calculate the min available bandwidth used for display (CIK).
1007  * Used for display watermark bandwidth calculations
1008  * Returns the min available bandwidth in MBytes/s
1009  */
1010 static u32 dce_v11_0_available_bandwidth(struct dce10_wm_params *wm)
1011 {
1012         /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
1013         u32 dram_bandwidth = dce_v11_0_dram_bandwidth(wm);
1014         u32 data_return_bandwidth = dce_v11_0_data_return_bandwidth(wm);
1015         u32 dmif_req_bandwidth = dce_v11_0_dmif_request_bandwidth(wm);
1016
1017         return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
1018 }
1019
1020 /**
1021  * dce_v11_0_average_bandwidth - get the average available bandwidth
1022  *
1023  * @wm: watermark calculation data
1024  *
1025  * Calculate the average available bandwidth used for display (CIK).
1026  * Used for display watermark bandwidth calculations
1027  * Returns the average available bandwidth in MBytes/s
1028  */
1029 static u32 dce_v11_0_average_bandwidth(struct dce10_wm_params *wm)
1030 {
1031         /* Calculate the display mode Average Bandwidth
1032          * DisplayMode should contain the source and destination dimensions,
1033          * timing, etc.
1034          */
1035         fixed20_12 bpp;
1036         fixed20_12 line_time;
1037         fixed20_12 src_width;
1038         fixed20_12 bandwidth;
1039         fixed20_12 a;
1040
1041         a.full = dfixed_const(1000);
1042         line_time.full = dfixed_const(wm->active_time + wm->blank_time);
1043         line_time.full = dfixed_div(line_time, a);
1044         bpp.full = dfixed_const(wm->bytes_per_pixel);
1045         src_width.full = dfixed_const(wm->src_width);
1046         bandwidth.full = dfixed_mul(src_width, bpp);
1047         bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
1048         bandwidth.full = dfixed_div(bandwidth, line_time);
1049
1050         return dfixed_trunc(bandwidth);
1051 }
1052
1053 /**
1054  * dce_v11_0_latency_watermark - get the latency watermark
1055  *
1056  * @wm: watermark calculation data
1057  *
1058  * Calculate the latency watermark (CIK).
1059  * Used for display watermark bandwidth calculations
1060  * Returns the latency watermark in ns
1061  */
1062 static u32 dce_v11_0_latency_watermark(struct dce10_wm_params *wm)
1063 {
1064         /* First calculate the latency in ns */
1065         u32 mc_latency = 2000; /* 2000 ns. */
1066         u32 available_bandwidth = dce_v11_0_available_bandwidth(wm);
1067         u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
1068         u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
1069         u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
1070         u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
1071                 (wm->num_heads * cursor_line_pair_return_time);
1072         u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
1073         u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
1074         u32 tmp, dmif_size = 12288;
1075         fixed20_12 a, b, c;
1076
1077         if (wm->num_heads == 0)
1078                 return 0;
1079
1080         a.full = dfixed_const(2);
1081         b.full = dfixed_const(1);
1082         if ((wm->vsc.full > a.full) ||
1083             ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
1084             (wm->vtaps >= 5) ||
1085             ((wm->vsc.full >= a.full) && wm->interlaced))
1086                 max_src_lines_per_dst_line = 4;
1087         else
1088                 max_src_lines_per_dst_line = 2;
1089
1090         a.full = dfixed_const(available_bandwidth);
1091         b.full = dfixed_const(wm->num_heads);
1092         a.full = dfixed_div(a, b);
1093
1094         b.full = dfixed_const(mc_latency + 512);
1095         c.full = dfixed_const(wm->disp_clk);
1096         b.full = dfixed_div(b, c);
1097
1098         c.full = dfixed_const(dmif_size);
1099         b.full = dfixed_div(c, b);
1100
1101         tmp = min(dfixed_trunc(a), dfixed_trunc(b));
1102
1103         b.full = dfixed_const(1000);
1104         c.full = dfixed_const(wm->disp_clk);
1105         b.full = dfixed_div(c, b);
1106         c.full = dfixed_const(wm->bytes_per_pixel);
1107         b.full = dfixed_mul(b, c);
1108
1109         lb_fill_bw = min(tmp, dfixed_trunc(b));
1110
1111         a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
1112         b.full = dfixed_const(1000);
1113         c.full = dfixed_const(lb_fill_bw);
1114         b.full = dfixed_div(c, b);
1115         a.full = dfixed_div(a, b);
1116         line_fill_time = dfixed_trunc(a);
1117
1118         if (line_fill_time < wm->active_time)
1119                 return latency;
1120         else
1121                 return latency + (line_fill_time - wm->active_time);
1122
1123 }
1124
1125 /**
1126  * dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display - check
1127  * average and available dram bandwidth
1128  *
1129  * @wm: watermark calculation data
1130  *
1131  * Check if the display average bandwidth fits in the display
1132  * dram bandwidth (CIK).
1133  * Used for display watermark bandwidth calculations
1134  * Returns true if the display fits, false if not.
1135  */
1136 static bool dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params *wm)
1137 {
1138         if (dce_v11_0_average_bandwidth(wm) <=
1139             (dce_v11_0_dram_bandwidth_for_display(wm) / wm->num_heads))
1140                 return true;
1141         else
1142                 return false;
1143 }
1144
1145 /**
1146  * dce_v11_0_average_bandwidth_vs_available_bandwidth - check
1147  * average and available bandwidth
1148  *
1149  * @wm: watermark calculation data
1150  *
1151  * Check if the display average bandwidth fits in the display
1152  * available bandwidth (CIK).
1153  * Used for display watermark bandwidth calculations
1154  * Returns true if the display fits, false if not.
1155  */
1156 static bool dce_v11_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params *wm)
1157 {
1158         if (dce_v11_0_average_bandwidth(wm) <=
1159             (dce_v11_0_available_bandwidth(wm) / wm->num_heads))
1160                 return true;
1161         else
1162                 return false;
1163 }
1164
1165 /**
1166  * dce_v11_0_check_latency_hiding - check latency hiding
1167  *
1168  * @wm: watermark calculation data
1169  *
1170  * Check latency hiding (CIK).
1171  * Used for display watermark bandwidth calculations
1172  * Returns true if the display fits, false if not.
1173  */
1174 static bool dce_v11_0_check_latency_hiding(struct dce10_wm_params *wm)
1175 {
1176         u32 lb_partitions = wm->lb_size / wm->src_width;
1177         u32 line_time = wm->active_time + wm->blank_time;
1178         u32 latency_tolerant_lines;
1179         u32 latency_hiding;
1180         fixed20_12 a;
1181
1182         a.full = dfixed_const(1);
1183         if (wm->vsc.full > a.full)
1184                 latency_tolerant_lines = 1;
1185         else {
1186                 if (lb_partitions <= (wm->vtaps + 1))
1187                         latency_tolerant_lines = 1;
1188                 else
1189                         latency_tolerant_lines = 2;
1190         }
1191
1192         latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
1193
1194         if (dce_v11_0_latency_watermark(wm) <= latency_hiding)
1195                 return true;
1196         else
1197                 return false;
1198 }
1199
1200 /**
1201  * dce_v11_0_program_watermarks - program display watermarks
1202  *
1203  * @adev: amdgpu_device pointer
1204  * @amdgpu_crtc: the selected display controller
1205  * @lb_size: line buffer size
1206  * @num_heads: number of display controllers in use
1207  *
1208  * Calculate and program the display watermarks for the
1209  * selected display controller (CIK).
1210  */
1211 static void dce_v11_0_program_watermarks(struct amdgpu_device *adev,
1212                                         struct amdgpu_crtc *amdgpu_crtc,
1213                                         u32 lb_size, u32 num_heads)
1214 {
1215         struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
1216         struct dce10_wm_params wm_low, wm_high;
1217         u32 pixel_period;
1218         u32 line_time = 0;
1219         u32 latency_watermark_a = 0, latency_watermark_b = 0;
1220         u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
1221
1222         if (amdgpu_crtc->base.enabled && num_heads && mode) {
1223                 pixel_period = 1000000 / (u32)mode->clock;
1224                 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
1225
1226                 /* watermark for high clocks */
1227                 if (adev->pm.dpm_enabled) {
1228                         wm_high.yclk =
1229                                 amdgpu_dpm_get_mclk(adev, false) * 10;
1230                         wm_high.sclk =
1231                                 amdgpu_dpm_get_sclk(adev, false) * 10;
1232                 } else {
1233                         wm_high.yclk = adev->pm.current_mclk * 10;
1234                         wm_high.sclk = adev->pm.current_sclk * 10;
1235                 }
1236
1237                 wm_high.disp_clk = mode->clock;
1238                 wm_high.src_width = mode->crtc_hdisplay;
1239                 wm_high.active_time = mode->crtc_hdisplay * pixel_period;
1240                 wm_high.blank_time = line_time - wm_high.active_time;
1241                 wm_high.interlaced = false;
1242                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1243                         wm_high.interlaced = true;
1244                 wm_high.vsc = amdgpu_crtc->vsc;
1245                 wm_high.vtaps = 1;
1246                 if (amdgpu_crtc->rmx_type != RMX_OFF)
1247                         wm_high.vtaps = 2;
1248                 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
1249                 wm_high.lb_size = lb_size;
1250                 wm_high.dram_channels = cik_get_number_of_dram_channels(adev);
1251                 wm_high.num_heads = num_heads;
1252
1253                 /* set for high clocks */
1254                 latency_watermark_a = min(dce_v11_0_latency_watermark(&wm_high), (u32)65535);
1255
1256                 /* possibly force display priority to high */
1257                 /* should really do this at mode validation time... */
1258                 if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
1259                     !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_high) ||
1260                     !dce_v11_0_check_latency_hiding(&wm_high) ||
1261                     (adev->mode_info.disp_priority == 2)) {
1262                         DRM_DEBUG_KMS("force priority to high\n");
1263                 }
1264
1265                 /* watermark for low clocks */
1266                 if (adev->pm.dpm_enabled) {
1267                         wm_low.yclk =
1268                                 amdgpu_dpm_get_mclk(adev, true) * 10;
1269                         wm_low.sclk =
1270                                 amdgpu_dpm_get_sclk(adev, true) * 10;
1271                 } else {
1272                         wm_low.yclk = adev->pm.current_mclk * 10;
1273                         wm_low.sclk = adev->pm.current_sclk * 10;
1274                 }
1275
1276                 wm_low.disp_clk = mode->clock;
1277                 wm_low.src_width = mode->crtc_hdisplay;
1278                 wm_low.active_time = mode->crtc_hdisplay * pixel_period;
1279                 wm_low.blank_time = line_time - wm_low.active_time;
1280                 wm_low.interlaced = false;
1281                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1282                         wm_low.interlaced = true;
1283                 wm_low.vsc = amdgpu_crtc->vsc;
1284                 wm_low.vtaps = 1;
1285                 if (amdgpu_crtc->rmx_type != RMX_OFF)
1286                         wm_low.vtaps = 2;
1287                 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
1288                 wm_low.lb_size = lb_size;
1289                 wm_low.dram_channels = cik_get_number_of_dram_channels(adev);
1290                 wm_low.num_heads = num_heads;
1291
1292                 /* set for low clocks */
1293                 latency_watermark_b = min(dce_v11_0_latency_watermark(&wm_low), (u32)65535);
1294
1295                 /* possibly force display priority to high */
1296                 /* should really do this at mode validation time... */
1297                 if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
1298                     !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_low) ||
1299                     !dce_v11_0_check_latency_hiding(&wm_low) ||
1300                     (adev->mode_info.disp_priority == 2)) {
1301                         DRM_DEBUG_KMS("force priority to high\n");
1302                 }
1303                 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);
1304         }
1305
1306         /* select wm A */
1307         wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1308         tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1);
1309         WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1310         tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1311         tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a);
1312         tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1313         WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1314         /* select wm B */
1315         tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2);
1316         WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1317         tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1318         tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b);
1319         tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1320         WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1321         /* restore original selection */
1322         WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);
1323
1324         /* save values for DPM */
1325         amdgpu_crtc->line_time = line_time;
1326         amdgpu_crtc->wm_high = latency_watermark_a;
1327         amdgpu_crtc->wm_low = latency_watermark_b;
1328         /* Save number of lines the linebuffer leads before the scanout */
1329         amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;
1330 }
1331
1332 /**
1333  * dce_v11_0_bandwidth_update - program display watermarks
1334  *
1335  * @adev: amdgpu_device pointer
1336  *
1337  * Calculate and program the display watermarks and line
1338  * buffer allocation (CIK).
1339  */
1340 static void dce_v11_0_bandwidth_update(struct amdgpu_device *adev)
1341 {
1342         struct drm_display_mode *mode = NULL;
1343         u32 num_heads = 0, lb_size;
1344         int i;
1345
1346         amdgpu_update_display_priority(adev);
1347
1348         for (i = 0; i < adev->mode_info.num_crtc; i++) {
1349                 if (adev->mode_info.crtcs[i]->base.enabled)
1350                         num_heads++;
1351         }
1352         for (i = 0; i < adev->mode_info.num_crtc; i++) {
1353                 mode = &adev->mode_info.crtcs[i]->base.mode;
1354                 lb_size = dce_v11_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode);
1355                 dce_v11_0_program_watermarks(adev, adev->mode_info.crtcs[i],
1356                                             lb_size, num_heads);
1357         }
1358 }
1359
1360 static void dce_v11_0_audio_get_connected_pins(struct amdgpu_device *adev)
1361 {
1362         int i;
1363         u32 offset, tmp;
1364
1365         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1366                 offset = adev->mode_info.audio.pin[i].offset;
1367                 tmp = RREG32_AUDIO_ENDPT(offset,
1368                                          ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
1369                 if (((tmp &
1370                 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >>
1371                 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1)
1372                         adev->mode_info.audio.pin[i].connected = false;
1373                 else
1374                         adev->mode_info.audio.pin[i].connected = true;
1375         }
1376 }
1377
1378 static struct amdgpu_audio_pin *dce_v11_0_audio_get_pin(struct amdgpu_device *adev)
1379 {
1380         int i;
1381
1382         dce_v11_0_audio_get_connected_pins(adev);
1383
1384         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1385                 if (adev->mode_info.audio.pin[i].connected)
1386                         return &adev->mode_info.audio.pin[i];
1387         }
1388         DRM_ERROR("No connected audio pins found!\n");
1389         return NULL;
1390 }
1391
1392 static void dce_v11_0_afmt_audio_select_pin(struct drm_encoder *encoder)
1393 {
1394         struct amdgpu_device *adev = encoder->dev->dev_private;
1395         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1396         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1397         u32 tmp;
1398
1399         if (!dig || !dig->afmt || !dig->afmt->pin)
1400                 return;
1401
1402         tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset);
1403         tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id);
1404         WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp);
1405 }
1406
1407 static void dce_v11_0_audio_write_latency_fields(struct drm_encoder *encoder,
1408                                                 struct drm_display_mode *mode)
1409 {
1410         struct amdgpu_device *adev = encoder->dev->dev_private;
1411         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1412         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1413         struct drm_connector *connector;
1414         struct amdgpu_connector *amdgpu_connector = NULL;
1415         u32 tmp;
1416         int interlace = 0;
1417
1418         if (!dig || !dig->afmt || !dig->afmt->pin)
1419                 return;
1420
1421         list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1422                 if (connector->encoder == encoder) {
1423                         amdgpu_connector = to_amdgpu_connector(connector);
1424                         break;
1425                 }
1426         }
1427
1428         if (!amdgpu_connector) {
1429                 DRM_ERROR("Couldn't find encoder's connector\n");
1430                 return;
1431         }
1432
1433         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1434                 interlace = 1;
1435         if (connector->latency_present[interlace]) {
1436                 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1437                                     VIDEO_LIPSYNC, connector->video_latency[interlace]);
1438                 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1439                                     AUDIO_LIPSYNC, connector->audio_latency[interlace]);
1440         } else {
1441                 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1442                                     VIDEO_LIPSYNC, 0);
1443                 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1444                                     AUDIO_LIPSYNC, 0);
1445         }
1446         WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1447                            ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
1448 }
1449
1450 static void dce_v11_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
1451 {
1452         struct amdgpu_device *adev = encoder->dev->dev_private;
1453         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1454         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1455         struct drm_connector *connector;
1456         struct amdgpu_connector *amdgpu_connector = NULL;
1457         u32 tmp;
1458         u8 *sadb = NULL;
1459         int sad_count;
1460
1461         if (!dig || !dig->afmt || !dig->afmt->pin)
1462                 return;
1463
1464         list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1465                 if (connector->encoder == encoder) {
1466                         amdgpu_connector = to_amdgpu_connector(connector);
1467                         break;
1468                 }
1469         }
1470
1471         if (!amdgpu_connector) {
1472                 DRM_ERROR("Couldn't find encoder's connector\n");
1473                 return;
1474         }
1475
1476         sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb);
1477         if (sad_count < 0) {
1478                 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
1479                 sad_count = 0;
1480         }
1481
1482         /* program the speaker allocation */
1483         tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1484                                  ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
1485         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1486                             DP_CONNECTION, 0);
1487         /* set HDMI mode */
1488         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1489                             HDMI_CONNECTION, 1);
1490         if (sad_count)
1491                 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1492                                     SPEAKER_ALLOCATION, sadb[0]);
1493         else
1494                 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1495                                     SPEAKER_ALLOCATION, 5); /* stereo */
1496         WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1497                            ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
1498
1499         kfree(sadb);
1500 }
1501
1502 static void dce_v11_0_audio_write_sad_regs(struct drm_encoder *encoder)
1503 {
1504         struct amdgpu_device *adev = encoder->dev->dev_private;
1505         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1506         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1507         struct drm_connector *connector;
1508         struct amdgpu_connector *amdgpu_connector = NULL;
1509         struct cea_sad *sads;
1510         int i, sad_count;
1511
1512         static const u16 eld_reg_to_type[][2] = {
1513                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
1514                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
1515                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
1516                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
1517                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
1518                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
1519                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
1520                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
1521                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
1522                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
1523                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
1524                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
1525         };
1526
1527         if (!dig || !dig->afmt || !dig->afmt->pin)
1528                 return;
1529
1530         list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1531                 if (connector->encoder == encoder) {
1532                         amdgpu_connector = to_amdgpu_connector(connector);
1533                         break;
1534                 }
1535         }
1536
1537         if (!amdgpu_connector) {
1538                 DRM_ERROR("Couldn't find encoder's connector\n");
1539                 return;
1540         }
1541
1542         sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads);
1543         if (sad_count <= 0) {
1544                 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
1545                 return;
1546         }
1547         BUG_ON(!sads);
1548
1549         for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
1550                 u32 tmp = 0;
1551                 u8 stereo_freqs = 0;
1552                 int max_channels = -1;
1553                 int j;
1554
1555                 for (j = 0; j < sad_count; j++) {
1556                         struct cea_sad *sad = &sads[j];
1557
1558                         if (sad->format == eld_reg_to_type[i][1]) {
1559                                 if (sad->channels > max_channels) {
1560                                         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1561                                                             MAX_CHANNELS, sad->channels);
1562                                         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1563                                                             DESCRIPTOR_BYTE_2, sad->byte2);
1564                                         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1565                                                             SUPPORTED_FREQUENCIES, sad->freq);
1566                                         max_channels = sad->channels;
1567                                 }
1568
1569                                 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
1570                                         stereo_freqs |= sad->freq;
1571                                 else
1572                                         break;
1573                         }
1574                 }
1575
1576                 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1577                                     SUPPORTED_FREQUENCIES_STEREO, stereo_freqs);
1578                 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp);
1579         }
1580
1581         kfree(sads);
1582 }
1583
1584 static void dce_v11_0_audio_enable(struct amdgpu_device *adev,
1585                                   struct amdgpu_audio_pin *pin,
1586                                   bool enable)
1587 {
1588         if (!pin)
1589                 return;
1590
1591         WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
1592                            enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);
1593 }
1594
1595 static const u32 pin_offsets[] =
1596 {
1597         AUD0_REGISTER_OFFSET,
1598         AUD1_REGISTER_OFFSET,
1599         AUD2_REGISTER_OFFSET,
1600         AUD3_REGISTER_OFFSET,
1601         AUD4_REGISTER_OFFSET,
1602         AUD5_REGISTER_OFFSET,
1603         AUD6_REGISTER_OFFSET,
1604         AUD7_REGISTER_OFFSET,
1605 };
1606
1607 static int dce_v11_0_audio_init(struct amdgpu_device *adev)
1608 {
1609         int i;
1610
1611         if (!amdgpu_audio)
1612                 return 0;
1613
1614         adev->mode_info.audio.enabled = true;
1615
1616         switch (adev->asic_type) {
1617         case CHIP_CARRIZO:
1618         case CHIP_STONEY:
1619                 adev->mode_info.audio.num_pins = 7;
1620                 break;
1621         case CHIP_POLARIS10:
1622                 adev->mode_info.audio.num_pins = 8;
1623                 break;
1624         case CHIP_POLARIS11:
1625                 adev->mode_info.audio.num_pins = 6;
1626                 break;
1627         default:
1628                 return -EINVAL;
1629         }
1630
1631         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1632                 adev->mode_info.audio.pin[i].channels = -1;
1633                 adev->mode_info.audio.pin[i].rate = -1;
1634                 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1635                 adev->mode_info.audio.pin[i].status_bits = 0;
1636                 adev->mode_info.audio.pin[i].category_code = 0;
1637                 adev->mode_info.audio.pin[i].connected = false;
1638                 adev->mode_info.audio.pin[i].offset = pin_offsets[i];
1639                 adev->mode_info.audio.pin[i].id = i;
1640                 /* disable audio.  it will be set up later */
1641                 /* XXX remove once we switch to ip funcs */
1642                 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1643         }
1644
1645         return 0;
1646 }
1647
1648 static void dce_v11_0_audio_fini(struct amdgpu_device *adev)
1649 {
1650         int i;
1651
1652         if (!amdgpu_audio)
1653                 return;
1654
1655         if (!adev->mode_info.audio.enabled)
1656                 return;
1657
1658         for (i = 0; i < adev->mode_info.audio.num_pins; i++)
1659                 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1660
1661         adev->mode_info.audio.enabled = false;
1662 }
1663
1664 /*
1665  * update the N and CTS parameters for a given pixel clock rate
1666  */
1667 static void dce_v11_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)
1668 {
1669         struct drm_device *dev = encoder->dev;
1670         struct amdgpu_device *adev = dev->dev_private;
1671         struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
1672         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1673         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1674         u32 tmp;
1675
1676         tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset);
1677         tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);
1678         WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp);
1679         tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset);
1680         tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);
1681         WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp);
1682
1683         tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset);
1684         tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz);
1685         WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp);
1686         tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset);
1687         tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);
1688         WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp);
1689
1690         tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset);
1691         tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);
1692         WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp);
1693         tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset);
1694         tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);
1695         WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp);
1696
1697 }
1698
1699 /*
1700  * build a HDMI Video Info Frame
1701  */
1702 static void dce_v11_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,
1703                                                void *buffer, size_t size)
1704 {
1705         struct drm_device *dev = encoder->dev;
1706         struct amdgpu_device *adev = dev->dev_private;
1707         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1708         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1709         uint8_t *frame = buffer + 3;
1710         uint8_t *header = buffer;
1711
1712         WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset,
1713                 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
1714         WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset,
1715                 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
1716         WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset,
1717                 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
1718         WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset,
1719                 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
1720 }
1721
1722 static void dce_v11_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
1723 {
1724         struct drm_device *dev = encoder->dev;
1725         struct amdgpu_device *adev = dev->dev_private;
1726         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1727         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1728         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1729         u32 dto_phase = 24 * 1000;
1730         u32 dto_modulo = clock;
1731         u32 tmp;
1732
1733         if (!dig || !dig->afmt)
1734                 return;
1735
1736         /* XXX two dtos; generally use dto0 for hdmi */
1737         /* Express [24MHz / target pixel clock] as an exact rational
1738          * number (coefficient of two integer numbers.  DCCG_AUDIO_DTOx_PHASE
1739          * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
1740          */
1741         tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE);
1742         tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL,
1743                             amdgpu_crtc->crtc_id);
1744         WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp);
1745         WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase);
1746         WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo);
1747 }
1748
1749 /*
1750  * update the info frames with the data from the current display mode
1751  */
1752 static void dce_v11_0_afmt_setmode(struct drm_encoder *encoder,
1753                                   struct drm_display_mode *mode)
1754 {
1755         struct drm_device *dev = encoder->dev;
1756         struct amdgpu_device *adev = dev->dev_private;
1757         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1758         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1759         struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
1760         u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
1761         struct hdmi_avi_infoframe frame;
1762         ssize_t err;
1763         u32 tmp;
1764         int bpc = 8;
1765
1766         if (!dig || !dig->afmt)
1767                 return;
1768
1769         /* Silent, r600_hdmi_enable will raise WARN for us */
1770         if (!dig->afmt->enabled)
1771                 return;
1772
1773         /* hdmi deep color mode general control packets setup, if bpc > 8 */
1774         if (encoder->crtc) {
1775                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1776                 bpc = amdgpu_crtc->bpc;
1777         }
1778
1779         /* disable audio prior to setting up hw */
1780         dig->afmt->pin = dce_v11_0_audio_get_pin(adev);
1781         dce_v11_0_audio_enable(adev, dig->afmt->pin, false);
1782
1783         dce_v11_0_audio_set_dto(encoder, mode->clock);
1784
1785         tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1786         tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1);
1787         WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */
1788
1789         WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000);
1790
1791         tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset);
1792         switch (bpc) {
1793         case 0:
1794         case 6:
1795         case 8:
1796         case 16:
1797         default:
1798                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0);
1799                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
1800                 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
1801                           connector->name, bpc);
1802                 break;
1803         case 10:
1804                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1805                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1);
1806                 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
1807                           connector->name);
1808                 break;
1809         case 12:
1810                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1811                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2);
1812                 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
1813                           connector->name);
1814                 break;
1815         }
1816         WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp);
1817
1818         tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1819         tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */
1820         tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */
1821         tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */
1822         WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp);
1823
1824         tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1825         /* enable audio info frames (frames won't be set until audio is enabled) */
1826         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
1827         /* required for audio info values to be updated */
1828         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1);
1829         WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1830
1831         tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset);
1832         /* required for audio info values to be updated */
1833         tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
1834         WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1835
1836         tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1837         /* anything other than 0 */
1838         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2);
1839         WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1840
1841         WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */
1842
1843         tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1844         /* set the default audio delay */
1845         tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1);
1846         /* should be suffient for all audio modes and small enough for all hblanks */
1847         tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3);
1848         WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1849
1850         tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1851         /* allow 60958 channel status fields to be updated */
1852         tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1853         WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1854
1855         tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset);
1856         if (bpc > 8)
1857                 /* clear SW CTS value */
1858                 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0);
1859         else
1860                 /* select SW CTS value */
1861                 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1);
1862         /* allow hw to sent ACR packets when required */
1863         tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1);
1864         WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp);
1865
1866         dce_v11_0_afmt_update_ACR(encoder, mode->clock);
1867
1868         tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset);
1869         tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1);
1870         WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp);
1871
1872         tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset);
1873         tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
1874         WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp);
1875
1876         tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset);
1877         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3);
1878         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4);
1879         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5);
1880         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6);
1881         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7);
1882         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
1883         WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp);
1884
1885         dce_v11_0_audio_write_speaker_allocation(encoder);
1886
1887         WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset,
1888                (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT));
1889
1890         dce_v11_0_afmt_audio_select_pin(encoder);
1891         dce_v11_0_audio_write_sad_regs(encoder);
1892         dce_v11_0_audio_write_latency_fields(encoder, mode);
1893
1894         err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
1895         if (err < 0) {
1896                 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
1897                 return;
1898         }
1899
1900         err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1901         if (err < 0) {
1902                 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
1903                 return;
1904         }
1905
1906         dce_v11_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer));
1907
1908         tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1909         /* enable AVI info frames */
1910         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1);
1911         /* required for audio info values to be updated */
1912         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1);
1913         WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1914
1915         tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1916         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2);
1917         WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1918
1919         tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1920         /* send audio packets */
1921         tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1);
1922         WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1923
1924         WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF);
1925         WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF);
1926         WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001);
1927         WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001);
1928
1929         /* enable audio after to setting up hw */
1930         dce_v11_0_audio_enable(adev, dig->afmt->pin, true);
1931 }
1932
1933 static void dce_v11_0_afmt_enable(struct drm_encoder *encoder, bool enable)
1934 {
1935         struct drm_device *dev = encoder->dev;
1936         struct amdgpu_device *adev = dev->dev_private;
1937         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1938         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1939
1940         if (!dig || !dig->afmt)
1941                 return;
1942
1943         /* Silent, r600_hdmi_enable will raise WARN for us */
1944         if (enable && dig->afmt->enabled)
1945                 return;
1946         if (!enable && !dig->afmt->enabled)
1947                 return;
1948
1949         if (!enable && dig->afmt->pin) {
1950                 dce_v11_0_audio_enable(adev, dig->afmt->pin, false);
1951                 dig->afmt->pin = NULL;
1952         }
1953
1954         dig->afmt->enabled = enable;
1955
1956         DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
1957                   enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
1958 }
1959
1960 static int dce_v11_0_afmt_init(struct amdgpu_device *adev)
1961 {
1962         int i;
1963
1964         for (i = 0; i < adev->mode_info.num_dig; i++)
1965                 adev->mode_info.afmt[i] = NULL;
1966
1967         /* DCE11 has audio blocks tied to DIG encoders */
1968         for (i = 0; i < adev->mode_info.num_dig; i++) {
1969                 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);
1970                 if (adev->mode_info.afmt[i]) {
1971                         adev->mode_info.afmt[i]->offset = dig_offsets[i];
1972                         adev->mode_info.afmt[i]->id = i;
1973                 } else {
1974                         int j;
1975                         for (j = 0; j < i; j++) {
1976                                 kfree(adev->mode_info.afmt[j]);
1977                                 adev->mode_info.afmt[j] = NULL;
1978                         }
1979                         return -ENOMEM;
1980                 }
1981         }
1982         return 0;
1983 }
1984
1985 static void dce_v11_0_afmt_fini(struct amdgpu_device *adev)
1986 {
1987         int i;
1988
1989         for (i = 0; i < adev->mode_info.num_dig; i++) {
1990                 kfree(adev->mode_info.afmt[i]);
1991                 adev->mode_info.afmt[i] = NULL;
1992         }
1993 }
1994
1995 static const u32 vga_control_regs[6] =
1996 {
1997         mmD1VGA_CONTROL,
1998         mmD2VGA_CONTROL,
1999         mmD3VGA_CONTROL,
2000         mmD4VGA_CONTROL,
2001         mmD5VGA_CONTROL,
2002         mmD6VGA_CONTROL,
2003 };
2004
2005 static void dce_v11_0_vga_enable(struct drm_crtc *crtc, bool enable)
2006 {
2007         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2008         struct drm_device *dev = crtc->dev;
2009         struct amdgpu_device *adev = dev->dev_private;
2010         u32 vga_control;
2011
2012         vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
2013         if (enable)
2014                 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
2015         else
2016                 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
2017 }
2018
2019 static void dce_v11_0_grph_enable(struct drm_crtc *crtc, bool enable)
2020 {
2021         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2022         struct drm_device *dev = crtc->dev;
2023         struct amdgpu_device *adev = dev->dev_private;
2024
2025         if (enable)
2026                 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
2027         else
2028                 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
2029 }
2030
2031 static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc,
2032                                      struct drm_framebuffer *fb,
2033                                      int x, int y, int atomic)
2034 {
2035         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2036         struct drm_device *dev = crtc->dev;
2037         struct amdgpu_device *adev = dev->dev_private;
2038         struct amdgpu_framebuffer *amdgpu_fb;
2039         struct drm_framebuffer *target_fb;
2040         struct drm_gem_object *obj;
2041         struct amdgpu_bo *rbo;
2042         uint64_t fb_location, tiling_flags;
2043         uint32_t fb_format, fb_pitch_pixels;
2044         u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE);
2045         u32 pipe_config;
2046         u32 tmp, viewport_w, viewport_h;
2047         int r;
2048         bool bypass_lut = false;
2049
2050         /* no fb bound */
2051         if (!atomic && !crtc->primary->fb) {
2052                 DRM_DEBUG_KMS("No FB bound\n");
2053                 return 0;
2054         }
2055
2056         if (atomic) {
2057                 amdgpu_fb = to_amdgpu_framebuffer(fb);
2058                 target_fb = fb;
2059         } else {
2060                 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
2061                 target_fb = crtc->primary->fb;
2062         }
2063
2064         /* If atomic, assume fb object is pinned & idle & fenced and
2065          * just update base pointers
2066          */
2067         obj = amdgpu_fb->obj;
2068         rbo = gem_to_amdgpu_bo(obj);
2069         r = amdgpu_bo_reserve(rbo, false);
2070         if (unlikely(r != 0))
2071                 return r;
2072
2073         if (atomic) {
2074                 fb_location = amdgpu_bo_gpu_offset(rbo);
2075         } else {
2076                 r = amdgpu_bo_pin(rbo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location);
2077                 if (unlikely(r != 0)) {
2078                         amdgpu_bo_unreserve(rbo);
2079                         return -EINVAL;
2080                 }
2081         }
2082
2083         amdgpu_bo_get_tiling_flags(rbo, &tiling_flags);
2084         amdgpu_bo_unreserve(rbo);
2085
2086         pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
2087
2088         switch (target_fb->pixel_format) {
2089         case DRM_FORMAT_C8:
2090                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0);
2091                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2092                 break;
2093         case DRM_FORMAT_XRGB4444:
2094         case DRM_FORMAT_ARGB4444:
2095                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2096                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 2);
2097 #ifdef __BIG_ENDIAN
2098                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2099                                         ENDIAN_8IN16);
2100 #endif
2101                 break;
2102         case DRM_FORMAT_XRGB1555:
2103         case DRM_FORMAT_ARGB1555:
2104                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2105                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2106 #ifdef __BIG_ENDIAN
2107                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2108                                         ENDIAN_8IN16);
2109 #endif
2110                 break;
2111         case DRM_FORMAT_BGRX5551:
2112         case DRM_FORMAT_BGRA5551:
2113                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2114                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 5);
2115 #ifdef __BIG_ENDIAN
2116                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2117                                         ENDIAN_8IN16);
2118 #endif
2119                 break;
2120         case DRM_FORMAT_RGB565:
2121                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2122                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
2123 #ifdef __BIG_ENDIAN
2124                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2125                                         ENDIAN_8IN16);
2126 #endif
2127                 break;
2128         case DRM_FORMAT_XRGB8888:
2129         case DRM_FORMAT_ARGB8888:
2130                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2131                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2132 #ifdef __BIG_ENDIAN
2133                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2134                                         ENDIAN_8IN32);
2135 #endif
2136                 break;
2137         case DRM_FORMAT_XRGB2101010:
2138         case DRM_FORMAT_ARGB2101010:
2139                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2140                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
2141 #ifdef __BIG_ENDIAN
2142                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2143                                         ENDIAN_8IN32);
2144 #endif
2145                 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2146                 bypass_lut = true;
2147                 break;
2148         case DRM_FORMAT_BGRX1010102:
2149         case DRM_FORMAT_BGRA1010102:
2150                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2151                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 4);
2152 #ifdef __BIG_ENDIAN
2153                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2154                                         ENDIAN_8IN32);
2155 #endif
2156                 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2157                 bypass_lut = true;
2158                 break;
2159         default:
2160                 DRM_ERROR("Unsupported screen format %s\n",
2161                         drm_get_format_name(target_fb->pixel_format));
2162                 return -EINVAL;
2163         }
2164
2165         if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
2166                 unsigned bankw, bankh, mtaspect, tile_split, num_banks;
2167
2168                 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
2169                 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
2170                 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
2171                 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
2172                 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
2173
2174                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks);
2175                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2176                                           ARRAY_2D_TILED_THIN1);
2177                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_TILE_SPLIT,
2178                                           tile_split);
2179                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw);
2180                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh);
2181                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT,
2182                                           mtaspect);
2183                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE,
2184                                           ADDR_SURF_MICRO_TILING_DISPLAY);
2185         } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
2186                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2187                                           ARRAY_1D_TILED_THIN1);
2188         }
2189
2190         fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG,
2191                                   pipe_config);
2192
2193         dce_v11_0_vga_enable(crtc, false);
2194
2195         /* Make sure surface address is updated at vertical blank rather than
2196          * horizontal blank
2197          */
2198         tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
2199         tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
2200                             GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0);
2201         WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2202
2203         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2204                upper_32_bits(fb_location));
2205         WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2206                upper_32_bits(fb_location));
2207         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2208                (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
2209         WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2210                (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK);
2211         WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
2212         WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
2213
2214         /*
2215          * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
2216          * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
2217          * retain the full precision throughout the pipeline.
2218          */
2219         tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset);
2220         if (bypass_lut)
2221                 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1);
2222         else
2223                 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0);
2224         WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp);
2225
2226         if (bypass_lut)
2227                 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
2228
2229         WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
2230         WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
2231         WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
2232         WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
2233         WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
2234         WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
2235
2236         fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
2237         WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
2238
2239         dce_v11_0_grph_enable(crtc, true);
2240
2241         WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
2242                target_fb->height);
2243
2244         x &= ~3;
2245         y &= ~1;
2246         WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
2247                (x << 16) | y);
2248         viewport_w = crtc->mode.hdisplay;
2249         viewport_h = (crtc->mode.vdisplay + 1) & ~1;
2250         WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
2251                (viewport_w << 16) | viewport_h);
2252
2253         /* set pageflip to happen only at start of vblank interval (front porch) */
2254         WREG32(mmCRTC_MASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 3);
2255
2256         if (!atomic && fb && fb != crtc->primary->fb) {
2257                 amdgpu_fb = to_amdgpu_framebuffer(fb);
2258                 rbo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2259                 r = amdgpu_bo_reserve(rbo, false);
2260                 if (unlikely(r != 0))
2261                         return r;
2262                 amdgpu_bo_unpin(rbo);
2263                 amdgpu_bo_unreserve(rbo);
2264         }
2265
2266         /* Bytes per pixel may have changed */
2267         dce_v11_0_bandwidth_update(adev);
2268
2269         return 0;
2270 }
2271
2272 static void dce_v11_0_set_interleave(struct drm_crtc *crtc,
2273                                      struct drm_display_mode *mode)
2274 {
2275         struct drm_device *dev = crtc->dev;
2276         struct amdgpu_device *adev = dev->dev_private;
2277         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2278         u32 tmp;
2279
2280         tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset);
2281         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2282                 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1);
2283         else
2284                 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0);
2285         WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp);
2286 }
2287
2288 static void dce_v11_0_crtc_load_lut(struct drm_crtc *crtc)
2289 {
2290         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2291         struct drm_device *dev = crtc->dev;
2292         struct amdgpu_device *adev = dev->dev_private;
2293         int i;
2294         u32 tmp;
2295
2296         DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
2297
2298         tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2299         tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0);
2300         WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2301
2302         tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset);
2303         tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1);
2304         WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2305
2306         tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2307         tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0);
2308         WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2309
2310         WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
2311
2312         WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
2313         WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
2314         WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
2315
2316         WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
2317         WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
2318         WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
2319
2320         WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
2321         WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
2322
2323         WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
2324         for (i = 0; i < 256; i++) {
2325                 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
2326                        (amdgpu_crtc->lut_r[i] << 20) |
2327                        (amdgpu_crtc->lut_g[i] << 10) |
2328                        (amdgpu_crtc->lut_b[i] << 0));
2329         }
2330
2331         tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2332         tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0);
2333         tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0);
2334         tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR2_DEGAMMA_MODE, 0);
2335         WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2336
2337         tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset);
2338         tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0);
2339         WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2340
2341         tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2342         tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0);
2343         WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2344
2345         tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2346         tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0);
2347         WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2348
2349         /* XXX match this to the depth of the crtc fmt block, move to modeset? */
2350         WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0);
2351         /* XXX this only needs to be programmed once per crtc at startup,
2352          * not sure where the best place for it is
2353          */
2354         tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset);
2355         tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1);
2356         WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2357 }
2358
2359 static int dce_v11_0_pick_dig_encoder(struct drm_encoder *encoder)
2360 {
2361         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2362         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2363
2364         switch (amdgpu_encoder->encoder_id) {
2365         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2366                 if (dig->linkb)
2367                         return 1;
2368                 else
2369                         return 0;
2370                 break;
2371         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2372                 if (dig->linkb)
2373                         return 3;
2374                 else
2375                         return 2;
2376                 break;
2377         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2378                 if (dig->linkb)
2379                         return 5;
2380                 else
2381                         return 4;
2382                 break;
2383         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2384                 return 6;
2385                 break;
2386         default:
2387                 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2388                 return 0;
2389         }
2390 }
2391
2392 /**
2393  * dce_v11_0_pick_pll - Allocate a PPLL for use by the crtc.
2394  *
2395  * @crtc: drm crtc
2396  *
2397  * Returns the PPLL (Pixel PLL) to be used by the crtc.  For DP monitors
2398  * a single PPLL can be used for all DP crtcs/encoders.  For non-DP
2399  * monitors a dedicated PPLL must be used.  If a particular board has
2400  * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
2401  * as there is no need to program the PLL itself.  If we are not able to
2402  * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
2403  * avoid messing up an existing monitor.
2404  *
2405  * Asic specific PLL information
2406  *
2407  * DCE 10.x
2408  * Tonga
2409  * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
2410  * CI
2411  * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
2412  *
2413  */
2414 static u32 dce_v11_0_pick_pll(struct drm_crtc *crtc)
2415 {
2416         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2417         struct drm_device *dev = crtc->dev;
2418         struct amdgpu_device *adev = dev->dev_private;
2419         u32 pll_in_use;
2420         int pll;
2421
2422         if ((adev->asic_type == CHIP_POLARIS10) ||
2423             (adev->asic_type == CHIP_POLARIS11)) {
2424                 struct amdgpu_encoder *amdgpu_encoder =
2425                         to_amdgpu_encoder(amdgpu_crtc->encoder);
2426                 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2427
2428                 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2429                         return ATOM_DP_DTO;
2430
2431                 switch (amdgpu_encoder->encoder_id) {
2432                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2433                         if (dig->linkb)
2434                                 return ATOM_COMBOPHY_PLL1;
2435                         else
2436                                 return ATOM_COMBOPHY_PLL0;
2437                         break;
2438                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2439                         if (dig->linkb)
2440                                 return ATOM_COMBOPHY_PLL3;
2441                         else
2442                                 return ATOM_COMBOPHY_PLL2;
2443                         break;
2444                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2445                         if (dig->linkb)
2446                                 return ATOM_COMBOPHY_PLL5;
2447                         else
2448                                 return ATOM_COMBOPHY_PLL4;
2449                         break;
2450                 default:
2451                         DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2452                         return ATOM_PPLL_INVALID;
2453                 }
2454         }
2455
2456         if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
2457                 if (adev->clock.dp_extclk)
2458                         /* skip PPLL programming if using ext clock */
2459                         return ATOM_PPLL_INVALID;
2460                 else {
2461                         /* use the same PPLL for all DP monitors */
2462                         pll = amdgpu_pll_get_shared_dp_ppll(crtc);
2463                         if (pll != ATOM_PPLL_INVALID)
2464                                 return pll;
2465                 }
2466         } else {
2467                 /* use the same PPLL for all monitors with the same clock */
2468                 pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
2469                 if (pll != ATOM_PPLL_INVALID)
2470                         return pll;
2471         }
2472
2473         /* XXX need to determine what plls are available on each DCE11 part */
2474         pll_in_use = amdgpu_pll_get_use_mask(crtc);
2475         if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY) {
2476                 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2477                         return ATOM_PPLL1;
2478                 if (!(pll_in_use & (1 << ATOM_PPLL0)))
2479                         return ATOM_PPLL0;
2480                 DRM_ERROR("unable to allocate a PPLL\n");
2481                 return ATOM_PPLL_INVALID;
2482         } else {
2483                 if (!(pll_in_use & (1 << ATOM_PPLL2)))
2484                         return ATOM_PPLL2;
2485                 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2486                         return ATOM_PPLL1;
2487                 if (!(pll_in_use & (1 << ATOM_PPLL0)))
2488                         return ATOM_PPLL0;
2489                 DRM_ERROR("unable to allocate a PPLL\n");
2490                 return ATOM_PPLL_INVALID;
2491         }
2492         return ATOM_PPLL_INVALID;
2493 }
2494
2495 static void dce_v11_0_lock_cursor(struct drm_crtc *crtc, bool lock)
2496 {
2497         struct amdgpu_device *adev = crtc->dev->dev_private;
2498         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2499         uint32_t cur_lock;
2500
2501         cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
2502         if (lock)
2503                 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 1);
2504         else
2505                 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 0);
2506         WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
2507 }
2508
2509 static void dce_v11_0_hide_cursor(struct drm_crtc *crtc)
2510 {
2511         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2512         struct amdgpu_device *adev = crtc->dev->dev_private;
2513         u32 tmp;
2514
2515         tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2516         tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0);
2517         WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2518 }
2519
2520 static void dce_v11_0_show_cursor(struct drm_crtc *crtc)
2521 {
2522         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2523         struct amdgpu_device *adev = crtc->dev->dev_private;
2524         u32 tmp;
2525
2526         WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2527                upper_32_bits(amdgpu_crtc->cursor_addr));
2528         WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2529                lower_32_bits(amdgpu_crtc->cursor_addr));
2530
2531         tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2532         tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1);
2533         tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2);
2534         WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2535 }
2536
2537 static int dce_v11_0_cursor_move_locked(struct drm_crtc *crtc,
2538                                         int x, int y)
2539 {
2540         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2541         struct amdgpu_device *adev = crtc->dev->dev_private;
2542         int xorigin = 0, yorigin = 0;
2543
2544         /* avivo cursor are offset into the total surface */
2545         x += crtc->x;
2546         y += crtc->y;
2547         DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
2548
2549         if (x < 0) {
2550                 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
2551                 x = 0;
2552         }
2553         if (y < 0) {
2554                 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
2555                 y = 0;
2556         }
2557
2558         WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
2559         WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
2560         WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
2561                ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
2562
2563         amdgpu_crtc->cursor_x = x;
2564         amdgpu_crtc->cursor_y = y;
2565
2566         return 0;
2567 }
2568
2569 static int dce_v11_0_crtc_cursor_move(struct drm_crtc *crtc,
2570                                       int x, int y)
2571 {
2572         int ret;
2573
2574         dce_v11_0_lock_cursor(crtc, true);
2575         ret = dce_v11_0_cursor_move_locked(crtc, x, y);
2576         dce_v11_0_lock_cursor(crtc, false);
2577
2578         return ret;
2579 }
2580
2581 static int dce_v11_0_crtc_cursor_set2(struct drm_crtc *crtc,
2582                                       struct drm_file *file_priv,
2583                                       uint32_t handle,
2584                                       uint32_t width,
2585                                       uint32_t height,
2586                                       int32_t hot_x,
2587                                       int32_t hot_y)
2588 {
2589         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2590         struct drm_gem_object *obj;
2591         struct amdgpu_bo *aobj;
2592         int ret;
2593
2594         if (!handle) {
2595                 /* turn off cursor */
2596                 dce_v11_0_hide_cursor(crtc);
2597                 obj = NULL;
2598                 goto unpin;
2599         }
2600
2601         if ((width > amdgpu_crtc->max_cursor_width) ||
2602             (height > amdgpu_crtc->max_cursor_height)) {
2603                 DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
2604                 return -EINVAL;
2605         }
2606
2607         obj = drm_gem_object_lookup(file_priv, handle);
2608         if (!obj) {
2609                 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
2610                 return -ENOENT;
2611         }
2612
2613         aobj = gem_to_amdgpu_bo(obj);
2614         ret = amdgpu_bo_reserve(aobj, false);
2615         if (ret != 0) {
2616                 drm_gem_object_unreference_unlocked(obj);
2617                 return ret;
2618         }
2619
2620         ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM, &amdgpu_crtc->cursor_addr);
2621         amdgpu_bo_unreserve(aobj);
2622         if (ret) {
2623                 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
2624                 drm_gem_object_unreference_unlocked(obj);
2625                 return ret;
2626         }
2627
2628         amdgpu_crtc->cursor_width = width;
2629         amdgpu_crtc->cursor_height = height;
2630
2631         dce_v11_0_lock_cursor(crtc, true);
2632
2633         if (hot_x != amdgpu_crtc->cursor_hot_x ||
2634             hot_y != amdgpu_crtc->cursor_hot_y) {
2635                 int x, y;
2636
2637                 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
2638                 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
2639
2640                 dce_v11_0_cursor_move_locked(crtc, x, y);
2641
2642                 amdgpu_crtc->cursor_hot_x = hot_x;
2643                 amdgpu_crtc->cursor_hot_y = hot_y;
2644         }
2645
2646         dce_v11_0_show_cursor(crtc);
2647         dce_v11_0_lock_cursor(crtc, false);
2648
2649 unpin:
2650         if (amdgpu_crtc->cursor_bo) {
2651                 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2652                 ret = amdgpu_bo_reserve(aobj, false);
2653                 if (likely(ret == 0)) {
2654                         amdgpu_bo_unpin(aobj);
2655                         amdgpu_bo_unreserve(aobj);
2656                 }
2657                 drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo);
2658         }
2659
2660         amdgpu_crtc->cursor_bo = obj;
2661         return 0;
2662 }
2663
2664 static void dce_v11_0_cursor_reset(struct drm_crtc *crtc)
2665 {
2666         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2667
2668         if (amdgpu_crtc->cursor_bo) {
2669                 dce_v11_0_lock_cursor(crtc, true);
2670
2671                 dce_v11_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
2672                                              amdgpu_crtc->cursor_y);
2673
2674                 dce_v11_0_show_cursor(crtc);
2675
2676                 dce_v11_0_lock_cursor(crtc, false);
2677         }
2678 }
2679
2680 static int dce_v11_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2681                                     u16 *blue, uint32_t size)
2682 {
2683         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2684         int i;
2685
2686         /* userspace palettes are always correct as is */
2687         for (i = 0; i < size; i++) {
2688                 amdgpu_crtc->lut_r[i] = red[i] >> 6;
2689                 amdgpu_crtc->lut_g[i] = green[i] >> 6;
2690                 amdgpu_crtc->lut_b[i] = blue[i] >> 6;
2691         }
2692         dce_v11_0_crtc_load_lut(crtc);
2693
2694         return 0;
2695 }
2696
2697 static void dce_v11_0_crtc_destroy(struct drm_crtc *crtc)
2698 {
2699         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2700
2701         drm_crtc_cleanup(crtc);
2702         kfree(amdgpu_crtc);
2703 }
2704
2705 static const struct drm_crtc_funcs dce_v11_0_crtc_funcs = {
2706         .cursor_set2 = dce_v11_0_crtc_cursor_set2,
2707         .cursor_move = dce_v11_0_crtc_cursor_move,
2708         .gamma_set = dce_v11_0_crtc_gamma_set,
2709         .set_config = amdgpu_crtc_set_config,
2710         .destroy = dce_v11_0_crtc_destroy,
2711         .page_flip = amdgpu_crtc_page_flip,
2712 };
2713
2714 static void dce_v11_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2715 {
2716         struct drm_device *dev = crtc->dev;
2717         struct amdgpu_device *adev = dev->dev_private;
2718         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2719         unsigned type;
2720
2721         switch (mode) {
2722         case DRM_MODE_DPMS_ON:
2723                 amdgpu_crtc->enabled = true;
2724                 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE);
2725                 dce_v11_0_vga_enable(crtc, true);
2726                 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
2727                 dce_v11_0_vga_enable(crtc, false);
2728                 /* Make sure VBLANK and PFLIP interrupts are still enabled */
2729                 type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id);
2730                 amdgpu_irq_update(adev, &adev->crtc_irq, type);
2731                 amdgpu_irq_update(adev, &adev->pageflip_irq, type);
2732                 drm_crtc_vblank_on(crtc);
2733                 dce_v11_0_crtc_load_lut(crtc);
2734                 break;
2735         case DRM_MODE_DPMS_STANDBY:
2736         case DRM_MODE_DPMS_SUSPEND:
2737         case DRM_MODE_DPMS_OFF:
2738                 drm_crtc_vblank_off(crtc);
2739                 if (amdgpu_crtc->enabled) {
2740                         dce_v11_0_vga_enable(crtc, true);
2741                         amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
2742                         dce_v11_0_vga_enable(crtc, false);
2743                 }
2744                 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE);
2745                 amdgpu_crtc->enabled = false;
2746                 break;
2747         }
2748         /* adjust pm to dpms */
2749         amdgpu_pm_compute_clocks(adev);
2750 }
2751
2752 static void dce_v11_0_crtc_prepare(struct drm_crtc *crtc)
2753 {
2754         /* disable crtc pair power gating before programming */
2755         amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE);
2756         amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE);
2757         dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2758 }
2759
2760 static void dce_v11_0_crtc_commit(struct drm_crtc *crtc)
2761 {
2762         dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2763         amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE);
2764 }
2765
2766 static void dce_v11_0_crtc_disable(struct drm_crtc *crtc)
2767 {
2768         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2769         struct drm_device *dev = crtc->dev;
2770         struct amdgpu_device *adev = dev->dev_private;
2771         struct amdgpu_atom_ss ss;
2772         int i;
2773
2774         dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2775         if (crtc->primary->fb) {
2776                 int r;
2777                 struct amdgpu_framebuffer *amdgpu_fb;
2778                 struct amdgpu_bo *rbo;
2779
2780                 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
2781                 rbo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2782                 r = amdgpu_bo_reserve(rbo, false);
2783                 if (unlikely(r))
2784                         DRM_ERROR("failed to reserve rbo before unpin\n");
2785                 else {
2786                         amdgpu_bo_unpin(rbo);
2787                         amdgpu_bo_unreserve(rbo);
2788                 }
2789         }
2790         /* disable the GRPH */
2791         dce_v11_0_grph_enable(crtc, false);
2792
2793         amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE);
2794
2795         for (i = 0; i < adev->mode_info.num_crtc; i++) {
2796                 if (adev->mode_info.crtcs[i] &&
2797                     adev->mode_info.crtcs[i]->enabled &&
2798                     i != amdgpu_crtc->crtc_id &&
2799                     amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
2800                         /* one other crtc is using this pll don't turn
2801                          * off the pll
2802                          */
2803                         goto done;
2804                 }
2805         }
2806
2807         switch (amdgpu_crtc->pll_id) {
2808         case ATOM_PPLL0:
2809         case ATOM_PPLL1:
2810         case ATOM_PPLL2:
2811                 /* disable the ppll */
2812                 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2813                                                  0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2814                 break;
2815         case ATOM_COMBOPHY_PLL0:
2816         case ATOM_COMBOPHY_PLL1:
2817         case ATOM_COMBOPHY_PLL2:
2818         case ATOM_COMBOPHY_PLL3:
2819         case ATOM_COMBOPHY_PLL4:
2820         case ATOM_COMBOPHY_PLL5:
2821                 /* disable the ppll */
2822                 amdgpu_atombios_crtc_program_pll(crtc, ATOM_CRTC_INVALID, amdgpu_crtc->pll_id,
2823                                                  0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2824                 break;
2825         default:
2826                 break;
2827         }
2828 done:
2829         amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2830         amdgpu_crtc->adjusted_clock = 0;
2831         amdgpu_crtc->encoder = NULL;
2832         amdgpu_crtc->connector = NULL;
2833 }
2834
2835 static int dce_v11_0_crtc_mode_set(struct drm_crtc *crtc,
2836                                   struct drm_display_mode *mode,
2837                                   struct drm_display_mode *adjusted_mode,
2838                                   int x, int y, struct drm_framebuffer *old_fb)
2839 {
2840         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2841         struct drm_device *dev = crtc->dev;
2842         struct amdgpu_device *adev = dev->dev_private;
2843
2844         if (!amdgpu_crtc->adjusted_clock)
2845                 return -EINVAL;
2846
2847         if ((adev->asic_type == CHIP_POLARIS10) ||
2848             (adev->asic_type == CHIP_POLARIS11)) {
2849                 struct amdgpu_encoder *amdgpu_encoder =
2850                         to_amdgpu_encoder(amdgpu_crtc->encoder);
2851                 int encoder_mode =
2852                         amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder);
2853
2854                 /* SetPixelClock calculates the plls and ss values now */
2855                 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id,
2856                                                  amdgpu_crtc->pll_id,
2857                                                  encoder_mode, amdgpu_encoder->encoder_id,
2858                                                  adjusted_mode->clock, 0, 0, 0, 0,
2859                                                  amdgpu_crtc->bpc, amdgpu_crtc->ss_enabled, &amdgpu_crtc->ss);
2860         } else {
2861                 amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
2862         }
2863         amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
2864         dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2865         amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
2866         amdgpu_atombios_crtc_scaler_setup(crtc);
2867         dce_v11_0_cursor_reset(crtc);
2868         /* update the hw version fpr dpm */
2869         amdgpu_crtc->hw_mode = *adjusted_mode;
2870
2871         return 0;
2872 }
2873
2874 static bool dce_v11_0_crtc_mode_fixup(struct drm_crtc *crtc,
2875                                      const struct drm_display_mode *mode,
2876                                      struct drm_display_mode *adjusted_mode)
2877 {
2878         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2879         struct drm_device *dev = crtc->dev;
2880         struct drm_encoder *encoder;
2881
2882         /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2883         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2884                 if (encoder->crtc == crtc) {
2885                         amdgpu_crtc->encoder = encoder;
2886                         amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
2887                         break;
2888                 }
2889         }
2890         if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {
2891                 amdgpu_crtc->encoder = NULL;
2892                 amdgpu_crtc->connector = NULL;
2893                 return false;
2894         }
2895         if (!amdgpu_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2896                 return false;
2897         if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode))
2898                 return false;
2899         /* pick pll */
2900         amdgpu_crtc->pll_id = dce_v11_0_pick_pll(crtc);
2901         /* if we can't get a PPLL for a non-DP encoder, fail */
2902         if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
2903             !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2904                 return false;
2905
2906         return true;
2907 }
2908
2909 static int dce_v11_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
2910                                   struct drm_framebuffer *old_fb)
2911 {
2912         return dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2913 }
2914
2915 static int dce_v11_0_crtc_set_base_atomic(struct drm_crtc *crtc,
2916                                          struct drm_framebuffer *fb,
2917                                          int x, int y, enum mode_set_atomic state)
2918 {
2919        return dce_v11_0_crtc_do_set_base(crtc, fb, x, y, 1);
2920 }
2921
2922 static const struct drm_crtc_helper_funcs dce_v11_0_crtc_helper_funcs = {
2923         .dpms = dce_v11_0_crtc_dpms,
2924         .mode_fixup = dce_v11_0_crtc_mode_fixup,
2925         .mode_set = dce_v11_0_crtc_mode_set,
2926         .mode_set_base = dce_v11_0_crtc_set_base,
2927         .mode_set_base_atomic = dce_v11_0_crtc_set_base_atomic,
2928         .prepare = dce_v11_0_crtc_prepare,
2929         .commit = dce_v11_0_crtc_commit,
2930         .load_lut = dce_v11_0_crtc_load_lut,
2931         .disable = dce_v11_0_crtc_disable,
2932 };
2933
2934 static int dce_v11_0_crtc_init(struct amdgpu_device *adev, int index)
2935 {
2936         struct amdgpu_crtc *amdgpu_crtc;
2937         int i;
2938
2939         amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
2940                               (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
2941         if (amdgpu_crtc == NULL)
2942                 return -ENOMEM;
2943
2944         drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v11_0_crtc_funcs);
2945
2946         drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
2947         amdgpu_crtc->crtc_id = index;
2948         adev->mode_info.crtcs[index] = amdgpu_crtc;
2949
2950         amdgpu_crtc->max_cursor_width = 128;
2951         amdgpu_crtc->max_cursor_height = 128;
2952         adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
2953         adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
2954
2955         for (i = 0; i < 256; i++) {
2956                 amdgpu_crtc->lut_r[i] = i << 2;
2957                 amdgpu_crtc->lut_g[i] = i << 2;
2958                 amdgpu_crtc->lut_b[i] = i << 2;
2959         }
2960
2961         switch (amdgpu_crtc->crtc_id) {
2962         case 0:
2963         default:
2964                 amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET;
2965                 break;
2966         case 1:
2967                 amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET;
2968                 break;
2969         case 2:
2970                 amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET;
2971                 break;
2972         case 3:
2973                 amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET;
2974                 break;
2975         case 4:
2976                 amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET;
2977                 break;
2978         case 5:
2979                 amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET;
2980                 break;
2981         }
2982
2983         amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2984         amdgpu_crtc->adjusted_clock = 0;
2985         amdgpu_crtc->encoder = NULL;
2986         amdgpu_crtc->connector = NULL;
2987         drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v11_0_crtc_helper_funcs);
2988
2989         return 0;
2990 }
2991
2992 static int dce_v11_0_early_init(void *handle)
2993 {
2994         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2995
2996         adev->audio_endpt_rreg = &dce_v11_0_audio_endpt_rreg;
2997         adev->audio_endpt_wreg = &dce_v11_0_audio_endpt_wreg;
2998
2999         dce_v11_0_set_display_funcs(adev);
3000         dce_v11_0_set_irq_funcs(adev);
3001
3002         switch (adev->asic_type) {
3003         case CHIP_CARRIZO:
3004                 adev->mode_info.num_crtc = 3;
3005                 adev->mode_info.num_hpd = 6;
3006                 adev->mode_info.num_dig = 9;
3007                 break;
3008         case CHIP_STONEY:
3009                 adev->mode_info.num_crtc = 2;
3010                 adev->mode_info.num_hpd = 6;
3011                 adev->mode_info.num_dig = 9;
3012                 break;
3013         case CHIP_POLARIS10:
3014                 adev->mode_info.num_crtc = 6;
3015                 adev->mode_info.num_hpd = 6;
3016                 adev->mode_info.num_dig = 6;
3017                 break;
3018         case CHIP_POLARIS11:
3019                 adev->mode_info.num_crtc = 5;
3020                 adev->mode_info.num_hpd = 5;
3021                 adev->mode_info.num_dig = 5;
3022                 break;
3023         default:
3024                 /* FIXME: not supported yet */
3025                 return -EINVAL;
3026         }
3027
3028         return 0;
3029 }
3030
3031 static int dce_v11_0_sw_init(void *handle)
3032 {
3033         int r, i;
3034         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3035
3036         for (i = 0; i < adev->mode_info.num_crtc; i++) {
3037                 r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq);
3038                 if (r)
3039                         return r;
3040         }
3041
3042         for (i = 8; i < 20; i += 2) {
3043                 r = amdgpu_irq_add_id(adev, i, &adev->pageflip_irq);
3044                 if (r)
3045                         return r;
3046         }
3047
3048         /* HPD hotplug */
3049         r = amdgpu_irq_add_id(adev, 42, &adev->hpd_irq);
3050         if (r)
3051                 return r;
3052
3053         adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
3054
3055         adev->ddev->mode_config.async_page_flip = true;
3056
3057         adev->ddev->mode_config.max_width = 16384;
3058         adev->ddev->mode_config.max_height = 16384;
3059
3060         adev->ddev->mode_config.preferred_depth = 24;
3061         adev->ddev->mode_config.prefer_shadow = 1;
3062
3063         adev->ddev->mode_config.fb_base = adev->mc.aper_base;
3064
3065         r = amdgpu_modeset_create_props(adev);
3066         if (r)
3067                 return r;
3068
3069         adev->ddev->mode_config.max_width = 16384;
3070         adev->ddev->mode_config.max_height = 16384;
3071
3072
3073         /* allocate crtcs */
3074         for (i = 0; i < adev->mode_info.num_crtc; i++) {
3075                 r = dce_v11_0_crtc_init(adev, i);
3076                 if (r)
3077                         return r;
3078         }
3079
3080         if (amdgpu_atombios_get_connector_info_from_object_table(adev))
3081                 amdgpu_print_display_setup(adev->ddev);
3082         else
3083                 return -EINVAL;
3084
3085         /* setup afmt */
3086         r = dce_v11_0_afmt_init(adev);
3087         if (r)
3088                 return r;
3089
3090         r = dce_v11_0_audio_init(adev);
3091         if (r)
3092                 return r;
3093
3094         drm_kms_helper_poll_init(adev->ddev);
3095
3096         adev->mode_info.mode_config_initialized = true;
3097         return 0;
3098 }
3099
3100 static int dce_v11_0_sw_fini(void *handle)
3101 {
3102         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3103
3104         kfree(adev->mode_info.bios_hardcoded_edid);
3105
3106         drm_kms_helper_poll_fini(adev->ddev);
3107
3108         dce_v11_0_audio_fini(adev);
3109
3110         dce_v11_0_afmt_fini(adev);
3111
3112         adev->mode_info.mode_config_initialized = false;
3113
3114         return 0;
3115 }
3116
3117 static int dce_v11_0_hw_init(void *handle)
3118 {
3119         int i;
3120         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3121
3122         dce_v11_0_init_golden_registers(adev);
3123
3124         /* init dig PHYs, disp eng pll */
3125         amdgpu_atombios_crtc_powergate_init(adev);
3126         amdgpu_atombios_encoder_init_dig(adev);
3127         if ((adev->asic_type == CHIP_POLARIS10) ||
3128             (adev->asic_type == CHIP_POLARIS11)) {
3129                 amdgpu_atombios_crtc_set_dce_clock(adev, adev->clock.default_dispclk,
3130                                                    DCE_CLOCK_TYPE_DISPCLK, ATOM_GCK_DFS);
3131                 amdgpu_atombios_crtc_set_dce_clock(adev, 0,
3132                                                    DCE_CLOCK_TYPE_DPREFCLK, ATOM_GCK_DFS);
3133         } else {
3134                 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
3135         }
3136
3137         /* initialize hpd */
3138         dce_v11_0_hpd_init(adev);
3139
3140         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
3141                 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
3142         }
3143
3144         dce_v11_0_pageflip_interrupt_init(adev);
3145
3146         return 0;
3147 }
3148
3149 static int dce_v11_0_hw_fini(void *handle)
3150 {
3151         int i;
3152         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3153
3154         dce_v11_0_hpd_fini(adev);
3155
3156         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
3157                 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
3158         }
3159
3160         dce_v11_0_pageflip_interrupt_fini(adev);
3161
3162         return 0;
3163 }
3164
3165 static int dce_v11_0_suspend(void *handle)
3166 {
3167         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3168
3169         amdgpu_atombios_scratch_regs_save(adev);
3170
3171         return dce_v11_0_hw_fini(handle);
3172 }
3173
3174 static int dce_v11_0_resume(void *handle)
3175 {
3176         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3177         int ret;
3178
3179         ret = dce_v11_0_hw_init(handle);
3180
3181         amdgpu_atombios_scratch_regs_restore(adev);
3182
3183         /* turn on the BL */
3184         if (adev->mode_info.bl_encoder) {
3185                 u8 bl_level = amdgpu_display_backlight_get_level(adev,
3186                                                                   adev->mode_info.bl_encoder);
3187                 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder,
3188                                                     bl_level);
3189         }
3190
3191         return ret;
3192 }
3193
3194 static bool dce_v11_0_is_idle(void *handle)
3195 {
3196         return true;
3197 }
3198
3199 static int dce_v11_0_wait_for_idle(void *handle)
3200 {
3201         return 0;
3202 }
3203
3204 static int dce_v11_0_soft_reset(void *handle)
3205 {
3206         u32 srbm_soft_reset = 0, tmp;
3207         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3208
3209         if (dce_v11_0_is_display_hung(adev))
3210                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
3211
3212         if (srbm_soft_reset) {
3213                 tmp = RREG32(mmSRBM_SOFT_RESET);
3214                 tmp |= srbm_soft_reset;
3215                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
3216                 WREG32(mmSRBM_SOFT_RESET, tmp);
3217                 tmp = RREG32(mmSRBM_SOFT_RESET);
3218
3219                 udelay(50);
3220
3221                 tmp &= ~srbm_soft_reset;
3222                 WREG32(mmSRBM_SOFT_RESET, tmp);
3223                 tmp = RREG32(mmSRBM_SOFT_RESET);
3224
3225                 /* Wait a little for things to settle down */
3226                 udelay(50);
3227         }
3228         return 0;
3229 }
3230
3231 static void dce_v11_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
3232                                                      int crtc,
3233                                                      enum amdgpu_interrupt_state state)
3234 {
3235         u32 lb_interrupt_mask;
3236
3237         if (crtc >= adev->mode_info.num_crtc) {
3238                 DRM_DEBUG("invalid crtc %d\n", crtc);
3239                 return;
3240         }
3241
3242         switch (state) {
3243         case AMDGPU_IRQ_STATE_DISABLE:
3244                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3245                 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3246                                                   VBLANK_INTERRUPT_MASK, 0);
3247                 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3248                 break;
3249         case AMDGPU_IRQ_STATE_ENABLE:
3250                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3251                 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3252                                                   VBLANK_INTERRUPT_MASK, 1);
3253                 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3254                 break;
3255         default:
3256                 break;
3257         }
3258 }
3259
3260 static void dce_v11_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
3261                                                     int crtc,
3262                                                     enum amdgpu_interrupt_state state)
3263 {
3264         u32 lb_interrupt_mask;
3265
3266         if (crtc >= adev->mode_info.num_crtc) {
3267                 DRM_DEBUG("invalid crtc %d\n", crtc);
3268                 return;
3269         }
3270
3271         switch (state) {
3272         case AMDGPU_IRQ_STATE_DISABLE:
3273                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3274                 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3275                                                   VLINE_INTERRUPT_MASK, 0);
3276                 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3277                 break;
3278         case AMDGPU_IRQ_STATE_ENABLE:
3279                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3280                 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3281                                                   VLINE_INTERRUPT_MASK, 1);
3282                 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3283                 break;
3284         default:
3285                 break;
3286         }
3287 }
3288
3289 static int dce_v11_0_set_hpd_irq_state(struct amdgpu_device *adev,
3290                                         struct amdgpu_irq_src *source,
3291                                         unsigned hpd,
3292                                         enum amdgpu_interrupt_state state)
3293 {
3294         u32 tmp;
3295
3296         if (hpd >= adev->mode_info.num_hpd) {
3297                 DRM_DEBUG("invalid hdp %d\n", hpd);
3298                 return 0;
3299         }
3300
3301         switch (state) {
3302         case AMDGPU_IRQ_STATE_DISABLE:
3303                 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3304                 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
3305                 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3306                 break;
3307         case AMDGPU_IRQ_STATE_ENABLE:
3308                 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3309                 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1);
3310                 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3311                 break;
3312         default:
3313                 break;
3314         }
3315
3316         return 0;
3317 }
3318
3319 static int dce_v11_0_set_crtc_irq_state(struct amdgpu_device *adev,
3320                                         struct amdgpu_irq_src *source,
3321                                         unsigned type,
3322                                         enum amdgpu_interrupt_state state)
3323 {
3324         switch (type) {
3325         case AMDGPU_CRTC_IRQ_VBLANK1:
3326                 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 0, state);
3327                 break;
3328         case AMDGPU_CRTC_IRQ_VBLANK2:
3329                 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 1, state);
3330                 break;
3331         case AMDGPU_CRTC_IRQ_VBLANK3:
3332                 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 2, state);
3333                 break;
3334         case AMDGPU_CRTC_IRQ_VBLANK4:
3335                 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 3, state);
3336                 break;
3337         case AMDGPU_CRTC_IRQ_VBLANK5:
3338                 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 4, state);
3339                 break;
3340         case AMDGPU_CRTC_IRQ_VBLANK6:
3341                 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 5, state);
3342                 break;
3343         case AMDGPU_CRTC_IRQ_VLINE1:
3344                 dce_v11_0_set_crtc_vline_interrupt_state(adev, 0, state);
3345                 break;
3346         case AMDGPU_CRTC_IRQ_VLINE2:
3347                 dce_v11_0_set_crtc_vline_interrupt_state(adev, 1, state);
3348                 break;
3349         case AMDGPU_CRTC_IRQ_VLINE3:
3350                 dce_v11_0_set_crtc_vline_interrupt_state(adev, 2, state);
3351                 break;
3352         case AMDGPU_CRTC_IRQ_VLINE4:
3353                 dce_v11_0_set_crtc_vline_interrupt_state(adev, 3, state);
3354                 break;
3355         case AMDGPU_CRTC_IRQ_VLINE5:
3356                 dce_v11_0_set_crtc_vline_interrupt_state(adev, 4, state);
3357                 break;
3358          case AMDGPU_CRTC_IRQ_VLINE6:
3359                 dce_v11_0_set_crtc_vline_interrupt_state(adev, 5, state);
3360                 break;
3361         default:
3362                 break;
3363         }
3364         return 0;
3365 }
3366
3367 static int dce_v11_0_set_pageflip_irq_state(struct amdgpu_device *adev,
3368                                             struct amdgpu_irq_src *src,
3369                                             unsigned type,
3370                                             enum amdgpu_interrupt_state state)
3371 {
3372         u32 reg;
3373
3374         if (type >= adev->mode_info.num_crtc) {
3375                 DRM_ERROR("invalid pageflip crtc %d\n", type);
3376                 return -EINVAL;
3377         }
3378
3379         reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
3380         if (state == AMDGPU_IRQ_STATE_DISABLE)
3381                 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3382                        reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3383         else
3384                 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3385                        reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3386
3387         return 0;
3388 }
3389
3390 static int dce_v11_0_pageflip_irq(struct amdgpu_device *adev,
3391                                   struct amdgpu_irq_src *source,
3392                                   struct amdgpu_iv_entry *entry)
3393 {
3394         unsigned long flags;
3395         unsigned crtc_id;
3396         struct amdgpu_crtc *amdgpu_crtc;
3397         struct amdgpu_flip_work *works;
3398
3399         crtc_id = (entry->src_id - 8) >> 1;
3400         amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
3401
3402         if (crtc_id >= adev->mode_info.num_crtc) {
3403                 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
3404                 return -EINVAL;
3405         }
3406
3407         if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
3408             GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
3409                 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
3410                        GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
3411
3412         /* IRQ could occur when in initial stage */
3413         if(amdgpu_crtc == NULL)
3414                 return 0;
3415
3416         spin_lock_irqsave(&adev->ddev->event_lock, flags);
3417         works = amdgpu_crtc->pflip_works;
3418         if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
3419                 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
3420                                                  "AMDGPU_FLIP_SUBMITTED(%d)\n",
3421                                                  amdgpu_crtc->pflip_status,
3422                                                  AMDGPU_FLIP_SUBMITTED);
3423                 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3424                 return 0;
3425         }
3426
3427         /* page flip completed. clean up */
3428         amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
3429         amdgpu_crtc->pflip_works = NULL;
3430
3431         /* wakeup usersapce */
3432         if(works->event)
3433                 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);
3434
3435         spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3436
3437         drm_crtc_vblank_put(&amdgpu_crtc->base);
3438         schedule_work(&works->unpin_work);
3439
3440         return 0;
3441 }
3442
3443 static void dce_v11_0_hpd_int_ack(struct amdgpu_device *adev,
3444                                   int hpd)
3445 {
3446         u32 tmp;
3447
3448         if (hpd >= adev->mode_info.num_hpd) {
3449                 DRM_DEBUG("invalid hdp %d\n", hpd);
3450                 return;
3451         }
3452
3453         tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3454         tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1);
3455         WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3456 }
3457
3458 static void dce_v11_0_crtc_vblank_int_ack(struct amdgpu_device *adev,
3459                                           int crtc)
3460 {
3461         u32 tmp;
3462
3463         if (crtc < 0 || crtc >= adev->mode_info.num_crtc) {
3464                 DRM_DEBUG("invalid crtc %d\n", crtc);
3465                 return;
3466         }
3467
3468         tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]);
3469         tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1);
3470         WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp);
3471 }
3472
3473 static void dce_v11_0_crtc_vline_int_ack(struct amdgpu_device *adev,
3474                                          int crtc)
3475 {
3476         u32 tmp;
3477
3478         if (crtc < 0 || crtc >= adev->mode_info.num_crtc) {
3479                 DRM_DEBUG("invalid crtc %d\n", crtc);
3480                 return;
3481         }
3482
3483         tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]);
3484         tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1);
3485         WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp);
3486 }
3487
3488 static int dce_v11_0_crtc_irq(struct amdgpu_device *adev,
3489                                 struct amdgpu_irq_src *source,
3490                                 struct amdgpu_iv_entry *entry)
3491 {
3492         unsigned crtc = entry->src_id - 1;
3493         uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
3494         unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc);
3495
3496         switch (entry->src_data) {
3497         case 0: /* vblank */
3498                 if (disp_int & interrupt_status_offsets[crtc].vblank)
3499                         dce_v11_0_crtc_vblank_int_ack(adev, crtc);
3500                 else
3501                         DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3502
3503                 if (amdgpu_irq_enabled(adev, source, irq_type)) {
3504                         drm_handle_vblank(adev->ddev, crtc);
3505                 }
3506                 DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
3507
3508                 break;
3509         case 1: /* vline */
3510                 if (disp_int & interrupt_status_offsets[crtc].vline)
3511                         dce_v11_0_crtc_vline_int_ack(adev, crtc);
3512                 else
3513                         DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3514
3515                 DRM_DEBUG("IH: D%d vline\n", crtc + 1);
3516
3517                 break;
3518         default:
3519                 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
3520                 break;
3521         }
3522
3523         return 0;
3524 }
3525
3526 static int dce_v11_0_hpd_irq(struct amdgpu_device *adev,
3527                              struct amdgpu_irq_src *source,
3528                              struct amdgpu_iv_entry *entry)
3529 {
3530         uint32_t disp_int, mask;
3531         unsigned hpd;
3532
3533         if (entry->src_data >= adev->mode_info.num_hpd) {
3534                 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
3535                 return 0;
3536         }
3537
3538         hpd = entry->src_data;
3539         disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3540         mask = interrupt_status_offsets[hpd].hpd;
3541
3542         if (disp_int & mask) {
3543                 dce_v11_0_hpd_int_ack(adev, hpd);
3544                 schedule_work(&adev->hotplug_work);
3545                 DRM_DEBUG("IH: HPD%d\n", hpd + 1);
3546         }
3547
3548         return 0;
3549 }
3550
3551 static int dce_v11_0_set_clockgating_state(void *handle,
3552                                           enum amd_clockgating_state state)
3553 {
3554         return 0;
3555 }
3556
3557 static int dce_v11_0_set_powergating_state(void *handle,
3558                                           enum amd_powergating_state state)
3559 {
3560         return 0;
3561 }
3562
3563 const struct amd_ip_funcs dce_v11_0_ip_funcs = {
3564         .name = "dce_v11_0",
3565         .early_init = dce_v11_0_early_init,
3566         .late_init = NULL,
3567         .sw_init = dce_v11_0_sw_init,
3568         .sw_fini = dce_v11_0_sw_fini,
3569         .hw_init = dce_v11_0_hw_init,
3570         .hw_fini = dce_v11_0_hw_fini,
3571         .suspend = dce_v11_0_suspend,
3572         .resume = dce_v11_0_resume,
3573         .is_idle = dce_v11_0_is_idle,
3574         .wait_for_idle = dce_v11_0_wait_for_idle,
3575         .soft_reset = dce_v11_0_soft_reset,
3576         .set_clockgating_state = dce_v11_0_set_clockgating_state,
3577         .set_powergating_state = dce_v11_0_set_powergating_state,
3578 };
3579
3580 static void
3581 dce_v11_0_encoder_mode_set(struct drm_encoder *encoder,
3582                           struct drm_display_mode *mode,
3583                           struct drm_display_mode *adjusted_mode)
3584 {
3585         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3586
3587         amdgpu_encoder->pixel_clock = adjusted_mode->clock;
3588
3589         /* need to call this here rather than in prepare() since we need some crtc info */
3590         amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3591
3592         /* set scaler clears this on some chips */
3593         dce_v11_0_set_interleave(encoder->crtc, mode);
3594
3595         if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
3596                 dce_v11_0_afmt_enable(encoder, true);
3597                 dce_v11_0_afmt_setmode(encoder, adjusted_mode);
3598         }
3599 }
3600
3601 static void dce_v11_0_encoder_prepare(struct drm_encoder *encoder)
3602 {
3603         struct amdgpu_device *adev = encoder->dev->dev_private;
3604         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3605         struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
3606
3607         if ((amdgpu_encoder->active_device &
3608              (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
3609             (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
3610              ENCODER_OBJECT_ID_NONE)) {
3611                 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
3612                 if (dig) {
3613                         dig->dig_encoder = dce_v11_0_pick_dig_encoder(encoder);
3614                         if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT)
3615                                 dig->afmt = adev->mode_info.afmt[dig->dig_encoder];
3616                 }
3617         }
3618
3619         amdgpu_atombios_scratch_regs_lock(adev, true);
3620
3621         if (connector) {
3622                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
3623
3624                 /* select the clock/data port if it uses a router */
3625                 if (amdgpu_connector->router.cd_valid)
3626                         amdgpu_i2c_router_select_cd_port(amdgpu_connector);
3627
3628                 /* turn eDP panel on for mode set */
3629                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3630                         amdgpu_atombios_encoder_set_edp_panel_power(connector,
3631                                                              ATOM_TRANSMITTER_ACTION_POWER_ON);
3632         }
3633
3634         /* this is needed for the pll/ss setup to work correctly in some cases */
3635         amdgpu_atombios_encoder_set_crtc_source(encoder);
3636         /* set up the FMT blocks */
3637         dce_v11_0_program_fmt(encoder);
3638 }
3639
3640 static void dce_v11_0_encoder_commit(struct drm_encoder *encoder)
3641 {
3642         struct drm_device *dev = encoder->dev;
3643         struct amdgpu_device *adev = dev->dev_private;
3644
3645         /* need to call this here as we need the crtc set up */
3646         amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
3647         amdgpu_atombios_scratch_regs_lock(adev, false);
3648 }
3649
3650 static void dce_v11_0_encoder_disable(struct drm_encoder *encoder)
3651 {
3652         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3653         struct amdgpu_encoder_atom_dig *dig;
3654
3655         amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3656
3657         if (amdgpu_atombios_encoder_is_digital(encoder)) {
3658                 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
3659                         dce_v11_0_afmt_enable(encoder, false);
3660                 dig = amdgpu_encoder->enc_priv;
3661                 dig->dig_encoder = -1;
3662         }
3663         amdgpu_encoder->active_device = 0;
3664 }
3665
3666 /* these are handled by the primary encoders */
3667 static void dce_v11_0_ext_prepare(struct drm_encoder *encoder)
3668 {
3669
3670 }
3671
3672 static void dce_v11_0_ext_commit(struct drm_encoder *encoder)
3673 {
3674
3675 }
3676
3677 static void
3678 dce_v11_0_ext_mode_set(struct drm_encoder *encoder,
3679                       struct drm_display_mode *mode,
3680                       struct drm_display_mode *adjusted_mode)
3681 {
3682
3683 }
3684
3685 static void dce_v11_0_ext_disable(struct drm_encoder *encoder)
3686 {
3687
3688 }
3689
3690 static void
3691 dce_v11_0_ext_dpms(struct drm_encoder *encoder, int mode)
3692 {
3693
3694 }
3695
3696 static const struct drm_encoder_helper_funcs dce_v11_0_ext_helper_funcs = {
3697         .dpms = dce_v11_0_ext_dpms,
3698         .prepare = dce_v11_0_ext_prepare,
3699         .mode_set = dce_v11_0_ext_mode_set,
3700         .commit = dce_v11_0_ext_commit,
3701         .disable = dce_v11_0_ext_disable,
3702         /* no detect for TMDS/LVDS yet */
3703 };
3704
3705 static const struct drm_encoder_helper_funcs dce_v11_0_dig_helper_funcs = {
3706         .dpms = amdgpu_atombios_encoder_dpms,
3707         .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3708         .prepare = dce_v11_0_encoder_prepare,
3709         .mode_set = dce_v11_0_encoder_mode_set,
3710         .commit = dce_v11_0_encoder_commit,
3711         .disable = dce_v11_0_encoder_disable,
3712         .detect = amdgpu_atombios_encoder_dig_detect,
3713 };
3714
3715 static const struct drm_encoder_helper_funcs dce_v11_0_dac_helper_funcs = {
3716         .dpms = amdgpu_atombios_encoder_dpms,
3717         .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3718         .prepare = dce_v11_0_encoder_prepare,
3719         .mode_set = dce_v11_0_encoder_mode_set,
3720         .commit = dce_v11_0_encoder_commit,
3721         .detect = amdgpu_atombios_encoder_dac_detect,
3722 };
3723
3724 static void dce_v11_0_encoder_destroy(struct drm_encoder *encoder)
3725 {
3726         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3727         if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3728                 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder);
3729         kfree(amdgpu_encoder->enc_priv);
3730         drm_encoder_cleanup(encoder);
3731         kfree(amdgpu_encoder);
3732 }
3733
3734 static const struct drm_encoder_funcs dce_v11_0_encoder_funcs = {
3735         .destroy = dce_v11_0_encoder_destroy,
3736 };
3737
3738 static void dce_v11_0_encoder_add(struct amdgpu_device *adev,
3739                                  uint32_t encoder_enum,
3740                                  uint32_t supported_device,
3741                                  u16 caps)
3742 {
3743         struct drm_device *dev = adev->ddev;
3744         struct drm_encoder *encoder;
3745         struct amdgpu_encoder *amdgpu_encoder;
3746
3747         /* see if we already added it */
3748         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3749                 amdgpu_encoder = to_amdgpu_encoder(encoder);
3750                 if (amdgpu_encoder->encoder_enum == encoder_enum) {
3751                         amdgpu_encoder->devices |= supported_device;
3752                         return;
3753                 }
3754
3755         }
3756
3757         /* add a new one */
3758         amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL);
3759         if (!amdgpu_encoder)
3760                 return;
3761
3762         encoder = &amdgpu_encoder->base;
3763         switch (adev->mode_info.num_crtc) {
3764         case 1:
3765                 encoder->possible_crtcs = 0x1;
3766                 break;
3767         case 2:
3768         default:
3769                 encoder->possible_crtcs = 0x3;
3770                 break;
3771         case 4:
3772                 encoder->possible_crtcs = 0xf;
3773                 break;
3774         case 6:
3775                 encoder->possible_crtcs = 0x3f;
3776                 break;
3777         }
3778
3779         amdgpu_encoder->enc_priv = NULL;
3780
3781         amdgpu_encoder->encoder_enum = encoder_enum;
3782         amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
3783         amdgpu_encoder->devices = supported_device;
3784         amdgpu_encoder->rmx_type = RMX_OFF;
3785         amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
3786         amdgpu_encoder->is_ext_encoder = false;
3787         amdgpu_encoder->caps = caps;
3788
3789         switch (amdgpu_encoder->encoder_id) {
3790         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
3791         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
3792                 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3793                                  DRM_MODE_ENCODER_DAC, NULL);
3794                 drm_encoder_helper_add(encoder, &dce_v11_0_dac_helper_funcs);
3795                 break;
3796         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
3797         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
3798         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
3799         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
3800         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3801                 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3802                         amdgpu_encoder->rmx_type = RMX_FULL;
3803                         drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3804                                          DRM_MODE_ENCODER_LVDS, NULL);
3805                         amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
3806                 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3807                         drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3808                                          DRM_MODE_ENCODER_DAC, NULL);
3809                         amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3810                 } else {
3811                         drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3812                                          DRM_MODE_ENCODER_TMDS, NULL);
3813                         amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3814                 }
3815                 drm_encoder_helper_add(encoder, &dce_v11_0_dig_helper_funcs);
3816                 break;
3817         case ENCODER_OBJECT_ID_SI170B:
3818         case ENCODER_OBJECT_ID_CH7303:
3819         case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
3820         case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
3821         case ENCODER_OBJECT_ID_TITFP513:
3822         case ENCODER_OBJECT_ID_VT1623:
3823         case ENCODER_OBJECT_ID_HDMI_SI1930:
3824         case ENCODER_OBJECT_ID_TRAVIS:
3825         case ENCODER_OBJECT_ID_NUTMEG:
3826                 /* these are handled by the primary encoders */
3827                 amdgpu_encoder->is_ext_encoder = true;
3828                 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3829                         drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3830                                          DRM_MODE_ENCODER_LVDS, NULL);
3831                 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
3832                         drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3833                                          DRM_MODE_ENCODER_DAC, NULL);
3834                 else
3835                         drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3836                                          DRM_MODE_ENCODER_TMDS, NULL);
3837                 drm_encoder_helper_add(encoder, &dce_v11_0_ext_helper_funcs);
3838                 break;
3839         }
3840 }
3841
3842 static const struct amdgpu_display_funcs dce_v11_0_display_funcs = {
3843         .set_vga_render_state = &dce_v11_0_set_vga_render_state,
3844         .bandwidth_update = &dce_v11_0_bandwidth_update,
3845         .vblank_get_counter = &dce_v11_0_vblank_get_counter,
3846         .vblank_wait = &dce_v11_0_vblank_wait,
3847         .is_display_hung = &dce_v11_0_is_display_hung,
3848         .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
3849         .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
3850         .hpd_sense = &dce_v11_0_hpd_sense,
3851         .hpd_set_polarity = &dce_v11_0_hpd_set_polarity,
3852         .hpd_get_gpio_reg = &dce_v11_0_hpd_get_gpio_reg,
3853         .page_flip = &dce_v11_0_page_flip,
3854         .page_flip_get_scanoutpos = &dce_v11_0_crtc_get_scanoutpos,
3855         .add_encoder = &dce_v11_0_encoder_add,
3856         .add_connector = &amdgpu_connector_add,
3857         .stop_mc_access = &dce_v11_0_stop_mc_access,
3858         .resume_mc_access = &dce_v11_0_resume_mc_access,
3859 };
3860
3861 static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev)
3862 {
3863         if (adev->mode_info.funcs == NULL)
3864                 adev->mode_info.funcs = &dce_v11_0_display_funcs;
3865 }
3866
3867 static const struct amdgpu_irq_src_funcs dce_v11_0_crtc_irq_funcs = {
3868         .set = dce_v11_0_set_crtc_irq_state,
3869         .process = dce_v11_0_crtc_irq,
3870 };
3871
3872 static const struct amdgpu_irq_src_funcs dce_v11_0_pageflip_irq_funcs = {
3873         .set = dce_v11_0_set_pageflip_irq_state,
3874         .process = dce_v11_0_pageflip_irq,
3875 };
3876
3877 static const struct amdgpu_irq_src_funcs dce_v11_0_hpd_irq_funcs = {
3878         .set = dce_v11_0_set_hpd_irq_state,
3879         .process = dce_v11_0_hpd_irq,
3880 };
3881
3882 static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev)
3883 {
3884         adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST;
3885         adev->crtc_irq.funcs = &dce_v11_0_crtc_irq_funcs;
3886
3887         adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST;
3888         adev->pageflip_irq.funcs = &dce_v11_0_pageflip_irq_funcs;
3889
3890         adev->hpd_irq.num_types = AMDGPU_HPD_LAST;
3891         adev->hpd_irq.funcs = &dce_v11_0_hpd_irq_funcs;
3892 }