drivers/gpu/drm/amd/amdgpu/dce_virtual.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <drm/drmP.h>
  24 #include "amdgpu.h"
  25 #include "amdgpu_pm.h"
  26 #include "amdgpu_i2c.h"
  27 #include "atom.h"
  28 #include "amdgpu_pll.h"
  29 #include "amdgpu_connectors.h"
  30 #ifdef CONFIG_DRM_AMDGPU_SI
  31 #include "dce_v6_0.h"
  32 #endif
  33 #ifdef CONFIG_DRM_AMDGPU_CIK
  34 #include "dce_v8_0.h"
  35 #endif
  36 #include "dce_v10_0.h"
  37 #include "dce_v11_0.h"
  38 #include "dce_virtual.h"
  39
  40 #define DCE_VIRTUAL_VBLANK_PERIOD 16666666
  41
  42
  43 static void dce_virtual_set_display_funcs(struct amdgpu_device *adev);
  44 static void dce_virtual_set_irq_funcs(struct amdgpu_device *adev);
  45 static int dce_virtual_connector_encoder_init(struct amdgpu_device *adev,
  46                                               int index);
  47
  48 /**
  49  * dce_virtual_vblank_wait - vblank wait asic callback.
  50  *
  51  * @adev: amdgpu_device pointer
  52  * @crtc: crtc to wait for vblank on
  53  *
  54  * Wait for vblank on the requested crtc (evergreen+).
  55  */
  56 static void dce_virtual_vblank_wait(struct amdgpu_device *adev, int crtc)
  57 {
  58         return;
  59 }
  60
  61 static u32 dce_virtual_vblank_get_counter(struct amdgpu_device *adev, int crtc)
  62 {
  63         return 0;
  64 }
  65
  66 static void dce_virtual_page_flip(struct amdgpu_device *adev,
  67                               int crtc_id, u64 crtc_base, bool async)
  68 {
  69         return;
  70 }
  71
  72 static int dce_virtual_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
  73                                         u32 *vbl, u32 *position)
  74 {
  75         *vbl = 0;
  76         *position = 0;
  77
  78         return -EINVAL;
  79 }
  80
  81 static bool dce_virtual_hpd_sense(struct amdgpu_device *adev,
  82                                enum amdgpu_hpd_id hpd)
  83 {
  84         return true;
  85 }
  86
  87 static void dce_virtual_hpd_set_polarity(struct amdgpu_device *adev,
  88                                       enum amdgpu_hpd_id hpd)
  89 {
  90         return;
  91 }
  92
  93 static u32 dce_virtual_hpd_get_gpio_reg(struct amdgpu_device *adev)
  94 {
  95         return 0;
  96 }
  97
  98 /**
  99  * dce_virtual_bandwidth_update - program display watermarks
 100  *
 101  * @adev: amdgpu_device pointer
 102  *
 103  * Calculate and program the display watermarks and line
 104  * buffer allocation (CIK).
 105  */
 106 static void dce_virtual_bandwidth_update(struct amdgpu_device *adev)
 107 {
 108         return;
 109 }
 110
 111 static int dce_virtual_crtc_gamma_set(struct drm_crtc *crtc, u16 *red,
 112                                       u16 *green, u16 *blue, uint32_t size,
 113                                       struct drm_modeset_acquire_ctx *ctx)
 114 {
 115         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 116         int i;
 117
 118         /* userspace palettes are always correct as is */
 119         for (i = 0; i < size; i++) {
 120                 amdgpu_crtc->lut_r[i] = red[i] >> 6;
 121                 amdgpu_crtc->lut_g[i] = green[i] >> 6;
 122                 amdgpu_crtc->lut_b[i] = blue[i] >> 6;
 123         }
 124
 125         return 0;
 126 }
 127
 128 static void dce_virtual_crtc_destroy(struct drm_crtc *crtc)
 129 {
 130         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 131
 132         drm_crtc_cleanup(crtc);
 133         kfree(amdgpu_crtc);
 134 }
 135
 136 static const struct drm_crtc_funcs dce_virtual_crtc_funcs = {
 137         .cursor_set2 = NULL,
 138         .cursor_move = NULL,
 139         .gamma_set = dce_virtual_crtc_gamma_set,
 140         .set_config = amdgpu_crtc_set_config,
 141         .destroy = dce_virtual_crtc_destroy,
 142         .page_flip_target = amdgpu_crtc_page_flip_target,
 143 };
 144
 145 static void dce_virtual_crtc_dpms(struct drm_crtc *crtc, int mode)
 146 {
 147         struct drm_device *dev = crtc->dev;
 148         struct amdgpu_device *adev = dev->dev_private;
 149         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 150         unsigned type;
 151
 152         if (amdgpu_sriov_vf(adev))
 153                 return;
 154
 155         switch (mode) {
 156         case DRM_MODE_DPMS_ON:
 157                 amdgpu_crtc->enabled = true;
 158                 /* Make sure VBLANK interrupts are still enabled */
 159                 type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id);
 160                 amdgpu_irq_update(adev, &adev->crtc_irq, type);
 161                 drm_crtc_vblank_on(crtc);
 162                 break;
 163         case DRM_MODE_DPMS_STANDBY:
 164         case DRM_MODE_DPMS_SUSPEND:
 165         case DRM_MODE_DPMS_OFF:
 166                 drm_crtc_vblank_off(crtc);
 167                 amdgpu_crtc->enabled = false;
 168                 break;
 169         }
 170 }
 171
 172
 173 static void dce_virtual_crtc_prepare(struct drm_crtc *crtc)
 174 {
 175         dce_virtual_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
 176 }
 177
 178 static void dce_virtual_crtc_commit(struct drm_crtc *crtc)
 179 {
 180         dce_virtual_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
 181 }
 182
 183 static void dce_virtual_crtc_disable(struct drm_crtc *crtc)
 184 {
 185         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 186
 187         dce_virtual_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
 188         if (crtc->primary->fb) {
 189                 int r;
 190                 struct amdgpu_framebuffer *amdgpu_fb;
 191                 struct amdgpu_bo *abo;
 192
 193                 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
 194                 abo = gem_to_amdgpu_bo(amdgpu_fb->obj);
 195                 r = amdgpu_bo_reserve(abo, true);
 196                 if (unlikely(r))
 197                         DRM_ERROR("failed to reserve abo before unpin\n");
 198                 else {
 199                         amdgpu_bo_unpin(abo);
 200                         amdgpu_bo_unreserve(abo);
 201                 }
 202         }
 203
 204         amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
 205         amdgpu_crtc->encoder = NULL;
 206         amdgpu_crtc->connector = NULL;
 207 }
 208
 209 static int dce_virtual_crtc_mode_set(struct drm_crtc *crtc,
 210                                   struct drm_display_mode *mode,
 211                                   struct drm_display_mode *adjusted_mode,
 212                                   int x, int y, struct drm_framebuffer *old_fb)
 213 {
 214         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 215
 216         /* update the hw version fpr dpm */
 217         amdgpu_crtc->hw_mode = *adjusted_mode;
 218
 219         return 0;
 220 }
 221
 222 static bool dce_virtual_crtc_mode_fixup(struct drm_crtc *crtc,
 223                                      const struct drm_display_mode *mode,
 224                                      struct drm_display_mode *adjusted_mode)
 225 {
 226         return true;
 227 }
 228
 229
 230 static int dce_virtual_crtc_set_base(struct drm_crtc *crtc, int x, int y,
 231                                   struct drm_framebuffer *old_fb)
 232 {
 233         return 0;
 234 }
 235
 236 static void dce_virtual_crtc_load_lut(struct drm_crtc *crtc)
 237 {
 238         return;
 239 }
 240
 241 static int dce_virtual_crtc_set_base_atomic(struct drm_crtc *crtc,
 242                                          struct drm_framebuffer *fb,
 243                                          int x, int y, enum mode_set_atomic state)
 244 {
 245         return 0;
 246 }
 247
 248 static const struct drm_crtc_helper_funcs dce_virtual_crtc_helper_funcs = {
 249         .dpms = dce_virtual_crtc_dpms,
 250         .mode_fixup = dce_virtual_crtc_mode_fixup,
 251         .mode_set = dce_virtual_crtc_mode_set,
 252         .mode_set_base = dce_virtual_crtc_set_base,
 253         .mode_set_base_atomic = dce_virtual_crtc_set_base_atomic,
 254         .prepare = dce_virtual_crtc_prepare,
 255         .commit = dce_virtual_crtc_commit,
 256         .load_lut = dce_virtual_crtc_load_lut,
 257         .disable = dce_virtual_crtc_disable,
 258 };
 259
 260 static int dce_virtual_crtc_init(struct amdgpu_device *adev, int index)
 261 {
 262         struct amdgpu_crtc *amdgpu_crtc;
 263         int i;
 264
 265         amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
 266                               (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
 267         if (amdgpu_crtc == NULL)
 268                 return -ENOMEM;
 269
 270         drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_virtual_crtc_funcs);
 271
 272         drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
 273         amdgpu_crtc->crtc_id = index;
 274         adev->mode_info.crtcs[index] = amdgpu_crtc;
 275
 276         for (i = 0; i < 256; i++) {
 277                 amdgpu_crtc->lut_r[i] = i << 2;
 278                 amdgpu_crtc->lut_g[i] = i << 2;
 279                 amdgpu_crtc->lut_b[i] = i << 2;
 280         }
 281
 282         amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
 283         amdgpu_crtc->encoder = NULL;
 284         amdgpu_crtc->connector = NULL;
 285         amdgpu_crtc->vsync_timer_enabled = AMDGPU_IRQ_STATE_DISABLE;
 286         drm_crtc_helper_add(&amdgpu_crtc->base, &dce_virtual_crtc_helper_funcs);
 287
 288         return 0;
 289 }
 290
 291 static int dce_virtual_early_init(void *handle)
 292 {
 293         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 294
 295         dce_virtual_set_display_funcs(adev);
 296         dce_virtual_set_irq_funcs(adev);
 297
 298         adev->mode_info.num_hpd = 1;
 299         adev->mode_info.num_dig = 1;
 300         return 0;
 301 }
 302
 303 static struct drm_encoder *
 304 dce_virtual_encoder(struct drm_connector *connector)
 305 {
 306         int enc_id = connector->encoder_ids[0];
 307         struct drm_encoder *encoder;
 308         int i;
 309
 310         for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
 311                 if (connector->encoder_ids[i] == 0)
 312                         break;
 313
 314                 encoder = drm_encoder_find(connector->dev, connector->encoder_ids[i]);
 315                 if (!encoder)
 316                         continue;
 317
 318                 if (encoder->encoder_type == DRM_MODE_ENCODER_VIRTUAL)
 319                         return encoder;
 320         }
 321
 322         /* pick the first one */
 323         if (enc_id)
 324                 return drm_encoder_find(connector->dev, enc_id);
 325         return NULL;
 326 }
 327
 328 static int dce_virtual_get_modes(struct drm_connector *connector)
 329 {
 330         struct drm_device *dev = connector->dev;
 331         struct drm_display_mode *mode = NULL;
 332         unsigned i;
 333         static const struct mode_size {
 334                 int w;
 335                 int h;
 336         } common_modes[17] = {
 337                 { 640,  480},
 338                 { 720,  480},
 339                 { 800,  600},
 340                 { 848,  480},
 341                 {1024,  768},
 342                 {1152,  768},
 343                 {1280,  720},
 344                 {1280,  800},
 345                 {1280,  854},
 346                 {1280,  960},
 347                 {1280, 1024},
 348                 {1440,  900},
 349                 {1400, 1050},
 350                 {1680, 1050},
 351                 {1600, 1200},
 352                 {1920, 1080},
 353                 {1920, 1200}
 354         };
 355
 356         for (i = 0; i < 17; i++) {
 357                 mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 60, false, false, false);
 358                 drm_mode_probed_add(connector, mode);
 359         }
 360
 361         return 0;
 362 }
 363
 364 static int dce_virtual_mode_valid(struct drm_connector *connector,
 365                                   struct drm_display_mode *mode)
 366 {
 367         return MODE_OK;
 368 }
 369
 370 static int
 371 dce_virtual_dpms(struct drm_connector *connector, int mode)
 372 {
 373         return 0;
 374 }
 375
 376 static int
 377 dce_virtual_set_property(struct drm_connector *connector,
 378                          struct drm_property *property,
 379                          uint64_t val)
 380 {
 381         return 0;
 382 }
 383
 384 static void dce_virtual_destroy(struct drm_connector *connector)
 385 {
 386         drm_connector_unregister(connector);
 387         drm_connector_cleanup(connector);
 388         kfree(connector);
 389 }
 390
 391 static void dce_virtual_force(struct drm_connector *connector)
 392 {
 393         return;
 394 }
 395
 396 static const struct drm_connector_helper_funcs dce_virtual_connector_helper_funcs = {
 397         .get_modes = dce_virtual_get_modes,
 398         .mode_valid = dce_virtual_mode_valid,
 399         .best_encoder = dce_virtual_encoder,
 400 };
 401
 402 static const struct drm_connector_funcs dce_virtual_connector_funcs = {
 403         .dpms = dce_virtual_dpms,
 404         .fill_modes = drm_helper_probe_single_connector_modes,
 405         .set_property = dce_virtual_set_property,
 406         .destroy = dce_virtual_destroy,
 407         .force = dce_virtual_force,
 408 };
 409
 410 static int dce_virtual_sw_init(void *handle)
 411 {
 412         int r, i;
 413         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 414
 415         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 229, &adev->crtc_irq);
 416         if (r)
 417                 return r;
 418
 419         adev->ddev->max_vblank_count = 0;
 420
 421         adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
 422
 423         adev->ddev->mode_config.max_width = 16384;
 424         adev->ddev->mode_config.max_height = 16384;
 425
 426         adev->ddev->mode_config.preferred_depth = 24;
 427         adev->ddev->mode_config.prefer_shadow = 1;
 428
 429         adev->ddev->mode_config.fb_base = adev->mc.aper_base;
 430
 431         r = amdgpu_modeset_create_props(adev);
 432         if (r)
 433                 return r;
 434
 435         adev->ddev->mode_config.max_width = 16384;
 436         adev->ddev->mode_config.max_height = 16384;
 437
 438         /* allocate crtcs, encoders, connectors */
 439         for (i = 0; i < adev->mode_info.num_crtc; i++) {
 440                 r = dce_virtual_crtc_init(adev, i);
 441                 if (r)
 442                         return r;
 443                 r = dce_virtual_connector_encoder_init(adev, i);
 444                 if (r)
 445                         return r;
 446         }
 447
 448         drm_kms_helper_poll_init(adev->ddev);
 449
 450         adev->mode_info.mode_config_initialized = true;
 451         return 0;
 452 }
 453
 454 static int dce_virtual_sw_fini(void *handle)
 455 {
 456         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 457
 458         kfree(adev->mode_info.bios_hardcoded_edid);
 459
 460         drm_kms_helper_poll_fini(adev->ddev);
 461
 462         drm_mode_config_cleanup(adev->ddev);
 463         adev->mode_info.mode_config_initialized = false;
 464         return 0;
 465 }
 466
 467 static int dce_virtual_hw_init(void *handle)
 468 {
 469         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 470
 471         switch (adev->asic_type) {
 472 #ifdef CONFIG_DRM_AMDGPU_SI
 473         case CHIP_TAHITI:
 474         case CHIP_PITCAIRN:
 475         case CHIP_VERDE:
 476         case CHIP_OLAND:
 477                 dce_v6_0_disable_dce(adev);
 478                 break;
 479 #endif
 480 #ifdef CONFIG_DRM_AMDGPU_CIK
 481         case CHIP_BONAIRE:
 482         case CHIP_HAWAII:
 483         case CHIP_KAVERI:
 484         case CHIP_KABINI:
 485         case CHIP_MULLINS:
 486                 dce_v8_0_disable_dce(adev);
 487                 break;
 488 #endif
 489         case CHIP_FIJI:
 490         case CHIP_TONGA:
 491                 dce_v10_0_disable_dce(adev);
 492                 break;
 493         case CHIP_CARRIZO:
 494         case CHIP_STONEY:
 495         case CHIP_POLARIS11:
 496         case CHIP_POLARIS10:
 497                 dce_v11_0_disable_dce(adev);
 498                 break;
 499         case CHIP_TOPAZ:
 500 #ifdef CONFIG_DRM_AMDGPU_SI
 501         case CHIP_HAINAN:
 502 #endif
 503                 /* no DCE */
 504                 break;
 505         default:
 506                 DRM_ERROR("Virtual display unsupported ASIC type: 0x%X\n", adev->asic_type);
 507         }
 508         return 0;
 509 }
 510
 511 static int dce_virtual_hw_fini(void *handle)
 512 {
 513         return 0;
 514 }
 515
 516 static int dce_virtual_suspend(void *handle)
 517 {
 518         return dce_virtual_hw_fini(handle);
 519 }
 520
 521 static int dce_virtual_resume(void *handle)
 522 {
 523         return dce_virtual_hw_init(handle);
 524 }
 525
 526 static bool dce_virtual_is_idle(void *handle)
 527 {
 528         return true;
 529 }
 530
 531 static int dce_virtual_wait_for_idle(void *handle)
 532 {
 533         return 0;
 534 }
 535
 536 static int dce_virtual_soft_reset(void *handle)
 537 {
 538         return 0;
 539 }
 540
 541 static int dce_virtual_set_clockgating_state(void *handle,
 542                                           enum amd_clockgating_state state)
 543 {
 544         return 0;
 545 }
 546
 547 static int dce_virtual_set_powergating_state(void *handle,
 548                                           enum amd_powergating_state state)
 549 {
 550         return 0;
 551 }
 552
 553 static const struct amd_ip_funcs dce_virtual_ip_funcs = {
 554         .name = "dce_virtual",
 555         .early_init = dce_virtual_early_init,
 556         .late_init = NULL,
 557         .sw_init = dce_virtual_sw_init,
 558         .sw_fini = dce_virtual_sw_fini,
 559         .hw_init = dce_virtual_hw_init,
 560         .hw_fini = dce_virtual_hw_fini,
 561         .suspend = dce_virtual_suspend,
 562         .resume = dce_virtual_resume,
 563         .is_idle = dce_virtual_is_idle,
 564         .wait_for_idle = dce_virtual_wait_for_idle,
 565         .soft_reset = dce_virtual_soft_reset,
 566         .set_clockgating_state = dce_virtual_set_clockgating_state,
 567         .set_powergating_state = dce_virtual_set_powergating_state,
 568 };
 569
 570 /* these are handled by the primary encoders */
 571 static void dce_virtual_encoder_prepare(struct drm_encoder *encoder)
 572 {
 573         return;
 574 }
 575
 576 static void dce_virtual_encoder_commit(struct drm_encoder *encoder)
 577 {
 578         return;
 579 }
 580
 581 static void
 582 dce_virtual_encoder_mode_set(struct drm_encoder *encoder,
 583                              struct drm_display_mode *mode,
 584                              struct drm_display_mode *adjusted_mode)
 585 {
 586         return;
 587 }
 588
 589 static void dce_virtual_encoder_disable(struct drm_encoder *encoder)
 590 {
 591         return;
 592 }
 593
 594 static void
 595 dce_virtual_encoder_dpms(struct drm_encoder *encoder, int mode)
 596 {
 597         return;
 598 }
 599
 600 static bool dce_virtual_encoder_mode_fixup(struct drm_encoder *encoder,
 601                                     const struct drm_display_mode *mode,
 602                                     struct drm_display_mode *adjusted_mode)
 603 {
 604         return true;
 605 }
 606
 607 static const struct drm_encoder_helper_funcs dce_virtual_encoder_helper_funcs = {
 608         .dpms = dce_virtual_encoder_dpms,
 609         .mode_fixup = dce_virtual_encoder_mode_fixup,
 610         .prepare = dce_virtual_encoder_prepare,
 611         .mode_set = dce_virtual_encoder_mode_set,
 612         .commit = dce_virtual_encoder_commit,
 613         .disable = dce_virtual_encoder_disable,
 614 };
 615
 616 static void dce_virtual_encoder_destroy(struct drm_encoder *encoder)
 617 {
 618         drm_encoder_cleanup(encoder);
 619         kfree(encoder);
 620 }
 621
 622 static const struct drm_encoder_funcs dce_virtual_encoder_funcs = {
 623         .destroy = dce_virtual_encoder_destroy,
 624 };
 625
 626 static int dce_virtual_connector_encoder_init(struct amdgpu_device *adev,
 627                                               int index)
 628 {
 629         struct drm_encoder *encoder;
 630         struct drm_connector *connector;
 631
 632         /* add a new encoder */
 633         encoder = kzalloc(sizeof(struct drm_encoder), GFP_KERNEL);
 634         if (!encoder)
 635                 return -ENOMEM;
 636         encoder->possible_crtcs = 1 << index;
 637         drm_encoder_init(adev->ddev, encoder, &dce_virtual_encoder_funcs,
 638                          DRM_MODE_ENCODER_VIRTUAL, NULL);
 639         drm_encoder_helper_add(encoder, &dce_virtual_encoder_helper_funcs);
 640
 641         connector = kzalloc(sizeof(struct drm_connector), GFP_KERNEL);
 642         if (!connector) {
 643                 kfree(encoder);
 644                 return -ENOMEM;
 645         }
 646
 647         /* add a new connector */
 648         drm_connector_init(adev->ddev, connector, &dce_virtual_connector_funcs,
 649                            DRM_MODE_CONNECTOR_VIRTUAL);
 650         drm_connector_helper_add(connector, &dce_virtual_connector_helper_funcs);
 651         connector->display_info.subpixel_order = SubPixelHorizontalRGB;
 652         connector->interlace_allowed = false;
 653         connector->doublescan_allowed = false;
 654         drm_connector_register(connector);
 655
 656         /* link them */
 657         drm_mode_connector_attach_encoder(connector, encoder);
 658
 659         return 0;
 660 }
 661
 662 static const struct amdgpu_display_funcs dce_virtual_display_funcs = {
 663         .bandwidth_update = &dce_virtual_bandwidth_update,
 664         .vblank_get_counter = &dce_virtual_vblank_get_counter,
 665         .vblank_wait = &dce_virtual_vblank_wait,
 666         .backlight_set_level = NULL,
 667         .backlight_get_level = NULL,
 668         .hpd_sense = &dce_virtual_hpd_sense,
 669         .hpd_set_polarity = &dce_virtual_hpd_set_polarity,
 670         .hpd_get_gpio_reg = &dce_virtual_hpd_get_gpio_reg,
 671         .page_flip = &dce_virtual_page_flip,
 672         .page_flip_get_scanoutpos = &dce_virtual_crtc_get_scanoutpos,
 673         .add_encoder = NULL,
 674         .add_connector = NULL,
 675 };
 676
 677 static void dce_virtual_set_display_funcs(struct amdgpu_device *adev)
 678 {
 679         if (adev->mode_info.funcs == NULL)
 680                 adev->mode_info.funcs = &dce_virtual_display_funcs;
 681 }
 682
 683 static int dce_virtual_pageflip(struct amdgpu_device *adev,
 684                                 unsigned crtc_id)
 685 {
 686         unsigned long flags;
 687         struct amdgpu_crtc *amdgpu_crtc;
 688         struct amdgpu_flip_work *works;
 689
 690         amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
 691
 692         if (crtc_id >= adev->mode_info.num_crtc) {
 693                 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
 694                 return -EINVAL;
 695         }
 696
 697         /* IRQ could occur when in initial stage */
 698         if (amdgpu_crtc == NULL)
 699                 return 0;
 700
 701         spin_lock_irqsave(&adev->ddev->event_lock, flags);
 702         works = amdgpu_crtc->pflip_works;
 703         if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) {
 704                 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
 705                         "AMDGPU_FLIP_SUBMITTED(%d)\n",
 706                         amdgpu_crtc->pflip_status,
 707                         AMDGPU_FLIP_SUBMITTED);
 708                 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
 709                 return 0;
 710         }
 711
 712         /* page flip completed. clean up */
 713         amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
 714         amdgpu_crtc->pflip_works = NULL;
 715
 716         /* wakeup usersapce */
 717         if (works->event)
 718                 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);
 719
 720         spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
 721
 722         drm_crtc_vblank_put(&amdgpu_crtc->base);
 723         schedule_work(&works->unpin_work);
 724
 725         return 0;
 726 }
 727
 728 static enum hrtimer_restart dce_virtual_vblank_timer_handle(struct hrtimer *vblank_timer)
 729 {
 730         struct amdgpu_crtc *amdgpu_crtc = container_of(vblank_timer,
 731                                                        struct amdgpu_crtc, vblank_timer);
 732         struct drm_device *ddev = amdgpu_crtc->base.dev;
 733         struct amdgpu_device *adev = ddev->dev_private;
 734
 735         drm_handle_vblank(ddev, amdgpu_crtc->crtc_id);
 736         dce_virtual_pageflip(adev, amdgpu_crtc->crtc_id);
 737         hrtimer_start(vblank_timer, DCE_VIRTUAL_VBLANK_PERIOD,
 738                       HRTIMER_MODE_REL);
 739
 740         return HRTIMER_NORESTART;
 741 }
 742
 743 static void dce_virtual_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
 744                                                         int crtc,
 745                                                         enum amdgpu_interrupt_state state)
 746 {
 747         if (crtc >= adev->mode_info.num_crtc) {
 748                 DRM_DEBUG("invalid crtc %d\n", crtc);
 749                 return;
 750         }
 751
 752         if (state && !adev->mode_info.crtcs[crtc]->vsync_timer_enabled) {
 753                 DRM_DEBUG("Enable software vsync timer\n");
 754                 hrtimer_init(&adev->mode_info.crtcs[crtc]->vblank_timer,
 755                              CLOCK_MONOTONIC, HRTIMER_MODE_REL);
 756                 hrtimer_set_expires(&adev->mode_info.crtcs[crtc]->vblank_timer,
 757                                     DCE_VIRTUAL_VBLANK_PERIOD);
 758                 adev->mode_info.crtcs[crtc]->vblank_timer.function =
 759                         dce_virtual_vblank_timer_handle;
 760                 hrtimer_start(&adev->mode_info.crtcs[crtc]->vblank_timer,
 761                               DCE_VIRTUAL_VBLANK_PERIOD, HRTIMER_MODE_REL);
 762         } else if (!state && adev->mode_info.crtcs[crtc]->vsync_timer_enabled) {
 763                 DRM_DEBUG("Disable software vsync timer\n");
 764                 hrtimer_cancel(&adev->mode_info.crtcs[crtc]->vblank_timer);
 765         }
 766
 767         adev->mode_info.crtcs[crtc]->vsync_timer_enabled = state;
 768         DRM_DEBUG("[FM]set crtc %d vblank interrupt state %d\n", crtc, state);
 769 }
 770
 771
 772 static int dce_virtual_set_crtc_irq_state(struct amdgpu_device *adev,
 773                                           struct amdgpu_irq_src *source,
 774                                           unsigned type,
 775                                           enum amdgpu_interrupt_state state)
 776 {
 777         if (type > AMDGPU_CRTC_IRQ_VBLANK6)
 778                 return -EINVAL;
 779
 780         dce_virtual_set_crtc_vblank_interrupt_state(adev, type, state);
 781
 782         return 0;
 783 }
 784
 785 static const struct amdgpu_irq_src_funcs dce_virtual_crtc_irq_funcs = {
 786         .set = dce_virtual_set_crtc_irq_state,
 787         .process = NULL,
 788 };
 789
 790 static void dce_virtual_set_irq_funcs(struct amdgpu_device *adev)
 791 {
 792         adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VBLANK6 + 1;
 793         adev->crtc_irq.funcs = &dce_virtual_crtc_irq_funcs;
 794 }
 795
 796 const struct amdgpu_ip_block_version dce_virtual_ip_block =
 797 {
 798         .type = AMD_IP_BLOCK_TYPE_DCE,
 799         .major = 1,
 800         .minor = 0,
 801         .rev = 0,
 802         .funcs = &dce_virtual_ip_funcs,
 803 };