drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include <linux/pci.h>
  25
  26 #include <drm/drm_cache.h>
  27
  28 #include "amdgpu.h"
  29 #include "amdgpu_atomfirmware.h"
  30 #include "gmc_v10_0.h"
  31 #include "umc_v8_7.h"
  32
  33 #include "athub/athub_2_0_0_sh_mask.h"
  34 #include "athub/athub_2_0_0_offset.h"
  35 #include "dcn/dcn_2_0_0_offset.h"
  36 #include "dcn/dcn_2_0_0_sh_mask.h"
  37 #include "oss/osssys_5_0_0_offset.h"
  38 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h"
  39 #include "navi10_enum.h"
  40
  41 #include "soc15.h"
  42 #include "soc15d.h"
  43 #include "soc15_common.h"
  44
  45 #include "nbio_v2_3.h"
  46
  47 #include "gfxhub_v2_0.h"
  48 #include "gfxhub_v2_1.h"
  49 #include "mmhub_v2_0.h"
  50 #include "mmhub_v2_3.h"
  51 #include "athub_v2_0.h"
  52 #include "athub_v2_1.h"
  53
  54 #include "amdgpu_reset.h"
  55
  56 #if 0
  57 static const struct soc15_reg_golden golden_settings_navi10_hdp[] =
  58 {
  59         /* TODO add golden setting for hdp */
  60 };
  61 #endif
  62
  63 static int gmc_v10_0_ecc_interrupt_state(struct amdgpu_device *adev,
  64                                          struct amdgpu_irq_src *src,
  65                                          unsigned type,
  66                                          enum amdgpu_interrupt_state state)
  67 {
  68         return 0;
  69 }
  70
  71 static int
  72 gmc_v10_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
  73                                    struct amdgpu_irq_src *src, unsigned type,
  74                                    enum amdgpu_interrupt_state state)
  75 {
  76         switch (state) {
  77         case AMDGPU_IRQ_STATE_DISABLE:
  78                 /* MM HUB */
  79                 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB_0, false);
  80                 /* GFX HUB */
  81                 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB_0, false);
  82                 break;
  83         case AMDGPU_IRQ_STATE_ENABLE:
  84                 /* MM HUB */
  85                 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB_0, true);
  86                 /* GFX HUB */
  87                 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB_0, true);
  88                 break;
  89         default:
  90                 break;
  91         }
  92
  93         return 0;
  94 }
  95
  96 static int gmc_v10_0_process_interrupt(struct amdgpu_device *adev,
  97                                        struct amdgpu_irq_src *source,
  98                                        struct amdgpu_iv_entry *entry)
  99 {
 100         bool retry_fault = !!(entry->src_data[1] & 0x80);
 101         bool write_fault = !!(entry->src_data[1] & 0x20);
 102         struct amdgpu_vmhub *hub = &adev->vmhub[entry->vmid_src];
 103         struct amdgpu_task_info task_info;
 104         uint32_t status = 0;
 105         u64 addr;
 106
 107         addr = (u64)entry->src_data[0] << 12;
 108         addr |= ((u64)entry->src_data[1] & 0xf) << 44;
 109
 110         if (retry_fault) {
 111                 /* Returning 1 here also prevents sending the IV to the KFD */
 112
 113                 /* Process it onyl if it's the first fault for this address */
 114                 if (entry->ih != &adev->irq.ih_soft &&
 115                     amdgpu_gmc_filter_faults(adev, entry->ih, addr, entry->pasid,
 116                                              entry->timestamp))
 117                         return 1;
 118
 119                 /* Delegate it to a different ring if the hardware hasn't
 120                  * already done it.
 121                  */
 122                 if (entry->ih == &adev->irq.ih) {
 123                         amdgpu_irq_delegate(adev, entry, 8);
 124                         return 1;
 125                 }
 126
 127                 /* Try to handle the recoverable page faults by filling page
 128                  * tables
 129                  */
 130                 if (amdgpu_vm_handle_fault(adev, entry->pasid, addr, write_fault))
 131                         return 1;
 132         }
 133
 134         if (!amdgpu_sriov_vf(adev)) {
 135                 /*
 136                  * Issue a dummy read to wait for the status register to
 137                  * be updated to avoid reading an incorrect value due to
 138                  * the new fast GRBM interface.
 139                  */
 140                 if ((entry->vmid_src == AMDGPU_GFXHUB_0) &&
 141                     (adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 3, 0)))
 142                         RREG32(hub->vm_l2_pro_fault_status);
 143
 144                 status = RREG32(hub->vm_l2_pro_fault_status);
 145                 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1);
 146         }
 147
 148         if (!printk_ratelimit())
 149                 return 0;
 150
 151         memset(&task_info, 0, sizeof(struct amdgpu_task_info));
 152         amdgpu_vm_get_task_info(adev, entry->pasid, &task_info);
 153
 154         dev_err(adev->dev,
 155                 "[%s] page fault (src_id:%u ring:%u vmid:%u pasid:%u, "
 156                 "for process %s pid %d thread %s pid %d)\n",
 157                 entry->vmid_src ? "mmhub" : "gfxhub",
 158                 entry->src_id, entry->ring_id, entry->vmid,
 159                 entry->pasid, task_info.process_name, task_info.tgid,
 160                 task_info.task_name, task_info.pid);
 161         dev_err(adev->dev, "  in page starting at address 0x%016llx from client 0x%x (%s)\n",
 162                 addr, entry->client_id,
 163                 soc15_ih_clientid_name[entry->client_id]);
 164
 165         if (!amdgpu_sriov_vf(adev))
 166                 hub->vmhub_funcs->print_l2_protection_fault_status(adev,
 167                                                                    status);
 168
 169         return 0;
 170 }
 171
 172 static const struct amdgpu_irq_src_funcs gmc_v10_0_irq_funcs = {
 173         .set = gmc_v10_0_vm_fault_interrupt_state,
 174         .process = gmc_v10_0_process_interrupt,
 175 };
 176
 177 static const struct amdgpu_irq_src_funcs gmc_v10_0_ecc_funcs = {
 178         .set = gmc_v10_0_ecc_interrupt_state,
 179         .process = amdgpu_umc_process_ecc_irq,
 180 };
 181
 182 static void gmc_v10_0_set_irq_funcs(struct amdgpu_device *adev)
 183 {
 184         adev->gmc.vm_fault.num_types = 1;
 185         adev->gmc.vm_fault.funcs = &gmc_v10_0_irq_funcs;
 186
 187         if (!amdgpu_sriov_vf(adev)) {
 188                 adev->gmc.ecc_irq.num_types = 1;
 189                 adev->gmc.ecc_irq.funcs = &gmc_v10_0_ecc_funcs;
 190         }
 191 }
 192
 193 /**
 194  * gmc_v10_0_use_invalidate_semaphore - judge whether to use semaphore
 195  *
 196  * @adev: amdgpu_device pointer
 197  * @vmhub: vmhub type
 198  *
 199  */
 200 static bool gmc_v10_0_use_invalidate_semaphore(struct amdgpu_device *adev,
 201                                        uint32_t vmhub)
 202 {
 203         return ((vmhub == AMDGPU_MMHUB_0 ||
 204                  vmhub == AMDGPU_MMHUB_1) &&
 205                 (!amdgpu_sriov_vf(adev)));
 206 }
 207
 208 static bool gmc_v10_0_get_atc_vmid_pasid_mapping_info(
 209                                         struct amdgpu_device *adev,
 210                                         uint8_t vmid, uint16_t *p_pasid)
 211 {
 212         uint32_t value;
 213
 214         value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)
 215                      + vmid);
 216         *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK;
 217
 218         return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK);
 219 }
 220
 221 /*
 222  * GART
 223  * VMID 0 is the physical GPU addresses as used by the kernel.
 224  * VMIDs 1-15 are used for userspace clients and are handled
 225  * by the amdgpu vm/hsa code.
 226  */
 227
 228 static void gmc_v10_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid,
 229                                    unsigned int vmhub, uint32_t flush_type)
 230 {
 231         bool use_semaphore = gmc_v10_0_use_invalidate_semaphore(adev, vmhub);
 232         struct amdgpu_vmhub *hub = &adev->vmhub[vmhub];
 233         u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type);
 234         u32 tmp;
 235         /* Use register 17 for GART */
 236         const unsigned eng = 17;
 237         unsigned int i;
 238         unsigned char hub_ip = 0;
 239
 240         hub_ip = (vmhub == AMDGPU_GFXHUB_0) ?
 241                    GC_HWIP : MMHUB_HWIP;
 242
 243         spin_lock(&adev->gmc.invalidate_lock);
 244         /*
 245          * It may lose gpuvm invalidate acknowldege state across power-gating
 246          * off cycle, add semaphore acquire before invalidation and semaphore
 247          * release after invalidation to avoid entering power gated state
 248          * to WA the Issue
 249          */
 250
 251         /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
 252         if (use_semaphore) {
 253                 for (i = 0; i < adev->usec_timeout; i++) {
 254                         /* a read return value of 1 means semaphore acuqire */
 255                         tmp = RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_sem +
 256                                          hub->eng_distance * eng, hub_ip);
 257
 258                         if (tmp & 0x1)
 259                                 break;
 260                         udelay(1);
 261                 }
 262
 263                 if (i >= adev->usec_timeout)
 264                         DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n");
 265         }
 266
 267         WREG32_RLC_NO_KIQ(hub->vm_inv_eng0_req +
 268                           hub->eng_distance * eng,
 269                           inv_req, hub_ip);
 270
 271         /*
 272          * Issue a dummy read to wait for the ACK register to be cleared
 273          * to avoid a false ACK due to the new fast GRBM interface.
 274          */
 275         if ((vmhub == AMDGPU_GFXHUB_0) &&
 276             (adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 3, 0)))
 277                 RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_req +
 278                                   hub->eng_distance * eng, hub_ip);
 279
 280         /* Wait for ACK with a delay.*/
 281         for (i = 0; i < adev->usec_timeout; i++) {
 282                 tmp = RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_ack +
 283                                   hub->eng_distance * eng, hub_ip);
 284
 285                 tmp &= 1 << vmid;
 286                 if (tmp)
 287                         break;
 288
 289                 udelay(1);
 290         }
 291
 292         /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
 293         if (use_semaphore)
 294                 /*
 295                  * add semaphore release after invalidation,
 296                  * write with 0 means semaphore release
 297                  */
 298                 WREG32_RLC_NO_KIQ(hub->vm_inv_eng0_sem +
 299                                   hub->eng_distance * eng, 0, hub_ip);
 300
 301         spin_unlock(&adev->gmc.invalidate_lock);
 302
 303         if (i < adev->usec_timeout)
 304                 return;
 305
 306         DRM_ERROR("Timeout waiting for VM flush hub: %d!\n", vmhub);
 307 }
 308
 309 /**
 310  * gmc_v10_0_flush_gpu_tlb - gart tlb flush callback
 311  *
 312  * @adev: amdgpu_device pointer
 313  * @vmid: vm instance to flush
 314  * @vmhub: vmhub type
 315  * @flush_type: the flush type
 316  *
 317  * Flush the TLB for the requested page table.
 318  */
 319 static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
 320                                         uint32_t vmhub, uint32_t flush_type)
 321 {
 322         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
 323         struct dma_fence *fence;
 324         struct amdgpu_job *job;
 325
 326         int r;
 327
 328         /* flush hdp cache */
 329         adev->hdp.funcs->flush_hdp(adev, NULL);
 330
 331         /* For SRIOV run time, driver shouldn't access the register through MMIO
 332          * Directly use kiq to do the vm invalidation instead
 333          */
 334         if (adev->gfx.kiq.ring.sched.ready && !adev->enable_mes &&
 335             (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) &&
 336             down_read_trylock(&adev->reset_domain->sem)) {
 337                 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub];
 338                 const unsigned eng = 17;
 339                 u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type);
 340                 u32 req = hub->vm_inv_eng0_req + hub->eng_distance * eng;
 341                 u32 ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng;
 342
 343                 amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, inv_req,
 344                                 1 << vmid);
 345
 346                 up_read(&adev->reset_domain->sem);
 347                 return;
 348         }
 349
 350         mutex_lock(&adev->mman.gtt_window_lock);
 351
 352         if (vmhub == AMDGPU_MMHUB_0) {
 353                 gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_MMHUB_0, 0);
 354                 mutex_unlock(&adev->mman.gtt_window_lock);
 355                 return;
 356         }
 357
 358         BUG_ON(vmhub != AMDGPU_GFXHUB_0);
 359
 360         if (!adev->mman.buffer_funcs_enabled ||
 361             !adev->ib_pool_ready ||
 362             amdgpu_in_reset(adev) ||
 363             ring->sched.ready == false) {
 364                 gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_GFXHUB_0, 0);
 365                 mutex_unlock(&adev->mman.gtt_window_lock);
 366                 return;
 367         }
 368
 369         /* The SDMA on Navi has a bug which can theoretically result in memory
 370          * corruption if an invalidation happens at the same time as an VA
 371          * translation. Avoid this by doing the invalidation from the SDMA
 372          * itself.
 373          */
 374         r = amdgpu_job_alloc_with_ib(ring->adev, &adev->mman.entity,
 375                                      AMDGPU_FENCE_OWNER_UNDEFINED,
 376                                      16 * 4, AMDGPU_IB_POOL_IMMEDIATE,
 377                                      &job);
 378         if (r)
 379                 goto error_alloc;
 380
 381         job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo);
 382         job->vm_needs_flush = true;
 383         job->ibs->ptr[job->ibs->length_dw++] = ring->funcs->nop;
 384         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
 385         fence = amdgpu_job_submit(job);
 386
 387         mutex_unlock(&adev->mman.gtt_window_lock);
 388
 389         dma_fence_wait(fence, false);
 390         dma_fence_put(fence);
 391
 392         return;
 393
 394 error_alloc:
 395         mutex_unlock(&adev->mman.gtt_window_lock);
 396         DRM_ERROR("Error flushing GPU TLB using the SDMA (%d)!\n", r);
 397 }
 398
 399 /**
 400  * gmc_v10_0_flush_gpu_tlb_pasid - tlb flush via pasid
 401  *
 402  * @adev: amdgpu_device pointer
 403  * @pasid: pasid to be flush
 404  * @flush_type: the flush type
 405  * @all_hub: Used with PACKET3_INVALIDATE_TLBS_ALL_HUB()
 406  *
 407  * Flush the TLB for the requested pasid.
 408  */
 409 static int gmc_v10_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
 410                                         uint16_t pasid, uint32_t flush_type,
 411                                         bool all_hub)
 412 {
 413         int vmid, i;
 414         signed long r;
 415         uint32_t seq;
 416         uint16_t queried_pasid;
 417         bool ret;
 418         u32 usec_timeout = amdgpu_sriov_vf(adev) ? SRIOV_USEC_TIMEOUT : adev->usec_timeout;
 419         struct amdgpu_ring *ring = &adev->gfx.kiq.ring;
 420         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
 421
 422         if (amdgpu_emu_mode == 0 && ring->sched.ready) {
 423                 spin_lock(&adev->gfx.kiq.ring_lock);
 424                 /* 2 dwords flush + 8 dwords fence */
 425                 amdgpu_ring_alloc(ring, kiq->pmf->invalidate_tlbs_size + 8);
 426                 kiq->pmf->kiq_invalidate_tlbs(ring,
 427                                         pasid, flush_type, all_hub);
 428                 r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT);
 429                 if (r) {
 430                         amdgpu_ring_undo(ring);
 431                         spin_unlock(&adev->gfx.kiq.ring_lock);
 432                         return -ETIME;
 433                 }
 434
 435                 amdgpu_ring_commit(ring);
 436                 spin_unlock(&adev->gfx.kiq.ring_lock);
 437                 r = amdgpu_fence_wait_polling(ring, seq, usec_timeout);
 438                 if (r < 1) {
 439                         dev_err(adev->dev, "wait for kiq fence error: %ld.\n", r);
 440                         return -ETIME;
 441                 }
 442
 443                 return 0;
 444         }
 445
 446         for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) {
 447
 448                 ret = gmc_v10_0_get_atc_vmid_pasid_mapping_info(adev, vmid,
 449                                 &queried_pasid);
 450                 if (ret && queried_pasid == pasid) {
 451                         if (all_hub) {
 452                                 for (i = 0; i < adev->num_vmhubs; i++)
 453                                         gmc_v10_0_flush_gpu_tlb(adev, vmid,
 454                                                         i, flush_type);
 455                         } else {
 456                                 gmc_v10_0_flush_gpu_tlb(adev, vmid,
 457                                                 AMDGPU_GFXHUB_0, flush_type);
 458                         }
 459                         if (!adev->enable_mes)
 460                                 break;
 461                 }
 462         }
 463
 464         return 0;
 465 }
 466
 467 static uint64_t gmc_v10_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
 468                                              unsigned vmid, uint64_t pd_addr)
 469 {
 470         bool use_semaphore = gmc_v10_0_use_invalidate_semaphore(ring->adev, ring->funcs->vmhub);
 471         struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
 472         uint32_t req = hub->vmhub_funcs->get_invalidate_req(vmid, 0);
 473         unsigned eng = ring->vm_inv_eng;
 474
 475         /*
 476          * It may lose gpuvm invalidate acknowldege state across power-gating
 477          * off cycle, add semaphore acquire before invalidation and semaphore
 478          * release after invalidation to avoid entering power gated state
 479          * to WA the Issue
 480          */
 481
 482         /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
 483         if (use_semaphore)
 484                 /* a read return value of 1 means semaphore acuqire */
 485                 amdgpu_ring_emit_reg_wait(ring,
 486                                           hub->vm_inv_eng0_sem +
 487                                           hub->eng_distance * eng, 0x1, 0x1);
 488
 489         amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 +
 490                               (hub->ctx_addr_distance * vmid),
 491                               lower_32_bits(pd_addr));
 492
 493         amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 +
 494                               (hub->ctx_addr_distance * vmid),
 495                               upper_32_bits(pd_addr));
 496
 497         amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req +
 498                                             hub->eng_distance * eng,
 499                                             hub->vm_inv_eng0_ack +
 500                                             hub->eng_distance * eng,
 501                                             req, 1 << vmid);
 502
 503         /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
 504         if (use_semaphore)
 505                 /*
 506                  * add semaphore release after invalidation,
 507                  * write with 0 means semaphore release
 508                  */
 509                 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem +
 510                                       hub->eng_distance * eng, 0);
 511
 512         return pd_addr;
 513 }
 514
 515 static void gmc_v10_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid,
 516                                          unsigned pasid)
 517 {
 518         struct amdgpu_device *adev = ring->adev;
 519         uint32_t reg;
 520
 521         /* MES fw manages IH_VMID_x_LUT updating */
 522         if (ring->is_mes_queue)
 523                 return;
 524
 525         if (ring->funcs->vmhub == AMDGPU_GFXHUB_0)
 526                 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid;
 527         else
 528                 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid;
 529
 530         amdgpu_ring_emit_wreg(ring, reg, pasid);
 531 }
 532
 533 /*
 534  * PTE format on NAVI 10:
 535  * 63:59 reserved
 536  * 58 reserved and for sienna_cichlid is used for MALL noalloc
 537  * 57 reserved
 538  * 56 F
 539  * 55 L
 540  * 54 reserved
 541  * 53:52 SW
 542  * 51 T
 543  * 50:48 mtype
 544  * 47:12 4k physical page base address
 545  * 11:7 fragment
 546  * 6 write
 547  * 5 read
 548  * 4 exe
 549  * 3 Z
 550  * 2 snooped
 551  * 1 system
 552  * 0 valid
 553  *
 554  * PDE format on NAVI 10:
 555  * 63:59 block fragment size
 556  * 58:55 reserved
 557  * 54 P
 558  * 53:48 reserved
 559  * 47:6 physical base address of PD or PTE
 560  * 5:3 reserved
 561  * 2 C
 562  * 1 system
 563  * 0 valid
 564  */
 565
 566 static uint64_t gmc_v10_0_map_mtype(struct amdgpu_device *adev, uint32_t flags)
 567 {
 568         switch (flags) {
 569         case AMDGPU_VM_MTYPE_DEFAULT:
 570                 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC);
 571         case AMDGPU_VM_MTYPE_NC:
 572                 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC);
 573         case AMDGPU_VM_MTYPE_WC:
 574                 return AMDGPU_PTE_MTYPE_NV10(MTYPE_WC);
 575         case AMDGPU_VM_MTYPE_CC:
 576                 return AMDGPU_PTE_MTYPE_NV10(MTYPE_CC);
 577         case AMDGPU_VM_MTYPE_UC:
 578                 return AMDGPU_PTE_MTYPE_NV10(MTYPE_UC);
 579         default:
 580                 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC);
 581         }
 582 }
 583
 584 static void gmc_v10_0_get_vm_pde(struct amdgpu_device *adev, int level,
 585                                  uint64_t *addr, uint64_t *flags)
 586 {
 587         if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM))
 588                 *addr = amdgpu_gmc_vram_mc2pa(adev, *addr);
 589         BUG_ON(*addr & 0xFFFF00000000003FULL);
 590
 591         if (!adev->gmc.translate_further)
 592                 return;
 593
 594         if (level == AMDGPU_VM_PDB1) {
 595                 /* Set the block fragment size */
 596                 if (!(*flags & AMDGPU_PDE_PTE))
 597                         *flags |= AMDGPU_PDE_BFS(0x9);
 598
 599         } else if (level == AMDGPU_VM_PDB0) {
 600                 if (*flags & AMDGPU_PDE_PTE)
 601                         *flags &= ~AMDGPU_PDE_PTE;
 602                 else
 603                         *flags |= AMDGPU_PTE_TF;
 604         }
 605 }
 606
 607 static void gmc_v10_0_get_vm_pte(struct amdgpu_device *adev,
 608                                  struct amdgpu_bo_va_mapping *mapping,
 609                                  uint64_t *flags)
 610 {
 611         struct amdgpu_bo *bo = mapping->bo_va->base.bo;
 612
 613         *flags &= ~AMDGPU_PTE_EXECUTABLE;
 614         *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE;
 615
 616         *flags &= ~AMDGPU_PTE_MTYPE_NV10_MASK;
 617         *flags |= (mapping->flags & AMDGPU_PTE_MTYPE_NV10_MASK);
 618
 619         *flags &= ~AMDGPU_PTE_NOALLOC;
 620         *flags |= (mapping->flags & AMDGPU_PTE_NOALLOC);
 621
 622         if (mapping->flags & AMDGPU_PTE_PRT) {
 623                 *flags |= AMDGPU_PTE_PRT;
 624                 *flags |= AMDGPU_PTE_SNOOPED;
 625                 *flags |= AMDGPU_PTE_LOG;
 626                 *flags |= AMDGPU_PTE_SYSTEM;
 627                 *flags &= ~AMDGPU_PTE_VALID;
 628         }
 629
 630         if (bo && bo->flags & (AMDGPU_GEM_CREATE_COHERENT |
 631                                AMDGPU_GEM_CREATE_UNCACHED))
 632                 *flags = (*flags & ~AMDGPU_PTE_MTYPE_NV10_MASK) |
 633                          AMDGPU_PTE_MTYPE_NV10(MTYPE_UC);
 634 }
 635
 636 static unsigned gmc_v10_0_get_vbios_fb_size(struct amdgpu_device *adev)
 637 {
 638         u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL);
 639         unsigned size;
 640
 641         if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
 642                 size = AMDGPU_VBIOS_VGA_ALLOCATION;
 643         } else {
 644                 u32 viewport;
 645                 u32 pitch;
 646
 647                 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION);
 648                 pitch = RREG32_SOC15(DCE, 0, mmHUBPREQ0_DCSURF_SURFACE_PITCH);
 649                 size = (REG_GET_FIELD(viewport,
 650                                         HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) *
 651                                 REG_GET_FIELD(pitch, HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH) *
 652                                 4);
 653         }
 654
 655         return size;
 656 }
 657
 658 static const struct amdgpu_gmc_funcs gmc_v10_0_gmc_funcs = {
 659         .flush_gpu_tlb = gmc_v10_0_flush_gpu_tlb,
 660         .flush_gpu_tlb_pasid = gmc_v10_0_flush_gpu_tlb_pasid,
 661         .emit_flush_gpu_tlb = gmc_v10_0_emit_flush_gpu_tlb,
 662         .emit_pasid_mapping = gmc_v10_0_emit_pasid_mapping,
 663         .map_mtype = gmc_v10_0_map_mtype,
 664         .get_vm_pde = gmc_v10_0_get_vm_pde,
 665         .get_vm_pte = gmc_v10_0_get_vm_pte,
 666         .get_vbios_fb_size = gmc_v10_0_get_vbios_fb_size,
 667 };
 668
 669 static void gmc_v10_0_set_gmc_funcs(struct amdgpu_device *adev)
 670 {
 671         if (adev->gmc.gmc_funcs == NULL)
 672                 adev->gmc.gmc_funcs = &gmc_v10_0_gmc_funcs;
 673 }
 674
 675 static void gmc_v10_0_set_umc_funcs(struct amdgpu_device *adev)
 676 {
 677         switch (adev->ip_versions[UMC_HWIP][0]) {
 678         case IP_VERSION(8, 7, 0):
 679                 adev->umc.max_ras_err_cnt_per_query = UMC_V8_7_TOTAL_CHANNEL_NUM;
 680                 adev->umc.channel_inst_num = UMC_V8_7_CHANNEL_INSTANCE_NUM;
 681                 adev->umc.umc_inst_num = UMC_V8_7_UMC_INSTANCE_NUM;
 682                 adev->umc.channel_offs = UMC_V8_7_PER_CHANNEL_OFFSET_SIENNA;
 683                 adev->umc.channel_idx_tbl = &umc_v8_7_channel_idx_tbl[0][0];
 684                 adev->umc.ras = &umc_v8_7_ras;
 685                 break;
 686         default:
 687                 break;
 688         }
 689         if (adev->umc.ras) {
 690                 amdgpu_ras_register_ras_block(adev, &adev->umc.ras->ras_block);
 691
 692                 strcpy(adev->umc.ras->ras_block.ras_comm.name, "umc");
 693                 adev->umc.ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__UMC;
 694                 adev->umc.ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
 695                 adev->umc.ras_if = &adev->umc.ras->ras_block.ras_comm;
 696
 697                 /* If don't define special ras_late_init function, use default ras_late_init */
 698                 if (!adev->umc.ras->ras_block.ras_late_init)
 699                                 adev->umc.ras->ras_block.ras_late_init = amdgpu_umc_ras_late_init;
 700
 701                 /* If not defined special ras_cb function, use default ras_cb */
 702                 if (!adev->umc.ras->ras_block.ras_cb)
 703                         adev->umc.ras->ras_block.ras_cb = amdgpu_umc_process_ras_data_cb;
 704         }
 705 }
 706
 707
 708 static void gmc_v10_0_set_mmhub_funcs(struct amdgpu_device *adev)
 709 {
 710         switch (adev->ip_versions[MMHUB_HWIP][0]) {
 711         case IP_VERSION(2, 3, 0):
 712         case IP_VERSION(2, 4, 0):
 713         case IP_VERSION(2, 4, 1):
 714                 adev->mmhub.funcs = &mmhub_v2_3_funcs;
 715                 break;
 716         default:
 717                 adev->mmhub.funcs = &mmhub_v2_0_funcs;
 718                 break;
 719         }
 720 }
 721
 722 static void gmc_v10_0_set_gfxhub_funcs(struct amdgpu_device *adev)
 723 {
 724         switch (adev->ip_versions[GC_HWIP][0]) {
 725         case IP_VERSION(10, 3, 0):
 726         case IP_VERSION(10, 3, 2):
 727         case IP_VERSION(10, 3, 1):
 728         case IP_VERSION(10, 3, 4):
 729         case IP_VERSION(10, 3, 5):
 730         case IP_VERSION(10, 3, 6):
 731         case IP_VERSION(10, 3, 3):
 732         case IP_VERSION(10, 3, 7):
 733                 adev->gfxhub.funcs = &gfxhub_v2_1_funcs;
 734                 break;
 735         default:
 736                 adev->gfxhub.funcs = &gfxhub_v2_0_funcs;
 737                 break;
 738         }
 739 }
 740
 741
 742 static int gmc_v10_0_early_init(void *handle)
 743 {
 744         int r;
 745         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 746
 747         gmc_v10_0_set_mmhub_funcs(adev);
 748         gmc_v10_0_set_gfxhub_funcs(adev);
 749         gmc_v10_0_set_gmc_funcs(adev);
 750         gmc_v10_0_set_irq_funcs(adev);
 751         gmc_v10_0_set_umc_funcs(adev);
 752
 753         adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
 754         adev->gmc.shared_aperture_end =
 755                 adev->gmc.shared_aperture_start + (4ULL << 30) - 1;
 756         adev->gmc.private_aperture_start = 0x1000000000000000ULL;
 757         adev->gmc.private_aperture_end =
 758                 adev->gmc.private_aperture_start + (4ULL << 30) - 1;
 759
 760         r = amdgpu_gmc_ras_early_init(adev);
 761         if (r)
 762                 return r;
 763
 764         return 0;
 765 }
 766
 767 static int gmc_v10_0_late_init(void *handle)
 768 {
 769         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 770         int r;
 771
 772         r = amdgpu_gmc_allocate_vm_inv_eng(adev);
 773         if (r)
 774                 return r;
 775
 776         r = amdgpu_gmc_ras_late_init(adev);
 777         if (r)
 778                 return r;
 779
 780         return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
 781 }
 782
 783 static void gmc_v10_0_vram_gtt_location(struct amdgpu_device *adev,
 784                                         struct amdgpu_gmc *mc)
 785 {
 786         u64 base = 0;
 787
 788         base = adev->gfxhub.funcs->get_fb_location(adev);
 789
 790         /* add the xgmi offset of the physical node */
 791         base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;
 792
 793         amdgpu_gmc_vram_location(adev, &adev->gmc, base);
 794         amdgpu_gmc_gart_location(adev, mc);
 795         amdgpu_gmc_agp_location(adev, mc);
 796
 797         /* base offset of vram pages */
 798         adev->vm_manager.vram_base_offset = adev->gfxhub.funcs->get_mc_fb_offset(adev);
 799
 800         /* add the xgmi offset of the physical node */
 801         adev->vm_manager.vram_base_offset +=
 802                 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;
 803 }
 804
 805 /**
 806  * gmc_v10_0_mc_init - initialize the memory controller driver params
 807  *
 808  * @adev: amdgpu_device pointer
 809  *
 810  * Look up the amount of vram, vram width, and decide how to place
 811  * vram and gart within the GPU's physical address space.
 812  * Returns 0 for success.
 813  */
 814 static int gmc_v10_0_mc_init(struct amdgpu_device *adev)
 815 {
 816         int r;
 817
 818         /* size in MB on si */
 819         adev->gmc.mc_vram_size =
 820                 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL;
 821         adev->gmc.real_vram_size = adev->gmc.mc_vram_size;
 822
 823         if (!(adev->flags & AMD_IS_APU)) {
 824                 r = amdgpu_device_resize_fb_bar(adev);
 825                 if (r)
 826                         return r;
 827         }
 828         adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
 829         adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
 830
 831 #ifdef CONFIG_X86_64
 832         if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) {
 833                 adev->gmc.aper_base = adev->gfxhub.funcs->get_mc_fb_offset(adev);
 834                 adev->gmc.aper_size = adev->gmc.real_vram_size;
 835         }
 836 #endif
 837
 838         /* In case the PCI BAR is larger than the actual amount of vram */
 839         adev->gmc.visible_vram_size = adev->gmc.aper_size;
 840         if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size)
 841                 adev->gmc.visible_vram_size = adev->gmc.real_vram_size;
 842
 843         /* set the gart size */
 844         if (amdgpu_gart_size == -1) {
 845                 switch (adev->ip_versions[GC_HWIP][0]) {
 846                 default:
 847                         adev->gmc.gart_size = 512ULL << 20;
 848                         break;
 849                 case IP_VERSION(10, 3, 1):   /* DCE SG support */
 850                 case IP_VERSION(10, 3, 3):   /* DCE SG support */
 851                 case IP_VERSION(10, 3, 6):   /* DCE SG support */
 852                 case IP_VERSION(10, 3, 7):   /* DCE SG support */
 853                         adev->gmc.gart_size = 1024ULL << 20;
 854                         break;
 855                 }
 856         } else {
 857                 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
 858         }
 859
 860         gmc_v10_0_vram_gtt_location(adev, &adev->gmc);
 861
 862         return 0;
 863 }
 864
 865 static int gmc_v10_0_gart_init(struct amdgpu_device *adev)
 866 {
 867         int r;
 868
 869         if (adev->gart.bo) {
 870                 WARN(1, "NAVI10 PCIE GART already initialized\n");
 871                 return 0;
 872         }
 873
 874         /* Initialize common gart structure */
 875         r = amdgpu_gart_init(adev);
 876         if (r)
 877                 return r;
 878
 879         adev->gart.table_size = adev->gart.num_gpu_pages * 8;
 880         adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_NV10(MTYPE_UC) |
 881                                  AMDGPU_PTE_EXECUTABLE;
 882
 883         return amdgpu_gart_table_vram_alloc(adev);
 884 }
 885
 886 static int gmc_v10_0_sw_init(void *handle)
 887 {
 888         int r, vram_width = 0, vram_type = 0, vram_vendor = 0;
 889         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 890
 891         adev->gfxhub.funcs->init(adev);
 892
 893         adev->mmhub.funcs->init(adev);
 894
 895         spin_lock_init(&adev->gmc.invalidate_lock);
 896
 897         if ((adev->flags & AMD_IS_APU) && amdgpu_emu_mode == 1) {
 898                 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_DDR4;
 899                 adev->gmc.vram_width = 64;
 900         } else if (amdgpu_emu_mode == 1) {
 901                 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_GDDR6;
 902                 adev->gmc.vram_width = 1 * 128; /* numchan * chansize */
 903         } else {
 904                 r = amdgpu_atomfirmware_get_vram_info(adev,
 905                                 &vram_width, &vram_type, &vram_vendor);
 906                 adev->gmc.vram_width = vram_width;
 907
 908                 adev->gmc.vram_type = vram_type;
 909                 adev->gmc.vram_vendor = vram_vendor;
 910         }
 911
 912         switch (adev->ip_versions[GC_HWIP][0]) {
 913         case IP_VERSION(10, 3, 0):
 914                 adev->gmc.mall_size = 128 * 1024 * 1024;
 915                 break;
 916         case IP_VERSION(10, 3, 2):
 917                 adev->gmc.mall_size = 96 * 1024 * 1024;
 918                 break;
 919         case IP_VERSION(10, 3, 4):
 920                 adev->gmc.mall_size = 32 * 1024 * 1024;
 921                 break;
 922         case IP_VERSION(10, 3, 5):
 923                 adev->gmc.mall_size = 16 * 1024 * 1024;
 924                 break;
 925         default:
 926                 adev->gmc.mall_size = 0;
 927                 break;
 928         }
 929
 930         switch (adev->ip_versions[GC_HWIP][0]) {
 931         case IP_VERSION(10, 1, 10):
 932         case IP_VERSION(10, 1, 1):
 933         case IP_VERSION(10, 1, 2):
 934         case IP_VERSION(10, 1, 3):
 935         case IP_VERSION(10, 1, 4):
 936         case IP_VERSION(10, 3, 0):
 937         case IP_VERSION(10, 3, 2):
 938         case IP_VERSION(10, 3, 1):
 939         case IP_VERSION(10, 3, 4):
 940         case IP_VERSION(10, 3, 5):
 941         case IP_VERSION(10, 3, 6):
 942         case IP_VERSION(10, 3, 3):
 943         case IP_VERSION(10, 3, 7):
 944                 adev->num_vmhubs = 2;
 945                 /*
 946                  * To fulfill 4-level page support,
 947                  * vm size is 256TB (48bit), maximum size of Navi10/Navi14/Navi12,
 948                  * block size 512 (9bit)
 949                  */
 950                 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
 951                 break;
 952         default:
 953                 break;
 954         }
 955
 956         /* This interrupt is VMC page fault.*/
 957         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC,
 958                               VMC_1_0__SRCID__VM_FAULT,
 959                               &adev->gmc.vm_fault);
 960
 961         if (r)
 962                 return r;
 963
 964         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2,
 965                               UTCL2_1_0__SRCID__FAULT,
 966                               &adev->gmc.vm_fault);
 967         if (r)
 968                 return r;
 969
 970         if (!amdgpu_sriov_vf(adev)) {
 971                 /* interrupt sent to DF. */
 972                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DF, 0,
 973                                       &adev->gmc.ecc_irq);
 974                 if (r)
 975                         return r;
 976         }
 977
 978         /*
 979          * Set the internal MC address mask This is the max address of the GPU's
 980          * internal address space.
 981          */
 982         adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */
 983
 984         r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44));
 985         if (r) {
 986                 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n");
 987                 return r;
 988         }
 989
 990         adev->need_swiotlb = drm_need_swiotlb(44);
 991
 992         r = gmc_v10_0_mc_init(adev);
 993         if (r)
 994                 return r;
 995
 996         amdgpu_gmc_get_vbios_allocations(adev);
 997
 998         /* Memory manager */
 999         r = amdgpu_bo_init(adev);
1000         if (r)
1001                 return r;
1002
1003         r = gmc_v10_0_gart_init(adev);
1004         if (r)
1005                 return r;
1006
1007         /*
1008          * number of VMs
1009          * VMID 0 is reserved for System
1010          * amdgpu graphics/compute will use VMIDs 1-7
1011          * amdkfd will use VMIDs 8-15
1012          */
1013         adev->vm_manager.first_kfd_vmid = 8;
1014
1015         amdgpu_vm_manager_init(adev);
1016
1017         return 0;
1018 }
1019
1020 /**
1021  * gmc_v10_0_gart_fini - vm fini callback
1022  *
1023  * @adev: amdgpu_device pointer
1024  *
1025  * Tears down the driver GART/VM setup (CIK).
1026  */
1027 static void gmc_v10_0_gart_fini(struct amdgpu_device *adev)
1028 {
1029         amdgpu_gart_table_vram_free(adev);
1030 }
1031
1032 static int gmc_v10_0_sw_fini(void *handle)
1033 {
1034         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1035
1036         amdgpu_vm_manager_fini(adev);
1037         gmc_v10_0_gart_fini(adev);
1038         amdgpu_gem_force_release(adev);
1039         amdgpu_bo_fini(adev);
1040
1041         return 0;
1042 }
1043
1044 static void gmc_v10_0_init_golden_registers(struct amdgpu_device *adev)
1045 {
1046 }
1047
1048 /**
1049  * gmc_v10_0_gart_enable - gart enable
1050  *
1051  * @adev: amdgpu_device pointer
1052  */
1053 static int gmc_v10_0_gart_enable(struct amdgpu_device *adev)
1054 {
1055         int r;
1056         bool value;
1057
1058         if (adev->gart.bo == NULL) {
1059                 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
1060                 return -EINVAL;
1061         }
1062
1063         amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr);
1064         r = adev->gfxhub.funcs->gart_enable(adev);
1065         if (r)
1066                 return r;
1067
1068         r = adev->mmhub.funcs->gart_enable(adev);
1069         if (r)
1070                 return r;
1071
1072         adev->hdp.funcs->init_registers(adev);
1073
1074         /* Flush HDP after it is initialized */
1075         adev->hdp.funcs->flush_hdp(adev, NULL);
1076
1077         value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ?
1078                 false : true;
1079
1080         adev->gfxhub.funcs->set_fault_enable_default(adev, value);
1081         adev->mmhub.funcs->set_fault_enable_default(adev, value);
1082         gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_MMHUB_0, 0);
1083         gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB_0, 0);
1084
1085         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
1086                  (unsigned)(adev->gmc.gart_size >> 20),
1087                  (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo));
1088
1089         return 0;
1090 }
1091
1092 static int gmc_v10_0_hw_init(void *handle)
1093 {
1094         int r;
1095         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1096
1097         /* The sequence of these two function calls matters.*/
1098         gmc_v10_0_init_golden_registers(adev);
1099
1100         /*
1101          * harvestable groups in gc_utcl2 need to be programmed before any GFX block
1102          * register setup within GMC, or else system hang when harvesting SA.
1103          */
1104         if (adev->gfxhub.funcs && adev->gfxhub.funcs->utcl2_harvest)
1105                 adev->gfxhub.funcs->utcl2_harvest(adev);
1106
1107         r = gmc_v10_0_gart_enable(adev);
1108         if (r)
1109                 return r;
1110
1111         if (amdgpu_emu_mode == 1) {
1112                 r = amdgpu_gmc_vram_checking(adev);
1113                 if (r)
1114                         return r;
1115         }
1116
1117         if (adev->umc.funcs && adev->umc.funcs->init_registers)
1118                 adev->umc.funcs->init_registers(adev);
1119
1120         return 0;
1121 }
1122
1123 /**
1124  * gmc_v10_0_gart_disable - gart disable
1125  *
1126  * @adev: amdgpu_device pointer
1127  *
1128  * This disables all VM page table.
1129  */
1130 static void gmc_v10_0_gart_disable(struct amdgpu_device *adev)
1131 {
1132         adev->gfxhub.funcs->gart_disable(adev);
1133         adev->mmhub.funcs->gart_disable(adev);
1134 }
1135
1136 static int gmc_v10_0_hw_fini(void *handle)
1137 {
1138         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1139
1140         gmc_v10_0_gart_disable(adev);
1141
1142         if (amdgpu_sriov_vf(adev)) {
1143                 /* full access mode, so don't touch any GMC register */
1144                 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n");
1145                 return 0;
1146         }
1147
1148         amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0);
1149         amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
1150
1151         return 0;
1152 }
1153
1154 static int gmc_v10_0_suspend(void *handle)
1155 {
1156         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1157
1158         gmc_v10_0_hw_fini(adev);
1159
1160         return 0;
1161 }
1162
1163 static int gmc_v10_0_resume(void *handle)
1164 {
1165         int r;
1166         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1167
1168         r = gmc_v10_0_hw_init(adev);
1169         if (r)
1170                 return r;
1171
1172         amdgpu_vmid_reset_all(adev);
1173
1174         return 0;
1175 }
1176
1177 static bool gmc_v10_0_is_idle(void *handle)
1178 {
1179         /* MC is always ready in GMC v10.*/
1180         return true;
1181 }
1182
1183 static int gmc_v10_0_wait_for_idle(void *handle)
1184 {
1185         /* There is no need to wait for MC idle in GMC v10.*/
1186         return 0;
1187 }
1188
1189 static int gmc_v10_0_soft_reset(void *handle)
1190 {
1191         return 0;
1192 }
1193
1194 static int gmc_v10_0_set_clockgating_state(void *handle,
1195                                            enum amd_clockgating_state state)
1196 {
1197         int r;
1198         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1199
1200         /*
1201          * The issue mmhub can't disconnect from DF with MMHUB clock gating being disabled
1202          * is a new problem observed at DF 3.0.3, however with the same suspend sequence not
1203          * seen any issue on the DF 3.0.2 series platform.
1204          */
1205         if (adev->in_s0ix && adev->ip_versions[DF_HWIP][0] > IP_VERSION(3, 0, 2)) {
1206                 dev_dbg(adev->dev, "keep mmhub clock gating being enabled for s0ix\n");
1207                 return 0;
1208         }
1209
1210         r = adev->mmhub.funcs->set_clockgating(adev, state);
1211         if (r)
1212                 return r;
1213
1214         if (adev->ip_versions[ATHUB_HWIP][0] >= IP_VERSION(2, 1, 0))
1215                 return athub_v2_1_set_clockgating(adev, state);
1216         else
1217                 return athub_v2_0_set_clockgating(adev, state);
1218 }
1219
1220 static void gmc_v10_0_get_clockgating_state(void *handle, u64 *flags)
1221 {
1222         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1223
1224         if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 3) ||
1225             adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 4))
1226                 return;
1227
1228         adev->mmhub.funcs->get_clockgating(adev, flags);
1229
1230         if (adev->ip_versions[ATHUB_HWIP][0] >= IP_VERSION(2, 1, 0))
1231                 athub_v2_1_get_clockgating(adev, flags);
1232         else
1233                 athub_v2_0_get_clockgating(adev, flags);
1234 }
1235
1236 static int gmc_v10_0_set_powergating_state(void *handle,
1237                                            enum amd_powergating_state state)
1238 {
1239         return 0;
1240 }
1241
1242 const struct amd_ip_funcs gmc_v10_0_ip_funcs = {
1243         .name = "gmc_v10_0",
1244         .early_init = gmc_v10_0_early_init,
1245         .late_init = gmc_v10_0_late_init,
1246         .sw_init = gmc_v10_0_sw_init,
1247         .sw_fini = gmc_v10_0_sw_fini,
1248         .hw_init = gmc_v10_0_hw_init,
1249         .hw_fini = gmc_v10_0_hw_fini,
1250         .suspend = gmc_v10_0_suspend,
1251         .resume = gmc_v10_0_resume,
1252         .is_idle = gmc_v10_0_is_idle,
1253         .wait_for_idle = gmc_v10_0_wait_for_idle,
1254         .soft_reset = gmc_v10_0_soft_reset,
1255         .set_clockgating_state = gmc_v10_0_set_clockgating_state,
1256         .set_powergating_state = gmc_v10_0_set_powergating_state,
1257         .get_clockgating_state = gmc_v10_0_get_clockgating_state,
1258 };
1259
1260 const struct amdgpu_ip_block_version gmc_v10_0_ip_block =
1261 {
1262         .type = AMD_IP_BLOCK_TYPE_GMC,
1263         .major = 10,
1264         .minor = 0,
1265         .rev = 0,
1266         .funcs = &gmc_v10_0_ip_funcs,
1267 };