drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include <linux/pci.h>
  25 #include "amdgpu.h"
  26 #include "amdgpu_atomfirmware.h"
  27 #include "gmc_v10_0.h"
  28
  29 #include "hdp/hdp_5_0_0_offset.h"
  30 #include "hdp/hdp_5_0_0_sh_mask.h"
  31 #include "gc/gc_10_1_0_sh_mask.h"
  32 #include "mmhub/mmhub_2_0_0_sh_mask.h"
  33 #include "dcn/dcn_2_0_0_offset.h"
  34 #include "dcn/dcn_2_0_0_sh_mask.h"
  35 #include "oss/osssys_5_0_0_offset.h"
  36 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h"
  37 #include "navi10_enum.h"
  38
  39 #include "soc15.h"
  40 #include "soc15_common.h"
  41
  42 #include "nbio_v2_3.h"
  43
  44 #include "gfxhub_v2_0.h"
  45 #include "mmhub_v2_0.h"
  46 #include "athub_v2_0.h"
  47 /* XXX Move this macro to navi10 header file, which is like vid.h for VI.*/
  48 #define AMDGPU_NUM_OF_VMIDS                     8
  49
  50 #if 0
  51 static const struct soc15_reg_golden golden_settings_navi10_hdp[] =
  52 {
  53         /* TODO add golden setting for hdp */
  54 };
  55 #endif
  56
  57 static int
  58 gmc_v10_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
  59                                    struct amdgpu_irq_src *src, unsigned type,
  60                                    enum amdgpu_interrupt_state state)
  61 {
  62         struct amdgpu_vmhub *hub;
  63         u32 tmp, reg, bits[AMDGPU_MAX_VMHUBS], i;
  64
  65         bits[AMDGPU_GFXHUB_0] = GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
  66                 GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
  67                 GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
  68                 GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
  69                 GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
  70                 GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
  71                 GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
  72
  73         bits[AMDGPU_MMHUB_0] = MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
  74                 MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
  75                 MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
  76                 MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
  77                 MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
  78                 MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
  79                 MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
  80
  81         switch (state) {
  82         case AMDGPU_IRQ_STATE_DISABLE:
  83                 /* MM HUB */
  84                 hub = &adev->vmhub[AMDGPU_MMHUB_0];
  85                 for (i = 0; i < 16; i++) {
  86                         reg = hub->vm_context0_cntl + i;
  87                         tmp = RREG32(reg);
  88                         tmp &= ~bits[AMDGPU_MMHUB_0];
  89                         WREG32(reg, tmp);
  90                 }
  91
  92                 /* GFX HUB */
  93                 hub = &adev->vmhub[AMDGPU_GFXHUB_0];
  94                 for (i = 0; i < 16; i++) {
  95                         reg = hub->vm_context0_cntl + i;
  96                         tmp = RREG32(reg);
  97                         tmp &= ~bits[AMDGPU_GFXHUB_0];
  98                         WREG32(reg, tmp);
  99                 }
 100                 break;
 101         case AMDGPU_IRQ_STATE_ENABLE:
 102                 /* MM HUB */
 103                 hub = &adev->vmhub[AMDGPU_MMHUB_0];
 104                 for (i = 0; i < 16; i++) {
 105                         reg = hub->vm_context0_cntl + i;
 106                         tmp = RREG32(reg);
 107                         tmp |= bits[AMDGPU_MMHUB_0];
 108                         WREG32(reg, tmp);
 109                 }
 110
 111                 /* GFX HUB */
 112                 hub = &adev->vmhub[AMDGPU_GFXHUB_0];
 113                 for (i = 0; i < 16; i++) {
 114                         reg = hub->vm_context0_cntl + i;
 115                         tmp = RREG32(reg);
 116                         tmp |= bits[AMDGPU_GFXHUB_0];
 117                         WREG32(reg, tmp);
 118                 }
 119                 break;
 120         default:
 121                 break;
 122         }
 123
 124         return 0;
 125 }
 126
 127 static int gmc_v10_0_process_interrupt(struct amdgpu_device *adev,
 128                                        struct amdgpu_irq_src *source,
 129                                        struct amdgpu_iv_entry *entry)
 130 {
 131         struct amdgpu_vmhub *hub = &adev->vmhub[entry->vmid_src];
 132         uint32_t status = 0;
 133         u64 addr;
 134
 135         addr = (u64)entry->src_data[0] << 12;
 136         addr |= ((u64)entry->src_data[1] & 0xf) << 44;
 137
 138         if (!amdgpu_sriov_vf(adev)) {
 139                 /*
 140                  * Issue a dummy read to wait for the status register to
 141                  * be updated to avoid reading an incorrect value due to
 142                  * the new fast GRBM interface.
 143                  */
 144                 if (entry->vmid_src == AMDGPU_GFXHUB_0)
 145                         RREG32(hub->vm_l2_pro_fault_status);
 146
 147                 status = RREG32(hub->vm_l2_pro_fault_status);
 148                 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1);
 149         }
 150
 151         if (printk_ratelimit()) {
 152                 struct amdgpu_task_info task_info;
 153
 154                 memset(&task_info, 0, sizeof(struct amdgpu_task_info));
 155                 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info);
 156
 157                 dev_err(adev->dev,
 158                         "[%s] page fault (src_id:%u ring:%u vmid:%u pasid:%u, "
 159                         "for process %s pid %d thread %s pid %d)\n",
 160                         entry->vmid_src ? "mmhub" : "gfxhub",
 161                         entry->src_id, entry->ring_id, entry->vmid,
 162                         entry->pasid, task_info.process_name, task_info.tgid,
 163                         task_info.task_name, task_info.pid);
 164                 dev_err(adev->dev, "  in page starting at address 0x%016llx from client %d\n",
 165                         addr, entry->client_id);
 166                 if (!amdgpu_sriov_vf(adev)) {
 167                         dev_err(adev->dev,
 168                                 "GCVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
 169                                 status);
 170                         dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n",
 171                                 REG_GET_FIELD(status,
 172                                 GCVM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS));
 173                         dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n",
 174                                 REG_GET_FIELD(status,
 175                                 GCVM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR));
 176                         dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n",
 177                                 REG_GET_FIELD(status,
 178                                 GCVM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS));
 179                         dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n",
 180                                 REG_GET_FIELD(status,
 181                                 GCVM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR));
 182                         dev_err(adev->dev, "\t RW: 0x%lx\n",
 183                                 REG_GET_FIELD(status,
 184                                 GCVM_L2_PROTECTION_FAULT_STATUS, RW));
 185                 }
 186         }
 187
 188         return 0;
 189 }
 190
 191 static const struct amdgpu_irq_src_funcs gmc_v10_0_irq_funcs = {
 192         .set = gmc_v10_0_vm_fault_interrupt_state,
 193         .process = gmc_v10_0_process_interrupt,
 194 };
 195
 196 static void gmc_v10_0_set_irq_funcs(struct amdgpu_device *adev)
 197 {
 198         adev->gmc.vm_fault.num_types = 1;
 199         adev->gmc.vm_fault.funcs = &gmc_v10_0_irq_funcs;
 200 }
 201
 202 static uint32_t gmc_v10_0_get_invalidate_req(unsigned int vmid,
 203                                              uint32_t flush_type)
 204 {
 205         u32 req = 0;
 206
 207         /* invalidate using legacy mode on vmid*/
 208         req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ,
 209                             PER_VMID_INVALIDATE_REQ, 1 << vmid);
 210         req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);
 211         req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
 212         req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
 213         req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
 214         req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
 215         req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
 216         req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ,
 217                             CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
 218
 219         return req;
 220 }
 221
 222 /**
 223  * gmc_v10_0_use_invalidate_semaphore - judge whether to use semaphore
 224  *
 225  * @adev: amdgpu_device pointer
 226  * @vmhub: vmhub type
 227  *
 228  */
 229 static bool gmc_v10_0_use_invalidate_semaphore(struct amdgpu_device *adev,
 230                                        uint32_t vmhub)
 231 {
 232         return ((vmhub == AMDGPU_MMHUB_0 ||
 233                  vmhub == AMDGPU_MMHUB_1) &&
 234                 (!amdgpu_sriov_vf(adev)));
 235 }
 236
 237 /*
 238  * GART
 239  * VMID 0 is the physical GPU addresses as used by the kernel.
 240  * VMIDs 1-15 are used for userspace clients and are handled
 241  * by the amdgpu vm/hsa code.
 242  */
 243
 244 static void gmc_v10_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid,
 245                                    unsigned int vmhub, uint32_t flush_type)
 246 {
 247         bool use_semaphore = gmc_v10_0_use_invalidate_semaphore(adev, vmhub);
 248         struct amdgpu_vmhub *hub = &adev->vmhub[vmhub];
 249         u32 tmp = gmc_v10_0_get_invalidate_req(vmid, flush_type);
 250         /* Use register 17 for GART */
 251         const unsigned eng = 17;
 252         unsigned int i;
 253
 254         spin_lock(&adev->gmc.invalidate_lock);
 255         /*
 256          * It may lose gpuvm invalidate acknowldege state across power-gating
 257          * off cycle, add semaphore acquire before invalidation and semaphore
 258          * release after invalidation to avoid entering power gated state
 259          * to WA the Issue
 260          */
 261
 262         /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
 263         if (use_semaphore) {
 264                 for (i = 0; i < adev->usec_timeout; i++) {
 265                         /* a read return value of 1 means semaphore acuqire */
 266                         tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_sem + eng);
 267                         if (tmp & 0x1)
 268                                 break;
 269                         udelay(1);
 270                 }
 271
 272                 if (i >= adev->usec_timeout)
 273                         DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n");
 274         }
 275
 276         WREG32_NO_KIQ(hub->vm_inv_eng0_req + eng, tmp);
 277
 278         /*
 279          * Issue a dummy read to wait for the ACK register to be cleared
 280          * to avoid a false ACK due to the new fast GRBM interface.
 281          */
 282         if (vmhub == AMDGPU_GFXHUB_0)
 283                 RREG32_NO_KIQ(hub->vm_inv_eng0_req + eng);
 284
 285         /* Wait for ACK with a delay.*/
 286         for (i = 0; i < adev->usec_timeout; i++) {
 287                 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng);
 288                 tmp &= 1 << vmid;
 289                 if (tmp)
 290                         break;
 291
 292                 udelay(1);
 293         }
 294
 295         /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
 296         if (use_semaphore)
 297                 /*
 298                  * add semaphore release after invalidation,
 299                  * write with 0 means semaphore release
 300                  */
 301                 WREG32_NO_KIQ(hub->vm_inv_eng0_sem + eng, 0);
 302
 303         spin_unlock(&adev->gmc.invalidate_lock);
 304
 305         if (i < adev->usec_timeout)
 306                 return;
 307
 308         DRM_ERROR("Timeout waiting for VM flush ACK!\n");
 309 }
 310
 311 /**
 312  * gmc_v10_0_flush_gpu_tlb - gart tlb flush callback
 313  *
 314  * @adev: amdgpu_device pointer
 315  * @vmid: vm instance to flush
 316  *
 317  * Flush the TLB for the requested page table.
 318  */
 319 static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
 320                                         uint32_t vmhub, uint32_t flush_type)
 321 {
 322         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
 323         struct dma_fence *fence;
 324         struct amdgpu_job *job;
 325
 326         int r;
 327
 328         /* flush hdp cache */
 329         adev->nbio.funcs->hdp_flush(adev, NULL);
 330
 331         mutex_lock(&adev->mman.gtt_window_lock);
 332
 333         if (vmhub == AMDGPU_MMHUB_0) {
 334                 gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_MMHUB_0, 0);
 335                 mutex_unlock(&adev->mman.gtt_window_lock);
 336                 return;
 337         }
 338
 339         BUG_ON(vmhub != AMDGPU_GFXHUB_0);
 340
 341         if (!adev->mman.buffer_funcs_enabled ||
 342             !adev->ib_pool_ready ||
 343             adev->in_gpu_reset ||
 344             ring->sched.ready == false) {
 345                 gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_GFXHUB_0, 0);
 346                 mutex_unlock(&adev->mman.gtt_window_lock);
 347                 return;
 348         }
 349
 350         /* The SDMA on Navi has a bug which can theoretically result in memory
 351          * corruption if an invalidation happens at the same time as an VA
 352          * translation. Avoid this by doing the invalidation from the SDMA
 353          * itself.
 354          */
 355         r = amdgpu_job_alloc_with_ib(adev, 16 * 4, &job);
 356         if (r)
 357                 goto error_alloc;
 358
 359         job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo);
 360         job->vm_needs_flush = true;
 361         job->ibs->ptr[job->ibs->length_dw++] = ring->funcs->nop;
 362         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
 363         r = amdgpu_job_submit(job, &adev->mman.entity,
 364                               AMDGPU_FENCE_OWNER_UNDEFINED, &fence);
 365         if (r)
 366                 goto error_submit;
 367
 368         mutex_unlock(&adev->mman.gtt_window_lock);
 369
 370         dma_fence_wait(fence, false);
 371         dma_fence_put(fence);
 372
 373         return;
 374
 375 error_submit:
 376         amdgpu_job_free(job);
 377
 378 error_alloc:
 379         mutex_unlock(&adev->mman.gtt_window_lock);
 380         DRM_ERROR("Error flushing GPU TLB using the SDMA (%d)!\n", r);
 381 }
 382
 383 static uint64_t gmc_v10_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
 384                                              unsigned vmid, uint64_t pd_addr)
 385 {
 386         bool use_semaphore = gmc_v10_0_use_invalidate_semaphore(ring->adev, ring->funcs->vmhub);
 387         struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
 388         uint32_t req = gmc_v10_0_get_invalidate_req(vmid, 0);
 389         unsigned eng = ring->vm_inv_eng;
 390
 391         /*
 392          * It may lose gpuvm invalidate acknowldege state across power-gating
 393          * off cycle, add semaphore acquire before invalidation and semaphore
 394          * release after invalidation to avoid entering power gated state
 395          * to WA the Issue
 396          */
 397
 398         /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
 399         if (use_semaphore)
 400                 /* a read return value of 1 means semaphore acuqire */
 401                 amdgpu_ring_emit_reg_wait(ring,
 402                                           hub->vm_inv_eng0_sem + eng, 0x1, 0x1);
 403
 404         amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + (2 * vmid),
 405                               lower_32_bits(pd_addr));
 406
 407         amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + (2 * vmid),
 408                               upper_32_bits(pd_addr));
 409
 410         amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + eng,
 411                                             hub->vm_inv_eng0_ack + eng,
 412                                             req, 1 << vmid);
 413
 414         /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
 415         if (use_semaphore)
 416                 /*
 417                  * add semaphore release after invalidation,
 418                  * write with 0 means semaphore release
 419                  */
 420                 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + eng, 0);
 421
 422         return pd_addr;
 423 }
 424
 425 static void gmc_v10_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid,
 426                                          unsigned pasid)
 427 {
 428         struct amdgpu_device *adev = ring->adev;
 429         uint32_t reg;
 430
 431         if (ring->funcs->vmhub == AMDGPU_GFXHUB_0)
 432                 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid;
 433         else
 434                 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid;
 435
 436         amdgpu_ring_emit_wreg(ring, reg, pasid);
 437 }
 438
 439 /*
 440  * PTE format on NAVI 10:
 441  * 63:59 reserved
 442  * 58:57 reserved
 443  * 56 F
 444  * 55 L
 445  * 54 reserved
 446  * 53:52 SW
 447  * 51 T
 448  * 50:48 mtype
 449  * 47:12 4k physical page base address
 450  * 11:7 fragment
 451  * 6 write
 452  * 5 read
 453  * 4 exe
 454  * 3 Z
 455  * 2 snooped
 456  * 1 system
 457  * 0 valid
 458  *
 459  * PDE format on NAVI 10:
 460  * 63:59 block fragment size
 461  * 58:55 reserved
 462  * 54 P
 463  * 53:48 reserved
 464  * 47:6 physical base address of PD or PTE
 465  * 5:3 reserved
 466  * 2 C
 467  * 1 system
 468  * 0 valid
 469  */
 470
 471 static uint64_t gmc_v10_0_map_mtype(struct amdgpu_device *adev, uint32_t flags)
 472 {
 473         switch (flags) {
 474         case AMDGPU_VM_MTYPE_DEFAULT:
 475                 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC);
 476         case AMDGPU_VM_MTYPE_NC:
 477                 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC);
 478         case AMDGPU_VM_MTYPE_WC:
 479                 return AMDGPU_PTE_MTYPE_NV10(MTYPE_WC);
 480         case AMDGPU_VM_MTYPE_CC:
 481                 return AMDGPU_PTE_MTYPE_NV10(MTYPE_CC);
 482         case AMDGPU_VM_MTYPE_UC:
 483                 return AMDGPU_PTE_MTYPE_NV10(MTYPE_UC);
 484         default:
 485                 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC);
 486         }
 487 }
 488
 489 static void gmc_v10_0_get_vm_pde(struct amdgpu_device *adev, int level,
 490                                  uint64_t *addr, uint64_t *flags)
 491 {
 492         if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM))
 493                 *addr = adev->vm_manager.vram_base_offset + *addr -
 494                         adev->gmc.vram_start;
 495         BUG_ON(*addr & 0xFFFF00000000003FULL);
 496
 497         if (!adev->gmc.translate_further)
 498                 return;
 499
 500         if (level == AMDGPU_VM_PDB1) {
 501                 /* Set the block fragment size */
 502                 if (!(*flags & AMDGPU_PDE_PTE))
 503                         *flags |= AMDGPU_PDE_BFS(0x9);
 504
 505         } else if (level == AMDGPU_VM_PDB0) {
 506                 if (*flags & AMDGPU_PDE_PTE)
 507                         *flags &= ~AMDGPU_PDE_PTE;
 508                 else
 509                         *flags |= AMDGPU_PTE_TF;
 510         }
 511 }
 512
 513 static void gmc_v10_0_get_vm_pte(struct amdgpu_device *adev,
 514                                  struct amdgpu_bo_va_mapping *mapping,
 515                                  uint64_t *flags)
 516 {
 517         *flags &= ~AMDGPU_PTE_EXECUTABLE;
 518         *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE;
 519
 520         *flags &= ~AMDGPU_PTE_MTYPE_NV10_MASK;
 521         *flags |= (mapping->flags & AMDGPU_PTE_MTYPE_NV10_MASK);
 522
 523         if (mapping->flags & AMDGPU_PTE_PRT) {
 524                 *flags |= AMDGPU_PTE_PRT;
 525                 *flags |= AMDGPU_PTE_SNOOPED;
 526                 *flags |= AMDGPU_PTE_LOG;
 527                 *flags |= AMDGPU_PTE_SYSTEM;
 528                 *flags &= ~AMDGPU_PTE_VALID;
 529         }
 530 }
 531
 532 static const struct amdgpu_gmc_funcs gmc_v10_0_gmc_funcs = {
 533         .flush_gpu_tlb = gmc_v10_0_flush_gpu_tlb,
 534         .emit_flush_gpu_tlb = gmc_v10_0_emit_flush_gpu_tlb,
 535         .emit_pasid_mapping = gmc_v10_0_emit_pasid_mapping,
 536         .map_mtype = gmc_v10_0_map_mtype,
 537         .get_vm_pde = gmc_v10_0_get_vm_pde,
 538         .get_vm_pte = gmc_v10_0_get_vm_pte
 539 };
 540
 541 static void gmc_v10_0_set_gmc_funcs(struct amdgpu_device *adev)
 542 {
 543         if (adev->gmc.gmc_funcs == NULL)
 544                 adev->gmc.gmc_funcs = &gmc_v10_0_gmc_funcs;
 545 }
 546
 547 static int gmc_v10_0_early_init(void *handle)
 548 {
 549         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 550
 551         gmc_v10_0_set_gmc_funcs(adev);
 552         gmc_v10_0_set_irq_funcs(adev);
 553
 554         adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
 555         adev->gmc.shared_aperture_end =
 556                 adev->gmc.shared_aperture_start + (4ULL << 30) - 1;
 557         adev->gmc.private_aperture_start = 0x1000000000000000ULL;
 558         adev->gmc.private_aperture_end =
 559                 adev->gmc.private_aperture_start + (4ULL << 30) - 1;
 560
 561         return 0;
 562 }
 563
 564 static int gmc_v10_0_late_init(void *handle)
 565 {
 566         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 567         int r;
 568
 569         r = amdgpu_gmc_allocate_vm_inv_eng(adev);
 570         if (r)
 571                 return r;
 572
 573         return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
 574 }
 575
 576 static void gmc_v10_0_vram_gtt_location(struct amdgpu_device *adev,
 577                                         struct amdgpu_gmc *mc)
 578 {
 579         u64 base = 0;
 580
 581         base = gfxhub_v2_0_get_fb_location(adev);
 582
 583         amdgpu_gmc_vram_location(adev, &adev->gmc, base);
 584         amdgpu_gmc_gart_location(adev, mc);
 585
 586         /* base offset of vram pages */
 587         adev->vm_manager.vram_base_offset = gfxhub_v2_0_get_mc_fb_offset(adev);
 588 }
 589
 590 /**
 591  * gmc_v10_0_mc_init - initialize the memory controller driver params
 592  *
 593  * @adev: amdgpu_device pointer
 594  *
 595  * Look up the amount of vram, vram width, and decide how to place
 596  * vram and gart within the GPU's physical address space.
 597  * Returns 0 for success.
 598  */
 599 static int gmc_v10_0_mc_init(struct amdgpu_device *adev)
 600 {
 601         /* Could aper size report 0 ? */
 602         adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
 603         adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
 604
 605         /* size in MB on si */
 606         adev->gmc.mc_vram_size =
 607                 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL;
 608         adev->gmc.real_vram_size = adev->gmc.mc_vram_size;
 609         adev->gmc.visible_vram_size = adev->gmc.aper_size;
 610
 611         /* In case the PCI BAR is larger than the actual amount of vram */
 612         if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size)
 613                 adev->gmc.visible_vram_size = adev->gmc.real_vram_size;
 614
 615         /* set the gart size */
 616         if (amdgpu_gart_size == -1) {
 617                 switch (adev->asic_type) {
 618                 case CHIP_NAVI10:
 619                 case CHIP_NAVI14:
 620                 case CHIP_NAVI12:
 621                 default:
 622                         adev->gmc.gart_size = 512ULL << 20;
 623                         break;
 624                 }
 625         } else
 626                 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
 627
 628         gmc_v10_0_vram_gtt_location(adev, &adev->gmc);
 629
 630         return 0;
 631 }
 632
 633 static int gmc_v10_0_gart_init(struct amdgpu_device *adev)
 634 {
 635         int r;
 636
 637         if (adev->gart.bo) {
 638                 WARN(1, "NAVI10 PCIE GART already initialized\n");
 639                 return 0;
 640         }
 641
 642         /* Initialize common gart structure */
 643         r = amdgpu_gart_init(adev);
 644         if (r)
 645                 return r;
 646
 647         adev->gart.table_size = adev->gart.num_gpu_pages * 8;
 648         adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_NV10(MTYPE_UC) |
 649                                  AMDGPU_PTE_EXECUTABLE;
 650
 651         return amdgpu_gart_table_vram_alloc(adev);
 652 }
 653
 654 static unsigned gmc_v10_0_get_vbios_fb_size(struct amdgpu_device *adev)
 655 {
 656         u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL);
 657         unsigned size;
 658
 659         if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
 660                 size = 9 * 1024 * 1024; /* reserve 8MB for vga emulator and 1 MB for FB */
 661         } else {
 662                 u32 viewport;
 663                 u32 pitch;
 664
 665                 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION);
 666                 pitch = RREG32_SOC15(DCE, 0, mmHUBPREQ0_DCSURF_SURFACE_PITCH);
 667                 size = (REG_GET_FIELD(viewport,
 668                                         HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) *
 669                                 REG_GET_FIELD(pitch, HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH) *
 670                                 4);
 671         }
 672         /* return 0 if the pre-OS buffer uses up most of vram */
 673         if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024)) {
 674                 DRM_ERROR("Warning: pre-OS buffer uses most of vram, \
 675                                 be aware of gart table overwrite\n");
 676                 return 0;
 677         }
 678
 679         return size;
 680 }
 681
 682
 683
 684 static int gmc_v10_0_sw_init(void *handle)
 685 {
 686         int r, vram_width = 0, vram_type = 0, vram_vendor = 0;
 687         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 688
 689         gfxhub_v2_0_init(adev);
 690         mmhub_v2_0_init(adev);
 691
 692         spin_lock_init(&adev->gmc.invalidate_lock);
 693
 694         r = amdgpu_atomfirmware_get_vram_info(adev,
 695                 &vram_width, &vram_type, &vram_vendor);
 696         if (!amdgpu_emu_mode)
 697                 adev->gmc.vram_width = vram_width;
 698         else
 699                 adev->gmc.vram_width = 1 * 128; /* numchan * chansize */
 700
 701         adev->gmc.vram_type = vram_type;
 702         adev->gmc.vram_vendor = vram_vendor;
 703         switch (adev->asic_type) {
 704         case CHIP_NAVI10:
 705         case CHIP_NAVI14:
 706         case CHIP_NAVI12:
 707                 adev->num_vmhubs = 2;
 708                 /*
 709                  * To fulfill 4-level page support,
 710                  * vm size is 256TB (48bit), maximum size of Navi10/Navi14/Navi12,
 711                  * block size 512 (9bit)
 712                  */
 713                 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
 714                 break;
 715         default:
 716                 break;
 717         }
 718
 719         /* This interrupt is VMC page fault.*/
 720         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC,
 721                               VMC_1_0__SRCID__VM_FAULT,
 722                               &adev->gmc.vm_fault);
 723         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2,
 724                               UTCL2_1_0__SRCID__FAULT,
 725                               &adev->gmc.vm_fault);
 726         if (r)
 727                 return r;
 728
 729         /*
 730          * Set the internal MC address mask This is the max address of the GPU's
 731          * internal address space.
 732          */
 733         adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */
 734
 735         /*
 736          * Reserve 8M stolen memory for navi10 like vega10
 737          * TODO: will check if it's really needed on asic.
 738          */
 739         if (amdgpu_emu_mode == 1)
 740                 adev->gmc.stolen_size = 0;
 741         else
 742                 adev->gmc.stolen_size = 9 * 1024 *1024;
 743
 744         r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44));
 745         if (r) {
 746                 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n");
 747                 return r;
 748         }
 749
 750         r = gmc_v10_0_mc_init(adev);
 751         if (r)
 752                 return r;
 753
 754         adev->gmc.stolen_size = gmc_v10_0_get_vbios_fb_size(adev);
 755
 756         /* Memory manager */
 757         r = amdgpu_bo_init(adev);
 758         if (r)
 759                 return r;
 760
 761         r = gmc_v10_0_gart_init(adev);
 762         if (r)
 763                 return r;
 764
 765         /*
 766          * number of VMs
 767          * VMID 0 is reserved for System
 768          * amdgpu graphics/compute will use VMIDs 1-7
 769          * amdkfd will use VMIDs 8-15
 770          */
 771         adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids = AMDGPU_NUM_OF_VMIDS;
 772         adev->vm_manager.id_mgr[AMDGPU_MMHUB_0].num_ids = AMDGPU_NUM_OF_VMIDS;
 773
 774         amdgpu_vm_manager_init(adev);
 775
 776         return 0;
 777 }
 778
 779 /**
 780  * gmc_v8_0_gart_fini - vm fini callback
 781  *
 782  * @adev: amdgpu_device pointer
 783  *
 784  * Tears down the driver GART/VM setup (CIK).
 785  */
 786 static void gmc_v10_0_gart_fini(struct amdgpu_device *adev)
 787 {
 788         amdgpu_gart_table_vram_free(adev);
 789         amdgpu_gart_fini(adev);
 790 }
 791
 792 static int gmc_v10_0_sw_fini(void *handle)
 793 {
 794         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 795
 796         amdgpu_vm_manager_fini(adev);
 797         gmc_v10_0_gart_fini(adev);
 798         amdgpu_gem_force_release(adev);
 799         amdgpu_bo_fini(adev);
 800
 801         return 0;
 802 }
 803
 804 static void gmc_v10_0_init_golden_registers(struct amdgpu_device *adev)
 805 {
 806         switch (adev->asic_type) {
 807         case CHIP_NAVI10:
 808         case CHIP_NAVI14:
 809         case CHIP_NAVI12:
 810                 break;
 811         default:
 812                 break;
 813         }
 814 }
 815
 816 /**
 817  * gmc_v10_0_gart_enable - gart enable
 818  *
 819  * @adev: amdgpu_device pointer
 820  */
 821 static int gmc_v10_0_gart_enable(struct amdgpu_device *adev)
 822 {
 823         int r;
 824         bool value;
 825         u32 tmp;
 826
 827         if (adev->gart.bo == NULL) {
 828                 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
 829                 return -EINVAL;
 830         }
 831
 832         r = amdgpu_gart_table_vram_pin(adev);
 833         if (r)
 834                 return r;
 835
 836         r = gfxhub_v2_0_gart_enable(adev);
 837         if (r)
 838                 return r;
 839
 840         r = mmhub_v2_0_gart_enable(adev);
 841         if (r)
 842                 return r;
 843
 844         tmp = RREG32_SOC15(HDP, 0, mmHDP_MISC_CNTL);
 845         tmp |= HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE_MASK;
 846         WREG32_SOC15(HDP, 0, mmHDP_MISC_CNTL, tmp);
 847
 848         tmp = RREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL);
 849         WREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL, tmp);
 850
 851         /* Flush HDP after it is initialized */
 852         adev->nbio.funcs->hdp_flush(adev, NULL);
 853
 854         value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ?
 855                 false : true;
 856
 857         gfxhub_v2_0_set_fault_enable_default(adev, value);
 858         mmhub_v2_0_set_fault_enable_default(adev, value);
 859         gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_MMHUB_0, 0);
 860         gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB_0, 0);
 861
 862         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
 863                  (unsigned)(adev->gmc.gart_size >> 20),
 864                  (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo));
 865
 866         adev->gart.ready = true;
 867
 868         return 0;
 869 }
 870
 871 static int gmc_v10_0_hw_init(void *handle)
 872 {
 873         int r;
 874         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 875
 876         /* The sequence of these two function calls matters.*/
 877         gmc_v10_0_init_golden_registers(adev);
 878
 879         r = gmc_v10_0_gart_enable(adev);
 880         if (r)
 881                 return r;
 882
 883         return 0;
 884 }
 885
 886 /**
 887  * gmc_v10_0_gart_disable - gart disable
 888  *
 889  * @adev: amdgpu_device pointer
 890  *
 891  * This disables all VM page table.
 892  */
 893 static void gmc_v10_0_gart_disable(struct amdgpu_device *adev)
 894 {
 895         gfxhub_v2_0_gart_disable(adev);
 896         mmhub_v2_0_gart_disable(adev);
 897         amdgpu_gart_table_vram_unpin(adev);
 898 }
 899
 900 static int gmc_v10_0_hw_fini(void *handle)
 901 {
 902         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 903
 904         if (amdgpu_sriov_vf(adev)) {
 905                 /* full access mode, so don't touch any GMC register */
 906                 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n");
 907                 return 0;
 908         }
 909
 910         amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
 911         gmc_v10_0_gart_disable(adev);
 912
 913         return 0;
 914 }
 915
 916 static int gmc_v10_0_suspend(void *handle)
 917 {
 918         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 919
 920         gmc_v10_0_hw_fini(adev);
 921
 922         return 0;
 923 }
 924
 925 static int gmc_v10_0_resume(void *handle)
 926 {
 927         int r;
 928         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 929
 930         r = gmc_v10_0_hw_init(adev);
 931         if (r)
 932                 return r;
 933
 934         amdgpu_vmid_reset_all(adev);
 935
 936         return 0;
 937 }
 938
 939 static bool gmc_v10_0_is_idle(void *handle)
 940 {
 941         /* MC is always ready in GMC v10.*/
 942         return true;
 943 }
 944
 945 static int gmc_v10_0_wait_for_idle(void *handle)
 946 {
 947         /* There is no need to wait for MC idle in GMC v10.*/
 948         return 0;
 949 }
 950
 951 static int gmc_v10_0_soft_reset(void *handle)
 952 {
 953         return 0;
 954 }
 955
 956 static int gmc_v10_0_set_clockgating_state(void *handle,
 957                                            enum amd_clockgating_state state)
 958 {
 959         int r;
 960         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 961
 962         r = mmhub_v2_0_set_clockgating(adev, state);
 963         if (r)
 964                 return r;
 965
 966         return athub_v2_0_set_clockgating(adev, state);
 967 }
 968
 969 static void gmc_v10_0_get_clockgating_state(void *handle, u32 *flags)
 970 {
 971         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 972
 973         mmhub_v2_0_get_clockgating(adev, flags);
 974
 975         athub_v2_0_get_clockgating(adev, flags);
 976 }
 977
 978 static int gmc_v10_0_set_powergating_state(void *handle,
 979                                            enum amd_powergating_state state)
 980 {
 981         return 0;
 982 }
 983
 984 const struct amd_ip_funcs gmc_v10_0_ip_funcs = {
 985         .name = "gmc_v10_0",
 986         .early_init = gmc_v10_0_early_init,
 987         .late_init = gmc_v10_0_late_init,
 988         .sw_init = gmc_v10_0_sw_init,
 989         .sw_fini = gmc_v10_0_sw_fini,
 990         .hw_init = gmc_v10_0_hw_init,
 991         .hw_fini = gmc_v10_0_hw_fini,
 992         .suspend = gmc_v10_0_suspend,
 993         .resume = gmc_v10_0_resume,
 994         .is_idle = gmc_v10_0_is_idle,
 995         .wait_for_idle = gmc_v10_0_wait_for_idle,
 996         .soft_reset = gmc_v10_0_soft_reset,
 997         .set_clockgating_state = gmc_v10_0_set_clockgating_state,
 998         .set_powergating_state = gmc_v10_0_set_powergating_state,
 999         .get_clockgating_state = gmc_v10_0_get_clockgating_state,
1000 };
1001
1002 const struct amdgpu_ip_block_version gmc_v10_0_ip_block =
1003 {
1004         .type = AMD_IP_BLOCK_TYPE_GMC,
1005         .major = 10,
1006         .minor = 0,
1007         .rev = 0,
1008         .funcs = &gmc_v10_0_ip_funcs,
1009 };