drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

   1 /*
   2  * Copyright 2022 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/delay.h>
  25 #include <linux/firmware.h>
  26 #include <linux/module.h>
  27 #include <linux/pci.h>
  28
  29 #include "amdgpu.h"
  30 #include "amdgpu_xcp.h"
  31 #include "amdgpu_ucode.h"
  32 #include "amdgpu_trace.h"
  33
  34 #include "sdma/sdma_4_4_2_offset.h"
  35 #include "sdma/sdma_4_4_2_sh_mask.h"
  36
  37 #include "soc15_common.h"
  38 #include "soc15.h"
  39 #include "vega10_sdma_pkt_open.h"
  40
  41 #include "ivsrcid/sdma0/irqsrcs_sdma0_4_0.h"
  42 #include "ivsrcid/sdma1/irqsrcs_sdma1_4_0.h"
  43
  44 #include "amdgpu_ras.h"
  45
  46 MODULE_FIRMWARE("amdgpu/sdma_4_4_2.bin");
  47
  48 #define WREG32_SDMA(instance, offset, value) \
  49         WREG32(sdma_v4_4_2_get_reg_offset(adev, (instance), (offset)), value)
  50 #define RREG32_SDMA(instance, offset) \
  51         RREG32(sdma_v4_4_2_get_reg_offset(adev, (instance), (offset)))
  52
  53 static void sdma_v4_4_2_set_ring_funcs(struct amdgpu_device *adev);
  54 static void sdma_v4_4_2_set_buffer_funcs(struct amdgpu_device *adev);
  55 static void sdma_v4_4_2_set_vm_pte_funcs(struct amdgpu_device *adev);
  56 static void sdma_v4_4_2_set_irq_funcs(struct amdgpu_device *adev);
  57
  58 static u32 sdma_v4_4_2_get_reg_offset(struct amdgpu_device *adev,
  59                 u32 instance, u32 offset)
  60 {
  61         u32 dev_inst = GET_INST(SDMA0, instance);
  62
  63         return (adev->reg_offset[SDMA0_HWIP][dev_inst][0] + offset);
  64 }
  65
  66 static unsigned sdma_v4_4_2_seq_to_irq_id(int seq_num)
  67 {
  68         switch (seq_num) {
  69         case 0:
  70                 return SOC15_IH_CLIENTID_SDMA0;
  71         case 1:
  72                 return SOC15_IH_CLIENTID_SDMA1;
  73         case 2:
  74                 return SOC15_IH_CLIENTID_SDMA2;
  75         case 3:
  76                 return SOC15_IH_CLIENTID_SDMA3;
  77         default:
  78                 return -EINVAL;
  79         }
  80 }
  81
  82 static int sdma_v4_4_2_irq_id_to_seq(unsigned client_id)
  83 {
  84         switch (client_id) {
  85         case SOC15_IH_CLIENTID_SDMA0:
  86                 return 0;
  87         case SOC15_IH_CLIENTID_SDMA1:
  88                 return 1;
  89         case SOC15_IH_CLIENTID_SDMA2:
  90                 return 2;
  91         case SOC15_IH_CLIENTID_SDMA3:
  92                 return 3;
  93         default:
  94                 return -EINVAL;
  95         }
  96 }
  97
  98 static void sdma_v4_4_2_inst_init_golden_registers(struct amdgpu_device *adev,
  99                                                    uint32_t inst_mask)
 100 {
 101         u32 val;
 102         int i;
 103
 104         for (i = 0; i < adev->sdma.num_instances; i++) {
 105                 val = RREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG);
 106                 val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG, NUM_BANKS, 4);
 107                 val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG,
 108                                     PIPE_INTERLEAVE_SIZE, 0);
 109                 WREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG, val);
 110
 111                 val = RREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG_READ);
 112                 val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG_READ, NUM_BANKS,
 113                                     4);
 114                 val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG_READ,
 115                                     PIPE_INTERLEAVE_SIZE, 0);
 116                 WREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG_READ, val);
 117         }
 118 }
 119
 120 /**
 121  * sdma_v4_4_2_init_microcode - load ucode images from disk
 122  *
 123  * @adev: amdgpu_device pointer
 124  *
 125  * Use the firmware interface to load the ucode images into
 126  * the driver (not loaded into hw).
 127  * Returns 0 on success, error on failure.
 128  */
 129 static int sdma_v4_4_2_init_microcode(struct amdgpu_device *adev)
 130 {
 131         int ret, i;
 132
 133         for (i = 0; i < adev->sdma.num_instances; i++) {
 134                 if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 4, 2)) {
 135                         ret = amdgpu_sdma_init_microcode(adev, 0, true);
 136                         break;
 137                 } else {
 138                         ret = amdgpu_sdma_init_microcode(adev, i, false);
 139                         if (ret)
 140                                 return ret;
 141                 }
 142         }
 143
 144         return ret;
 145 }
 146
 147 /**
 148  * sdma_v4_4_2_ring_get_rptr - get the current read pointer
 149  *
 150  * @ring: amdgpu ring pointer
 151  *
 152  * Get the current rptr from the hardware.
 153  */
 154 static uint64_t sdma_v4_4_2_ring_get_rptr(struct amdgpu_ring *ring)
 155 {
 156         u64 *rptr;
 157
 158         /* XXX check if swapping is necessary on BE */
 159         rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]);
 160
 161         DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr);
 162         return ((*rptr) >> 2);
 163 }
 164
 165 /**
 166  * sdma_v4_4_2_ring_get_wptr - get the current write pointer
 167  *
 168  * @ring: amdgpu ring pointer
 169  *
 170  * Get the current wptr from the hardware.
 171  */
 172 static uint64_t sdma_v4_4_2_ring_get_wptr(struct amdgpu_ring *ring)
 173 {
 174         struct amdgpu_device *adev = ring->adev;
 175         u64 wptr;
 176
 177         if (ring->use_doorbell) {
 178                 /* XXX check if swapping is necessary on BE */
 179                 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]));
 180                 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
 181         } else {
 182                 wptr = RREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR_HI);
 183                 wptr = wptr << 32;
 184                 wptr |= RREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR);
 185                 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n",
 186                                 ring->me, wptr);
 187         }
 188
 189         return wptr >> 2;
 190 }
 191
 192 /**
 193  * sdma_v4_4_2_ring_set_wptr - commit the write pointer
 194  *
 195  * @ring: amdgpu ring pointer
 196  *
 197  * Write the wptr back to the hardware.
 198  */
 199 static void sdma_v4_4_2_ring_set_wptr(struct amdgpu_ring *ring)
 200 {
 201         struct amdgpu_device *adev = ring->adev;
 202
 203         DRM_DEBUG("Setting write pointer\n");
 204         if (ring->use_doorbell) {
 205                 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs];
 206
 207                 DRM_DEBUG("Using doorbell -- "
 208                                 "wptr_offs == 0x%08x "
 209                                 "lower_32_bits(ring->wptr) << 2 == 0x%08x "
 210                                 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n",
 211                                 ring->wptr_offs,
 212                                 lower_32_bits(ring->wptr << 2),
 213                                 upper_32_bits(ring->wptr << 2));
 214                 /* XXX check if swapping is necessary on BE */
 215                 WRITE_ONCE(*wb, (ring->wptr << 2));
 216                 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
 217                                 ring->doorbell_index, ring->wptr << 2);
 218                 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
 219         } else {
 220                 DRM_DEBUG("Not using doorbell -- "
 221                                 "regSDMA%i_GFX_RB_WPTR == 0x%08x "
 222                                 "regSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
 223                                 ring->me,
 224                                 lower_32_bits(ring->wptr << 2),
 225                                 ring->me,
 226                                 upper_32_bits(ring->wptr << 2));
 227                 WREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR,
 228                             lower_32_bits(ring->wptr << 2));
 229                 WREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR_HI,
 230                             upper_32_bits(ring->wptr << 2));
 231         }
 232 }
 233
 234 /**
 235  * sdma_v4_4_2_page_ring_get_wptr - get the current write pointer
 236  *
 237  * @ring: amdgpu ring pointer
 238  *
 239  * Get the current wptr from the hardware.
 240  */
 241 static uint64_t sdma_v4_4_2_page_ring_get_wptr(struct amdgpu_ring *ring)
 242 {
 243         struct amdgpu_device *adev = ring->adev;
 244         u64 wptr;
 245
 246         if (ring->use_doorbell) {
 247                 /* XXX check if swapping is necessary on BE */
 248                 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]));
 249         } else {
 250                 wptr = RREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR_HI);
 251                 wptr = wptr << 32;
 252                 wptr |= RREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR);
 253         }
 254
 255         return wptr >> 2;
 256 }
 257
 258 /**
 259  * sdma_v4_4_2_page_ring_set_wptr - commit the write pointer
 260  *
 261  * @ring: amdgpu ring pointer
 262  *
 263  * Write the wptr back to the hardware.
 264  */
 265 static void sdma_v4_4_2_page_ring_set_wptr(struct amdgpu_ring *ring)
 266 {
 267         struct amdgpu_device *adev = ring->adev;
 268
 269         if (ring->use_doorbell) {
 270                 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs];
 271
 272                 /* XXX check if swapping is necessary on BE */
 273                 WRITE_ONCE(*wb, (ring->wptr << 2));
 274                 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
 275         } else {
 276                 uint64_t wptr = ring->wptr << 2;
 277
 278                 WREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR,
 279                             lower_32_bits(wptr));
 280                 WREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR_HI,
 281                             upper_32_bits(wptr));
 282         }
 283 }
 284
 285 static void sdma_v4_4_2_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 286 {
 287         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
 288         int i;
 289
 290         for (i = 0; i < count; i++)
 291                 if (sdma && sdma->burst_nop && (i == 0))
 292                         amdgpu_ring_write(ring, ring->funcs->nop |
 293                                 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
 294                 else
 295                         amdgpu_ring_write(ring, ring->funcs->nop);
 296 }
 297
 298 /**
 299  * sdma_v4_4_2_ring_emit_ib - Schedule an IB on the DMA engine
 300  *
 301  * @ring: amdgpu ring pointer
 302  * @job: job to retrieve vmid from
 303  * @ib: IB object to schedule
 304  * @flags: unused
 305  *
 306  * Schedule an IB in the DMA ring.
 307  */
 308 static void sdma_v4_4_2_ring_emit_ib(struct amdgpu_ring *ring,
 309                                    struct amdgpu_job *job,
 310                                    struct amdgpu_ib *ib,
 311                                    uint32_t flags)
 312 {
 313         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
 314
 315         /* IB packet must end on a 8 DW boundary */
 316         sdma_v4_4_2_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
 317
 318         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
 319                           SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
 320         /* base must be 32 byte aligned */
 321         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
 322         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 323         amdgpu_ring_write(ring, ib->length_dw);
 324         amdgpu_ring_write(ring, 0);
 325         amdgpu_ring_write(ring, 0);
 326
 327 }
 328
 329 static void sdma_v4_4_2_wait_reg_mem(struct amdgpu_ring *ring,
 330                                    int mem_space, int hdp,
 331                                    uint32_t addr0, uint32_t addr1,
 332                                    uint32_t ref, uint32_t mask,
 333                                    uint32_t inv)
 334 {
 335         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 336                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(hdp) |
 337                           SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(mem_space) |
 338                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
 339         if (mem_space) {
 340                 /* memory */
 341                 amdgpu_ring_write(ring, addr0);
 342                 amdgpu_ring_write(ring, addr1);
 343         } else {
 344                 /* registers */
 345                 amdgpu_ring_write(ring, addr0 << 2);
 346                 amdgpu_ring_write(ring, addr1 << 2);
 347         }
 348         amdgpu_ring_write(ring, ref); /* reference */
 349         amdgpu_ring_write(ring, mask); /* mask */
 350         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 351                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(inv)); /* retry count, poll interval */
 352 }
 353
 354 /**
 355  * sdma_v4_4_2_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
 356  *
 357  * @ring: amdgpu ring pointer
 358  *
 359  * Emit an hdp flush packet on the requested DMA ring.
 360  */
 361 static void sdma_v4_4_2_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 362 {
 363         struct amdgpu_device *adev = ring->adev;
 364         u32 ref_and_mask = 0;
 365         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
 366
 367         ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me;
 368
 369         sdma_v4_4_2_wait_reg_mem(ring, 0, 1,
 370                                adev->nbio.funcs->get_hdp_flush_done_offset(adev),
 371                                adev->nbio.funcs->get_hdp_flush_req_offset(adev),
 372                                ref_and_mask, ref_and_mask, 10);
 373 }
 374
 375 /**
 376  * sdma_v4_4_2_ring_emit_fence - emit a fence on the DMA ring
 377  *
 378  * @ring: amdgpu ring pointer
 379  * @addr: address
 380  * @seq: sequence number
 381  * @flags: fence related flags
 382  *
 383  * Add a DMA fence packet to the ring to write
 384  * the fence seq number and DMA trap packet to generate
 385  * an interrupt if needed.
 386  */
 387 static void sdma_v4_4_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 388                                       unsigned flags)
 389 {
 390         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
 391         /* write the fence */
 392         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
 393         /* zero in first two bits */
 394         BUG_ON(addr & 0x3);
 395         amdgpu_ring_write(ring, lower_32_bits(addr));
 396         amdgpu_ring_write(ring, upper_32_bits(addr));
 397         amdgpu_ring_write(ring, lower_32_bits(seq));
 398
 399         /* optionally write high bits as well */
 400         if (write64bit) {
 401                 addr += 4;
 402                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
 403                 /* zero in first two bits */
 404                 BUG_ON(addr & 0x3);
 405                 amdgpu_ring_write(ring, lower_32_bits(addr));
 406                 amdgpu_ring_write(ring, upper_32_bits(addr));
 407                 amdgpu_ring_write(ring, upper_32_bits(seq));
 408         }
 409
 410         /* generate an interrupt */
 411         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
 412         amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
 413 }
 414
 415
 416 /**
 417  * sdma_v4_4_2_gfx_stop - stop the gfx async dma engines
 418  *
 419  * @adev: amdgpu_device pointer
 420  *
 421  * Stop the gfx async dma ring buffers.
 422  */
 423 static void sdma_v4_4_2_inst_gfx_stop(struct amdgpu_device *adev,
 424                                       uint32_t inst_mask)
 425 {
 426         struct amdgpu_ring *sdma[AMDGPU_MAX_SDMA_INSTANCES];
 427         u32 rb_cntl, ib_cntl;
 428         int i, unset = 0;
 429
 430         for_each_inst(i, inst_mask) {
 431                 sdma[i] = &adev->sdma.instance[i].ring;
 432
 433                 if ((adev->mman.buffer_funcs_ring == sdma[i]) && unset != 1) {
 434                         amdgpu_ttm_set_buffer_funcs_status(adev, false);
 435                         unset = 1;
 436                 }
 437
 438                 rb_cntl = RREG32_SDMA(i, regSDMA_GFX_RB_CNTL);
 439                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_ENABLE, 0);
 440                 WREG32_SDMA(i, regSDMA_GFX_RB_CNTL, rb_cntl);
 441                 ib_cntl = RREG32_SDMA(i, regSDMA_GFX_IB_CNTL);
 442                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_GFX_IB_CNTL, IB_ENABLE, 0);
 443                 WREG32_SDMA(i, regSDMA_GFX_IB_CNTL, ib_cntl);
 444         }
 445 }
 446
 447 /**
 448  * sdma_v4_4_2_rlc_stop - stop the compute async dma engines
 449  *
 450  * @adev: amdgpu_device pointer
 451  *
 452  * Stop the compute async dma queues.
 453  */
 454 static void sdma_v4_4_2_inst_rlc_stop(struct amdgpu_device *adev,
 455                                       uint32_t inst_mask)
 456 {
 457         /* XXX todo */
 458 }
 459
 460 /**
 461  * sdma_v4_4_2_page_stop - stop the page async dma engines
 462  *
 463  * @adev: amdgpu_device pointer
 464  *
 465  * Stop the page async dma ring buffers.
 466  */
 467 static void sdma_v4_4_2_inst_page_stop(struct amdgpu_device *adev,
 468                                        uint32_t inst_mask)
 469 {
 470         struct amdgpu_ring *sdma[AMDGPU_MAX_SDMA_INSTANCES];
 471         u32 rb_cntl, ib_cntl;
 472         int i;
 473         bool unset = false;
 474
 475         for_each_inst(i, inst_mask) {
 476                 sdma[i] = &adev->sdma.instance[i].page;
 477
 478                 if ((adev->mman.buffer_funcs_ring == sdma[i]) &&
 479                         (!unset)) {
 480                         amdgpu_ttm_set_buffer_funcs_status(adev, false);
 481                         unset = true;
 482                 }
 483
 484                 rb_cntl = RREG32_SDMA(i, regSDMA_PAGE_RB_CNTL);
 485                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_PAGE_RB_CNTL,
 486                                         RB_ENABLE, 0);
 487                 WREG32_SDMA(i, regSDMA_PAGE_RB_CNTL, rb_cntl);
 488                 ib_cntl = RREG32_SDMA(i, regSDMA_PAGE_IB_CNTL);
 489                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_PAGE_IB_CNTL,
 490                                         IB_ENABLE, 0);
 491                 WREG32_SDMA(i, regSDMA_PAGE_IB_CNTL, ib_cntl);
 492         }
 493 }
 494
 495 /**
 496  * sdma_v4_4_2_ctx_switch_enable - stop the async dma engines context switch
 497  *
 498  * @adev: amdgpu_device pointer
 499  * @enable: enable/disable the DMA MEs context switch.
 500  *
 501  * Halt or unhalt the async dma engines context switch.
 502  */
 503 static void sdma_v4_4_2_inst_ctx_switch_enable(struct amdgpu_device *adev,
 504                                                bool enable, uint32_t inst_mask)
 505 {
 506         u32 f32_cntl, phase_quantum = 0;
 507         int i;
 508
 509         if (amdgpu_sdma_phase_quantum) {
 510                 unsigned value = amdgpu_sdma_phase_quantum;
 511                 unsigned unit = 0;
 512
 513                 while (value > (SDMA_PHASE0_QUANTUM__VALUE_MASK >>
 514                                 SDMA_PHASE0_QUANTUM__VALUE__SHIFT)) {
 515                         value = (value + 1) >> 1;
 516                         unit++;
 517                 }
 518                 if (unit > (SDMA_PHASE0_QUANTUM__UNIT_MASK >>
 519                             SDMA_PHASE0_QUANTUM__UNIT__SHIFT)) {
 520                         value = (SDMA_PHASE0_QUANTUM__VALUE_MASK >>
 521                                  SDMA_PHASE0_QUANTUM__VALUE__SHIFT);
 522                         unit = (SDMA_PHASE0_QUANTUM__UNIT_MASK >>
 523                                 SDMA_PHASE0_QUANTUM__UNIT__SHIFT);
 524                         WARN_ONCE(1,
 525                         "clamping sdma_phase_quantum to %uK clock cycles\n",
 526                                   value << unit);
 527                 }
 528                 phase_quantum =
 529                         value << SDMA_PHASE0_QUANTUM__VALUE__SHIFT |
 530                         unit  << SDMA_PHASE0_QUANTUM__UNIT__SHIFT;
 531         }
 532
 533         for_each_inst(i, inst_mask) {
 534                 f32_cntl = RREG32_SDMA(i, regSDMA_CNTL);
 535                 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA_CNTL,
 536                                 AUTO_CTXSW_ENABLE, enable ? 1 : 0);
 537                 if (enable && amdgpu_sdma_phase_quantum) {
 538                         WREG32_SDMA(i, regSDMA_PHASE0_QUANTUM, phase_quantum);
 539                         WREG32_SDMA(i, regSDMA_PHASE1_QUANTUM, phase_quantum);
 540                         WREG32_SDMA(i, regSDMA_PHASE2_QUANTUM, phase_quantum);
 541                 }
 542                 WREG32_SDMA(i, regSDMA_CNTL, f32_cntl);
 543
 544                 /* Extend page fault timeout to avoid interrupt storm */
 545                 WREG32_SDMA(i, regSDMA_UTCL1_TIMEOUT, 0x00800080);
 546         }
 547 }
 548
 549 /**
 550  * sdma_v4_4_2_enable - stop the async dma engines
 551  *
 552  * @adev: amdgpu_device pointer
 553  * @enable: enable/disable the DMA MEs.
 554  * @inst_mask: mask of dma engine instances to be enabled
 555  *
 556  * Halt or unhalt the async dma engines.
 557  */
 558 static void sdma_v4_4_2_inst_enable(struct amdgpu_device *adev, bool enable,
 559                                     uint32_t inst_mask)
 560 {
 561         u32 f32_cntl;
 562         int i;
 563
 564         if (!enable) {
 565                 sdma_v4_4_2_inst_gfx_stop(adev, inst_mask);
 566                 sdma_v4_4_2_inst_rlc_stop(adev, inst_mask);
 567                 if (adev->sdma.has_page_queue)
 568                         sdma_v4_4_2_inst_page_stop(adev, inst_mask);
 569         }
 570
 571         for_each_inst(i, inst_mask) {
 572                 f32_cntl = RREG32_SDMA(i, regSDMA_F32_CNTL);
 573                 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA_F32_CNTL, HALT, enable ? 0 : 1);
 574                 WREG32_SDMA(i, regSDMA_F32_CNTL, f32_cntl);
 575         }
 576 }
 577
 578 /*
 579  * sdma_v4_4_2_rb_cntl - get parameters for rb_cntl
 580  */
 581 static uint32_t sdma_v4_4_2_rb_cntl(struct amdgpu_ring *ring, uint32_t rb_cntl)
 582 {
 583         /* Set ring buffer size in dwords */
 584         uint32_t rb_bufsz = order_base_2(ring->ring_size / 4);
 585
 586         barrier(); /* work around https://bugs.llvm.org/show_bug.cgi?id=42576 */
 587         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
 588 #ifdef __BIG_ENDIAN
 589         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
 590         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL,
 591                                 RPTR_WRITEBACK_SWAP_ENABLE, 1);
 592 #endif
 593         return rb_cntl;
 594 }
 595
 596 /**
 597  * sdma_v4_4_2_gfx_resume - setup and start the async dma engines
 598  *
 599  * @adev: amdgpu_device pointer
 600  * @i: instance to resume
 601  *
 602  * Set up the gfx DMA ring buffers and enable them.
 603  * Returns 0 for success, error for failure.
 604  */
 605 static void sdma_v4_4_2_gfx_resume(struct amdgpu_device *adev, unsigned int i)
 606 {
 607         struct amdgpu_ring *ring = &adev->sdma.instance[i].ring;
 608         u32 rb_cntl, ib_cntl, wptr_poll_cntl;
 609         u32 wb_offset;
 610         u32 doorbell;
 611         u32 doorbell_offset;
 612         u64 wptr_gpu_addr;
 613
 614         wb_offset = (ring->rptr_offs * 4);
 615
 616         rb_cntl = RREG32_SDMA(i, regSDMA_GFX_RB_CNTL);
 617         rb_cntl = sdma_v4_4_2_rb_cntl(ring, rb_cntl);
 618         WREG32_SDMA(i, regSDMA_GFX_RB_CNTL, rb_cntl);
 619
 620         /* Initialize the ring buffer's read and write pointers */
 621         WREG32_SDMA(i, regSDMA_GFX_RB_RPTR, 0);
 622         WREG32_SDMA(i, regSDMA_GFX_RB_RPTR_HI, 0);
 623         WREG32_SDMA(i, regSDMA_GFX_RB_WPTR, 0);
 624         WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_HI, 0);
 625
 626         /* set the wb address whether it's enabled or not */
 627         WREG32_SDMA(i, regSDMA_GFX_RB_RPTR_ADDR_HI,
 628                upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
 629         WREG32_SDMA(i, regSDMA_GFX_RB_RPTR_ADDR_LO,
 630                lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
 631
 632         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL,
 633                                 RPTR_WRITEBACK_ENABLE, 1);
 634
 635         WREG32_SDMA(i, regSDMA_GFX_RB_BASE, ring->gpu_addr >> 8);
 636         WREG32_SDMA(i, regSDMA_GFX_RB_BASE_HI, ring->gpu_addr >> 40);
 637
 638         ring->wptr = 0;
 639
 640         /* before programing wptr to a less value, need set minor_ptr_update first */
 641         WREG32_SDMA(i, regSDMA_GFX_MINOR_PTR_UPDATE, 1);
 642
 643         doorbell = RREG32_SDMA(i, regSDMA_GFX_DOORBELL);
 644         doorbell_offset = RREG32_SDMA(i, regSDMA_GFX_DOORBELL_OFFSET);
 645
 646         doorbell = REG_SET_FIELD(doorbell, SDMA_GFX_DOORBELL, ENABLE,
 647                                  ring->use_doorbell);
 648         doorbell_offset = REG_SET_FIELD(doorbell_offset,
 649                                         SDMA_GFX_DOORBELL_OFFSET,
 650                                         OFFSET, ring->doorbell_index);
 651         WREG32_SDMA(i, regSDMA_GFX_DOORBELL, doorbell);
 652         WREG32_SDMA(i, regSDMA_GFX_DOORBELL_OFFSET, doorbell_offset);
 653
 654         sdma_v4_4_2_ring_set_wptr(ring);
 655
 656         /* set minor_ptr_update to 0 after wptr programed */
 657         WREG32_SDMA(i, regSDMA_GFX_MINOR_PTR_UPDATE, 0);
 658
 659         /* setup the wptr shadow polling */
 660         wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
 661         WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_ADDR_LO,
 662                     lower_32_bits(wptr_gpu_addr));
 663         WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_ADDR_HI,
 664                     upper_32_bits(wptr_gpu_addr));
 665         wptr_poll_cntl = RREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_CNTL);
 666         wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
 667                                        SDMA_GFX_RB_WPTR_POLL_CNTL,
 668                                        F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0);
 669         WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_CNTL, wptr_poll_cntl);
 670
 671         /* enable DMA RB */
 672         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_ENABLE, 1);
 673         WREG32_SDMA(i, regSDMA_GFX_RB_CNTL, rb_cntl);
 674
 675         ib_cntl = RREG32_SDMA(i, regSDMA_GFX_IB_CNTL);
 676         ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_GFX_IB_CNTL, IB_ENABLE, 1);
 677 #ifdef __BIG_ENDIAN
 678         ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
 679 #endif
 680         /* enable DMA IBs */
 681         WREG32_SDMA(i, regSDMA_GFX_IB_CNTL, ib_cntl);
 682
 683         ring->sched.ready = true;
 684 }
 685
 686 /**
 687  * sdma_v4_4_2_page_resume - setup and start the async dma engines
 688  *
 689  * @adev: amdgpu_device pointer
 690  * @i: instance to resume
 691  *
 692  * Set up the page DMA ring buffers and enable them.
 693  * Returns 0 for success, error for failure.
 694  */
 695 static void sdma_v4_4_2_page_resume(struct amdgpu_device *adev, unsigned int i)
 696 {
 697         struct amdgpu_ring *ring = &adev->sdma.instance[i].page;
 698         u32 rb_cntl, ib_cntl, wptr_poll_cntl;
 699         u32 wb_offset;
 700         u32 doorbell;
 701         u32 doorbell_offset;
 702         u64 wptr_gpu_addr;
 703
 704         wb_offset = (ring->rptr_offs * 4);
 705
 706         rb_cntl = RREG32_SDMA(i, regSDMA_PAGE_RB_CNTL);
 707         rb_cntl = sdma_v4_4_2_rb_cntl(ring, rb_cntl);
 708         WREG32_SDMA(i, regSDMA_PAGE_RB_CNTL, rb_cntl);
 709
 710         /* Initialize the ring buffer's read and write pointers */
 711         WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR, 0);
 712         WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR_HI, 0);
 713         WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR, 0);
 714         WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_HI, 0);
 715
 716         /* set the wb address whether it's enabled or not */
 717         WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR_ADDR_HI,
 718                upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
 719         WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR_ADDR_LO,
 720                lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
 721
 722         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_PAGE_RB_CNTL,
 723                                 RPTR_WRITEBACK_ENABLE, 1);
 724
 725         WREG32_SDMA(i, regSDMA_PAGE_RB_BASE, ring->gpu_addr >> 8);
 726         WREG32_SDMA(i, regSDMA_PAGE_RB_BASE_HI, ring->gpu_addr >> 40);
 727
 728         ring->wptr = 0;
 729
 730         /* before programing wptr to a less value, need set minor_ptr_update first */
 731         WREG32_SDMA(i, regSDMA_PAGE_MINOR_PTR_UPDATE, 1);
 732
 733         doorbell = RREG32_SDMA(i, regSDMA_PAGE_DOORBELL);
 734         doorbell_offset = RREG32_SDMA(i, regSDMA_PAGE_DOORBELL_OFFSET);
 735
 736         doorbell = REG_SET_FIELD(doorbell, SDMA_PAGE_DOORBELL, ENABLE,
 737                                  ring->use_doorbell);
 738         doorbell_offset = REG_SET_FIELD(doorbell_offset,
 739                                         SDMA_PAGE_DOORBELL_OFFSET,
 740                                         OFFSET, ring->doorbell_index);
 741         WREG32_SDMA(i, regSDMA_PAGE_DOORBELL, doorbell);
 742         WREG32_SDMA(i, regSDMA_PAGE_DOORBELL_OFFSET, doorbell_offset);
 743
 744         /* paging queue doorbell range is setup at sdma_v4_4_2_gfx_resume */
 745         sdma_v4_4_2_page_ring_set_wptr(ring);
 746
 747         /* set minor_ptr_update to 0 after wptr programed */
 748         WREG32_SDMA(i, regSDMA_PAGE_MINOR_PTR_UPDATE, 0);
 749
 750         /* setup the wptr shadow polling */
 751         wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
 752         WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_ADDR_LO,
 753                     lower_32_bits(wptr_gpu_addr));
 754         WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_ADDR_HI,
 755                     upper_32_bits(wptr_gpu_addr));
 756         wptr_poll_cntl = RREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_CNTL);
 757         wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
 758                                        SDMA_PAGE_RB_WPTR_POLL_CNTL,
 759                                        F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0);
 760         WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_CNTL, wptr_poll_cntl);
 761
 762         /* enable DMA RB */
 763         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_PAGE_RB_CNTL, RB_ENABLE, 1);
 764         WREG32_SDMA(i, regSDMA_PAGE_RB_CNTL, rb_cntl);
 765
 766         ib_cntl = RREG32_SDMA(i, regSDMA_PAGE_IB_CNTL);
 767         ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_PAGE_IB_CNTL, IB_ENABLE, 1);
 768 #ifdef __BIG_ENDIAN
 769         ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_PAGE_IB_CNTL, IB_SWAP_ENABLE, 1);
 770 #endif
 771         /* enable DMA IBs */
 772         WREG32_SDMA(i, regSDMA_PAGE_IB_CNTL, ib_cntl);
 773
 774         ring->sched.ready = true;
 775 }
 776
 777 static void sdma_v4_4_2_init_pg(struct amdgpu_device *adev)
 778 {
 779
 780 }
 781
 782 /**
 783  * sdma_v4_4_2_rlc_resume - setup and start the async dma engines
 784  *
 785  * @adev: amdgpu_device pointer
 786  *
 787  * Set up the compute DMA queues and enable them.
 788  * Returns 0 for success, error for failure.
 789  */
 790 static int sdma_v4_4_2_inst_rlc_resume(struct amdgpu_device *adev,
 791                                        uint32_t inst_mask)
 792 {
 793         sdma_v4_4_2_init_pg(adev);
 794
 795         return 0;
 796 }
 797
 798 /**
 799  * sdma_v4_4_2_load_microcode - load the sDMA ME ucode
 800  *
 801  * @adev: amdgpu_device pointer
 802  *
 803  * Loads the sDMA0/1 ucode.
 804  * Returns 0 for success, -EINVAL if the ucode is not available.
 805  */
 806 static int sdma_v4_4_2_inst_load_microcode(struct amdgpu_device *adev,
 807                                            uint32_t inst_mask)
 808 {
 809         const struct sdma_firmware_header_v1_0 *hdr;
 810         const __le32 *fw_data;
 811         u32 fw_size;
 812         int i, j;
 813
 814         /* halt the MEs */
 815         sdma_v4_4_2_inst_enable(adev, false, inst_mask);
 816
 817         for_each_inst(i, inst_mask) {
 818                 if (!adev->sdma.instance[i].fw)
 819                         return -EINVAL;
 820
 821                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 822                 amdgpu_ucode_print_sdma_hdr(&hdr->header);
 823                 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 824
 825                 fw_data = (const __le32 *)
 826                         (adev->sdma.instance[i].fw->data +
 827                                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 828
 829                 WREG32_SDMA(i, regSDMA_UCODE_ADDR, 0);
 830
 831                 for (j = 0; j < fw_size; j++)
 832                         WREG32_SDMA(i, regSDMA_UCODE_DATA,
 833                                     le32_to_cpup(fw_data++));
 834
 835                 WREG32_SDMA(i, regSDMA_UCODE_ADDR,
 836                             adev->sdma.instance[i].fw_version);
 837         }
 838
 839         return 0;
 840 }
 841
 842 /**
 843  * sdma_v4_4_2_inst_start - setup and start the async dma engines
 844  *
 845  * @adev: amdgpu_device pointer
 846  *
 847  * Set up the DMA engines and enable them.
 848  * Returns 0 for success, error for failure.
 849  */
 850 static int sdma_v4_4_2_inst_start(struct amdgpu_device *adev,
 851                                   uint32_t inst_mask)
 852 {
 853         struct amdgpu_ring *ring;
 854         uint32_t tmp_mask;
 855         int i, r = 0;
 856
 857         if (amdgpu_sriov_vf(adev)) {
 858                 sdma_v4_4_2_inst_ctx_switch_enable(adev, false, inst_mask);
 859                 sdma_v4_4_2_inst_enable(adev, false, inst_mask);
 860         } else {
 861                 /* bypass sdma microcode loading on Gopher */
 862                 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP &&
 863                     adev->sdma.instance[0].fw) {
 864                         r = sdma_v4_4_2_inst_load_microcode(adev, inst_mask);
 865                         if (r)
 866                                 return r;
 867                 }
 868
 869                 /* unhalt the MEs */
 870                 sdma_v4_4_2_inst_enable(adev, true, inst_mask);
 871                 /* enable sdma ring preemption */
 872                 sdma_v4_4_2_inst_ctx_switch_enable(adev, true, inst_mask);
 873         }
 874
 875         /* start the gfx rings and rlc compute queues */
 876         tmp_mask = inst_mask;
 877         for_each_inst(i, tmp_mask) {
 878                 uint32_t temp;
 879
 880                 WREG32_SDMA(i, regSDMA_SEM_WAIT_FAIL_TIMER_CNTL, 0);
 881                 sdma_v4_4_2_gfx_resume(adev, i);
 882                 if (adev->sdma.has_page_queue)
 883                         sdma_v4_4_2_page_resume(adev, i);
 884
 885                 /* set utc l1 enable flag always to 1 */
 886                 temp = RREG32_SDMA(i, regSDMA_CNTL);
 887                 temp = REG_SET_FIELD(temp, SDMA_CNTL, UTC_L1_ENABLE, 1);
 888                 WREG32_SDMA(i, regSDMA_CNTL, temp);
 889
 890                 if (!amdgpu_sriov_vf(adev)) {
 891                         ring = &adev->sdma.instance[i].ring;
 892                         adev->nbio.funcs->sdma_doorbell_range(adev, i,
 893                                 ring->use_doorbell, ring->doorbell_index,
 894                                 adev->doorbell_index.sdma_doorbell_range);
 895
 896                         /* unhalt engine */
 897                         temp = RREG32_SDMA(i, regSDMA_F32_CNTL);
 898                         temp = REG_SET_FIELD(temp, SDMA_F32_CNTL, HALT, 0);
 899                         WREG32_SDMA(i, regSDMA_F32_CNTL, temp);
 900                 }
 901         }
 902
 903         if (amdgpu_sriov_vf(adev)) {
 904                 sdma_v4_4_2_inst_ctx_switch_enable(adev, true, inst_mask);
 905                 sdma_v4_4_2_inst_enable(adev, true, inst_mask);
 906         } else {
 907                 r = sdma_v4_4_2_inst_rlc_resume(adev, inst_mask);
 908                 if (r)
 909                         return r;
 910         }
 911
 912         tmp_mask = inst_mask;
 913         for_each_inst(i, tmp_mask) {
 914                 ring = &adev->sdma.instance[i].ring;
 915
 916                 r = amdgpu_ring_test_helper(ring);
 917                 if (r)
 918                         return r;
 919
 920                 if (adev->sdma.has_page_queue) {
 921                         struct amdgpu_ring *page = &adev->sdma.instance[i].page;
 922
 923                         r = amdgpu_ring_test_helper(page);
 924                         if (r)
 925                                 return r;
 926
 927                         if (adev->mman.buffer_funcs_ring == page)
 928                                 amdgpu_ttm_set_buffer_funcs_status(adev, true);
 929                 }
 930
 931                 if (adev->mman.buffer_funcs_ring == ring)
 932                         amdgpu_ttm_set_buffer_funcs_status(adev, true);
 933         }
 934
 935         return r;
 936 }
 937
 938 /**
 939  * sdma_v4_4_2_ring_test_ring - simple async dma engine test
 940  *
 941  * @ring: amdgpu_ring structure holding ring information
 942  *
 943  * Test the DMA engine by writing using it to write an
 944  * value to memory.
 945  * Returns 0 for success, error for failure.
 946  */
 947 static int sdma_v4_4_2_ring_test_ring(struct amdgpu_ring *ring)
 948 {
 949         struct amdgpu_device *adev = ring->adev;
 950         unsigned i;
 951         unsigned index;
 952         int r;
 953         u32 tmp;
 954         u64 gpu_addr;
 955
 956         r = amdgpu_device_wb_get(adev, &index);
 957         if (r)
 958                 return r;
 959
 960         gpu_addr = adev->wb.gpu_addr + (index * 4);
 961         tmp = 0xCAFEDEAD;
 962         adev->wb.wb[index] = cpu_to_le32(tmp);
 963
 964         r = amdgpu_ring_alloc(ring, 5);
 965         if (r)
 966                 goto error_free_wb;
 967
 968         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 969                           SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
 970         amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
 971         amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
 972         amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
 973         amdgpu_ring_write(ring, 0xDEADBEEF);
 974         amdgpu_ring_commit(ring);
 975
 976         for (i = 0; i < adev->usec_timeout; i++) {
 977                 tmp = le32_to_cpu(adev->wb.wb[index]);
 978                 if (tmp == 0xDEADBEEF)
 979                         break;
 980                 udelay(1);
 981         }
 982
 983         if (i >= adev->usec_timeout)
 984                 r = -ETIMEDOUT;
 985
 986 error_free_wb:
 987         amdgpu_device_wb_free(adev, index);
 988         return r;
 989 }
 990
 991 /**
 992  * sdma_v4_4_2_ring_test_ib - test an IB on the DMA engine
 993  *
 994  * @ring: amdgpu_ring structure holding ring information
 995  * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
 996  *
 997  * Test a simple IB in the DMA ring.
 998  * Returns 0 on success, error on failure.
 999  */
1000 static int sdma_v4_4_2_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1001 {
1002         struct amdgpu_device *adev = ring->adev;
1003         struct amdgpu_ib ib;
1004         struct dma_fence *f = NULL;
1005         unsigned index;
1006         long r;
1007         u32 tmp = 0;
1008         u64 gpu_addr;
1009
1010         r = amdgpu_device_wb_get(adev, &index);
1011         if (r)
1012                 return r;
1013
1014         gpu_addr = adev->wb.gpu_addr + (index * 4);
1015         tmp = 0xCAFEDEAD;
1016         adev->wb.wb[index] = cpu_to_le32(tmp);
1017         memset(&ib, 0, sizeof(ib));
1018         r = amdgpu_ib_get(adev, NULL, 256,
1019                                         AMDGPU_IB_POOL_DIRECT, &ib);
1020         if (r)
1021                 goto err0;
1022
1023         ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1024                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1025         ib.ptr[1] = lower_32_bits(gpu_addr);
1026         ib.ptr[2] = upper_32_bits(gpu_addr);
1027         ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
1028         ib.ptr[4] = 0xDEADBEEF;
1029         ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1030         ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1031         ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1032         ib.length_dw = 8;
1033
1034         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1035         if (r)
1036                 goto err1;
1037
1038         r = dma_fence_wait_timeout(f, false, timeout);
1039         if (r == 0) {
1040                 r = -ETIMEDOUT;
1041                 goto err1;
1042         } else if (r < 0) {
1043                 goto err1;
1044         }
1045         tmp = le32_to_cpu(adev->wb.wb[index]);
1046         if (tmp == 0xDEADBEEF)
1047                 r = 0;
1048         else
1049                 r = -EINVAL;
1050
1051 err1:
1052         amdgpu_ib_free(adev, &ib, NULL);
1053         dma_fence_put(f);
1054 err0:
1055         amdgpu_device_wb_free(adev, index);
1056         return r;
1057 }
1058
1059
1060 /**
1061  * sdma_v4_4_2_vm_copy_pte - update PTEs by copying them from the GART
1062  *
1063  * @ib: indirect buffer to fill with commands
1064  * @pe: addr of the page entry
1065  * @src: src addr to copy from
1066  * @count: number of page entries to update
1067  *
1068  * Update PTEs by copying them from the GART using sDMA.
1069  */
1070 static void sdma_v4_4_2_vm_copy_pte(struct amdgpu_ib *ib,
1071                                   uint64_t pe, uint64_t src,
1072                                   unsigned count)
1073 {
1074         unsigned bytes = count * 8;
1075
1076         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1077                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1078         ib->ptr[ib->length_dw++] = bytes - 1;
1079         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1080         ib->ptr[ib->length_dw++] = lower_32_bits(src);
1081         ib->ptr[ib->length_dw++] = upper_32_bits(src);
1082         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1083         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1084
1085 }
1086
1087 /**
1088  * sdma_v4_4_2_vm_write_pte - update PTEs by writing them manually
1089  *
1090  * @ib: indirect buffer to fill with commands
1091  * @pe: addr of the page entry
1092  * @value: dst addr to write into pe
1093  * @count: number of page entries to update
1094  * @incr: increase next addr by incr bytes
1095  *
1096  * Update PTEs by writing them manually using sDMA.
1097  */
1098 static void sdma_v4_4_2_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1099                                    uint64_t value, unsigned count,
1100                                    uint32_t incr)
1101 {
1102         unsigned ndw = count * 2;
1103
1104         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1105                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1106         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1107         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1108         ib->ptr[ib->length_dw++] = ndw - 1;
1109         for (; ndw > 0; ndw -= 2) {
1110                 ib->ptr[ib->length_dw++] = lower_32_bits(value);
1111                 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1112                 value += incr;
1113         }
1114 }
1115
1116 /**
1117  * sdma_v4_4_2_vm_set_pte_pde - update the page tables using sDMA
1118  *
1119  * @ib: indirect buffer to fill with commands
1120  * @pe: addr of the page entry
1121  * @addr: dst addr to write into pe
1122  * @count: number of page entries to update
1123  * @incr: increase next addr by incr bytes
1124  * @flags: access flags
1125  *
1126  * Update the page tables using sDMA.
1127  */
1128 static void sdma_v4_4_2_vm_set_pte_pde(struct amdgpu_ib *ib,
1129                                      uint64_t pe,
1130                                      uint64_t addr, unsigned count,
1131                                      uint32_t incr, uint64_t flags)
1132 {
1133         /* for physically contiguous pages (vram) */
1134         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE);
1135         ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1136         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1137         ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1138         ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1139         ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1140         ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1141         ib->ptr[ib->length_dw++] = incr; /* increment size */
1142         ib->ptr[ib->length_dw++] = 0;
1143         ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1144 }
1145
1146 /**
1147  * sdma_v4_4_2_ring_pad_ib - pad the IB to the required number of dw
1148  *
1149  * @ring: amdgpu_ring structure holding ring information
1150  * @ib: indirect buffer to fill with padding
1151  */
1152 static void sdma_v4_4_2_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1153 {
1154         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1155         u32 pad_count;
1156         int i;
1157
1158         pad_count = (-ib->length_dw) & 7;
1159         for (i = 0; i < pad_count; i++)
1160                 if (sdma && sdma->burst_nop && (i == 0))
1161                         ib->ptr[ib->length_dw++] =
1162                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1163                                 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1164                 else
1165                         ib->ptr[ib->length_dw++] =
1166                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1167 }
1168
1169
1170 /**
1171  * sdma_v4_4_2_ring_emit_pipeline_sync - sync the pipeline
1172  *
1173  * @ring: amdgpu_ring pointer
1174  *
1175  * Make sure all previous operations are completed (CIK).
1176  */
1177 static void sdma_v4_4_2_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1178 {
1179         uint32_t seq = ring->fence_drv.sync_seq;
1180         uint64_t addr = ring->fence_drv.gpu_addr;
1181
1182         /* wait for idle */
1183         sdma_v4_4_2_wait_reg_mem(ring, 1, 0,
1184                                addr & 0xfffffffc,
1185                                upper_32_bits(addr) & 0xffffffff,
1186                                seq, 0xffffffff, 4);
1187 }
1188
1189
1190 /**
1191  * sdma_v4_4_2_ring_emit_vm_flush - vm flush using sDMA
1192  *
1193  * @ring: amdgpu_ring pointer
1194  * @vmid: vmid number to use
1195  * @pd_addr: address
1196  *
1197  * Update the page table base and flush the VM TLB
1198  * using sDMA.
1199  */
1200 static void sdma_v4_4_2_ring_emit_vm_flush(struct amdgpu_ring *ring,
1201                                          unsigned vmid, uint64_t pd_addr)
1202 {
1203         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1204 }
1205
1206 static void sdma_v4_4_2_ring_emit_wreg(struct amdgpu_ring *ring,
1207                                      uint32_t reg, uint32_t val)
1208 {
1209         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1210                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1211         amdgpu_ring_write(ring, reg);
1212         amdgpu_ring_write(ring, val);
1213 }
1214
1215 static void sdma_v4_4_2_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1216                                          uint32_t val, uint32_t mask)
1217 {
1218         sdma_v4_4_2_wait_reg_mem(ring, 0, 0, reg, 0, val, mask, 10);
1219 }
1220
1221 static bool sdma_v4_4_2_fw_support_paging_queue(struct amdgpu_device *adev)
1222 {
1223         switch (adev->ip_versions[SDMA0_HWIP][0]) {
1224         case IP_VERSION(4, 4, 2):
1225                 return false;
1226         default:
1227                 return false;
1228         }
1229 }
1230
1231 static int sdma_v4_4_2_early_init(void *handle)
1232 {
1233         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1234         int r;
1235
1236         r = sdma_v4_4_2_init_microcode(adev);
1237         if (r) {
1238                 DRM_ERROR("Failed to load sdma firmware!\n");
1239                 return r;
1240         }
1241
1242         /* TODO: Page queue breaks driver reload under SRIOV */
1243         if (sdma_v4_4_2_fw_support_paging_queue(adev))
1244                 adev->sdma.has_page_queue = true;
1245
1246         sdma_v4_4_2_set_ring_funcs(adev);
1247         sdma_v4_4_2_set_buffer_funcs(adev);
1248         sdma_v4_4_2_set_vm_pte_funcs(adev);
1249         sdma_v4_4_2_set_irq_funcs(adev);
1250
1251         return 0;
1252 }
1253
1254 #if 0
1255 static int sdma_v4_4_2_process_ras_data_cb(struct amdgpu_device *adev,
1256                 void *err_data,
1257                 struct amdgpu_iv_entry *entry);
1258 #endif
1259
1260 static int sdma_v4_4_2_late_init(void *handle)
1261 {
1262         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1263 #if 0
1264         struct ras_ih_if ih_info = {
1265                 .cb = sdma_v4_4_2_process_ras_data_cb,
1266         };
1267 #endif
1268         if (!amdgpu_persistent_edc_harvesting_supported(adev)) {
1269                 if (adev->sdma.ras && adev->sdma.ras->ras_block.hw_ops &&
1270                     adev->sdma.ras->ras_block.hw_ops->reset_ras_error_count)
1271                         adev->sdma.ras->ras_block.hw_ops->reset_ras_error_count(adev);
1272         }
1273
1274         return 0;
1275 }
1276
1277 static int sdma_v4_4_2_sw_init(void *handle)
1278 {
1279         struct amdgpu_ring *ring;
1280         int r, i;
1281         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1282         u32 aid_id;
1283
1284         /* SDMA trap event */
1285         for (i = 0; i < adev->sdma.num_inst_per_aid; i++) {
1286                 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i),
1287                                       SDMA0_4_0__SRCID__SDMA_TRAP,
1288                                       &adev->sdma.trap_irq);
1289                 if (r)
1290                         return r;
1291         }
1292
1293         /* SDMA SRAM ECC event */
1294         for (i = 0; i < adev->sdma.num_inst_per_aid; i++) {
1295                 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i),
1296                                       SDMA0_4_0__SRCID__SDMA_SRAM_ECC,
1297                                       &adev->sdma.ecc_irq);
1298                 if (r)
1299                         return r;
1300         }
1301
1302         /* SDMA VM_HOLE/DOORBELL_INV/POLL_TIMEOUT/SRBM_WRITE_PROTECTION event*/
1303         for (i = 0; i < adev->sdma.num_inst_per_aid; i++) {
1304                 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i),
1305                                       SDMA0_4_0__SRCID__SDMA_VM_HOLE,
1306                                       &adev->sdma.vm_hole_irq);
1307                 if (r)
1308                         return r;
1309
1310                 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i),
1311                                       SDMA0_4_0__SRCID__SDMA_DOORBELL_INVALID,
1312                                       &adev->sdma.doorbell_invalid_irq);
1313                 if (r)
1314                         return r;
1315
1316                 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i),
1317                                       SDMA0_4_0__SRCID__SDMA_POLL_TIMEOUT,
1318                                       &adev->sdma.pool_timeout_irq);
1319                 if (r)
1320                         return r;
1321
1322                 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i),
1323                                       SDMA0_4_0__SRCID__SDMA_SRBMWRITE,
1324                                       &adev->sdma.srbm_write_irq);
1325                 if (r)
1326                         return r;
1327         }
1328
1329         for (i = 0; i < adev->sdma.num_instances; i++) {
1330                 ring = &adev->sdma.instance[i].ring;
1331                 ring->ring_obj = NULL;
1332                 ring->use_doorbell = true;
1333                 aid_id = adev->sdma.instance[i].aid_id;
1334
1335                 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i,
1336                                 ring->use_doorbell?"true":"false");
1337
1338                 /* doorbell size is 2 dwords, get DWORD offset */
1339                 ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1;
1340                 ring->vm_hub = AMDGPU_MMHUB0(aid_id);
1341
1342                 sprintf(ring->name, "sdma%d.%d", aid_id,
1343                                 i % adev->sdma.num_inst_per_aid);
1344                 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq,
1345                                      AMDGPU_SDMA_IRQ_INSTANCE0 + i,
1346                                      AMDGPU_RING_PRIO_DEFAULT, NULL);
1347                 if (r)
1348                         return r;
1349
1350                 if (adev->sdma.has_page_queue) {
1351                         ring = &adev->sdma.instance[i].page;
1352                         ring->ring_obj = NULL;
1353                         ring->use_doorbell = true;
1354
1355                         /* doorbell index of page queue is assigned right after
1356                          * gfx queue on the same instance
1357                          */
1358                         ring->doorbell_index =
1359                                 (adev->doorbell_index.sdma_engine[i] + 1) << 1;
1360                         ring->vm_hub = AMDGPU_MMHUB0(aid_id);
1361
1362                         sprintf(ring->name, "page%d.%d", aid_id,
1363                                         i % adev->sdma.num_inst_per_aid);
1364                         r = amdgpu_ring_init(adev, ring, 1024,
1365                                              &adev->sdma.trap_irq,
1366                                              AMDGPU_SDMA_IRQ_INSTANCE0 + i,
1367                                              AMDGPU_RING_PRIO_DEFAULT, NULL);
1368                         if (r)
1369                                 return r;
1370                 }
1371         }
1372
1373         return r;
1374 }
1375
1376 static int sdma_v4_4_2_sw_fini(void *handle)
1377 {
1378         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1379         int i;
1380
1381         for (i = 0; i < adev->sdma.num_instances; i++) {
1382                 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1383                 if (adev->sdma.has_page_queue)
1384                         amdgpu_ring_fini(&adev->sdma.instance[i].page);
1385         }
1386
1387         if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 4, 2))
1388                 amdgpu_sdma_destroy_inst_ctx(adev, true);
1389         else
1390                 amdgpu_sdma_destroy_inst_ctx(adev, false);
1391
1392         return 0;
1393 }
1394
1395 static int sdma_v4_4_2_hw_init(void *handle)
1396 {
1397         int r;
1398         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1399         uint32_t inst_mask;
1400
1401         inst_mask = GENMASK(adev->sdma.num_instances - 1, 0);
1402         if (!amdgpu_sriov_vf(adev))
1403                 sdma_v4_4_2_inst_init_golden_registers(adev, inst_mask);
1404
1405         r = sdma_v4_4_2_inst_start(adev, inst_mask);
1406
1407         return r;
1408 }
1409
1410 static int sdma_v4_4_2_hw_fini(void *handle)
1411 {
1412         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1413         uint32_t inst_mask;
1414         int i;
1415
1416         if (amdgpu_sriov_vf(adev))
1417                 return 0;
1418
1419         inst_mask = GENMASK(adev->sdma.num_instances - 1, 0);
1420         for (i = 0; i < adev->sdma.num_instances; i++) {
1421                 amdgpu_irq_put(adev, &adev->sdma.ecc_irq,
1422                                AMDGPU_SDMA_IRQ_INSTANCE0 + i);
1423         }
1424
1425         sdma_v4_4_2_inst_ctx_switch_enable(adev, false, inst_mask);
1426         sdma_v4_4_2_inst_enable(adev, false, inst_mask);
1427
1428         return 0;
1429 }
1430
1431 static int sdma_v4_4_2_set_clockgating_state(void *handle,
1432                                              enum amd_clockgating_state state);
1433
1434 static int sdma_v4_4_2_suspend(void *handle)
1435 {
1436         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1437
1438         return sdma_v4_4_2_hw_fini(adev);
1439 }
1440
1441 static int sdma_v4_4_2_resume(void *handle)
1442 {
1443         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1444
1445         return sdma_v4_4_2_hw_init(adev);
1446 }
1447
1448 static bool sdma_v4_4_2_is_idle(void *handle)
1449 {
1450         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1451         u32 i;
1452
1453         for (i = 0; i < adev->sdma.num_instances; i++) {
1454                 u32 tmp = RREG32_SDMA(i, regSDMA_STATUS_REG);
1455
1456                 if (!(tmp & SDMA_STATUS_REG__IDLE_MASK))
1457                         return false;
1458         }
1459
1460         return true;
1461 }
1462
1463 static int sdma_v4_4_2_wait_for_idle(void *handle)
1464 {
1465         unsigned i, j;
1466         u32 sdma[AMDGPU_MAX_SDMA_INSTANCES];
1467         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1468
1469         for (i = 0; i < adev->usec_timeout; i++) {
1470                 for (j = 0; j < adev->sdma.num_instances; j++) {
1471                         sdma[j] = RREG32_SDMA(j, regSDMA_STATUS_REG);
1472                         if (!(sdma[j] & SDMA_STATUS_REG__IDLE_MASK))
1473                                 break;
1474                 }
1475                 if (j == adev->sdma.num_instances)
1476                         return 0;
1477                 udelay(1);
1478         }
1479         return -ETIMEDOUT;
1480 }
1481
1482 static int sdma_v4_4_2_soft_reset(void *handle)
1483 {
1484         /* todo */
1485
1486         return 0;
1487 }
1488
1489 static int sdma_v4_4_2_set_trap_irq_state(struct amdgpu_device *adev,
1490                                         struct amdgpu_irq_src *source,
1491                                         unsigned type,
1492                                         enum amdgpu_interrupt_state state)
1493 {
1494         u32 sdma_cntl;
1495
1496         sdma_cntl = RREG32_SDMA(type, regSDMA_CNTL);
1497         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA_CNTL, TRAP_ENABLE,
1498                        state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1499         WREG32_SDMA(type, regSDMA_CNTL, sdma_cntl);
1500
1501         return 0;
1502 }
1503
1504 static int sdma_v4_4_2_process_trap_irq(struct amdgpu_device *adev,
1505                                       struct amdgpu_irq_src *source,
1506                                       struct amdgpu_iv_entry *entry)
1507 {
1508         uint32_t instance, i;
1509
1510         DRM_DEBUG("IH: SDMA trap\n");
1511         instance = sdma_v4_4_2_irq_id_to_seq(entry->client_id);
1512
1513         /* Client id gives the SDMA instance in AID. To know the exact SDMA
1514          * instance, interrupt entry gives the node id which corresponds to the AID instance.
1515          * Match node id with the AID id associated with the SDMA instance. */
1516         for (i = instance; i < adev->sdma.num_instances;
1517              i += adev->sdma.num_inst_per_aid) {
1518                 if (adev->sdma.instance[i].aid_id ==
1519                     node_id_to_phys_map[entry->node_id])
1520                         break;
1521         }
1522
1523         if (i >= adev->sdma.num_instances) {
1524                 dev_WARN_ONCE(
1525                         adev->dev, 1,
1526                         "Couldn't find the right sdma instance in trap handler");
1527                 return 0;
1528         }
1529
1530         switch (entry->ring_id) {
1531         case 0:
1532                 amdgpu_fence_process(&adev->sdma.instance[i].ring);
1533                 break;
1534         default:
1535                 break;
1536         }
1537         return 0;
1538 }
1539
1540 #if 0
1541 static int sdma_v4_4_2_process_ras_data_cb(struct amdgpu_device *adev,
1542                 void *err_data,
1543                 struct amdgpu_iv_entry *entry)
1544 {
1545         int instance;
1546
1547         /* When “Full RAS” is enabled, the per-IP interrupt sources should
1548          * be disabled and the driver should only look for the aggregated
1549          * interrupt via sync flood
1550          */
1551         if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX))
1552                 goto out;
1553
1554         instance = sdma_v4_4_2_irq_id_to_seq(entry->client_id);
1555         if (instance < 0)
1556                 goto out;
1557
1558         amdgpu_sdma_process_ras_data_cb(adev, err_data, entry);
1559
1560 out:
1561         return AMDGPU_RAS_SUCCESS;
1562 }
1563 #endif
1564
1565 static int sdma_v4_4_2_process_illegal_inst_irq(struct amdgpu_device *adev,
1566                                               struct amdgpu_irq_src *source,
1567                                               struct amdgpu_iv_entry *entry)
1568 {
1569         int instance;
1570
1571         DRM_ERROR("Illegal instruction in SDMA command stream\n");
1572
1573         instance = sdma_v4_4_2_irq_id_to_seq(entry->client_id);
1574         if (instance < 0)
1575                 return 0;
1576
1577         switch (entry->ring_id) {
1578         case 0:
1579                 drm_sched_fault(&adev->sdma.instance[instance].ring.sched);
1580                 break;
1581         }
1582         return 0;
1583 }
1584
1585 static int sdma_v4_4_2_set_ecc_irq_state(struct amdgpu_device *adev,
1586                                         struct amdgpu_irq_src *source,
1587                                         unsigned type,
1588                                         enum amdgpu_interrupt_state state)
1589 {
1590         u32 sdma_edc_config;
1591
1592         sdma_edc_config = RREG32_SDMA(type, regCC_SDMA_EDC_CONFIG);
1593         /*
1594          * FIXME: This was inherited from Aldebaran, but no this field
1595          * definition in the regspec of both Aldebaran and SDMA 4.4.2
1596          */
1597         sdma_edc_config |= (state == AMDGPU_IRQ_STATE_ENABLE) ? (1 << 2) : 0;
1598         WREG32_SDMA(type, regCC_SDMA_EDC_CONFIG, sdma_edc_config);
1599
1600         return 0;
1601 }
1602
1603 static int sdma_v4_4_2_print_iv_entry(struct amdgpu_device *adev,
1604                                               struct amdgpu_iv_entry *entry)
1605 {
1606         int instance;
1607         struct amdgpu_task_info task_info;
1608         u64 addr;
1609
1610         instance = sdma_v4_4_2_irq_id_to_seq(entry->client_id);
1611         if (instance < 0 || instance >= adev->sdma.num_instances) {
1612                 dev_err(adev->dev, "sdma instance invalid %d\n", instance);
1613                 return -EINVAL;
1614         }
1615
1616         addr = (u64)entry->src_data[0] << 12;
1617         addr |= ((u64)entry->src_data[1] & 0xf) << 44;
1618
1619         memset(&task_info, 0, sizeof(struct amdgpu_task_info));
1620         amdgpu_vm_get_task_info(adev, entry->pasid, &task_info);
1621
1622         dev_dbg_ratelimited(adev->dev,
1623                    "[sdma%d] address:0x%016llx src_id:%u ring:%u vmid:%u "
1624                    "pasid:%u, for process %s pid %d thread %s pid %d\n",
1625                    instance, addr, entry->src_id, entry->ring_id, entry->vmid,
1626                    entry->pasid, task_info.process_name, task_info.tgid,
1627                    task_info.task_name, task_info.pid);
1628         return 0;
1629 }
1630
1631 static int sdma_v4_4_2_process_vm_hole_irq(struct amdgpu_device *adev,
1632                                               struct amdgpu_irq_src *source,
1633                                               struct amdgpu_iv_entry *entry)
1634 {
1635         dev_dbg_ratelimited(adev->dev, "MC or SEM address in VM hole\n");
1636         sdma_v4_4_2_print_iv_entry(adev, entry);
1637         return 0;
1638 }
1639
1640 static int sdma_v4_4_2_process_doorbell_invalid_irq(struct amdgpu_device *adev,
1641                                               struct amdgpu_irq_src *source,
1642                                               struct amdgpu_iv_entry *entry)
1643 {
1644
1645         dev_dbg_ratelimited(adev->dev, "SDMA received a doorbell from BIF with byte_enable !=0xff\n");
1646         sdma_v4_4_2_print_iv_entry(adev, entry);
1647         return 0;
1648 }
1649
1650 static int sdma_v4_4_2_process_pool_timeout_irq(struct amdgpu_device *adev,
1651                                               struct amdgpu_irq_src *source,
1652                                               struct amdgpu_iv_entry *entry)
1653 {
1654         dev_dbg_ratelimited(adev->dev,
1655                 "Polling register/memory timeout executing POLL_REG/MEM with finite timer\n");
1656         sdma_v4_4_2_print_iv_entry(adev, entry);
1657         return 0;
1658 }
1659
1660 static int sdma_v4_4_2_process_srbm_write_irq(struct amdgpu_device *adev,
1661                                               struct amdgpu_irq_src *source,
1662                                               struct amdgpu_iv_entry *entry)
1663 {
1664         dev_dbg_ratelimited(adev->dev,
1665                 "SDMA gets an Register Write SRBM_WRITE command in non-privilege command buffer\n");
1666         sdma_v4_4_2_print_iv_entry(adev, entry);
1667         return 0;
1668 }
1669
1670 static void sdma_v4_4_2_inst_update_medium_grain_light_sleep(
1671         struct amdgpu_device *adev, bool enable, uint32_t inst_mask)
1672 {
1673         uint32_t data, def;
1674         int i;
1675
1676         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
1677                 for_each_inst(i, inst_mask) {
1678                         /* 1-not override: enable sdma mem light sleep */
1679                         def = data = RREG32_SDMA(i, regSDMA_POWER_CNTL);
1680                         data |= SDMA_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1681                         if (def != data)
1682                                 WREG32_SDMA(i, regSDMA_POWER_CNTL, data);
1683                 }
1684         } else {
1685                 for_each_inst(i, inst_mask) {
1686                         /* 0-override:disable sdma mem light sleep */
1687                         def = data = RREG32_SDMA(i, regSDMA_POWER_CNTL);
1688                         data &= ~SDMA_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1689                         if (def != data)
1690                                 WREG32_SDMA(i, regSDMA_POWER_CNTL, data);
1691                 }
1692         }
1693 }
1694
1695 static void sdma_v4_4_2_inst_update_medium_grain_clock_gating(
1696         struct amdgpu_device *adev, bool enable, uint32_t inst_mask)
1697 {
1698         uint32_t data, def;
1699         int i;
1700
1701         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
1702                 for_each_inst(i, inst_mask) {
1703                         def = data = RREG32_SDMA(i, regSDMA_CLK_CTRL);
1704                         data &= ~(SDMA_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1705                                   SDMA_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1706                                   SDMA_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1707                                   SDMA_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1708                                   SDMA_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1709                                   SDMA_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1710                                   SDMA_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1711                                   SDMA_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1712                         if (def != data)
1713                                 WREG32_SDMA(i, regSDMA_CLK_CTRL, data);
1714                 }
1715         } else {
1716                 for_each_inst(i, inst_mask) {
1717                         def = data = RREG32_SDMA(i, regSDMA_CLK_CTRL);
1718                         data |= (SDMA_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1719                                  SDMA_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1720                                  SDMA_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1721                                  SDMA_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1722                                  SDMA_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1723                                  SDMA_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1724                                  SDMA_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1725                                  SDMA_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1726                         if (def != data)
1727                                 WREG32_SDMA(i, regSDMA_CLK_CTRL, data);
1728                 }
1729         }
1730 }
1731
1732 static int sdma_v4_4_2_set_clockgating_state(void *handle,
1733                                           enum amd_clockgating_state state)
1734 {
1735         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1736         uint32_t inst_mask;
1737
1738         if (amdgpu_sriov_vf(adev))
1739                 return 0;
1740
1741         inst_mask = GENMASK(adev->sdma.num_instances - 1, 0);
1742
1743         sdma_v4_4_2_inst_update_medium_grain_clock_gating(
1744                 adev, state == AMD_CG_STATE_GATE, inst_mask);
1745         sdma_v4_4_2_inst_update_medium_grain_light_sleep(
1746                 adev, state == AMD_CG_STATE_GATE, inst_mask);
1747         return 0;
1748 }
1749
1750 static int sdma_v4_4_2_set_powergating_state(void *handle,
1751                                           enum amd_powergating_state state)
1752 {
1753         return 0;
1754 }
1755
1756 static void sdma_v4_4_2_get_clockgating_state(void *handle, u64 *flags)
1757 {
1758         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1759         int data;
1760
1761         if (amdgpu_sriov_vf(adev))
1762                 *flags = 0;
1763
1764         /* AMD_CG_SUPPORT_SDMA_MGCG */
1765         data = RREG32(SOC15_REG_OFFSET(SDMA0, GET_INST(SDMA0, 0), regSDMA_CLK_CTRL));
1766         if (!(data & SDMA_CLK_CTRL__SOFT_OVERRIDE7_MASK))
1767                 *flags |= AMD_CG_SUPPORT_SDMA_MGCG;
1768
1769         /* AMD_CG_SUPPORT_SDMA_LS */
1770         data = RREG32(SOC15_REG_OFFSET(SDMA0, GET_INST(SDMA0, 0), regSDMA_POWER_CNTL));
1771         if (data & SDMA_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
1772                 *flags |= AMD_CG_SUPPORT_SDMA_LS;
1773 }
1774
1775 const struct amd_ip_funcs sdma_v4_4_2_ip_funcs = {
1776         .name = "sdma_v4_4_2",
1777         .early_init = sdma_v4_4_2_early_init,
1778         .late_init = sdma_v4_4_2_late_init,
1779         .sw_init = sdma_v4_4_2_sw_init,
1780         .sw_fini = sdma_v4_4_2_sw_fini,
1781         .hw_init = sdma_v4_4_2_hw_init,
1782         .hw_fini = sdma_v4_4_2_hw_fini,
1783         .suspend = sdma_v4_4_2_suspend,
1784         .resume = sdma_v4_4_2_resume,
1785         .is_idle = sdma_v4_4_2_is_idle,
1786         .wait_for_idle = sdma_v4_4_2_wait_for_idle,
1787         .soft_reset = sdma_v4_4_2_soft_reset,
1788         .set_clockgating_state = sdma_v4_4_2_set_clockgating_state,
1789         .set_powergating_state = sdma_v4_4_2_set_powergating_state,
1790         .get_clockgating_state = sdma_v4_4_2_get_clockgating_state,
1791 };
1792
1793 static const struct amdgpu_ring_funcs sdma_v4_4_2_ring_funcs = {
1794         .type = AMDGPU_RING_TYPE_SDMA,
1795         .align_mask = 0xf,
1796         .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1797         .support_64bit_ptrs = true,
1798         .get_rptr = sdma_v4_4_2_ring_get_rptr,
1799         .get_wptr = sdma_v4_4_2_ring_get_wptr,
1800         .set_wptr = sdma_v4_4_2_ring_set_wptr,
1801         .emit_frame_size =
1802                 6 + /* sdma_v4_4_2_ring_emit_hdp_flush */
1803                 3 + /* hdp invalidate */
1804                 6 + /* sdma_v4_4_2_ring_emit_pipeline_sync */
1805                 /* sdma_v4_4_2_ring_emit_vm_flush */
1806                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1807                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
1808                 10 + 10 + 10, /* sdma_v4_4_2_ring_emit_fence x3 for user fence, vm fence */
1809         .emit_ib_size = 7 + 6, /* sdma_v4_4_2_ring_emit_ib */
1810         .emit_ib = sdma_v4_4_2_ring_emit_ib,
1811         .emit_fence = sdma_v4_4_2_ring_emit_fence,
1812         .emit_pipeline_sync = sdma_v4_4_2_ring_emit_pipeline_sync,
1813         .emit_vm_flush = sdma_v4_4_2_ring_emit_vm_flush,
1814         .emit_hdp_flush = sdma_v4_4_2_ring_emit_hdp_flush,
1815         .test_ring = sdma_v4_4_2_ring_test_ring,
1816         .test_ib = sdma_v4_4_2_ring_test_ib,
1817         .insert_nop = sdma_v4_4_2_ring_insert_nop,
1818         .pad_ib = sdma_v4_4_2_ring_pad_ib,
1819         .emit_wreg = sdma_v4_4_2_ring_emit_wreg,
1820         .emit_reg_wait = sdma_v4_4_2_ring_emit_reg_wait,
1821         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1822 };
1823
1824 static const struct amdgpu_ring_funcs sdma_v4_4_2_page_ring_funcs = {
1825         .type = AMDGPU_RING_TYPE_SDMA,
1826         .align_mask = 0xf,
1827         .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1828         .support_64bit_ptrs = true,
1829         .get_rptr = sdma_v4_4_2_ring_get_rptr,
1830         .get_wptr = sdma_v4_4_2_page_ring_get_wptr,
1831         .set_wptr = sdma_v4_4_2_page_ring_set_wptr,
1832         .emit_frame_size =
1833                 6 + /* sdma_v4_4_2_ring_emit_hdp_flush */
1834                 3 + /* hdp invalidate */
1835                 6 + /* sdma_v4_4_2_ring_emit_pipeline_sync */
1836                 /* sdma_v4_4_2_ring_emit_vm_flush */
1837                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1838                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
1839                 10 + 10 + 10, /* sdma_v4_4_2_ring_emit_fence x3 for user fence, vm fence */
1840         .emit_ib_size = 7 + 6, /* sdma_v4_4_2_ring_emit_ib */
1841         .emit_ib = sdma_v4_4_2_ring_emit_ib,
1842         .emit_fence = sdma_v4_4_2_ring_emit_fence,
1843         .emit_pipeline_sync = sdma_v4_4_2_ring_emit_pipeline_sync,
1844         .emit_vm_flush = sdma_v4_4_2_ring_emit_vm_flush,
1845         .emit_hdp_flush = sdma_v4_4_2_ring_emit_hdp_flush,
1846         .test_ring = sdma_v4_4_2_ring_test_ring,
1847         .test_ib = sdma_v4_4_2_ring_test_ib,
1848         .insert_nop = sdma_v4_4_2_ring_insert_nop,
1849         .pad_ib = sdma_v4_4_2_ring_pad_ib,
1850         .emit_wreg = sdma_v4_4_2_ring_emit_wreg,
1851         .emit_reg_wait = sdma_v4_4_2_ring_emit_reg_wait,
1852         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1853 };
1854
1855 static void sdma_v4_4_2_set_ring_funcs(struct amdgpu_device *adev)
1856 {
1857         int i, dev_inst;
1858
1859         for (i = 0; i < adev->sdma.num_instances; i++) {
1860                 adev->sdma.instance[i].ring.funcs = &sdma_v4_4_2_ring_funcs;
1861                 adev->sdma.instance[i].ring.me = i;
1862                 if (adev->sdma.has_page_queue) {
1863                         adev->sdma.instance[i].page.funcs =
1864                                 &sdma_v4_4_2_page_ring_funcs;
1865                         adev->sdma.instance[i].page.me = i;
1866                 }
1867
1868                 dev_inst = GET_INST(SDMA0, i);
1869                 /* AID to which SDMA belongs depends on physical instance */
1870                 adev->sdma.instance[i].aid_id =
1871                         dev_inst / adev->sdma.num_inst_per_aid;
1872         }
1873 }
1874
1875 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_trap_irq_funcs = {
1876         .set = sdma_v4_4_2_set_trap_irq_state,
1877         .process = sdma_v4_4_2_process_trap_irq,
1878 };
1879
1880 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_illegal_inst_irq_funcs = {
1881         .process = sdma_v4_4_2_process_illegal_inst_irq,
1882 };
1883
1884 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_ecc_irq_funcs = {
1885         .set = sdma_v4_4_2_set_ecc_irq_state,
1886         .process = amdgpu_sdma_process_ecc_irq,
1887 };
1888
1889 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_vm_hole_irq_funcs = {
1890         .process = sdma_v4_4_2_process_vm_hole_irq,
1891 };
1892
1893 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_doorbell_invalid_irq_funcs = {
1894         .process = sdma_v4_4_2_process_doorbell_invalid_irq,
1895 };
1896
1897 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_pool_timeout_irq_funcs = {
1898         .process = sdma_v4_4_2_process_pool_timeout_irq,
1899 };
1900
1901 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_srbm_write_irq_funcs = {
1902         .process = sdma_v4_4_2_process_srbm_write_irq,
1903 };
1904
1905 static void sdma_v4_4_2_set_irq_funcs(struct amdgpu_device *adev)
1906 {
1907         adev->sdma.trap_irq.num_types = adev->sdma.num_instances;
1908         adev->sdma.ecc_irq.num_types = adev->sdma.num_instances;
1909         adev->sdma.vm_hole_irq.num_types = adev->sdma.num_instances;
1910         adev->sdma.doorbell_invalid_irq.num_types = adev->sdma.num_instances;
1911         adev->sdma.pool_timeout_irq.num_types = adev->sdma.num_instances;
1912         adev->sdma.srbm_write_irq.num_types = adev->sdma.num_instances;
1913
1914         adev->sdma.trap_irq.funcs = &sdma_v4_4_2_trap_irq_funcs;
1915         adev->sdma.illegal_inst_irq.funcs = &sdma_v4_4_2_illegal_inst_irq_funcs;
1916         adev->sdma.ecc_irq.funcs = &sdma_v4_4_2_ecc_irq_funcs;
1917         adev->sdma.vm_hole_irq.funcs = &sdma_v4_4_2_vm_hole_irq_funcs;
1918         adev->sdma.doorbell_invalid_irq.funcs = &sdma_v4_4_2_doorbell_invalid_irq_funcs;
1919         adev->sdma.pool_timeout_irq.funcs = &sdma_v4_4_2_pool_timeout_irq_funcs;
1920         adev->sdma.srbm_write_irq.funcs = &sdma_v4_4_2_srbm_write_irq_funcs;
1921 }
1922
1923 /**
1924  * sdma_v4_4_2_emit_copy_buffer - copy buffer using the sDMA engine
1925  *
1926  * @ib: indirect buffer to copy to
1927  * @src_offset: src GPU address
1928  * @dst_offset: dst GPU address
1929  * @byte_count: number of bytes to xfer
1930  * @tmz: if a secure copy should be used
1931  *
1932  * Copy GPU buffers using the DMA engine.
1933  * Used by the amdgpu ttm implementation to move pages if
1934  * registered as the asic copy callback.
1935  */
1936 static void sdma_v4_4_2_emit_copy_buffer(struct amdgpu_ib *ib,
1937                                        uint64_t src_offset,
1938                                        uint64_t dst_offset,
1939                                        uint32_t byte_count,
1940                                        bool tmz)
1941 {
1942         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1943                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |
1944                 SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0);
1945         ib->ptr[ib->length_dw++] = byte_count - 1;
1946         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1947         ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1948         ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1949         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1950         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1951 }
1952
1953 /**
1954  * sdma_v4_4_2_emit_fill_buffer - fill buffer using the sDMA engine
1955  *
1956  * @ib: indirect buffer to copy to
1957  * @src_data: value to write to buffer
1958  * @dst_offset: dst GPU address
1959  * @byte_count: number of bytes to xfer
1960  *
1961  * Fill GPU buffers using the DMA engine.
1962  */
1963 static void sdma_v4_4_2_emit_fill_buffer(struct amdgpu_ib *ib,
1964                                        uint32_t src_data,
1965                                        uint64_t dst_offset,
1966                                        uint32_t byte_count)
1967 {
1968         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1969         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1970         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1971         ib->ptr[ib->length_dw++] = src_data;
1972         ib->ptr[ib->length_dw++] = byte_count - 1;
1973 }
1974
1975 static const struct amdgpu_buffer_funcs sdma_v4_4_2_buffer_funcs = {
1976         .copy_max_bytes = 0x400000,
1977         .copy_num_dw = 7,
1978         .emit_copy_buffer = sdma_v4_4_2_emit_copy_buffer,
1979
1980         .fill_max_bytes = 0x400000,
1981         .fill_num_dw = 5,
1982         .emit_fill_buffer = sdma_v4_4_2_emit_fill_buffer,
1983 };
1984
1985 static void sdma_v4_4_2_set_buffer_funcs(struct amdgpu_device *adev)
1986 {
1987         adev->mman.buffer_funcs = &sdma_v4_4_2_buffer_funcs;
1988         if (adev->sdma.has_page_queue)
1989                 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].page;
1990         else
1991                 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1992 }
1993
1994 static const struct amdgpu_vm_pte_funcs sdma_v4_4_2_vm_pte_funcs = {
1995         .copy_pte_num_dw = 7,
1996         .copy_pte = sdma_v4_4_2_vm_copy_pte,
1997
1998         .write_pte = sdma_v4_4_2_vm_write_pte,
1999         .set_pte_pde = sdma_v4_4_2_vm_set_pte_pde,
2000 };
2001
2002 static void sdma_v4_4_2_set_vm_pte_funcs(struct amdgpu_device *adev)
2003 {
2004         struct drm_gpu_scheduler *sched;
2005         unsigned i;
2006
2007         adev->vm_manager.vm_pte_funcs = &sdma_v4_4_2_vm_pte_funcs;
2008         for (i = 0; i < adev->sdma.num_instances; i++) {
2009                 if (adev->sdma.has_page_queue)
2010                         sched = &adev->sdma.instance[i].page.sched;
2011                 else
2012                         sched = &adev->sdma.instance[i].ring.sched;
2013                 adev->vm_manager.vm_pte_scheds[i] = sched;
2014         }
2015         adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
2016 }
2017
2018 const struct amdgpu_ip_block_version sdma_v4_4_2_ip_block = {
2019         .type = AMD_IP_BLOCK_TYPE_SDMA,
2020         .major = 4,
2021         .minor = 4,
2022         .rev = 0,
2023         .funcs = &sdma_v4_4_2_ip_funcs,
2024 };
2025
2026 static int sdma_v4_4_2_xcp_resume(void *handle, uint32_t inst_mask)
2027 {
2028         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2029         int r;
2030
2031         if (!amdgpu_sriov_vf(adev))
2032                 sdma_v4_4_2_inst_init_golden_registers(adev, inst_mask);
2033
2034         r = sdma_v4_4_2_inst_start(adev, inst_mask);
2035
2036         return r;
2037 }
2038
2039 static int sdma_v4_4_2_xcp_suspend(void *handle, uint32_t inst_mask)
2040 {
2041         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2042         uint32_t tmp_mask = inst_mask;
2043         int i;
2044
2045         for_each_inst(i, tmp_mask) {
2046                 amdgpu_irq_put(adev, &adev->sdma.ecc_irq,
2047                                AMDGPU_SDMA_IRQ_INSTANCE0 + i);
2048         }
2049
2050         sdma_v4_4_2_inst_ctx_switch_enable(adev, false, inst_mask);
2051         sdma_v4_4_2_inst_enable(adev, false, inst_mask);
2052
2053         return 0;
2054 }
2055
2056 struct amdgpu_xcp_ip_funcs sdma_v4_4_2_xcp_funcs = {
2057         .suspend = &sdma_v4_4_2_xcp_suspend,
2058         .resume = &sdma_v4_4_2_xcp_resume
2059 };