2 * Copyright 2016 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/firmware.h>
24 #include <linux/slab.h>
25 #include <linux/module.h>
26 #include <linux/pci.h>
29 #include "amdgpu_atombios.h"
30 #include "amdgpu_ih.h"
31 #include "amdgpu_uvd.h"
32 #include "amdgpu_vce.h"
33 #include "amdgpu_ucode.h"
34 #include "amdgpu_psp.h"
38 #include "uvd/uvd_7_0_offset.h"
39 #include "gc/gc_9_0_offset.h"
40 #include "gc/gc_9_0_sh_mask.h"
41 #include "sdma0/sdma0_4_0_offset.h"
42 #include "sdma1/sdma1_4_0_offset.h"
43 #include "hdp/hdp_4_0_offset.h"
44 #include "hdp/hdp_4_0_sh_mask.h"
45 #include "smuio/smuio_9_0_offset.h"
46 #include "smuio/smuio_9_0_sh_mask.h"
47 #include "nbio/nbio_7_0_default.h"
48 #include "nbio/nbio_7_0_offset.h"
49 #include "nbio/nbio_7_0_sh_mask.h"
50 #include "nbio/nbio_7_0_smn.h"
51 #include "mp/mp_9_0_offset.h"
54 #include "soc15_common.h"
57 #include "gfxhub_v1_0.h"
58 #include "mmhub_v1_0.h"
61 #include "nbio_v6_1.h"
62 #include "nbio_v7_0.h"
63 #include "nbio_v7_4.h"
64 #include "vega10_ih.h"
65 #include "sdma_v4_0.h"
70 #include "jpeg_v2_0.h"
72 #include "jpeg_v2_5.h"
73 #include "dce_virtual.h"
75 #include "amdgpu_smu.h"
76 #include "amdgpu_ras.h"
77 #include "amdgpu_xgmi.h"
78 #include <uapi/linux/kfd_ioctl.h>
80 #define mmMP0_MISC_CGTT_CTRL0 0x01b9
81 #define mmMP0_MISC_CGTT_CTRL0_BASE_IDX 0
82 #define mmMP0_MISC_LIGHT_SLEEP_CTRL 0x01ba
83 #define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX 0
85 /* for Vega20 register name change */
86 #define mmHDP_MEM_POWER_CTRL 0x00d4
87 #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK 0x00000001L
88 #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK 0x00000002L
89 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK 0x00010000L
90 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK 0x00020000L
91 #define mmHDP_MEM_POWER_CTRL_BASE_IDX 0
93 /* for Vega20/arcturus regiter offset change */
94 #define mmROM_INDEX_VG20 0x00e4
95 #define mmROM_INDEX_VG20_BASE_IDX 0
96 #define mmROM_DATA_VG20 0x00e5
97 #define mmROM_DATA_VG20_BASE_IDX 0
100 * Indirect registers accessor
102 static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg)
104 unsigned long flags, address, data;
106 address = adev->nbio.funcs->get_pcie_index_offset(adev);
107 data = adev->nbio.funcs->get_pcie_data_offset(adev);
109 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
110 WREG32(address, reg);
111 (void)RREG32(address);
113 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
117 static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
119 unsigned long flags, address, data;
121 address = adev->nbio.funcs->get_pcie_index_offset(adev);
122 data = adev->nbio.funcs->get_pcie_data_offset(adev);
124 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
125 WREG32(address, reg);
126 (void)RREG32(address);
129 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
132 static u64 soc15_pcie_rreg64(struct amdgpu_device *adev, u32 reg)
134 unsigned long flags, address, data;
136 address = adev->nbio.funcs->get_pcie_index_offset(adev);
137 data = adev->nbio.funcs->get_pcie_data_offset(adev);
139 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
140 /* read low 32 bit */
141 WREG32(address, reg);
142 (void)RREG32(address);
145 /* read high 32 bit*/
146 WREG32(address, reg + 4);
147 (void)RREG32(address);
148 r |= ((u64)RREG32(data) << 32);
149 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
153 static void soc15_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v)
155 unsigned long flags, address, data;
157 address = adev->nbio.funcs->get_pcie_index_offset(adev);
158 data = adev->nbio.funcs->get_pcie_data_offset(adev);
160 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
161 /* write low 32 bit */
162 WREG32(address, reg);
163 (void)RREG32(address);
164 WREG32(data, (u32)(v & 0xffffffffULL));
167 /* write high 32 bit */
168 WREG32(address, reg + 4);
169 (void)RREG32(address);
170 WREG32(data, (u32)(v >> 32));
172 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
175 static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
177 unsigned long flags, address, data;
180 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
181 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
183 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
184 WREG32(address, ((reg) & 0x1ff));
186 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
190 static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
192 unsigned long flags, address, data;
194 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
195 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
197 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
198 WREG32(address, ((reg) & 0x1ff));
200 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
203 static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg)
205 unsigned long flags, address, data;
208 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
209 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
211 spin_lock_irqsave(&adev->didt_idx_lock, flags);
212 WREG32(address, (reg));
214 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
218 static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
220 unsigned long flags, address, data;
222 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
223 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
225 spin_lock_irqsave(&adev->didt_idx_lock, flags);
226 WREG32(address, (reg));
228 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
231 static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg)
236 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
237 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
238 r = RREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA);
239 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
243 static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
247 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
248 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
249 WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, (v));
250 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
253 static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg)
258 spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
259 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
260 r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA);
261 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
265 static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
269 spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
270 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
271 WREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA, (v));
272 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
275 static u32 soc15_get_config_memsize(struct amdgpu_device *adev)
277 return adev->nbio.funcs->get_memsize(adev);
280 static u32 soc15_get_xclk(struct amdgpu_device *adev)
282 u32 reference_clock = adev->clock.spll.reference_freq;
284 if (adev->asic_type == CHIP_RAVEN)
285 return reference_clock / 4;
287 return reference_clock;
291 void soc15_grbm_select(struct amdgpu_device *adev,
292 u32 me, u32 pipe, u32 queue, u32 vmid)
294 u32 grbm_gfx_cntl = 0;
295 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
296 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
297 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
298 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
300 WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl);
303 static void soc15_vga_set_state(struct amdgpu_device *adev, bool state)
308 static bool soc15_read_disabled_bios(struct amdgpu_device *adev)
314 static bool soc15_read_bios_from_rom(struct amdgpu_device *adev,
315 u8 *bios, u32 length_bytes)
319 uint32_t rom_index_offset;
320 uint32_t rom_data_offset;
324 if (length_bytes == 0)
326 /* APU vbios image is part of sbios image */
327 if (adev->flags & AMD_IS_APU)
330 dw_ptr = (u32 *)bios;
331 length_dw = ALIGN(length_bytes, 4) / 4;
333 switch (adev->asic_type) {
336 rom_index_offset = SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX_VG20);
337 rom_data_offset = SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA_VG20);
340 rom_index_offset = SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX);
341 rom_data_offset = SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA);
345 /* set rom index to 0 */
346 WREG32(rom_index_offset, 0);
347 /* read out the rom data */
348 for (i = 0; i < length_dw; i++)
349 dw_ptr[i] = RREG32(rom_data_offset);
354 static struct soc15_allowed_register_entry soc15_allowed_read_registers[] = {
355 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
356 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
357 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)},
358 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)},
359 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)},
360 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)},
361 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
362 { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)},
363 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)},
364 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)},
365 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)},
366 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)},
367 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)},
368 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)},
369 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
370 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)},
371 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)},
372 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
373 { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},
374 { SOC15_REG_ENTRY(GC, 0, mmDB_DEBUG2)},
377 static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
378 u32 sh_num, u32 reg_offset)
382 mutex_lock(&adev->grbm_idx_mutex);
383 if (se_num != 0xffffffff || sh_num != 0xffffffff)
384 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
386 val = RREG32(reg_offset);
388 if (se_num != 0xffffffff || sh_num != 0xffffffff)
389 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
390 mutex_unlock(&adev->grbm_idx_mutex);
394 static uint32_t soc15_get_register_value(struct amdgpu_device *adev,
395 bool indexed, u32 se_num,
396 u32 sh_num, u32 reg_offset)
399 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset);
401 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
402 return adev->gfx.config.gb_addr_config;
403 else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2))
404 return adev->gfx.config.db_debug2;
405 return RREG32(reg_offset);
409 static int soc15_read_register(struct amdgpu_device *adev, u32 se_num,
410 u32 sh_num, u32 reg_offset, u32 *value)
413 struct soc15_allowed_register_entry *en;
416 for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) {
417 en = &soc15_allowed_read_registers[i];
418 if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
422 *value = soc15_get_register_value(adev,
423 soc15_allowed_read_registers[i].grbm_indexed,
424 se_num, sh_num, reg_offset);
432 * soc15_program_register_sequence - program an array of registers.
434 * @adev: amdgpu_device pointer
435 * @regs: pointer to the register array
436 * @array_size: size of the register array
438 * Programs an array or registers with and and or masks.
439 * This is a helper for setting golden registers.
442 void soc15_program_register_sequence(struct amdgpu_device *adev,
443 const struct soc15_reg_golden *regs,
444 const u32 array_size)
446 const struct soc15_reg_golden *entry;
450 for (i = 0; i < array_size; ++i) {
452 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
454 if (entry->and_mask == 0xffffffff) {
455 tmp = entry->or_mask;
458 tmp &= ~(entry->and_mask);
459 tmp |= (entry->or_mask & entry->and_mask);
462 if (reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3) ||
463 reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE) ||
464 reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1) ||
465 reg == SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG))
466 WREG32_RLC(reg, tmp);
474 static int soc15_asic_mode1_reset(struct amdgpu_device *adev)
479 amdgpu_atombios_scratch_regs_engine_hung(adev, true);
481 dev_info(adev->dev, "GPU mode1 reset\n");
484 pci_clear_master(adev->pdev);
486 pci_save_state(adev->pdev);
488 ret = psp_gpu_reset(adev);
490 dev_err(adev->dev, "GPU mode1 reset failed\n");
492 pci_restore_state(adev->pdev);
494 /* wait for asic to come out of reset */
495 for (i = 0; i < adev->usec_timeout; i++) {
496 u32 memsize = adev->nbio.funcs->get_memsize(adev);
498 if (memsize != 0xffffffff)
503 amdgpu_atombios_scratch_regs_engine_hung(adev, false);
508 static int soc15_asic_baco_reset(struct amdgpu_device *adev)
510 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
513 /* avoid NBIF got stuck when do RAS recovery in BACO reset */
514 if (ras && ras->supported)
515 adev->nbio.funcs->enable_doorbell_interrupt(adev, false);
517 ret = amdgpu_dpm_baco_reset(adev);
521 /* re-enable doorbell interrupt after BACO exit */
522 if (ras && ras->supported)
523 adev->nbio.funcs->enable_doorbell_interrupt(adev, true);
528 static enum amd_reset_method
529 soc15_asic_reset_method(struct amdgpu_device *adev)
531 bool baco_reset = false;
532 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
534 switch (adev->asic_type) {
537 return AMD_RESET_METHOD_MODE2;
541 baco_reset = amdgpu_dpm_is_baco_supported(adev);
544 if (adev->psp.sos_fw_version >= 0x80067)
545 baco_reset = amdgpu_dpm_is_baco_supported(adev);
548 * 1. PMFW version > 0x284300: all cases use baco
549 * 2. PMFW version <= 0x284300: only sGPU w/o RAS use baco
551 if ((ras && ras->supported) && adev->pm.fw_version <= 0x283400)
559 return AMD_RESET_METHOD_BACO;
561 return AMD_RESET_METHOD_MODE1;
564 static int soc15_asic_reset(struct amdgpu_device *adev)
566 /* original raven doesn't have full asic reset */
567 if (adev->pdev->device == 0x15dd && adev->rev_id < 0x8)
570 switch (soc15_asic_reset_method(adev)) {
571 case AMD_RESET_METHOD_BACO:
572 if (!adev->in_suspend)
573 amdgpu_inc_vram_lost(adev);
574 return soc15_asic_baco_reset(adev);
575 case AMD_RESET_METHOD_MODE2:
576 return amdgpu_dpm_mode2_reset(adev);
578 if (!adev->in_suspend)
579 amdgpu_inc_vram_lost(adev);
580 return soc15_asic_mode1_reset(adev);
584 static bool soc15_supports_baco(struct amdgpu_device *adev)
586 switch (adev->asic_type) {
590 return amdgpu_dpm_is_baco_supported(adev);
592 if (adev->psp.sos_fw_version >= 0x80067)
593 return amdgpu_dpm_is_baco_supported(adev);
600 /*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
601 u32 cntl_reg, u32 status_reg)
606 static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
610 r = soc15_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
614 r = soc15_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
619 static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
626 static void soc15_pcie_gen3_enable(struct amdgpu_device *adev)
628 if (pci_is_root_bus(adev->pdev->bus))
631 if (amdgpu_pcie_gen2 == 0)
634 if (adev->flags & AMD_IS_APU)
637 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
638 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
644 static void soc15_program_aspm(struct amdgpu_device *adev)
647 if (amdgpu_aspm == 0)
653 static void soc15_enable_doorbell_aperture(struct amdgpu_device *adev,
656 adev->nbio.funcs->enable_doorbell_aperture(adev, enable);
657 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable);
660 static const struct amdgpu_ip_block_version vega10_common_ip_block =
662 .type = AMD_IP_BLOCK_TYPE_COMMON,
666 .funcs = &soc15_common_ip_funcs,
669 static uint32_t soc15_get_rev_id(struct amdgpu_device *adev)
671 return adev->nbio.funcs->get_rev_id(adev);
674 int soc15_set_ip_blocks(struct amdgpu_device *adev)
676 /* Set IP register base before any HW register access */
677 switch (adev->asic_type) {
682 vega10_reg_base_init(adev);
685 vega20_reg_base_init(adev);
688 arct_reg_base_init(adev);
694 if (adev->asic_type == CHIP_VEGA20 || adev->asic_type == CHIP_ARCTURUS)
695 adev->gmc.xgmi.supported = true;
697 if (adev->flags & AMD_IS_APU) {
698 adev->nbio.funcs = &nbio_v7_0_funcs;
699 adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg;
700 } else if (adev->asic_type == CHIP_VEGA20 ||
701 adev->asic_type == CHIP_ARCTURUS) {
702 adev->nbio.funcs = &nbio_v7_4_funcs;
703 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg;
705 adev->nbio.funcs = &nbio_v6_1_funcs;
706 adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg;
709 if (adev->asic_type == CHIP_VEGA20 || adev->asic_type == CHIP_ARCTURUS)
710 adev->df.funcs = &df_v3_6_funcs;
712 adev->df.funcs = &df_v1_7_funcs;
714 adev->rev_id = soc15_get_rev_id(adev);
715 adev->nbio.funcs->detect_hw_virt(adev);
717 if (amdgpu_sriov_vf(adev))
718 adev->virt.ops = &xgpu_ai_virt_ops;
720 switch (adev->asic_type) {
724 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
725 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
727 /* For Vega10 SR-IOV, PSP need to be initialized before IH */
728 if (amdgpu_sriov_vf(adev)) {
729 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
730 if (adev->asic_type == CHIP_VEGA20)
731 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
733 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
735 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
737 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
738 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
739 if (adev->asic_type == CHIP_VEGA20)
740 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
742 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
745 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
746 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
747 if (is_support_sw_smu(adev)) {
748 if (!amdgpu_sriov_vf(adev))
749 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
751 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
753 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
754 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
755 #if defined(CONFIG_DRM_AMD_DC)
756 else if (amdgpu_device_has_dc_support(adev))
757 amdgpu_device_ip_block_add(adev, &dm_ip_block);
759 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) {
760 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block);
761 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block);
765 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
766 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
767 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
768 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
769 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block);
770 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
771 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
772 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
773 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
774 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
775 #if defined(CONFIG_DRM_AMD_DC)
776 else if (amdgpu_device_has_dc_support(adev))
777 amdgpu_device_ip_block_add(adev, &dm_ip_block);
779 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block);
782 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
783 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
785 if (amdgpu_sriov_vf(adev)) {
786 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
787 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
788 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
790 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
791 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
792 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
795 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
796 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
797 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
798 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
799 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
801 if (amdgpu_sriov_vf(adev)) {
802 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
803 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block);
805 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block);
807 if (!amdgpu_sriov_vf(adev))
808 amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block);
811 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
812 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
813 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
814 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
815 amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block);
816 amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block);
817 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
818 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
819 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
820 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
821 #if defined(CONFIG_DRM_AMD_DC)
822 else if (amdgpu_device_has_dc_support(adev))
823 amdgpu_device_ip_block_add(adev, &dm_ip_block);
825 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
826 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
835 static void soc15_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring)
837 adev->nbio.funcs->hdp_flush(adev, ring);
840 static void soc15_invalidate_hdp(struct amdgpu_device *adev,
841 struct amdgpu_ring *ring)
843 if (!ring || !ring->funcs->emit_wreg)
844 WREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE, 1);
846 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
847 HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1);
850 static bool soc15_need_full_reset(struct amdgpu_device *adev)
852 /* change this when we implement soft reset */
856 static void vega20_reset_hdp_ras_error_count(struct amdgpu_device *adev)
858 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__HDP))
860 /*read back hdp ras counter to reset it to 0 */
861 RREG32_SOC15(HDP, 0, mmHDP_EDC_CNT);
864 static void soc15_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
867 uint32_t perfctr = 0;
868 uint64_t cnt0_of, cnt1_of;
871 /* This reports 0 on APUs, so return to avoid writing/reading registers
872 * that may or may not be different from their GPU counterparts
874 if (adev->flags & AMD_IS_APU)
877 /* Set the 2 events that we wish to watch, defined above */
878 /* Reg 40 is # received msgs */
879 /* Reg 104 is # of posted requests sent */
880 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40);
881 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104);
883 /* Write to enable desired perf counters */
884 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK, perfctr);
885 /* Zero out and enable the perf counters
887 * Bit 0 = Start all counters(1)
888 * Bit 2 = Global counter reset enable(1)
890 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005);
894 /* Load the shadow and disable the perf counters
896 * Bit 0 = Stop counters(0)
897 * Bit 1 = Load the shadow counters(1)
899 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002);
901 /* Read register values to get any >32bit overflow */
902 tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK);
903 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER);
904 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER);
906 /* Get the values and add the overflow */
907 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32);
908 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32);
911 static void vega20_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
914 uint32_t perfctr = 0;
915 uint64_t cnt0_of, cnt1_of;
918 /* This reports 0 on APUs, so return to avoid writing/reading registers
919 * that may or may not be different from their GPU counterparts
921 if (adev->flags & AMD_IS_APU)
924 /* Set the 2 events that we wish to watch, defined above */
925 /* Reg 40 is # received msgs */
926 /* Reg 108 is # of posted requests sent on VG20 */
927 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3,
929 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3,
932 /* Write to enable desired perf counters */
933 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3, perfctr);
934 /* Zero out and enable the perf counters
936 * Bit 0 = Start all counters(1)
937 * Bit 2 = Global counter reset enable(1)
939 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005);
943 /* Load the shadow and disable the perf counters
945 * Bit 0 = Stop counters(0)
946 * Bit 1 = Load the shadow counters(1)
948 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002);
950 /* Read register values to get any >32bit overflow */
951 tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3);
952 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER0_UPPER);
953 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER1_UPPER);
955 /* Get the values and add the overflow */
956 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK3) | (cnt0_of << 32);
957 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK3) | (cnt1_of << 32);
960 static bool soc15_need_reset_on_init(struct amdgpu_device *adev)
964 /* Just return false for soc15 GPUs. Reset does not seem to
967 if (!amdgpu_passthrough(adev))
970 if (adev->flags & AMD_IS_APU)
973 /* Check sOS sign of life register to confirm sys driver and sOS
974 * are already been loaded.
976 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
983 static uint64_t soc15_get_pcie_replay_count(struct amdgpu_device *adev)
985 uint64_t nak_r, nak_g;
987 /* Get the number of NAKs received and generated */
988 nak_r = RREG32_PCIE(smnPCIE_RX_NUM_NAK);
989 nak_g = RREG32_PCIE(smnPCIE_RX_NUM_NAK_GENERATED);
991 /* Add the total number of NAKs, i.e the number of replays */
992 return (nak_r + nak_g);
995 static const struct amdgpu_asic_funcs soc15_asic_funcs =
997 .read_disabled_bios = &soc15_read_disabled_bios,
998 .read_bios_from_rom = &soc15_read_bios_from_rom,
999 .read_register = &soc15_read_register,
1000 .reset = &soc15_asic_reset,
1001 .reset_method = &soc15_asic_reset_method,
1002 .set_vga_state = &soc15_vga_set_state,
1003 .get_xclk = &soc15_get_xclk,
1004 .set_uvd_clocks = &soc15_set_uvd_clocks,
1005 .set_vce_clocks = &soc15_set_vce_clocks,
1006 .get_config_memsize = &soc15_get_config_memsize,
1007 .flush_hdp = &soc15_flush_hdp,
1008 .invalidate_hdp = &soc15_invalidate_hdp,
1009 .need_full_reset = &soc15_need_full_reset,
1010 .init_doorbell_index = &vega10_doorbell_index_init,
1011 .get_pcie_usage = &soc15_get_pcie_usage,
1012 .need_reset_on_init = &soc15_need_reset_on_init,
1013 .get_pcie_replay_count = &soc15_get_pcie_replay_count,
1014 .supports_baco = &soc15_supports_baco,
1017 static const struct amdgpu_asic_funcs vega20_asic_funcs =
1019 .read_disabled_bios = &soc15_read_disabled_bios,
1020 .read_bios_from_rom = &soc15_read_bios_from_rom,
1021 .read_register = &soc15_read_register,
1022 .reset = &soc15_asic_reset,
1023 .reset_method = &soc15_asic_reset_method,
1024 .set_vga_state = &soc15_vga_set_state,
1025 .get_xclk = &soc15_get_xclk,
1026 .set_uvd_clocks = &soc15_set_uvd_clocks,
1027 .set_vce_clocks = &soc15_set_vce_clocks,
1028 .get_config_memsize = &soc15_get_config_memsize,
1029 .flush_hdp = &soc15_flush_hdp,
1030 .invalidate_hdp = &soc15_invalidate_hdp,
1031 .reset_hdp_ras_error_count = &vega20_reset_hdp_ras_error_count,
1032 .need_full_reset = &soc15_need_full_reset,
1033 .init_doorbell_index = &vega20_doorbell_index_init,
1034 .get_pcie_usage = &vega20_get_pcie_usage,
1035 .need_reset_on_init = &soc15_need_reset_on_init,
1036 .get_pcie_replay_count = &soc15_get_pcie_replay_count,
1037 .supports_baco = &soc15_supports_baco,
1040 static int soc15_common_early_init(void *handle)
1042 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
1043 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1045 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
1046 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
1047 adev->smc_rreg = NULL;
1048 adev->smc_wreg = NULL;
1049 adev->pcie_rreg = &soc15_pcie_rreg;
1050 adev->pcie_wreg = &soc15_pcie_wreg;
1051 adev->pcie_rreg64 = &soc15_pcie_rreg64;
1052 adev->pcie_wreg64 = &soc15_pcie_wreg64;
1053 adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg;
1054 adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg;
1055 adev->didt_rreg = &soc15_didt_rreg;
1056 adev->didt_wreg = &soc15_didt_wreg;
1057 adev->gc_cac_rreg = &soc15_gc_cac_rreg;
1058 adev->gc_cac_wreg = &soc15_gc_cac_wreg;
1059 adev->se_cac_rreg = &soc15_se_cac_rreg;
1060 adev->se_cac_wreg = &soc15_se_cac_wreg;
1063 adev->external_rev_id = 0xFF;
1064 switch (adev->asic_type) {
1066 adev->asic_funcs = &soc15_asic_funcs;
1067 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1068 AMD_CG_SUPPORT_GFX_MGLS |
1069 AMD_CG_SUPPORT_GFX_RLC_LS |
1070 AMD_CG_SUPPORT_GFX_CP_LS |
1071 AMD_CG_SUPPORT_GFX_3D_CGCG |
1072 AMD_CG_SUPPORT_GFX_3D_CGLS |
1073 AMD_CG_SUPPORT_GFX_CGCG |
1074 AMD_CG_SUPPORT_GFX_CGLS |
1075 AMD_CG_SUPPORT_BIF_MGCG |
1076 AMD_CG_SUPPORT_BIF_LS |
1077 AMD_CG_SUPPORT_HDP_LS |
1078 AMD_CG_SUPPORT_DRM_MGCG |
1079 AMD_CG_SUPPORT_DRM_LS |
1080 AMD_CG_SUPPORT_ROM_MGCG |
1081 AMD_CG_SUPPORT_DF_MGCG |
1082 AMD_CG_SUPPORT_SDMA_MGCG |
1083 AMD_CG_SUPPORT_SDMA_LS |
1084 AMD_CG_SUPPORT_MC_MGCG |
1085 AMD_CG_SUPPORT_MC_LS;
1087 adev->external_rev_id = 0x1;
1090 adev->asic_funcs = &soc15_asic_funcs;
1091 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1092 AMD_CG_SUPPORT_GFX_MGLS |
1093 AMD_CG_SUPPORT_GFX_CGCG |
1094 AMD_CG_SUPPORT_GFX_CGLS |
1095 AMD_CG_SUPPORT_GFX_3D_CGCG |
1096 AMD_CG_SUPPORT_GFX_3D_CGLS |
1097 AMD_CG_SUPPORT_GFX_CP_LS |
1098 AMD_CG_SUPPORT_MC_LS |
1099 AMD_CG_SUPPORT_MC_MGCG |
1100 AMD_CG_SUPPORT_SDMA_MGCG |
1101 AMD_CG_SUPPORT_SDMA_LS |
1102 AMD_CG_SUPPORT_BIF_MGCG |
1103 AMD_CG_SUPPORT_BIF_LS |
1104 AMD_CG_SUPPORT_HDP_MGCG |
1105 AMD_CG_SUPPORT_HDP_LS |
1106 AMD_CG_SUPPORT_ROM_MGCG |
1107 AMD_CG_SUPPORT_VCE_MGCG |
1108 AMD_CG_SUPPORT_UVD_MGCG;
1110 adev->external_rev_id = adev->rev_id + 0x14;
1113 adev->asic_funcs = &vega20_asic_funcs;
1114 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1115 AMD_CG_SUPPORT_GFX_MGLS |
1116 AMD_CG_SUPPORT_GFX_CGCG |
1117 AMD_CG_SUPPORT_GFX_CGLS |
1118 AMD_CG_SUPPORT_GFX_3D_CGCG |
1119 AMD_CG_SUPPORT_GFX_3D_CGLS |
1120 AMD_CG_SUPPORT_GFX_CP_LS |
1121 AMD_CG_SUPPORT_MC_LS |
1122 AMD_CG_SUPPORT_MC_MGCG |
1123 AMD_CG_SUPPORT_SDMA_MGCG |
1124 AMD_CG_SUPPORT_SDMA_LS |
1125 AMD_CG_SUPPORT_BIF_MGCG |
1126 AMD_CG_SUPPORT_BIF_LS |
1127 AMD_CG_SUPPORT_HDP_MGCG |
1128 AMD_CG_SUPPORT_HDP_LS |
1129 AMD_CG_SUPPORT_ROM_MGCG |
1130 AMD_CG_SUPPORT_VCE_MGCG |
1131 AMD_CG_SUPPORT_UVD_MGCG;
1133 adev->external_rev_id = adev->rev_id + 0x28;
1136 adev->asic_funcs = &soc15_asic_funcs;
1137 if (adev->rev_id >= 0x8)
1138 adev->external_rev_id = adev->rev_id + 0x79;
1139 else if (adev->pdev->device == 0x15d8)
1140 adev->external_rev_id = adev->rev_id + 0x41;
1141 else if (adev->rev_id == 1)
1142 adev->external_rev_id = adev->rev_id + 0x20;
1144 adev->external_rev_id = adev->rev_id + 0x01;
1146 if (adev->rev_id >= 0x8) {
1147 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1148 AMD_CG_SUPPORT_GFX_MGLS |
1149 AMD_CG_SUPPORT_GFX_CP_LS |
1150 AMD_CG_SUPPORT_GFX_3D_CGCG |
1151 AMD_CG_SUPPORT_GFX_3D_CGLS |
1152 AMD_CG_SUPPORT_GFX_CGCG |
1153 AMD_CG_SUPPORT_GFX_CGLS |
1154 AMD_CG_SUPPORT_BIF_LS |
1155 AMD_CG_SUPPORT_HDP_LS |
1156 AMD_CG_SUPPORT_ROM_MGCG |
1157 AMD_CG_SUPPORT_MC_MGCG |
1158 AMD_CG_SUPPORT_MC_LS |
1159 AMD_CG_SUPPORT_SDMA_MGCG |
1160 AMD_CG_SUPPORT_SDMA_LS |
1161 AMD_CG_SUPPORT_VCN_MGCG;
1163 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
1164 } else if (adev->pdev->device == 0x15d8) {
1165 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1166 AMD_CG_SUPPORT_GFX_MGLS |
1167 AMD_CG_SUPPORT_GFX_CP_LS |
1168 AMD_CG_SUPPORT_GFX_3D_CGCG |
1169 AMD_CG_SUPPORT_GFX_3D_CGLS |
1170 AMD_CG_SUPPORT_GFX_CGCG |
1171 AMD_CG_SUPPORT_GFX_CGLS |
1172 AMD_CG_SUPPORT_BIF_LS |
1173 AMD_CG_SUPPORT_HDP_LS |
1174 AMD_CG_SUPPORT_ROM_MGCG |
1175 AMD_CG_SUPPORT_MC_MGCG |
1176 AMD_CG_SUPPORT_MC_LS |
1177 AMD_CG_SUPPORT_SDMA_MGCG |
1178 AMD_CG_SUPPORT_SDMA_LS;
1180 adev->pg_flags = AMD_PG_SUPPORT_SDMA |
1181 AMD_PG_SUPPORT_MMHUB |
1182 AMD_PG_SUPPORT_VCN |
1183 AMD_PG_SUPPORT_VCN_DPG;
1185 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1186 AMD_CG_SUPPORT_GFX_MGLS |
1187 AMD_CG_SUPPORT_GFX_RLC_LS |
1188 AMD_CG_SUPPORT_GFX_CP_LS |
1189 AMD_CG_SUPPORT_GFX_3D_CGCG |
1190 AMD_CG_SUPPORT_GFX_3D_CGLS |
1191 AMD_CG_SUPPORT_GFX_CGCG |
1192 AMD_CG_SUPPORT_GFX_CGLS |
1193 AMD_CG_SUPPORT_BIF_MGCG |
1194 AMD_CG_SUPPORT_BIF_LS |
1195 AMD_CG_SUPPORT_HDP_MGCG |
1196 AMD_CG_SUPPORT_HDP_LS |
1197 AMD_CG_SUPPORT_DRM_MGCG |
1198 AMD_CG_SUPPORT_DRM_LS |
1199 AMD_CG_SUPPORT_ROM_MGCG |
1200 AMD_CG_SUPPORT_MC_MGCG |
1201 AMD_CG_SUPPORT_MC_LS |
1202 AMD_CG_SUPPORT_SDMA_MGCG |
1203 AMD_CG_SUPPORT_SDMA_LS |
1204 AMD_CG_SUPPORT_VCN_MGCG;
1206 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
1210 adev->asic_funcs = &vega20_asic_funcs;
1211 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1212 AMD_CG_SUPPORT_GFX_MGLS |
1213 AMD_CG_SUPPORT_GFX_CGCG |
1214 AMD_CG_SUPPORT_GFX_CGLS |
1215 AMD_CG_SUPPORT_GFX_CP_LS |
1216 AMD_CG_SUPPORT_HDP_MGCG |
1217 AMD_CG_SUPPORT_HDP_LS |
1218 AMD_CG_SUPPORT_SDMA_MGCG |
1219 AMD_CG_SUPPORT_SDMA_LS |
1220 AMD_CG_SUPPORT_MC_MGCG |
1221 AMD_CG_SUPPORT_MC_LS |
1222 AMD_CG_SUPPORT_IH_CG |
1223 AMD_CG_SUPPORT_VCN_MGCG |
1224 AMD_CG_SUPPORT_JPEG_MGCG;
1226 adev->external_rev_id = adev->rev_id + 0x32;
1229 adev->asic_funcs = &soc15_asic_funcs;
1230 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1231 AMD_CG_SUPPORT_GFX_MGLS |
1232 AMD_CG_SUPPORT_GFX_3D_CGCG |
1233 AMD_CG_SUPPORT_GFX_3D_CGLS |
1234 AMD_CG_SUPPORT_GFX_CGCG |
1235 AMD_CG_SUPPORT_GFX_CGLS |
1236 AMD_CG_SUPPORT_GFX_CP_LS |
1237 AMD_CG_SUPPORT_MC_MGCG |
1238 AMD_CG_SUPPORT_MC_LS |
1239 AMD_CG_SUPPORT_SDMA_MGCG |
1240 AMD_CG_SUPPORT_SDMA_LS |
1241 AMD_CG_SUPPORT_BIF_LS |
1242 AMD_CG_SUPPORT_HDP_LS |
1243 AMD_CG_SUPPORT_ROM_MGCG |
1244 AMD_CG_SUPPORT_VCN_MGCG |
1245 AMD_CG_SUPPORT_JPEG_MGCG |
1246 AMD_CG_SUPPORT_IH_CG |
1247 AMD_CG_SUPPORT_ATHUB_LS |
1248 AMD_CG_SUPPORT_ATHUB_MGCG |
1249 AMD_CG_SUPPORT_DF_MGCG;
1250 adev->pg_flags = AMD_PG_SUPPORT_SDMA |
1251 AMD_PG_SUPPORT_VCN |
1252 AMD_PG_SUPPORT_JPEG |
1253 AMD_PG_SUPPORT_VCN_DPG;
1254 adev->external_rev_id = adev->rev_id + 0x91;
1257 /* FIXME: not supported yet */
1261 if (amdgpu_sriov_vf(adev)) {
1262 amdgpu_virt_init_setting(adev);
1263 xgpu_ai_mailbox_set_irq_funcs(adev);
1269 static int soc15_common_late_init(void *handle)
1271 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1274 if (amdgpu_sriov_vf(adev))
1275 xgpu_ai_mailbox_get_irq(adev);
1277 if (adev->asic_funcs &&
1278 adev->asic_funcs->reset_hdp_ras_error_count)
1279 adev->asic_funcs->reset_hdp_ras_error_count(adev);
1281 if (adev->nbio.funcs->ras_late_init)
1282 r = adev->nbio.funcs->ras_late_init(adev);
1287 static int soc15_common_sw_init(void *handle)
1289 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1291 if (amdgpu_sriov_vf(adev))
1292 xgpu_ai_mailbox_add_irq_id(adev);
1294 adev->df.funcs->sw_init(adev);
1299 static int soc15_common_sw_fini(void *handle)
1301 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1303 amdgpu_nbio_ras_fini(adev);
1304 adev->df.funcs->sw_fini(adev);
1308 static void soc15_doorbell_range_init(struct amdgpu_device *adev)
1311 struct amdgpu_ring *ring;
1313 /* sdma/ih doorbell range are programed by hypervisor */
1314 if (!amdgpu_sriov_vf(adev)) {
1315 for (i = 0; i < adev->sdma.num_instances; i++) {
1316 ring = &adev->sdma.instance[i].ring;
1317 adev->nbio.funcs->sdma_doorbell_range(adev, i,
1318 ring->use_doorbell, ring->doorbell_index,
1319 adev->doorbell_index.sdma_doorbell_range);
1322 adev->nbio.funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell,
1323 adev->irq.ih.doorbell_index);
1327 static int soc15_common_hw_init(void *handle)
1329 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1331 /* enable pcie gen2/3 link */
1332 soc15_pcie_gen3_enable(adev);
1334 soc15_program_aspm(adev);
1335 /* setup nbio registers */
1336 adev->nbio.funcs->init_registers(adev);
1337 /* remap HDP registers to a hole in mmio space,
1338 * for the purpose of expose those registers
1341 if (adev->nbio.funcs->remap_hdp_registers)
1342 adev->nbio.funcs->remap_hdp_registers(adev);
1344 /* enable the doorbell aperture */
1345 soc15_enable_doorbell_aperture(adev, true);
1346 /* HW doorbell routing policy: doorbell writing not
1347 * in SDMA/IH/MM/ACV range will be routed to CP. So
1348 * we need to init SDMA/IH/MM/ACV doorbell range prior
1349 * to CP ip block init and ring test.
1351 soc15_doorbell_range_init(adev);
1356 static int soc15_common_hw_fini(void *handle)
1358 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1360 /* disable the doorbell aperture */
1361 soc15_enable_doorbell_aperture(adev, false);
1362 if (amdgpu_sriov_vf(adev))
1363 xgpu_ai_mailbox_put_irq(adev);
1365 if (adev->nbio.ras_if &&
1366 amdgpu_ras_is_supported(adev, adev->nbio.ras_if->block)) {
1367 if (adev->nbio.funcs->init_ras_controller_interrupt)
1368 amdgpu_irq_put(adev, &adev->nbio.ras_controller_irq, 0);
1369 if (adev->nbio.funcs->init_ras_err_event_athub_interrupt)
1370 amdgpu_irq_put(adev, &adev->nbio.ras_err_event_athub_irq, 0);
1376 static int soc15_common_suspend(void *handle)
1378 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1380 return soc15_common_hw_fini(adev);
1383 static int soc15_common_resume(void *handle)
1385 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1387 return soc15_common_hw_init(adev);
1390 static bool soc15_common_is_idle(void *handle)
1395 static int soc15_common_wait_for_idle(void *handle)
1400 static int soc15_common_soft_reset(void *handle)
1405 static void soc15_update_hdp_light_sleep(struct amdgpu_device *adev, bool enable)
1409 if (adev->asic_type == CHIP_VEGA20 ||
1410 adev->asic_type == CHIP_ARCTURUS) {
1411 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL));
1413 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
1414 data |= HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK |
1415 HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK |
1416 HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK |
1417 HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK;
1419 data &= ~(HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK |
1420 HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK |
1421 HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK |
1422 HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK);
1425 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL), data);
1427 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
1429 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
1430 data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK;
1432 data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK;
1435 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data);
1439 static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable)
1443 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
1445 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG))
1446 data &= ~(0x01000000 |
1455 data |= (0x01000000 |
1465 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0), data);
1468 static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable)
1472 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
1474 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS))
1480 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data);
1483 static void soc15_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev,
1488 def = data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));
1490 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG))
1491 data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
1492 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK);
1494 data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
1495 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK;
1498 WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0), data);
1501 static int soc15_common_set_clockgating_state(void *handle,
1502 enum amd_clockgating_state state)
1504 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1506 if (amdgpu_sriov_vf(adev))
1509 switch (adev->asic_type) {
1513 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
1514 state == AMD_CG_STATE_GATE);
1515 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
1516 state == AMD_CG_STATE_GATE);
1517 soc15_update_hdp_light_sleep(adev,
1518 state == AMD_CG_STATE_GATE);
1519 soc15_update_drm_clock_gating(adev,
1520 state == AMD_CG_STATE_GATE);
1521 soc15_update_drm_light_sleep(adev,
1522 state == AMD_CG_STATE_GATE);
1523 soc15_update_rom_medium_grain_clock_gating(adev,
1524 state == AMD_CG_STATE_GATE);
1525 adev->df.funcs->update_medium_grain_clock_gating(adev,
1526 state == AMD_CG_STATE_GATE);
1530 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
1531 state == AMD_CG_STATE_GATE);
1532 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
1533 state == AMD_CG_STATE_GATE);
1534 soc15_update_hdp_light_sleep(adev,
1535 state == AMD_CG_STATE_GATE);
1536 soc15_update_drm_clock_gating(adev,
1537 state == AMD_CG_STATE_GATE);
1538 soc15_update_drm_light_sleep(adev,
1539 state == AMD_CG_STATE_GATE);
1540 soc15_update_rom_medium_grain_clock_gating(adev,
1541 state == AMD_CG_STATE_GATE);
1544 soc15_update_hdp_light_sleep(adev,
1545 state == AMD_CG_STATE_GATE);
1553 static void soc15_common_get_clockgating_state(void *handle, u32 *flags)
1555 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1558 if (amdgpu_sriov_vf(adev))
1561 adev->nbio.funcs->get_clockgating_state(adev, flags);
1563 /* AMD_CG_SUPPORT_HDP_LS */
1564 data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
1565 if (data & HDP_MEM_POWER_LS__LS_ENABLE_MASK)
1566 *flags |= AMD_CG_SUPPORT_HDP_LS;
1568 /* AMD_CG_SUPPORT_DRM_MGCG */
1569 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
1570 if (!(data & 0x01000000))
1571 *flags |= AMD_CG_SUPPORT_DRM_MGCG;
1573 /* AMD_CG_SUPPORT_DRM_LS */
1574 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
1576 *flags |= AMD_CG_SUPPORT_DRM_LS;
1578 /* AMD_CG_SUPPORT_ROM_MGCG */
1579 data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));
1580 if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK))
1581 *flags |= AMD_CG_SUPPORT_ROM_MGCG;
1583 adev->df.funcs->get_clockgating_state(adev, flags);
1586 static int soc15_common_set_powergating_state(void *handle,
1587 enum amd_powergating_state state)
1593 const struct amd_ip_funcs soc15_common_ip_funcs = {
1594 .name = "soc15_common",
1595 .early_init = soc15_common_early_init,
1596 .late_init = soc15_common_late_init,
1597 .sw_init = soc15_common_sw_init,
1598 .sw_fini = soc15_common_sw_fini,
1599 .hw_init = soc15_common_hw_init,
1600 .hw_fini = soc15_common_hw_fini,
1601 .suspend = soc15_common_suspend,
1602 .resume = soc15_common_resume,
1603 .is_idle = soc15_common_is_idle,
1604 .wait_for_idle = soc15_common_wait_for_idle,
1605 .soft_reset = soc15_common_soft_reset,
1606 .set_clockgating_state = soc15_common_set_clockgating_state,
1607 .set_powergating_state = soc15_common_set_powergating_state,
1608 .get_clockgating_state= soc15_common_get_clockgating_state,