drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include <linux/version.h>
  27 #include <drm/drm_atomic_helper.h>
  28 #include <drm/drm_dp_mst_helper.h>
  29 #include "dm_services.h"
  30 #include "amdgpu.h"
  31 #include "amdgpu_dm.h"
  32 #include "amdgpu_dm_mst_types.h"
  33
  34 #include "dc.h"
  35 #include "dm_helpers.h"
  36
  37 #include "dc_link_ddc.h"
  38
  39 #include "i2caux_interface.h"
  40 #if defined(CONFIG_DEBUG_FS)
  41 #include "amdgpu_dm_debugfs.h"
  42 #endif
  43
  44
  45 #if defined(CONFIG_DRM_AMD_DC_DCN)
  46 #include "dc/dcn20/dcn20_resource.h"
  47 #endif
  48
  49 /* #define TRACE_DPCD */
  50
  51 #ifdef TRACE_DPCD
  52 #define SIDE_BAND_MSG(address) (address >= DP_SIDEBAND_MSG_DOWN_REQ_BASE && address < DP_SINK_COUNT_ESI)
  53
  54 static inline char *side_band_msg_type_to_str(uint32_t address)
  55 {
  56         static char str[10] = {0};
  57
  58         if (address < DP_SIDEBAND_MSG_UP_REP_BASE)
  59                 strcpy(str, "DOWN_REQ");
  60         else if (address < DP_SIDEBAND_MSG_DOWN_REP_BASE)
  61                 strcpy(str, "UP_REP");
  62         else if (address < DP_SIDEBAND_MSG_UP_REQ_BASE)
  63                 strcpy(str, "DOWN_REP");
  64         else
  65                 strcpy(str, "UP_REQ");
  66
  67         return str;
  68 }
  69
  70 static void log_dpcd(uint8_t type,
  71                      uint32_t address,
  72                      uint8_t *data,
  73                      uint32_t size,
  74                      bool res)
  75 {
  76         DRM_DEBUG_KMS("Op: %s, addr: %04x, SideBand Msg: %s, Op res: %s\n",
  77                         (type == DP_AUX_NATIVE_READ) ||
  78                         (type == DP_AUX_I2C_READ) ?
  79                                         "Read" : "Write",
  80                         address,
  81                         SIDE_BAND_MSG(address) ?
  82                                         side_band_msg_type_to_str(address) : "Nop",
  83                         res ? "OK" : "Fail");
  84
  85         if (res) {
  86                 print_hex_dump(KERN_INFO, "Body: ", DUMP_PREFIX_NONE, 16, 1, data, size, false);
  87         }
  88 }
  89 #endif
  90
  91 static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux,
  92                                   struct drm_dp_aux_msg *msg)
  93 {
  94         ssize_t result = 0;
  95         struct aux_payload payload;
  96         enum aux_channel_operation_result operation_result;
  97
  98         if (WARN_ON(msg->size > 16))
  99                 return -E2BIG;
 100
 101         payload.address = msg->address;
 102         payload.data = msg->buffer;
 103         payload.length = msg->size;
 104         payload.reply = &msg->reply;
 105         payload.i2c_over_aux = (msg->request & DP_AUX_NATIVE_WRITE) == 0;
 106         payload.write = (msg->request & DP_AUX_I2C_READ) == 0;
 107         payload.mot = (msg->request & DP_AUX_I2C_MOT) != 0;
 108         payload.defer_delay = 0;
 109
 110         result = dc_link_aux_transfer_raw(TO_DM_AUX(aux)->ddc_service, &payload,
 111                                       &operation_result);
 112
 113         if (payload.write)
 114                 result = msg->size;
 115
 116         if (result < 0)
 117                 switch (operation_result) {
 118                 case AUX_CHANNEL_OPERATION_SUCCEEDED:
 119                         break;
 120                 case AUX_CHANNEL_OPERATION_FAILED_HPD_DISCON:
 121                 case AUX_CHANNEL_OPERATION_FAILED_REASON_UNKNOWN:
 122                         result = -EIO;
 123                         break;
 124                 case AUX_CHANNEL_OPERATION_FAILED_INVALID_REPLY:
 125                 case AUX_CHANNEL_OPERATION_FAILED_ENGINE_ACQUIRE:
 126                         result = -EBUSY;
 127                         break;
 128                 case AUX_CHANNEL_OPERATION_FAILED_TIMEOUT:
 129                         result = -ETIMEDOUT;
 130                         break;
 131                 }
 132
 133         return result;
 134 }
 135
 136 static void
 137 dm_dp_mst_connector_destroy(struct drm_connector *connector)
 138 {
 139         struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector);
 140         struct amdgpu_encoder *amdgpu_encoder = amdgpu_dm_connector->mst_encoder;
 141
 142         kfree(amdgpu_dm_connector->edid);
 143         amdgpu_dm_connector->edid = NULL;
 144
 145         drm_encoder_cleanup(&amdgpu_encoder->base);
 146         kfree(amdgpu_encoder);
 147         drm_connector_cleanup(connector);
 148         drm_dp_mst_put_port_malloc(amdgpu_dm_connector->port);
 149         kfree(amdgpu_dm_connector);
 150 }
 151
 152 static int
 153 amdgpu_dm_mst_connector_late_register(struct drm_connector *connector)
 154 {
 155         struct amdgpu_dm_connector *amdgpu_dm_connector =
 156                 to_amdgpu_dm_connector(connector);
 157         int r;
 158
 159         amdgpu_dm_connector->dm_dp_aux.aux.dev = connector->kdev;
 160         r = drm_dp_aux_register(&amdgpu_dm_connector->dm_dp_aux.aux);
 161         if (r)
 162                 return r;
 163
 164 #if defined(CONFIG_DEBUG_FS)
 165         connector_debugfs_init(amdgpu_dm_connector);
 166 #endif
 167
 168         return r;
 169 }
 170
 171 static void
 172 amdgpu_dm_mst_connector_early_unregister(struct drm_connector *connector)
 173 {
 174         struct amdgpu_dm_connector *amdgpu_dm_connector =
 175                 to_amdgpu_dm_connector(connector);
 176         struct drm_dp_mst_port *port = amdgpu_dm_connector->port;
 177
 178         drm_dp_mst_connector_early_unregister(connector, port);
 179 }
 180
 181 static const struct drm_connector_funcs dm_dp_mst_connector_funcs = {
 182         .fill_modes = drm_helper_probe_single_connector_modes,
 183         .destroy = dm_dp_mst_connector_destroy,
 184         .reset = amdgpu_dm_connector_funcs_reset,
 185         .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
 186         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 187         .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
 188         .atomic_get_property = amdgpu_dm_connector_atomic_get_property,
 189         .late_register = amdgpu_dm_mst_connector_late_register,
 190         .early_unregister = amdgpu_dm_mst_connector_early_unregister,
 191 };
 192
 193 #if defined(CONFIG_DRM_AMD_DC_DCN)
 194 static bool validate_dsc_caps_on_connector(struct amdgpu_dm_connector *aconnector)
 195 {
 196         struct dc_sink *dc_sink = aconnector->dc_sink;
 197         struct drm_dp_mst_port *port = aconnector->port;
 198         u8 dsc_caps[16] = { 0 };
 199
 200         aconnector->dsc_aux = drm_dp_mst_dsc_aux_for_port(port);
 201
 202         if (!aconnector->dsc_aux)
 203                 return false;
 204
 205         if (drm_dp_dpcd_read(aconnector->dsc_aux, DP_DSC_SUPPORT, dsc_caps, 16) < 0)
 206                 return false;
 207
 208         if (!dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc,
 209                                    dsc_caps, NULL,
 210                                    &dc_sink->dsc_caps.dsc_dec_caps))
 211                 return false;
 212
 213         return true;
 214 }
 215 #endif
 216
 217 static int dm_dp_mst_get_modes(struct drm_connector *connector)
 218 {
 219         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
 220         int ret = 0;
 221
 222         if (!aconnector)
 223                 return drm_add_edid_modes(connector, NULL);
 224
 225         if (!aconnector->edid) {
 226                 struct edid *edid;
 227                 edid = drm_dp_mst_get_edid(connector, &aconnector->mst_port->mst_mgr, aconnector->port);
 228
 229                 if (!edid) {
 230                         drm_connector_update_edid_property(
 231                                 &aconnector->base,
 232                                 NULL);
 233                         return ret;
 234                 }
 235
 236                 aconnector->edid = edid;
 237         }
 238
 239         if (aconnector->dc_sink && aconnector->dc_sink->sink_signal == SIGNAL_TYPE_VIRTUAL) {
 240                 dc_sink_release(aconnector->dc_sink);
 241                 aconnector->dc_sink = NULL;
 242         }
 243
 244         if (!aconnector->dc_sink) {
 245                 struct dc_sink *dc_sink;
 246                 struct dc_sink_init_data init_params = {
 247                                 .link = aconnector->dc_link,
 248                                 .sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST };
 249                 dc_sink = dc_link_add_remote_sink(
 250                         aconnector->dc_link,
 251                         (uint8_t *)aconnector->edid,
 252                         (aconnector->edid->extensions + 1) * EDID_LENGTH,
 253                         &init_params);
 254
 255                 dc_sink->priv = aconnector;
 256                 /* dc_link_add_remote_sink returns a new reference */
 257                 aconnector->dc_sink = dc_sink;
 258
 259                 if (aconnector->dc_sink) {
 260                         amdgpu_dm_update_freesync_caps(
 261                                         connector, aconnector->edid);
 262
 263 #if defined(CONFIG_DRM_AMD_DC_DCN)
 264                         if (!validate_dsc_caps_on_connector(aconnector))
 265                                 memset(&aconnector->dc_sink->dsc_caps,
 266                                        0, sizeof(aconnector->dc_sink->dsc_caps));
 267 #endif
 268                 }
 269         }
 270
 271         drm_connector_update_edid_property(
 272                                         &aconnector->base, aconnector->edid);
 273
 274         ret = drm_add_edid_modes(connector, aconnector->edid);
 275
 276         return ret;
 277 }
 278
 279 static struct drm_encoder *
 280 dm_mst_atomic_best_encoder(struct drm_connector *connector,
 281                            struct drm_connector_state *connector_state)
 282 {
 283         return &to_amdgpu_dm_connector(connector)->mst_encoder->base;
 284 }
 285
 286 static int
 287 dm_dp_mst_detect(struct drm_connector *connector,
 288                  struct drm_modeset_acquire_ctx *ctx, bool force)
 289 {
 290         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
 291         struct amdgpu_dm_connector *master = aconnector->mst_port;
 292
 293         return drm_dp_mst_detect_port(connector, ctx, &master->mst_mgr,
 294                                       aconnector->port);
 295 }
 296
 297 static int dm_dp_mst_atomic_check(struct drm_connector *connector,
 298                                 struct drm_atomic_state *state)
 299 {
 300         struct drm_connector_state *new_conn_state =
 301                         drm_atomic_get_new_connector_state(state, connector);
 302         struct drm_connector_state *old_conn_state =
 303                         drm_atomic_get_old_connector_state(state, connector);
 304         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
 305         struct drm_crtc_state *new_crtc_state;
 306         struct drm_dp_mst_topology_mgr *mst_mgr;
 307         struct drm_dp_mst_port *mst_port;
 308
 309         mst_port = aconnector->port;
 310         mst_mgr = &aconnector->mst_port->mst_mgr;
 311
 312         if (!old_conn_state->crtc)
 313                 return 0;
 314
 315         if (new_conn_state->crtc) {
 316                 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc);
 317                 if (!new_crtc_state ||
 318                     !drm_atomic_crtc_needs_modeset(new_crtc_state) ||
 319                     new_crtc_state->enable)
 320                         return 0;
 321                 }
 322
 323         return drm_dp_atomic_release_vcpi_slots(state,
 324                                                 mst_mgr,
 325                                                 mst_port);
 326 }
 327
 328 static const struct drm_connector_helper_funcs dm_dp_mst_connector_helper_funcs = {
 329         .get_modes = dm_dp_mst_get_modes,
 330         .mode_valid = amdgpu_dm_connector_mode_valid,
 331         .atomic_best_encoder = dm_mst_atomic_best_encoder,
 332         .detect_ctx = dm_dp_mst_detect,
 333         .atomic_check = dm_dp_mst_atomic_check,
 334 };
 335
 336 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
 337 {
 338         drm_encoder_cleanup(encoder);
 339         kfree(encoder);
 340 }
 341
 342 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
 343         .destroy = amdgpu_dm_encoder_destroy,
 344 };
 345
 346 static struct amdgpu_encoder *
 347 dm_dp_create_fake_mst_encoder(struct amdgpu_dm_connector *connector)
 348 {
 349         struct drm_device *dev = connector->base.dev;
 350         struct amdgpu_device *adev = dev->dev_private;
 351         struct amdgpu_encoder *amdgpu_encoder;
 352         struct drm_encoder *encoder;
 353
 354         amdgpu_encoder = kzalloc(sizeof(*amdgpu_encoder), GFP_KERNEL);
 355         if (!amdgpu_encoder)
 356                 return NULL;
 357
 358         encoder = &amdgpu_encoder->base;
 359         encoder->possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
 360
 361         drm_encoder_init(
 362                 dev,
 363                 &amdgpu_encoder->base,
 364                 &amdgpu_dm_encoder_funcs,
 365                 DRM_MODE_ENCODER_DPMST,
 366                 NULL);
 367
 368         drm_encoder_helper_add(encoder, &amdgpu_dm_encoder_helper_funcs);
 369
 370         return amdgpu_encoder;
 371 }
 372
 373 static struct drm_connector *
 374 dm_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
 375                         struct drm_dp_mst_port *port,
 376                         const char *pathprop)
 377 {
 378         struct amdgpu_dm_connector *master = container_of(mgr, struct amdgpu_dm_connector, mst_mgr);
 379         struct drm_device *dev = master->base.dev;
 380         struct amdgpu_device *adev = dev->dev_private;
 381         struct amdgpu_dm_connector *aconnector;
 382         struct drm_connector *connector;
 383
 384         aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
 385         if (!aconnector)
 386                 return NULL;
 387
 388         connector = &aconnector->base;
 389         aconnector->port = port;
 390         aconnector->mst_port = master;
 391
 392         if (drm_connector_init(
 393                 dev,
 394                 connector,
 395                 &dm_dp_mst_connector_funcs,
 396                 DRM_MODE_CONNECTOR_DisplayPort)) {
 397                 kfree(aconnector);
 398                 return NULL;
 399         }
 400         drm_connector_helper_add(connector, &dm_dp_mst_connector_helper_funcs);
 401
 402         amdgpu_dm_connector_init_helper(
 403                 &adev->dm,
 404                 aconnector,
 405                 DRM_MODE_CONNECTOR_DisplayPort,
 406                 master->dc_link,
 407                 master->connector_id);
 408
 409         aconnector->mst_encoder = dm_dp_create_fake_mst_encoder(master);
 410         drm_connector_attach_encoder(&aconnector->base,
 411                                      &aconnector->mst_encoder->base);
 412
 413         connector->max_bpc_property = master->base.max_bpc_property;
 414         if (connector->max_bpc_property)
 415                 drm_connector_attach_max_bpc_property(connector, 8, 16);
 416
 417         connector->vrr_capable_property = master->base.vrr_capable_property;
 418         if (connector->vrr_capable_property)
 419                 drm_connector_attach_vrr_capable_property(connector);
 420
 421         drm_object_attach_property(
 422                 &connector->base,
 423                 dev->mode_config.path_property,
 424                 0);
 425         drm_object_attach_property(
 426                 &connector->base,
 427                 dev->mode_config.tile_property,
 428                 0);
 429
 430         drm_connector_set_path_property(connector, pathprop);
 431
 432         /*
 433          * Initialize connector state before adding the connectror to drm and
 434          * framebuffer lists
 435          */
 436         amdgpu_dm_connector_funcs_reset(connector);
 437
 438         DRM_INFO("DM_MST: added connector: %p [id: %d] [master: %p]\n",
 439                  aconnector, connector->base.id, aconnector->mst_port);
 440
 441         drm_dp_mst_get_port_malloc(port);
 442
 443         DRM_DEBUG_KMS(":%d\n", connector->base.id);
 444
 445         return connector;
 446 }
 447
 448 static void dm_dp_destroy_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
 449                                         struct drm_connector *connector)
 450 {
 451         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
 452
 453         DRM_INFO("DM_MST: Disabling connector: %p [id: %d] [master: %p]\n",
 454                  aconnector, connector->base.id, aconnector->mst_port);
 455
 456         if (aconnector->dc_sink) {
 457                 amdgpu_dm_update_freesync_caps(connector, NULL);
 458                 dc_link_remove_remote_sink(aconnector->dc_link,
 459                                            aconnector->dc_sink);
 460                 dc_sink_release(aconnector->dc_sink);
 461                 aconnector->dc_sink = NULL;
 462                 aconnector->dc_link->cur_link_settings.lane_count = 0;
 463         }
 464
 465         drm_connector_unregister(connector);
 466         drm_connector_put(connector);
 467 }
 468
 469 static const struct drm_dp_mst_topology_cbs dm_mst_cbs = {
 470         .add_connector = dm_dp_add_mst_connector,
 471         .destroy_connector = dm_dp_destroy_mst_connector,
 472 };
 473
 474 void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm,
 475                                        struct amdgpu_dm_connector *aconnector)
 476 {
 477         aconnector->dm_dp_aux.aux.name = "dmdc";
 478         aconnector->dm_dp_aux.aux.transfer = dm_dp_aux_transfer;
 479         aconnector->dm_dp_aux.ddc_service = aconnector->dc_link->ddc;
 480
 481         drm_dp_aux_init(&aconnector->dm_dp_aux.aux);
 482         drm_dp_cec_register_connector(&aconnector->dm_dp_aux.aux,
 483                                       &aconnector->base);
 484
 485         if (aconnector->base.connector_type == DRM_MODE_CONNECTOR_eDP)
 486                 return;
 487
 488         aconnector->mst_mgr.cbs = &dm_mst_cbs;
 489         drm_dp_mst_topology_mgr_init(
 490                 &aconnector->mst_mgr,
 491                 dm->adev->ddev,
 492                 &aconnector->dm_dp_aux.aux,
 493                 16,
 494                 4,
 495                 aconnector->connector_id);
 496 }
 497
 498 int dm_mst_get_pbn_divider(struct dc_link *link)
 499 {
 500         if (!link)
 501                 return 0;
 502
 503         return dc_link_bandwidth_kbps(link,
 504                         dc_link_get_link_cap(link)) / (8 * 1000 * 54);
 505 }
 506
 507 #if defined(CONFIG_DRM_AMD_DC_DCN)
 508
 509 struct dsc_mst_fairness_params {
 510         struct dc_crtc_timing *timing;
 511         struct dc_sink *sink;
 512         struct dc_dsc_bw_range bw_range;
 513         bool compression_possible;
 514         struct drm_dp_mst_port *port;
 515 };
 516
 517 struct dsc_mst_fairness_vars {
 518         int pbn;
 519         bool dsc_enabled;
 520         int bpp_x16;
 521 };
 522
 523 static int kbps_to_peak_pbn(int kbps)
 524 {
 525         u64 peak_kbps = kbps;
 526
 527         peak_kbps *= 1006;
 528         peak_kbps = div_u64(peak_kbps, 1000);
 529         return (int) DIV64_U64_ROUND_UP(peak_kbps * 64, (54 * 8 * 1000));
 530 }
 531
 532 static void set_dsc_configs_from_fairness_vars(struct dsc_mst_fairness_params *params,
 533                 struct dsc_mst_fairness_vars *vars,
 534                 int count)
 535 {
 536         int i;
 537
 538         for (i = 0; i < count; i++) {
 539                 memset(&params[i].timing->dsc_cfg, 0, sizeof(params[i].timing->dsc_cfg));
 540                 if (vars[i].dsc_enabled && dc_dsc_compute_config(
 541                                         params[i].sink->ctx->dc->res_pool->dscs[0],
 542                                         &params[i].sink->dsc_caps.dsc_dec_caps,
 543                                         params[i].sink->ctx->dc->debug.dsc_min_slice_height_override,
 544                                         0,
 545                                         params[i].timing,
 546                                         &params[i].timing->dsc_cfg)) {
 547                         params[i].timing->flags.DSC = 1;
 548                         params[i].timing->dsc_cfg.bits_per_pixel = vars[i].bpp_x16;
 549                 } else {
 550                         params[i].timing->flags.DSC = 0;
 551                 }
 552         }
 553 }
 554
 555 static int bpp_x16_from_pbn(struct dsc_mst_fairness_params param, int pbn)
 556 {
 557         struct dc_dsc_config dsc_config;
 558         u64 kbps;
 559
 560         kbps = div_u64((u64)pbn * 994 * 8 * 54, 64);
 561         dc_dsc_compute_config(
 562                         param.sink->ctx->dc->res_pool->dscs[0],
 563                         &param.sink->dsc_caps.dsc_dec_caps,
 564                         param.sink->ctx->dc->debug.dsc_min_slice_height_override,
 565                         (int) kbps, param.timing, &dsc_config);
 566
 567         return dsc_config.bits_per_pixel;
 568 }
 569
 570 static void increase_dsc_bpp(struct drm_atomic_state *state,
 571                              struct dc_link *dc_link,
 572                              struct dsc_mst_fairness_params *params,
 573                              struct dsc_mst_fairness_vars *vars,
 574                              int count)
 575 {
 576         int i;
 577         bool bpp_increased[MAX_PIPES];
 578         int initial_slack[MAX_PIPES];
 579         int min_initial_slack;
 580         int next_index;
 581         int remaining_to_increase = 0;
 582         int pbn_per_timeslot;
 583         int link_timeslots_used;
 584         int fair_pbn_alloc;
 585
 586         for (i = 0; i < count; i++) {
 587                 if (vars[i].dsc_enabled) {
 588                         initial_slack[i] = kbps_to_peak_pbn(params[i].bw_range.max_kbps) - vars[i].pbn;
 589                         bpp_increased[i] = false;
 590                         remaining_to_increase += 1;
 591                 } else {
 592                         initial_slack[i] = 0;
 593                         bpp_increased[i] = true;
 594                 }
 595         }
 596
 597         pbn_per_timeslot = dc_link_bandwidth_kbps(dc_link,
 598                         dc_link_get_link_cap(dc_link)) / (8 * 1000 * 54);
 599
 600         while (remaining_to_increase) {
 601                 next_index = -1;
 602                 min_initial_slack = -1;
 603                 for (i = 0; i < count; i++) {
 604                         if (!bpp_increased[i]) {
 605                                 if (min_initial_slack == -1 || min_initial_slack > initial_slack[i]) {
 606                                         min_initial_slack = initial_slack[i];
 607                                         next_index = i;
 608                                 }
 609                         }
 610                 }
 611
 612                 if (next_index == -1)
 613                         break;
 614
 615                 link_timeslots_used = 0;
 616
 617                 for (i = 0; i < count; i++)
 618                         link_timeslots_used += DIV_ROUND_UP(vars[i].pbn, pbn_per_timeslot);
 619
 620                 fair_pbn_alloc = (63 - link_timeslots_used) / remaining_to_increase * pbn_per_timeslot;
 621
 622                 if (initial_slack[next_index] > fair_pbn_alloc) {
 623                         vars[next_index].pbn += fair_pbn_alloc;
 624                         if (drm_dp_atomic_find_vcpi_slots(state,
 625                                                           params[next_index].port->mgr,
 626                                                           params[next_index].port,
 627                                                           vars[next_index].pbn,
 628                                                           dm_mst_get_pbn_divider(dc_link)) < 0)
 629                                 return;
 630                         if (!drm_dp_mst_atomic_check(state)) {
 631                                 vars[next_index].bpp_x16 = bpp_x16_from_pbn(params[next_index], vars[next_index].pbn);
 632                         } else {
 633                                 vars[next_index].pbn -= fair_pbn_alloc;
 634                                 if (drm_dp_atomic_find_vcpi_slots(state,
 635                                                                   params[next_index].port->mgr,
 636                                                                   params[next_index].port,
 637                                                                   vars[next_index].pbn,
 638                                                                   dm_mst_get_pbn_divider(dc_link)) < 0)
 639                                         return;
 640                         }
 641                 } else {
 642                         vars[next_index].pbn += initial_slack[next_index];
 643                         if (drm_dp_atomic_find_vcpi_slots(state,
 644                                                           params[next_index].port->mgr,
 645                                                           params[next_index].port,
 646                                                           vars[next_index].pbn,
 647                                                           dm_mst_get_pbn_divider(dc_link)) < 0)
 648                                 return;
 649                         if (!drm_dp_mst_atomic_check(state)) {
 650                                 vars[next_index].bpp_x16 = params[next_index].bw_range.max_target_bpp_x16;
 651                         } else {
 652                                 vars[next_index].pbn -= initial_slack[next_index];
 653                                 if (drm_dp_atomic_find_vcpi_slots(state,
 654                                                                   params[next_index].port->mgr,
 655                                                                   params[next_index].port,
 656                                                                   vars[next_index].pbn,
 657                                                                   dm_mst_get_pbn_divider(dc_link)) < 0)
 658                                         return;
 659                         }
 660                 }
 661
 662                 bpp_increased[next_index] = true;
 663                 remaining_to_increase--;
 664         }
 665 }
 666
 667 static void try_disable_dsc(struct drm_atomic_state *state,
 668                             struct dc_link *dc_link,
 669                             struct dsc_mst_fairness_params *params,
 670                             struct dsc_mst_fairness_vars *vars,
 671                             int count)
 672 {
 673         int i;
 674         bool tried[MAX_PIPES];
 675         int kbps_increase[MAX_PIPES];
 676         int max_kbps_increase;
 677         int next_index;
 678         int remaining_to_try = 0;
 679
 680         for (i = 0; i < count; i++) {
 681                 if (vars[i].dsc_enabled && vars[i].bpp_x16 == params[i].bw_range.max_target_bpp_x16) {
 682                         kbps_increase[i] = params[i].bw_range.stream_kbps - params[i].bw_range.max_kbps;
 683                         tried[i] = false;
 684                         remaining_to_try += 1;
 685                 } else {
 686                         kbps_increase[i] = 0;
 687                         tried[i] = true;
 688                 }
 689         }
 690
 691         while (remaining_to_try) {
 692                 next_index = -1;
 693                 max_kbps_increase = -1;
 694                 for (i = 0; i < count; i++) {
 695                         if (!tried[i]) {
 696                                 if (max_kbps_increase == -1 || max_kbps_increase < kbps_increase[i]) {
 697                                         max_kbps_increase = kbps_increase[i];
 698                                         next_index = i;
 699                                 }
 700                         }
 701                 }
 702
 703                 if (next_index == -1)
 704                         break;
 705
 706                 vars[next_index].pbn = kbps_to_peak_pbn(params[next_index].bw_range.stream_kbps);
 707                 if (drm_dp_atomic_find_vcpi_slots(state,
 708                                                   params[next_index].port->mgr,
 709                                                   params[next_index].port,
 710                                                   vars[next_index].pbn,
 711                                                   0) < 0)
 712                         return;
 713
 714                 if (!drm_dp_mst_atomic_check(state)) {
 715                         vars[next_index].dsc_enabled = false;
 716                         vars[next_index].bpp_x16 = 0;
 717                 } else {
 718                         vars[next_index].pbn = kbps_to_peak_pbn(params[next_index].bw_range.max_kbps);
 719                         if (drm_dp_atomic_find_vcpi_slots(state,
 720                                                           params[next_index].port->mgr,
 721                                                           params[next_index].port,
 722                                                           vars[next_index].pbn,
 723                                                           dm_mst_get_pbn_divider(dc_link)) < 0)
 724                                 return;
 725                 }
 726
 727                 tried[next_index] = true;
 728                 remaining_to_try--;
 729         }
 730 }
 731
 732 static bool compute_mst_dsc_configs_for_link(struct drm_atomic_state *state,
 733                                              struct dc_state *dc_state,
 734                                              struct dc_link *dc_link)
 735 {
 736         int i;
 737         struct dc_stream_state *stream;
 738         struct dsc_mst_fairness_params params[MAX_PIPES];
 739         struct dsc_mst_fairness_vars vars[MAX_PIPES];
 740         struct amdgpu_dm_connector *aconnector;
 741         int count = 0;
 742
 743         memset(params, 0, sizeof(params));
 744
 745         /* Set up params */
 746         for (i = 0; i < dc_state->stream_count; i++) {
 747                 struct dc_dsc_policy dsc_policy = {0};
 748
 749                 stream = dc_state->streams[i];
 750
 751                 if (stream->link != dc_link)
 752                         continue;
 753
 754                 stream->timing.flags.DSC = 0;
 755
 756                 params[count].timing = &stream->timing;
 757                 params[count].sink = stream->sink;
 758                 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
 759                 params[count].port = aconnector->port;
 760                 params[count].compression_possible = stream->sink->dsc_caps.dsc_dec_caps.is_dsc_supported;
 761                 dc_dsc_get_policy_for_timing(params[count].timing, &dsc_policy);
 762                 if (!dc_dsc_compute_bandwidth_range(
 763                                 stream->sink->ctx->dc->res_pool->dscs[0],
 764                                 stream->sink->ctx->dc->debug.dsc_min_slice_height_override,
 765                                 dsc_policy.min_target_bpp,
 766                                 dsc_policy.max_target_bpp,
 767                                 &stream->sink->dsc_caps.dsc_dec_caps,
 768                                 &stream->timing, &params[count].bw_range))
 769                         params[count].bw_range.stream_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing);
 770
 771                 count++;
 772         }
 773         /* Try no compression */
 774         for (i = 0; i < count; i++) {
 775                 vars[i].pbn = kbps_to_peak_pbn(params[i].bw_range.stream_kbps);
 776                 vars[i].dsc_enabled = false;
 777                 vars[i].bpp_x16 = 0;
 778                 if (drm_dp_atomic_find_vcpi_slots(state,
 779                                                  params[i].port->mgr,
 780                                                  params[i].port,
 781                                                  vars[i].pbn,
 782                                                  0) < 0)
 783                         return false;
 784         }
 785         if (!drm_dp_mst_atomic_check(state)) {
 786                 set_dsc_configs_from_fairness_vars(params, vars, count);
 787                 return true;
 788         }
 789
 790         /* Try max compression */
 791         for (i = 0; i < count; i++) {
 792                 if (params[i].compression_possible) {
 793                         vars[i].pbn = kbps_to_peak_pbn(params[i].bw_range.min_kbps);
 794                         vars[i].dsc_enabled = true;
 795                         vars[i].bpp_x16 = params[i].bw_range.min_target_bpp_x16;
 796                         if (drm_dp_atomic_find_vcpi_slots(state,
 797                                                           params[i].port->mgr,
 798                                                           params[i].port,
 799                                                           vars[i].pbn,
 800                                                           dm_mst_get_pbn_divider(dc_link)) < 0)
 801                                 return false;
 802                 } else {
 803                         vars[i].pbn = kbps_to_peak_pbn(params[i].bw_range.stream_kbps);
 804                         vars[i].dsc_enabled = false;
 805                         vars[i].bpp_x16 = 0;
 806                         if (drm_dp_atomic_find_vcpi_slots(state,
 807                                                           params[i].port->mgr,
 808                                                           params[i].port,
 809                                                           vars[i].pbn,
 810                                                           0) < 0)
 811                                 return false;
 812                 }
 813         }
 814         if (drm_dp_mst_atomic_check(state))
 815                 return false;
 816
 817         /* Optimize degree of compression */
 818         increase_dsc_bpp(state, dc_link, params, vars, count);
 819
 820         try_disable_dsc(state, dc_link, params, vars, count);
 821
 822         set_dsc_configs_from_fairness_vars(params, vars, count);
 823
 824         return true;
 825 }
 826
 827 bool compute_mst_dsc_configs_for_state(struct drm_atomic_state *state,
 828                                        struct dc_state *dc_state)
 829 {
 830         int i, j;
 831         struct dc_stream_state *stream;
 832         bool computed_streams[MAX_PIPES];
 833         struct amdgpu_dm_connector *aconnector;
 834
 835         for (i = 0; i < dc_state->stream_count; i++)
 836                 computed_streams[i] = false;
 837
 838         for (i = 0; i < dc_state->stream_count; i++) {
 839                 stream = dc_state->streams[i];
 840
 841                 if (stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST)
 842                         continue;
 843
 844                 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
 845
 846                 if (!aconnector || !aconnector->dc_sink)
 847                         continue;
 848
 849                 if (!aconnector->dc_sink->dsc_caps.dsc_dec_caps.is_dsc_supported)
 850                         continue;
 851
 852                 if (computed_streams[i])
 853                         continue;
 854
 855                 mutex_lock(&aconnector->mst_mgr.lock);
 856                 if (!compute_mst_dsc_configs_for_link(state, dc_state, stream->link)) {
 857                         mutex_unlock(&aconnector->mst_mgr.lock);
 858                         return false;
 859                 }
 860                 mutex_unlock(&aconnector->mst_mgr.lock);
 861
 862                 for (j = 0; j < dc_state->stream_count; j++) {
 863                         if (dc_state->streams[j]->link == stream->link)
 864                                 computed_streams[j] = true;
 865                 }
 866         }
 867
 868         for (i = 0; i < dc_state->stream_count; i++) {
 869                 stream = dc_state->streams[i];
 870
 871                 if (stream->timing.flags.DSC == 1)
 872                         dcn20_add_dsc_to_stream_resource(stream->ctx->dc, dc_state, stream);
 873         }
 874
 875         return true;
 876 }
 877
 878 #endif