drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  */
  24 #include <linux/string.h>
  25 #include <linux/acpi.h>
  26
  27 #include <drm/drm_probe_helper.h>
  28 #include <drm/amdgpu_drm.h>
  29 #include "dm_services.h"
  30 #include "amdgpu.h"
  31 #include "amdgpu_dm.h"
  32 #include "amdgpu_dm_irq.h"
  33 #include "amdgpu_pm.h"
  34 #include "dm_pp_smu.h"
  35 #include "amdgpu_smu.h"
  36
  37
  38 bool dm_pp_apply_display_requirements(
  39                 const struct dc_context *ctx,
  40                 const struct dm_pp_display_configuration *pp_display_cfg)
  41 {
  42         struct amdgpu_device *adev = ctx->driver_context;
  43         struct smu_context *smu = &adev->smu;
  44         int i;
  45
  46         if (adev->pm.dpm_enabled) {
  47
  48                 memset(&adev->pm.pm_display_cfg, 0,
  49                                 sizeof(adev->pm.pm_display_cfg));
  50
  51                 adev->pm.pm_display_cfg.cpu_cc6_disable =
  52                         pp_display_cfg->cpu_cc6_disable;
  53
  54                 adev->pm.pm_display_cfg.cpu_pstate_disable =
  55                         pp_display_cfg->cpu_pstate_disable;
  56
  57                 adev->pm.pm_display_cfg.cpu_pstate_separation_time =
  58                         pp_display_cfg->cpu_pstate_separation_time;
  59
  60                 adev->pm.pm_display_cfg.nb_pstate_switch_disable =
  61                         pp_display_cfg->nb_pstate_switch_disable;
  62
  63                 adev->pm.pm_display_cfg.num_display =
  64                                 pp_display_cfg->display_count;
  65                 adev->pm.pm_display_cfg.num_path_including_non_display =
  66                                 pp_display_cfg->display_count;
  67
  68                 adev->pm.pm_display_cfg.min_core_set_clock =
  69                                 pp_display_cfg->min_engine_clock_khz/10;
  70                 adev->pm.pm_display_cfg.min_core_set_clock_in_sr =
  71                                 pp_display_cfg->min_engine_clock_deep_sleep_khz/10;
  72                 adev->pm.pm_display_cfg.min_mem_set_clock =
  73                                 pp_display_cfg->min_memory_clock_khz/10;
  74
  75                 adev->pm.pm_display_cfg.min_dcef_deep_sleep_set_clk =
  76                                 pp_display_cfg->min_engine_clock_deep_sleep_khz/10;
  77                 adev->pm.pm_display_cfg.min_dcef_set_clk =
  78                                 pp_display_cfg->min_dcfclock_khz/10;
  79
  80                 adev->pm.pm_display_cfg.multi_monitor_in_sync =
  81                                 pp_display_cfg->all_displays_in_sync;
  82                 adev->pm.pm_display_cfg.min_vblank_time =
  83                                 pp_display_cfg->avail_mclk_switch_time_us;
  84
  85                 adev->pm.pm_display_cfg.display_clk =
  86                                 pp_display_cfg->disp_clk_khz/10;
  87
  88                 adev->pm.pm_display_cfg.dce_tolerable_mclk_in_active_latency =
  89                                 pp_display_cfg->avail_mclk_switch_time_in_disp_active_us;
  90
  91                 adev->pm.pm_display_cfg.crtc_index = pp_display_cfg->crtc_index;
  92                 adev->pm.pm_display_cfg.line_time_in_us =
  93                                 pp_display_cfg->line_time_in_us;
  94
  95                 adev->pm.pm_display_cfg.vrefresh = pp_display_cfg->disp_configs[0].v_refresh;
  96                 adev->pm.pm_display_cfg.crossfire_display_index = -1;
  97                 adev->pm.pm_display_cfg.min_bus_bandwidth = 0;
  98
  99                 for (i = 0; i < pp_display_cfg->display_count; i++) {
 100                         const struct dm_pp_single_disp_config *dc_cfg =
 101                                                 &pp_display_cfg->disp_configs[i];
 102                         adev->pm.pm_display_cfg.displays[i].controller_id = dc_cfg->pipe_idx + 1;
 103                 }
 104
 105                 if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->display_configuration_change)
 106                         adev->powerplay.pp_funcs->display_configuration_change(
 107                                 adev->powerplay.pp_handle,
 108                                 &adev->pm.pm_display_cfg);
 109                 else
 110                         smu_display_configuration_change(smu,
 111                                                          &adev->pm.pm_display_cfg);
 112
 113                 amdgpu_pm_compute_clocks(adev);
 114         }
 115
 116         return true;
 117 }
 118
 119 static void get_default_clock_levels(
 120                 enum dm_pp_clock_type clk_type,
 121                 struct dm_pp_clock_levels *clks)
 122 {
 123         uint32_t disp_clks_in_khz[6] = {
 124                         300000, 400000, 496560, 626090, 685720, 757900 };
 125         uint32_t sclks_in_khz[6] = {
 126                         300000, 360000, 423530, 514290, 626090, 720000 };
 127         uint32_t mclks_in_khz[2] = { 333000, 800000 };
 128
 129         switch (clk_type) {
 130         case DM_PP_CLOCK_TYPE_DISPLAY_CLK:
 131                 clks->num_levels = 6;
 132                 memmove(clks->clocks_in_khz, disp_clks_in_khz,
 133                                 sizeof(disp_clks_in_khz));
 134                 break;
 135         case DM_PP_CLOCK_TYPE_ENGINE_CLK:
 136                 clks->num_levels = 6;
 137                 memmove(clks->clocks_in_khz, sclks_in_khz,
 138                                 sizeof(sclks_in_khz));
 139                 break;
 140         case DM_PP_CLOCK_TYPE_MEMORY_CLK:
 141                 clks->num_levels = 2;
 142                 memmove(clks->clocks_in_khz, mclks_in_khz,
 143                                 sizeof(mclks_in_khz));
 144                 break;
 145         default:
 146                 clks->num_levels = 0;
 147                 break;
 148         }
 149 }
 150
 151 static enum smu_clk_type dc_to_smu_clock_type(
 152                 enum dm_pp_clock_type dm_pp_clk_type)
 153 {
 154         enum smu_clk_type smu_clk_type = SMU_CLK_COUNT;
 155
 156         switch (dm_pp_clk_type) {
 157         case DM_PP_CLOCK_TYPE_DISPLAY_CLK:
 158                 smu_clk_type = SMU_DISPCLK;
 159                 break;
 160         case DM_PP_CLOCK_TYPE_ENGINE_CLK:
 161                 smu_clk_type = SMU_GFXCLK;
 162                 break;
 163         case DM_PP_CLOCK_TYPE_MEMORY_CLK:
 164                 smu_clk_type = SMU_MCLK;
 165                 break;
 166         case DM_PP_CLOCK_TYPE_DCEFCLK:
 167                 smu_clk_type = SMU_DCEFCLK;
 168                 break;
 169         case DM_PP_CLOCK_TYPE_SOCCLK:
 170                 smu_clk_type = SMU_SOCCLK;
 171                 break;
 172         default:
 173                 DRM_ERROR("DM_PPLIB: invalid clock type: %d!\n",
 174                           dm_pp_clk_type);
 175                 break;
 176         }
 177
 178         return smu_clk_type;
 179 }
 180
 181 static enum amd_pp_clock_type dc_to_pp_clock_type(
 182                 enum dm_pp_clock_type dm_pp_clk_type)
 183 {
 184         enum amd_pp_clock_type amd_pp_clk_type = 0;
 185
 186         switch (dm_pp_clk_type) {
 187         case DM_PP_CLOCK_TYPE_DISPLAY_CLK:
 188                 amd_pp_clk_type = amd_pp_disp_clock;
 189                 break;
 190         case DM_PP_CLOCK_TYPE_ENGINE_CLK:
 191                 amd_pp_clk_type = amd_pp_sys_clock;
 192                 break;
 193         case DM_PP_CLOCK_TYPE_MEMORY_CLK:
 194                 amd_pp_clk_type = amd_pp_mem_clock;
 195                 break;
 196         case DM_PP_CLOCK_TYPE_DCEFCLK:
 197                 amd_pp_clk_type  = amd_pp_dcef_clock;
 198                 break;
 199         case DM_PP_CLOCK_TYPE_DCFCLK:
 200                 amd_pp_clk_type = amd_pp_dcf_clock;
 201                 break;
 202         case DM_PP_CLOCK_TYPE_PIXELCLK:
 203                 amd_pp_clk_type = amd_pp_pixel_clock;
 204                 break;
 205         case DM_PP_CLOCK_TYPE_FCLK:
 206                 amd_pp_clk_type = amd_pp_f_clock;
 207                 break;
 208         case DM_PP_CLOCK_TYPE_DISPLAYPHYCLK:
 209                 amd_pp_clk_type = amd_pp_phy_clock;
 210                 break;
 211         case DM_PP_CLOCK_TYPE_DPPCLK:
 212                 amd_pp_clk_type = amd_pp_dpp_clock;
 213                 break;
 214         default:
 215                 DRM_ERROR("DM_PPLIB: invalid clock type: %d!\n",
 216                                 dm_pp_clk_type);
 217                 break;
 218         }
 219
 220         return amd_pp_clk_type;
 221 }
 222
 223 static enum dm_pp_clocks_state pp_to_dc_powerlevel_state(
 224                         enum PP_DAL_POWERLEVEL max_clocks_state)
 225 {
 226         switch (max_clocks_state) {
 227         case PP_DAL_POWERLEVEL_0:
 228                 return DM_PP_CLOCKS_DPM_STATE_LEVEL_0;
 229         case PP_DAL_POWERLEVEL_1:
 230                 return DM_PP_CLOCKS_DPM_STATE_LEVEL_1;
 231         case PP_DAL_POWERLEVEL_2:
 232                 return DM_PP_CLOCKS_DPM_STATE_LEVEL_2;
 233         case PP_DAL_POWERLEVEL_3:
 234                 return DM_PP_CLOCKS_DPM_STATE_LEVEL_3;
 235         case PP_DAL_POWERLEVEL_4:
 236                 return DM_PP_CLOCKS_DPM_STATE_LEVEL_4;
 237         case PP_DAL_POWERLEVEL_5:
 238                 return DM_PP_CLOCKS_DPM_STATE_LEVEL_5;
 239         case PP_DAL_POWERLEVEL_6:
 240                 return DM_PP_CLOCKS_DPM_STATE_LEVEL_6;
 241         case PP_DAL_POWERLEVEL_7:
 242                 return DM_PP_CLOCKS_DPM_STATE_LEVEL_7;
 243         default:
 244                 DRM_ERROR("DM_PPLIB: invalid powerlevel state: %d!\n",
 245                                 max_clocks_state);
 246                 return DM_PP_CLOCKS_STATE_INVALID;
 247         }
 248 }
 249
 250 static void pp_to_dc_clock_levels(
 251                 const struct amd_pp_clocks *pp_clks,
 252                 struct dm_pp_clock_levels *dc_clks,
 253                 enum dm_pp_clock_type dc_clk_type)
 254 {
 255         uint32_t i;
 256
 257         if (pp_clks->count > DM_PP_MAX_CLOCK_LEVELS) {
 258                 DRM_INFO("DM_PPLIB: Warning: %s clock: number of levels %d exceeds maximum of %d!\n",
 259                                 DC_DECODE_PP_CLOCK_TYPE(dc_clk_type),
 260                                 pp_clks->count,
 261                                 DM_PP_MAX_CLOCK_LEVELS);
 262
 263                 dc_clks->num_levels = DM_PP_MAX_CLOCK_LEVELS;
 264         } else
 265                 dc_clks->num_levels = pp_clks->count;
 266
 267         DRM_INFO("DM_PPLIB: values for %s clock\n",
 268                         DC_DECODE_PP_CLOCK_TYPE(dc_clk_type));
 269
 270         for (i = 0; i < dc_clks->num_levels; i++) {
 271                 DRM_INFO("DM_PPLIB:\t %d\n", pp_clks->clock[i]);
 272                 dc_clks->clocks_in_khz[i] = pp_clks->clock[i];
 273         }
 274 }
 275
 276 static void pp_to_dc_clock_levels_with_latency(
 277                 const struct pp_clock_levels_with_latency *pp_clks,
 278                 struct dm_pp_clock_levels_with_latency *clk_level_info,
 279                 enum dm_pp_clock_type dc_clk_type)
 280 {
 281         uint32_t i;
 282
 283         if (pp_clks->num_levels > DM_PP_MAX_CLOCK_LEVELS) {
 284                 DRM_INFO("DM_PPLIB: Warning: %s clock: number of levels %d exceeds maximum of %d!\n",
 285                                 DC_DECODE_PP_CLOCK_TYPE(dc_clk_type),
 286                                 pp_clks->num_levels,
 287                                 DM_PP_MAX_CLOCK_LEVELS);
 288
 289                 clk_level_info->num_levels = DM_PP_MAX_CLOCK_LEVELS;
 290         } else
 291                 clk_level_info->num_levels = pp_clks->num_levels;
 292
 293         DRM_DEBUG("DM_PPLIB: values for %s clock\n",
 294                         DC_DECODE_PP_CLOCK_TYPE(dc_clk_type));
 295
 296         for (i = 0; i < clk_level_info->num_levels; i++) {
 297                 DRM_DEBUG("DM_PPLIB:\t %d in kHz\n", pp_clks->data[i].clocks_in_khz);
 298                 clk_level_info->data[i].clocks_in_khz = pp_clks->data[i].clocks_in_khz;
 299                 clk_level_info->data[i].latency_in_us = pp_clks->data[i].latency_in_us;
 300         }
 301 }
 302
 303 static void pp_to_dc_clock_levels_with_voltage(
 304                 const struct pp_clock_levels_with_voltage *pp_clks,
 305                 struct dm_pp_clock_levels_with_voltage *clk_level_info,
 306                 enum dm_pp_clock_type dc_clk_type)
 307 {
 308         uint32_t i;
 309
 310         if (pp_clks->num_levels > DM_PP_MAX_CLOCK_LEVELS) {
 311                 DRM_INFO("DM_PPLIB: Warning: %s clock: number of levels %d exceeds maximum of %d!\n",
 312                                 DC_DECODE_PP_CLOCK_TYPE(dc_clk_type),
 313                                 pp_clks->num_levels,
 314                                 DM_PP_MAX_CLOCK_LEVELS);
 315
 316                 clk_level_info->num_levels = DM_PP_MAX_CLOCK_LEVELS;
 317         } else
 318                 clk_level_info->num_levels = pp_clks->num_levels;
 319
 320         DRM_INFO("DM_PPLIB: values for %s clock\n",
 321                         DC_DECODE_PP_CLOCK_TYPE(dc_clk_type));
 322
 323         for (i = 0; i < clk_level_info->num_levels; i++) {
 324                 DRM_INFO("DM_PPLIB:\t %d in kHz, %d in mV\n", pp_clks->data[i].clocks_in_khz,
 325                          pp_clks->data[i].voltage_in_mv);
 326                 clk_level_info->data[i].clocks_in_khz = pp_clks->data[i].clocks_in_khz;
 327                 clk_level_info->data[i].voltage_in_mv = pp_clks->data[i].voltage_in_mv;
 328         }
 329 }
 330
 331 bool dm_pp_get_clock_levels_by_type(
 332                 const struct dc_context *ctx,
 333                 enum dm_pp_clock_type clk_type,
 334                 struct dm_pp_clock_levels *dc_clks)
 335 {
 336         struct amdgpu_device *adev = ctx->driver_context;
 337         void *pp_handle = adev->powerplay.pp_handle;
 338         struct amd_pp_clocks pp_clks = { 0 };
 339         struct amd_pp_simple_clock_info validation_clks = { 0 };
 340         uint32_t i;
 341
 342         if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_clock_by_type) {
 343                 if (adev->powerplay.pp_funcs->get_clock_by_type(pp_handle,
 344                         dc_to_pp_clock_type(clk_type), &pp_clks)) {
 345                 /* Error in pplib. Provide default values. */
 346                         return true;
 347                 }
 348         } else if (adev->smu.ppt_funcs && adev->smu.ppt_funcs->get_clock_by_type) {
 349                 if (smu_get_clock_by_type(&adev->smu,
 350                                           dc_to_pp_clock_type(clk_type),
 351                                           &pp_clks)) {
 352                         get_default_clock_levels(clk_type, dc_clks);
 353                         return true;
 354                 }
 355         }
 356
 357         pp_to_dc_clock_levels(&pp_clks, dc_clks, clk_type);
 358
 359         if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_display_mode_validation_clocks) {
 360                 if (adev->powerplay.pp_funcs->get_display_mode_validation_clocks(
 361                                                 pp_handle, &validation_clks)) {
 362                         /* Error in pplib. Provide default values. */
 363                         DRM_INFO("DM_PPLIB: Warning: using default validation clocks!\n");
 364                         validation_clks.engine_max_clock = 72000;
 365                         validation_clks.memory_max_clock = 80000;
 366                         validation_clks.level = 0;
 367                 }
 368         } else if (adev->smu.ppt_funcs && adev->smu.ppt_funcs->get_max_high_clocks) {
 369                 if (smu_get_max_high_clocks(&adev->smu, &validation_clks)) {
 370                         DRM_INFO("DM_PPLIB: Warning: using default validation clocks!\n");
 371                         validation_clks.engine_max_clock = 72000;
 372                         validation_clks.memory_max_clock = 80000;
 373                         validation_clks.level = 0;
 374                 }
 375         }
 376
 377         DRM_INFO("DM_PPLIB: Validation clocks:\n");
 378         DRM_INFO("DM_PPLIB:    engine_max_clock: %d\n",
 379                         validation_clks.engine_max_clock);
 380         DRM_INFO("DM_PPLIB:    memory_max_clock: %d\n",
 381                         validation_clks.memory_max_clock);
 382         DRM_INFO("DM_PPLIB:    level           : %d\n",
 383                         validation_clks.level);
 384
 385         /* Translate 10 kHz to kHz. */
 386         validation_clks.engine_max_clock *= 10;
 387         validation_clks.memory_max_clock *= 10;
 388
 389         /* Determine the highest non-boosted level from the Validation Clocks */
 390         if (clk_type == DM_PP_CLOCK_TYPE_ENGINE_CLK) {
 391                 for (i = 0; i < dc_clks->num_levels; i++) {
 392                         if (dc_clks->clocks_in_khz[i] > validation_clks.engine_max_clock) {
 393                                 /* This clock is higher the validation clock.
 394                                  * Than means the previous one is the highest
 395                                  * non-boosted one. */
 396                                 DRM_INFO("DM_PPLIB: reducing engine clock level from %d to %d\n",
 397                                                 dc_clks->num_levels, i);
 398                                 dc_clks->num_levels = i > 0 ? i : 1;
 399                                 break;
 400                         }
 401                 }
 402         } else if (clk_type == DM_PP_CLOCK_TYPE_MEMORY_CLK) {
 403                 for (i = 0; i < dc_clks->num_levels; i++) {
 404                         if (dc_clks->clocks_in_khz[i] > validation_clks.memory_max_clock) {
 405                                 DRM_INFO("DM_PPLIB: reducing memory clock level from %d to %d\n",
 406                                                 dc_clks->num_levels, i);
 407                                 dc_clks->num_levels = i > 0 ? i : 1;
 408                                 break;
 409                         }
 410                 }
 411         }
 412
 413         return true;
 414 }
 415
 416 bool dm_pp_get_clock_levels_by_type_with_latency(
 417         const struct dc_context *ctx,
 418         enum dm_pp_clock_type clk_type,
 419         struct dm_pp_clock_levels_with_latency *clk_level_info)
 420 {
 421         struct amdgpu_device *adev = ctx->driver_context;
 422         void *pp_handle = adev->powerplay.pp_handle;
 423         struct pp_clock_levels_with_latency pp_clks = { 0 };
 424         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
 425         int ret;
 426
 427         if (pp_funcs && pp_funcs->get_clock_by_type_with_latency) {
 428                 ret = pp_funcs->get_clock_by_type_with_latency(pp_handle,
 429                                                 dc_to_pp_clock_type(clk_type),
 430                                                 &pp_clks);
 431                 if (ret)
 432                         return false;
 433         } else if (adev->smu.ppt_funcs && adev->smu.ppt_funcs->get_clock_by_type_with_latency) {
 434                 if (smu_get_clock_by_type_with_latency(&adev->smu,
 435                                                        dc_to_smu_clock_type(clk_type),
 436                                                        &pp_clks))
 437                         return false;
 438         }
 439
 440
 441         pp_to_dc_clock_levels_with_latency(&pp_clks, clk_level_info, clk_type);
 442
 443         return true;
 444 }
 445
 446 bool dm_pp_get_clock_levels_by_type_with_voltage(
 447         const struct dc_context *ctx,
 448         enum dm_pp_clock_type clk_type,
 449         struct dm_pp_clock_levels_with_voltage *clk_level_info)
 450 {
 451         struct amdgpu_device *adev = ctx->driver_context;
 452         void *pp_handle = adev->powerplay.pp_handle;
 453         struct pp_clock_levels_with_voltage pp_clk_info = {0};
 454         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
 455         int ret;
 456
 457         if (pp_funcs && pp_funcs->get_clock_by_type_with_voltage) {
 458                 ret = pp_funcs->get_clock_by_type_with_voltage(pp_handle,
 459                                                 dc_to_pp_clock_type(clk_type),
 460                                                 &pp_clk_info);
 461                 if (ret)
 462                         return false;
 463         } else if (adev->smu.ppt_funcs && adev->smu.ppt_funcs->get_clock_by_type_with_voltage) {
 464                 if (smu_get_clock_by_type_with_voltage(&adev->smu,
 465                                                        dc_to_pp_clock_type(clk_type),
 466                                                        &pp_clk_info))
 467                         return false;
 468         }
 469
 470         pp_to_dc_clock_levels_with_voltage(&pp_clk_info, clk_level_info, clk_type);
 471
 472         return true;
 473 }
 474
 475 bool dm_pp_notify_wm_clock_changes(
 476         const struct dc_context *ctx,
 477         struct dm_pp_wm_sets_with_clock_ranges *wm_with_clock_ranges)
 478 {
 479         /* TODO: to be implemented */
 480         return false;
 481 }
 482
 483 bool dm_pp_apply_power_level_change_request(
 484         const struct dc_context *ctx,
 485         struct dm_pp_power_level_change_request *level_change_req)
 486 {
 487         /* TODO: to be implemented */
 488         return false;
 489 }
 490
 491 bool dm_pp_apply_clock_for_voltage_request(
 492         const struct dc_context *ctx,
 493         struct dm_pp_clock_for_voltage_req *clock_for_voltage_req)
 494 {
 495         struct amdgpu_device *adev = ctx->driver_context;
 496         struct pp_display_clock_request pp_clock_request = {0};
 497         int ret = 0;
 498
 499         pp_clock_request.clock_type = dc_to_pp_clock_type(clock_for_voltage_req->clk_type);
 500         pp_clock_request.clock_freq_in_khz = clock_for_voltage_req->clocks_in_khz;
 501
 502         if (!pp_clock_request.clock_type)
 503                 return false;
 504
 505         if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->display_clock_voltage_request)
 506                 ret = adev->powerplay.pp_funcs->display_clock_voltage_request(
 507                         adev->powerplay.pp_handle,
 508                         &pp_clock_request);
 509         else if (adev->smu.ppt_funcs &&
 510                  adev->smu.ppt_funcs->display_clock_voltage_request)
 511                 ret = smu_display_clock_voltage_request(&adev->smu,
 512                                                         &pp_clock_request);
 513         if (ret)
 514                 return false;
 515         return true;
 516 }
 517
 518 bool dm_pp_get_static_clocks(
 519         const struct dc_context *ctx,
 520         struct dm_pp_static_clock_info *static_clk_info)
 521 {
 522         struct amdgpu_device *adev = ctx->driver_context;
 523         struct amd_pp_clock_info pp_clk_info = {0};
 524         int ret = 0;
 525
 526         if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_current_clocks)
 527                 ret = adev->powerplay.pp_funcs->get_current_clocks(
 528                         adev->powerplay.pp_handle,
 529                         &pp_clk_info);
 530         else if (adev->smu.ppt_funcs)
 531                 ret = smu_get_current_clocks(&adev->smu, &pp_clk_info);
 532         if (ret)
 533                 return false;
 534
 535         static_clk_info->max_clocks_state = pp_to_dc_powerlevel_state(pp_clk_info.max_clocks_state);
 536         static_clk_info->max_mclk_khz = pp_clk_info.max_memory_clock * 10;
 537         static_clk_info->max_sclk_khz = pp_clk_info.max_engine_clock * 10;
 538
 539         return true;
 540 }
 541
 542 void pp_rv_set_wm_ranges(struct pp_smu *pp,
 543                 struct pp_smu_wm_range_sets *ranges)
 544 {
 545         const struct dc_context *ctx = pp->dm;
 546         struct amdgpu_device *adev = ctx->driver_context;
 547         void *pp_handle = adev->powerplay.pp_handle;
 548         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
 549         struct dm_pp_wm_sets_with_clock_ranges_soc15 wm_with_clock_ranges;
 550         struct dm_pp_clock_range_for_dmif_wm_set_soc15 *wm_dce_clocks = wm_with_clock_ranges.wm_dmif_clocks_ranges;
 551         struct dm_pp_clock_range_for_mcif_wm_set_soc15 *wm_soc_clocks = wm_with_clock_ranges.wm_mcif_clocks_ranges;
 552         int32_t i;
 553
 554         wm_with_clock_ranges.num_wm_dmif_sets = ranges->num_reader_wm_sets;
 555         wm_with_clock_ranges.num_wm_mcif_sets = ranges->num_writer_wm_sets;
 556
 557         for (i = 0; i < wm_with_clock_ranges.num_wm_dmif_sets; i++) {
 558                 if (ranges->reader_wm_sets[i].wm_inst > 3)
 559                         wm_dce_clocks[i].wm_set_id = WM_SET_A;
 560                 else
 561                         wm_dce_clocks[i].wm_set_id =
 562                                         ranges->reader_wm_sets[i].wm_inst;
 563                 wm_dce_clocks[i].wm_max_dcfclk_clk_in_khz =
 564                                 ranges->reader_wm_sets[i].max_drain_clk_mhz * 1000;
 565                 wm_dce_clocks[i].wm_min_dcfclk_clk_in_khz =
 566                                 ranges->reader_wm_sets[i].min_drain_clk_mhz * 1000;
 567                 wm_dce_clocks[i].wm_max_mem_clk_in_khz =
 568                                 ranges->reader_wm_sets[i].max_fill_clk_mhz * 1000;
 569                 wm_dce_clocks[i].wm_min_mem_clk_in_khz =
 570                                 ranges->reader_wm_sets[i].min_fill_clk_mhz * 1000;
 571         }
 572
 573         for (i = 0; i < wm_with_clock_ranges.num_wm_mcif_sets; i++) {
 574                 if (ranges->writer_wm_sets[i].wm_inst > 3)
 575                         wm_soc_clocks[i].wm_set_id = WM_SET_A;
 576                 else
 577                         wm_soc_clocks[i].wm_set_id =
 578                                         ranges->writer_wm_sets[i].wm_inst;
 579                 wm_soc_clocks[i].wm_max_socclk_clk_in_khz =
 580                                 ranges->writer_wm_sets[i].max_fill_clk_mhz * 1000;
 581                 wm_soc_clocks[i].wm_min_socclk_clk_in_khz =
 582                                 ranges->writer_wm_sets[i].min_fill_clk_mhz * 1000;
 583                 wm_soc_clocks[i].wm_max_mem_clk_in_khz =
 584                                 ranges->writer_wm_sets[i].max_drain_clk_mhz * 1000;
 585                 wm_soc_clocks[i].wm_min_mem_clk_in_khz =
 586                                 ranges->writer_wm_sets[i].min_drain_clk_mhz * 1000;
 587         }
 588
 589         if (pp_funcs && pp_funcs->set_watermarks_for_clocks_ranges)
 590                 pp_funcs->set_watermarks_for_clocks_ranges(pp_handle,
 591                                                            &wm_with_clock_ranges);
 592         else
 593                 smu_set_watermarks_for_clock_ranges(&adev->smu,
 594                                 &wm_with_clock_ranges);
 595 }
 596
 597 void pp_rv_set_pme_wa_enable(struct pp_smu *pp)
 598 {
 599         const struct dc_context *ctx = pp->dm;
 600         struct amdgpu_device *adev = ctx->driver_context;
 601         void *pp_handle = adev->powerplay.pp_handle;
 602         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
 603
 604         if (pp_funcs && pp_funcs->notify_smu_enable_pwe)
 605                 pp_funcs->notify_smu_enable_pwe(pp_handle);
 606         else if (adev->smu.ppt_funcs)
 607                 smu_notify_smu_enable_pwe(&adev->smu);
 608 }
 609
 610 void pp_rv_set_active_display_count(struct pp_smu *pp, int count)
 611 {
 612         const struct dc_context *ctx = pp->dm;
 613         struct amdgpu_device *adev = ctx->driver_context;
 614         void *pp_handle = adev->powerplay.pp_handle;
 615         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
 616
 617         if (!pp_funcs || !pp_funcs->set_active_display_count)
 618                 return;
 619
 620         pp_funcs->set_active_display_count(pp_handle, count);
 621 }
 622
 623 void pp_rv_set_min_deep_sleep_dcfclk(struct pp_smu *pp, int clock)
 624 {
 625         const struct dc_context *ctx = pp->dm;
 626         struct amdgpu_device *adev = ctx->driver_context;
 627         void *pp_handle = adev->powerplay.pp_handle;
 628         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
 629
 630         if (!pp_funcs || !pp_funcs->set_min_deep_sleep_dcefclk)
 631                 return;
 632
 633         pp_funcs->set_min_deep_sleep_dcefclk(pp_handle, clock);
 634 }
 635
 636 void pp_rv_set_hard_min_dcefclk_by_freq(struct pp_smu *pp, int clock)
 637 {
 638         const struct dc_context *ctx = pp->dm;
 639         struct amdgpu_device *adev = ctx->driver_context;
 640         void *pp_handle = adev->powerplay.pp_handle;
 641         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
 642
 643         if (!pp_funcs || !pp_funcs->set_hard_min_dcefclk_by_freq)
 644                 return;
 645
 646         pp_funcs->set_hard_min_dcefclk_by_freq(pp_handle, clock);
 647 }
 648
 649 void pp_rv_set_hard_min_fclk_by_freq(struct pp_smu *pp, int mhz)
 650 {
 651         const struct dc_context *ctx = pp->dm;
 652         struct amdgpu_device *adev = ctx->driver_context;
 653         void *pp_handle = adev->powerplay.pp_handle;
 654         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
 655
 656         if (!pp_funcs || !pp_funcs->set_hard_min_fclk_by_freq)
 657                 return;
 658
 659         pp_funcs->set_hard_min_fclk_by_freq(pp_handle, mhz);
 660 }
 661
 662 enum pp_smu_status pp_nv_set_wm_ranges(struct pp_smu *pp,
 663                 struct pp_smu_wm_range_sets *ranges)
 664 {
 665         const struct dc_context *ctx = pp->dm;
 666         struct amdgpu_device *adev = ctx->driver_context;
 667         struct dm_pp_wm_sets_with_clock_ranges_soc15 wm_with_clock_ranges;
 668         struct dm_pp_clock_range_for_dmif_wm_set_soc15 *wm_dce_clocks =
 669                         wm_with_clock_ranges.wm_dmif_clocks_ranges;
 670         struct dm_pp_clock_range_for_mcif_wm_set_soc15 *wm_soc_clocks =
 671                         wm_with_clock_ranges.wm_mcif_clocks_ranges;
 672         int32_t i;
 673
 674         wm_with_clock_ranges.num_wm_dmif_sets = ranges->num_reader_wm_sets;
 675         wm_with_clock_ranges.num_wm_mcif_sets = ranges->num_writer_wm_sets;
 676
 677         for (i = 0; i < wm_with_clock_ranges.num_wm_dmif_sets; i++) {
 678                 if (ranges->reader_wm_sets[i].wm_inst > 3)
 679                         wm_dce_clocks[i].wm_set_id = WM_SET_A;
 680                 else
 681                         wm_dce_clocks[i].wm_set_id =
 682                                         ranges->reader_wm_sets[i].wm_inst;
 683                 wm_dce_clocks[i].wm_max_dcfclk_clk_in_khz =
 684                         ranges->reader_wm_sets[i].max_drain_clk_mhz * 1000;
 685                 wm_dce_clocks[i].wm_min_dcfclk_clk_in_khz =
 686                         ranges->reader_wm_sets[i].min_drain_clk_mhz * 1000;
 687                 wm_dce_clocks[i].wm_max_mem_clk_in_khz =
 688                         ranges->reader_wm_sets[i].max_fill_clk_mhz * 1000;
 689                 wm_dce_clocks[i].wm_min_mem_clk_in_khz =
 690                         ranges->reader_wm_sets[i].min_fill_clk_mhz * 1000;
 691         }
 692
 693         for (i = 0; i < wm_with_clock_ranges.num_wm_mcif_sets; i++) {
 694                 if (ranges->writer_wm_sets[i].wm_inst > 3)
 695                         wm_soc_clocks[i].wm_set_id = WM_SET_A;
 696                 else
 697                         wm_soc_clocks[i].wm_set_id =
 698                                         ranges->writer_wm_sets[i].wm_inst;
 699                 wm_soc_clocks[i].wm_max_socclk_clk_in_khz =
 700                         ranges->writer_wm_sets[i].max_fill_clk_mhz * 1000;
 701                 wm_soc_clocks[i].wm_min_socclk_clk_in_khz =
 702                         ranges->writer_wm_sets[i].min_fill_clk_mhz * 1000;
 703                 wm_soc_clocks[i].wm_max_mem_clk_in_khz =
 704                         ranges->writer_wm_sets[i].max_drain_clk_mhz * 1000;
 705                 wm_soc_clocks[i].wm_min_mem_clk_in_khz =
 706                         ranges->writer_wm_sets[i].min_drain_clk_mhz * 1000;
 707         }
 708
 709         smu_set_watermarks_for_clock_ranges(&adev->smu, &wm_with_clock_ranges);
 710
 711         return PP_SMU_RESULT_OK;
 712 }
 713
 714 enum pp_smu_status pp_nv_set_pme_wa_enable(struct pp_smu *pp)
 715 {
 716         const struct dc_context *ctx = pp->dm;
 717         struct amdgpu_device *adev = ctx->driver_context;
 718         struct smu_context *smu = &adev->smu;
 719
 720         if (!smu->ppt_funcs)
 721                 return PP_SMU_RESULT_UNSUPPORTED;
 722
 723         /* 0: successful or smu.ppt_funcs->set_azalia_d3_pme = NULL;  1: fail */
 724         if (smu_set_azalia_d3_pme(smu))
 725                 return PP_SMU_RESULT_FAIL;
 726
 727         return PP_SMU_RESULT_OK;
 728 }
 729
 730 enum pp_smu_status pp_nv_set_display_count(struct pp_smu *pp, int count)
 731 {
 732         const struct dc_context *ctx = pp->dm;
 733         struct amdgpu_device *adev = ctx->driver_context;
 734         struct smu_context *smu = &adev->smu;
 735
 736         if (!smu->ppt_funcs)
 737                 return PP_SMU_RESULT_UNSUPPORTED;
 738
 739         /* 0: successful or smu.ppt_funcs->set_display_count = NULL;  1: fail */
 740         if (smu_set_display_count(smu, count))
 741                 return PP_SMU_RESULT_FAIL;
 742
 743         return PP_SMU_RESULT_OK;
 744 }
 745
 746 enum pp_smu_status pp_nv_set_min_deep_sleep_dcfclk(struct pp_smu *pp, int mhz)
 747 {
 748         const struct dc_context *ctx = pp->dm;
 749         struct amdgpu_device *adev = ctx->driver_context;
 750         struct smu_context *smu = &adev->smu;
 751
 752         if (!smu->ppt_funcs)
 753                 return PP_SMU_RESULT_UNSUPPORTED;
 754
 755         /* 0: successful or smu.ppt_funcs->set_deep_sleep_dcefclk = NULL;1: fail */
 756         if (smu_set_deep_sleep_dcefclk(smu, mhz))
 757                 return PP_SMU_RESULT_FAIL;
 758
 759         return PP_SMU_RESULT_OK;
 760 }
 761
 762 enum pp_smu_status pp_nv_set_hard_min_dcefclk_by_freq(
 763                 struct pp_smu *pp, int mhz)
 764 {
 765         const struct dc_context *ctx = pp->dm;
 766         struct amdgpu_device *adev = ctx->driver_context;
 767         struct smu_context *smu = &adev->smu;
 768         struct pp_display_clock_request clock_req;
 769
 770         if (!smu->ppt_funcs)
 771                 return PP_SMU_RESULT_UNSUPPORTED;
 772
 773         clock_req.clock_type = amd_pp_dcef_clock;
 774         clock_req.clock_freq_in_khz = mhz * 1000;
 775
 776         /* 0: successful or smu.ppt_funcs->display_clock_voltage_request = NULL
 777          * 1: fail
 778          */
 779         if (smu_display_clock_voltage_request(smu, &clock_req))
 780                 return PP_SMU_RESULT_FAIL;
 781
 782         return PP_SMU_RESULT_OK;
 783 }
 784
 785 enum pp_smu_status pp_nv_set_hard_min_uclk_by_freq(struct pp_smu *pp, int mhz)
 786 {
 787         const struct dc_context *ctx = pp->dm;
 788         struct amdgpu_device *adev = ctx->driver_context;
 789         struct smu_context *smu = &adev->smu;
 790         struct pp_display_clock_request clock_req;
 791
 792         if (!smu->ppt_funcs)
 793                 return PP_SMU_RESULT_UNSUPPORTED;
 794
 795         clock_req.clock_type = amd_pp_mem_clock;
 796         clock_req.clock_freq_in_khz = mhz * 1000;
 797
 798         /* 0: successful or smu.ppt_funcs->display_clock_voltage_request = NULL
 799          * 1: fail
 800          */
 801         if (smu_display_clock_voltage_request(smu, &clock_req))
 802                 return PP_SMU_RESULT_FAIL;
 803
 804         return PP_SMU_RESULT_OK;
 805 }
 806
 807 enum pp_smu_status pp_nv_set_pstate_handshake_support(
 808         struct pp_smu *pp, BOOLEAN pstate_handshake_supported)
 809 {
 810         const struct dc_context *ctx = pp->dm;
 811         struct amdgpu_device *adev = ctx->driver_context;
 812         struct smu_context *smu = &adev->smu;
 813
 814         if (smu_display_disable_memory_clock_switch(smu, !pstate_handshake_supported))
 815                 return PP_SMU_RESULT_FAIL;
 816
 817         return PP_SMU_RESULT_OK;
 818 }
 819
 820 enum pp_smu_status pp_nv_set_voltage_by_freq(struct pp_smu *pp,
 821                 enum pp_smu_nv_clock_id clock_id, int mhz)
 822 {
 823         const struct dc_context *ctx = pp->dm;
 824         struct amdgpu_device *adev = ctx->driver_context;
 825         struct smu_context *smu = &adev->smu;
 826         struct pp_display_clock_request clock_req;
 827
 828         if (!smu->ppt_funcs)
 829                 return PP_SMU_RESULT_UNSUPPORTED;
 830
 831         switch (clock_id) {
 832         case PP_SMU_NV_DISPCLK:
 833                 clock_req.clock_type = amd_pp_disp_clock;
 834                 break;
 835         case PP_SMU_NV_PHYCLK:
 836                 clock_req.clock_type = amd_pp_phy_clock;
 837                 break;
 838         case PP_SMU_NV_PIXELCLK:
 839                 clock_req.clock_type = amd_pp_pixel_clock;
 840                 break;
 841         default:
 842                 break;
 843         }
 844         clock_req.clock_freq_in_khz = mhz * 1000;
 845
 846         /* 0: successful or smu.ppt_funcs->display_clock_voltage_request = NULL
 847          * 1: fail
 848          */
 849         if (smu_display_clock_voltage_request(smu, &clock_req))
 850                 return PP_SMU_RESULT_FAIL;
 851
 852         return PP_SMU_RESULT_OK;
 853 }
 854
 855 enum pp_smu_status pp_nv_get_maximum_sustainable_clocks(
 856                 struct pp_smu *pp, struct pp_smu_nv_clock_table *max_clocks)
 857 {
 858         const struct dc_context *ctx = pp->dm;
 859         struct amdgpu_device *adev = ctx->driver_context;
 860         struct smu_context *smu = &adev->smu;
 861
 862         if (!smu->ppt_funcs)
 863                 return PP_SMU_RESULT_UNSUPPORTED;
 864
 865         if (!smu->ppt_funcs->get_max_sustainable_clocks_by_dc)
 866                 return PP_SMU_RESULT_UNSUPPORTED;
 867
 868         if (!smu_get_max_sustainable_clocks_by_dc(smu, max_clocks))
 869                 return PP_SMU_RESULT_OK;
 870
 871         return PP_SMU_RESULT_FAIL;
 872 }
 873
 874 enum pp_smu_status pp_nv_get_uclk_dpm_states(struct pp_smu *pp,
 875                 unsigned int *clock_values_in_khz, unsigned int *num_states)
 876 {
 877         const struct dc_context *ctx = pp->dm;
 878         struct amdgpu_device *adev = ctx->driver_context;
 879         struct smu_context *smu = &adev->smu;
 880
 881         if (!smu->ppt_funcs)
 882                 return PP_SMU_RESULT_UNSUPPORTED;
 883
 884         if (!smu->ppt_funcs->get_uclk_dpm_states)
 885                 return PP_SMU_RESULT_UNSUPPORTED;
 886
 887         if (!smu_get_uclk_dpm_states(smu,
 888                         clock_values_in_khz, num_states))
 889                 return PP_SMU_RESULT_OK;
 890
 891         return PP_SMU_RESULT_FAIL;
 892 }
 893
 894 #ifdef CONFIG_DRM_AMD_DC_DCN2_1
 895 enum pp_smu_status pp_rn_get_dpm_clock_table(
 896                 struct pp_smu *pp, struct dpm_clocks *clock_table)
 897 {
 898         const struct dc_context *ctx = pp->dm;
 899         struct amdgpu_device *adev = ctx->driver_context;
 900         struct smu_context *smu = &adev->smu;
 901
 902         if (!smu->ppt_funcs)
 903                 return PP_SMU_RESULT_UNSUPPORTED;
 904
 905         if (!smu->ppt_funcs->get_dpm_clock_table)
 906                 return PP_SMU_RESULT_UNSUPPORTED;
 907
 908         if (!smu_get_dpm_clock_table(smu, clock_table))
 909                 return PP_SMU_RESULT_OK;
 910
 911         return PP_SMU_RESULT_FAIL;
 912 }
 913
 914 enum pp_smu_status pp_rn_set_wm_ranges(struct pp_smu *pp,
 915                 struct pp_smu_wm_range_sets *ranges)
 916 {
 917         const struct dc_context *ctx = pp->dm;
 918         struct amdgpu_device *adev = ctx->driver_context;
 919         struct smu_context *smu = &adev->smu;
 920         struct dm_pp_wm_sets_with_clock_ranges_soc15 wm_with_clock_ranges;
 921         struct dm_pp_clock_range_for_dmif_wm_set_soc15 *wm_dce_clocks =
 922                         wm_with_clock_ranges.wm_dmif_clocks_ranges;
 923         struct dm_pp_clock_range_for_mcif_wm_set_soc15 *wm_soc_clocks =
 924                         wm_with_clock_ranges.wm_mcif_clocks_ranges;
 925         int32_t i;
 926
 927         if (!smu->ppt_funcs)
 928                 return PP_SMU_RESULT_UNSUPPORTED;
 929
 930         wm_with_clock_ranges.num_wm_dmif_sets = ranges->num_reader_wm_sets;
 931         wm_with_clock_ranges.num_wm_mcif_sets = ranges->num_writer_wm_sets;
 932
 933         for (i = 0; i < wm_with_clock_ranges.num_wm_dmif_sets; i++) {
 934                 if (ranges->reader_wm_sets[i].wm_inst > 3)
 935                         wm_dce_clocks[i].wm_set_id = WM_SET_A;
 936                 else
 937                         wm_dce_clocks[i].wm_set_id =
 938                                         ranges->reader_wm_sets[i].wm_inst;
 939
 940                 wm_dce_clocks[i].wm_min_dcfclk_clk_in_khz =
 941                         ranges->reader_wm_sets[i].min_drain_clk_mhz;
 942
 943                 wm_dce_clocks[i].wm_max_dcfclk_clk_in_khz =
 944                         ranges->reader_wm_sets[i].max_drain_clk_mhz;
 945
 946                 wm_dce_clocks[i].wm_min_mem_clk_in_khz =
 947                         ranges->reader_wm_sets[i].min_fill_clk_mhz;
 948
 949                 wm_dce_clocks[i].wm_max_mem_clk_in_khz =
 950                         ranges->reader_wm_sets[i].max_fill_clk_mhz;
 951         }
 952
 953         for (i = 0; i < wm_with_clock_ranges.num_wm_mcif_sets; i++) {
 954                 if (ranges->writer_wm_sets[i].wm_inst > 3)
 955                         wm_soc_clocks[i].wm_set_id = WM_SET_A;
 956                 else
 957                         wm_soc_clocks[i].wm_set_id =
 958                                         ranges->writer_wm_sets[i].wm_inst;
 959                 wm_soc_clocks[i].wm_min_socclk_clk_in_khz =
 960                                 ranges->writer_wm_sets[i].min_fill_clk_mhz;
 961
 962                 wm_soc_clocks[i].wm_max_socclk_clk_in_khz =
 963                         ranges->writer_wm_sets[i].max_fill_clk_mhz;
 964
 965                 wm_soc_clocks[i].wm_min_mem_clk_in_khz =
 966                         ranges->writer_wm_sets[i].min_drain_clk_mhz;
 967
 968                 wm_soc_clocks[i].wm_max_mem_clk_in_khz =
 969                         ranges->writer_wm_sets[i].max_drain_clk_mhz;
 970         }
 971
 972         smu_set_watermarks_for_clock_ranges(&adev->smu, &wm_with_clock_ranges);
 973
 974         return PP_SMU_RESULT_OK;
 975 }
 976 #endif
 977
 978 void dm_pp_get_funcs(
 979                 struct dc_context *ctx,
 980                 struct pp_smu_funcs *funcs)
 981 {
 982         switch (ctx->dce_version) {
 983         case DCN_VERSION_1_0:
 984         case DCN_VERSION_1_01:
 985                 funcs->ctx.ver = PP_SMU_VER_RV;
 986                 funcs->rv_funcs.pp_smu.dm = ctx;
 987                 funcs->rv_funcs.set_wm_ranges = pp_rv_set_wm_ranges;
 988                 funcs->rv_funcs.set_pme_wa_enable = pp_rv_set_pme_wa_enable;
 989                 funcs->rv_funcs.set_display_count =
 990                                 pp_rv_set_active_display_count;
 991                 funcs->rv_funcs.set_min_deep_sleep_dcfclk =
 992                                 pp_rv_set_min_deep_sleep_dcfclk;
 993                 funcs->rv_funcs.set_hard_min_dcfclk_by_freq =
 994                                 pp_rv_set_hard_min_dcefclk_by_freq;
 995                 funcs->rv_funcs.set_hard_min_fclk_by_freq =
 996                                 pp_rv_set_hard_min_fclk_by_freq;
 997                 break;
 998 #ifdef CONFIG_DRM_AMD_DC_DCN2_0
 999         case DCN_VERSION_2_0:
1000                 funcs->ctx.ver = PP_SMU_VER_NV;
1001                 funcs->nv_funcs.pp_smu.dm = ctx;
1002                 funcs->nv_funcs.set_display_count = pp_nv_set_display_count;
1003                 funcs->nv_funcs.set_hard_min_dcfclk_by_freq =
1004                                 pp_nv_set_hard_min_dcefclk_by_freq;
1005                 funcs->nv_funcs.set_min_deep_sleep_dcfclk =
1006                                 pp_nv_set_min_deep_sleep_dcfclk;
1007                 funcs->nv_funcs.set_voltage_by_freq =
1008                                 pp_nv_set_voltage_by_freq;
1009                 funcs->nv_funcs.set_wm_ranges = pp_nv_set_wm_ranges;
1010
1011                 /* todo set_pme_wa_enable cause 4k@6ohz display not light up */
1012                 funcs->nv_funcs.set_pme_wa_enable = NULL;
1013                 /* todo debug waring message */
1014                 funcs->nv_funcs.set_hard_min_uclk_by_freq = pp_nv_set_hard_min_uclk_by_freq;
1015                 /* todo  compare data with window driver*/
1016                 funcs->nv_funcs.get_maximum_sustainable_clocks = pp_nv_get_maximum_sustainable_clocks;
1017                 /*todo  compare data with window driver */
1018                 funcs->nv_funcs.get_uclk_dpm_states = pp_nv_get_uclk_dpm_states;
1019                 funcs->nv_funcs.set_pstate_handshake_support = pp_nv_set_pstate_handshake_support;
1020                 break;
1021 #endif
1022
1023 #ifdef CONFIG_DRM_AMD_DC_DCN2_1
1024         case DCN_VERSION_2_1:
1025                 funcs->ctx.ver = PP_SMU_VER_RN;
1026                 funcs->rn_funcs.pp_smu.dm = ctx;
1027                 funcs->rn_funcs.set_wm_ranges = pp_rn_set_wm_ranges;
1028                 funcs->rn_funcs.get_dpm_clock_table = pp_rn_get_dpm_clock_table;
1029                 break;
1030 #endif
1031         default:
1032                 DRM_ERROR("smu version is not supported !\n");
1033                 break;
1034         }
1035 }