drivers/gpu/drm/amd/display/dc/core/dc.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  */
  24
  25 #include <linux/slab.h>
  26 #include <linux/mm.h>
  27
  28 #include "dm_services.h"
  29
  30 #include "dc.h"
  31
  32 #include "core_status.h"
  33 #include "core_types.h"
  34 #include "hw_sequencer.h"
  35 #include "dce/dce_hwseq.h"
  36
  37 #include "resource.h"
  38
  39 #include "clk_mgr.h"
  40 #include "clock_source.h"
  41 #include "dc_bios_types.h"
  42
  43 #include "bios_parser_interface.h"
  44 #include "include/irq_service_interface.h"
  45 #include "transform.h"
  46 #include "dmcu.h"
  47 #include "dpp.h"
  48 #include "timing_generator.h"
  49 #include "abm.h"
  50 #include "virtual/virtual_link_encoder.h"
  51
  52 #include "link_hwss.h"
  53 #include "link_encoder.h"
  54
  55 #include "dc_link_ddc.h"
  56 #include "dm_helpers.h"
  57 #include "mem_input.h"
  58 #include "hubp.h"
  59
  60 #include "dc_link_dp.h"
  61 #include "dc_dmub_srv.h"
  62
  63 #include "dsc.h"
  64
  65 #include "vm_helper.h"
  66
  67 #include "dce/dce_i2c.h"
  68
  69 #define CTX \
  70         dc->ctx
  71
  72 #define DC_LOGGER \
  73         dc->ctx->logger
  74
  75 static const char DC_BUILD_ID[] = "production-build";
  76
  77 /**
  78  * DOC: Overview
  79  *
  80  * DC is the OS-agnostic component of the amdgpu DC driver.
  81  *
  82  * DC maintains and validates a set of structs representing the state of the
  83  * driver and writes that state to AMD hardware
  84  *
  85  * Main DC HW structs:
  86  *
  87  * struct dc - The central struct.  One per driver.  Created on driver load,
  88  * destroyed on driver unload.
  89  *
  90  * struct dc_context - One per driver.
  91  * Used as a backpointer by most other structs in dc.
  92  *
  93  * struct dc_link - One per connector (the physical DP, HDMI, miniDP, or eDP
  94  * plugpoints).  Created on driver load, destroyed on driver unload.
  95  *
  96  * struct dc_sink - One per display.  Created on boot or hotplug.
  97  * Destroyed on shutdown or hotunplug.  A dc_link can have a local sink
  98  * (the display directly attached).  It may also have one or more remote
  99  * sinks (in the Multi-Stream Transport case)
 100  *
 101  * struct resource_pool - One per driver.  Represents the hw blocks not in the
 102  * main pipeline.  Not directly accessible by dm.
 103  *
 104  * Main dc state structs:
 105  *
 106  * These structs can be created and destroyed as needed.  There is a full set of
 107  * these structs in dc->current_state representing the currently programmed state.
 108  *
 109  * struct dc_state - The global DC state to track global state information,
 110  * such as bandwidth values.
 111  *
 112  * struct dc_stream_state - Represents the hw configuration for the pipeline from
 113  * a framebuffer to a display.  Maps one-to-one with dc_sink.
 114  *
 115  * struct dc_plane_state - Represents a framebuffer.  Each stream has at least one,
 116  * and may have more in the Multi-Plane Overlay case.
 117  *
 118  * struct resource_context - Represents the programmable state of everything in
 119  * the resource_pool.  Not directly accessible by dm.
 120  *
 121  * struct pipe_ctx - A member of struct resource_context.  Represents the
 122  * internal hardware pipeline components.  Each dc_plane_state has either
 123  * one or two (in the pipe-split case).
 124  */
 125
 126 /*******************************************************************************
 127  * Private functions
 128  ******************************************************************************/
 129
 130 static inline void elevate_update_type(enum surface_update_type *original, enum surface_update_type new)
 131 {
 132         if (new > *original)
 133                 *original = new;
 134 }
 135
 136 static void destroy_links(struct dc *dc)
 137 {
 138         uint32_t i;
 139
 140         for (i = 0; i < dc->link_count; i++) {
 141                 if (NULL != dc->links[i])
 142                         link_destroy(&dc->links[i]);
 143         }
 144 }
 145
 146 static bool create_links(
 147                 struct dc *dc,
 148                 uint32_t num_virtual_links)
 149 {
 150         int i;
 151         int connectors_num;
 152         struct dc_bios *bios = dc->ctx->dc_bios;
 153
 154         dc->link_count = 0;
 155
 156         connectors_num = bios->funcs->get_connectors_number(bios);
 157
 158         if (connectors_num > ENUM_ID_COUNT) {
 159                 dm_error(
 160                         "DC: Number of connectors %d exceeds maximum of %d!\n",
 161                         connectors_num,
 162                         ENUM_ID_COUNT);
 163                 return false;
 164         }
 165
 166         dm_output_to_console(
 167                 "DC: %s: connectors_num: physical:%d, virtual:%d\n",
 168                 __func__,
 169                 connectors_num,
 170                 num_virtual_links);
 171
 172         for (i = 0; i < connectors_num; i++) {
 173                 struct link_init_data link_init_params = {0};
 174                 struct dc_link *link;
 175
 176                 link_init_params.ctx = dc->ctx;
 177                 /* next BIOS object table connector */
 178                 link_init_params.connector_index = i;
 179                 link_init_params.link_index = dc->link_count;
 180                 link_init_params.dc = dc;
 181                 link = link_create(&link_init_params);
 182
 183                 if (link) {
 184                         bool should_destory_link = false;
 185
 186                         if (link->connector_signal == SIGNAL_TYPE_EDP) {
 187                                 if (dc->config.edp_not_connected)
 188                                         should_destory_link = true;
 189                                 else if (dc->debug.remove_disconnect_edp) {
 190                                         enum dc_connection_type type;
 191                                         dc_link_detect_sink(link, &type);
 192                                         if (type == dc_connection_none)
 193                                                 should_destory_link = true;
 194                                 }
 195                         }
 196
 197                         if (dc->config.force_enum_edp || !should_destory_link) {
 198                                 dc->links[dc->link_count] = link;
 199                                 link->dc = dc;
 200                                 ++dc->link_count;
 201                         } else {
 202                                 link_destroy(&link);
 203                         }
 204                 }
 205         }
 206
 207         for (i = 0; i < num_virtual_links; i++) {
 208                 struct dc_link *link = kzalloc(sizeof(*link), GFP_KERNEL);
 209                 struct encoder_init_data enc_init = {0};
 210
 211                 if (link == NULL) {
 212                         BREAK_TO_DEBUGGER();
 213                         goto failed_alloc;
 214                 }
 215
 216                 link->link_index = dc->link_count;
 217                 dc->links[dc->link_count] = link;
 218                 dc->link_count++;
 219
 220                 link->ctx = dc->ctx;
 221                 link->dc = dc;
 222                 link->connector_signal = SIGNAL_TYPE_VIRTUAL;
 223                 link->link_id.type = OBJECT_TYPE_CONNECTOR;
 224                 link->link_id.id = CONNECTOR_ID_VIRTUAL;
 225                 link->link_id.enum_id = ENUM_ID_1;
 226                 link->link_enc = kzalloc(sizeof(*link->link_enc), GFP_KERNEL);
 227
 228                 if (!link->link_enc) {
 229                         BREAK_TO_DEBUGGER();
 230                         goto failed_alloc;
 231                 }
 232
 233                 link->link_status.dpcd_caps = &link->dpcd_caps;
 234
 235                 enc_init.ctx = dc->ctx;
 236                 enc_init.channel = CHANNEL_ID_UNKNOWN;
 237                 enc_init.hpd_source = HPD_SOURCEID_UNKNOWN;
 238                 enc_init.transmitter = TRANSMITTER_UNKNOWN;
 239                 enc_init.connector = link->link_id;
 240                 enc_init.encoder.type = OBJECT_TYPE_ENCODER;
 241                 enc_init.encoder.id = ENCODER_ID_INTERNAL_VIRTUAL;
 242                 enc_init.encoder.enum_id = ENUM_ID_1;
 243                 virtual_link_encoder_construct(link->link_enc, &enc_init);
 244         }
 245
 246         return true;
 247
 248 failed_alloc:
 249         return false;
 250 }
 251
 252 static struct dc_perf_trace *dc_perf_trace_create(void)
 253 {
 254         return kzalloc(sizeof(struct dc_perf_trace), GFP_KERNEL);
 255 }
 256
 257 static void dc_perf_trace_destroy(struct dc_perf_trace **perf_trace)
 258 {
 259         kfree(*perf_trace);
 260         *perf_trace = NULL;
 261 }
 262
 263 /**
 264  *****************************************************************************
 265  *  Function: dc_stream_adjust_vmin_vmax
 266  *
 267  *  @brief
 268  *     Looks up the pipe context of dc_stream_state and updates the
 269  *     vertical_total_min and vertical_total_max of the DRR, Dynamic Refresh
 270  *     Rate, which is a power-saving feature that targets reducing panel
 271  *     refresh rate while the screen is static
 272  *
 273  *  @param [in] dc: dc reference
 274  *  @param [in] stream: Initial dc stream state
 275  *  @param [in] adjust: Updated parameters for vertical_total_min and
 276  *  vertical_total_max
 277  *****************************************************************************
 278  */
 279 bool dc_stream_adjust_vmin_vmax(struct dc *dc,
 280                 struct dc_stream_state *stream,
 281                 struct dc_crtc_timing_adjust *adjust)
 282 {
 283         int i = 0;
 284         bool ret = false;
 285
 286         for (i = 0; i < MAX_PIPES; i++) {
 287                 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 288
 289                 if (pipe->stream == stream && pipe->stream_res.tg) {
 290                         dc->hwss.set_drr(&pipe,
 291                                         1,
 292                                         adjust->v_total_min,
 293                                         adjust->v_total_max,
 294                                         adjust->v_total_mid,
 295                                         adjust->v_total_mid_frame_num);
 296
 297                         ret = true;
 298                 }
 299         }
 300         return ret;
 301 }
 302
 303 bool dc_stream_get_crtc_position(struct dc *dc,
 304                 struct dc_stream_state **streams, int num_streams,
 305                 unsigned int *v_pos, unsigned int *nom_v_pos)
 306 {
 307         /* TODO: Support multiple streams */
 308         const struct dc_stream_state *stream = streams[0];
 309         int i = 0;
 310         bool ret = false;
 311         struct crtc_position position;
 312
 313         for (i = 0; i < MAX_PIPES; i++) {
 314                 struct pipe_ctx *pipe =
 315                                 &dc->current_state->res_ctx.pipe_ctx[i];
 316
 317                 if (pipe->stream == stream && pipe->stream_res.stream_enc) {
 318                         dc->hwss.get_position(&pipe, 1, &position);
 319
 320                         *v_pos = position.vertical_count;
 321                         *nom_v_pos = position.nominal_vcount;
 322                         ret = true;
 323                 }
 324         }
 325         return ret;
 326 }
 327
 328 /**
 329  * dc_stream_configure_crc() - Configure CRC capture for the given stream.
 330  * @dc: DC Object
 331  * @stream: The stream to configure CRC on.
 332  * @enable: Enable CRC if true, disable otherwise.
 333  * @continuous: Capture CRC on every frame if true. Otherwise, only capture
 334  *              once.
 335  *
 336  * By default, only CRC0 is configured, and the entire frame is used to
 337  * calculate the crc.
 338  */
 339 bool dc_stream_configure_crc(struct dc *dc, struct dc_stream_state *stream,
 340                              bool enable, bool continuous)
 341 {
 342         int i;
 343         struct pipe_ctx *pipe;
 344         struct crc_params param;
 345         struct timing_generator *tg;
 346
 347         for (i = 0; i < MAX_PIPES; i++) {
 348                 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 349                 if (pipe->stream == stream)
 350                         break;
 351         }
 352         /* Stream not found */
 353         if (i == MAX_PIPES)
 354                 return false;
 355
 356         /* Always capture the full frame */
 357         param.windowa_x_start = 0;
 358         param.windowa_y_start = 0;
 359         param.windowa_x_end = pipe->stream->timing.h_addressable;
 360         param.windowa_y_end = pipe->stream->timing.v_addressable;
 361         param.windowb_x_start = 0;
 362         param.windowb_y_start = 0;
 363         param.windowb_x_end = pipe->stream->timing.h_addressable;
 364         param.windowb_y_end = pipe->stream->timing.v_addressable;
 365
 366         /* Default to the union of both windows */
 367         param.selection = UNION_WINDOW_A_B;
 368         param.continuous_mode = continuous;
 369         param.enable = enable;
 370
 371         tg = pipe->stream_res.tg;
 372
 373         /* Only call if supported */
 374         if (tg->funcs->configure_crc)
 375                 return tg->funcs->configure_crc(tg, &param);
 376         DC_LOG_WARNING("CRC capture not supported.");
 377         return false;
 378 }
 379
 380 /**
 381  * dc_stream_get_crc() - Get CRC values for the given stream.
 382  * @dc: DC object
 383  * @stream: The DC stream state of the stream to get CRCs from.
 384  * @r_cr, g_y, b_cb: CRC values for the three channels are stored here.
 385  *
 386  * dc_stream_configure_crc needs to be called beforehand to enable CRCs.
 387  * Return false if stream is not found, or if CRCs are not enabled.
 388  */
 389 bool dc_stream_get_crc(struct dc *dc, struct dc_stream_state *stream,
 390                        uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb)
 391 {
 392         int i;
 393         struct pipe_ctx *pipe;
 394         struct timing_generator *tg;
 395
 396         for (i = 0; i < MAX_PIPES; i++) {
 397                 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 398                 if (pipe->stream == stream)
 399                         break;
 400         }
 401         /* Stream not found */
 402         if (i == MAX_PIPES)
 403                 return false;
 404
 405         tg = pipe->stream_res.tg;
 406
 407         if (tg->funcs->get_crc)
 408                 return tg->funcs->get_crc(tg, r_cr, g_y, b_cb);
 409         DC_LOG_WARNING("CRC capture not supported.");
 410         return false;
 411 }
 412
 413 void dc_stream_set_dyn_expansion(struct dc *dc, struct dc_stream_state *stream,
 414                 enum dc_dynamic_expansion option)
 415 {
 416         /* OPP FMT dyn expansion updates*/
 417         int i = 0;
 418         struct pipe_ctx *pipe_ctx;
 419
 420         for (i = 0; i < MAX_PIPES; i++) {
 421                 if (dc->current_state->res_ctx.pipe_ctx[i].stream
 422                                 == stream) {
 423                         pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
 424                         pipe_ctx->stream_res.opp->dyn_expansion = option;
 425                         pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(
 426                                         pipe_ctx->stream_res.opp,
 427                                         COLOR_SPACE_YCBCR601,
 428                                         stream->timing.display_color_depth,
 429                                         stream->signal);
 430                 }
 431         }
 432 }
 433
 434 void dc_stream_set_dither_option(struct dc_stream_state *stream,
 435                 enum dc_dither_option option)
 436 {
 437         struct bit_depth_reduction_params params;
 438         struct dc_link *link = stream->link;
 439         struct pipe_ctx *pipes = NULL;
 440         int i;
 441
 442         for (i = 0; i < MAX_PIPES; i++) {
 443                 if (link->dc->current_state->res_ctx.pipe_ctx[i].stream ==
 444                                 stream) {
 445                         pipes = &link->dc->current_state->res_ctx.pipe_ctx[i];
 446                         break;
 447                 }
 448         }
 449
 450         if (!pipes)
 451                 return;
 452         if (option > DITHER_OPTION_MAX)
 453                 return;
 454
 455         stream->dither_option = option;
 456
 457         memset(&params, 0, sizeof(params));
 458         resource_build_bit_depth_reduction_params(stream, &params);
 459         stream->bit_depth_params = params;
 460
 461         if (pipes->plane_res.xfm &&
 462             pipes->plane_res.xfm->funcs->transform_set_pixel_storage_depth) {
 463                 pipes->plane_res.xfm->funcs->transform_set_pixel_storage_depth(
 464                         pipes->plane_res.xfm,
 465                         pipes->plane_res.scl_data.lb_params.depth,
 466                         &stream->bit_depth_params);
 467         }
 468
 469         pipes->stream_res.opp->funcs->
 470                 opp_program_bit_depth_reduction(pipes->stream_res.opp, &params);
 471 }
 472
 473 bool dc_stream_set_gamut_remap(struct dc *dc, const struct dc_stream_state *stream)
 474 {
 475         int i = 0;
 476         bool ret = false;
 477         struct pipe_ctx *pipes;
 478
 479         for (i = 0; i < MAX_PIPES; i++) {
 480                 if (dc->current_state->res_ctx.pipe_ctx[i].stream == stream) {
 481                         pipes = &dc->current_state->res_ctx.pipe_ctx[i];
 482                         dc->hwss.program_gamut_remap(pipes);
 483                         ret = true;
 484                 }
 485         }
 486
 487         return ret;
 488 }
 489
 490 bool dc_stream_program_csc_matrix(struct dc *dc, struct dc_stream_state *stream)
 491 {
 492         int i = 0;
 493         bool ret = false;
 494         struct pipe_ctx *pipes;
 495
 496         for (i = 0; i < MAX_PIPES; i++) {
 497                 if (dc->current_state->res_ctx.pipe_ctx[i].stream
 498                                 == stream) {
 499
 500                         pipes = &dc->current_state->res_ctx.pipe_ctx[i];
 501                         dc->hwss.program_output_csc(dc,
 502                                         pipes,
 503                                         stream->output_color_space,
 504                                         stream->csc_color_matrix.matrix,
 505                                         pipes->stream_res.opp->inst);
 506                         ret = true;
 507                 }
 508         }
 509
 510         return ret;
 511 }
 512
 513 void dc_stream_set_static_screen_params(struct dc *dc,
 514                 struct dc_stream_state **streams,
 515                 int num_streams,
 516                 const struct dc_static_screen_params *params)
 517 {
 518         int i = 0;
 519         int j = 0;
 520         struct pipe_ctx *pipes_affected[MAX_PIPES];
 521         int num_pipes_affected = 0;
 522
 523         for (i = 0; i < num_streams; i++) {
 524                 struct dc_stream_state *stream = streams[i];
 525
 526                 for (j = 0; j < MAX_PIPES; j++) {
 527                         if (dc->current_state->res_ctx.pipe_ctx[j].stream
 528                                         == stream) {
 529                                 pipes_affected[num_pipes_affected++] =
 530                                                 &dc->current_state->res_ctx.pipe_ctx[j];
 531                         }
 532                 }
 533         }
 534
 535         dc->hwss.set_static_screen_control(pipes_affected, num_pipes_affected, params);
 536 }
 537
 538 static void dc_destruct(struct dc *dc)
 539 {
 540         if (dc->current_state) {
 541                 dc_release_state(dc->current_state);
 542                 dc->current_state = NULL;
 543         }
 544
 545         destroy_links(dc);
 546
 547         if (dc->clk_mgr) {
 548                 dc_destroy_clk_mgr(dc->clk_mgr);
 549                 dc->clk_mgr = NULL;
 550         }
 551
 552         dc_destroy_resource_pool(dc);
 553
 554         if (dc->ctx->gpio_service)
 555                 dal_gpio_service_destroy(&dc->ctx->gpio_service);
 556
 557         if (dc->ctx->created_bios)
 558                 dal_bios_parser_destroy(&dc->ctx->dc_bios);
 559
 560         dc_perf_trace_destroy(&dc->ctx->perf_trace);
 561
 562         kfree(dc->ctx);
 563         dc->ctx = NULL;
 564
 565         kfree(dc->bw_vbios);
 566         dc->bw_vbios = NULL;
 567
 568         kfree(dc->bw_dceip);
 569         dc->bw_dceip = NULL;
 570
 571 #ifdef CONFIG_DRM_AMD_DC_DCN
 572         kfree(dc->dcn_soc);
 573         dc->dcn_soc = NULL;
 574
 575         kfree(dc->dcn_ip);
 576         dc->dcn_ip = NULL;
 577
 578 #endif
 579         kfree(dc->vm_helper);
 580         dc->vm_helper = NULL;
 581
 582 }
 583
 584 static bool dc_construct_ctx(struct dc *dc,
 585                 const struct dc_init_data *init_params)
 586 {
 587         struct dc_context *dc_ctx;
 588         enum dce_version dc_version = DCE_VERSION_UNKNOWN;
 589
 590         dc_ctx = kzalloc(sizeof(*dc_ctx), GFP_KERNEL);
 591         if (!dc_ctx)
 592                 return false;
 593
 594         dc_ctx->cgs_device = init_params->cgs_device;
 595         dc_ctx->driver_context = init_params->driver;
 596         dc_ctx->dc = dc;
 597         dc_ctx->asic_id = init_params->asic_id;
 598         dc_ctx->dc_sink_id_count = 0;
 599         dc_ctx->dc_stream_id_count = 0;
 600         dc_ctx->dce_environment = init_params->dce_environment;
 601
 602         /* Create logger */
 603
 604         dc_version = resource_parse_asic_id(init_params->asic_id);
 605         dc_ctx->dce_version = dc_version;
 606
 607         dc_ctx->perf_trace = dc_perf_trace_create();
 608         if (!dc_ctx->perf_trace) {
 609                 ASSERT_CRITICAL(false);
 610                 return false;
 611         }
 612
 613         dc->ctx = dc_ctx;
 614
 615         return true;
 616 }
 617
 618 static bool dc_construct(struct dc *dc,
 619                 const struct dc_init_data *init_params)
 620 {
 621         struct dc_context *dc_ctx;
 622         struct bw_calcs_dceip *dc_dceip;
 623         struct bw_calcs_vbios *dc_vbios;
 624 #ifdef CONFIG_DRM_AMD_DC_DCN
 625         struct dcn_soc_bounding_box *dcn_soc;
 626         struct dcn_ip_params *dcn_ip;
 627 #endif
 628
 629         dc->config = init_params->flags;
 630
 631         // Allocate memory for the vm_helper
 632         dc->vm_helper = kzalloc(sizeof(struct vm_helper), GFP_KERNEL);
 633         if (!dc->vm_helper) {
 634                 dm_error("%s: failed to create dc->vm_helper\n", __func__);
 635                 goto fail;
 636         }
 637
 638         memcpy(&dc->bb_overrides, &init_params->bb_overrides, sizeof(dc->bb_overrides));
 639
 640         dc_dceip = kzalloc(sizeof(*dc_dceip), GFP_KERNEL);
 641         if (!dc_dceip) {
 642                 dm_error("%s: failed to create dceip\n", __func__);
 643                 goto fail;
 644         }
 645
 646         dc->bw_dceip = dc_dceip;
 647
 648         dc_vbios = kzalloc(sizeof(*dc_vbios), GFP_KERNEL);
 649         if (!dc_vbios) {
 650                 dm_error("%s: failed to create vbios\n", __func__);
 651                 goto fail;
 652         }
 653
 654         dc->bw_vbios = dc_vbios;
 655 #ifdef CONFIG_DRM_AMD_DC_DCN
 656         dcn_soc = kzalloc(sizeof(*dcn_soc), GFP_KERNEL);
 657         if (!dcn_soc) {
 658                 dm_error("%s: failed to create dcn_soc\n", __func__);
 659                 goto fail;
 660         }
 661
 662         dc->dcn_soc = dcn_soc;
 663
 664         dcn_ip = kzalloc(sizeof(*dcn_ip), GFP_KERNEL);
 665         if (!dcn_ip) {
 666                 dm_error("%s: failed to create dcn_ip\n", __func__);
 667                 goto fail;
 668         }
 669
 670         dc->dcn_ip = dcn_ip;
 671         dc->soc_bounding_box = init_params->soc_bounding_box;
 672 #endif
 673
 674         if (!dc_construct_ctx(dc, init_params)) {
 675                 dm_error("%s: failed to create ctx\n", __func__);
 676                 goto fail;
 677         }
 678
 679         dc_ctx = dc->ctx;
 680
 681         /* Resource should construct all asic specific resources.
 682          * This should be the only place where we need to parse the asic id
 683          */
 684         if (init_params->vbios_override)
 685                 dc_ctx->dc_bios = init_params->vbios_override;
 686         else {
 687                 /* Create BIOS parser */
 688                 struct bp_init_data bp_init_data;
 689
 690                 bp_init_data.ctx = dc_ctx;
 691                 bp_init_data.bios = init_params->asic_id.atombios_base_address;
 692
 693                 dc_ctx->dc_bios = dal_bios_parser_create(
 694                                 &bp_init_data, dc_ctx->dce_version);
 695
 696                 if (!dc_ctx->dc_bios) {
 697                         ASSERT_CRITICAL(false);
 698                         goto fail;
 699                 }
 700
 701                 dc_ctx->created_bios = true;
 702         }
 703
 704         dc->vendor_signature = init_params->vendor_signature;
 705
 706         /* Create GPIO service */
 707         dc_ctx->gpio_service = dal_gpio_service_create(
 708                         dc_ctx->dce_version,
 709                         dc_ctx->dce_environment,
 710                         dc_ctx);
 711
 712         if (!dc_ctx->gpio_service) {
 713                 ASSERT_CRITICAL(false);
 714                 goto fail;
 715         }
 716
 717         dc->res_pool = dc_create_resource_pool(dc, init_params, dc_ctx->dce_version);
 718         if (!dc->res_pool)
 719                 goto fail;
 720
 721         dc->clk_mgr = dc_clk_mgr_create(dc->ctx, dc->res_pool->pp_smu, dc->res_pool->dccg);
 722         if (!dc->clk_mgr)
 723                 goto fail;
 724
 725         if (dc->res_pool->funcs->update_bw_bounding_box)
 726                 dc->res_pool->funcs->update_bw_bounding_box(dc, dc->clk_mgr->bw_params);
 727
 728         /* Creation of current_state must occur after dc->dml
 729          * is initialized in dc_create_resource_pool because
 730          * on creation it copies the contents of dc->dml
 731          */
 732
 733         dc->current_state = dc_create_state(dc);
 734
 735         if (!dc->current_state) {
 736                 dm_error("%s: failed to create validate ctx\n", __func__);
 737                 goto fail;
 738         }
 739
 740         dc_resource_state_construct(dc, dc->current_state);
 741
 742         if (!create_links(dc, init_params->num_virtual_links))
 743                 goto fail;
 744
 745         return true;
 746
 747 fail:
 748         return false;
 749 }
 750
 751 static bool disable_all_writeback_pipes_for_stream(
 752                 const struct dc *dc,
 753                 struct dc_stream_state *stream,
 754                 struct dc_state *context)
 755 {
 756         int i;
 757
 758         for (i = 0; i < stream->num_wb_info; i++)
 759                 stream->writeback_info[i].wb_enabled = false;
 760
 761         return true;
 762 }
 763
 764 void apply_ctx_interdependent_lock(struct dc *dc, struct dc_state *context, struct dc_stream_state *stream, bool lock)
 765 {
 766         int i = 0;
 767
 768         /* Checks if interdependent update function pointer is NULL or not, takes care of DCE110 case */
 769         if (dc->hwss.interdependent_update_lock)
 770                 dc->hwss.interdependent_update_lock(dc, context, lock);
 771         else {
 772                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
 773                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
 774                         struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
 775
 776                         // Copied conditions that were previously in dce110_apply_ctx_for_surface
 777                         if (stream == pipe_ctx->stream) {
 778                                 if (!pipe_ctx->top_pipe &&
 779                                         (pipe_ctx->plane_state || old_pipe_ctx->plane_state))
 780                                         dc->hwss.pipe_control_lock(dc, pipe_ctx, lock);
 781                         }
 782                 }
 783         }
 784 }
 785
 786 static void disable_dangling_plane(struct dc *dc, struct dc_state *context)
 787 {
 788         int i, j;
 789         struct dc_state *dangling_context = dc_create_state(dc);
 790         struct dc_state *current_ctx;
 791
 792         if (dangling_context == NULL)
 793                 return;
 794
 795         dc_resource_state_copy_construct(dc->current_state, dangling_context);
 796
 797         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 798                 struct dc_stream_state *old_stream =
 799                                 dc->current_state->res_ctx.pipe_ctx[i].stream;
 800                 bool should_disable = true;
 801
 802                 for (j = 0; j < context->stream_count; j++) {
 803                         if (old_stream == context->streams[j]) {
 804                                 should_disable = false;
 805                                 break;
 806                         }
 807                 }
 808                 if (should_disable && old_stream) {
 809                         dc_rem_all_planes_for_stream(dc, old_stream, dangling_context);
 810                         disable_all_writeback_pipes_for_stream(dc, old_stream, dangling_context);
 811
 812                         if (dc->hwss.apply_ctx_for_surface) {
 813                                 apply_ctx_interdependent_lock(dc, dc->current_state, old_stream, true);
 814                                 dc->hwss.apply_ctx_for_surface(dc, old_stream, 0, dangling_context);
 815                                 apply_ctx_interdependent_lock(dc, dc->current_state, old_stream, false);
 816                                 dc->hwss.post_unlock_program_front_end(dc, dangling_context);
 817                         }
 818                         if (dc->hwss.program_front_end_for_ctx) {
 819                                 dc->hwss.interdependent_update_lock(dc, dc->current_state, true);
 820                                 dc->hwss.program_front_end_for_ctx(dc, dangling_context);
 821                                 dc->hwss.interdependent_update_lock(dc, dc->current_state, false);
 822                                 dc->hwss.post_unlock_program_front_end(dc, dangling_context);
 823                         }
 824                 }
 825         }
 826
 827         current_ctx = dc->current_state;
 828         dc->current_state = dangling_context;
 829         dc_release_state(current_ctx);
 830 }
 831
 832 static void wait_for_no_pipes_pending(struct dc *dc, struct dc_state *context)
 833 {
 834         int i;
 835         int count = 0;
 836         struct pipe_ctx *pipe;
 837         PERF_TRACE();
 838         for (i = 0; i < MAX_PIPES; i++) {
 839                 pipe = &context->res_ctx.pipe_ctx[i];
 840
 841                 if (!pipe->plane_state)
 842                         continue;
 843
 844                 /* Timeout 100 ms */
 845                 while (count < 100000) {
 846                         /* Must set to false to start with, due to OR in update function */
 847                         pipe->plane_state->status.is_flip_pending = false;
 848                         dc->hwss.update_pending_status(pipe);
 849                         if (!pipe->plane_state->status.is_flip_pending)
 850                                 break;
 851                         udelay(1);
 852                         count++;
 853                 }
 854                 ASSERT(!pipe->plane_state->status.is_flip_pending);
 855         }
 856         PERF_TRACE();
 857 }
 858
 859 /*******************************************************************************
 860  * Public functions
 861  ******************************************************************************/
 862
 863 struct dc *dc_create(const struct dc_init_data *init_params)
 864 {
 865         struct dc *dc = kzalloc(sizeof(*dc), GFP_KERNEL);
 866         unsigned int full_pipe_count;
 867
 868         if (NULL == dc)
 869                 goto alloc_fail;
 870
 871         if (init_params->dce_environment == DCE_ENV_VIRTUAL_HW) {
 872                 if (false == dc_construct_ctx(dc, init_params)) {
 873                         dc_destruct(dc);
 874                         goto construct_fail;
 875                 }
 876         } else {
 877                 if (false == dc_construct(dc, init_params)) {
 878                         dc_destruct(dc);
 879                         goto construct_fail;
 880                 }
 881
 882                 full_pipe_count = dc->res_pool->pipe_count;
 883                 if (dc->res_pool->underlay_pipe_index != NO_UNDERLAY_PIPE)
 884                         full_pipe_count--;
 885                 dc->caps.max_streams = min(
 886                                 full_pipe_count,
 887                                 dc->res_pool->stream_enc_count);
 888
 889                 dc->optimize_seamless_boot_streams = 0;
 890                 dc->caps.max_links = dc->link_count;
 891                 dc->caps.max_audios = dc->res_pool->audio_count;
 892                 dc->caps.linear_pitch_alignment = 64;
 893
 894                 dc->caps.max_dp_protocol_version = DP_VERSION_1_4;
 895
 896                 if (dc->res_pool->dmcu != NULL)
 897                         dc->versions.dmcu_version = dc->res_pool->dmcu->dmcu_version;
 898         }
 899
 900         /* Populate versioning information */
 901         dc->versions.dc_ver = DC_VER;
 902
 903         dc->build_id = DC_BUILD_ID;
 904
 905         DC_LOG_DC("Display Core initialized\n");
 906
 907
 908
 909         return dc;
 910
 911 construct_fail:
 912         kfree(dc);
 913
 914 alloc_fail:
 915         return NULL;
 916 }
 917
 918 void dc_hardware_init(struct dc *dc)
 919 {
 920         if (dc->ctx->dce_environment != DCE_ENV_VIRTUAL_HW)
 921                 dc->hwss.init_hw(dc);
 922 }
 923
 924 void dc_init_callbacks(struct dc *dc,
 925                 const struct dc_callback_init *init_params)
 926 {
 927 #ifdef CONFIG_DRM_AMD_DC_HDCP
 928         dc->ctx->cp_psp = init_params->cp_psp;
 929 #endif
 930 }
 931
 932 void dc_deinit_callbacks(struct dc *dc)
 933 {
 934 #ifdef CONFIG_DRM_AMD_DC_HDCP
 935         memset(&dc->ctx->cp_psp, 0, sizeof(dc->ctx->cp_psp));
 936 #endif
 937 }
 938
 939 void dc_destroy(struct dc **dc)
 940 {
 941         dc_destruct(*dc);
 942         kfree(*dc);
 943         *dc = NULL;
 944 }
 945
 946 static void enable_timing_multisync(
 947                 struct dc *dc,
 948                 struct dc_state *ctx)
 949 {
 950         int i = 0, multisync_count = 0;
 951         int pipe_count = dc->res_pool->pipe_count;
 952         struct pipe_ctx *multisync_pipes[MAX_PIPES] = { NULL };
 953
 954         for (i = 0; i < pipe_count; i++) {
 955                 if (!ctx->res_ctx.pipe_ctx[i].stream ||
 956                                 !ctx->res_ctx.pipe_ctx[i].stream->triggered_crtc_reset.enabled)
 957                         continue;
 958                 if (ctx->res_ctx.pipe_ctx[i].stream == ctx->res_ctx.pipe_ctx[i].stream->triggered_crtc_reset.event_source)
 959                         continue;
 960                 multisync_pipes[multisync_count] = &ctx->res_ctx.pipe_ctx[i];
 961                 multisync_count++;
 962         }
 963
 964         if (multisync_count > 0) {
 965                 dc->hwss.enable_per_frame_crtc_position_reset(
 966                         dc, multisync_count, multisync_pipes);
 967         }
 968 }
 969
 970 static void program_timing_sync(
 971                 struct dc *dc,
 972                 struct dc_state *ctx)
 973 {
 974         int i, j, k;
 975         int group_index = 0;
 976         int num_group = 0;
 977         int pipe_count = dc->res_pool->pipe_count;
 978         struct pipe_ctx *unsynced_pipes[MAX_PIPES] = { NULL };
 979
 980         for (i = 0; i < pipe_count; i++) {
 981                 if (!ctx->res_ctx.pipe_ctx[i].stream || ctx->res_ctx.pipe_ctx[i].top_pipe)
 982                         continue;
 983
 984                 unsynced_pipes[i] = &ctx->res_ctx.pipe_ctx[i];
 985         }
 986
 987         for (i = 0; i < pipe_count; i++) {
 988                 int group_size = 1;
 989                 struct pipe_ctx *pipe_set[MAX_PIPES];
 990
 991                 if (!unsynced_pipes[i])
 992                         continue;
 993
 994                 pipe_set[0] = unsynced_pipes[i];
 995                 unsynced_pipes[i] = NULL;
 996
 997                 /* Add tg to the set, search rest of the tg's for ones with
 998                  * same timing, add all tgs with same timing to the group
 999                  */
1000                 for (j = i + 1; j < pipe_count; j++) {
1001                         if (!unsynced_pipes[j])
1002                                 continue;
1003
1004                         if (resource_are_streams_timing_synchronizable(
1005                                         unsynced_pipes[j]->stream,
1006                                         pipe_set[0]->stream)) {
1007                                 pipe_set[group_size] = unsynced_pipes[j];
1008                                 unsynced_pipes[j] = NULL;
1009                                 group_size++;
1010                         }
1011                 }
1012
1013                 /* set first pipe with plane as master */
1014                 for (j = 0; j < group_size; j++) {
1015                         if (pipe_set[j]->plane_state) {
1016                                 if (j == 0)
1017                                         break;
1018
1019                                 swap(pipe_set[0], pipe_set[j]);
1020                                 break;
1021                         }
1022                 }
1023
1024
1025                 for (k = 0; k < group_size; k++) {
1026                         struct dc_stream_status *status = dc_stream_get_status_from_state(ctx, pipe_set[k]->stream);
1027
1028                         status->timing_sync_info.group_id = num_group;
1029                         status->timing_sync_info.group_size = group_size;
1030                         if (k == 0)
1031                                 status->timing_sync_info.master = true;
1032                         else
1033                                 status->timing_sync_info.master = false;
1034
1035                 }
1036                 /* remove any other pipes with plane as they have already been synced */
1037                 for (j = j + 1; j < group_size; j++) {
1038                         if (pipe_set[j]->plane_state) {
1039                                 group_size--;
1040                                 pipe_set[j] = pipe_set[group_size];
1041                                 j--;
1042                         }
1043                 }
1044
1045                 if (group_size > 1) {
1046                         dc->hwss.enable_timing_synchronization(
1047                                 dc, group_index, group_size, pipe_set);
1048                         group_index++;
1049                 }
1050                 num_group++;
1051         }
1052 }
1053
1054 static bool context_changed(
1055                 struct dc *dc,
1056                 struct dc_state *context)
1057 {
1058         uint8_t i;
1059
1060         if (context->stream_count != dc->current_state->stream_count)
1061                 return true;
1062
1063         for (i = 0; i < dc->current_state->stream_count; i++) {
1064                 if (dc->current_state->streams[i] != context->streams[i])
1065                         return true;
1066         }
1067
1068         return false;
1069 }
1070
1071 bool dc_validate_seamless_boot_timing(const struct dc *dc,
1072                                 const struct dc_sink *sink,
1073                                 struct dc_crtc_timing *crtc_timing)
1074 {
1075         struct timing_generator *tg;
1076         struct stream_encoder *se = NULL;
1077
1078         struct dc_crtc_timing hw_crtc_timing = {0};
1079
1080         struct dc_link *link = sink->link;
1081         unsigned int i, enc_inst, tg_inst = 0;
1082
1083         // Seamless port only support single DP and EDP so far
1084         if (sink->sink_signal != SIGNAL_TYPE_DISPLAY_PORT &&
1085                 sink->sink_signal != SIGNAL_TYPE_EDP)
1086                 return false;
1087
1088         /* Check for enabled DIG to identify enabled display */
1089         if (!link->link_enc->funcs->is_dig_enabled(link->link_enc))
1090                 return false;
1091
1092         enc_inst = link->link_enc->funcs->get_dig_frontend(link->link_enc);
1093
1094         if (enc_inst == ENGINE_ID_UNKNOWN)
1095                 return false;
1096
1097         for (i = 0; i < dc->res_pool->stream_enc_count; i++) {
1098                 if (dc->res_pool->stream_enc[i]->id == enc_inst) {
1099
1100                         se = dc->res_pool->stream_enc[i];
1101
1102                         tg_inst = dc->res_pool->stream_enc[i]->funcs->dig_source_otg(
1103                                 dc->res_pool->stream_enc[i]);
1104                         break;
1105                 }
1106         }
1107
1108         // tg_inst not found
1109         if (i == dc->res_pool->stream_enc_count)
1110                 return false;
1111
1112         if (tg_inst >= dc->res_pool->timing_generator_count)
1113                 return false;
1114
1115         tg = dc->res_pool->timing_generators[tg_inst];
1116
1117         if (!tg->funcs->get_hw_timing)
1118                 return false;
1119
1120         if (!tg->funcs->get_hw_timing(tg, &hw_crtc_timing))
1121                 return false;
1122
1123         if (crtc_timing->h_total != hw_crtc_timing.h_total)
1124                 return false;
1125
1126         if (crtc_timing->h_border_left != hw_crtc_timing.h_border_left)
1127                 return false;
1128
1129         if (crtc_timing->h_addressable != hw_crtc_timing.h_addressable)
1130                 return false;
1131
1132         if (crtc_timing->h_border_right != hw_crtc_timing.h_border_right)
1133                 return false;
1134
1135         if (crtc_timing->h_front_porch != hw_crtc_timing.h_front_porch)
1136                 return false;
1137
1138         if (crtc_timing->h_sync_width != hw_crtc_timing.h_sync_width)
1139                 return false;
1140
1141         if (crtc_timing->v_total != hw_crtc_timing.v_total)
1142                 return false;
1143
1144         if (crtc_timing->v_border_top != hw_crtc_timing.v_border_top)
1145                 return false;
1146
1147         if (crtc_timing->v_addressable != hw_crtc_timing.v_addressable)
1148                 return false;
1149
1150         if (crtc_timing->v_border_bottom != hw_crtc_timing.v_border_bottom)
1151                 return false;
1152
1153         if (crtc_timing->v_front_porch != hw_crtc_timing.v_front_porch)
1154                 return false;
1155
1156         if (crtc_timing->v_sync_width != hw_crtc_timing.v_sync_width)
1157                 return false;
1158
1159         if (dc_is_dp_signal(link->connector_signal)) {
1160                 unsigned int pix_clk_100hz;
1161
1162                 dc->res_pool->dp_clock_source->funcs->get_pixel_clk_frequency_100hz(
1163                         dc->res_pool->dp_clock_source,
1164                         tg_inst, &pix_clk_100hz);
1165
1166                 if (crtc_timing->pix_clk_100hz != pix_clk_100hz)
1167                         return false;
1168
1169                 if (!se->funcs->dp_get_pixel_format)
1170                         return false;
1171
1172                 if (!se->funcs->dp_get_pixel_format(
1173                         se,
1174                         &hw_crtc_timing.pixel_encoding,
1175                         &hw_crtc_timing.display_color_depth))
1176                         return false;
1177
1178                 if (hw_crtc_timing.display_color_depth != crtc_timing->display_color_depth)
1179                         return false;
1180
1181                 if (hw_crtc_timing.pixel_encoding != crtc_timing->pixel_encoding)
1182                         return false;
1183         }
1184
1185         return true;
1186 }
1187
1188 bool dc_enable_stereo(
1189         struct dc *dc,
1190         struct dc_state *context,
1191         struct dc_stream_state *streams[],
1192         uint8_t stream_count)
1193 {
1194         bool ret = true;
1195         int i, j;
1196         struct pipe_ctx *pipe;
1197
1198         for (i = 0; i < MAX_PIPES; i++) {
1199                 if (context != NULL)
1200                         pipe = &context->res_ctx.pipe_ctx[i];
1201                 else
1202                         pipe = &dc->current_state->res_ctx.pipe_ctx[i];
1203                 for (j = 0 ; pipe && j < stream_count; j++)  {
1204                         if (streams[j] && streams[j] == pipe->stream &&
1205                                 dc->hwss.setup_stereo)
1206                                 dc->hwss.setup_stereo(pipe, dc);
1207                 }
1208         }
1209
1210         return ret;
1211 }
1212
1213 /*
1214  * Applies given context to HW and copy it into current context.
1215  * It's up to the user to release the src context afterwards.
1216  */
1217 static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *context)
1218 {
1219         struct dc_bios *dcb = dc->ctx->dc_bios;
1220         enum dc_status result = DC_ERROR_UNEXPECTED;
1221         struct pipe_ctx *pipe;
1222         int i, k, l;
1223         struct dc_stream_state *dc_streams[MAX_STREAMS] = {0};
1224
1225         disable_dangling_plane(dc, context);
1226
1227         for (i = 0; i < context->stream_count; i++)
1228                 dc_streams[i] =  context->streams[i];
1229
1230         if (!dcb->funcs->is_accelerated_mode(dcb))
1231                 dc->hwss.enable_accelerated_mode(dc, context);
1232
1233         for (i = 0; i < context->stream_count; i++) {
1234                 if (context->streams[i]->apply_seamless_boot_optimization)
1235                         dc->optimize_seamless_boot_streams++;
1236         }
1237
1238         if (dc->optimize_seamless_boot_streams == 0)
1239                 dc->hwss.prepare_bandwidth(dc, context);
1240
1241         /* re-program planes for existing stream, in case we need to
1242          * free up plane resource for later use
1243          */
1244         if (dc->hwss.apply_ctx_for_surface) {
1245                 for (i = 0; i < context->stream_count; i++) {
1246                         if (context->streams[i]->mode_changed)
1247                                 continue;
1248                         apply_ctx_interdependent_lock(dc, context, context->streams[i], true);
1249                         dc->hwss.apply_ctx_for_surface(
1250                                 dc, context->streams[i],
1251                                 context->stream_status[i].plane_count,
1252                                 context); /* use new pipe config in new context */
1253                         apply_ctx_interdependent_lock(dc, context, context->streams[i], false);
1254                         dc->hwss.post_unlock_program_front_end(dc, context);
1255                 }
1256         }
1257
1258         /* Program hardware */
1259         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1260                 pipe = &context->res_ctx.pipe_ctx[i];
1261                 dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe);
1262         }
1263
1264         result = dc->hwss.apply_ctx_to_hw(dc, context);
1265
1266         if (result != DC_OK)
1267                 return result;
1268
1269         if (context->stream_count > 1 && !dc->debug.disable_timing_sync) {
1270                 enable_timing_multisync(dc, context);
1271                 program_timing_sync(dc, context);
1272         }
1273
1274         /* Program all planes within new context*/
1275         if (dc->hwss.program_front_end_for_ctx) {
1276                 dc->hwss.interdependent_update_lock(dc, context, true);
1277                 dc->hwss.program_front_end_for_ctx(dc, context);
1278                 dc->hwss.interdependent_update_lock(dc, context, false);
1279                 dc->hwss.post_unlock_program_front_end(dc, context);
1280         }
1281         for (i = 0; i < context->stream_count; i++) {
1282                 const struct dc_link *link = context->streams[i]->link;
1283
1284                 if (!context->streams[i]->mode_changed)
1285                         continue;
1286
1287                 if (dc->hwss.apply_ctx_for_surface) {
1288                         apply_ctx_interdependent_lock(dc, context, context->streams[i], true);
1289                         dc->hwss.apply_ctx_for_surface(
1290                                         dc, context->streams[i],
1291                                         context->stream_status[i].plane_count,
1292                                         context);
1293                         apply_ctx_interdependent_lock(dc, context, context->streams[i], false);
1294                         dc->hwss.post_unlock_program_front_end(dc, context);
1295                 }
1296
1297                 /*
1298                  * enable stereo
1299                  * TODO rework dc_enable_stereo call to work with validation sets?
1300                  */
1301                 for (k = 0; k < MAX_PIPES; k++) {
1302                         pipe = &context->res_ctx.pipe_ctx[k];
1303
1304                         for (l = 0 ; pipe && l < context->stream_count; l++)  {
1305                                 if (context->streams[l] &&
1306                                         context->streams[l] == pipe->stream &&
1307                                         dc->hwss.setup_stereo)
1308                                         dc->hwss.setup_stereo(pipe, dc);
1309                         }
1310                 }
1311
1312                 CONN_MSG_MODE(link, "{%dx%d, %dx%d@%dKhz}",
1313                                 context->streams[i]->timing.h_addressable,
1314                                 context->streams[i]->timing.v_addressable,
1315                                 context->streams[i]->timing.h_total,
1316                                 context->streams[i]->timing.v_total,
1317                                 context->streams[i]->timing.pix_clk_100hz / 10);
1318         }
1319
1320         dc_enable_stereo(dc, context, dc_streams, context->stream_count);
1321
1322         if (dc->optimize_seamless_boot_streams == 0) {
1323                 /* Must wait for no flips to be pending before doing optimize bw */
1324                 wait_for_no_pipes_pending(dc, context);
1325                 /* pplib is notified if disp_num changed */
1326                 dc->hwss.optimize_bandwidth(dc, context);
1327         }
1328
1329         for (i = 0; i < context->stream_count; i++)
1330                 context->streams[i]->mode_changed = false;
1331
1332         dc_release_state(dc->current_state);
1333
1334         dc->current_state = context;
1335
1336         dc_retain_state(dc->current_state);
1337
1338         return result;
1339 }
1340
1341 bool dc_commit_state(struct dc *dc, struct dc_state *context)
1342 {
1343         enum dc_status result = DC_ERROR_UNEXPECTED;
1344         int i;
1345
1346         if (false == context_changed(dc, context))
1347                 return DC_OK;
1348
1349         DC_LOG_DC("%s: %d streams\n",
1350                                 __func__, context->stream_count);
1351
1352         for (i = 0; i < context->stream_count; i++) {
1353                 struct dc_stream_state *stream = context->streams[i];
1354
1355                 dc_stream_log(dc, stream);
1356         }
1357
1358         result = dc_commit_state_no_check(dc, context);
1359
1360         return (result == DC_OK);
1361 }
1362
1363 static bool is_flip_pending_in_pipes(struct dc *dc, struct dc_state *context)
1364 {
1365         int i;
1366         struct pipe_ctx *pipe;
1367
1368         for (i = 0; i < MAX_PIPES; i++) {
1369                 pipe = &context->res_ctx.pipe_ctx[i];
1370
1371                 if (!pipe->plane_state)
1372                         continue;
1373
1374                 /* Must set to false to start with, due to OR in update function */
1375                 pipe->plane_state->status.is_flip_pending = false;
1376                 dc->hwss.update_pending_status(pipe);
1377                 if (pipe->plane_state->status.is_flip_pending)
1378                         return true;
1379         }
1380         return false;
1381 }
1382
1383 bool dc_post_update_surfaces_to_stream(struct dc *dc)
1384 {
1385         int i;
1386         struct dc_state *context = dc->current_state;
1387
1388         if ((!dc->optimized_required) || dc->optimize_seamless_boot_streams > 0)
1389                 return true;
1390
1391         post_surface_trace(dc);
1392
1393         if (is_flip_pending_in_pipes(dc, context))
1394                 return true;
1395
1396         for (i = 0; i < dc->res_pool->pipe_count; i++)
1397                 if (context->res_ctx.pipe_ctx[i].stream == NULL ||
1398                     context->res_ctx.pipe_ctx[i].plane_state == NULL) {
1399                         context->res_ctx.pipe_ctx[i].pipe_idx = i;
1400                         dc->hwss.disable_plane(dc, &context->res_ctx.pipe_ctx[i]);
1401                 }
1402
1403         dc->hwss.optimize_bandwidth(dc, context);
1404
1405         dc->optimized_required = false;
1406         dc->wm_optimized_required = false;
1407
1408         return true;
1409 }
1410
1411 struct dc_state *dc_create_state(struct dc *dc)
1412 {
1413         struct dc_state *context = kvzalloc(sizeof(struct dc_state),
1414                                             GFP_KERNEL);
1415
1416         if (!context)
1417                 return NULL;
1418         /* Each context must have their own instance of VBA and in order to
1419          * initialize and obtain IP and SOC the base DML instance from DC is
1420          * initially copied into every context
1421          */
1422 #ifdef CONFIG_DRM_AMD_DC_DCN
1423         memcpy(&context->bw_ctx.dml, &dc->dml, sizeof(struct display_mode_lib));
1424 #endif
1425
1426         kref_init(&context->refcount);
1427
1428         return context;
1429 }
1430
1431 struct dc_state *dc_copy_state(struct dc_state *src_ctx)
1432 {
1433         int i, j;
1434         struct dc_state *new_ctx = kvmalloc(sizeof(struct dc_state), GFP_KERNEL);
1435
1436         if (!new_ctx)
1437                 return NULL;
1438         memcpy(new_ctx, src_ctx, sizeof(struct dc_state));
1439
1440         for (i = 0; i < MAX_PIPES; i++) {
1441                         struct pipe_ctx *cur_pipe = &new_ctx->res_ctx.pipe_ctx[i];
1442
1443                         if (cur_pipe->top_pipe)
1444                                 cur_pipe->top_pipe =  &new_ctx->res_ctx.pipe_ctx[cur_pipe->top_pipe->pipe_idx];
1445
1446                         if (cur_pipe->bottom_pipe)
1447                                 cur_pipe->bottom_pipe = &new_ctx->res_ctx.pipe_ctx[cur_pipe->bottom_pipe->pipe_idx];
1448
1449                         if (cur_pipe->prev_odm_pipe)
1450                                 cur_pipe->prev_odm_pipe =  &new_ctx->res_ctx.pipe_ctx[cur_pipe->prev_odm_pipe->pipe_idx];
1451
1452                         if (cur_pipe->next_odm_pipe)
1453                                 cur_pipe->next_odm_pipe = &new_ctx->res_ctx.pipe_ctx[cur_pipe->next_odm_pipe->pipe_idx];
1454
1455         }
1456
1457         for (i = 0; i < new_ctx->stream_count; i++) {
1458                         dc_stream_retain(new_ctx->streams[i]);
1459                         for (j = 0; j < new_ctx->stream_status[i].plane_count; j++)
1460                                 dc_plane_state_retain(
1461                                         new_ctx->stream_status[i].plane_states[j]);
1462         }
1463
1464         kref_init(&new_ctx->refcount);
1465
1466         return new_ctx;
1467 }
1468
1469 void dc_retain_state(struct dc_state *context)
1470 {
1471         kref_get(&context->refcount);
1472 }
1473
1474 static void dc_state_free(struct kref *kref)
1475 {
1476         struct dc_state *context = container_of(kref, struct dc_state, refcount);
1477         dc_resource_state_destruct(context);
1478         kvfree(context);
1479 }
1480
1481 void dc_release_state(struct dc_state *context)
1482 {
1483         kref_put(&context->refcount, dc_state_free);
1484 }
1485
1486 bool dc_set_generic_gpio_for_stereo(bool enable,
1487                 struct gpio_service *gpio_service)
1488 {
1489         enum gpio_result gpio_result = GPIO_RESULT_NON_SPECIFIC_ERROR;
1490         struct gpio_pin_info pin_info;
1491         struct gpio *generic;
1492         struct gpio_generic_mux_config *config = kzalloc(sizeof(struct gpio_generic_mux_config),
1493                            GFP_KERNEL);
1494
1495         if (!config)
1496                 return false;
1497         pin_info = dal_gpio_get_generic_pin_info(gpio_service, GPIO_ID_GENERIC, 0);
1498
1499         if (pin_info.mask == 0xFFFFFFFF || pin_info.offset == 0xFFFFFFFF) {
1500                 kfree(config);
1501                 return false;
1502         } else {
1503                 generic = dal_gpio_service_create_generic_mux(
1504                         gpio_service,
1505                         pin_info.offset,
1506                         pin_info.mask);
1507         }
1508
1509         if (!generic) {
1510                 kfree(config);
1511                 return false;
1512         }
1513
1514         gpio_result = dal_gpio_open(generic, GPIO_MODE_OUTPUT);
1515
1516         config->enable_output_from_mux = enable;
1517         config->mux_select = GPIO_SIGNAL_SOURCE_PASS_THROUGH_STEREO_SYNC;
1518
1519         if (gpio_result == GPIO_RESULT_OK)
1520                 gpio_result = dal_mux_setup_config(generic, config);
1521
1522         if (gpio_result == GPIO_RESULT_OK) {
1523                 dal_gpio_close(generic);
1524                 dal_gpio_destroy_generic_mux(&generic);
1525                 kfree(config);
1526                 return true;
1527         } else {
1528                 dal_gpio_close(generic);
1529                 dal_gpio_destroy_generic_mux(&generic);
1530                 kfree(config);
1531                 return false;
1532         }
1533 }
1534
1535 static bool is_surface_in_context(
1536                 const struct dc_state *context,
1537                 const struct dc_plane_state *plane_state)
1538 {
1539         int j;
1540
1541         for (j = 0; j < MAX_PIPES; j++) {
1542                 const struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
1543
1544                 if (plane_state == pipe_ctx->plane_state) {
1545                         return true;
1546                 }
1547         }
1548
1549         return false;
1550 }
1551
1552 static enum surface_update_type get_plane_info_update_type(const struct dc_surface_update *u)
1553 {
1554         union surface_update_flags *update_flags = &u->surface->update_flags;
1555         enum surface_update_type update_type = UPDATE_TYPE_FAST;
1556
1557         if (!u->plane_info)
1558                 return UPDATE_TYPE_FAST;
1559
1560         if (u->plane_info->color_space != u->surface->color_space) {
1561                 update_flags->bits.color_space_change = 1;
1562                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
1563         }
1564
1565         if (u->plane_info->horizontal_mirror != u->surface->horizontal_mirror) {
1566                 update_flags->bits.horizontal_mirror_change = 1;
1567                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
1568         }
1569
1570         if (u->plane_info->rotation != u->surface->rotation) {
1571                 update_flags->bits.rotation_change = 1;
1572                 elevate_update_type(&update_type, UPDATE_TYPE_FULL);
1573         }
1574
1575         if (u->plane_info->format != u->surface->format) {
1576                 update_flags->bits.pixel_format_change = 1;
1577                 elevate_update_type(&update_type, UPDATE_TYPE_FULL);
1578         }
1579
1580         if (u->plane_info->stereo_format != u->surface->stereo_format) {
1581                 update_flags->bits.stereo_format_change = 1;
1582                 elevate_update_type(&update_type, UPDATE_TYPE_FULL);
1583         }
1584
1585         if (u->plane_info->per_pixel_alpha != u->surface->per_pixel_alpha) {
1586                 update_flags->bits.per_pixel_alpha_change = 1;
1587                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
1588         }
1589
1590         if (u->plane_info->global_alpha_value != u->surface->global_alpha_value) {
1591                 update_flags->bits.global_alpha_change = 1;
1592                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
1593         }
1594
1595         if (u->plane_info->dcc.enable != u->surface->dcc.enable
1596                         || u->plane_info->dcc.independent_64b_blks != u->surface->dcc.independent_64b_blks
1597                         || u->plane_info->dcc.meta_pitch != u->surface->dcc.meta_pitch) {
1598                 update_flags->bits.dcc_change = 1;
1599                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
1600         }
1601
1602         if (resource_pixel_format_to_bpp(u->plane_info->format) !=
1603                         resource_pixel_format_to_bpp(u->surface->format)) {
1604                 /* different bytes per element will require full bandwidth
1605                  * and DML calculation
1606                  */
1607                 update_flags->bits.bpp_change = 1;
1608                 elevate_update_type(&update_type, UPDATE_TYPE_FULL);
1609         }
1610
1611         if (u->plane_info->plane_size.surface_pitch != u->surface->plane_size.surface_pitch
1612                         || u->plane_info->plane_size.chroma_pitch != u->surface->plane_size.chroma_pitch) {
1613                 update_flags->bits.plane_size_change = 1;
1614                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
1615         }
1616
1617
1618         if (memcmp(&u->plane_info->tiling_info, &u->surface->tiling_info,
1619                         sizeof(union dc_tiling_info)) != 0) {
1620                 update_flags->bits.swizzle_change = 1;
1621                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
1622
1623                 /* todo: below are HW dependent, we should add a hook to
1624                  * DCE/N resource and validated there.
1625                  */
1626                 if (u->plane_info->tiling_info.gfx9.swizzle != DC_SW_LINEAR) {
1627                         /* swizzled mode requires RQ to be setup properly,
1628                          * thus need to run DML to calculate RQ settings
1629                          */
1630                         update_flags->bits.bandwidth_change = 1;
1631                         elevate_update_type(&update_type, UPDATE_TYPE_FULL);
1632                 }
1633         }
1634
1635         /* This should be UPDATE_TYPE_FAST if nothing has changed. */
1636         return update_type;
1637 }
1638
1639 static enum surface_update_type get_scaling_info_update_type(
1640                 const struct dc_surface_update *u)
1641 {
1642         union surface_update_flags *update_flags = &u->surface->update_flags;
1643
1644         if (!u->scaling_info)
1645                 return UPDATE_TYPE_FAST;
1646
1647         if (u->scaling_info->clip_rect.width != u->surface->clip_rect.width
1648                         || u->scaling_info->clip_rect.height != u->surface->clip_rect.height
1649                         || u->scaling_info->dst_rect.width != u->surface->dst_rect.width
1650                         || u->scaling_info->dst_rect.height != u->surface->dst_rect.height
1651                         || u->scaling_info->scaling_quality.integer_scaling !=
1652                                 u->surface->scaling_quality.integer_scaling
1653                         ) {
1654                 update_flags->bits.scaling_change = 1;
1655
1656                 if ((u->scaling_info->dst_rect.width < u->surface->dst_rect.width
1657                         || u->scaling_info->dst_rect.height < u->surface->dst_rect.height)
1658                                 && (u->scaling_info->dst_rect.width < u->surface->src_rect.width
1659                                         || u->scaling_info->dst_rect.height < u->surface->src_rect.height))
1660                         /* Making dst rect smaller requires a bandwidth change */
1661                         update_flags->bits.bandwidth_change = 1;
1662         }
1663
1664         if (u->scaling_info->src_rect.width != u->surface->src_rect.width
1665                 || u->scaling_info->src_rect.height != u->surface->src_rect.height) {
1666
1667                 update_flags->bits.scaling_change = 1;
1668                 if (u->scaling_info->src_rect.width > u->surface->src_rect.width
1669                                 || u->scaling_info->src_rect.height > u->surface->src_rect.height)
1670                         /* Making src rect bigger requires a bandwidth change */
1671                         update_flags->bits.clock_change = 1;
1672         }
1673
1674         if (u->scaling_info->src_rect.x != u->surface->src_rect.x
1675                         || u->scaling_info->src_rect.y != u->surface->src_rect.y
1676                         || u->scaling_info->clip_rect.x != u->surface->clip_rect.x
1677                         || u->scaling_info->clip_rect.y != u->surface->clip_rect.y
1678                         || u->scaling_info->dst_rect.x != u->surface->dst_rect.x
1679                         || u->scaling_info->dst_rect.y != u->surface->dst_rect.y)
1680                 update_flags->bits.position_change = 1;
1681
1682         if (update_flags->bits.clock_change
1683                         || update_flags->bits.bandwidth_change
1684                         || update_flags->bits.scaling_change)
1685                 return UPDATE_TYPE_FULL;
1686
1687         if (update_flags->bits.position_change)
1688                 return UPDATE_TYPE_MED;
1689
1690         return UPDATE_TYPE_FAST;
1691 }
1692
1693 static enum surface_update_type det_surface_update(const struct dc *dc,
1694                 const struct dc_surface_update *u)
1695 {
1696         const struct dc_state *context = dc->current_state;
1697         enum surface_update_type type;
1698         enum surface_update_type overall_type = UPDATE_TYPE_FAST;
1699         union surface_update_flags *update_flags = &u->surface->update_flags;
1700
1701         if (u->flip_addr)
1702                 update_flags->bits.addr_update = 1;
1703
1704         if (!is_surface_in_context(context, u->surface) || u->surface->force_full_update) {
1705                 update_flags->raw = 0xFFFFFFFF;
1706                 return UPDATE_TYPE_FULL;
1707         }
1708
1709         update_flags->raw = 0; // Reset all flags
1710
1711         type = get_plane_info_update_type(u);
1712         elevate_update_type(&overall_type, type);
1713
1714         type = get_scaling_info_update_type(u);
1715         elevate_update_type(&overall_type, type);
1716
1717         if (u->flip_addr)
1718                 update_flags->bits.addr_update = 1;
1719
1720         if (u->in_transfer_func)
1721                 update_flags->bits.in_transfer_func_change = 1;
1722
1723         if (u->input_csc_color_matrix)
1724                 update_flags->bits.input_csc_change = 1;
1725
1726         if (u->coeff_reduction_factor)
1727                 update_flags->bits.coeff_reduction_change = 1;
1728
1729         if (u->gamut_remap_matrix)
1730                 update_flags->bits.gamut_remap_change = 1;
1731
1732         if (u->gamma) {
1733                 enum surface_pixel_format format = SURFACE_PIXEL_FORMAT_GRPH_BEGIN;
1734
1735                 if (u->plane_info)
1736                         format = u->plane_info->format;
1737                 else if (u->surface)
1738                         format = u->surface->format;
1739
1740                 if (dce_use_lut(format))
1741                         update_flags->bits.gamma_change = 1;
1742         }
1743
1744         if (u->hdr_mult.value)
1745                 if (u->hdr_mult.value != u->surface->hdr_mult.value) {
1746                         update_flags->bits.hdr_mult = 1;
1747                         elevate_update_type(&overall_type, UPDATE_TYPE_MED);
1748                 }
1749
1750         if (update_flags->bits.in_transfer_func_change) {
1751                 type = UPDATE_TYPE_MED;
1752                 elevate_update_type(&overall_type, type);
1753         }
1754
1755         if (update_flags->bits.input_csc_change
1756                         || update_flags->bits.coeff_reduction_change
1757                         || update_flags->bits.gamma_change
1758                         || update_flags->bits.gamut_remap_change) {
1759                 type = UPDATE_TYPE_FULL;
1760                 elevate_update_type(&overall_type, type);
1761         }
1762
1763         return overall_type;
1764 }
1765
1766 static enum surface_update_type check_update_surfaces_for_stream(
1767                 struct dc *dc,
1768                 struct dc_surface_update *updates,
1769                 int surface_count,
1770                 struct dc_stream_update *stream_update,
1771                 const struct dc_stream_status *stream_status)
1772 {
1773         int i;
1774         enum surface_update_type overall_type = UPDATE_TYPE_FAST;
1775
1776         if (stream_status == NULL || stream_status->plane_count != surface_count)
1777                 overall_type = UPDATE_TYPE_FULL;
1778
1779         /* some stream updates require passive update */
1780         if (stream_update) {
1781                 union stream_update_flags *su_flags = &stream_update->stream->update_flags;
1782
1783                 if ((stream_update->src.height != 0 && stream_update->src.width != 0) ||
1784                         (stream_update->dst.height != 0 && stream_update->dst.width != 0) ||
1785                         stream_update->integer_scaling_update)
1786                         su_flags->bits.scaling = 1;
1787
1788                 if (stream_update->out_transfer_func)
1789                         su_flags->bits.out_tf = 1;
1790
1791                 if (stream_update->abm_level)
1792                         su_flags->bits.abm_level = 1;
1793
1794                 if (stream_update->dpms_off)
1795                         su_flags->bits.dpms_off = 1;
1796
1797                 if (stream_update->gamut_remap)
1798                         su_flags->bits.gamut_remap = 1;
1799
1800                 if (stream_update->wb_update)
1801                         su_flags->bits.wb_update = 1;
1802
1803                 if (stream_update->dsc_config)
1804                         su_flags->bits.dsc_changed = 1;
1805
1806                 if (su_flags->raw != 0)
1807                         overall_type = UPDATE_TYPE_FULL;
1808
1809                 if (stream_update->output_csc_transform || stream_update->output_color_space)
1810                         su_flags->bits.out_csc = 1;
1811         }
1812
1813         for (i = 0 ; i < surface_count; i++) {
1814                 enum surface_update_type type =
1815                                 det_surface_update(dc, &updates[i]);
1816
1817                 elevate_update_type(&overall_type, type);
1818         }
1819
1820         return overall_type;
1821 }
1822
1823 /**
1824  * dc_check_update_surfaces_for_stream() - Determine update type (fast, med, or full)
1825  *
1826  * See :c:type:`enum surface_update_type <surface_update_type>` for explanation of update types
1827  */
1828 enum surface_update_type dc_check_update_surfaces_for_stream(
1829                 struct dc *dc,
1830                 struct dc_surface_update *updates,
1831                 int surface_count,
1832                 struct dc_stream_update *stream_update,
1833                 const struct dc_stream_status *stream_status)
1834 {
1835         int i;
1836         enum surface_update_type type;
1837
1838         if (stream_update)
1839                 stream_update->stream->update_flags.raw = 0;
1840         for (i = 0; i < surface_count; i++)
1841                 updates[i].surface->update_flags.raw = 0;
1842
1843         type = check_update_surfaces_for_stream(dc, updates, surface_count, stream_update, stream_status);
1844         if (type == UPDATE_TYPE_FULL) {
1845                 if (stream_update) {
1846                         uint32_t dsc_changed = stream_update->stream->update_flags.bits.dsc_changed;
1847                         stream_update->stream->update_flags.raw = 0xFFFFFFFF;
1848                         stream_update->stream->update_flags.bits.dsc_changed = dsc_changed;
1849                 }
1850                 for (i = 0; i < surface_count; i++)
1851                         updates[i].surface->update_flags.raw = 0xFFFFFFFF;
1852         }
1853
1854         if (type == UPDATE_TYPE_FAST) {
1855                 // If there's an available clock comparator, we use that.
1856                 if (dc->clk_mgr->funcs->are_clock_states_equal) {
1857                         if (!dc->clk_mgr->funcs->are_clock_states_equal(&dc->clk_mgr->clks, &dc->current_state->bw_ctx.bw.dcn.clk))
1858                                 dc->optimized_required = true;
1859                 // Else we fallback to mem compare.
1860                 } else if (memcmp(&dc->current_state->bw_ctx.bw.dcn.clk, &dc->clk_mgr->clks, offsetof(struct dc_clocks, prev_p_state_change_support)) != 0) {
1861                         dc->optimized_required = true;
1862                 } else if (dc->wm_optimized_required)
1863                         dc->optimized_required = true;
1864         }
1865
1866         return type;
1867 }
1868
1869 static struct dc_stream_status *stream_get_status(
1870         struct dc_state *ctx,
1871         struct dc_stream_state *stream)
1872 {
1873         uint8_t i;
1874
1875         for (i = 0; i < ctx->stream_count; i++) {
1876                 if (stream == ctx->streams[i]) {
1877                         return &ctx->stream_status[i];
1878                 }
1879         }
1880
1881         return NULL;
1882 }
1883
1884 static const enum surface_update_type update_surface_trace_level = UPDATE_TYPE_FULL;
1885
1886 static void copy_surface_update_to_plane(
1887                 struct dc_plane_state *surface,
1888                 struct dc_surface_update *srf_update)
1889 {
1890         if (srf_update->flip_addr) {
1891                 surface->address = srf_update->flip_addr->address;
1892                 surface->flip_immediate =
1893                         srf_update->flip_addr->flip_immediate;
1894                 surface->time.time_elapsed_in_us[surface->time.index] =
1895                         srf_update->flip_addr->flip_timestamp_in_us -
1896                                 surface->time.prev_update_time_in_us;
1897                 surface->time.prev_update_time_in_us =
1898                         srf_update->flip_addr->flip_timestamp_in_us;
1899                 surface->time.index++;
1900                 if (surface->time.index >= DC_PLANE_UPDATE_TIMES_MAX)
1901                         surface->time.index = 0;
1902
1903                 surface->triplebuffer_flips = srf_update->flip_addr->triplebuffer_flips;
1904         }
1905
1906         if (srf_update->scaling_info) {
1907                 surface->scaling_quality =
1908                                 srf_update->scaling_info->scaling_quality;
1909                 surface->dst_rect =
1910                                 srf_update->scaling_info->dst_rect;
1911                 surface->src_rect =
1912                                 srf_update->scaling_info->src_rect;
1913                 surface->clip_rect =
1914                                 srf_update->scaling_info->clip_rect;
1915         }
1916
1917         if (srf_update->plane_info) {
1918                 surface->color_space =
1919                                 srf_update->plane_info->color_space;
1920                 surface->format =
1921                                 srf_update->plane_info->format;
1922                 surface->plane_size =
1923                                 srf_update->plane_info->plane_size;
1924                 surface->rotation =
1925                                 srf_update->plane_info->rotation;
1926                 surface->horizontal_mirror =
1927                                 srf_update->plane_info->horizontal_mirror;
1928                 surface->stereo_format =
1929                                 srf_update->plane_info->stereo_format;
1930                 surface->tiling_info =
1931                                 srf_update->plane_info->tiling_info;
1932                 surface->visible =
1933                                 srf_update->plane_info->visible;
1934                 surface->per_pixel_alpha =
1935                                 srf_update->plane_info->per_pixel_alpha;
1936                 surface->global_alpha =
1937                                 srf_update->plane_info->global_alpha;
1938                 surface->global_alpha_value =
1939                                 srf_update->plane_info->global_alpha_value;
1940                 surface->dcc =
1941                                 srf_update->plane_info->dcc;
1942                 surface->layer_index =
1943                                 srf_update->plane_info->layer_index;
1944         }
1945
1946         if (srf_update->gamma &&
1947                         (surface->gamma_correction !=
1948                                         srf_update->gamma)) {
1949                 memcpy(&surface->gamma_correction->entries,
1950                         &srf_update->gamma->entries,
1951                         sizeof(struct dc_gamma_entries));
1952                 surface->gamma_correction->is_identity =
1953                         srf_update->gamma->is_identity;
1954                 surface->gamma_correction->num_entries =
1955                         srf_update->gamma->num_entries;
1956                 surface->gamma_correction->type =
1957                         srf_update->gamma->type;
1958         }
1959
1960         if (srf_update->in_transfer_func &&
1961                         (surface->in_transfer_func !=
1962                                 srf_update->in_transfer_func)) {
1963                 surface->in_transfer_func->sdr_ref_white_level =
1964                         srf_update->in_transfer_func->sdr_ref_white_level;
1965                 surface->in_transfer_func->tf =
1966                         srf_update->in_transfer_func->tf;
1967                 surface->in_transfer_func->type =
1968                         srf_update->in_transfer_func->type;
1969                 memcpy(&surface->in_transfer_func->tf_pts,
1970                         &srf_update->in_transfer_func->tf_pts,
1971                         sizeof(struct dc_transfer_func_distributed_points));
1972         }
1973
1974         if (srf_update->func_shaper &&
1975                         (surface->in_shaper_func !=
1976                         srf_update->func_shaper))
1977                 memcpy(surface->in_shaper_func, srf_update->func_shaper,
1978                 sizeof(*surface->in_shaper_func));
1979
1980         if (srf_update->lut3d_func &&
1981                         (surface->lut3d_func !=
1982                         srf_update->lut3d_func))
1983                 memcpy(surface->lut3d_func, srf_update->lut3d_func,
1984                 sizeof(*surface->lut3d_func));
1985
1986         if (srf_update->hdr_mult.value)
1987                 surface->hdr_mult =
1988                                 srf_update->hdr_mult;
1989
1990         if (srf_update->blend_tf &&
1991                         (surface->blend_tf !=
1992                         srf_update->blend_tf))
1993                 memcpy(surface->blend_tf, srf_update->blend_tf,
1994                 sizeof(*surface->blend_tf));
1995
1996         if (srf_update->input_csc_color_matrix)
1997                 surface->input_csc_color_matrix =
1998                         *srf_update->input_csc_color_matrix;
1999
2000         if (srf_update->coeff_reduction_factor)
2001                 surface->coeff_reduction_factor =
2002                         *srf_update->coeff_reduction_factor;
2003
2004         if (srf_update->gamut_remap_matrix)
2005                 surface->gamut_remap_matrix =
2006                         *srf_update->gamut_remap_matrix;
2007 }
2008
2009 static void copy_stream_update_to_stream(struct dc *dc,
2010                                          struct dc_state *context,
2011                                          struct dc_stream_state *stream,
2012                                          struct dc_stream_update *update)
2013 {
2014         struct dc_context *dc_ctx = dc->ctx;
2015
2016         if (update == NULL || stream == NULL)
2017                 return;
2018
2019         if (update->src.height && update->src.width)
2020                 stream->src = update->src;
2021
2022         if (update->dst.height && update->dst.width)
2023                 stream->dst = update->dst;
2024
2025         if (update->out_transfer_func &&
2026             stream->out_transfer_func != update->out_transfer_func) {
2027                 stream->out_transfer_func->sdr_ref_white_level =
2028                         update->out_transfer_func->sdr_ref_white_level;
2029                 stream->out_transfer_func->tf = update->out_transfer_func->tf;
2030                 stream->out_transfer_func->type =
2031                         update->out_transfer_func->type;
2032                 memcpy(&stream->out_transfer_func->tf_pts,
2033                        &update->out_transfer_func->tf_pts,
2034                        sizeof(struct dc_transfer_func_distributed_points));
2035         }
2036
2037         if (update->hdr_static_metadata)
2038                 stream->hdr_static_metadata = *update->hdr_static_metadata;
2039
2040         if (update->abm_level)
2041                 stream->abm_level = *update->abm_level;
2042
2043         if (update->periodic_interrupt0)
2044                 stream->periodic_interrupt0 = *update->periodic_interrupt0;
2045
2046         if (update->periodic_interrupt1)
2047                 stream->periodic_interrupt1 = *update->periodic_interrupt1;
2048
2049         if (update->gamut_remap)
2050                 stream->gamut_remap_matrix = *update->gamut_remap;
2051
2052         /* Note: this being updated after mode set is currently not a use case
2053          * however if it arises OCSC would need to be reprogrammed at the
2054          * minimum
2055          */
2056         if (update->output_color_space)
2057                 stream->output_color_space = *update->output_color_space;
2058
2059         if (update->output_csc_transform)
2060                 stream->csc_color_matrix = *update->output_csc_transform;
2061
2062         if (update->vrr_infopacket)
2063                 stream->vrr_infopacket = *update->vrr_infopacket;
2064
2065         if (update->dpms_off)
2066                 stream->dpms_off = *update->dpms_off;
2067
2068         if (update->vsc_infopacket)
2069                 stream->vsc_infopacket = *update->vsc_infopacket;
2070
2071         if (update->vsp_infopacket)
2072                 stream->vsp_infopacket = *update->vsp_infopacket;
2073
2074         if (update->dither_option)
2075                 stream->dither_option = *update->dither_option;
2076         /* update current stream with writeback info */
2077         if (update->wb_update) {
2078                 int i;
2079
2080                 stream->num_wb_info = update->wb_update->num_wb_info;
2081                 ASSERT(stream->num_wb_info <= MAX_DWB_PIPES);
2082                 for (i = 0; i < stream->num_wb_info; i++)
2083                         stream->writeback_info[i] =
2084                                 update->wb_update->writeback_info[i];
2085         }
2086         if (update->dsc_config) {
2087                 struct dc_dsc_config old_dsc_cfg = stream->timing.dsc_cfg;
2088                 uint32_t old_dsc_enabled = stream->timing.flags.DSC;
2089                 uint32_t enable_dsc = (update->dsc_config->num_slices_h != 0 &&
2090                                        update->dsc_config->num_slices_v != 0);
2091
2092                 /* Use temporarry context for validating new DSC config */
2093                 struct dc_state *dsc_validate_context = dc_create_state(dc);
2094
2095                 if (dsc_validate_context) {
2096                         dc_resource_state_copy_construct(dc->current_state, dsc_validate_context);
2097
2098                         stream->timing.dsc_cfg = *update->dsc_config;
2099                         stream->timing.flags.DSC = enable_dsc;
2100                         if (!dc->res_pool->funcs->validate_bandwidth(dc, dsc_validate_context, true)) {
2101                                 stream->timing.dsc_cfg = old_dsc_cfg;
2102                                 stream->timing.flags.DSC = old_dsc_enabled;
2103                                 update->dsc_config = NULL;
2104                         }
2105
2106                         dc_release_state(dsc_validate_context);
2107                 } else {
2108                         DC_ERROR("Failed to allocate new validate context for DSC change\n");
2109                         update->dsc_config = NULL;
2110                 }
2111         }
2112 }
2113
2114 static void commit_planes_do_stream_update(struct dc *dc,
2115                 struct dc_stream_state *stream,
2116                 struct dc_stream_update *stream_update,
2117                 enum surface_update_type update_type,
2118                 struct dc_state *context)
2119 {
2120         int j;
2121         bool should_program_abm;
2122
2123         // Stream updates
2124         for (j = 0; j < dc->res_pool->pipe_count; j++) {
2125                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2126
2127                 if (!pipe_ctx->top_pipe &&  !pipe_ctx->prev_odm_pipe && pipe_ctx->stream == stream) {
2128
2129                         if (stream_update->periodic_interrupt0 &&
2130                                         dc->hwss.setup_periodic_interrupt)
2131                                 dc->hwss.setup_periodic_interrupt(dc, pipe_ctx, VLINE0);
2132
2133                         if (stream_update->periodic_interrupt1 &&
2134                                         dc->hwss.setup_periodic_interrupt)
2135                                 dc->hwss.setup_periodic_interrupt(dc, pipe_ctx, VLINE1);
2136
2137                         if ((stream_update->hdr_static_metadata && !stream->use_dynamic_meta) ||
2138                                         stream_update->vrr_infopacket ||
2139                                         stream_update->vsc_infopacket ||
2140                                         stream_update->vsp_infopacket) {
2141                                 resource_build_info_frame(pipe_ctx);
2142                                 dc->hwss.update_info_frame(pipe_ctx);
2143                         }
2144
2145                         if (stream_update->hdr_static_metadata &&
2146                                         stream->use_dynamic_meta &&
2147                                         dc->hwss.set_dmdata_attributes &&
2148                                         pipe_ctx->stream->dmdata_address.quad_part != 0)
2149                                 dc->hwss.set_dmdata_attributes(pipe_ctx);
2150
2151                         if (stream_update->gamut_remap)
2152                                 dc_stream_set_gamut_remap(dc, stream);
2153
2154                         if (stream_update->output_csc_transform)
2155                                 dc_stream_program_csc_matrix(dc, stream);
2156
2157                         if (stream_update->dither_option) {
2158                                 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
2159                                 resource_build_bit_depth_reduction_params(pipe_ctx->stream,
2160                                                                         &pipe_ctx->stream->bit_depth_params);
2161                                 pipe_ctx->stream_res.opp->funcs->opp_program_fmt(pipe_ctx->stream_res.opp,
2162                                                 &stream->bit_depth_params,
2163                                                 &stream->clamping);
2164                                 while (odm_pipe) {
2165                                         odm_pipe->stream_res.opp->funcs->opp_program_fmt(odm_pipe->stream_res.opp,
2166                                                         &stream->bit_depth_params,
2167                                                         &stream->clamping);
2168                                         odm_pipe = odm_pipe->next_odm_pipe;
2169                                 }
2170                         }
2171
2172                         /* Full fe update*/
2173                         if (update_type == UPDATE_TYPE_FAST)
2174                                 continue;
2175
2176                         if (stream_update->dsc_config)
2177                                 dp_update_dsc_config(pipe_ctx);
2178
2179                         if (stream_update->dpms_off) {
2180                                 if (*stream_update->dpms_off) {
2181                                         core_link_disable_stream(pipe_ctx);
2182                                         /* for dpms, keep acquired resources*/
2183                                         if (pipe_ctx->stream_res.audio && !dc->debug.az_endpoint_mute_only)
2184                                                 pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);
2185
2186                                         dc->hwss.optimize_bandwidth(dc, dc->current_state);
2187                                 } else {
2188                                         if (dc->optimize_seamless_boot_streams == 0)
2189                                                 dc->hwss.prepare_bandwidth(dc, dc->current_state);
2190
2191                                         core_link_enable_stream(dc->current_state, pipe_ctx);
2192                                 }
2193                         }
2194
2195                         if (stream_update->abm_level && pipe_ctx->stream_res.abm) {
2196                                 should_program_abm = true;
2197
2198                                 // if otg funcs defined check if blanked before programming
2199                                 if (pipe_ctx->stream_res.tg->funcs->is_blanked)
2200                                         if (pipe_ctx->stream_res.tg->funcs->is_blanked(pipe_ctx->stream_res.tg))
2201                                                 should_program_abm = false;
2202
2203                                 if (should_program_abm) {
2204                                         if (*stream_update->abm_level == ABM_LEVEL_IMMEDIATE_DISABLE) {
2205                                                 pipe_ctx->stream_res.abm->funcs->set_abm_immediate_disable(pipe_ctx->stream_res.abm);
2206                                         } else {
2207                                                 pipe_ctx->stream_res.abm->funcs->set_abm_level(
2208                                                         pipe_ctx->stream_res.abm, stream->abm_level);
2209                                         }
2210                                 }
2211                         }
2212                 }
2213         }
2214 }
2215
2216 static void commit_planes_for_stream(struct dc *dc,
2217                 struct dc_surface_update *srf_updates,
2218                 int surface_count,
2219                 struct dc_stream_state *stream,
2220                 struct dc_stream_update *stream_update,
2221                 enum surface_update_type update_type,
2222                 struct dc_state *context)
2223 {
2224         int i, j;
2225         struct pipe_ctx *top_pipe_to_program = NULL;
2226
2227         if (dc->optimize_seamless_boot_streams > 0 && surface_count > 0) {
2228                 /* Optimize seamless boot flag keeps clocks and watermarks high until
2229                  * first flip. After first flip, optimization is required to lower
2230                  * bandwidth. Important to note that it is expected UEFI will
2231                  * only light up a single display on POST, therefore we only expect
2232                  * one stream with seamless boot flag set.
2233                  */
2234                 if (stream->apply_seamless_boot_optimization) {
2235                         stream->apply_seamless_boot_optimization = false;
2236                         dc->optimize_seamless_boot_streams--;
2237
2238                         if (dc->optimize_seamless_boot_streams == 0)
2239                                 dc->optimized_required = true;
2240                 }
2241         }
2242
2243         if (update_type == UPDATE_TYPE_FULL && dc->optimize_seamless_boot_streams == 0) {
2244                 dc->hwss.prepare_bandwidth(dc, context);
2245                 context_clock_trace(dc, context);
2246         }
2247
2248         for (j = 0; j < dc->res_pool->pipe_count; j++) {
2249                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2250
2251                 if (!pipe_ctx->top_pipe &&
2252                         !pipe_ctx->prev_odm_pipe &&
2253                         pipe_ctx->stream &&
2254                         pipe_ctx->stream == stream) {
2255                         top_pipe_to_program = pipe_ctx;
2256                 }
2257         }
2258
2259         if ((update_type != UPDATE_TYPE_FAST) && stream->update_flags.bits.dsc_changed)
2260                 if (top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable)
2261                         top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable(
2262                                         top_pipe_to_program->stream_res.tg);
2263
2264         if ((update_type != UPDATE_TYPE_FAST) && dc->hwss.interdependent_update_lock)
2265                 dc->hwss.interdependent_update_lock(dc, context, true);
2266         else
2267                 /* Lock the top pipe while updating plane addrs, since freesync requires
2268                  *  plane addr update event triggers to be synchronized.
2269                  *  top_pipe_to_program is expected to never be NULL
2270                  */
2271                 dc->hwss.pipe_control_lock(dc, top_pipe_to_program, true);
2272
2273
2274         // Stream updates
2275         if (stream_update)
2276                 commit_planes_do_stream_update(dc, stream, stream_update, update_type, context);
2277
2278         if (surface_count == 0) {
2279                 /*
2280                  * In case of turning off screen, no need to program front end a second time.
2281                  * just return after program blank.
2282                  */
2283                 if (dc->hwss.apply_ctx_for_surface)
2284                         dc->hwss.apply_ctx_for_surface(dc, stream, 0, context);
2285                 if (dc->hwss.program_front_end_for_ctx)
2286                         dc->hwss.program_front_end_for_ctx(dc, context);
2287
2288                 if ((update_type != UPDATE_TYPE_FAST) && dc->hwss.interdependent_update_lock)
2289                         dc->hwss.interdependent_update_lock(dc, context, false);
2290                 else
2291                         dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false);
2292
2293                 dc->hwss.post_unlock_program_front_end(dc, context);
2294                 return;
2295         }
2296
2297         if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
2298                 for (i = 0; i < surface_count; i++) {
2299                         struct dc_plane_state *plane_state = srf_updates[i].surface;
2300                         /*set logical flag for lock/unlock use*/
2301                         for (j = 0; j < dc->res_pool->pipe_count; j++) {
2302                                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2303                                 if (!pipe_ctx->plane_state)
2304                                         continue;
2305                                 if (pipe_ctx->plane_state != plane_state)
2306                                         continue;
2307                                 plane_state->triplebuffer_flips = false;
2308                                 if (update_type == UPDATE_TYPE_FAST &&
2309                                         dc->hwss.program_triplebuffer != NULL &&
2310                                         !plane_state->flip_immediate &&
2311                                         !dc->debug.disable_tri_buf) {
2312                                                 /*triple buffer for VUpdate  only*/
2313                                                 plane_state->triplebuffer_flips = true;
2314                                 }
2315                         }
2316                 }
2317         }
2318
2319         // Update Type FULL, Surface updates
2320         for (j = 0; j < dc->res_pool->pipe_count; j++) {
2321                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2322
2323                 if (!pipe_ctx->top_pipe &&
2324                         !pipe_ctx->prev_odm_pipe &&
2325                         pipe_ctx->stream &&
2326                         pipe_ctx->stream == stream) {
2327                         struct dc_stream_status *stream_status = NULL;
2328
2329                         if (!pipe_ctx->plane_state)
2330                                 continue;
2331
2332                         /* Full fe update*/
2333                         if (update_type == UPDATE_TYPE_FAST)
2334                                 continue;
2335
2336                         ASSERT(!pipe_ctx->plane_state->triplebuffer_flips);
2337
2338                         if (dc->hwss.program_triplebuffer != NULL &&
2339                                 !dc->debug.disable_tri_buf) {
2340                                 /*turn off triple buffer for full update*/
2341                                 dc->hwss.program_triplebuffer(
2342                                         dc, pipe_ctx, pipe_ctx->plane_state->triplebuffer_flips);
2343                         }
2344                         stream_status =
2345                                 stream_get_status(context, pipe_ctx->stream);
2346
2347                         if (dc->hwss.apply_ctx_for_surface)
2348                                 dc->hwss.apply_ctx_for_surface(
2349                                         dc, pipe_ctx->stream, stream_status->plane_count, context);
2350                 }
2351         }
2352         if (dc->hwss.program_front_end_for_ctx && update_type != UPDATE_TYPE_FAST) {
2353                 dc->hwss.program_front_end_for_ctx(dc, context);
2354 #ifdef CONFIG_DRM_AMD_DC_DCN
2355                 if (dc->debug.validate_dml_output) {
2356                         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2357                                 struct pipe_ctx cur_pipe = context->res_ctx.pipe_ctx[i];
2358                                 if (cur_pipe.stream == NULL)
2359                                         continue;
2360
2361                                 cur_pipe.plane_res.hubp->funcs->validate_dml_output(
2362                                                 cur_pipe.plane_res.hubp, dc->ctx,
2363                                                 &context->res_ctx.pipe_ctx[i].rq_regs,
2364                                                 &context->res_ctx.pipe_ctx[i].dlg_regs,
2365                                                 &context->res_ctx.pipe_ctx[i].ttu_regs);
2366                         }
2367                 }
2368 #endif
2369         }
2370
2371         // Update Type FAST, Surface updates
2372         if (update_type == UPDATE_TYPE_FAST) {
2373                 if (dc->hwss.set_flip_control_gsl)
2374                         for (i = 0; i < surface_count; i++) {
2375                                 struct dc_plane_state *plane_state = srf_updates[i].surface;
2376
2377                                 for (j = 0; j < dc->res_pool->pipe_count; j++) {
2378                                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2379
2380                                         if (pipe_ctx->stream != stream)
2381                                                 continue;
2382
2383                                         if (pipe_ctx->plane_state != plane_state)
2384                                                 continue;
2385
2386                                         // GSL has to be used for flip immediate
2387                                         dc->hwss.set_flip_control_gsl(pipe_ctx,
2388                                                         plane_state->flip_immediate);
2389                                 }
2390                         }
2391                 /* Perform requested Updates */
2392                 for (i = 0; i < surface_count; i++) {
2393                         struct dc_plane_state *plane_state = srf_updates[i].surface;
2394
2395                         for (j = 0; j < dc->res_pool->pipe_count; j++) {
2396                                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2397
2398                                 if (pipe_ctx->stream != stream)
2399                                         continue;
2400
2401                                 if (pipe_ctx->plane_state != plane_state)
2402                                         continue;
2403                                 /*program triple buffer after lock based on flip type*/
2404                                 if (dc->hwss.program_triplebuffer != NULL &&
2405                                         !dc->debug.disable_tri_buf) {
2406                                         /*only enable triplebuffer for  fast_update*/
2407                                         dc->hwss.program_triplebuffer(
2408                                                 dc, pipe_ctx, plane_state->triplebuffer_flips);
2409                                 }
2410                                 if (srf_updates[i].flip_addr)
2411                                         dc->hwss.update_plane_addr(dc, pipe_ctx);
2412                         }
2413                 }
2414         }
2415
2416         if ((update_type != UPDATE_TYPE_FAST) && dc->hwss.interdependent_update_lock)
2417                 dc->hwss.interdependent_update_lock(dc, context, false);
2418         else
2419                 dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false);
2420
2421         if ((update_type != UPDATE_TYPE_FAST) && stream->update_flags.bits.dsc_changed)
2422                 if (top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable) {
2423                         top_pipe_to_program->stream_res.tg->funcs->wait_for_state(
2424                                         top_pipe_to_program->stream_res.tg,
2425                                         CRTC_STATE_VACTIVE);
2426                         top_pipe_to_program->stream_res.tg->funcs->wait_for_state(
2427                                         top_pipe_to_program->stream_res.tg,
2428                                         CRTC_STATE_VBLANK);
2429                         top_pipe_to_program->stream_res.tg->funcs->wait_for_state(
2430                                         top_pipe_to_program->stream_res.tg,
2431                                         CRTC_STATE_VACTIVE);
2432                         top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_disable(
2433                                         top_pipe_to_program->stream_res.tg);
2434                 }
2435
2436         if (update_type != UPDATE_TYPE_FAST)
2437                 dc->hwss.post_unlock_program_front_end(dc, context);
2438
2439         // Fire manual trigger only when bottom plane is flipped
2440         for (j = 0; j < dc->res_pool->pipe_count; j++) {
2441                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2442
2443                 if (pipe_ctx->bottom_pipe ||
2444                                 !pipe_ctx->stream ||
2445                                 pipe_ctx->stream != stream ||
2446                                 !pipe_ctx->plane_state->update_flags.bits.addr_update)
2447                         continue;
2448
2449                 if (pipe_ctx->stream_res.tg->funcs->program_manual_trigger)
2450                         pipe_ctx->stream_res.tg->funcs->program_manual_trigger(pipe_ctx->stream_res.tg);
2451         }
2452 }
2453
2454 void dc_commit_updates_for_stream(struct dc *dc,
2455                 struct dc_surface_update *srf_updates,
2456                 int surface_count,
2457                 struct dc_stream_state *stream,
2458                 struct dc_stream_update *stream_update,
2459                 struct dc_state *state)
2460 {
2461         const struct dc_stream_status *stream_status;
2462         enum surface_update_type update_type;
2463         struct dc_state *context;
2464         struct dc_context *dc_ctx = dc->ctx;
2465         int i;
2466
2467         stream_status = dc_stream_get_status(stream);
2468         context = dc->current_state;
2469
2470         update_type = dc_check_update_surfaces_for_stream(
2471                                 dc, srf_updates, surface_count, stream_update, stream_status);
2472
2473         if (update_type >= update_surface_trace_level)
2474                 update_surface_trace(dc, srf_updates, surface_count);
2475
2476
2477         if (update_type >= UPDATE_TYPE_FULL) {
2478
2479                 /* initialize scratch memory for building context */
2480                 context = dc_create_state(dc);
2481                 if (context == NULL) {
2482                         DC_ERROR("Failed to allocate new validate context!\n");
2483                         return;
2484                 }
2485
2486                 dc_resource_state_copy_construct(state, context);
2487
2488                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2489                         struct pipe_ctx *new_pipe = &context->res_ctx.pipe_ctx[i];
2490                         struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
2491
2492                         if (new_pipe->plane_state && new_pipe->plane_state != old_pipe->plane_state)
2493                                 new_pipe->plane_state->force_full_update = true;
2494                 }
2495         }
2496
2497
2498         for (i = 0; i < surface_count; i++) {
2499                 struct dc_plane_state *surface = srf_updates[i].surface;
2500
2501                 copy_surface_update_to_plane(surface, &srf_updates[i]);
2502
2503         }
2504
2505         copy_stream_update_to_stream(dc, context, stream, stream_update);
2506
2507         commit_planes_for_stream(
2508                                 dc,
2509                                 srf_updates,
2510                                 surface_count,
2511                                 stream,
2512                                 stream_update,
2513                                 update_type,
2514                                 context);
2515         /*update current_State*/
2516         if (dc->current_state != context) {
2517
2518                 struct dc_state *old = dc->current_state;
2519
2520                 dc->current_state = context;
2521                 dc_release_state(old);
2522
2523                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2524                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2525
2526                         if (pipe_ctx->plane_state && pipe_ctx->stream == stream)
2527                                 pipe_ctx->plane_state->force_full_update = false;
2528                 }
2529         }
2530         /*let's use current_state to update watermark etc*/
2531         if (update_type >= UPDATE_TYPE_FULL)
2532                 dc_post_update_surfaces_to_stream(dc);
2533
2534         return;
2535
2536 }
2537
2538 uint8_t dc_get_current_stream_count(struct dc *dc)
2539 {
2540         return dc->current_state->stream_count;
2541 }
2542
2543 struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i)
2544 {
2545         if (i < dc->current_state->stream_count)
2546                 return dc->current_state->streams[i];
2547         return NULL;
2548 }
2549
2550 enum dc_irq_source dc_interrupt_to_irq_source(
2551                 struct dc *dc,
2552                 uint32_t src_id,
2553                 uint32_t ext_id)
2554 {
2555         return dal_irq_service_to_irq_source(dc->res_pool->irqs, src_id, ext_id);
2556 }
2557
2558 /**
2559  * dc_interrupt_set() - Enable/disable an AMD hw interrupt source
2560  */
2561 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable)
2562 {
2563
2564         if (dc == NULL)
2565                 return false;
2566
2567         return dal_irq_service_set(dc->res_pool->irqs, src, enable);
2568 }
2569
2570 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src)
2571 {
2572         dal_irq_service_ack(dc->res_pool->irqs, src);
2573 }
2574
2575 void dc_set_power_state(
2576         struct dc *dc,
2577         enum dc_acpi_cm_power_state power_state)
2578 {
2579         struct kref refcount;
2580         struct display_mode_lib *dml;
2581
2582         switch (power_state) {
2583         case DC_ACPI_CM_POWER_STATE_D0:
2584                 dc_resource_state_construct(dc, dc->current_state);
2585
2586                 if (dc->ctx->dmub_srv)
2587                         dc_dmub_srv_wait_phy_init(dc->ctx->dmub_srv);
2588
2589                 dc->hwss.init_hw(dc);
2590
2591                 if (dc->hwss.init_sys_ctx != NULL &&
2592                         dc->vm_pa_config.valid) {
2593                         dc->hwss.init_sys_ctx(dc->hwseq, dc, &dc->vm_pa_config);
2594                 }
2595
2596                 break;
2597         default:
2598                 ASSERT(dc->current_state->stream_count == 0);
2599                 /* Zero out the current context so that on resume we start with
2600                  * clean state, and dc hw programming optimizations will not
2601                  * cause any trouble.
2602                  */
2603                 dml = kzalloc(sizeof(struct display_mode_lib),
2604                                 GFP_KERNEL);
2605
2606                 ASSERT(dml);
2607                 if (!dml)
2608                         return;
2609
2610                 /* Preserve refcount */
2611                 refcount = dc->current_state->refcount;
2612                 /* Preserve display mode lib */
2613                 memcpy(dml, &dc->current_state->bw_ctx.dml, sizeof(struct display_mode_lib));
2614
2615                 dc_resource_state_destruct(dc->current_state);
2616                 memset(dc->current_state, 0,
2617                                 sizeof(*dc->current_state));
2618
2619                 dc->current_state->refcount = refcount;
2620                 dc->current_state->bw_ctx.dml = *dml;
2621
2622                 kfree(dml);
2623
2624                 break;
2625         }
2626 }
2627
2628 void dc_resume(struct dc *dc)
2629 {
2630
2631         uint32_t i;
2632
2633         for (i = 0; i < dc->link_count; i++)
2634                 core_link_resume(dc->links[i]);
2635 }
2636
2637 unsigned int dc_get_current_backlight_pwm(struct dc *dc)
2638 {
2639         struct abm *abm = dc->res_pool->abm;
2640
2641         if (abm)
2642                 return abm->funcs->get_current_backlight(abm);
2643
2644         return 0;
2645 }
2646
2647 unsigned int dc_get_target_backlight_pwm(struct dc *dc)
2648 {
2649         struct abm *abm = dc->res_pool->abm;
2650
2651         if (abm)
2652                 return abm->funcs->get_target_backlight(abm);
2653
2654         return 0;
2655 }
2656
2657 bool dc_is_dmcu_initialized(struct dc *dc)
2658 {
2659         struct dmcu *dmcu = dc->res_pool->dmcu;
2660
2661         if (dmcu)
2662                 return dmcu->funcs->is_dmcu_initialized(dmcu);
2663         return false;
2664 }
2665
2666 bool dc_submit_i2c(
2667                 struct dc *dc,
2668                 uint32_t link_index,
2669                 struct i2c_command *cmd)
2670 {
2671
2672         struct dc_link *link = dc->links[link_index];
2673         struct ddc_service *ddc = link->ddc;
2674         return dce_i2c_submit_command(
2675                 dc->res_pool,
2676                 ddc->ddc_pin,
2677                 cmd);
2678 }
2679
2680 bool dc_submit_i2c_oem(
2681                 struct dc *dc,
2682                 struct i2c_command *cmd)
2683 {
2684         struct ddc_service *ddc = dc->res_pool->oem_device;
2685         return dce_i2c_submit_command(
2686                 dc->res_pool,
2687                 ddc->ddc_pin,
2688                 cmd);
2689 }
2690
2691 static bool link_add_remote_sink_helper(struct dc_link *dc_link, struct dc_sink *sink)
2692 {
2693         if (dc_link->sink_count >= MAX_SINKS_PER_LINK) {
2694                 BREAK_TO_DEBUGGER();
2695                 return false;
2696         }
2697
2698         dc_sink_retain(sink);
2699
2700         dc_link->remote_sinks[dc_link->sink_count] = sink;
2701         dc_link->sink_count++;
2702
2703         return true;
2704 }
2705
2706 /**
2707  * dc_link_add_remote_sink() - Create a sink and attach it to an existing link
2708  *
2709  * EDID length is in bytes
2710  */
2711 struct dc_sink *dc_link_add_remote_sink(
2712                 struct dc_link *link,
2713                 const uint8_t *edid,
2714                 int len,
2715                 struct dc_sink_init_data *init_data)
2716 {
2717         struct dc_sink *dc_sink;
2718         enum dc_edid_status edid_status;
2719
2720         if (len > DC_MAX_EDID_BUFFER_SIZE) {
2721                 dm_error("Max EDID buffer size breached!\n");
2722                 return NULL;
2723         }
2724
2725         if (!init_data) {
2726                 BREAK_TO_DEBUGGER();
2727                 return NULL;
2728         }
2729
2730         if (!init_data->link) {
2731                 BREAK_TO_DEBUGGER();
2732                 return NULL;
2733         }
2734
2735         dc_sink = dc_sink_create(init_data);
2736
2737         if (!dc_sink)
2738                 return NULL;
2739
2740         memmove(dc_sink->dc_edid.raw_edid, edid, len);
2741         dc_sink->dc_edid.length = len;
2742
2743         if (!link_add_remote_sink_helper(
2744                         link,
2745                         dc_sink))
2746                 goto fail_add_sink;
2747
2748         edid_status = dm_helpers_parse_edid_caps(
2749                         link->ctx,
2750                         &dc_sink->dc_edid,
2751                         &dc_sink->edid_caps);
2752
2753         /*
2754          * Treat device as no EDID device if EDID
2755          * parsing fails
2756          */
2757         if (edid_status != EDID_OK) {
2758                 dc_sink->dc_edid.length = 0;
2759                 dm_error("Bad EDID, status%d!\n", edid_status);
2760         }
2761
2762         return dc_sink;
2763
2764 fail_add_sink:
2765         dc_sink_release(dc_sink);
2766         return NULL;
2767 }
2768
2769 /**
2770  * dc_link_remove_remote_sink() - Remove a remote sink from a dc_link
2771  *
2772  * Note that this just removes the struct dc_sink - it doesn't
2773  * program hardware or alter other members of dc_link
2774  */
2775 void dc_link_remove_remote_sink(struct dc_link *link, struct dc_sink *sink)
2776 {
2777         int i;
2778
2779         if (!link->sink_count) {
2780                 BREAK_TO_DEBUGGER();
2781                 return;
2782         }
2783
2784         for (i = 0; i < link->sink_count; i++) {
2785                 if (link->remote_sinks[i] == sink) {
2786                         dc_sink_release(sink);
2787                         link->remote_sinks[i] = NULL;
2788
2789                         /* shrink array to remove empty place */
2790                         while (i < link->sink_count - 1) {
2791                                 link->remote_sinks[i] = link->remote_sinks[i+1];
2792                                 i++;
2793                         }
2794                         link->remote_sinks[i] = NULL;
2795                         link->sink_count--;
2796                         return;
2797                 }
2798         }
2799 }
2800
2801 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info)
2802 {
2803         info->displayClock                              = (unsigned int)state->bw_ctx.bw.dcn.clk.dispclk_khz;
2804         info->engineClock                               = (unsigned int)state->bw_ctx.bw.dcn.clk.dcfclk_khz;
2805         info->memoryClock                               = (unsigned int)state->bw_ctx.bw.dcn.clk.dramclk_khz;
2806         info->maxSupportedDppClock              = (unsigned int)state->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz;
2807         info->dppClock                                  = (unsigned int)state->bw_ctx.bw.dcn.clk.dppclk_khz;
2808         info->socClock                                  = (unsigned int)state->bw_ctx.bw.dcn.clk.socclk_khz;
2809         info->dcfClockDeepSleep                 = (unsigned int)state->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz;
2810         info->fClock                                    = (unsigned int)state->bw_ctx.bw.dcn.clk.fclk_khz;
2811         info->phyClock                                  = (unsigned int)state->bw_ctx.bw.dcn.clk.phyclk_khz;
2812 }
2813 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping)
2814 {
2815         if (dc->hwss.set_clock)
2816                 return dc->hwss.set_clock(dc, clock_type, clk_khz, stepping);
2817         return DC_ERROR_UNEXPECTED;
2818 }
2819 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg)
2820 {
2821         if (dc->hwss.get_clock)
2822                 dc->hwss.get_clock(dc, clock_type, clock_cfg);
2823 }