drivers/gpu/drm/amd/display/dc/core/dc.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  */
  24
  25 #include "dm_services.h"
  26
  27 #include "dc.h"
  28
  29 #include "core_status.h"
  30 #include "core_types.h"
  31 #include "hw_sequencer.h"
  32 #include "dce/dce_hwseq.h"
  33
  34 #include "resource.h"
  35
  36 #include "clock_source.h"
  37 #include "dc_bios_types.h"
  38
  39 #include "bios_parser_interface.h"
  40 #include "include/irq_service_interface.h"
  41 #include "transform.h"
  42 #include "dmcu.h"
  43 #include "dpp.h"
  44 #include "timing_generator.h"
  45 #include "abm.h"
  46 #include "virtual/virtual_link_encoder.h"
  47
  48 #include "link_hwss.h"
  49 #include "link_encoder.h"
  50
  51 #include "dc_link_ddc.h"
  52 #include "dm_helpers.h"
  53 #include "mem_input.h"
  54 #include "hubp.h"
  55
  56 #include "dc_link_dp.h"
  57
  58 #include "dce/dce_i2c.h"
  59
  60 #define DC_LOGGER \
  61         dc->ctx->logger
  62
  63 const static char DC_BUILD_ID[] = "production-build";
  64
  65 /**
  66  * DOC: Overview
  67  *
  68  * DC is the OS-agnostic component of the amdgpu DC driver.
  69  *
  70  * DC maintains and validates a set of structs representing the state of the
  71  * driver and writes that state to AMD hardware
  72  *
  73  * Main DC HW structs:
  74  *
  75  * struct dc - The central struct.  One per driver.  Created on driver load,
  76  * destroyed on driver unload.
  77  *
  78  * struct dc_context - One per driver.
  79  * Used as a backpointer by most other structs in dc.
  80  *
  81  * struct dc_link - One per connector (the physical DP, HDMI, miniDP, or eDP
  82  * plugpoints).  Created on driver load, destroyed on driver unload.
  83  *
  84  * struct dc_sink - One per display.  Created on boot or hotplug.
  85  * Destroyed on shutdown or hotunplug.  A dc_link can have a local sink
  86  * (the display directly attached).  It may also have one or more remote
  87  * sinks (in the Multi-Stream Transport case)
  88  *
  89  * struct resource_pool - One per driver.  Represents the hw blocks not in the
  90  * main pipeline.  Not directly accessible by dm.
  91  *
  92  * Main dc state structs:
  93  *
  94  * These structs can be created and destroyed as needed.  There is a full set of
  95  * these structs in dc->current_state representing the currently programmed state.
  96  *
  97  * struct dc_state - The global DC state to track global state information,
  98  * such as bandwidth values.
  99  *
 100  * struct dc_stream_state - Represents the hw configuration for the pipeline from
 101  * a framebuffer to a display.  Maps one-to-one with dc_sink.
 102  *
 103  * struct dc_plane_state - Represents a framebuffer.  Each stream has at least one,
 104  * and may have more in the Multi-Plane Overlay case.
 105  *
 106  * struct resource_context - Represents the programmable state of everything in
 107  * the resource_pool.  Not directly accessible by dm.
 108  *
 109  * struct pipe_ctx - A member of struct resource_context.  Represents the
 110  * internal hardware pipeline components.  Each dc_plane_state has either
 111  * one or two (in the pipe-split case).
 112  */
 113
 114 /*******************************************************************************
 115  * Private functions
 116  ******************************************************************************/
 117
 118 static inline void elevate_update_type(enum surface_update_type *original, enum surface_update_type new)
 119 {
 120         if (new > *original)
 121                 *original = new;
 122 }
 123
 124 static void destroy_links(struct dc *dc)
 125 {
 126         uint32_t i;
 127
 128         for (i = 0; i < dc->link_count; i++) {
 129                 if (NULL != dc->links[i])
 130                         link_destroy(&dc->links[i]);
 131         }
 132 }
 133
 134 static bool create_links(
 135                 struct dc *dc,
 136                 uint32_t num_virtual_links)
 137 {
 138         int i;
 139         int connectors_num;
 140         struct dc_bios *bios = dc->ctx->dc_bios;
 141
 142         dc->link_count = 0;
 143
 144         connectors_num = bios->funcs->get_connectors_number(bios);
 145
 146         if (connectors_num > ENUM_ID_COUNT) {
 147                 dm_error(
 148                         "DC: Number of connectors %d exceeds maximum of %d!\n",
 149                         connectors_num,
 150                         ENUM_ID_COUNT);
 151                 return false;
 152         }
 153
 154         dm_output_to_console(
 155                 "DC: %s: connectors_num: physical:%d, virtual:%d\n",
 156                 __func__,
 157                 connectors_num,
 158                 num_virtual_links);
 159
 160         for (i = 0; i < connectors_num; i++) {
 161                 struct link_init_data link_init_params = {0};
 162                 struct dc_link *link;
 163
 164                 link_init_params.ctx = dc->ctx;
 165                 /* next BIOS object table connector */
 166                 link_init_params.connector_index = i;
 167                 link_init_params.link_index = dc->link_count;
 168                 link_init_params.dc = dc;
 169                 link = link_create(&link_init_params);
 170
 171                 if (link) {
 172                         dc->links[dc->link_count] = link;
 173                         link->dc = dc;
 174                         ++dc->link_count;
 175                 }
 176         }
 177
 178         for (i = 0; i < num_virtual_links; i++) {
 179                 struct dc_link *link = kzalloc(sizeof(*link), GFP_KERNEL);
 180                 struct encoder_init_data enc_init = {0};
 181
 182                 if (link == NULL) {
 183                         BREAK_TO_DEBUGGER();
 184                         goto failed_alloc;
 185                 }
 186
 187                 link->link_index = dc->link_count;
 188                 dc->links[dc->link_count] = link;
 189                 dc->link_count++;
 190
 191                 link->ctx = dc->ctx;
 192                 link->dc = dc;
 193                 link->connector_signal = SIGNAL_TYPE_VIRTUAL;
 194                 link->link_id.type = OBJECT_TYPE_CONNECTOR;
 195                 link->link_id.id = CONNECTOR_ID_VIRTUAL;
 196                 link->link_id.enum_id = ENUM_ID_1;
 197                 link->link_enc = kzalloc(sizeof(*link->link_enc), GFP_KERNEL);
 198
 199                 if (!link->link_enc) {
 200                         BREAK_TO_DEBUGGER();
 201                         goto failed_alloc;
 202                 }
 203
 204                 link->link_status.dpcd_caps = &link->dpcd_caps;
 205
 206                 enc_init.ctx = dc->ctx;
 207                 enc_init.channel = CHANNEL_ID_UNKNOWN;
 208                 enc_init.hpd_source = HPD_SOURCEID_UNKNOWN;
 209                 enc_init.transmitter = TRANSMITTER_UNKNOWN;
 210                 enc_init.connector = link->link_id;
 211                 enc_init.encoder.type = OBJECT_TYPE_ENCODER;
 212                 enc_init.encoder.id = ENCODER_ID_INTERNAL_VIRTUAL;
 213                 enc_init.encoder.enum_id = ENUM_ID_1;
 214                 virtual_link_encoder_construct(link->link_enc, &enc_init);
 215         }
 216
 217         return true;
 218
 219 failed_alloc:
 220         return false;
 221 }
 222
 223 static struct dc_perf_trace *dc_perf_trace_create(void)
 224 {
 225         return kzalloc(sizeof(struct dc_perf_trace), GFP_KERNEL);
 226 }
 227
 228 static void dc_perf_trace_destroy(struct dc_perf_trace **perf_trace)
 229 {
 230         kfree(*perf_trace);
 231         *perf_trace = NULL;
 232 }
 233
 234 /**
 235  *****************************************************************************
 236  *  Function: dc_stream_adjust_vmin_vmax
 237  *
 238  *  @brief
 239  *     Looks up the pipe context of dc_stream_state and updates the
 240  *     vertical_total_min and vertical_total_max of the DRR, Dynamic Refresh
 241  *     Rate, which is a power-saving feature that targets reducing panel
 242  *     refresh rate while the screen is static
 243  *
 244  *  @param [in] dc: dc reference
 245  *  @param [in] stream: Initial dc stream state
 246  *  @param [in] adjust: Updated parameters for vertical_total_min and
 247  *  vertical_total_max
 248  *****************************************************************************
 249  */
 250 bool dc_stream_adjust_vmin_vmax(struct dc *dc,
 251                 struct dc_stream_state *stream,
 252                 struct dc_crtc_timing_adjust *adjust)
 253 {
 254         int i = 0;
 255         bool ret = false;
 256
 257         for (i = 0; i < MAX_PIPES; i++) {
 258                 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 259
 260                 if (pipe->stream == stream && pipe->stream_res.stream_enc) {
 261                         pipe->stream->adjust = *adjust;
 262                         dc->hwss.set_drr(&pipe,
 263                                         1,
 264                                         adjust->v_total_min,
 265                                         adjust->v_total_max);
 266
 267                         ret = true;
 268                 }
 269         }
 270         return ret;
 271 }
 272
 273 bool dc_stream_get_crtc_position(struct dc *dc,
 274                 struct dc_stream_state **streams, int num_streams,
 275                 unsigned int *v_pos, unsigned int *nom_v_pos)
 276 {
 277         /* TODO: Support multiple streams */
 278         const struct dc_stream_state *stream = streams[0];
 279         int i = 0;
 280         bool ret = false;
 281         struct crtc_position position;
 282
 283         for (i = 0; i < MAX_PIPES; i++) {
 284                 struct pipe_ctx *pipe =
 285                                 &dc->current_state->res_ctx.pipe_ctx[i];
 286
 287                 if (pipe->stream == stream && pipe->stream_res.stream_enc) {
 288                         dc->hwss.get_position(&pipe, 1, &position);
 289
 290                         *v_pos = position.vertical_count;
 291                         *nom_v_pos = position.nominal_vcount;
 292                         ret = true;
 293                 }
 294         }
 295         return ret;
 296 }
 297
 298 /**
 299  * dc_stream_configure_crc() - Configure CRC capture for the given stream.
 300  * @dc: DC Object
 301  * @stream: The stream to configure CRC on.
 302  * @enable: Enable CRC if true, disable otherwise.
 303  * @continuous: Capture CRC on every frame if true. Otherwise, only capture
 304  *              once.
 305  *
 306  * By default, only CRC0 is configured, and the entire frame is used to
 307  * calculate the crc.
 308  */
 309 bool dc_stream_configure_crc(struct dc *dc, struct dc_stream_state *stream,
 310                              bool enable, bool continuous)
 311 {
 312         int i;
 313         struct pipe_ctx *pipe;
 314         struct crc_params param;
 315         struct timing_generator *tg;
 316
 317         for (i = 0; i < MAX_PIPES; i++) {
 318                 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 319                 if (pipe->stream == stream)
 320                         break;
 321         }
 322         /* Stream not found */
 323         if (i == MAX_PIPES)
 324                 return false;
 325
 326         /* Always capture the full frame */
 327         param.windowa_x_start = 0;
 328         param.windowa_y_start = 0;
 329         param.windowa_x_end = pipe->stream->timing.h_addressable;
 330         param.windowa_y_end = pipe->stream->timing.v_addressable;
 331         param.windowb_x_start = 0;
 332         param.windowb_y_start = 0;
 333         param.windowb_x_end = pipe->stream->timing.h_addressable;
 334         param.windowb_y_end = pipe->stream->timing.v_addressable;
 335
 336         /* Default to the union of both windows */
 337         param.selection = UNION_WINDOW_A_B;
 338         param.continuous_mode = continuous;
 339         param.enable = enable;
 340
 341         tg = pipe->stream_res.tg;
 342
 343         /* Only call if supported */
 344         if (tg->funcs->configure_crc)
 345                 return tg->funcs->configure_crc(tg, &param);
 346         DC_LOG_WARNING("CRC capture not supported.");
 347         return false;
 348 }
 349
 350 /**
 351  * dc_stream_get_crc() - Get CRC values for the given stream.
 352  * @dc: DC object
 353  * @stream: The DC stream state of the stream to get CRCs from.
 354  * @r_cr, g_y, b_cb: CRC values for the three channels are stored here.
 355  *
 356  * dc_stream_configure_crc needs to be called beforehand to enable CRCs.
 357  * Return false if stream is not found, or if CRCs are not enabled.
 358  */
 359 bool dc_stream_get_crc(struct dc *dc, struct dc_stream_state *stream,
 360                        uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb)
 361 {
 362         int i;
 363         struct pipe_ctx *pipe;
 364         struct timing_generator *tg;
 365
 366         for (i = 0; i < MAX_PIPES; i++) {
 367                 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 368                 if (pipe->stream == stream)
 369                         break;
 370         }
 371         /* Stream not found */
 372         if (i == MAX_PIPES)
 373                 return false;
 374
 375         tg = pipe->stream_res.tg;
 376
 377         if (tg->funcs->get_crc)
 378                 return tg->funcs->get_crc(tg, r_cr, g_y, b_cb);
 379         DC_LOG_WARNING("CRC capture not supported.");
 380         return false;
 381 }
 382
 383 void dc_stream_set_dither_option(struct dc_stream_state *stream,
 384                 enum dc_dither_option option)
 385 {
 386         struct bit_depth_reduction_params params;
 387         struct dc_link *link = stream->link;
 388         struct pipe_ctx *pipes = NULL;
 389         int i;
 390
 391         for (i = 0; i < MAX_PIPES; i++) {
 392                 if (link->dc->current_state->res_ctx.pipe_ctx[i].stream ==
 393                                 stream) {
 394                         pipes = &link->dc->current_state->res_ctx.pipe_ctx[i];
 395                         break;
 396                 }
 397         }
 398
 399         if (!pipes)
 400                 return;
 401         if (option > DITHER_OPTION_MAX)
 402                 return;
 403
 404         stream->dither_option = option;
 405
 406         memset(&params, 0, sizeof(params));
 407         resource_build_bit_depth_reduction_params(stream, &params);
 408         stream->bit_depth_params = params;
 409
 410         if (pipes->plane_res.xfm &&
 411             pipes->plane_res.xfm->funcs->transform_set_pixel_storage_depth) {
 412                 pipes->plane_res.xfm->funcs->transform_set_pixel_storage_depth(
 413                         pipes->plane_res.xfm,
 414                         pipes->plane_res.scl_data.lb_params.depth,
 415                         &stream->bit_depth_params);
 416         }
 417
 418         pipes->stream_res.opp->funcs->
 419                 opp_program_bit_depth_reduction(pipes->stream_res.opp, &params);
 420 }
 421
 422 bool dc_stream_set_gamut_remap(struct dc *dc, const struct dc_stream_state *stream)
 423 {
 424         int i = 0;
 425         bool ret = false;
 426         struct pipe_ctx *pipes;
 427
 428         for (i = 0; i < MAX_PIPES; i++) {
 429                 if (dc->current_state->res_ctx.pipe_ctx[i].stream == stream) {
 430                         pipes = &dc->current_state->res_ctx.pipe_ctx[i];
 431                         dc->hwss.program_gamut_remap(pipes);
 432                         ret = true;
 433                 }
 434         }
 435
 436         return ret;
 437 }
 438
 439 bool dc_stream_program_csc_matrix(struct dc *dc, struct dc_stream_state *stream)
 440 {
 441         int i = 0;
 442         bool ret = false;
 443         struct pipe_ctx *pipes;
 444
 445         for (i = 0; i < MAX_PIPES; i++) {
 446                 if (dc->current_state->res_ctx.pipe_ctx[i].stream
 447                                 == stream) {
 448
 449                         pipes = &dc->current_state->res_ctx.pipe_ctx[i];
 450                         dc->hwss.program_output_csc(dc,
 451                                         pipes,
 452                                         stream->output_color_space,
 453                                         stream->csc_color_matrix.matrix,
 454                                         pipes->plane_res.hubp ? pipes->plane_res.hubp->opp_id : 0);
 455                         ret = true;
 456                 }
 457         }
 458
 459         return ret;
 460 }
 461
 462 void dc_stream_set_static_screen_events(struct dc *dc,
 463                 struct dc_stream_state **streams,
 464                 int num_streams,
 465                 const struct dc_static_screen_events *events)
 466 {
 467         int i = 0;
 468         int j = 0;
 469         struct pipe_ctx *pipes_affected[MAX_PIPES];
 470         int num_pipes_affected = 0;
 471
 472         for (i = 0; i < num_streams; i++) {
 473                 struct dc_stream_state *stream = streams[i];
 474
 475                 for (j = 0; j < MAX_PIPES; j++) {
 476                         if (dc->current_state->res_ctx.pipe_ctx[j].stream
 477                                         == stream) {
 478                                 pipes_affected[num_pipes_affected++] =
 479                                                 &dc->current_state->res_ctx.pipe_ctx[j];
 480                         }
 481                 }
 482         }
 483
 484         dc->hwss.set_static_screen_control(pipes_affected, num_pipes_affected, events);
 485 }
 486
 487 void dc_link_set_drive_settings(struct dc *dc,
 488                                 struct link_training_settings *lt_settings,
 489                                 const struct dc_link *link)
 490 {
 491
 492         int i;
 493
 494         for (i = 0; i < dc->link_count; i++) {
 495                 if (dc->links[i] == link)
 496                         break;
 497         }
 498
 499         if (i >= dc->link_count)
 500                 ASSERT_CRITICAL(false);
 501
 502         dc_link_dp_set_drive_settings(dc->links[i], lt_settings);
 503 }
 504
 505 void dc_link_perform_link_training(struct dc *dc,
 506                                    struct dc_link_settings *link_setting,
 507                                    bool skip_video_pattern)
 508 {
 509         int i;
 510
 511         for (i = 0; i < dc->link_count; i++)
 512                 dc_link_dp_perform_link_training(
 513                         dc->links[i],
 514                         link_setting,
 515                         skip_video_pattern);
 516 }
 517
 518 void dc_link_set_preferred_link_settings(struct dc *dc,
 519                                          struct dc_link_settings *link_setting,
 520                                          struct dc_link *link)
 521 {
 522         int i;
 523         struct pipe_ctx *pipe;
 524         struct dc_stream_state *link_stream;
 525         struct dc_link_settings store_settings = *link_setting;
 526
 527         for (i = 0; i < MAX_PIPES; i++) {
 528                 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 529                 if (pipe->stream && pipe->stream->link) {
 530                         if (pipe->stream->link == link)
 531                                 break;
 532                 }
 533         }
 534
 535         /* Stream not found */
 536         if (i == MAX_PIPES)
 537                 return;
 538
 539         link_stream = link->dc->current_state->res_ctx.pipe_ctx[i].stream;
 540
 541         link->preferred_link_setting = store_settings;
 542         if (link_stream)
 543                 decide_link_settings(link_stream, &store_settings);
 544
 545         if ((store_settings.lane_count != LANE_COUNT_UNKNOWN) &&
 546                 (store_settings.link_rate != LINK_RATE_UNKNOWN))
 547                 dp_retrain_link_dp_test(link, &store_settings, false);
 548 }
 549
 550 void dc_link_enable_hpd(const struct dc_link *link)
 551 {
 552         dc_link_dp_enable_hpd(link);
 553 }
 554
 555 void dc_link_disable_hpd(const struct dc_link *link)
 556 {
 557         dc_link_dp_disable_hpd(link);
 558 }
 559
 560
 561 void dc_link_set_test_pattern(struct dc_link *link,
 562                               enum dp_test_pattern test_pattern,
 563                               const struct link_training_settings *p_link_settings,
 564                               const unsigned char *p_custom_pattern,
 565                               unsigned int cust_pattern_size)
 566 {
 567         if (link != NULL)
 568                 dc_link_dp_set_test_pattern(
 569                         link,
 570                         test_pattern,
 571                         p_link_settings,
 572                         p_custom_pattern,
 573                         cust_pattern_size);
 574 }
 575
 576 static void destruct(struct dc *dc)
 577 {
 578         dc_release_state(dc->current_state);
 579         dc->current_state = NULL;
 580
 581         destroy_links(dc);
 582
 583         dc_destroy_resource_pool(dc);
 584
 585         if (dc->ctx->gpio_service)
 586                 dal_gpio_service_destroy(&dc->ctx->gpio_service);
 587
 588         if (dc->ctx->created_bios)
 589                 dal_bios_parser_destroy(&dc->ctx->dc_bios);
 590
 591         dc_perf_trace_destroy(&dc->ctx->perf_trace);
 592
 593         kfree(dc->ctx);
 594         dc->ctx = NULL;
 595
 596         kfree(dc->bw_vbios);
 597         dc->bw_vbios = NULL;
 598
 599         kfree(dc->bw_dceip);
 600         dc->bw_dceip = NULL;
 601
 602 #ifdef CONFIG_DRM_AMD_DC_DCN1_0
 603         kfree(dc->dcn_soc);
 604         dc->dcn_soc = NULL;
 605
 606         kfree(dc->dcn_ip);
 607         dc->dcn_ip = NULL;
 608
 609 #endif
 610 }
 611
 612 static bool construct(struct dc *dc,
 613                 const struct dc_init_data *init_params)
 614 {
 615         struct dc_context *dc_ctx;
 616         struct bw_calcs_dceip *dc_dceip;
 617         struct bw_calcs_vbios *dc_vbios;
 618 #ifdef CONFIG_DRM_AMD_DC_DCN1_0
 619         struct dcn_soc_bounding_box *dcn_soc;
 620         struct dcn_ip_params *dcn_ip;
 621 #endif
 622
 623         enum dce_version dc_version = DCE_VERSION_UNKNOWN;
 624
 625         dc_dceip = kzalloc(sizeof(*dc_dceip), GFP_KERNEL);
 626         if (!dc_dceip) {
 627                 dm_error("%s: failed to create dceip\n", __func__);
 628                 goto fail;
 629         }
 630
 631         dc->bw_dceip = dc_dceip;
 632
 633         dc_vbios = kzalloc(sizeof(*dc_vbios), GFP_KERNEL);
 634         if (!dc_vbios) {
 635                 dm_error("%s: failed to create vbios\n", __func__);
 636                 goto fail;
 637         }
 638
 639         dc->bw_vbios = dc_vbios;
 640 #ifdef CONFIG_DRM_AMD_DC_DCN1_0
 641         dcn_soc = kzalloc(sizeof(*dcn_soc), GFP_KERNEL);
 642         if (!dcn_soc) {
 643                 dm_error("%s: failed to create dcn_soc\n", __func__);
 644                 goto fail;
 645         }
 646
 647         dc->dcn_soc = dcn_soc;
 648
 649         dcn_ip = kzalloc(sizeof(*dcn_ip), GFP_KERNEL);
 650         if (!dcn_ip) {
 651                 dm_error("%s: failed to create dcn_ip\n", __func__);
 652                 goto fail;
 653         }
 654
 655         dc->dcn_ip = dcn_ip;
 656 #endif
 657
 658         dc_ctx = kzalloc(sizeof(*dc_ctx), GFP_KERNEL);
 659         if (!dc_ctx) {
 660                 dm_error("%s: failed to create ctx\n", __func__);
 661                 goto fail;
 662         }
 663
 664         dc_ctx->cgs_device = init_params->cgs_device;
 665         dc_ctx->driver_context = init_params->driver;
 666         dc_ctx->dc = dc;
 667         dc_ctx->asic_id = init_params->asic_id;
 668         dc_ctx->dc_sink_id_count = 0;
 669         dc_ctx->dc_stream_id_count = 0;
 670         dc->ctx = dc_ctx;
 671
 672         dc->current_state = dc_create_state();
 673
 674         if (!dc->current_state) {
 675                 dm_error("%s: failed to create validate ctx\n", __func__);
 676                 goto fail;
 677         }
 678
 679         /* Create logger */
 680
 681         dc_ctx->dce_environment = init_params->dce_environment;
 682
 683         dc_version = resource_parse_asic_id(init_params->asic_id);
 684         dc_ctx->dce_version = dc_version;
 685
 686         /* Resource should construct all asic specific resources.
 687          * This should be the only place where we need to parse the asic id
 688          */
 689         if (init_params->vbios_override)
 690                 dc_ctx->dc_bios = init_params->vbios_override;
 691         else {
 692                 /* Create BIOS parser */
 693                 struct bp_init_data bp_init_data;
 694
 695                 bp_init_data.ctx = dc_ctx;
 696                 bp_init_data.bios = init_params->asic_id.atombios_base_address;
 697
 698                 dc_ctx->dc_bios = dal_bios_parser_create(
 699                                 &bp_init_data, dc_version);
 700
 701                 if (!dc_ctx->dc_bios) {
 702                         ASSERT_CRITICAL(false);
 703                         goto fail;
 704                 }
 705
 706                 dc_ctx->created_bios = true;
 707                 }
 708
 709         dc_ctx->perf_trace = dc_perf_trace_create();
 710         if (!dc_ctx->perf_trace) {
 711                 ASSERT_CRITICAL(false);
 712                 goto fail;
 713         }
 714
 715         /* Create GPIO service */
 716         dc_ctx->gpio_service = dal_gpio_service_create(
 717                         dc_version,
 718                         dc_ctx->dce_environment,
 719                         dc_ctx);
 720
 721         if (!dc_ctx->gpio_service) {
 722                 ASSERT_CRITICAL(false);
 723                 goto fail;
 724         }
 725
 726         dc->res_pool = dc_create_resource_pool(
 727                         dc,
 728                         init_params->num_virtual_links,
 729                         dc_version,
 730                         init_params->asic_id);
 731         if (!dc->res_pool)
 732                 goto fail;
 733
 734         dc_resource_state_construct(dc, dc->current_state);
 735
 736         if (!create_links(dc, init_params->num_virtual_links))
 737                 goto fail;
 738
 739         return true;
 740
 741 fail:
 742
 743         destruct(dc);
 744         return false;
 745 }
 746
 747 static void disable_dangling_plane(struct dc *dc, struct dc_state *context)
 748 {
 749         int i, j;
 750         struct dc_state *dangling_context = dc_create_state();
 751         struct dc_state *current_ctx;
 752
 753         if (dangling_context == NULL)
 754                 return;
 755
 756         dc_resource_state_copy_construct(dc->current_state, dangling_context);
 757
 758         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 759                 struct dc_stream_state *old_stream =
 760                                 dc->current_state->res_ctx.pipe_ctx[i].stream;
 761                 bool should_disable = true;
 762
 763                 for (j = 0; j < context->stream_count; j++) {
 764                         if (old_stream == context->streams[j]) {
 765                                 should_disable = false;
 766                                 break;
 767                         }
 768                 }
 769                 if (should_disable && old_stream) {
 770                         dc_rem_all_planes_for_stream(dc, old_stream, dangling_context);
 771                         dc->hwss.apply_ctx_for_surface(dc, old_stream, 0, dangling_context);
 772                 }
 773         }
 774
 775         current_ctx = dc->current_state;
 776         dc->current_state = dangling_context;
 777         dc_release_state(current_ctx);
 778 }
 779
 780 /*******************************************************************************
 781  * Public functions
 782  ******************************************************************************/
 783
 784 struct dc *dc_create(const struct dc_init_data *init_params)
 785 {
 786         struct dc *dc = kzalloc(sizeof(*dc), GFP_KERNEL);
 787         unsigned int full_pipe_count;
 788
 789         if (NULL == dc)
 790                 goto alloc_fail;
 791
 792         if (false == construct(dc, init_params))
 793                 goto construct_fail;
 794
 795         /*TODO: separate HW and SW initialization*/
 796         dc->hwss.init_hw(dc);
 797
 798         full_pipe_count = dc->res_pool->pipe_count;
 799         if (dc->res_pool->underlay_pipe_index != NO_UNDERLAY_PIPE)
 800                 full_pipe_count--;
 801         dc->caps.max_streams = min(
 802                         full_pipe_count,
 803                         dc->res_pool->stream_enc_count);
 804
 805         dc->caps.max_links = dc->link_count;
 806         dc->caps.max_audios = dc->res_pool->audio_count;
 807         dc->caps.linear_pitch_alignment = 64;
 808
 809         /* Populate versioning information */
 810         dc->versions.dc_ver = DC_VER;
 811
 812         if (dc->res_pool->dmcu != NULL)
 813                 dc->versions.dmcu_version = dc->res_pool->dmcu->dmcu_version;
 814
 815         dc->config = init_params->flags;
 816
 817         dc->build_id = DC_BUILD_ID;
 818
 819         DC_LOG_DC("Display Core initialized\n");
 820
 821
 822
 823         return dc;
 824
 825 construct_fail:
 826         kfree(dc);
 827
 828 alloc_fail:
 829         return NULL;
 830 }
 831
 832 void dc_init_callbacks(struct dc *dc,
 833                 const struct dc_callback_init *init_params)
 834 {
 835 }
 836
 837 void dc_destroy(struct dc **dc)
 838 {
 839         destruct(*dc);
 840         kfree(*dc);
 841         *dc = NULL;
 842 }
 843
 844 static void enable_timing_multisync(
 845                 struct dc *dc,
 846                 struct dc_state *ctx)
 847 {
 848         int i = 0, multisync_count = 0;
 849         int pipe_count = dc->res_pool->pipe_count;
 850         struct pipe_ctx *multisync_pipes[MAX_PIPES] = { NULL };
 851
 852         for (i = 0; i < pipe_count; i++) {
 853                 if (!ctx->res_ctx.pipe_ctx[i].stream ||
 854                                 !ctx->res_ctx.pipe_ctx[i].stream->triggered_crtc_reset.enabled)
 855                         continue;
 856                 if (ctx->res_ctx.pipe_ctx[i].stream == ctx->res_ctx.pipe_ctx[i].stream->triggered_crtc_reset.event_source)
 857                         continue;
 858                 multisync_pipes[multisync_count] = &ctx->res_ctx.pipe_ctx[i];
 859                 multisync_count++;
 860         }
 861
 862         if (multisync_count > 0) {
 863                 dc->hwss.enable_per_frame_crtc_position_reset(
 864                         dc, multisync_count, multisync_pipes);
 865         }
 866 }
 867
 868 static void program_timing_sync(
 869                 struct dc *dc,
 870                 struct dc_state *ctx)
 871 {
 872         int i, j;
 873         int group_index = 0;
 874         int pipe_count = dc->res_pool->pipe_count;
 875         struct pipe_ctx *unsynced_pipes[MAX_PIPES] = { NULL };
 876
 877         for (i = 0; i < pipe_count; i++) {
 878                 if (!ctx->res_ctx.pipe_ctx[i].stream || ctx->res_ctx.pipe_ctx[i].top_pipe)
 879                         continue;
 880
 881                 unsynced_pipes[i] = &ctx->res_ctx.pipe_ctx[i];
 882         }
 883
 884         for (i = 0; i < pipe_count; i++) {
 885                 int group_size = 1;
 886                 struct pipe_ctx *pipe_set[MAX_PIPES];
 887
 888                 if (!unsynced_pipes[i])
 889                         continue;
 890
 891                 pipe_set[0] = unsynced_pipes[i];
 892                 unsynced_pipes[i] = NULL;
 893
 894                 /* Add tg to the set, search rest of the tg's for ones with
 895                  * same timing, add all tgs with same timing to the group
 896                  */
 897                 for (j = i + 1; j < pipe_count; j++) {
 898                         if (!unsynced_pipes[j])
 899                                 continue;
 900
 901                         if (resource_are_streams_timing_synchronizable(
 902                                         unsynced_pipes[j]->stream,
 903                                         pipe_set[0]->stream)) {
 904                                 pipe_set[group_size] = unsynced_pipes[j];
 905                                 unsynced_pipes[j] = NULL;
 906                                 group_size++;
 907                         }
 908                 }
 909
 910                 /* set first pipe with plane as master */
 911                 for (j = 0; j < group_size; j++) {
 912                         struct pipe_ctx *temp;
 913
 914                         if (pipe_set[j]->plane_state) {
 915                                 if (j == 0)
 916                                         break;
 917
 918                                 temp = pipe_set[0];
 919                                 pipe_set[0] = pipe_set[j];
 920                                 pipe_set[j] = temp;
 921                                 break;
 922                         }
 923                 }
 924
 925                 /* remove any other pipes with plane as they have already been synced */
 926                 for (j = j + 1; j < group_size; j++) {
 927                         if (pipe_set[j]->plane_state) {
 928                                 group_size--;
 929                                 pipe_set[j] = pipe_set[group_size];
 930                                 j--;
 931                         }
 932                 }
 933
 934                 if (group_size > 1) {
 935                         dc->hwss.enable_timing_synchronization(
 936                                 dc, group_index, group_size, pipe_set);
 937                         group_index++;
 938                 }
 939         }
 940 }
 941
 942 static bool context_changed(
 943                 struct dc *dc,
 944                 struct dc_state *context)
 945 {
 946         uint8_t i;
 947
 948         if (context->stream_count != dc->current_state->stream_count)
 949                 return true;
 950
 951         for (i = 0; i < dc->current_state->stream_count; i++) {
 952                 if (dc->current_state->streams[i] != context->streams[i])
 953                         return true;
 954         }
 955
 956         return false;
 957 }
 958
 959 bool dc_enable_stereo(
 960         struct dc *dc,
 961         struct dc_state *context,
 962         struct dc_stream_state *streams[],
 963         uint8_t stream_count)
 964 {
 965         bool ret = true;
 966         int i, j;
 967         struct pipe_ctx *pipe;
 968
 969         for (i = 0; i < MAX_PIPES; i++) {
 970                 if (context != NULL)
 971                         pipe = &context->res_ctx.pipe_ctx[i];
 972                 else
 973                         pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 974                 for (j = 0 ; pipe && j < stream_count; j++)  {
 975                         if (streams[j] && streams[j] == pipe->stream &&
 976                                 dc->hwss.setup_stereo)
 977                                 dc->hwss.setup_stereo(pipe, dc);
 978                 }
 979         }
 980
 981         return ret;
 982 }
 983
 984 /*
 985  * Applies given context to HW and copy it into current context.
 986  * It's up to the user to release the src context afterwards.
 987  */
 988 static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *context)
 989 {
 990         struct dc_bios *dcb = dc->ctx->dc_bios;
 991         enum dc_status result = DC_ERROR_UNEXPECTED;
 992         struct pipe_ctx *pipe;
 993         int i, k, l;
 994         struct dc_stream_state *dc_streams[MAX_STREAMS] = {0};
 995
 996         disable_dangling_plane(dc, context);
 997
 998         for (i = 0; i < context->stream_count; i++)
 999                 dc_streams[i] =  context->streams[i];
1000
1001         if (!dcb->funcs->is_accelerated_mode(dcb))
1002                 dc->hwss.enable_accelerated_mode(dc, context);
1003
1004         dc->hwss.prepare_bandwidth(dc, context);
1005
1006         /* re-program planes for existing stream, in case we need to
1007          * free up plane resource for later use
1008          */
1009         for (i = 0; i < context->stream_count; i++) {
1010                 if (context->streams[i]->mode_changed)
1011                         continue;
1012
1013                 dc->hwss.apply_ctx_for_surface(
1014                         dc, context->streams[i],
1015                         context->stream_status[i].plane_count,
1016                         context); /* use new pipe config in new context */
1017         }
1018
1019         /* Program hardware */
1020         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1021                 pipe = &context->res_ctx.pipe_ctx[i];
1022                 dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe);
1023         }
1024
1025         result = dc->hwss.apply_ctx_to_hw(dc, context);
1026
1027         if (result != DC_OK)
1028                 return result;
1029
1030         if (context->stream_count > 1) {
1031                 enable_timing_multisync(dc, context);
1032                 program_timing_sync(dc, context);
1033         }
1034
1035         /* Program all planes within new context*/
1036         for (i = 0; i < context->stream_count; i++) {
1037                 const struct dc_link *link = context->streams[i]->link;
1038                 struct dc_stream_status *status;
1039
1040                 if (!context->streams[i]->mode_changed)
1041                         continue;
1042
1043                 dc->hwss.apply_ctx_for_surface(
1044                                 dc, context->streams[i],
1045                                 context->stream_status[i].plane_count,
1046                                 context);
1047
1048                 /*
1049                  * enable stereo
1050                  * TODO rework dc_enable_stereo call to work with validation sets?
1051                  */
1052                 for (k = 0; k < MAX_PIPES; k++) {
1053                         pipe = &context->res_ctx.pipe_ctx[k];
1054
1055                         for (l = 0 ; pipe && l < context->stream_count; l++)  {
1056                                 if (context->streams[l] &&
1057                                         context->streams[l] == pipe->stream &&
1058                                         dc->hwss.setup_stereo)
1059                                         dc->hwss.setup_stereo(pipe, dc);
1060                         }
1061                 }
1062
1063                 status = dc_stream_get_status_from_state(context, context->streams[i]);
1064                 context->streams[i]->out.otg_offset = status->primary_otg_inst;
1065
1066                 CONN_MSG_MODE(link, "{%dx%d, %dx%d@%dKhz}",
1067                                 context->streams[i]->timing.h_addressable,
1068                                 context->streams[i]->timing.v_addressable,
1069                                 context->streams[i]->timing.h_total,
1070                                 context->streams[i]->timing.v_total,
1071                                 context->streams[i]->timing.pix_clk_100hz / 10);
1072         }
1073
1074         dc_enable_stereo(dc, context, dc_streams, context->stream_count);
1075
1076         /* pplib is notified if disp_num changed */
1077         dc->hwss.optimize_bandwidth(dc, context);
1078
1079         dc_release_state(dc->current_state);
1080
1081         dc->current_state = context;
1082
1083         dc_retain_state(dc->current_state);
1084
1085         return result;
1086 }
1087
1088 bool dc_commit_state(struct dc *dc, struct dc_state *context)
1089 {
1090         enum dc_status result = DC_ERROR_UNEXPECTED;
1091         int i;
1092
1093         if (false == context_changed(dc, context))
1094                 return DC_OK;
1095
1096         DC_LOG_DC("%s: %d streams\n",
1097                                 __func__, context->stream_count);
1098
1099         for (i = 0; i < context->stream_count; i++) {
1100                 struct dc_stream_state *stream = context->streams[i];
1101
1102                 dc_stream_log(dc, stream);
1103         }
1104
1105         result = dc_commit_state_no_check(dc, context);
1106
1107         return (result == DC_OK);
1108 }
1109
1110 bool dc_post_update_surfaces_to_stream(struct dc *dc)
1111 {
1112         int i;
1113         struct dc_state *context = dc->current_state;
1114
1115         post_surface_trace(dc);
1116
1117         for (i = 0; i < dc->res_pool->pipe_count; i++)
1118                 if (context->res_ctx.pipe_ctx[i].stream == NULL ||
1119                     context->res_ctx.pipe_ctx[i].plane_state == NULL) {
1120                         context->res_ctx.pipe_ctx[i].pipe_idx = i;
1121                         dc->hwss.disable_plane(dc, &context->res_ctx.pipe_ctx[i]);
1122                 }
1123
1124         dc->optimized_required = false;
1125
1126         dc->hwss.optimize_bandwidth(dc, context);
1127         return true;
1128 }
1129
1130 struct dc_state *dc_create_state(void)
1131 {
1132         struct dc_state *context = kzalloc(sizeof(struct dc_state),
1133                                            GFP_KERNEL);
1134
1135         if (!context)
1136                 return NULL;
1137
1138         kref_init(&context->refcount);
1139         return context;
1140 }
1141
1142 void dc_retain_state(struct dc_state *context)
1143 {
1144         kref_get(&context->refcount);
1145 }
1146
1147 static void dc_state_free(struct kref *kref)
1148 {
1149         struct dc_state *context = container_of(kref, struct dc_state, refcount);
1150         dc_resource_state_destruct(context);
1151         kfree(context);
1152 }
1153
1154 void dc_release_state(struct dc_state *context)
1155 {
1156         kref_put(&context->refcount, dc_state_free);
1157 }
1158
1159 static bool is_surface_in_context(
1160                 const struct dc_state *context,
1161                 const struct dc_plane_state *plane_state)
1162 {
1163         int j;
1164
1165         for (j = 0; j < MAX_PIPES; j++) {
1166                 const struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
1167
1168                 if (plane_state == pipe_ctx->plane_state) {
1169                         return true;
1170                 }
1171         }
1172
1173         return false;
1174 }
1175
1176 static enum surface_update_type get_plane_info_update_type(const struct dc_surface_update *u)
1177 {
1178         union surface_update_flags *update_flags = &u->surface->update_flags;
1179
1180         if (!u->plane_info)
1181                 return UPDATE_TYPE_FAST;
1182
1183         if (u->plane_info->color_space != u->surface->color_space)
1184                 update_flags->bits.color_space_change = 1;
1185
1186         if (u->plane_info->horizontal_mirror != u->surface->horizontal_mirror)
1187                 update_flags->bits.horizontal_mirror_change = 1;
1188
1189         if (u->plane_info->rotation != u->surface->rotation)
1190                 update_flags->bits.rotation_change = 1;
1191
1192         if (u->plane_info->format != u->surface->format)
1193                 update_flags->bits.pixel_format_change = 1;
1194
1195         if (u->plane_info->stereo_format != u->surface->stereo_format)
1196                 update_flags->bits.stereo_format_change = 1;
1197
1198         if (u->plane_info->per_pixel_alpha != u->surface->per_pixel_alpha)
1199                 update_flags->bits.per_pixel_alpha_change = 1;
1200
1201         if (u->plane_info->global_alpha_value != u->surface->global_alpha_value)
1202                 update_flags->bits.global_alpha_change = 1;
1203
1204         if (u->plane_info->dcc.enable != u->surface->dcc.enable
1205                         || u->plane_info->dcc.grph.independent_64b_blks != u->surface->dcc.grph.independent_64b_blks
1206                         || u->plane_info->dcc.grph.meta_pitch != u->surface->dcc.grph.meta_pitch)
1207                 update_flags->bits.dcc_change = 1;
1208
1209         if (resource_pixel_format_to_bpp(u->plane_info->format) !=
1210                         resource_pixel_format_to_bpp(u->surface->format))
1211                 /* different bytes per element will require full bandwidth
1212                  * and DML calculation
1213                  */
1214                 update_flags->bits.bpp_change = 1;
1215
1216         if (u->plane_info->plane_size.grph.surface_pitch != u->surface->plane_size.grph.surface_pitch
1217                         || u->plane_info->plane_size.video.luma_pitch != u->surface->plane_size.video.luma_pitch
1218                         || u->plane_info->plane_size.video.chroma_pitch != u->surface->plane_size.video.chroma_pitch)
1219                 update_flags->bits.plane_size_change = 1;
1220
1221
1222         if (memcmp(&u->plane_info->tiling_info, &u->surface->tiling_info,
1223                         sizeof(union dc_tiling_info)) != 0) {
1224                 update_flags->bits.swizzle_change = 1;
1225                 /* todo: below are HW dependent, we should add a hook to
1226                  * DCE/N resource and validated there.
1227                  */
1228                 if (u->plane_info->tiling_info.gfx9.swizzle != DC_SW_LINEAR)
1229                         /* swizzled mode requires RQ to be setup properly,
1230                          * thus need to run DML to calculate RQ settings
1231                          */
1232                         update_flags->bits.bandwidth_change = 1;
1233         }
1234
1235         if (update_flags->bits.rotation_change
1236                         || update_flags->bits.stereo_format_change
1237                         || update_flags->bits.pixel_format_change
1238                         || update_flags->bits.bpp_change
1239                         || update_flags->bits.bandwidth_change
1240                         || update_flags->bits.output_tf_change)
1241                 return UPDATE_TYPE_FULL;
1242
1243         return update_flags->raw ? UPDATE_TYPE_MED : UPDATE_TYPE_FAST;
1244 }
1245
1246 static enum surface_update_type get_scaling_info_update_type(
1247                 const struct dc_surface_update *u)
1248 {
1249         union surface_update_flags *update_flags = &u->surface->update_flags;
1250
1251         if (!u->scaling_info)
1252                 return UPDATE_TYPE_FAST;
1253
1254         if (u->scaling_info->clip_rect.width != u->surface->clip_rect.width
1255                         || u->scaling_info->clip_rect.height != u->surface->clip_rect.height
1256                         || u->scaling_info->dst_rect.width != u->surface->dst_rect.width
1257                         || u->scaling_info->dst_rect.height != u->surface->dst_rect.height) {
1258                 update_flags->bits.scaling_change = 1;
1259
1260                 if ((u->scaling_info->dst_rect.width < u->surface->dst_rect.width
1261                         || u->scaling_info->dst_rect.height < u->surface->dst_rect.height)
1262                                 && (u->scaling_info->dst_rect.width < u->surface->src_rect.width
1263                                         || u->scaling_info->dst_rect.height < u->surface->src_rect.height))
1264                         /* Making dst rect smaller requires a bandwidth change */
1265                         update_flags->bits.bandwidth_change = 1;
1266         }
1267
1268         if (u->scaling_info->src_rect.width != u->surface->src_rect.width
1269                 || u->scaling_info->src_rect.height != u->surface->src_rect.height) {
1270
1271                 update_flags->bits.scaling_change = 1;
1272                 if (u->scaling_info->src_rect.width > u->surface->src_rect.width
1273                                 && u->scaling_info->src_rect.height > u->surface->src_rect.height)
1274                         /* Making src rect bigger requires a bandwidth change */
1275                         update_flags->bits.clock_change = 1;
1276         }
1277
1278         if (u->scaling_info->src_rect.x != u->surface->src_rect.x
1279                         || u->scaling_info->src_rect.y != u->surface->src_rect.y
1280                         || u->scaling_info->clip_rect.x != u->surface->clip_rect.x
1281                         || u->scaling_info->clip_rect.y != u->surface->clip_rect.y
1282                         || u->scaling_info->dst_rect.x != u->surface->dst_rect.x
1283                         || u->scaling_info->dst_rect.y != u->surface->dst_rect.y)
1284                 update_flags->bits.position_change = 1;
1285
1286         if (update_flags->bits.clock_change
1287                         || update_flags->bits.bandwidth_change)
1288                 return UPDATE_TYPE_FULL;
1289
1290         if (update_flags->bits.scaling_change
1291                         || update_flags->bits.position_change)
1292                 return UPDATE_TYPE_MED;
1293
1294         return UPDATE_TYPE_FAST;
1295 }
1296
1297 static enum surface_update_type det_surface_update(const struct dc *dc,
1298                 const struct dc_surface_update *u)
1299 {
1300         const struct dc_state *context = dc->current_state;
1301         enum surface_update_type type;
1302         enum surface_update_type overall_type = UPDATE_TYPE_FAST;
1303         union surface_update_flags *update_flags = &u->surface->update_flags;
1304
1305         update_flags->raw = 0; // Reset all flags
1306
1307         if (!is_surface_in_context(context, u->surface)) {
1308                 update_flags->bits.new_plane = 1;
1309                 return UPDATE_TYPE_FULL;
1310         }
1311
1312         type = get_plane_info_update_type(u);
1313         elevate_update_type(&overall_type, type);
1314
1315         type = get_scaling_info_update_type(u);
1316         elevate_update_type(&overall_type, type);
1317
1318         if (u->in_transfer_func)
1319                 update_flags->bits.in_transfer_func_change = 1;
1320
1321         if (u->input_csc_color_matrix)
1322                 update_flags->bits.input_csc_change = 1;
1323
1324         if (u->coeff_reduction_factor)
1325                 update_flags->bits.coeff_reduction_change = 1;
1326
1327         if (u->gamma) {
1328                 enum surface_pixel_format format = SURFACE_PIXEL_FORMAT_GRPH_BEGIN;
1329
1330                 if (u->plane_info)
1331                         format = u->plane_info->format;
1332                 else if (u->surface)
1333                         format = u->surface->format;
1334
1335                 if (dce_use_lut(format))
1336                         update_flags->bits.gamma_change = 1;
1337         }
1338
1339         if (update_flags->bits.in_transfer_func_change) {
1340                 type = UPDATE_TYPE_MED;
1341                 elevate_update_type(&overall_type, type);
1342         }
1343
1344         if (update_flags->bits.input_csc_change
1345                         || update_flags->bits.coeff_reduction_change
1346                         || update_flags->bits.gamma_change) {
1347                 type = UPDATE_TYPE_FULL;
1348                 elevate_update_type(&overall_type, type);
1349         }
1350
1351         return overall_type;
1352 }
1353
1354 static enum surface_update_type check_update_surfaces_for_stream(
1355                 struct dc *dc,
1356                 struct dc_surface_update *updates,
1357                 int surface_count,
1358                 struct dc_stream_update *stream_update,
1359                 const struct dc_stream_status *stream_status)
1360 {
1361         int i;
1362         enum surface_update_type overall_type = UPDATE_TYPE_FAST;
1363
1364         if (stream_status == NULL || stream_status->plane_count != surface_count)
1365                 return UPDATE_TYPE_FULL;
1366
1367         /* some stream updates require passive update */
1368         if (stream_update) {
1369                 if ((stream_update->src.height != 0) &&
1370                                 (stream_update->src.width != 0))
1371                         return UPDATE_TYPE_FULL;
1372
1373                 if ((stream_update->dst.height != 0) &&
1374                                 (stream_update->dst.width != 0))
1375                         return UPDATE_TYPE_FULL;
1376
1377                 if (stream_update->out_transfer_func)
1378                         return UPDATE_TYPE_FULL;
1379
1380                 if (stream_update->abm_level)
1381                         return UPDATE_TYPE_FULL;
1382
1383                 if (stream_update->dpms_off)
1384                         return UPDATE_TYPE_FULL;
1385         }
1386
1387         for (i = 0 ; i < surface_count; i++) {
1388                 enum surface_update_type type =
1389                                 det_surface_update(dc, &updates[i]);
1390
1391                 if (type == UPDATE_TYPE_FULL)
1392                         return type;
1393
1394                 elevate_update_type(&overall_type, type);
1395         }
1396
1397         return overall_type;
1398 }
1399
1400 /**
1401  * dc_check_update_surfaces_for_stream() - Determine update type (fast, med, or full)
1402  *
1403  * See :c:type:`enum surface_update_type <surface_update_type>` for explanation of update types
1404  */
1405 enum surface_update_type dc_check_update_surfaces_for_stream(
1406                 struct dc *dc,
1407                 struct dc_surface_update *updates,
1408                 int surface_count,
1409                 struct dc_stream_update *stream_update,
1410                 const struct dc_stream_status *stream_status)
1411 {
1412         int i;
1413         enum surface_update_type type;
1414
1415         for (i = 0; i < surface_count; i++)
1416                 updates[i].surface->update_flags.raw = 0;
1417
1418         type = check_update_surfaces_for_stream(dc, updates, surface_count, stream_update, stream_status);
1419         if (type == UPDATE_TYPE_FULL)
1420                 for (i = 0; i < surface_count; i++)
1421                         updates[i].surface->update_flags.raw = 0xFFFFFFFF;
1422
1423         return type;
1424 }
1425
1426 static struct dc_stream_status *stream_get_status(
1427         struct dc_state *ctx,
1428         struct dc_stream_state *stream)
1429 {
1430         uint8_t i;
1431
1432         for (i = 0; i < ctx->stream_count; i++) {
1433                 if (stream == ctx->streams[i]) {
1434                         return &ctx->stream_status[i];
1435                 }
1436         }
1437
1438         return NULL;
1439 }
1440
1441 static const enum surface_update_type update_surface_trace_level = UPDATE_TYPE_FULL;
1442
1443 static void copy_surface_update_to_plane(
1444                 struct dc_plane_state *surface,
1445                 struct dc_surface_update *srf_update)
1446 {
1447         if (srf_update->flip_addr) {
1448                 surface->address = srf_update->flip_addr->address;
1449                 surface->flip_immediate =
1450                         srf_update->flip_addr->flip_immediate;
1451                 surface->time.time_elapsed_in_us[surface->time.index] =
1452                         srf_update->flip_addr->flip_timestamp_in_us -
1453                                 surface->time.prev_update_time_in_us;
1454                 surface->time.prev_update_time_in_us =
1455                         srf_update->flip_addr->flip_timestamp_in_us;
1456                 surface->time.index++;
1457                 if (surface->time.index >= DC_PLANE_UPDATE_TIMES_MAX)
1458                         surface->time.index = 0;
1459         }
1460
1461         if (srf_update->scaling_info) {
1462                 surface->scaling_quality =
1463                                 srf_update->scaling_info->scaling_quality;
1464                 surface->dst_rect =
1465                                 srf_update->scaling_info->dst_rect;
1466                 surface->src_rect =
1467                                 srf_update->scaling_info->src_rect;
1468                 surface->clip_rect =
1469                                 srf_update->scaling_info->clip_rect;
1470         }
1471
1472         if (srf_update->plane_info) {
1473                 surface->color_space =
1474                                 srf_update->plane_info->color_space;
1475                 surface->format =
1476                                 srf_update->plane_info->format;
1477                 surface->plane_size =
1478                                 srf_update->plane_info->plane_size;
1479                 surface->rotation =
1480                                 srf_update->plane_info->rotation;
1481                 surface->horizontal_mirror =
1482                                 srf_update->plane_info->horizontal_mirror;
1483                 surface->stereo_format =
1484                                 srf_update->plane_info->stereo_format;
1485                 surface->tiling_info =
1486                                 srf_update->plane_info->tiling_info;
1487                 surface->visible =
1488                                 srf_update->plane_info->visible;
1489                 surface->per_pixel_alpha =
1490                                 srf_update->plane_info->per_pixel_alpha;
1491                 surface->global_alpha =
1492                                 srf_update->plane_info->global_alpha;
1493                 surface->global_alpha_value =
1494                                 srf_update->plane_info->global_alpha_value;
1495                 surface->dcc =
1496                                 srf_update->plane_info->dcc;
1497                 surface->sdr_white_level =
1498                                 srf_update->plane_info->sdr_white_level;
1499         }
1500
1501         if (srf_update->gamma &&
1502                         (surface->gamma_correction !=
1503                                         srf_update->gamma)) {
1504                 memcpy(&surface->gamma_correction->entries,
1505                         &srf_update->gamma->entries,
1506                         sizeof(struct dc_gamma_entries));
1507                 surface->gamma_correction->is_identity =
1508                         srf_update->gamma->is_identity;
1509                 surface->gamma_correction->num_entries =
1510                         srf_update->gamma->num_entries;
1511                 surface->gamma_correction->type =
1512                         srf_update->gamma->type;
1513         }
1514
1515         if (srf_update->in_transfer_func &&
1516                         (surface->in_transfer_func !=
1517                                 srf_update->in_transfer_func)) {
1518                 surface->in_transfer_func->sdr_ref_white_level =
1519                         srf_update->in_transfer_func->sdr_ref_white_level;
1520                 surface->in_transfer_func->tf =
1521                         srf_update->in_transfer_func->tf;
1522                 surface->in_transfer_func->type =
1523                         srf_update->in_transfer_func->type;
1524                 memcpy(&surface->in_transfer_func->tf_pts,
1525                         &srf_update->in_transfer_func->tf_pts,
1526                         sizeof(struct dc_transfer_func_distributed_points));
1527         }
1528
1529         if (srf_update->input_csc_color_matrix)
1530                 surface->input_csc_color_matrix =
1531                         *srf_update->input_csc_color_matrix;
1532
1533         if (srf_update->coeff_reduction_factor)
1534                 surface->coeff_reduction_factor =
1535                         *srf_update->coeff_reduction_factor;
1536 }
1537
1538 static void commit_planes_do_stream_update(struct dc *dc,
1539                 struct dc_stream_state *stream,
1540                 struct dc_stream_update *stream_update,
1541                 enum surface_update_type update_type,
1542                 struct dc_state *context)
1543 {
1544         int j;
1545
1546         // Stream updates
1547         for (j = 0; j < dc->res_pool->pipe_count; j++) {
1548                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
1549
1550                 if (!pipe_ctx->top_pipe &&
1551                         pipe_ctx->stream &&
1552                         pipe_ctx->stream == stream) {
1553
1554                         /* Fast update*/
1555                         // VRR program can be done as part of FAST UPDATE
1556                         if (stream_update->adjust)
1557                                 dc->hwss.set_drr(&pipe_ctx, 1,
1558                                         stream_update->adjust->v_total_min,
1559                                         stream_update->adjust->v_total_max);
1560
1561                         if (stream_update->vline0_config && pipe_ctx->stream_res.tg->funcs->program_vline_interrupt)
1562                                 pipe_ctx->stream_res.tg->funcs->program_vline_interrupt(
1563                                         pipe_ctx->stream_res.tg, VLINE0, stream->vline0_config);
1564
1565                         if (stream_update->vline1_config && pipe_ctx->stream_res.tg->funcs->program_vline_interrupt)
1566                                 pipe_ctx->stream_res.tg->funcs->program_vline_interrupt(
1567                                         pipe_ctx->stream_res.tg, VLINE1, stream->vline1_config);
1568
1569                         if ((stream_update->hdr_static_metadata && !stream->use_dynamic_meta) ||
1570                                         stream_update->vrr_infopacket ||
1571                                         stream_update->vsc_infopacket ||
1572                                         stream_update->vsp_infopacket) {
1573                                 resource_build_info_frame(pipe_ctx);
1574                                 dc->hwss.update_info_frame(pipe_ctx);
1575                         }
1576
1577                         if (stream_update->gamut_remap)
1578                                 dc_stream_set_gamut_remap(dc, stream);
1579
1580                         if (stream_update->output_csc_transform)
1581                                 dc_stream_program_csc_matrix(dc, stream);
1582
1583                         if (stream_update->dither_option) {
1584                                 resource_build_bit_depth_reduction_params(pipe_ctx->stream,
1585                                                                         &pipe_ctx->stream->bit_depth_params);
1586                                 pipe_ctx->stream_res.opp->funcs->opp_program_fmt(pipe_ctx->stream_res.opp,
1587                                                 &stream->bit_depth_params,
1588                                                 &stream->clamping);
1589                         }
1590
1591                         /* Full fe update*/
1592                         if (update_type == UPDATE_TYPE_FAST)
1593                                 continue;
1594
1595                         if (stream_update->dpms_off) {
1596                                 if (*stream_update->dpms_off) {
1597                                         core_link_disable_stream(pipe_ctx, KEEP_ACQUIRED_RESOURCE);
1598                                         dc->hwss.optimize_bandwidth(dc, dc->current_state);
1599                                 } else {
1600                                         dc->hwss.prepare_bandwidth(dc, dc->current_state);
1601                                         core_link_enable_stream(dc->current_state, pipe_ctx);
1602                                 }
1603                         }
1604
1605                         if (stream_update->abm_level && pipe_ctx->stream_res.abm) {
1606                                 if (pipe_ctx->stream_res.tg->funcs->is_blanked) {
1607                                         // if otg funcs defined check if blanked before programming
1608                                         if (!pipe_ctx->stream_res.tg->funcs->is_blanked(pipe_ctx->stream_res.tg))
1609                                                 pipe_ctx->stream_res.abm->funcs->set_abm_level(
1610                                                         pipe_ctx->stream_res.abm, stream->abm_level);
1611                                 } else
1612                                         pipe_ctx->stream_res.abm->funcs->set_abm_level(
1613                                                 pipe_ctx->stream_res.abm, stream->abm_level);
1614                         }
1615                 }
1616         }
1617 }
1618
1619 static void commit_planes_for_stream(struct dc *dc,
1620                 struct dc_surface_update *srf_updates,
1621                 int surface_count,
1622                 struct dc_stream_state *stream,
1623                 struct dc_stream_update *stream_update,
1624                 enum surface_update_type update_type,
1625                 struct dc_state *context)
1626 {
1627         int i, j;
1628         struct pipe_ctx *top_pipe_to_program = NULL;
1629
1630         if (update_type == UPDATE_TYPE_FULL) {
1631                 dc->hwss.prepare_bandwidth(dc, context);
1632                 context_clock_trace(dc, context);
1633         }
1634
1635         // Stream updates
1636         if (stream_update)
1637                 commit_planes_do_stream_update(dc, stream, stream_update, update_type, context);
1638
1639         if (surface_count == 0) {
1640                 /*
1641                  * In case of turning off screen, no need to program front end a second time.
1642                  * just return after program blank.
1643                  */
1644                 dc->hwss.apply_ctx_for_surface(dc, stream, 0, context);
1645                 return;
1646         }
1647
1648         // Update Type FULL, Surface updates
1649         for (j = 0; j < dc->res_pool->pipe_count; j++) {
1650                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
1651
1652                 if (!pipe_ctx->top_pipe &&
1653                         pipe_ctx->stream &&
1654                         pipe_ctx->stream == stream) {
1655                         struct dc_stream_status *stream_status = NULL;
1656
1657                         top_pipe_to_program = pipe_ctx;
1658
1659                         if (!pipe_ctx->plane_state)
1660                                 continue;
1661
1662                         /* Full fe update*/
1663                         if (update_type == UPDATE_TYPE_FAST)
1664                                 continue;
1665
1666                         stream_status =
1667                                 stream_get_status(context, pipe_ctx->stream);
1668
1669                         dc->hwss.apply_ctx_for_surface(
1670                                         dc, pipe_ctx->stream, stream_status->plane_count, context);
1671                 }
1672         }
1673
1674         // Update Type FAST, Surface updates
1675         if (update_type == UPDATE_TYPE_FAST) {
1676                 /* Lock the top pipe while updating plane addrs, since freesync requires
1677                  *  plane addr update event triggers to be synchronized.
1678                  *  top_pipe_to_program is expected to never be NULL
1679                  */
1680                 dc->hwss.pipe_control_lock(dc, top_pipe_to_program, true);
1681
1682                 /* Perform requested Updates */
1683                 for (i = 0; i < surface_count; i++) {
1684                         struct dc_plane_state *plane_state = srf_updates[i].surface;
1685
1686                         for (j = 0; j < dc->res_pool->pipe_count; j++) {
1687                                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
1688
1689                                 if (pipe_ctx->stream != stream)
1690                                         continue;
1691
1692                                 if (pipe_ctx->plane_state != plane_state)
1693                                         continue;
1694
1695                                 if (srf_updates[i].flip_addr)
1696                                         dc->hwss.update_plane_addr(dc, pipe_ctx);
1697                         }
1698                 }
1699
1700                 dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false);
1701         }
1702 }
1703
1704 void dc_commit_updates_for_stream(struct dc *dc,
1705                 struct dc_surface_update *srf_updates,
1706                 int surface_count,
1707                 struct dc_stream_state *stream,
1708                 struct dc_stream_update *stream_update,
1709                 struct dc_state *state)
1710 {
1711         const struct dc_stream_status *stream_status;
1712         enum surface_update_type update_type;
1713         struct dc_state *context;
1714         struct dc_context *dc_ctx = dc->ctx;
1715         int i, j;
1716
1717         stream_status = dc_stream_get_status(stream);
1718         context = dc->current_state;
1719
1720         update_type = dc_check_update_surfaces_for_stream(
1721                                 dc, srf_updates, surface_count, stream_update, stream_status);
1722
1723         if (update_type >= update_surface_trace_level)
1724                 update_surface_trace(dc, srf_updates, surface_count);
1725
1726
1727         if (update_type >= UPDATE_TYPE_FULL) {
1728
1729                 /* initialize scratch memory for building context */
1730                 context = dc_create_state();
1731                 if (context == NULL) {
1732                         DC_ERROR("Failed to allocate new validate context!\n");
1733                         return;
1734                 }
1735
1736                 dc_resource_state_copy_construct(state, context);
1737         }
1738
1739
1740         for (i = 0; i < surface_count; i++) {
1741                 struct dc_plane_state *surface = srf_updates[i].surface;
1742
1743                 copy_surface_update_to_plane(surface, &srf_updates[i]);
1744
1745                 if (update_type >= UPDATE_TYPE_MED) {
1746                         for (j = 0; j < dc->res_pool->pipe_count; j++) {
1747                                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
1748
1749                                 if (pipe_ctx->plane_state != surface)
1750                                         continue;
1751
1752                                 resource_build_scaling_params(pipe_ctx);
1753                         }
1754                 }
1755         }
1756
1757         commit_planes_for_stream(
1758                                 dc,
1759                                 srf_updates,
1760                                 surface_count,
1761                                 stream,
1762                                 stream_update,
1763                                 update_type,
1764                                 context);
1765         /*update current_State*/
1766         if (dc->current_state != context) {
1767
1768                 struct dc_state *old = dc->current_state;
1769
1770                 dc->current_state = context;
1771                 dc_release_state(old);
1772
1773         }
1774         /*let's use current_state to update watermark etc*/
1775         if (update_type >= UPDATE_TYPE_FULL)
1776                 dc_post_update_surfaces_to_stream(dc);
1777
1778         return;
1779
1780 }
1781
1782 uint8_t dc_get_current_stream_count(struct dc *dc)
1783 {
1784         return dc->current_state->stream_count;
1785 }
1786
1787 struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i)
1788 {
1789         if (i < dc->current_state->stream_count)
1790                 return dc->current_state->streams[i];
1791         return NULL;
1792 }
1793
1794 enum dc_irq_source dc_interrupt_to_irq_source(
1795                 struct dc *dc,
1796                 uint32_t src_id,
1797                 uint32_t ext_id)
1798 {
1799         return dal_irq_service_to_irq_source(dc->res_pool->irqs, src_id, ext_id);
1800 }
1801
1802 /**
1803  * dc_interrupt_set() - Enable/disable an AMD hw interrupt source
1804  */
1805 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable)
1806 {
1807
1808         if (dc == NULL)
1809                 return false;
1810
1811         return dal_irq_service_set(dc->res_pool->irqs, src, enable);
1812 }
1813
1814 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src)
1815 {
1816         dal_irq_service_ack(dc->res_pool->irqs, src);
1817 }
1818
1819 void dc_set_power_state(
1820         struct dc *dc,
1821         enum dc_acpi_cm_power_state power_state)
1822 {
1823         struct kref refcount;
1824
1825         switch (power_state) {
1826         case DC_ACPI_CM_POWER_STATE_D0:
1827                 dc_resource_state_construct(dc, dc->current_state);
1828
1829                 dc->hwss.init_hw(dc);
1830                 break;
1831         default:
1832                 ASSERT(dc->current_state->stream_count == 0);
1833                 /* Zero out the current context so that on resume we start with
1834                  * clean state, and dc hw programming optimizations will not
1835                  * cause any trouble.
1836                  */
1837
1838                 /* Preserve refcount */
1839                 refcount = dc->current_state->refcount;
1840                 dc_resource_state_destruct(dc->current_state);
1841                 memset(dc->current_state, 0,
1842                                 sizeof(*dc->current_state));
1843
1844                 dc->current_state->refcount = refcount;
1845
1846                 break;
1847         }
1848
1849 }
1850
1851 void dc_resume(struct dc *dc)
1852 {
1853
1854         uint32_t i;
1855
1856         for (i = 0; i < dc->link_count; i++)
1857                 core_link_resume(dc->links[i]);
1858 }
1859
1860 unsigned int dc_get_current_backlight_pwm(struct dc *dc)
1861 {
1862         struct abm *abm = dc->res_pool->abm;
1863
1864         if (abm)
1865                 return abm->funcs->get_current_backlight(abm);
1866
1867         return 0;
1868 }
1869
1870 unsigned int dc_get_target_backlight_pwm(struct dc *dc)
1871 {
1872         struct abm *abm = dc->res_pool->abm;
1873
1874         if (abm)
1875                 return abm->funcs->get_target_backlight(abm);
1876
1877         return 0;
1878 }
1879
1880 bool dc_is_dmcu_initialized(struct dc *dc)
1881 {
1882         struct dmcu *dmcu = dc->res_pool->dmcu;
1883
1884         if (dmcu)
1885                 return dmcu->funcs->is_dmcu_initialized(dmcu);
1886         return false;
1887 }
1888
1889 bool dc_submit_i2c(
1890                 struct dc *dc,
1891                 uint32_t link_index,
1892                 struct i2c_command *cmd)
1893 {
1894
1895         struct dc_link *link = dc->links[link_index];
1896         struct ddc_service *ddc = link->ddc;
1897         return dce_i2c_submit_command(
1898                 dc->res_pool,
1899                 ddc->ddc_pin,
1900                 cmd);
1901 }
1902
1903 static bool link_add_remote_sink_helper(struct dc_link *dc_link, struct dc_sink *sink)
1904 {
1905         if (dc_link->sink_count >= MAX_SINKS_PER_LINK) {
1906                 BREAK_TO_DEBUGGER();
1907                 return false;
1908         }
1909
1910         dc_sink_retain(sink);
1911
1912         dc_link->remote_sinks[dc_link->sink_count] = sink;
1913         dc_link->sink_count++;
1914
1915         return true;
1916 }
1917
1918 /**
1919  * dc_link_add_remote_sink() - Create a sink and attach it to an existing link
1920  *
1921  * EDID length is in bytes
1922  */
1923 struct dc_sink *dc_link_add_remote_sink(
1924                 struct dc_link *link,
1925                 const uint8_t *edid,
1926                 int len,
1927                 struct dc_sink_init_data *init_data)
1928 {
1929         struct dc_sink *dc_sink;
1930         enum dc_edid_status edid_status;
1931
1932         if (len > DC_MAX_EDID_BUFFER_SIZE) {
1933                 dm_error("Max EDID buffer size breached!\n");
1934                 return NULL;
1935         }
1936
1937         if (!init_data) {
1938                 BREAK_TO_DEBUGGER();
1939                 return NULL;
1940         }
1941
1942         if (!init_data->link) {
1943                 BREAK_TO_DEBUGGER();
1944                 return NULL;
1945         }
1946
1947         dc_sink = dc_sink_create(init_data);
1948
1949         if (!dc_sink)
1950                 return NULL;
1951
1952         memmove(dc_sink->dc_edid.raw_edid, edid, len);
1953         dc_sink->dc_edid.length = len;
1954
1955         if (!link_add_remote_sink_helper(
1956                         link,
1957                         dc_sink))
1958                 goto fail_add_sink;
1959
1960         edid_status = dm_helpers_parse_edid_caps(
1961                         link->ctx,
1962                         &dc_sink->dc_edid,
1963                         &dc_sink->edid_caps);
1964
1965         /*
1966          * Treat device as no EDID device if EDID
1967          * parsing fails
1968          */
1969         if (edid_status != EDID_OK) {
1970                 dc_sink->dc_edid.length = 0;
1971                 dm_error("Bad EDID, status%d!\n", edid_status);
1972         }
1973
1974         return dc_sink;
1975
1976 fail_add_sink:
1977         dc_sink_release(dc_sink);
1978         return NULL;
1979 }
1980
1981 /**
1982  * dc_link_remove_remote_sink() - Remove a remote sink from a dc_link
1983  *
1984  * Note that this just removes the struct dc_sink - it doesn't
1985  * program hardware or alter other members of dc_link
1986  */
1987 void dc_link_remove_remote_sink(struct dc_link *link, struct dc_sink *sink)
1988 {
1989         int i;
1990
1991         if (!link->sink_count) {
1992                 BREAK_TO_DEBUGGER();
1993                 return;
1994         }
1995
1996         for (i = 0; i < link->sink_count; i++) {
1997                 if (link->remote_sinks[i] == sink) {
1998                         dc_sink_release(sink);
1999                         link->remote_sinks[i] = NULL;
2000
2001                         /* shrink array to remove empty place */
2002                         while (i < link->sink_count - 1) {
2003                                 link->remote_sinks[i] = link->remote_sinks[i+1];
2004                                 i++;
2005                         }
2006                         link->remote_sinks[i] = NULL;
2007                         link->sink_count--;
2008                         return;
2009                 }
2010         }
2011 }
2012
2013 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info)
2014 {
2015         info->displayClock                              = (unsigned int)state->bw.dcn.clk.dispclk_khz;
2016         info->engineClock                               = (unsigned int)state->bw.dcn.clk.dcfclk_khz;
2017         info->memoryClock                               = (unsigned int)state->bw.dcn.clk.dramclk_khz;
2018         info->maxSupportedDppClock              = (unsigned int)state->bw.dcn.clk.max_supported_dppclk_khz;
2019         info->dppClock                                  = (unsigned int)state->bw.dcn.clk.dppclk_khz;
2020         info->socClock                                  = (unsigned int)state->bw.dcn.clk.socclk_khz;
2021         info->dcfClockDeepSleep                 = (unsigned int)state->bw.dcn.clk.dcfclk_deep_sleep_khz;
2022         info->fClock                                    = (unsigned int)state->bw.dcn.clk.fclk_khz;
2023         info->phyClock                                  = (unsigned int)state->bw.dcn.clk.phyclk_khz;
2024 }