drivers/gpu/drm/amd/display/dc/core/dc_link.c

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include <linux/slab.h>
  27
  28 #include "dm_services.h"
  29 #include "atom.h"
  30 #include "dm_helpers.h"
  31 #include "dc.h"
  32 #include "grph_object_id.h"
  33 #include "gpio_service_interface.h"
  34 #include "core_status.h"
  35 #include "dc_link_dp.h"
  36 #include "dc_link_ddc.h"
  37 #include "link_hwss.h"
  38 #include "opp.h"
  39
  40 #include "link_encoder.h"
  41 #include "hw_sequencer.h"
  42 #include "resource.h"
  43 #include "abm.h"
  44 #include "fixed31_32.h"
  45 #include "dpcd_defs.h"
  46 #include "dmcu.h"
  47 #include "hw/clk_mgr.h"
  48
  49 #define DC_LOGGER_INIT(logger)
  50
  51
  52 #define LINK_INFO(...) \
  53         DC_LOG_HW_HOTPLUG(  \
  54                 __VA_ARGS__)
  55
  56 #define RETIMER_REDRIVER_INFO(...) \
  57         DC_LOG_RETIMER_REDRIVER(  \
  58                 __VA_ARGS__)
  59 /*******************************************************************************
  60  * Private structures
  61  ******************************************************************************/
  62
  63 enum {
  64         PEAK_FACTOR_X1000 = 1006,
  65         /*
  66         * Some receivers fail to train on first try and are good
  67         * on subsequent tries. 2 retries should be plenty. If we
  68         * don't have a successful training then we don't expect to
  69         * ever get one.
  70         */
  71         LINK_TRAINING_MAX_VERIFY_RETRY = 2
  72 };
  73
  74 /*******************************************************************************
  75  * Private functions
  76  ******************************************************************************/
  77 static void destruct(struct dc_link *link)
  78 {
  79         int i;
  80
  81         if (link->hpd_gpio != NULL) {
  82                 dal_gpio_close(link->hpd_gpio);
  83                 dal_gpio_destroy_irq(&link->hpd_gpio);
  84                 link->hpd_gpio = NULL;
  85         }
  86
  87         if (link->ddc)
  88                 dal_ddc_service_destroy(&link->ddc);
  89
  90         if(link->link_enc)
  91                 link->link_enc->funcs->destroy(&link->link_enc);
  92
  93         if (link->local_sink)
  94                 dc_sink_release(link->local_sink);
  95
  96         for (i = 0; i < link->sink_count; ++i)
  97                 dc_sink_release(link->remote_sinks[i]);
  98 }
  99
 100 struct gpio *get_hpd_gpio(struct dc_bios *dcb,
 101                 struct graphics_object_id link_id,
 102                 struct gpio_service *gpio_service)
 103 {
 104         enum bp_result bp_result;
 105         struct graphics_object_hpd_info hpd_info;
 106         struct gpio_pin_info pin_info;
 107
 108         if (dcb->funcs->get_hpd_info(dcb, link_id, &hpd_info) != BP_RESULT_OK)
 109                 return NULL;
 110
 111         bp_result = dcb->funcs->get_gpio_pin_info(dcb,
 112                 hpd_info.hpd_int_gpio_uid, &pin_info);
 113
 114         if (bp_result != BP_RESULT_OK) {
 115                 ASSERT(bp_result == BP_RESULT_NORECORD);
 116                 return NULL;
 117         }
 118
 119         return dal_gpio_service_create_irq(
 120                 gpio_service,
 121                 pin_info.offset,
 122                 pin_info.mask);
 123 }
 124
 125 /*
 126  *  Function: program_hpd_filter
 127  *
 128  *  @brief
 129  *     Programs HPD filter on associated HPD line
 130  *
 131  *  @param [in] delay_on_connect_in_ms: Connect filter timeout
 132  *  @param [in] delay_on_disconnect_in_ms: Disconnect filter timeout
 133  *
 134  *  @return
 135  *     true on success, false otherwise
 136  */
 137 static bool program_hpd_filter(
 138         const struct dc_link *link)
 139 {
 140         bool result = false;
 141
 142         struct gpio *hpd;
 143
 144         int delay_on_connect_in_ms = 0;
 145         int delay_on_disconnect_in_ms = 0;
 146
 147         if (link->is_hpd_filter_disabled)
 148                 return false;
 149         /* Verify feature is supported */
 150         switch (link->connector_signal) {
 151         case SIGNAL_TYPE_DVI_SINGLE_LINK:
 152         case SIGNAL_TYPE_DVI_DUAL_LINK:
 153         case SIGNAL_TYPE_HDMI_TYPE_A:
 154                 /* Program hpd filter */
 155                 delay_on_connect_in_ms = 500;
 156                 delay_on_disconnect_in_ms = 100;
 157                 break;
 158         case SIGNAL_TYPE_DISPLAY_PORT:
 159         case SIGNAL_TYPE_DISPLAY_PORT_MST:
 160                 /* Program hpd filter to allow DP signal to settle */
 161                 /* 500: not able to detect MST <-> SST switch as HPD is low for
 162                  *      only 100ms on DELL U2413
 163                  * 0:   some passive dongle still show aux mode instead of i2c
 164                  * 20-50:not enough to hide bouncing HPD with passive dongle.
 165                  *      also see intermittent i2c read issues.
 166                  */
 167                 delay_on_connect_in_ms = 80;
 168                 delay_on_disconnect_in_ms = 0;
 169                 break;
 170         case SIGNAL_TYPE_LVDS:
 171         case SIGNAL_TYPE_EDP:
 172         default:
 173                 /* Don't program hpd filter */
 174                 return false;
 175         }
 176
 177         /* Obtain HPD handle */
 178         hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
 179
 180         if (!hpd)
 181                 return result;
 182
 183         /* Setup HPD filtering */
 184         if (dal_gpio_open(hpd, GPIO_MODE_INTERRUPT) == GPIO_RESULT_OK) {
 185                 struct gpio_hpd_config config;
 186
 187                 config.delay_on_connect = delay_on_connect_in_ms;
 188                 config.delay_on_disconnect = delay_on_disconnect_in_ms;
 189
 190                 dal_irq_setup_hpd_filter(hpd, &config);
 191
 192                 dal_gpio_close(hpd);
 193
 194                 result = true;
 195         } else {
 196                 ASSERT_CRITICAL(false);
 197         }
 198
 199         /* Release HPD handle */
 200         dal_gpio_destroy_irq(&hpd);
 201
 202         return result;
 203 }
 204
 205 /**
 206  * dc_link_detect_sink() - Determine if there is a sink connected
 207  *
 208  * @type: Returned connection type
 209  * Does not detect downstream devices, such as MST sinks
 210  * or display connected through active dongles
 211  */
 212 bool dc_link_detect_sink(struct dc_link *link, enum dc_connection_type *type)
 213 {
 214         uint32_t is_hpd_high = 0;
 215         struct gpio *hpd_pin;
 216
 217         if (link->connector_signal == SIGNAL_TYPE_LVDS) {
 218                 *type = dc_connection_single;
 219                 return true;
 220         }
 221
 222         if (link->connector_signal == SIGNAL_TYPE_EDP) {
 223                 /*in case it is not on*/
 224                 link->dc->hwss.edp_power_control(link, true);
 225                 link->dc->hwss.edp_wait_for_hpd_ready(link, true);
 226         }
 227
 228         /* todo: may need to lock gpio access */
 229         hpd_pin = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
 230         if (hpd_pin == NULL)
 231                 goto hpd_gpio_failure;
 232
 233         dal_gpio_open(hpd_pin, GPIO_MODE_INTERRUPT);
 234         dal_gpio_get_value(hpd_pin, &is_hpd_high);
 235         dal_gpio_close(hpd_pin);
 236         dal_gpio_destroy_irq(&hpd_pin);
 237
 238         if (is_hpd_high) {
 239                 *type = dc_connection_single;
 240                 /* TODO: need to do the actual detection */
 241         } else {
 242                 *type = dc_connection_none;
 243         }
 244
 245         return true;
 246
 247 hpd_gpio_failure:
 248         return false;
 249 }
 250
 251 static enum ddc_transaction_type get_ddc_transaction_type(
 252                 enum signal_type sink_signal)
 253 {
 254         enum ddc_transaction_type transaction_type = DDC_TRANSACTION_TYPE_NONE;
 255
 256         switch (sink_signal) {
 257         case SIGNAL_TYPE_DVI_SINGLE_LINK:
 258         case SIGNAL_TYPE_DVI_DUAL_LINK:
 259         case SIGNAL_TYPE_HDMI_TYPE_A:
 260         case SIGNAL_TYPE_LVDS:
 261         case SIGNAL_TYPE_RGB:
 262                 transaction_type = DDC_TRANSACTION_TYPE_I2C;
 263                 break;
 264
 265         case SIGNAL_TYPE_DISPLAY_PORT:
 266         case SIGNAL_TYPE_EDP:
 267                 transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
 268                 break;
 269
 270         case SIGNAL_TYPE_DISPLAY_PORT_MST:
 271                 /* MST does not use I2COverAux, but there is the
 272                  * SPECIAL use case for "immediate dwnstrm device
 273                  * access" (EPR#370830). */
 274                 transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
 275                 break;
 276
 277         default:
 278                 break;
 279         }
 280
 281         return transaction_type;
 282 }
 283
 284 static enum signal_type get_basic_signal_type(
 285         struct graphics_object_id encoder,
 286         struct graphics_object_id downstream)
 287 {
 288         if (downstream.type == OBJECT_TYPE_CONNECTOR) {
 289                 switch (downstream.id) {
 290                 case CONNECTOR_ID_SINGLE_LINK_DVII:
 291                         switch (encoder.id) {
 292                         case ENCODER_ID_INTERNAL_DAC1:
 293                         case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
 294                         case ENCODER_ID_INTERNAL_DAC2:
 295                         case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
 296                                 return SIGNAL_TYPE_RGB;
 297                         default:
 298                                 return SIGNAL_TYPE_DVI_SINGLE_LINK;
 299                         }
 300                 break;
 301                 case CONNECTOR_ID_DUAL_LINK_DVII:
 302                 {
 303                         switch (encoder.id) {
 304                         case ENCODER_ID_INTERNAL_DAC1:
 305                         case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
 306                         case ENCODER_ID_INTERNAL_DAC2:
 307                         case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
 308                                 return SIGNAL_TYPE_RGB;
 309                         default:
 310                                 return SIGNAL_TYPE_DVI_DUAL_LINK;
 311                         }
 312                 }
 313                 break;
 314                 case CONNECTOR_ID_SINGLE_LINK_DVID:
 315                         return SIGNAL_TYPE_DVI_SINGLE_LINK;
 316                 case CONNECTOR_ID_DUAL_LINK_DVID:
 317                         return SIGNAL_TYPE_DVI_DUAL_LINK;
 318                 case CONNECTOR_ID_VGA:
 319                         return SIGNAL_TYPE_RGB;
 320                 case CONNECTOR_ID_HDMI_TYPE_A:
 321                         return SIGNAL_TYPE_HDMI_TYPE_A;
 322                 case CONNECTOR_ID_LVDS:
 323                         return SIGNAL_TYPE_LVDS;
 324                 case CONNECTOR_ID_DISPLAY_PORT:
 325                         return SIGNAL_TYPE_DISPLAY_PORT;
 326                 case CONNECTOR_ID_EDP:
 327                         return SIGNAL_TYPE_EDP;
 328                 default:
 329                         return SIGNAL_TYPE_NONE;
 330                 }
 331         } else if (downstream.type == OBJECT_TYPE_ENCODER) {
 332                 switch (downstream.id) {
 333                 case ENCODER_ID_EXTERNAL_NUTMEG:
 334                 case ENCODER_ID_EXTERNAL_TRAVIS:
 335                         return SIGNAL_TYPE_DISPLAY_PORT;
 336                 default:
 337                         return SIGNAL_TYPE_NONE;
 338                 }
 339         }
 340
 341         return SIGNAL_TYPE_NONE;
 342 }
 343
 344 /**
 345  * dc_link_is_dp_sink_present() - Check if there is a native DP
 346  * or passive DP-HDMI dongle connected
 347  */
 348 bool dc_link_is_dp_sink_present(struct dc_link *link)
 349 {
 350         enum gpio_result gpio_result;
 351         uint32_t clock_pin = 0;
 352         uint8_t retry = 0;
 353         struct ddc *ddc;
 354
 355         enum connector_id connector_id =
 356                 dal_graphics_object_id_get_connector_id(link->link_id);
 357
 358         bool present =
 359                 ((connector_id == CONNECTOR_ID_DISPLAY_PORT) ||
 360                 (connector_id == CONNECTOR_ID_EDP));
 361
 362         ddc = dal_ddc_service_get_ddc_pin(link->ddc);
 363
 364         if (!ddc) {
 365                 BREAK_TO_DEBUGGER();
 366                 return present;
 367         }
 368
 369         /* Open GPIO and set it to I2C mode */
 370         /* Note: this GpioMode_Input will be converted
 371          * to GpioConfigType_I2cAuxDualMode in GPIO component,
 372          * which indicates we need additional delay */
 373
 374         if (GPIO_RESULT_OK != dal_ddc_open(
 375                 ddc, GPIO_MODE_INPUT, GPIO_DDC_CONFIG_TYPE_MODE_I2C)) {
 376                 dal_gpio_destroy_ddc(&ddc);
 377
 378                 return present;
 379         }
 380
 381         /*
 382          * Read GPIO: DP sink is present if both clock and data pins are zero
 383          *
 384          * [W/A] plug-unplug DP cable, sometimes customer board has
 385          * one short pulse on clk_pin(1V, < 1ms). DP will be config to HDMI/DVI
 386          * then monitor can't br light up. Add retry 3 times
 387          * But in real passive dongle, it need additional 3ms to detect
 388          */
 389         do {
 390                 gpio_result = dal_gpio_get_value(ddc->pin_clock, &clock_pin);
 391                 ASSERT(gpio_result == GPIO_RESULT_OK);
 392                 if (clock_pin)
 393                         udelay(1000);
 394                 else
 395                         break;
 396         } while (retry++ < 3);
 397
 398         present = (gpio_result == GPIO_RESULT_OK) && !clock_pin;
 399
 400         dal_ddc_close(ddc);
 401
 402         return present;
 403 }
 404
 405 /*
 406  * @brief
 407  * Detect output sink type
 408  */
 409 static enum signal_type link_detect_sink(
 410         struct dc_link *link,
 411         enum dc_detect_reason reason)
 412 {
 413         enum signal_type result = get_basic_signal_type(
 414                 link->link_enc->id, link->link_id);
 415
 416         /* Internal digital encoder will detect only dongles
 417          * that require digital signal */
 418
 419         /* Detection mechanism is different
 420          * for different native connectors.
 421          * LVDS connector supports only LVDS signal;
 422          * PCIE is a bus slot, the actual connector needs to be detected first;
 423          * eDP connector supports only eDP signal;
 424          * HDMI should check straps for audio */
 425
 426         /* PCIE detects the actual connector on add-on board */
 427
 428         if (link->link_id.id == CONNECTOR_ID_PCIE) {
 429                 /* ZAZTODO implement PCIE add-on card detection */
 430         }
 431
 432         switch (link->link_id.id) {
 433         case CONNECTOR_ID_HDMI_TYPE_A: {
 434                 /* check audio support:
 435                  * if native HDMI is not supported, switch to DVI */
 436                 struct audio_support *aud_support = &link->dc->res_pool->audio_support;
 437
 438                 if (!aud_support->hdmi_audio_native)
 439                         if (link->link_id.id == CONNECTOR_ID_HDMI_TYPE_A)
 440                                 result = SIGNAL_TYPE_DVI_SINGLE_LINK;
 441         }
 442         break;
 443         case CONNECTOR_ID_DISPLAY_PORT: {
 444                 /* DP HPD short pulse. Passive DP dongle will not
 445                  * have short pulse
 446                  */
 447                 if (reason != DETECT_REASON_HPDRX) {
 448                         /* Check whether DP signal detected: if not -
 449                          * we assume signal is DVI; it could be corrected
 450                          * to HDMI after dongle detection
 451                          */
 452                         if (!dm_helpers_is_dp_sink_present(link))
 453                                 result = SIGNAL_TYPE_DVI_SINGLE_LINK;
 454                 }
 455         }
 456         break;
 457         default:
 458         break;
 459         }
 460
 461         return result;
 462 }
 463
 464 static enum signal_type decide_signal_from_strap_and_dongle_type(
 465                 enum display_dongle_type dongle_type,
 466                 struct audio_support *audio_support)
 467 {
 468         enum signal_type signal = SIGNAL_TYPE_NONE;
 469
 470         switch (dongle_type) {
 471         case DISPLAY_DONGLE_DP_HDMI_DONGLE:
 472                 if (audio_support->hdmi_audio_on_dongle)
 473                         signal =  SIGNAL_TYPE_HDMI_TYPE_A;
 474                 else
 475                         signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 476                 break;
 477         case DISPLAY_DONGLE_DP_DVI_DONGLE:
 478                 signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 479                 break;
 480         case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE:
 481                 if (audio_support->hdmi_audio_native)
 482                         signal =  SIGNAL_TYPE_HDMI_TYPE_A;
 483                 else
 484                         signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 485                 break;
 486         default:
 487                 signal = SIGNAL_TYPE_NONE;
 488                 break;
 489         }
 490
 491         return signal;
 492 }
 493
 494 static enum signal_type dp_passive_dongle_detection(
 495                 struct ddc_service *ddc,
 496                 struct display_sink_capability *sink_cap,
 497                 struct audio_support *audio_support)
 498 {
 499         dal_ddc_service_i2c_query_dp_dual_mode_adaptor(
 500                                                 ddc, sink_cap);
 501         return decide_signal_from_strap_and_dongle_type(
 502                         sink_cap->dongle_type,
 503                         audio_support);
 504 }
 505
 506 static void link_disconnect_sink(struct dc_link *link)
 507 {
 508         if (link->local_sink) {
 509                 dc_sink_release(link->local_sink);
 510                 link->local_sink = NULL;
 511         }
 512
 513         link->dpcd_sink_count = 0;
 514 }
 515
 516 static void link_disconnect_remap(struct dc_sink *prev_sink, struct dc_link *link)
 517 {
 518         dc_sink_release(link->local_sink);
 519         link->local_sink = prev_sink;
 520 }
 521
 522
 523 static void read_edp_current_link_settings_on_detect(struct dc_link *link)
 524 {
 525         union lane_count_set lane_count_set = { {0} };
 526         uint8_t link_bw_set;
 527         uint8_t link_rate_set;
 528         uint32_t read_dpcd_retry_cnt = 10;
 529         enum dc_status status = DC_ERROR_UNEXPECTED;
 530         int i;
 531         union max_down_spread max_down_spread = { {0} };
 532
 533         // Read DPCD 00101h to find out the number of lanes currently set
 534         for (i = 0; i < read_dpcd_retry_cnt; i++) {
 535                 status = core_link_read_dpcd(
 536                                 link,
 537                                 DP_LANE_COUNT_SET,
 538                                 &lane_count_set.raw,
 539                                 sizeof(lane_count_set));
 540                 /* First DPCD read after VDD ON can fail if the particular board
 541                  * does not have HPD pin wired correctly. So if DPCD read fails,
 542                  * which it should never happen, retry a few times. Target worst
 543                  * case scenario of 80 ms.
 544                  */
 545                 if (status == DC_OK) {
 546                         link->cur_link_settings.lane_count = lane_count_set.bits.LANE_COUNT_SET;
 547                         break;
 548                 }
 549
 550                 msleep(8);
 551         }
 552
 553         // Read DPCD 00100h to find if standard link rates are set
 554         core_link_read_dpcd(link, DP_LINK_BW_SET,
 555                         &link_bw_set, sizeof(link_bw_set));
 556
 557         if (link_bw_set == 0) {
 558                 /* If standard link rates are not being used,
 559                  * Read DPCD 00115h to find the link rate set used
 560                  */
 561                 core_link_read_dpcd(link, DP_LINK_RATE_SET,
 562                                 &link_rate_set, sizeof(link_rate_set));
 563
 564                 if (link_rate_set < link->dpcd_caps.edp_supported_link_rates_count) {
 565                         link->cur_link_settings.link_rate =
 566                                 link->dpcd_caps.edp_supported_link_rates[link_rate_set];
 567                         link->cur_link_settings.link_rate_set = link_rate_set;
 568                         link->cur_link_settings.use_link_rate_set = true;
 569                 }
 570         } else {
 571                 link->cur_link_settings.link_rate = link_bw_set;
 572                 link->cur_link_settings.use_link_rate_set = false;
 573         }
 574         // Read DPCD 00003h to find the max down spread.
 575         core_link_read_dpcd(link, DP_MAX_DOWNSPREAD,
 576                         &max_down_spread.raw, sizeof(max_down_spread));
 577         link->cur_link_settings.link_spread =
 578                 max_down_spread.bits.MAX_DOWN_SPREAD ?
 579                 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
 580 }
 581
 582 static bool detect_dp(
 583         struct dc_link *link,
 584         struct display_sink_capability *sink_caps,
 585         bool *converter_disable_audio,
 586         struct audio_support *audio_support,
 587         enum dc_detect_reason reason)
 588 {
 589         bool boot = false;
 590         sink_caps->signal = link_detect_sink(link, reason);
 591         sink_caps->transaction_type =
 592                 get_ddc_transaction_type(sink_caps->signal);
 593
 594         if (sink_caps->transaction_type == DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
 595                 sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT;
 596                 if (!detect_dp_sink_caps(link))
 597                         return false;
 598
 599                 if (is_mst_supported(link)) {
 600                         sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
 601                         link->type = dc_connection_mst_branch;
 602
 603                         dal_ddc_service_set_transaction_type(
 604                                                         link->ddc,
 605                                                         sink_caps->transaction_type);
 606
 607                         /*
 608                          * This call will initiate MST topology discovery. Which
 609                          * will detect MST ports and add new DRM connector DRM
 610                          * framework. Then read EDID via remote i2c over aux. In
 611                          * the end, will notify DRM detect result and save EDID
 612                          * into DRM framework.
 613                          *
 614                          * .detect is called by .fill_modes.
 615                          * .fill_modes is called by user mode ioctl
 616                          * DRM_IOCTL_MODE_GETCONNECTOR.
 617                          *
 618                          * .get_modes is called by .fill_modes.
 619                          *
 620                          * call .get_modes, AMDGPU DM implementation will create
 621                          * new dc_sink and add to dc_link. For long HPD plug
 622                          * in/out, MST has its own handle.
 623                          *
 624                          * Therefore, just after dc_create, link->sink is not
 625                          * created for MST until user mode app calls
 626                          * DRM_IOCTL_MODE_GETCONNECTOR.
 627                          *
 628                          * Need check ->sink usages in case ->sink = NULL
 629                          * TODO: s3 resume check
 630                          */
 631                         if (reason == DETECT_REASON_BOOT)
 632                                 boot = true;
 633
 634                         dm_helpers_dp_update_branch_info(
 635                                 link->ctx,
 636                                 link);
 637
 638                         if (!dm_helpers_dp_mst_start_top_mgr(
 639                                 link->ctx,
 640                                 link, boot)) {
 641                                 /* MST not supported */
 642                                 link->type = dc_connection_single;
 643                                 sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT;
 644                         }
 645                 }
 646
 647                 if (link->type != dc_connection_mst_branch &&
 648                         is_dp_active_dongle(link)) {
 649                         /* DP active dongles */
 650                         link->type = dc_connection_active_dongle;
 651                         if (!link->dpcd_caps.sink_count.bits.SINK_COUNT) {
 652                                 /*
 653                                  * active dongle unplug processing for short irq
 654                                  */
 655                                 link_disconnect_sink(link);
 656                                 return true;
 657                         }
 658
 659                         if (link->dpcd_caps.dongle_type != DISPLAY_DONGLE_DP_HDMI_CONVERTER)
 660                                 *converter_disable_audio = true;
 661                 }
 662         } else {
 663                 /* DP passive dongles */
 664                 sink_caps->signal = dp_passive_dongle_detection(link->ddc,
 665                                 sink_caps,
 666                                 audio_support);
 667         }
 668
 669         return true;
 670 }
 671
 672 static bool is_same_edid(struct dc_edid *old_edid, struct dc_edid *new_edid)
 673 {
 674         if (old_edid->length != new_edid->length)
 675                 return false;
 676
 677         if (new_edid->length == 0)
 678                 return false;
 679
 680         return (memcmp(old_edid->raw_edid, new_edid->raw_edid, new_edid->length) == 0);
 681 }
 682
 683 bool wait_for_alt_mode(struct dc_link *link)
 684 {
 685
 686         /**
 687          * something is terribly wrong if time out is > 200ms. (5Hz)
 688          * 500 microseconds * 400 tries us 200 ms
 689          **/
 690         unsigned int sleep_time_in_microseconds = 500;
 691         unsigned int tries_allowed = 400;
 692         bool is_in_alt_mode;
 693         unsigned long long enter_timestamp;
 694         unsigned long long finish_timestamp;
 695         unsigned long long time_taken_in_ns;
 696         int tries_taken;
 697
 698         DC_LOGGER_INIT(link->ctx->logger);
 699
 700         if (link->link_enc->funcs->is_in_alt_mode == NULL)
 701                 return true;
 702
 703         is_in_alt_mode = link->link_enc->funcs->is_in_alt_mode(link->link_enc);
 704         DC_LOG_WARNING("DP Alt mode state on HPD: %d\n", is_in_alt_mode);
 705
 706         if (is_in_alt_mode)
 707                 return true;
 708
 709         enter_timestamp = dm_get_timestamp(link->ctx);
 710
 711         for (tries_taken = 0; tries_taken < tries_allowed; tries_taken++) {
 712                 udelay(sleep_time_in_microseconds);
 713                 /* ask the link if alt mode is enabled, if so return ok */
 714                 if (link->link_enc->funcs->is_in_alt_mode(link->link_enc)) {
 715
 716                         finish_timestamp = dm_get_timestamp(link->ctx);
 717                         time_taken_in_ns = dm_get_elapse_time_in_ns(
 718                                 link->ctx, finish_timestamp, enter_timestamp);
 719                         DC_LOG_WARNING("Alt mode entered finished after %llu ms\n",
 720                                        div_u64(time_taken_in_ns, 1000000));
 721                         return true;
 722                 }
 723
 724         }
 725         finish_timestamp = dm_get_timestamp(link->ctx);
 726         time_taken_in_ns = dm_get_elapse_time_in_ns(link->ctx, finish_timestamp,
 727                                                     enter_timestamp);
 728         DC_LOG_WARNING("Alt mode has timed out after %llu ms\n",
 729                         div_u64(time_taken_in_ns, 1000000));
 730         return false;
 731 }
 732
 733 /**
 734  * dc_link_detect() - Detect if a sink is attached to a given link
 735  *
 736  * link->local_sink is created or destroyed as needed.
 737  *
 738  * This does not create remote sinks but will trigger DM
 739  * to start MST detection if a branch is detected.
 740  */
 741 bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason)
 742 {
 743         struct dc_sink_init_data sink_init_data = { 0 };
 744         struct display_sink_capability sink_caps = { 0 };
 745         uint8_t i;
 746         bool converter_disable_audio = false;
 747         struct audio_support *aud_support = &link->dc->res_pool->audio_support;
 748         bool same_edid = false;
 749         enum dc_edid_status edid_status;
 750         struct dc_context *dc_ctx = link->ctx;
 751         struct dc_sink *sink = NULL;
 752         struct dc_sink *prev_sink = NULL;
 753         struct dpcd_caps prev_dpcd_caps;
 754         bool same_dpcd = true;
 755         enum dc_connection_type new_connection_type = dc_connection_none;
 756         DC_LOGGER_INIT(link->ctx->logger);
 757
 758         if (dc_is_virtual_signal(link->connector_signal))
 759                 return false;
 760
 761         if ((link->connector_signal == SIGNAL_TYPE_LVDS ||
 762                         link->connector_signal == SIGNAL_TYPE_EDP) &&
 763                         link->local_sink)
 764                 return true;
 765
 766         if (false == dc_link_detect_sink(link, &new_connection_type)) {
 767                 BREAK_TO_DEBUGGER();
 768                 return false;
 769         }
 770
 771         prev_sink = link->local_sink;
 772         if (prev_sink != NULL) {
 773                 dc_sink_retain(prev_sink);
 774                 memcpy(&prev_dpcd_caps, &link->dpcd_caps, sizeof(struct dpcd_caps));
 775         }
 776         link_disconnect_sink(link);
 777
 778         if (new_connection_type != dc_connection_none) {
 779                 link->type = new_connection_type;
 780                 link->link_state_valid = false;
 781
 782                 /* From Disconnected-to-Connected. */
 783                 switch (link->connector_signal) {
 784                 case SIGNAL_TYPE_HDMI_TYPE_A: {
 785                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 786                         if (aud_support->hdmi_audio_native)
 787                                 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
 788                         else
 789                                 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 790                         break;
 791                 }
 792
 793                 case SIGNAL_TYPE_DVI_SINGLE_LINK: {
 794                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 795                         sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 796                         break;
 797                 }
 798
 799                 case SIGNAL_TYPE_DVI_DUAL_LINK: {
 800                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 801                         sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
 802                         break;
 803                 }
 804
 805                 case SIGNAL_TYPE_LVDS: {
 806                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 807                         sink_caps.signal = SIGNAL_TYPE_LVDS;
 808                         break;
 809                 }
 810
 811                 case SIGNAL_TYPE_EDP: {
 812                         read_edp_current_link_settings_on_detect(link);
 813                         detect_edp_sink_caps(link);
 814                         sink_caps.transaction_type =
 815                                 DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
 816                         sink_caps.signal = SIGNAL_TYPE_EDP;
 817                         break;
 818                 }
 819
 820                 case SIGNAL_TYPE_DISPLAY_PORT: {
 821                         /* wa HPD high coming too early*/
 822                         if (link->link_enc->features.flags.bits.DP_IS_USB_C == 1) {
 823
 824                                 /* if alt mode times out, return false */
 825                                 if (wait_for_alt_mode(link) == false) {
 826                                         return false;
 827                                 }
 828                         }
 829
 830                         if (!detect_dp(
 831                                 link,
 832                                 &sink_caps,
 833                                 &converter_disable_audio,
 834                                 aud_support, reason)) {
 835                                 if (prev_sink != NULL)
 836                                         dc_sink_release(prev_sink);
 837                                 return false;
 838                         }
 839
 840                         // Check if dpcp block is the same
 841                         if (prev_sink != NULL) {
 842                                 if (memcmp(&link->dpcd_caps, &prev_dpcd_caps, sizeof(struct dpcd_caps)))
 843                                         same_dpcd = false;
 844                         }
 845                         /* Active dongle plug in without display or downstream unplug*/
 846                         if (link->type == dc_connection_active_dongle &&
 847                                 link->dpcd_caps.sink_count.bits.SINK_COUNT == 0) {
 848                                 if (prev_sink != NULL) {
 849                                         /* Downstream unplug */
 850                                         dc_sink_release(prev_sink);
 851                                 } else {
 852                                         /* Empty dongle plug in */
 853                                         dp_verify_link_cap_with_retries(link,
 854                                                         &link->reported_link_cap,
 855                                                         LINK_TRAINING_MAX_VERIFY_RETRY);
 856                                 }
 857                                 return true;
 858                         }
 859
 860                         if (link->type == dc_connection_mst_branch) {
 861                                 LINK_INFO("link=%d, mst branch is now Connected\n",
 862                                         link->link_index);
 863                                 /* Need to setup mst link_cap struct here
 864                                  * otherwise dc_link_detect() will leave mst link_cap
 865                                  * empty which leads to allocate_mst_payload() has "0"
 866                                  * pbn_per_slot value leading to exception on dc_fixpt_div()
 867                                  */
 868                                 link->verified_link_cap = link->reported_link_cap;
 869                                 if (prev_sink != NULL)
 870                                         dc_sink_release(prev_sink);
 871                                 return false;
 872                         }
 873
 874                         break;
 875                 }
 876
 877                 default:
 878                         DC_ERROR("Invalid connector type! signal:%d\n",
 879                                 link->connector_signal);
 880                         if (prev_sink != NULL)
 881                                 dc_sink_release(prev_sink);
 882                         return false;
 883                 } /* switch() */
 884
 885                 if (link->dpcd_caps.sink_count.bits.SINK_COUNT)
 886                         link->dpcd_sink_count = link->dpcd_caps.sink_count.
 887                                         bits.SINK_COUNT;
 888                 else
 889                         link->dpcd_sink_count = 1;
 890
 891                 dal_ddc_service_set_transaction_type(
 892                                                 link->ddc,
 893                                                 sink_caps.transaction_type);
 894
 895                 link->aux_mode = dal_ddc_service_is_in_aux_transaction_mode(
 896                                 link->ddc);
 897
 898                 sink_init_data.link = link;
 899                 sink_init_data.sink_signal = sink_caps.signal;
 900
 901                 sink = dc_sink_create(&sink_init_data);
 902                 if (!sink) {
 903                         DC_ERROR("Failed to create sink!\n");
 904                         if (prev_sink != NULL)
 905                                 dc_sink_release(prev_sink);
 906                         return false;
 907                 }
 908
 909                 sink->link->dongle_max_pix_clk = sink_caps.max_hdmi_pixel_clock;
 910                 sink->converter_disable_audio = converter_disable_audio;
 911
 912                 /* dc_sink_create returns a new reference */
 913                 link->local_sink = sink;
 914
 915                 edid_status = dm_helpers_read_local_edid(
 916                                 link->ctx,
 917                                 link,
 918                                 sink);
 919
 920                 switch (edid_status) {
 921                 case EDID_BAD_CHECKSUM:
 922                         DC_LOG_ERROR("EDID checksum invalid.\n");
 923                         break;
 924                 case EDID_NO_RESPONSE:
 925                         DC_LOG_ERROR("No EDID read.\n");
 926
 927                         /*
 928                          * Abort detection for non-DP connectors if we have
 929                          * no EDID
 930                          *
 931                          * DP needs to report as connected if HDP is high
 932                          * even if we have no EDID in order to go to
 933                          * fail-safe mode
 934                          */
 935                         if (dc_is_hdmi_signal(link->connector_signal) ||
 936                             dc_is_dvi_signal(link->connector_signal)) {
 937                                 if (prev_sink != NULL)
 938                                         dc_sink_release(prev_sink);
 939
 940                                 return false;
 941                         }
 942                 default:
 943                         break;
 944                 }
 945
 946                 // Check if edid is the same
 947                 if ((prev_sink != NULL) && ((edid_status == EDID_THE_SAME) || (edid_status == EDID_OK)))
 948                         same_edid = is_same_edid(&prev_sink->dc_edid, &sink->dc_edid);
 949
 950                 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
 951                         sink_caps.transaction_type == DDC_TRANSACTION_TYPE_I2C_OVER_AUX &&
 952                         reason != DETECT_REASON_HPDRX) {
 953                         /*
 954                          * TODO debug why Dell 2413 doesn't like
 955                          *  two link trainings
 956                          */
 957
 958                         /* deal with non-mst cases */
 959                         dp_verify_link_cap_with_retries(link,
 960                                         &link->reported_link_cap,
 961                                         LINK_TRAINING_MAX_VERIFY_RETRY);
 962                 } else {
 963                         // If edid is the same, then discard new sink and revert back to original sink
 964                         if (same_edid) {
 965                                 link_disconnect_remap(prev_sink, link);
 966                                 sink = prev_sink;
 967                                 prev_sink = NULL;
 968
 969                         }
 970                 }
 971
 972                 /* HDMI-DVI Dongle */
 973                 if (sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A &&
 974                                 !sink->edid_caps.edid_hdmi)
 975                         sink->sink_signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 976
 977                 /* Connectivity log: detection */
 978                 for (i = 0; i < sink->dc_edid.length / DC_EDID_BLOCK_SIZE; i++) {
 979                         CONN_DATA_DETECT(link,
 980                                         &sink->dc_edid.raw_edid[i * DC_EDID_BLOCK_SIZE],
 981                                         DC_EDID_BLOCK_SIZE,
 982                                         "%s: [Block %d] ", sink->edid_caps.display_name, i);
 983                 }
 984
 985                 DC_LOG_DETECTION_EDID_PARSER("%s: "
 986                         "manufacturer_id = %X, "
 987                         "product_id = %X, "
 988                         "serial_number = %X, "
 989                         "manufacture_week = %d, "
 990                         "manufacture_year = %d, "
 991                         "display_name = %s, "
 992                         "speaker_flag = %d, "
 993                         "audio_mode_count = %d\n",
 994                         __func__,
 995                         sink->edid_caps.manufacturer_id,
 996                         sink->edid_caps.product_id,
 997                         sink->edid_caps.serial_number,
 998                         sink->edid_caps.manufacture_week,
 999                         sink->edid_caps.manufacture_year,
1000                         sink->edid_caps.display_name,
1001                         sink->edid_caps.speaker_flags,
1002                         sink->edid_caps.audio_mode_count);
1003
1004                 for (i = 0; i < sink->edid_caps.audio_mode_count; i++) {
1005                         DC_LOG_DETECTION_EDID_PARSER("%s: mode number = %d, "
1006                                 "format_code = %d, "
1007                                 "channel_count = %d, "
1008                                 "sample_rate = %d, "
1009                                 "sample_size = %d\n",
1010                                 __func__,
1011                                 i,
1012                                 sink->edid_caps.audio_modes[i].format_code,
1013                                 sink->edid_caps.audio_modes[i].channel_count,
1014                                 sink->edid_caps.audio_modes[i].sample_rate,
1015                                 sink->edid_caps.audio_modes[i].sample_size);
1016                 }
1017
1018         } else {
1019                 /* From Connected-to-Disconnected. */
1020                 if (link->type == dc_connection_mst_branch) {
1021                         LINK_INFO("link=%d, mst branch is now Disconnected\n",
1022                                 link->link_index);
1023
1024                         dm_helpers_dp_mst_stop_top_mgr(link->ctx, link);
1025
1026                         link->mst_stream_alloc_table.stream_count = 0;
1027                         memset(link->mst_stream_alloc_table.stream_allocations, 0, sizeof(link->mst_stream_alloc_table.stream_allocations));
1028                 }
1029
1030                 link->type = dc_connection_none;
1031                 sink_caps.signal = SIGNAL_TYPE_NONE;
1032                 /* When we unplug a passive DP-HDMI dongle connection, dongle_max_pix_clk
1033                  *  is not cleared. If we emulate a DP signal on this connection, it thinks
1034                  *  the dongle is still there and limits the number of modes we can emulate.
1035                  *  Clear dongle_max_pix_clk on disconnect to fix this
1036                  */
1037                 link->dongle_max_pix_clk = 0;
1038         }
1039
1040         LINK_INFO("link=%d, dc_sink_in=%p is now %s prev_sink=%p dpcd same=%d edid same=%d\n",
1041                 link->link_index, sink,
1042                 (sink_caps.signal == SIGNAL_TYPE_NONE ?
1043                         "Disconnected":"Connected"), prev_sink,
1044                         same_dpcd, same_edid);
1045
1046         if (prev_sink != NULL)
1047                 dc_sink_release(prev_sink);
1048
1049         return true;
1050 }
1051
1052 bool dc_link_get_hpd_state(struct dc_link *dc_link)
1053 {
1054         uint32_t state;
1055
1056         dal_gpio_lock_pin(dc_link->hpd_gpio);
1057         dal_gpio_get_value(dc_link->hpd_gpio, &state);
1058         dal_gpio_unlock_pin(dc_link->hpd_gpio);
1059
1060         return state;
1061 }
1062
1063 static enum hpd_source_id get_hpd_line(
1064                 struct dc_link *link)
1065 {
1066         struct gpio *hpd;
1067         enum hpd_source_id hpd_id = HPD_SOURCEID_UNKNOWN;
1068
1069         hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
1070
1071         if (hpd) {
1072                 switch (dal_irq_get_source(hpd)) {
1073                 case DC_IRQ_SOURCE_HPD1:
1074                         hpd_id = HPD_SOURCEID1;
1075                 break;
1076                 case DC_IRQ_SOURCE_HPD2:
1077                         hpd_id = HPD_SOURCEID2;
1078                 break;
1079                 case DC_IRQ_SOURCE_HPD3:
1080                         hpd_id = HPD_SOURCEID3;
1081                 break;
1082                 case DC_IRQ_SOURCE_HPD4:
1083                         hpd_id = HPD_SOURCEID4;
1084                 break;
1085                 case DC_IRQ_SOURCE_HPD5:
1086                         hpd_id = HPD_SOURCEID5;
1087                 break;
1088                 case DC_IRQ_SOURCE_HPD6:
1089                         hpd_id = HPD_SOURCEID6;
1090                 break;
1091                 default:
1092                         BREAK_TO_DEBUGGER();
1093                 break;
1094                 }
1095
1096                 dal_gpio_destroy_irq(&hpd);
1097         }
1098
1099         return hpd_id;
1100 }
1101
1102 static enum channel_id get_ddc_line(struct dc_link *link)
1103 {
1104         struct ddc *ddc;
1105         enum channel_id channel = CHANNEL_ID_UNKNOWN;
1106
1107         ddc = dal_ddc_service_get_ddc_pin(link->ddc);
1108
1109         if (ddc) {
1110                 switch (dal_ddc_get_line(ddc)) {
1111                 case GPIO_DDC_LINE_DDC1:
1112                         channel = CHANNEL_ID_DDC1;
1113                         break;
1114                 case GPIO_DDC_LINE_DDC2:
1115                         channel = CHANNEL_ID_DDC2;
1116                         break;
1117                 case GPIO_DDC_LINE_DDC3:
1118                         channel = CHANNEL_ID_DDC3;
1119                         break;
1120                 case GPIO_DDC_LINE_DDC4:
1121                         channel = CHANNEL_ID_DDC4;
1122                         break;
1123                 case GPIO_DDC_LINE_DDC5:
1124                         channel = CHANNEL_ID_DDC5;
1125                         break;
1126                 case GPIO_DDC_LINE_DDC6:
1127                         channel = CHANNEL_ID_DDC6;
1128                         break;
1129                 case GPIO_DDC_LINE_DDC_VGA:
1130                         channel = CHANNEL_ID_DDC_VGA;
1131                         break;
1132                 case GPIO_DDC_LINE_I2C_PAD:
1133                         channel = CHANNEL_ID_I2C_PAD;
1134                         break;
1135                 default:
1136                         BREAK_TO_DEBUGGER();
1137                         break;
1138                 }
1139         }
1140
1141         return channel;
1142 }
1143
1144 static enum transmitter translate_encoder_to_transmitter(
1145         struct graphics_object_id encoder)
1146 {
1147         switch (encoder.id) {
1148         case ENCODER_ID_INTERNAL_UNIPHY:
1149                 switch (encoder.enum_id) {
1150                 case ENUM_ID_1:
1151                         return TRANSMITTER_UNIPHY_A;
1152                 case ENUM_ID_2:
1153                         return TRANSMITTER_UNIPHY_B;
1154                 default:
1155                         return TRANSMITTER_UNKNOWN;
1156                 }
1157         break;
1158         case ENCODER_ID_INTERNAL_UNIPHY1:
1159                 switch (encoder.enum_id) {
1160                 case ENUM_ID_1:
1161                         return TRANSMITTER_UNIPHY_C;
1162                 case ENUM_ID_2:
1163                         return TRANSMITTER_UNIPHY_D;
1164                 default:
1165                         return TRANSMITTER_UNKNOWN;
1166                 }
1167         break;
1168         case ENCODER_ID_INTERNAL_UNIPHY2:
1169                 switch (encoder.enum_id) {
1170                 case ENUM_ID_1:
1171                         return TRANSMITTER_UNIPHY_E;
1172                 case ENUM_ID_2:
1173                         return TRANSMITTER_UNIPHY_F;
1174                 default:
1175                         return TRANSMITTER_UNKNOWN;
1176                 }
1177         break;
1178         case ENCODER_ID_INTERNAL_UNIPHY3:
1179                 switch (encoder.enum_id) {
1180                 case ENUM_ID_1:
1181                         return TRANSMITTER_UNIPHY_G;
1182                 default:
1183                         return TRANSMITTER_UNKNOWN;
1184                 }
1185         break;
1186         case ENCODER_ID_EXTERNAL_NUTMEG:
1187                 switch (encoder.enum_id) {
1188                 case ENUM_ID_1:
1189                         return TRANSMITTER_NUTMEG_CRT;
1190                 default:
1191                         return TRANSMITTER_UNKNOWN;
1192                 }
1193         break;
1194         case ENCODER_ID_EXTERNAL_TRAVIS:
1195                 switch (encoder.enum_id) {
1196                 case ENUM_ID_1:
1197                         return TRANSMITTER_TRAVIS_CRT;
1198                 case ENUM_ID_2:
1199                         return TRANSMITTER_TRAVIS_LCD;
1200                 default:
1201                         return TRANSMITTER_UNKNOWN;
1202                 }
1203         break;
1204         default:
1205                 return TRANSMITTER_UNKNOWN;
1206         }
1207 }
1208
1209 static bool construct(
1210         struct dc_link *link,
1211         const struct link_init_data *init_params)
1212 {
1213         uint8_t i;
1214         struct ddc_service_init_data ddc_service_init_data = { { 0 } };
1215         struct dc_context *dc_ctx = init_params->ctx;
1216         struct encoder_init_data enc_init_data = { 0 };
1217         struct integrated_info info = {{{ 0 }}};
1218         struct dc_bios *bios = init_params->dc->ctx->dc_bios;
1219         const struct dc_vbios_funcs *bp_funcs = bios->funcs;
1220         DC_LOGGER_INIT(dc_ctx->logger);
1221
1222         link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
1223         link->irq_source_hpd_rx = DC_IRQ_SOURCE_INVALID;
1224
1225         link->link_status.dpcd_caps = &link->dpcd_caps;
1226
1227         link->dc = init_params->dc;
1228         link->ctx = dc_ctx;
1229         link->link_index = init_params->link_index;
1230
1231         memset(&link->preferred_training_settings, 0, sizeof(struct dc_link_training_overrides));
1232         memset(&link->preferred_link_setting, 0, sizeof(struct dc_link_settings));
1233
1234         link->link_id = bios->funcs->get_connector_id(bios, init_params->connector_index);
1235
1236         if (link->link_id.type != OBJECT_TYPE_CONNECTOR) {
1237                 dm_output_to_console("%s: Invalid Connector ObjectID from Adapter Service for connector index:%d! type %d expected %d\n",
1238                          __func__, init_params->connector_index,
1239                          link->link_id.type, OBJECT_TYPE_CONNECTOR);
1240                 goto create_fail;
1241         }
1242
1243         if (link->dc->res_pool->funcs->link_init)
1244                 link->dc->res_pool->funcs->link_init(link);
1245
1246         link->hpd_gpio = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
1247         if (link->hpd_gpio != NULL) {
1248                 dal_gpio_open(link->hpd_gpio, GPIO_MODE_INTERRUPT);
1249                 dal_gpio_unlock_pin(link->hpd_gpio);
1250                 link->irq_source_hpd = dal_irq_get_source(link->hpd_gpio);
1251         }
1252
1253         switch (link->link_id.id) {
1254         case CONNECTOR_ID_HDMI_TYPE_A:
1255                 link->connector_signal = SIGNAL_TYPE_HDMI_TYPE_A;
1256
1257                 break;
1258         case CONNECTOR_ID_SINGLE_LINK_DVID:
1259         case CONNECTOR_ID_SINGLE_LINK_DVII:
1260                 link->connector_signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1261                 break;
1262         case CONNECTOR_ID_DUAL_LINK_DVID:
1263         case CONNECTOR_ID_DUAL_LINK_DVII:
1264                 link->connector_signal = SIGNAL_TYPE_DVI_DUAL_LINK;
1265                 break;
1266         case CONNECTOR_ID_DISPLAY_PORT:
1267                 link->connector_signal =        SIGNAL_TYPE_DISPLAY_PORT;
1268
1269                 if (link->hpd_gpio != NULL)
1270                         link->irq_source_hpd_rx =
1271                                         dal_irq_get_rx_source(link->hpd_gpio);
1272
1273                 break;
1274         case CONNECTOR_ID_EDP:
1275                 link->connector_signal = SIGNAL_TYPE_EDP;
1276
1277                 if (link->hpd_gpio != NULL) {
1278                         link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
1279                         link->irq_source_hpd_rx =
1280                                         dal_irq_get_rx_source(link->hpd_gpio);
1281                 }
1282                 break;
1283         case CONNECTOR_ID_LVDS:
1284                 link->connector_signal = SIGNAL_TYPE_LVDS;
1285                 break;
1286         default:
1287                 DC_LOG_WARNING("Unsupported Connector type:%d!\n", link->link_id.id);
1288                 goto create_fail;
1289         }
1290
1291         /* TODO: #DAL3 Implement id to str function.*/
1292         LINK_INFO("Connector[%d] description:"
1293                         "signal %d\n",
1294                         init_params->connector_index,
1295                         link->connector_signal);
1296
1297         ddc_service_init_data.ctx = link->ctx;
1298         ddc_service_init_data.id = link->link_id;
1299         ddc_service_init_data.link = link;
1300         link->ddc = dal_ddc_service_create(&ddc_service_init_data);
1301
1302         if (link->ddc == NULL) {
1303                 DC_ERROR("Failed to create ddc_service!\n");
1304                 goto ddc_create_fail;
1305         }
1306
1307         link->ddc_hw_inst =
1308                 dal_ddc_get_line(
1309                         dal_ddc_service_get_ddc_pin(link->ddc));
1310
1311         enc_init_data.ctx = dc_ctx;
1312         bp_funcs->get_src_obj(dc_ctx->dc_bios, link->link_id, 0, &enc_init_data.encoder);
1313         enc_init_data.connector = link->link_id;
1314         enc_init_data.channel = get_ddc_line(link);
1315         enc_init_data.hpd_source = get_hpd_line(link);
1316
1317         link->hpd_src = enc_init_data.hpd_source;
1318
1319         enc_init_data.transmitter =
1320                         translate_encoder_to_transmitter(enc_init_data.encoder);
1321         link->link_enc = link->dc->res_pool->funcs->link_enc_create(
1322                                                                 &enc_init_data);
1323
1324         if (link->link_enc == NULL) {
1325                 DC_ERROR("Failed to create link encoder!\n");
1326                 goto link_enc_create_fail;
1327         }
1328
1329         link->link_enc_hw_inst = link->link_enc->transmitter;
1330
1331         for (i = 0; i < 4; i++) {
1332                 if (BP_RESULT_OK !=
1333                                 bp_funcs->get_device_tag(dc_ctx->dc_bios, link->link_id, i, &link->device_tag)) {
1334                         DC_ERROR("Failed to find device tag!\n");
1335                         goto device_tag_fail;
1336                 }
1337
1338                 /* Look for device tag that matches connector signal,
1339                  * CRT for rgb, LCD for other supported signal tyes
1340                  */
1341                 if (!bp_funcs->is_device_id_supported(dc_ctx->dc_bios, link->device_tag.dev_id))
1342                         continue;
1343                 if (link->device_tag.dev_id.device_type == DEVICE_TYPE_CRT
1344                         && link->connector_signal != SIGNAL_TYPE_RGB)
1345                         continue;
1346                 if (link->device_tag.dev_id.device_type == DEVICE_TYPE_LCD
1347                         && link->connector_signal == SIGNAL_TYPE_RGB)
1348                         continue;
1349                 break;
1350         }
1351
1352         if (bios->integrated_info)
1353                 info = *bios->integrated_info;
1354
1355         /* Look for channel mapping corresponding to connector and device tag */
1356         for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; i++) {
1357                 struct external_display_path *path =
1358                         &info.ext_disp_conn_info.path[i];
1359                 if (path->device_connector_id.enum_id == link->link_id.enum_id
1360                         && path->device_connector_id.id == link->link_id.id
1361                         && path->device_connector_id.type == link->link_id.type) {
1362
1363                         if (link->device_tag.acpi_device != 0
1364                                 && path->device_acpi_enum == link->device_tag.acpi_device) {
1365                                 link->ddi_channel_mapping = path->channel_mapping;
1366                                 link->chip_caps = path->caps;
1367                         } else if (path->device_tag ==
1368                                         link->device_tag.dev_id.raw_device_tag) {
1369                                 link->ddi_channel_mapping = path->channel_mapping;
1370                                 link->chip_caps = path->caps;
1371                         }
1372                         break;
1373                 }
1374         }
1375
1376         /*
1377          * TODO check if GPIO programmed correctly
1378          *
1379          * If GPIO isn't programmed correctly HPD might not rise or drain
1380          * fast enough, leading to bounces.
1381          */
1382         program_hpd_filter(link);
1383
1384         return true;
1385 device_tag_fail:
1386         link->link_enc->funcs->destroy(&link->link_enc);
1387 link_enc_create_fail:
1388         dal_ddc_service_destroy(&link->ddc);
1389 ddc_create_fail:
1390 create_fail:
1391
1392         if (link->hpd_gpio != NULL) {
1393                 dal_gpio_destroy_irq(&link->hpd_gpio);
1394                 link->hpd_gpio = NULL;
1395         }
1396
1397         return false;
1398 }
1399
1400 /*******************************************************************************
1401  * Public functions
1402  ******************************************************************************/
1403 struct dc_link *link_create(const struct link_init_data *init_params)
1404 {
1405         struct dc_link *link =
1406                         kzalloc(sizeof(*link), GFP_KERNEL);
1407
1408         if (NULL == link)
1409                 goto alloc_fail;
1410
1411         if (false == construct(link, init_params))
1412                 goto construct_fail;
1413
1414         return link;
1415
1416 construct_fail:
1417         kfree(link);
1418
1419 alloc_fail:
1420         return NULL;
1421 }
1422
1423 void link_destroy(struct dc_link **link)
1424 {
1425         destruct(*link);
1426         kfree(*link);
1427         *link = NULL;
1428 }
1429
1430 static void enable_stream_features(struct pipe_ctx *pipe_ctx)
1431 {
1432         struct dc_stream_state *stream = pipe_ctx->stream;
1433         struct dc_link *link = stream->link;
1434         union down_spread_ctrl old_downspread;
1435         union down_spread_ctrl new_downspread;
1436
1437         core_link_read_dpcd(link, DP_DOWNSPREAD_CTRL,
1438                         &old_downspread.raw, sizeof(old_downspread));
1439
1440         new_downspread.raw = old_downspread.raw;
1441
1442         new_downspread.bits.IGNORE_MSA_TIMING_PARAM =
1443                         (stream->ignore_msa_timing_param) ? 1 : 0;
1444
1445         if (new_downspread.raw != old_downspread.raw) {
1446                 core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
1447                         &new_downspread.raw, sizeof(new_downspread));
1448         }
1449 }
1450
1451 static enum dc_status enable_link_dp(
1452                 struct dc_state *state,
1453                 struct pipe_ctx *pipe_ctx)
1454 {
1455         struct dc_stream_state *stream = pipe_ctx->stream;
1456         enum dc_status status;
1457         bool skip_video_pattern;
1458         struct dc_link *link = stream->link;
1459         struct dc_link_settings link_settings = {0};
1460         enum dp_panel_mode panel_mode;
1461 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
1462         bool fec_enable;
1463 #endif
1464         int i;
1465         bool apply_seamless_boot_optimization = false;
1466
1467         // check for seamless boot
1468         for (i = 0; i < state->stream_count; i++) {
1469                 if (state->streams[i]->apply_seamless_boot_optimization) {
1470                         apply_seamless_boot_optimization = true;
1471                         break;
1472                 }
1473         }
1474
1475         /* get link settings for video mode timing */
1476         decide_link_settings(stream, &link_settings);
1477
1478         if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP) {
1479                 /* If link settings are different than current and link already enabled
1480                  * then need to disable before programming to new rate.
1481                  */
1482                 if (link->link_status.link_active &&
1483                         (link->cur_link_settings.lane_count != link_settings.lane_count ||
1484                          link->cur_link_settings.link_rate != link_settings.link_rate)) {
1485                         dp_disable_link_phy(link, pipe_ctx->stream->signal);
1486                 }
1487
1488                 /*in case it is not on*/
1489                 link->dc->hwss.edp_power_control(link, true);
1490                 link->dc->hwss.edp_wait_for_hpd_ready(link, true);
1491         }
1492
1493         pipe_ctx->stream_res.pix_clk_params.requested_sym_clk =
1494                         link_settings.link_rate * LINK_RATE_REF_FREQ_IN_KHZ;
1495         if (!apply_seamless_boot_optimization)
1496                 state->clk_mgr->funcs->update_clocks(state->clk_mgr, state, false);
1497
1498         dp_enable_link_phy(
1499                 link,
1500                 pipe_ctx->stream->signal,
1501                 pipe_ctx->clock_source->id,
1502                 &link_settings);
1503
1504         if (stream->sink_patches.dppowerup_delay > 0) {
1505                 int delay_dp_power_up_in_ms = stream->sink_patches.dppowerup_delay;
1506
1507                 msleep(delay_dp_power_up_in_ms);
1508         }
1509
1510         panel_mode = dp_get_panel_mode(link);
1511         dp_set_panel_mode(link, panel_mode);
1512
1513         skip_video_pattern = true;
1514
1515         if (link_settings.link_rate == LINK_RATE_LOW)
1516                         skip_video_pattern = false;
1517
1518         if (link->aux_access_disabled) {
1519                 dc_link_dp_perform_link_training_skip_aux(link, &link_settings);
1520
1521                 link->cur_link_settings = link_settings;
1522                 status = DC_OK;
1523         } else if (perform_link_training_with_retries(
1524                         link,
1525                         &link_settings,
1526                         skip_video_pattern,
1527                         LINK_TRAINING_ATTEMPTS)) {
1528                 link->cur_link_settings = link_settings;
1529                 status = DC_OK;
1530         }
1531         else
1532                 status = DC_FAIL_DP_LINK_TRAINING;
1533
1534 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
1535         if (link->preferred_training_settings.fec_enable != NULL)
1536                 fec_enable = *link->preferred_training_settings.fec_enable;
1537         else
1538                 fec_enable = true;
1539
1540         dp_set_fec_enable(link, fec_enable);
1541 #endif
1542         return status;
1543 }
1544
1545 static enum dc_status enable_link_edp(
1546                 struct dc_state *state,
1547                 struct pipe_ctx *pipe_ctx)
1548 {
1549         enum dc_status status;
1550
1551         status = enable_link_dp(state, pipe_ctx);
1552
1553         return status;
1554 }
1555
1556 static enum dc_status enable_link_dp_mst(
1557                 struct dc_state *state,
1558                 struct pipe_ctx *pipe_ctx)
1559 {
1560         struct dc_link *link = pipe_ctx->stream->link;
1561
1562         /* sink signal type after MST branch is MST. Multiple MST sinks
1563          * share one link. Link DP PHY is enable or training only once.
1564          */
1565         if (link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN)
1566                 return DC_OK;
1567
1568         /* clear payload table */
1569         dm_helpers_dp_mst_clear_payload_allocation_table(link->ctx, link);
1570
1571         /* to make sure the pending down rep can be processed
1572          * before enabling the link
1573          */
1574         dm_helpers_dp_mst_poll_pending_down_reply(link->ctx, link);
1575
1576         /* set the sink to MST mode before enabling the link */
1577         dp_enable_mst_on_sink(link, true);
1578
1579         return enable_link_dp(state, pipe_ctx);
1580 }
1581
1582 static bool get_ext_hdmi_settings(struct pipe_ctx *pipe_ctx,
1583                 enum engine_id eng_id,
1584                 struct ext_hdmi_settings *settings)
1585 {
1586         bool result = false;
1587         int i = 0;
1588         struct integrated_info *integrated_info =
1589                         pipe_ctx->stream->ctx->dc_bios->integrated_info;
1590
1591         if (integrated_info == NULL)
1592                 return false;
1593
1594         /*
1595          * Get retimer settings from sbios for passing SI eye test for DCE11
1596          * The setting values are varied based on board revision and port id
1597          * Therefore the setting values of each ports is passed by sbios.
1598          */
1599
1600         // Check if current bios contains ext Hdmi settings
1601         if (integrated_info->gpu_cap_info & 0x20) {
1602                 switch (eng_id) {
1603                 case ENGINE_ID_DIGA:
1604                         settings->slv_addr = integrated_info->dp0_ext_hdmi_slv_addr;
1605                         settings->reg_num = integrated_info->dp0_ext_hdmi_6g_reg_num;
1606                         settings->reg_num_6g = integrated_info->dp0_ext_hdmi_6g_reg_num;
1607                         memmove(settings->reg_settings,
1608                                         integrated_info->dp0_ext_hdmi_reg_settings,
1609                                         sizeof(integrated_info->dp0_ext_hdmi_reg_settings));
1610                         memmove(settings->reg_settings_6g,
1611                                         integrated_info->dp0_ext_hdmi_6g_reg_settings,
1612                                         sizeof(integrated_info->dp0_ext_hdmi_6g_reg_settings));
1613                         result = true;
1614                         break;
1615                 case ENGINE_ID_DIGB:
1616                         settings->slv_addr = integrated_info->dp1_ext_hdmi_slv_addr;
1617                         settings->reg_num = integrated_info->dp1_ext_hdmi_6g_reg_num;
1618                         settings->reg_num_6g = integrated_info->dp1_ext_hdmi_6g_reg_num;
1619                         memmove(settings->reg_settings,
1620                                         integrated_info->dp1_ext_hdmi_reg_settings,
1621                                         sizeof(integrated_info->dp1_ext_hdmi_reg_settings));
1622                         memmove(settings->reg_settings_6g,
1623                                         integrated_info->dp1_ext_hdmi_6g_reg_settings,
1624                                         sizeof(integrated_info->dp1_ext_hdmi_6g_reg_settings));
1625                         result = true;
1626                         break;
1627                 case ENGINE_ID_DIGC:
1628                         settings->slv_addr = integrated_info->dp2_ext_hdmi_slv_addr;
1629                         settings->reg_num = integrated_info->dp2_ext_hdmi_6g_reg_num;
1630                         settings->reg_num_6g = integrated_info->dp2_ext_hdmi_6g_reg_num;
1631                         memmove(settings->reg_settings,
1632                                         integrated_info->dp2_ext_hdmi_reg_settings,
1633                                         sizeof(integrated_info->dp2_ext_hdmi_reg_settings));
1634                         memmove(settings->reg_settings_6g,
1635                                         integrated_info->dp2_ext_hdmi_6g_reg_settings,
1636                                         sizeof(integrated_info->dp2_ext_hdmi_6g_reg_settings));
1637                         result = true;
1638                         break;
1639                 case ENGINE_ID_DIGD:
1640                         settings->slv_addr = integrated_info->dp3_ext_hdmi_slv_addr;
1641                         settings->reg_num = integrated_info->dp3_ext_hdmi_6g_reg_num;
1642                         settings->reg_num_6g = integrated_info->dp3_ext_hdmi_6g_reg_num;
1643                         memmove(settings->reg_settings,
1644                                         integrated_info->dp3_ext_hdmi_reg_settings,
1645                                         sizeof(integrated_info->dp3_ext_hdmi_reg_settings));
1646                         memmove(settings->reg_settings_6g,
1647                                         integrated_info->dp3_ext_hdmi_6g_reg_settings,
1648                                         sizeof(integrated_info->dp3_ext_hdmi_6g_reg_settings));
1649                         result = true;
1650                         break;
1651                 default:
1652                         break;
1653                 }
1654
1655                 if (result == true) {
1656                         // Validate settings from bios integrated info table
1657                         if (settings->slv_addr == 0)
1658                                 return false;
1659                         if (settings->reg_num > 9)
1660                                 return false;
1661                         if (settings->reg_num_6g > 3)
1662                                 return false;
1663
1664                         for (i = 0; i < settings->reg_num; i++) {
1665                                 if (settings->reg_settings[i].i2c_reg_index > 0x20)
1666                                         return false;
1667                         }
1668
1669                         for (i = 0; i < settings->reg_num_6g; i++) {
1670                                 if (settings->reg_settings_6g[i].i2c_reg_index > 0x20)
1671                                         return false;
1672                         }
1673                 }
1674         }
1675
1676         return result;
1677 }
1678
1679 static bool i2c_write(struct pipe_ctx *pipe_ctx,
1680                 uint8_t address, uint8_t *buffer, uint32_t length)
1681 {
1682         struct i2c_command cmd = {0};
1683         struct i2c_payload payload = {0};
1684
1685         memset(&payload, 0, sizeof(payload));
1686         memset(&cmd, 0, sizeof(cmd));
1687
1688         cmd.number_of_payloads = 1;
1689         cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
1690         cmd.speed = pipe_ctx->stream->ctx->dc->caps.i2c_speed_in_khz;
1691
1692         payload.address = address;
1693         payload.data = buffer;
1694         payload.length = length;
1695         payload.write = true;
1696         cmd.payloads = &payload;
1697
1698         if (dm_helpers_submit_i2c(pipe_ctx->stream->ctx,
1699                         pipe_ctx->stream->link, &cmd))
1700                 return true;
1701
1702         return false;
1703 }
1704
1705 static void write_i2c_retimer_setting(
1706                 struct pipe_ctx *pipe_ctx,
1707                 bool is_vga_mode,
1708                 bool is_over_340mhz,
1709                 struct ext_hdmi_settings *settings)
1710 {
1711         uint8_t slave_address = (settings->slv_addr >> 1);
1712         uint8_t buffer[2];
1713         const uint8_t apply_rx_tx_change = 0x4;
1714         uint8_t offset = 0xA;
1715         uint8_t value = 0;
1716         int i = 0;
1717         bool i2c_success = false;
1718         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
1719
1720         memset(&buffer, 0, sizeof(buffer));
1721
1722         /* Start Ext-Hdmi programming*/
1723
1724         for (i = 0; i < settings->reg_num; i++) {
1725                 /* Apply 3G settings */
1726                 if (settings->reg_settings[i].i2c_reg_index <= 0x20) {
1727
1728                         buffer[0] = settings->reg_settings[i].i2c_reg_index;
1729                         buffer[1] = settings->reg_settings[i].i2c_reg_val;
1730                         i2c_success = i2c_write(pipe_ctx, slave_address,
1731                                                 buffer, sizeof(buffer));
1732                         RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
1733                                 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
1734                                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1735
1736                         if (!i2c_success)
1737                                 /* Write failure */
1738                                 ASSERT(i2c_success);
1739
1740                         /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A
1741                          * needs to be set to 1 on every 0xA-0xC write.
1742                          */
1743                         if (settings->reg_settings[i].i2c_reg_index == 0xA ||
1744                                 settings->reg_settings[i].i2c_reg_index == 0xB ||
1745                                 settings->reg_settings[i].i2c_reg_index == 0xC) {
1746
1747                                 /* Query current value from offset 0xA */
1748                                 if (settings->reg_settings[i].i2c_reg_index == 0xA)
1749                                         value = settings->reg_settings[i].i2c_reg_val;
1750                                 else {
1751                                         i2c_success =
1752                                                 dal_ddc_service_query_ddc_data(
1753                                                 pipe_ctx->stream->link->ddc,
1754                                                 slave_address, &offset, 1, &value, 1);
1755                                         if (!i2c_success)
1756                                                 /* Write failure */
1757                                                 ASSERT(i2c_success);
1758                                 }
1759
1760                                 buffer[0] = offset;
1761                                 /* Set APPLY_RX_TX_CHANGE bit to 1 */
1762                                 buffer[1] = value | apply_rx_tx_change;
1763                                 i2c_success = i2c_write(pipe_ctx, slave_address,
1764                                                 buffer, sizeof(buffer));
1765                                 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
1766                                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1767                                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
1768                                 if (!i2c_success)
1769                                         /* Write failure */
1770                                         ASSERT(i2c_success);
1771                         }
1772                 }
1773         }
1774
1775         /* Apply 3G settings */
1776         if (is_over_340mhz) {
1777                 for (i = 0; i < settings->reg_num_6g; i++) {
1778                         /* Apply 3G settings */
1779                         if (settings->reg_settings[i].i2c_reg_index <= 0x20) {
1780
1781                                 buffer[0] = settings->reg_settings_6g[i].i2c_reg_index;
1782                                 buffer[1] = settings->reg_settings_6g[i].i2c_reg_val;
1783                                 i2c_success = i2c_write(pipe_ctx, slave_address,
1784                                                         buffer, sizeof(buffer));
1785                                 RETIMER_REDRIVER_INFO("above 340Mhz: retimer write to slave_address = 0x%x,\
1786                                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1787                                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
1788
1789                                 if (!i2c_success)
1790                                         /* Write failure */
1791                                         ASSERT(i2c_success);
1792
1793                                 /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A
1794                                  * needs to be set to 1 on every 0xA-0xC write.
1795                                  */
1796                                 if (settings->reg_settings_6g[i].i2c_reg_index == 0xA ||
1797                                         settings->reg_settings_6g[i].i2c_reg_index == 0xB ||
1798                                         settings->reg_settings_6g[i].i2c_reg_index == 0xC) {
1799
1800                                         /* Query current value from offset 0xA */
1801                                         if (settings->reg_settings_6g[i].i2c_reg_index == 0xA)
1802                                                 value = settings->reg_settings_6g[i].i2c_reg_val;
1803                                         else {
1804                                                 i2c_success =
1805                                                                 dal_ddc_service_query_ddc_data(
1806                                                                 pipe_ctx->stream->link->ddc,
1807                                                                 slave_address, &offset, 1, &value, 1);
1808                                                 if (!i2c_success)
1809                                                         /* Write failure */
1810                                                         ASSERT(i2c_success);
1811                                         }
1812
1813                                         buffer[0] = offset;
1814                                         /* Set APPLY_RX_TX_CHANGE bit to 1 */
1815                                         buffer[1] = value | apply_rx_tx_change;
1816                                         i2c_success = i2c_write(pipe_ctx, slave_address,
1817                                                         buffer, sizeof(buffer));
1818                                         RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
1819                                                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1820                                                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1821                                         if (!i2c_success)
1822                                                 /* Write failure */
1823                                                 ASSERT(i2c_success);
1824                                 }
1825                         }
1826                 }
1827         }
1828
1829         if (is_vga_mode) {
1830                 /* Program additional settings if using 640x480 resolution */
1831
1832                 /* Write offset 0xFF to 0x01 */
1833                 buffer[0] = 0xff;
1834                 buffer[1] = 0x01;
1835                 i2c_success = i2c_write(pipe_ctx, slave_address,
1836                                 buffer, sizeof(buffer));
1837                 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
1838                                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1839                                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1840                 if (!i2c_success)
1841                         /* Write failure */
1842                         ASSERT(i2c_success);
1843
1844                 /* Write offset 0x00 to 0x23 */
1845                 buffer[0] = 0x00;
1846                 buffer[1] = 0x23;
1847                 i2c_success = i2c_write(pipe_ctx, slave_address,
1848                                 buffer, sizeof(buffer));
1849                 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
1850                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1851                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
1852                 if (!i2c_success)
1853                         /* Write failure */
1854                         ASSERT(i2c_success);
1855
1856                 /* Write offset 0xff to 0x00 */
1857                 buffer[0] = 0xff;
1858                 buffer[1] = 0x00;
1859                 i2c_success = i2c_write(pipe_ctx, slave_address,
1860                                 buffer, sizeof(buffer));
1861                 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
1862                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1863                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
1864                 if (!i2c_success)
1865                         /* Write failure */
1866                         ASSERT(i2c_success);
1867
1868         }
1869 }
1870
1871 static void write_i2c_default_retimer_setting(
1872                 struct pipe_ctx *pipe_ctx,
1873                 bool is_vga_mode,
1874                 bool is_over_340mhz)
1875 {
1876         uint8_t slave_address = (0xBA >> 1);
1877         uint8_t buffer[2];
1878         bool i2c_success = false;
1879         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
1880
1881         memset(&buffer, 0, sizeof(buffer));
1882
1883         /* Program Slave Address for tuning single integrity */
1884         /* Write offset 0x0A to 0x13 */
1885         buffer[0] = 0x0A;
1886         buffer[1] = 0x13;
1887         i2c_success = i2c_write(pipe_ctx, slave_address,
1888                         buffer, sizeof(buffer));
1889         RETIMER_REDRIVER_INFO("retimer writes default setting to slave_address = 0x%x,\
1890                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1891                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1892         if (!i2c_success)
1893                 /* Write failure */
1894                 ASSERT(i2c_success);
1895
1896         /* Write offset 0x0A to 0x17 */
1897         buffer[0] = 0x0A;
1898         buffer[1] = 0x17;
1899         i2c_success = i2c_write(pipe_ctx, slave_address,
1900                         buffer, sizeof(buffer));
1901         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
1902                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1903                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1904         if (!i2c_success)
1905                 /* Write failure */
1906                 ASSERT(i2c_success);
1907
1908         /* Write offset 0x0B to 0xDA or 0xD8 */
1909         buffer[0] = 0x0B;
1910         buffer[1] = is_over_340mhz ? 0xDA : 0xD8;
1911         i2c_success = i2c_write(pipe_ctx, slave_address,
1912                         buffer, sizeof(buffer));
1913         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
1914                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1915                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1916         if (!i2c_success)
1917                 /* Write failure */
1918                 ASSERT(i2c_success);
1919
1920         /* Write offset 0x0A to 0x17 */
1921         buffer[0] = 0x0A;
1922         buffer[1] = 0x17;
1923         i2c_success = i2c_write(pipe_ctx, slave_address,
1924                         buffer, sizeof(buffer));
1925         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
1926                 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
1927                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1928         if (!i2c_success)
1929                 /* Write failure */
1930                 ASSERT(i2c_success);
1931
1932         /* Write offset 0x0C to 0x1D or 0x91 */
1933         buffer[0] = 0x0C;
1934         buffer[1] = is_over_340mhz ? 0x1D : 0x91;
1935         i2c_success = i2c_write(pipe_ctx, slave_address,
1936                         buffer, sizeof(buffer));
1937         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
1938                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1939                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1940         if (!i2c_success)
1941                 /* Write failure */
1942                 ASSERT(i2c_success);
1943
1944         /* Write offset 0x0A to 0x17 */
1945         buffer[0] = 0x0A;
1946         buffer[1] = 0x17;
1947         i2c_success = i2c_write(pipe_ctx, slave_address,
1948                         buffer, sizeof(buffer));
1949         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
1950                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1951                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1952         if (!i2c_success)
1953                 /* Write failure */
1954                 ASSERT(i2c_success);
1955
1956
1957         if (is_vga_mode) {
1958                 /* Program additional settings if using 640x480 resolution */
1959
1960                 /* Write offset 0xFF to 0x01 */
1961                 buffer[0] = 0xff;
1962                 buffer[1] = 0x01;
1963                 i2c_success = i2c_write(pipe_ctx, slave_address,
1964                                 buffer, sizeof(buffer));
1965                 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
1966                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1967                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
1968                 if (!i2c_success)
1969                         /* Write failure */
1970                         ASSERT(i2c_success);
1971
1972                 /* Write offset 0x00 to 0x23 */
1973                 buffer[0] = 0x00;
1974                 buffer[1] = 0x23;
1975                 i2c_success = i2c_write(pipe_ctx, slave_address,
1976                                 buffer, sizeof(buffer));
1977                 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
1978                         offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
1979                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
1980                 if (!i2c_success)
1981                         /* Write failure */
1982                         ASSERT(i2c_success);
1983
1984                 /* Write offset 0xff to 0x00 */
1985                 buffer[0] = 0xff;
1986                 buffer[1] = 0x00;
1987                 i2c_success = i2c_write(pipe_ctx, slave_address,
1988                                 buffer, sizeof(buffer));
1989                 RETIMER_REDRIVER_INFO("retimer write default setting to slave_addr = 0x%x,\
1990                         offset = 0x%x, reg_val= 0x%x, i2c_success = %d end here\n",
1991                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
1992                 if (!i2c_success)
1993                         /* Write failure */
1994                         ASSERT(i2c_success);
1995         }
1996 }
1997
1998 static void write_i2c_redriver_setting(
1999                 struct pipe_ctx *pipe_ctx,
2000                 bool is_over_340mhz)
2001 {
2002         uint8_t slave_address = (0xF0 >> 1);
2003         uint8_t buffer[16];
2004         bool i2c_success = false;
2005         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
2006
2007         memset(&buffer, 0, sizeof(buffer));
2008
2009         // Program Slave Address for tuning single integrity
2010         buffer[3] = 0x4E;
2011         buffer[4] = 0x4E;
2012         buffer[5] = 0x4E;
2013         buffer[6] = is_over_340mhz ? 0x4E : 0x4A;
2014
2015         i2c_success = i2c_write(pipe_ctx, slave_address,
2016                                         buffer, sizeof(buffer));
2017         RETIMER_REDRIVER_INFO("redriver write 0 to all 16 reg offset expect following:\n\
2018                 \t slave_addr = 0x%x, offset[3] = 0x%x, offset[4] = 0x%x,\
2019                 offset[5] = 0x%x,offset[6] is_over_340mhz = 0x%x,\
2020                 i2c_success = %d\n",
2021                 slave_address, buffer[3], buffer[4], buffer[5], buffer[6], i2c_success?1:0);
2022
2023         if (!i2c_success)
2024                 /* Write failure */
2025                 ASSERT(i2c_success);
2026 }
2027
2028 static void enable_link_hdmi(struct pipe_ctx *pipe_ctx)
2029 {
2030         struct dc_stream_state *stream = pipe_ctx->stream;
2031         struct dc_link *link = stream->link;
2032         enum dc_color_depth display_color_depth;
2033         enum engine_id eng_id;
2034         struct ext_hdmi_settings settings = {0};
2035         bool is_over_340mhz = false;
2036         bool is_vga_mode = (stream->timing.h_addressable == 640)
2037                         && (stream->timing.v_addressable == 480);
2038
2039         if (stream->phy_pix_clk == 0)
2040                 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10;
2041         if (stream->phy_pix_clk > 340000)
2042                 is_over_340mhz = true;
2043
2044         if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {
2045                 unsigned short masked_chip_caps = pipe_ctx->stream->link->chip_caps &
2046                                 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK;
2047                 if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) {
2048                         /* DP159, Retimer settings */
2049                         eng_id = pipe_ctx->stream_res.stream_enc->id;
2050
2051                         if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings)) {
2052                                 write_i2c_retimer_setting(pipe_ctx,
2053                                                 is_vga_mode, is_over_340mhz, &settings);
2054                         } else {
2055                                 write_i2c_default_retimer_setting(pipe_ctx,
2056                                                 is_vga_mode, is_over_340mhz);
2057                         }
2058                 } else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) {
2059                         /* PI3EQX1204, Redriver settings */
2060                         write_i2c_redriver_setting(pipe_ctx, is_over_340mhz);
2061                 }
2062         }
2063
2064         if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
2065                 dal_ddc_service_write_scdc_data(
2066                         stream->link->ddc,
2067                         stream->phy_pix_clk,
2068                         stream->timing.flags.LTE_340MCSC_SCRAMBLE);
2069
2070         memset(&stream->link->cur_link_settings, 0,
2071                         sizeof(struct dc_link_settings));
2072
2073         display_color_depth = stream->timing.display_color_depth;
2074         if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
2075                 display_color_depth = COLOR_DEPTH_888;
2076
2077         link->link_enc->funcs->enable_tmds_output(
2078                         link->link_enc,
2079                         pipe_ctx->clock_source->id,
2080                         display_color_depth,
2081                         pipe_ctx->stream->signal,
2082                         stream->phy_pix_clk);
2083
2084         if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
2085                 dal_ddc_service_read_scdc_data(link->ddc);
2086 }
2087
2088 static void enable_link_lvds(struct pipe_ctx *pipe_ctx)
2089 {
2090         struct dc_stream_state *stream = pipe_ctx->stream;
2091         struct dc_link *link = stream->link;
2092
2093         if (stream->phy_pix_clk == 0)
2094                 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10;
2095
2096         memset(&stream->link->cur_link_settings, 0,
2097                         sizeof(struct dc_link_settings));
2098
2099         link->link_enc->funcs->enable_lvds_output(
2100                         link->link_enc,
2101                         pipe_ctx->clock_source->id,
2102                         stream->phy_pix_clk);
2103
2104 }
2105
2106 /****************************enable_link***********************************/
2107 static enum dc_status enable_link(
2108                 struct dc_state *state,
2109                 struct pipe_ctx *pipe_ctx)
2110 {
2111         enum dc_status status = DC_ERROR_UNEXPECTED;
2112         switch (pipe_ctx->stream->signal) {
2113         case SIGNAL_TYPE_DISPLAY_PORT:
2114                 status = enable_link_dp(state, pipe_ctx);
2115                 break;
2116         case SIGNAL_TYPE_EDP:
2117                 status = enable_link_edp(state, pipe_ctx);
2118                 break;
2119         case SIGNAL_TYPE_DISPLAY_PORT_MST:
2120                 status = enable_link_dp_mst(state, pipe_ctx);
2121                 msleep(200);
2122                 break;
2123         case SIGNAL_TYPE_DVI_SINGLE_LINK:
2124         case SIGNAL_TYPE_DVI_DUAL_LINK:
2125         case SIGNAL_TYPE_HDMI_TYPE_A:
2126                 enable_link_hdmi(pipe_ctx);
2127                 status = DC_OK;
2128                 break;
2129         case SIGNAL_TYPE_LVDS:
2130                 enable_link_lvds(pipe_ctx);
2131                 status = DC_OK;
2132                 break;
2133         case SIGNAL_TYPE_VIRTUAL:
2134                 status = DC_OK;
2135                 break;
2136         default:
2137                 break;
2138         }
2139
2140         if (status == DC_OK)
2141                 pipe_ctx->stream->link->link_status.link_active = true;
2142
2143         return status;
2144 }
2145
2146 static void disable_link(struct dc_link *link, enum signal_type signal)
2147 {
2148         /*
2149          * TODO: implement call for dp_set_hw_test_pattern
2150          * it is needed for compliance testing
2151          */
2152
2153         /* here we need to specify that encoder output settings
2154          * need to be calculated as for the set mode,
2155          * it will lead to querying dynamic link capabilities
2156          * which should be done before enable output */
2157
2158         if (dc_is_dp_signal(signal)) {
2159                 /* SST DP, eDP */
2160                 if (dc_is_dp_sst_signal(signal))
2161                         dp_disable_link_phy(link, signal);
2162                 else
2163                         dp_disable_link_phy_mst(link, signal);
2164 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
2165
2166                 if (dc_is_dp_sst_signal(signal) ||
2167                                 link->mst_stream_alloc_table.stream_count == 0) {
2168                         dp_set_fec_enable(link, false);
2169                         dp_set_fec_ready(link, false);
2170                 }
2171 #endif
2172         } else
2173                 link->link_enc->funcs->disable_output(link->link_enc, signal);
2174
2175         if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
2176                 /* MST disable link only when no stream use the link */
2177                 if (link->mst_stream_alloc_table.stream_count <= 0)
2178                         link->link_status.link_active = false;
2179         } else {
2180                 link->link_status.link_active = false;
2181         }
2182 }
2183
2184 static uint32_t get_timing_pixel_clock_100hz(const struct dc_crtc_timing *timing)
2185 {
2186
2187         uint32_t pxl_clk = timing->pix_clk_100hz;
2188
2189         if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
2190                 pxl_clk /= 2;
2191         else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
2192                 pxl_clk = pxl_clk * 2 / 3;
2193
2194         if (timing->display_color_depth == COLOR_DEPTH_101010)
2195                 pxl_clk = pxl_clk * 10 / 8;
2196         else if (timing->display_color_depth == COLOR_DEPTH_121212)
2197                 pxl_clk = pxl_clk * 12 / 8;
2198
2199         return pxl_clk;
2200 }
2201
2202 static bool dp_active_dongle_validate_timing(
2203                 const struct dc_crtc_timing *timing,
2204                 const struct dpcd_caps *dpcd_caps)
2205 {
2206         const struct dc_dongle_caps *dongle_caps = &dpcd_caps->dongle_caps;
2207
2208         switch (dpcd_caps->dongle_type) {
2209         case DISPLAY_DONGLE_DP_VGA_CONVERTER:
2210         case DISPLAY_DONGLE_DP_DVI_CONVERTER:
2211         case DISPLAY_DONGLE_DP_DVI_DONGLE:
2212                 if (timing->pixel_encoding == PIXEL_ENCODING_RGB)
2213                         return true;
2214                 else
2215                         return false;
2216         default:
2217                 break;
2218         }
2219
2220         if (dongle_caps->dongle_type != DISPLAY_DONGLE_DP_HDMI_CONVERTER ||
2221                 dongle_caps->extendedCapValid == false)
2222                 return true;
2223
2224         /* Check Pixel Encoding */
2225         switch (timing->pixel_encoding) {
2226         case PIXEL_ENCODING_RGB:
2227         case PIXEL_ENCODING_YCBCR444:
2228                 break;
2229         case PIXEL_ENCODING_YCBCR422:
2230                 if (!dongle_caps->is_dp_hdmi_ycbcr422_pass_through)
2231                         return false;
2232                 break;
2233         case PIXEL_ENCODING_YCBCR420:
2234                 if (!dongle_caps->is_dp_hdmi_ycbcr420_pass_through)
2235                         return false;
2236                 break;
2237         default:
2238                 /* Invalid Pixel Encoding*/
2239                 return false;
2240         }
2241
2242         switch (timing->display_color_depth) {
2243         case COLOR_DEPTH_666:
2244         case COLOR_DEPTH_888:
2245                 /*888 and 666 should always be supported*/
2246                 break;
2247         case COLOR_DEPTH_101010:
2248                 if (dongle_caps->dp_hdmi_max_bpc < 10)
2249                         return false;
2250                 break;
2251         case COLOR_DEPTH_121212:
2252                 if (dongle_caps->dp_hdmi_max_bpc < 12)
2253                         return false;
2254                 break;
2255         case COLOR_DEPTH_141414:
2256         case COLOR_DEPTH_161616:
2257         default:
2258                 /* These color depths are currently not supported */
2259                 return false;
2260         }
2261
2262         if (get_timing_pixel_clock_100hz(timing) > (dongle_caps->dp_hdmi_max_pixel_clk_in_khz * 10))
2263                 return false;
2264
2265         return true;
2266 }
2267
2268 enum dc_status dc_link_validate_mode_timing(
2269                 const struct dc_stream_state *stream,
2270                 struct dc_link *link,
2271                 const struct dc_crtc_timing *timing)
2272 {
2273         uint32_t max_pix_clk = stream->link->dongle_max_pix_clk * 10;
2274         struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
2275
2276         /* A hack to avoid failing any modes for EDID override feature on
2277          * topology change such as lower quality cable for DP or different dongle
2278          */
2279         if (link->remote_sinks[0])
2280                 return DC_OK;
2281
2282         /* Passive Dongle */
2283         if (max_pix_clk != 0 && get_timing_pixel_clock_100hz(timing) > max_pix_clk)
2284                 return DC_EXCEED_DONGLE_CAP;
2285
2286         /* Active Dongle*/
2287         if (!dp_active_dongle_validate_timing(timing, dpcd_caps))
2288                 return DC_EXCEED_DONGLE_CAP;
2289
2290         switch (stream->signal) {
2291         case SIGNAL_TYPE_EDP:
2292         case SIGNAL_TYPE_DISPLAY_PORT:
2293                 if (!dp_validate_mode_timing(
2294                                 link,
2295                                 timing))
2296                         return DC_NO_DP_LINK_BANDWIDTH;
2297                 break;
2298
2299         default:
2300                 break;
2301         }
2302
2303         return DC_OK;
2304 }
2305
2306 int dc_link_get_backlight_level(const struct dc_link *link)
2307 {
2308         struct abm *abm = link->ctx->dc->res_pool->abm;
2309
2310         if (abm == NULL || abm->funcs->get_current_backlight == NULL)
2311                 return DC_ERROR_UNEXPECTED;
2312
2313         return (int) abm->funcs->get_current_backlight(abm);
2314 }
2315
2316 bool dc_link_set_backlight_level(const struct dc_link *link,
2317                 uint32_t backlight_pwm_u16_16,
2318                 uint32_t frame_ramp)
2319 {
2320         struct dc  *core_dc = link->ctx->dc;
2321         struct abm *abm = core_dc->res_pool->abm;
2322         struct dmcu *dmcu = core_dc->res_pool->dmcu;
2323         unsigned int controller_id = 0;
2324         bool use_smooth_brightness = true;
2325         int i;
2326         DC_LOGGER_INIT(link->ctx->logger);
2327
2328         if ((dmcu == NULL) ||
2329                 (abm == NULL) ||
2330                 (abm->funcs->set_backlight_level_pwm == NULL))
2331                 return false;
2332
2333         use_smooth_brightness = dmcu->funcs->is_dmcu_initialized(dmcu);
2334
2335         DC_LOG_BACKLIGHT("New Backlight level: %d (0x%X)\n",
2336                         backlight_pwm_u16_16, backlight_pwm_u16_16);
2337
2338         if (dc_is_embedded_signal(link->connector_signal)) {
2339                 for (i = 0; i < MAX_PIPES; i++) {
2340                         if (core_dc->current_state->res_ctx.pipe_ctx[i].stream) {
2341                                 if (core_dc->current_state->res_ctx.
2342                                                 pipe_ctx[i].stream->link
2343                                                 == link) {
2344                                         /* DMCU -1 for all controller id values,
2345                                          * therefore +1 here
2346                                          */
2347                                         controller_id =
2348                                                 core_dc->current_state->
2349                                                 res_ctx.pipe_ctx[i].stream_res.tg->inst +
2350                                                 1;
2351
2352                                         /* Disable brightness ramping when the display is blanked
2353                                          * as it can hang the DMCU
2354                                          */
2355                                         if (core_dc->current_state->res_ctx.pipe_ctx[i].plane_state == NULL)
2356                                                 frame_ramp = 0;
2357                                 }
2358                         }
2359                 }
2360                 abm->funcs->set_backlight_level_pwm(
2361                                 abm,
2362                                 backlight_pwm_u16_16,
2363                                 frame_ramp,
2364                                 controller_id,
2365                                 use_smooth_brightness);
2366         }
2367
2368         return true;
2369 }
2370
2371 bool dc_link_set_abm_disable(const struct dc_link *link)
2372 {
2373         struct dc  *core_dc = link->ctx->dc;
2374         struct abm *abm = core_dc->res_pool->abm;
2375
2376         if ((abm == NULL) || (abm->funcs->set_backlight_level_pwm == NULL))
2377                 return false;
2378
2379         abm->funcs->set_abm_immediate_disable(abm);
2380
2381         return true;
2382 }
2383
2384 bool dc_link_set_psr_enable(const struct dc_link *link, bool enable, bool wait)
2385 {
2386         struct dc  *core_dc = link->ctx->dc;
2387         struct dmcu *dmcu = core_dc->res_pool->dmcu;
2388
2389         if ((dmcu != NULL && dmcu->funcs->is_dmcu_initialized(dmcu)) && link->psr_enabled)
2390                 dmcu->funcs->set_psr_enable(dmcu, enable, wait);
2391
2392         return true;
2393 }
2394
2395 const struct dc_link_status *dc_link_get_status(const struct dc_link *link)
2396 {
2397         return &link->link_status;
2398 }
2399
2400 void core_link_resume(struct dc_link *link)
2401 {
2402         if (link->connector_signal != SIGNAL_TYPE_VIRTUAL)
2403                 program_hpd_filter(link);
2404 }
2405
2406 static struct fixed31_32 get_pbn_per_slot(struct dc_stream_state *stream)
2407 {
2408         struct fixed31_32 mbytes_per_sec;
2409         uint32_t link_rate_in_mbytes_per_sec = dc_link_bandwidth_kbps(stream->link,
2410                         &stream->link->cur_link_settings);
2411         link_rate_in_mbytes_per_sec /= 8000; /* Kbits to MBytes */
2412
2413         mbytes_per_sec = dc_fixpt_from_int(link_rate_in_mbytes_per_sec);
2414
2415         return dc_fixpt_div_int(mbytes_per_sec, 54);
2416 }
2417
2418 static int get_color_depth(enum dc_color_depth color_depth)
2419 {
2420         switch (color_depth) {
2421         case COLOR_DEPTH_666: return 6;
2422         case COLOR_DEPTH_888: return 8;
2423         case COLOR_DEPTH_101010: return 10;
2424         case COLOR_DEPTH_121212: return 12;
2425         case COLOR_DEPTH_141414: return 14;
2426         case COLOR_DEPTH_161616: return 16;
2427         default: return 0;
2428         }
2429 }
2430
2431 static struct fixed31_32 get_pbn_from_timing(struct pipe_ctx *pipe_ctx)
2432 {
2433         uint32_t bpc;
2434         uint64_t kbps;
2435         struct fixed31_32 peak_kbps;
2436         uint32_t numerator;
2437         uint32_t denominator;
2438
2439         bpc = get_color_depth(pipe_ctx->stream_res.pix_clk_params.color_depth);
2440         kbps = dc_bandwidth_in_kbps_from_timing(&pipe_ctx->stream->timing);
2441
2442         /*
2443          * margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006
2444          * The unit of 54/64Mbytes/sec is an arbitrary unit chosen based on
2445          * common multiplier to render an integer PBN for all link rate/lane
2446          * counts combinations
2447          * calculate
2448          * peak_kbps *= (1006/1000)
2449          * peak_kbps *= (64/54)
2450          * peak_kbps *= 8    convert to bytes
2451          */
2452
2453         numerator = 64 * PEAK_FACTOR_X1000;
2454         denominator = 54 * 8 * 1000 * 1000;
2455         kbps *= numerator;
2456         peak_kbps = dc_fixpt_from_fraction(kbps, denominator);
2457
2458         return peak_kbps;
2459 }
2460
2461 static void update_mst_stream_alloc_table(
2462         struct dc_link *link,
2463         struct stream_encoder *stream_enc,
2464         const struct dp_mst_stream_allocation_table *proposed_table)
2465 {
2466         struct link_mst_stream_allocation work_table[MAX_CONTROLLER_NUM] = {
2467                         { 0 } };
2468         struct link_mst_stream_allocation *dc_alloc;
2469
2470         int i;
2471         int j;
2472
2473         /* if DRM proposed_table has more than one new payload */
2474         ASSERT(proposed_table->stream_count -
2475                         link->mst_stream_alloc_table.stream_count < 2);
2476
2477         /* copy proposed_table to link, add stream encoder */
2478         for (i = 0; i < proposed_table->stream_count; i++) {
2479
2480                 for (j = 0; j < link->mst_stream_alloc_table.stream_count; j++) {
2481                         dc_alloc =
2482                         &link->mst_stream_alloc_table.stream_allocations[j];
2483
2484                         if (dc_alloc->vcp_id ==
2485                                 proposed_table->stream_allocations[i].vcp_id) {
2486
2487                                 work_table[i] = *dc_alloc;
2488                                 break; /* exit j loop */
2489                         }
2490                 }
2491
2492                 /* new vcp_id */
2493                 if (j == link->mst_stream_alloc_table.stream_count) {
2494                         work_table[i].vcp_id =
2495                                 proposed_table->stream_allocations[i].vcp_id;
2496                         work_table[i].slot_count =
2497                                 proposed_table->stream_allocations[i].slot_count;
2498                         work_table[i].stream_enc = stream_enc;
2499                 }
2500         }
2501
2502         /* update link->mst_stream_alloc_table with work_table */
2503         link->mst_stream_alloc_table.stream_count =
2504                         proposed_table->stream_count;
2505         for (i = 0; i < MAX_CONTROLLER_NUM; i++)
2506                 link->mst_stream_alloc_table.stream_allocations[i] =
2507                                 work_table[i];
2508 }
2509
2510 /* convert link_mst_stream_alloc_table to dm dp_mst_stream_alloc_table
2511  * because stream_encoder is not exposed to dm
2512  */
2513 static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx)
2514 {
2515         struct dc_stream_state *stream = pipe_ctx->stream;
2516         struct dc_link *link = stream->link;
2517         struct link_encoder *link_encoder = link->link_enc;
2518         struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;
2519         struct dp_mst_stream_allocation_table proposed_table = {0};
2520         struct fixed31_32 avg_time_slots_per_mtp;
2521         struct fixed31_32 pbn;
2522         struct fixed31_32 pbn_per_slot;
2523         uint8_t i;
2524         DC_LOGGER_INIT(link->ctx->logger);
2525
2526         /* enable_link_dp_mst already check link->enabled_stream_count
2527          * and stream is in link->stream[]. This is called during set mode,
2528          * stream_enc is available.
2529          */
2530
2531         /* get calculate VC payload for stream: stream_alloc */
2532         if (dm_helpers_dp_mst_write_payload_allocation_table(
2533                 stream->ctx,
2534                 stream,
2535                 &proposed_table,
2536                 true)) {
2537                 update_mst_stream_alloc_table(
2538                                         link, pipe_ctx->stream_res.stream_enc, &proposed_table);
2539         }
2540         else
2541                 DC_LOG_WARNING("Failed to update"
2542                                 "MST allocation table for"
2543                                 "pipe idx:%d\n",
2544                                 pipe_ctx->pipe_idx);
2545
2546         DC_LOG_MST("%s  "
2547                         "stream_count: %d: \n ",
2548                         __func__,
2549                         link->mst_stream_alloc_table.stream_count);
2550
2551         for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
2552                 DC_LOG_MST("stream_enc[%d]: %p      "
2553                 "stream[%d].vcp_id: %d      "
2554                 "stream[%d].slot_count: %d\n",
2555                 i,
2556                 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
2557                 i,
2558                 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
2559                 i,
2560                 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
2561         }
2562
2563         ASSERT(proposed_table.stream_count > 0);
2564
2565         /* program DP source TX for payload */
2566         link_encoder->funcs->update_mst_stream_allocation_table(
2567                 link_encoder,
2568                 &link->mst_stream_alloc_table);
2569
2570         /* send down message */
2571         dm_helpers_dp_mst_poll_for_allocation_change_trigger(
2572                         stream->ctx,
2573                         stream);
2574
2575         dm_helpers_dp_mst_send_payload_allocation(
2576                         stream->ctx,
2577                         stream,
2578                         true);
2579
2580         /* slot X.Y for only current stream */
2581         pbn_per_slot = get_pbn_per_slot(stream);
2582         pbn = get_pbn_from_timing(pipe_ctx);
2583         avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot);
2584
2585         stream_encoder->funcs->set_mst_bandwidth(
2586                 stream_encoder,
2587                 avg_time_slots_per_mtp);
2588
2589         return DC_OK;
2590
2591 }
2592
2593 static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx)
2594 {
2595         struct dc_stream_state *stream = pipe_ctx->stream;
2596         struct dc_link *link = stream->link;
2597         struct link_encoder *link_encoder = link->link_enc;
2598         struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;
2599         struct dp_mst_stream_allocation_table proposed_table = {0};
2600         struct fixed31_32 avg_time_slots_per_mtp = dc_fixpt_from_int(0);
2601         uint8_t i;
2602         bool mst_mode = (link->type == dc_connection_mst_branch);
2603         DC_LOGGER_INIT(link->ctx->logger);
2604
2605         /* deallocate_mst_payload is called before disable link. When mode or
2606          * disable/enable monitor, new stream is created which is not in link
2607          * stream[] yet. For this, payload is not allocated yet, so de-alloc
2608          * should not done. For new mode set, map_resources will get engine
2609          * for new stream, so stream_enc->id should be validated until here.
2610          */
2611
2612         /* slot X.Y */
2613         stream_encoder->funcs->set_mst_bandwidth(
2614                 stream_encoder,
2615                 avg_time_slots_per_mtp);
2616
2617         /* TODO: which component is responsible for remove payload table? */
2618         if (mst_mode) {
2619                 if (dm_helpers_dp_mst_write_payload_allocation_table(
2620                                 stream->ctx,
2621                                 stream,
2622                                 &proposed_table,
2623                                 false)) {
2624
2625                         update_mst_stream_alloc_table(
2626                                 link, pipe_ctx->stream_res.stream_enc, &proposed_table);
2627                 }
2628                 else {
2629                                 DC_LOG_WARNING("Failed to update"
2630                                                 "MST allocation table for"
2631                                                 "pipe idx:%d\n",
2632                                                 pipe_ctx->pipe_idx);
2633                 }
2634         }
2635
2636         DC_LOG_MST("%s"
2637                         "stream_count: %d: ",
2638                         __func__,
2639                         link->mst_stream_alloc_table.stream_count);
2640
2641         for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
2642                 DC_LOG_MST("stream_enc[%d]: %p      "
2643                 "stream[%d].vcp_id: %d      "
2644                 "stream[%d].slot_count: %d\n",
2645                 i,
2646                 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
2647                 i,
2648                 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
2649                 i,
2650                 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
2651         }
2652
2653         link_encoder->funcs->update_mst_stream_allocation_table(
2654                 link_encoder,
2655                 &link->mst_stream_alloc_table);
2656
2657         if (mst_mode) {
2658                 dm_helpers_dp_mst_poll_for_allocation_change_trigger(
2659                         stream->ctx,
2660                         stream);
2661
2662                 dm_helpers_dp_mst_send_payload_allocation(
2663                         stream->ctx,
2664                         stream,
2665                         false);
2666         }
2667
2668         return DC_OK;
2669 }
2670
2671 void core_link_enable_stream(
2672                 struct dc_state *state,
2673                 struct pipe_ctx *pipe_ctx)
2674 {
2675         struct dc *core_dc = pipe_ctx->stream->ctx->dc;
2676         struct dc_stream_state *stream = pipe_ctx->stream;
2677         enum dc_status status;
2678         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
2679
2680         if (!dc_is_virtual_signal(pipe_ctx->stream->signal)) {
2681                 stream->link->link_enc->funcs->setup(
2682                         stream->link->link_enc,
2683                         pipe_ctx->stream->signal);
2684                 pipe_ctx->stream_res.stream_enc->funcs->setup_stereo_sync(
2685                         pipe_ctx->stream_res.stream_enc,
2686                         pipe_ctx->stream_res.tg->inst,
2687                         stream->timing.timing_3d_format != TIMING_3D_FORMAT_NONE);
2688         }
2689
2690         if (dc_is_dp_signal(pipe_ctx->stream->signal))
2691                 pipe_ctx->stream_res.stream_enc->funcs->dp_set_stream_attribute(
2692                         pipe_ctx->stream_res.stream_enc,
2693                         &stream->timing,
2694                         stream->output_color_space,
2695                         stream->link->dpcd_caps.dprx_feature.bits.SST_SPLIT_SDP_CAP);
2696
2697         if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal))
2698                 pipe_ctx->stream_res.stream_enc->funcs->hdmi_set_stream_attribute(
2699                         pipe_ctx->stream_res.stream_enc,
2700                         &stream->timing,
2701                         stream->phy_pix_clk,
2702                         pipe_ctx->stream_res.audio != NULL);
2703
2704         pipe_ctx->stream->link->link_state_valid = true;
2705
2706         if (dc_is_dvi_signal(pipe_ctx->stream->signal))
2707                 pipe_ctx->stream_res.stream_enc->funcs->dvi_set_stream_attribute(
2708                         pipe_ctx->stream_res.stream_enc,
2709                         &stream->timing,
2710                         (pipe_ctx->stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK) ?
2711                         true : false);
2712
2713         if (dc_is_lvds_signal(pipe_ctx->stream->signal))
2714                 pipe_ctx->stream_res.stream_enc->funcs->lvds_set_stream_attribute(
2715                         pipe_ctx->stream_res.stream_enc,
2716                         &stream->timing);
2717
2718         if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
2719                 bool apply_edp_fast_boot_optimization =
2720                         pipe_ctx->stream->apply_edp_fast_boot_optimization;
2721
2722                 pipe_ctx->stream->apply_edp_fast_boot_optimization = false;
2723
2724                 resource_build_info_frame(pipe_ctx);
2725                 core_dc->hwss.update_info_frame(pipe_ctx);
2726
2727                 /* Do not touch link on seamless boot optimization. */
2728                 if (pipe_ctx->stream->apply_seamless_boot_optimization) {
2729                         pipe_ctx->stream->dpms_off = false;
2730                         return;
2731                 }
2732
2733                 /* eDP lit up by bios already, no need to enable again. */
2734                 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP &&
2735                                         apply_edp_fast_boot_optimization) {
2736                         pipe_ctx->stream->dpms_off = false;
2737                         return;
2738                 }
2739
2740                 if (pipe_ctx->stream->dpms_off)
2741                         return;
2742
2743                 status = enable_link(state, pipe_ctx);
2744
2745                 if (status != DC_OK) {
2746                         DC_LOG_WARNING("enabling link %u failed: %d\n",
2747                         pipe_ctx->stream->link->link_index,
2748                         status);
2749
2750                         /* Abort stream enable *unless* the failure was due to
2751                          * DP link training - some DP monitors will recover and
2752                          * show the stream anyway. But MST displays can't proceed
2753                          * without link training.
2754                          */
2755                         if (status != DC_FAIL_DP_LINK_TRAINING ||
2756                                         pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
2757                                 BREAK_TO_DEBUGGER();
2758                                 return;
2759                         }
2760                 }
2761
2762                 core_dc->hwss.enable_audio_stream(pipe_ctx);
2763
2764                 /* turn off otg test pattern if enable */
2765                 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
2766                         pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
2767                                         CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
2768                                         COLOR_DEPTH_UNDEFINED);
2769
2770                 /* This second call is needed to reconfigure the DIG
2771                  * as a workaround for the incorrect value being applied
2772                  * from transmitter control.
2773                  */
2774                 if (!dc_is_virtual_signal(pipe_ctx->stream->signal))
2775                         stream->link->link_enc->funcs->setup(
2776                                 stream->link->link_enc,
2777                                 pipe_ctx->stream->signal);
2778
2779 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
2780                 if (pipe_ctx->stream->timing.flags.DSC) {
2781                         if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
2782                                         dc_is_virtual_signal(pipe_ctx->stream->signal))
2783                                 dp_set_dsc_enable(pipe_ctx, true);
2784                 }
2785 #endif
2786                 core_dc->hwss.enable_stream(pipe_ctx);
2787
2788 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
2789                 /* Set DPS PPS SDP (AKA "info frames") */
2790                 if (pipe_ctx->stream->timing.flags.DSC) {
2791                         if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
2792                                         dc_is_virtual_signal(pipe_ctx->stream->signal))
2793                                 dp_set_dsc_pps_sdp(pipe_ctx, true);
2794                 }
2795 #endif
2796
2797                 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
2798                         allocate_mst_payload(pipe_ctx);
2799
2800                 core_dc->hwss.unblank_stream(pipe_ctx,
2801                         &pipe_ctx->stream->link->cur_link_settings);
2802
2803                 if (dc_is_dp_signal(pipe_ctx->stream->signal))
2804                         enable_stream_features(pipe_ctx);
2805         }
2806 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
2807         else { // if (IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment))
2808                 if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
2809                                 dc_is_virtual_signal(pipe_ctx->stream->signal))
2810                         dp_set_dsc_enable(pipe_ctx, true);
2811
2812         }
2813 #endif
2814 }
2815
2816 void core_link_disable_stream(struct pipe_ctx *pipe_ctx)
2817 {
2818         struct dc  *core_dc = pipe_ctx->stream->ctx->dc;
2819         struct dc_stream_state *stream = pipe_ctx->stream;
2820         struct dc_link *link = stream->sink->link;
2821
2822         core_dc->hwss.blank_stream(pipe_ctx);
2823
2824         if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
2825                 deallocate_mst_payload(pipe_ctx);
2826
2827         if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {
2828                 struct ext_hdmi_settings settings = {0};
2829                 enum engine_id eng_id = pipe_ctx->stream_res.stream_enc->id;
2830
2831                 unsigned short masked_chip_caps = link->chip_caps &
2832                                 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK;
2833                 //Need to inform that sink is going to use legacy HDMI mode.
2834                 dal_ddc_service_write_scdc_data(
2835                         link->ddc,
2836                         165000,//vbios only handles 165Mhz.
2837                         false);
2838                 if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) {
2839                         /* DP159, Retimer settings */
2840                         if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings))
2841                                 write_i2c_retimer_setting(pipe_ctx,
2842                                                 false, false, &settings);
2843                         else
2844                                 write_i2c_default_retimer_setting(pipe_ctx,
2845                                                 false, false);
2846                 } else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) {
2847                         /* PI3EQX1204, Redriver settings */
2848                         write_i2c_redriver_setting(pipe_ctx, false);
2849                 }
2850         }
2851         core_dc->hwss.disable_stream(pipe_ctx);
2852
2853         disable_link(pipe_ctx->stream->link, pipe_ctx->stream->signal);
2854 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
2855         if (pipe_ctx->stream->timing.flags.DSC) {
2856                 if (dc_is_dp_signal(pipe_ctx->stream->signal))
2857                         dp_set_dsc_enable(pipe_ctx, false);
2858         }
2859 #endif
2860 }
2861
2862 void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
2863 {
2864         struct dc  *core_dc = pipe_ctx->stream->ctx->dc;
2865
2866         if (!dc_is_hdmi_signal(pipe_ctx->stream->signal))
2867                 return;
2868
2869         core_dc->hwss.set_avmute(pipe_ctx, enable);
2870 }
2871
2872 /**
2873  *****************************************************************************
2874  *  Function: dc_link_enable_hpd_filter
2875  *
2876  *  @brief
2877  *     If enable is true, programs HPD filter on associated HPD line using
2878  *     delay_on_disconnect/delay_on_connect values dependent on
2879  *     link->connector_signal
2880  *
2881  *     If enable is false, programs HPD filter on associated HPD line with no
2882  *     delays on connect or disconnect
2883  *
2884  *  @param [in] link: pointer to the dc link
2885  *  @param [in] enable: boolean specifying whether to enable hbd
2886  *****************************************************************************
2887  */
2888 void dc_link_enable_hpd_filter(struct dc_link *link, bool enable)
2889 {
2890         struct gpio *hpd;
2891
2892         if (enable) {
2893                 link->is_hpd_filter_disabled = false;
2894                 program_hpd_filter(link);
2895         } else {
2896                 link->is_hpd_filter_disabled = true;
2897                 /* Obtain HPD handle */
2898                 hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
2899
2900                 if (!hpd)
2901                         return;
2902
2903                 /* Setup HPD filtering */
2904                 if (dal_gpio_open(hpd, GPIO_MODE_INTERRUPT) == GPIO_RESULT_OK) {
2905                         struct gpio_hpd_config config;
2906
2907                         config.delay_on_connect = 0;
2908                         config.delay_on_disconnect = 0;
2909
2910                         dal_irq_setup_hpd_filter(hpd, &config);
2911
2912                         dal_gpio_close(hpd);
2913                 } else {
2914                         ASSERT_CRITICAL(false);
2915                 }
2916                 /* Release HPD handle */
2917                 dal_gpio_destroy_irq(&hpd);
2918         }
2919 }
2920
2921 uint32_t dc_bandwidth_in_kbps_from_timing(
2922         const struct dc_crtc_timing *timing)
2923 {
2924         uint32_t bits_per_channel = 0;
2925         uint32_t kbps;
2926
2927 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
2928         if (timing->flags.DSC) {
2929                 kbps = (timing->pix_clk_100hz * timing->dsc_cfg.bits_per_pixel);
2930                 kbps = kbps / 160 + ((kbps % 160) ? 1 : 0);
2931                 return kbps;
2932         }
2933 #endif
2934
2935         switch (timing->display_color_depth) {
2936         case COLOR_DEPTH_666:
2937                 bits_per_channel = 6;
2938                 break;
2939         case COLOR_DEPTH_888:
2940                 bits_per_channel = 8;
2941                 break;
2942         case COLOR_DEPTH_101010:
2943                 bits_per_channel = 10;
2944                 break;
2945         case COLOR_DEPTH_121212:
2946                 bits_per_channel = 12;
2947                 break;
2948         case COLOR_DEPTH_141414:
2949                 bits_per_channel = 14;
2950                 break;
2951         case COLOR_DEPTH_161616:
2952                 bits_per_channel = 16;
2953                 break;
2954         default:
2955                 break;
2956         }
2957
2958         ASSERT(bits_per_channel != 0);
2959
2960         kbps = timing->pix_clk_100hz / 10;
2961         kbps *= bits_per_channel;
2962
2963         if (timing->flags.Y_ONLY != 1) {
2964                 /*Only YOnly make reduce bandwidth by 1/3 compares to RGB*/
2965                 kbps *= 3;
2966                 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
2967                         kbps /= 2;
2968                 else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
2969                         kbps = kbps * 2 / 3;
2970         }
2971
2972         return kbps;
2973
2974 }
2975
2976 void dc_link_set_drive_settings(struct dc *dc,
2977                                 struct link_training_settings *lt_settings,
2978                                 const struct dc_link *link)
2979 {
2980
2981         int i;
2982
2983         for (i = 0; i < dc->link_count; i++) {
2984                 if (dc->links[i] == link)
2985                         break;
2986         }
2987
2988         if (i >= dc->link_count)
2989                 ASSERT_CRITICAL(false);
2990
2991         dc_link_dp_set_drive_settings(dc->links[i], lt_settings);
2992 }
2993
2994 void dc_link_perform_link_training(struct dc *dc,
2995                                    struct dc_link_settings *link_setting,
2996                                    bool skip_video_pattern)
2997 {
2998         int i;
2999
3000         for (i = 0; i < dc->link_count; i++)
3001                 dc_link_dp_perform_link_training(
3002                         dc->links[i],
3003                         link_setting,
3004                         skip_video_pattern);
3005 }
3006
3007 void dc_link_set_preferred_link_settings(struct dc *dc,
3008                                          struct dc_link_settings *link_setting,
3009                                          struct dc_link *link)
3010 {
3011         int i;
3012         struct pipe_ctx *pipe;
3013         struct dc_stream_state *link_stream;
3014         struct dc_link_settings store_settings = *link_setting;
3015
3016         link->preferred_link_setting = store_settings;
3017
3018         /* Retrain with preferred link settings only relevant for
3019          * DP signal type
3020          * Check for non-DP signal or if passive dongle present
3021          */
3022         if (!dc_is_dp_signal(link->connector_signal) ||
3023                 link->dongle_max_pix_clk > 0)
3024                 return;
3025
3026         for (i = 0; i < MAX_PIPES; i++) {
3027                 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
3028                 if (pipe->stream && pipe->stream->link) {
3029                         if (pipe->stream->link == link) {
3030                                 link_stream = pipe->stream;
3031                                 break;
3032                         }
3033                 }
3034         }
3035
3036         /* Stream not found */
3037         if (i == MAX_PIPES)
3038                 return;
3039
3040         /* Cannot retrain link if backend is off */
3041         if (link_stream->dpms_off)
3042                 return;
3043
3044         decide_link_settings(link_stream, &store_settings);
3045
3046         if ((store_settings.lane_count != LANE_COUNT_UNKNOWN) &&
3047                 (store_settings.link_rate != LINK_RATE_UNKNOWN))
3048                 dp_retrain_link_dp_test(link, &store_settings, false);
3049 }
3050
3051 void dc_link_set_preferred_training_settings(struct dc *dc,
3052                                                  struct dc_link_settings *link_setting,
3053                                                  struct dc_link_training_overrides *lt_overrides,
3054                                                  struct dc_link *link,
3055                                                  bool skip_immediate_retrain)
3056 {
3057         if (lt_overrides != NULL)
3058                 link->preferred_training_settings = *lt_overrides;
3059         else
3060                 memset(&link->preferred_training_settings, 0, sizeof(link->preferred_training_settings));
3061
3062         if (link_setting != NULL) {
3063                 link->preferred_link_setting = *link_setting;
3064         } else {
3065                 link->preferred_link_setting.lane_count = LANE_COUNT_UNKNOWN;
3066                 link->preferred_link_setting.link_rate = LINK_RATE_UNKNOWN;
3067         }
3068
3069         /* Retrain now, or wait until next stream update to apply */
3070         if (skip_immediate_retrain == false)
3071                 dc_link_set_preferred_link_settings(dc, &link->preferred_link_setting, link);
3072 }
3073
3074 void dc_link_enable_hpd(const struct dc_link *link)
3075 {
3076         dc_link_dp_enable_hpd(link);
3077 }
3078
3079 void dc_link_disable_hpd(const struct dc_link *link)
3080 {
3081         dc_link_dp_disable_hpd(link);
3082 }
3083
3084 void dc_link_set_test_pattern(struct dc_link *link,
3085                               enum dp_test_pattern test_pattern,
3086                               const struct link_training_settings *p_link_settings,
3087                               const unsigned char *p_custom_pattern,
3088                               unsigned int cust_pattern_size)
3089 {
3090         if (link != NULL)
3091                 dc_link_dp_set_test_pattern(
3092                         link,
3093                         test_pattern,
3094                         p_link_settings,
3095                         p_custom_pattern,
3096                         cust_pattern_size);
3097 }
3098
3099 uint32_t dc_link_bandwidth_kbps(
3100         const struct dc_link *link,
3101         const struct dc_link_settings *link_setting)
3102 {
3103         uint32_t link_bw_kbps =
3104                 link_setting->link_rate * LINK_RATE_REF_FREQ_IN_KHZ; /* bytes per sec */
3105
3106         link_bw_kbps *= 8;   /* 8 bits per byte*/
3107         link_bw_kbps *= link_setting->lane_count;
3108
3109 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
3110         if (link->dpcd_caps.fec_cap.bits.FEC_CAPABLE) {
3111                 /* Account for FEC overhead.
3112                  * We have to do it based on caps,
3113                  * and not based on FEC being set ready,
3114                  * because FEC is set ready too late in
3115                  * the process to correctly be picked up
3116                  * by mode enumeration.
3117                  *
3118                  * There's enough zeros at the end of 'kbps'
3119                  * that make the below operation 100% precise
3120                  * for our purposes.
3121                  * 'long long' makes it work even for HDMI 2.1
3122                  * max bandwidth (and much, much bigger bandwidths
3123                  * than that, actually).
3124                  *
3125                  * NOTE: Reducing link BW by 3% may not be precise
3126                  * because it may be a stream BT that increases by 3%, and so
3127                  * 1/1.03 = 0.970873 factor should have been used instead,
3128                  * but the difference is minimal and is in a safe direction,
3129                  * which all works well around potential ambiguity of DP 1.4a spec.
3130                  */
3131                 link_bw_kbps = mul_u64_u32_shr(BIT_ULL(32) * 970LL / 1000,
3132                                                link_bw_kbps, 32);
3133         }
3134 #endif
3135
3136         return link_bw_kbps;
3137
3138 }
3139
3140 const struct dc_link_settings *dc_link_get_link_cap(
3141                 const struct dc_link *link)
3142 {
3143         if (link->preferred_link_setting.lane_count != LANE_COUNT_UNKNOWN &&
3144                         link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN)
3145                 return &link->preferred_link_setting;
3146         return &link->verified_link_cap;
3147 }