2 * Copyright 2012-15 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include "dm_services.h"
28 #include "dm_helpers.h"
30 #include "grph_object_id.h"
31 #include "gpio_service_interface.h"
32 #include "core_status.h"
33 #include "dc_link_dp.h"
34 #include "dc_link_ddc.h"
35 #include "link_hwss.h"
38 #include "link_encoder.h"
39 #include "hw_sequencer.h"
42 #include "fixed31_32.h"
43 #include "dpcd_defs.h"
46 #include "dce/dce_11_0_d.h"
47 #include "dce/dce_11_0_enum.h"
48 #include "dce/dce_11_0_sh_mask.h"
50 #define DC_LOGGER_INIT(logger)
53 #define LINK_INFO(...) \
57 #define RETIMER_REDRIVER_INFO(...) \
58 DC_LOG_RETIMER_REDRIVER( \
60 /*******************************************************************************
62 ******************************************************************************/
65 LINK_RATE_REF_FREQ_IN_MHZ = 27,
66 PEAK_FACTOR_X1000 = 1006,
68 * Some receivers fail to train on first try and are good
69 * on subsequent tries. 2 retries should be plenty. If we
70 * don't have a successful training then we don't expect to
73 LINK_TRAINING_MAX_VERIFY_RETRY = 2
76 /*******************************************************************************
78 ******************************************************************************/
79 static void destruct(struct dc_link *link)
84 dal_ddc_service_destroy(&link->ddc);
87 link->link_enc->funcs->destroy(&link->link_enc);
90 dc_sink_release(link->local_sink);
92 for (i = 0; i < link->sink_count; ++i)
93 dc_sink_release(link->remote_sinks[i]);
96 struct gpio *get_hpd_gpio(struct dc_bios *dcb,
97 struct graphics_object_id link_id,
98 struct gpio_service *gpio_service)
100 enum bp_result bp_result;
101 struct graphics_object_hpd_info hpd_info;
102 struct gpio_pin_info pin_info;
104 if (dcb->funcs->get_hpd_info(dcb, link_id, &hpd_info) != BP_RESULT_OK)
107 bp_result = dcb->funcs->get_gpio_pin_info(dcb,
108 hpd_info.hpd_int_gpio_uid, &pin_info);
110 if (bp_result != BP_RESULT_OK) {
111 ASSERT(bp_result == BP_RESULT_NORECORD);
115 return dal_gpio_service_create_irq(
122 * Function: program_hpd_filter
125 * Programs HPD filter on associated HPD line
127 * @param [in] delay_on_connect_in_ms: Connect filter timeout
128 * @param [in] delay_on_disconnect_in_ms: Disconnect filter timeout
131 * true on success, false otherwise
133 static bool program_hpd_filter(
134 const struct dc_link *link)
140 int delay_on_connect_in_ms = 0;
141 int delay_on_disconnect_in_ms = 0;
143 if (link->is_hpd_filter_disabled)
145 /* Verify feature is supported */
146 switch (link->connector_signal) {
147 case SIGNAL_TYPE_DVI_SINGLE_LINK:
148 case SIGNAL_TYPE_DVI_DUAL_LINK:
149 case SIGNAL_TYPE_HDMI_TYPE_A:
150 /* Program hpd filter */
151 delay_on_connect_in_ms = 500;
152 delay_on_disconnect_in_ms = 100;
154 case SIGNAL_TYPE_DISPLAY_PORT:
155 case SIGNAL_TYPE_DISPLAY_PORT_MST:
156 /* Program hpd filter to allow DP signal to settle */
157 /* 500: not able to detect MST <-> SST switch as HPD is low for
158 * only 100ms on DELL U2413
159 * 0: some passive dongle still show aux mode instead of i2c
160 * 20-50:not enough to hide bouncing HPD with passive dongle.
161 * also see intermittent i2c read issues.
163 delay_on_connect_in_ms = 80;
164 delay_on_disconnect_in_ms = 0;
166 case SIGNAL_TYPE_LVDS:
167 case SIGNAL_TYPE_EDP:
169 /* Don't program hpd filter */
173 /* Obtain HPD handle */
174 hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
179 /* Setup HPD filtering */
180 if (dal_gpio_open(hpd, GPIO_MODE_INTERRUPT) == GPIO_RESULT_OK) {
181 struct gpio_hpd_config config;
183 config.delay_on_connect = delay_on_connect_in_ms;
184 config.delay_on_disconnect = delay_on_disconnect_in_ms;
186 dal_irq_setup_hpd_filter(hpd, &config);
192 ASSERT_CRITICAL(false);
195 /* Release HPD handle */
196 dal_gpio_destroy_irq(&hpd);
202 * dc_link_detect_sink() - Determine if there is a sink connected
204 * @type: Returned connection type
205 * Does not detect downstream devices, such as MST sinks
206 * or display connected through active dongles
208 bool dc_link_detect_sink(struct dc_link *link, enum dc_connection_type *type)
210 uint32_t is_hpd_high = 0;
211 struct gpio *hpd_pin;
213 if (link->connector_signal == SIGNAL_TYPE_LVDS) {
214 *type = dc_connection_single;
218 if (link->connector_signal == SIGNAL_TYPE_EDP)
219 link->dc->hwss.edp_wait_for_hpd_ready(link, true);
221 /* todo: may need to lock gpio access */
222 hpd_pin = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
224 goto hpd_gpio_failure;
226 dal_gpio_open(hpd_pin, GPIO_MODE_INTERRUPT);
227 dal_gpio_get_value(hpd_pin, &is_hpd_high);
228 dal_gpio_close(hpd_pin);
229 dal_gpio_destroy_irq(&hpd_pin);
232 *type = dc_connection_single;
233 /* TODO: need to do the actual detection */
235 *type = dc_connection_none;
244 static enum ddc_transaction_type get_ddc_transaction_type(
245 enum signal_type sink_signal)
247 enum ddc_transaction_type transaction_type = DDC_TRANSACTION_TYPE_NONE;
249 switch (sink_signal) {
250 case SIGNAL_TYPE_DVI_SINGLE_LINK:
251 case SIGNAL_TYPE_DVI_DUAL_LINK:
252 case SIGNAL_TYPE_HDMI_TYPE_A:
253 case SIGNAL_TYPE_LVDS:
254 case SIGNAL_TYPE_RGB:
255 transaction_type = DDC_TRANSACTION_TYPE_I2C;
258 case SIGNAL_TYPE_DISPLAY_PORT:
259 case SIGNAL_TYPE_EDP:
260 transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
263 case SIGNAL_TYPE_DISPLAY_PORT_MST:
264 /* MST does not use I2COverAux, but there is the
265 * SPECIAL use case for "immediate dwnstrm device
266 * access" (EPR#370830). */
267 transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
274 return transaction_type;
277 static enum signal_type get_basic_signal_type(
278 struct graphics_object_id encoder,
279 struct graphics_object_id downstream)
281 if (downstream.type == OBJECT_TYPE_CONNECTOR) {
282 switch (downstream.id) {
283 case CONNECTOR_ID_SINGLE_LINK_DVII:
284 switch (encoder.id) {
285 case ENCODER_ID_INTERNAL_DAC1:
286 case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
287 case ENCODER_ID_INTERNAL_DAC2:
288 case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
289 return SIGNAL_TYPE_RGB;
291 return SIGNAL_TYPE_DVI_SINGLE_LINK;
294 case CONNECTOR_ID_DUAL_LINK_DVII:
296 switch (encoder.id) {
297 case ENCODER_ID_INTERNAL_DAC1:
298 case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
299 case ENCODER_ID_INTERNAL_DAC2:
300 case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
301 return SIGNAL_TYPE_RGB;
303 return SIGNAL_TYPE_DVI_DUAL_LINK;
307 case CONNECTOR_ID_SINGLE_LINK_DVID:
308 return SIGNAL_TYPE_DVI_SINGLE_LINK;
309 case CONNECTOR_ID_DUAL_LINK_DVID:
310 return SIGNAL_TYPE_DVI_DUAL_LINK;
311 case CONNECTOR_ID_VGA:
312 return SIGNAL_TYPE_RGB;
313 case CONNECTOR_ID_HDMI_TYPE_A:
314 return SIGNAL_TYPE_HDMI_TYPE_A;
315 case CONNECTOR_ID_LVDS:
316 return SIGNAL_TYPE_LVDS;
317 case CONNECTOR_ID_DISPLAY_PORT:
318 return SIGNAL_TYPE_DISPLAY_PORT;
319 case CONNECTOR_ID_EDP:
320 return SIGNAL_TYPE_EDP;
322 return SIGNAL_TYPE_NONE;
324 } else if (downstream.type == OBJECT_TYPE_ENCODER) {
325 switch (downstream.id) {
326 case ENCODER_ID_EXTERNAL_NUTMEG:
327 case ENCODER_ID_EXTERNAL_TRAVIS:
328 return SIGNAL_TYPE_DISPLAY_PORT;
330 return SIGNAL_TYPE_NONE;
334 return SIGNAL_TYPE_NONE;
338 * dc_link_is_dp_sink_present() - Check if there is a native DP
339 * or passive DP-HDMI dongle connected
341 bool dc_link_is_dp_sink_present(struct dc_link *link)
343 enum gpio_result gpio_result;
344 uint32_t clock_pin = 0;
348 enum connector_id connector_id =
349 dal_graphics_object_id_get_connector_id(link->link_id);
352 ((connector_id == CONNECTOR_ID_DISPLAY_PORT) ||
353 (connector_id == CONNECTOR_ID_EDP));
355 ddc = dal_ddc_service_get_ddc_pin(link->ddc);
362 /* Open GPIO and set it to I2C mode */
363 /* Note: this GpioMode_Input will be converted
364 * to GpioConfigType_I2cAuxDualMode in GPIO component,
365 * which indicates we need additional delay */
367 if (GPIO_RESULT_OK != dal_ddc_open(
368 ddc, GPIO_MODE_INPUT, GPIO_DDC_CONFIG_TYPE_MODE_I2C)) {
369 dal_gpio_destroy_ddc(&ddc);
375 * Read GPIO: DP sink is present if both clock and data pins are zero
377 * [W/A] plug-unplug DP cable, sometimes customer board has
378 * one short pulse on clk_pin(1V, < 1ms). DP will be config to HDMI/DVI
379 * then monitor can't br light up. Add retry 3 times
380 * But in real passive dongle, it need additional 3ms to detect
383 gpio_result = dal_gpio_get_value(ddc->pin_clock, &clock_pin);
384 ASSERT(gpio_result == GPIO_RESULT_OK);
389 } while (retry++ < 3);
391 present = (gpio_result == GPIO_RESULT_OK) && !clock_pin;
400 * Detect output sink type
402 static enum signal_type link_detect_sink(
403 struct dc_link *link,
404 enum dc_detect_reason reason)
406 enum signal_type result = get_basic_signal_type(
407 link->link_enc->id, link->link_id);
409 /* Internal digital encoder will detect only dongles
410 * that require digital signal */
412 /* Detection mechanism is different
413 * for different native connectors.
414 * LVDS connector supports only LVDS signal;
415 * PCIE is a bus slot, the actual connector needs to be detected first;
416 * eDP connector supports only eDP signal;
417 * HDMI should check straps for audio */
419 /* PCIE detects the actual connector on add-on board */
421 if (link->link_id.id == CONNECTOR_ID_PCIE) {
422 /* ZAZTODO implement PCIE add-on card detection */
425 switch (link->link_id.id) {
426 case CONNECTOR_ID_HDMI_TYPE_A: {
427 /* check audio support:
428 * if native HDMI is not supported, switch to DVI */
429 struct audio_support *aud_support = &link->dc->res_pool->audio_support;
431 if (!aud_support->hdmi_audio_native)
432 if (link->link_id.id == CONNECTOR_ID_HDMI_TYPE_A)
433 result = SIGNAL_TYPE_DVI_SINGLE_LINK;
436 case CONNECTOR_ID_DISPLAY_PORT: {
437 /* DP HPD short pulse. Passive DP dongle will not
440 if (reason != DETECT_REASON_HPDRX) {
441 /* Check whether DP signal detected: if not -
442 * we assume signal is DVI; it could be corrected
443 * to HDMI after dongle detection
445 if (!dm_helpers_is_dp_sink_present(link))
446 result = SIGNAL_TYPE_DVI_SINGLE_LINK;
457 static enum signal_type decide_signal_from_strap_and_dongle_type(
458 enum display_dongle_type dongle_type,
459 struct audio_support *audio_support)
461 enum signal_type signal = SIGNAL_TYPE_NONE;
463 switch (dongle_type) {
464 case DISPLAY_DONGLE_DP_HDMI_DONGLE:
465 if (audio_support->hdmi_audio_on_dongle)
466 signal = SIGNAL_TYPE_HDMI_TYPE_A;
468 signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
470 case DISPLAY_DONGLE_DP_DVI_DONGLE:
471 signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
473 case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE:
474 if (audio_support->hdmi_audio_native)
475 signal = SIGNAL_TYPE_HDMI_TYPE_A;
477 signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
480 signal = SIGNAL_TYPE_NONE;
487 static enum signal_type dp_passive_dongle_detection(
488 struct ddc_service *ddc,
489 struct display_sink_capability *sink_cap,
490 struct audio_support *audio_support)
492 dal_ddc_service_i2c_query_dp_dual_mode_adaptor(
494 return decide_signal_from_strap_and_dongle_type(
495 sink_cap->dongle_type,
499 static void link_disconnect_sink(struct dc_link *link)
501 if (link->local_sink) {
502 dc_sink_release(link->local_sink);
503 link->local_sink = NULL;
506 link->dpcd_sink_count = 0;
509 static void link_disconnect_remap(struct dc_sink *prev_sink, struct dc_link *link)
511 dc_sink_release(link->local_sink);
512 link->local_sink = prev_sink;
516 static bool detect_dp(
517 struct dc_link *link,
518 struct display_sink_capability *sink_caps,
519 bool *converter_disable_audio,
520 struct audio_support *audio_support,
521 enum dc_detect_reason reason)
524 sink_caps->signal = link_detect_sink(link, reason);
525 sink_caps->transaction_type =
526 get_ddc_transaction_type(sink_caps->signal);
528 if (sink_caps->transaction_type == DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
529 sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT;
530 if (!detect_dp_sink_caps(link))
533 if (is_mst_supported(link)) {
534 sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
535 link->type = dc_connection_mst_branch;
537 dal_ddc_service_set_transaction_type(
539 sink_caps->transaction_type);
542 * This call will initiate MST topology discovery. Which
543 * will detect MST ports and add new DRM connector DRM
544 * framework. Then read EDID via remote i2c over aux. In
545 * the end, will notify DRM detect result and save EDID
546 * into DRM framework.
548 * .detect is called by .fill_modes.
549 * .fill_modes is called by user mode ioctl
550 * DRM_IOCTL_MODE_GETCONNECTOR.
552 * .get_modes is called by .fill_modes.
554 * call .get_modes, AMDGPU DM implementation will create
555 * new dc_sink and add to dc_link. For long HPD plug
556 * in/out, MST has its own handle.
558 * Therefore, just after dc_create, link->sink is not
559 * created for MST until user mode app calls
560 * DRM_IOCTL_MODE_GETCONNECTOR.
562 * Need check ->sink usages in case ->sink = NULL
563 * TODO: s3 resume check
565 if (reason == DETECT_REASON_BOOT)
568 dm_helpers_dp_update_branch_info(
572 if (!dm_helpers_dp_mst_start_top_mgr(
575 /* MST not supported */
576 link->type = dc_connection_single;
577 sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT;
581 if (link->type != dc_connection_mst_branch &&
582 is_dp_active_dongle(link)) {
583 /* DP active dongles */
584 link->type = dc_connection_active_dongle;
585 if (!link->dpcd_caps.sink_count.bits.SINK_COUNT) {
587 * active dongle unplug processing for short irq
589 link_disconnect_sink(link);
593 if (link->dpcd_caps.dongle_type != DISPLAY_DONGLE_DP_HDMI_CONVERTER)
594 *converter_disable_audio = true;
597 /* DP passive dongles */
598 sink_caps->signal = dp_passive_dongle_detection(link->ddc,
606 static bool is_same_edid(struct dc_edid *old_edid, struct dc_edid *new_edid)
608 if (old_edid->length != new_edid->length)
611 if (new_edid->length == 0)
614 return (memcmp(old_edid->raw_edid, new_edid->raw_edid, new_edid->length) == 0);
618 * dc_link_detect() - Detect if a sink is attached to a given link
620 * link->local_sink is created or destroyed as needed.
622 * This does not create remote sinks but will trigger DM
623 * to start MST detection if a branch is detected.
625 bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason)
627 struct dc_sink_init_data sink_init_data = { 0 };
628 struct display_sink_capability sink_caps = { 0 };
630 bool converter_disable_audio = false;
631 struct audio_support *aud_support = &link->dc->res_pool->audio_support;
632 bool same_edid = false;
633 enum dc_edid_status edid_status;
634 struct dc_context *dc_ctx = link->ctx;
635 struct dc_sink *sink = NULL;
636 struct dc_sink *prev_sink = NULL;
637 struct dpcd_caps prev_dpcd_caps;
638 bool same_dpcd = true;
639 enum dc_connection_type new_connection_type = dc_connection_none;
640 DC_LOGGER_INIT(link->ctx->logger);
641 if (link->connector_signal == SIGNAL_TYPE_VIRTUAL)
644 if (false == dc_link_detect_sink(link, &new_connection_type)) {
649 if (link->connector_signal == SIGNAL_TYPE_EDP &&
653 if (link->connector_signal == SIGNAL_TYPE_LVDS &&
657 prev_sink = link->local_sink;
658 if (prev_sink != NULL) {
659 dc_sink_retain(prev_sink);
660 memcpy(&prev_dpcd_caps, &link->dpcd_caps, sizeof(struct dpcd_caps));
662 link_disconnect_sink(link);
664 if (new_connection_type != dc_connection_none) {
665 link->type = new_connection_type;
667 /* From Disconnected-to-Connected. */
668 switch (link->connector_signal) {
669 case SIGNAL_TYPE_HDMI_TYPE_A: {
670 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
671 if (aud_support->hdmi_audio_native)
672 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
674 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
678 case SIGNAL_TYPE_DVI_SINGLE_LINK: {
679 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
680 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
684 case SIGNAL_TYPE_DVI_DUAL_LINK: {
685 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
686 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
690 case SIGNAL_TYPE_LVDS: {
691 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
692 sink_caps.signal = SIGNAL_TYPE_LVDS;
696 case SIGNAL_TYPE_EDP: {
697 detect_edp_sink_caps(link);
698 sink_caps.transaction_type =
699 DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
700 sink_caps.signal = SIGNAL_TYPE_EDP;
704 case SIGNAL_TYPE_DISPLAY_PORT: {
708 &converter_disable_audio,
709 aud_support, reason)) {
710 if (prev_sink != NULL)
711 dc_sink_release(prev_sink);
715 // Check if dpcp block is the same
716 if (prev_sink != NULL) {
717 if (memcmp(&link->dpcd_caps, &prev_dpcd_caps, sizeof(struct dpcd_caps)))
720 /* Active dongle plug in without display or downstream unplug*/
721 if (link->type == dc_connection_active_dongle
722 && link->dpcd_caps.sink_count.
723 bits.SINK_COUNT == 0) {
724 if (prev_sink != NULL) {
725 /* Downstream unplug */
726 dc_sink_release(prev_sink);
728 /* Empty dongle plug in */
729 for (i = 0; i < LINK_TRAINING_MAX_VERIFY_RETRY; i++) {
732 dp_verify_link_cap(link,
733 &link->reported_link_cap,
743 if (link->type == dc_connection_mst_branch) {
744 LINK_INFO("link=%d, mst branch is now Connected\n",
746 /* Need to setup mst link_cap struct here
747 * otherwise dc_link_detect() will leave mst link_cap
748 * empty which leads to allocate_mst_payload() has "0"
749 * pbn_per_slot value leading to exception on dc_fixpt_div()
751 link->verified_link_cap = link->reported_link_cap;
752 if (prev_sink != NULL)
753 dc_sink_release(prev_sink);
761 DC_ERROR("Invalid connector type! signal:%d\n",
762 link->connector_signal);
763 if (prev_sink != NULL)
764 dc_sink_release(prev_sink);
768 if (link->dpcd_caps.sink_count.bits.SINK_COUNT)
769 link->dpcd_sink_count = link->dpcd_caps.sink_count.
772 link->dpcd_sink_count = 1;
774 dal_ddc_service_set_transaction_type(
776 sink_caps.transaction_type);
778 link->aux_mode = dal_ddc_service_is_in_aux_transaction_mode(
781 sink_init_data.link = link;
782 sink_init_data.sink_signal = sink_caps.signal;
784 sink = dc_sink_create(&sink_init_data);
786 DC_ERROR("Failed to create sink!\n");
787 if (prev_sink != NULL)
788 dc_sink_release(prev_sink);
792 sink->dongle_max_pix_clk = sink_caps.max_hdmi_pixel_clock;
793 sink->converter_disable_audio = converter_disable_audio;
795 link->local_sink = sink;
797 edid_status = dm_helpers_read_local_edid(
802 switch (edid_status) {
803 case EDID_BAD_CHECKSUM:
804 DC_LOG_ERROR("EDID checksum invalid.\n");
806 case EDID_NO_RESPONSE:
807 DC_LOG_ERROR("No EDID read.\n");
810 * Abort detection for non-DP connectors if we have
813 * DP needs to report as connected if HDP is high
814 * even if we have no EDID in order to go to
817 if (dc_is_hdmi_signal(link->connector_signal) ||
818 dc_is_dvi_signal(link->connector_signal)) {
819 if (prev_sink != NULL)
820 dc_sink_release(prev_sink);
828 // Check if edid is the same
829 if ((prev_sink != NULL) && ((edid_status == EDID_THE_SAME) || (edid_status == EDID_OK)))
830 same_edid = is_same_edid(&prev_sink->dc_edid, &sink->dc_edid);
832 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
833 sink_caps.transaction_type == DDC_TRANSACTION_TYPE_I2C_OVER_AUX &&
834 reason != DETECT_REASON_HPDRX) {
836 * TODO debug why Dell 2413 doesn't like
840 /* deal with non-mst cases */
841 for (i = 0; i < LINK_TRAINING_MAX_VERIFY_RETRY; i++) {
844 dp_verify_link_cap(link,
845 &link->reported_link_cap,
853 // If edid is the same, then discard new sink and revert back to original sink
855 link_disconnect_remap(prev_sink, link);
862 /* HDMI-DVI Dongle */
863 if (sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A &&
864 !sink->edid_caps.edid_hdmi)
865 sink->sink_signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
867 /* Connectivity log: detection */
868 for (i = 0; i < sink->dc_edid.length / EDID_BLOCK_SIZE; i++) {
869 CONN_DATA_DETECT(link,
870 &sink->dc_edid.raw_edid[i * EDID_BLOCK_SIZE],
872 "%s: [Block %d] ", sink->edid_caps.display_name, i);
875 DC_LOG_DETECTION_EDID_PARSER("%s: "
876 "manufacturer_id = %X, "
878 "serial_number = %X, "
879 "manufacture_week = %d, "
880 "manufacture_year = %d, "
881 "display_name = %s, "
882 "speaker_flag = %d, "
883 "audio_mode_count = %d\n",
885 sink->edid_caps.manufacturer_id,
886 sink->edid_caps.product_id,
887 sink->edid_caps.serial_number,
888 sink->edid_caps.manufacture_week,
889 sink->edid_caps.manufacture_year,
890 sink->edid_caps.display_name,
891 sink->edid_caps.speaker_flags,
892 sink->edid_caps.audio_mode_count);
894 for (i = 0; i < sink->edid_caps.audio_mode_count; i++) {
895 DC_LOG_DETECTION_EDID_PARSER("%s: mode number = %d, "
897 "channel_count = %d, "
899 "sample_size = %d\n",
902 sink->edid_caps.audio_modes[i].format_code,
903 sink->edid_caps.audio_modes[i].channel_count,
904 sink->edid_caps.audio_modes[i].sample_rate,
905 sink->edid_caps.audio_modes[i].sample_size);
909 /* From Connected-to-Disconnected. */
910 if (link->type == dc_connection_mst_branch) {
911 LINK_INFO("link=%d, mst branch is now Disconnected\n",
914 dm_helpers_dp_mst_stop_top_mgr(link->ctx, link);
916 link->mst_stream_alloc_table.stream_count = 0;
917 memset(link->mst_stream_alloc_table.stream_allocations, 0, sizeof(link->mst_stream_alloc_table.stream_allocations));
920 link->type = dc_connection_none;
921 sink_caps.signal = SIGNAL_TYPE_NONE;
924 LINK_INFO("link=%d, dc_sink_in=%p is now %s prev_sink=%p dpcd same=%d edid same=%d\n",
925 link->link_index, sink,
926 (sink_caps.signal == SIGNAL_TYPE_NONE ?
927 "Disconnected":"Connected"), prev_sink,
928 same_dpcd, same_edid);
930 if (prev_sink != NULL)
931 dc_sink_release(prev_sink);
936 bool dc_link_get_hpd_state(struct dc_link *dc_link)
938 struct gpio *hpd_pin;
941 hpd_pin = get_hpd_gpio(dc_link->ctx->dc_bios,
942 dc_link->link_id, dc_link->ctx->gpio_service);
946 dal_gpio_open(hpd_pin, GPIO_MODE_INTERRUPT);
947 dal_gpio_get_value(hpd_pin, &state);
948 dal_gpio_close(hpd_pin);
949 dal_gpio_destroy_irq(&hpd_pin);
954 static enum hpd_source_id get_hpd_line(
955 struct dc_link *link)
958 enum hpd_source_id hpd_id = HPD_SOURCEID_UNKNOWN;
960 hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
963 switch (dal_irq_get_source(hpd)) {
964 case DC_IRQ_SOURCE_HPD1:
965 hpd_id = HPD_SOURCEID1;
967 case DC_IRQ_SOURCE_HPD2:
968 hpd_id = HPD_SOURCEID2;
970 case DC_IRQ_SOURCE_HPD3:
971 hpd_id = HPD_SOURCEID3;
973 case DC_IRQ_SOURCE_HPD4:
974 hpd_id = HPD_SOURCEID4;
976 case DC_IRQ_SOURCE_HPD5:
977 hpd_id = HPD_SOURCEID5;
979 case DC_IRQ_SOURCE_HPD6:
980 hpd_id = HPD_SOURCEID6;
987 dal_gpio_destroy_irq(&hpd);
993 static enum channel_id get_ddc_line(struct dc_link *link)
996 enum channel_id channel = CHANNEL_ID_UNKNOWN;
998 ddc = dal_ddc_service_get_ddc_pin(link->ddc);
1001 switch (dal_ddc_get_line(ddc)) {
1002 case GPIO_DDC_LINE_DDC1:
1003 channel = CHANNEL_ID_DDC1;
1005 case GPIO_DDC_LINE_DDC2:
1006 channel = CHANNEL_ID_DDC2;
1008 case GPIO_DDC_LINE_DDC3:
1009 channel = CHANNEL_ID_DDC3;
1011 case GPIO_DDC_LINE_DDC4:
1012 channel = CHANNEL_ID_DDC4;
1014 case GPIO_DDC_LINE_DDC5:
1015 channel = CHANNEL_ID_DDC5;
1017 case GPIO_DDC_LINE_DDC6:
1018 channel = CHANNEL_ID_DDC6;
1020 case GPIO_DDC_LINE_DDC_VGA:
1021 channel = CHANNEL_ID_DDC_VGA;
1023 case GPIO_DDC_LINE_I2C_PAD:
1024 channel = CHANNEL_ID_I2C_PAD;
1027 BREAK_TO_DEBUGGER();
1035 static enum transmitter translate_encoder_to_transmitter(
1036 struct graphics_object_id encoder)
1038 switch (encoder.id) {
1039 case ENCODER_ID_INTERNAL_UNIPHY:
1040 switch (encoder.enum_id) {
1042 return TRANSMITTER_UNIPHY_A;
1044 return TRANSMITTER_UNIPHY_B;
1046 return TRANSMITTER_UNKNOWN;
1049 case ENCODER_ID_INTERNAL_UNIPHY1:
1050 switch (encoder.enum_id) {
1052 return TRANSMITTER_UNIPHY_C;
1054 return TRANSMITTER_UNIPHY_D;
1056 return TRANSMITTER_UNKNOWN;
1059 case ENCODER_ID_INTERNAL_UNIPHY2:
1060 switch (encoder.enum_id) {
1062 return TRANSMITTER_UNIPHY_E;
1064 return TRANSMITTER_UNIPHY_F;
1066 return TRANSMITTER_UNKNOWN;
1069 case ENCODER_ID_INTERNAL_UNIPHY3:
1070 switch (encoder.enum_id) {
1072 return TRANSMITTER_UNIPHY_G;
1074 return TRANSMITTER_UNKNOWN;
1077 case ENCODER_ID_EXTERNAL_NUTMEG:
1078 switch (encoder.enum_id) {
1080 return TRANSMITTER_NUTMEG_CRT;
1082 return TRANSMITTER_UNKNOWN;
1085 case ENCODER_ID_EXTERNAL_TRAVIS:
1086 switch (encoder.enum_id) {
1088 return TRANSMITTER_TRAVIS_CRT;
1090 return TRANSMITTER_TRAVIS_LCD;
1092 return TRANSMITTER_UNKNOWN;
1096 return TRANSMITTER_UNKNOWN;
1100 static bool construct(
1101 struct dc_link *link,
1102 const struct link_init_data *init_params)
1105 struct gpio *hpd_gpio = NULL;
1106 struct ddc_service_init_data ddc_service_init_data = { { 0 } };
1107 struct dc_context *dc_ctx = init_params->ctx;
1108 struct encoder_init_data enc_init_data = { 0 };
1109 struct integrated_info info = {{{ 0 }}};
1110 struct dc_bios *bios = init_params->dc->ctx->dc_bios;
1111 const struct dc_vbios_funcs *bp_funcs = bios->funcs;
1112 DC_LOGGER_INIT(dc_ctx->logger);
1114 link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
1115 link->irq_source_hpd_rx = DC_IRQ_SOURCE_INVALID;
1117 link->link_status.dpcd_caps = &link->dpcd_caps;
1119 link->dc = init_params->dc;
1121 link->link_index = init_params->link_index;
1123 link->link_id = bios->funcs->get_connector_id(bios, init_params->connector_index);
1125 if (link->link_id.type != OBJECT_TYPE_CONNECTOR) {
1126 dm_error("%s: Invalid Connector ObjectID from Adapter Service for connector index:%d! type %d expected %d\n",
1127 __func__, init_params->connector_index,
1128 link->link_id.type, OBJECT_TYPE_CONNECTOR);
1132 if (link->dc->res_pool->funcs->link_init)
1133 link->dc->res_pool->funcs->link_init(link);
1135 hpd_gpio = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
1137 if (hpd_gpio != NULL)
1138 link->irq_source_hpd = dal_irq_get_source(hpd_gpio);
1140 switch (link->link_id.id) {
1141 case CONNECTOR_ID_HDMI_TYPE_A:
1142 link->connector_signal = SIGNAL_TYPE_HDMI_TYPE_A;
1145 case CONNECTOR_ID_SINGLE_LINK_DVID:
1146 case CONNECTOR_ID_SINGLE_LINK_DVII:
1147 link->connector_signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1149 case CONNECTOR_ID_DUAL_LINK_DVID:
1150 case CONNECTOR_ID_DUAL_LINK_DVII:
1151 link->connector_signal = SIGNAL_TYPE_DVI_DUAL_LINK;
1153 case CONNECTOR_ID_DISPLAY_PORT:
1154 link->connector_signal = SIGNAL_TYPE_DISPLAY_PORT;
1156 if (hpd_gpio != NULL)
1157 link->irq_source_hpd_rx =
1158 dal_irq_get_rx_source(hpd_gpio);
1161 case CONNECTOR_ID_EDP:
1162 link->connector_signal = SIGNAL_TYPE_EDP;
1164 if (hpd_gpio != NULL) {
1165 link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
1166 link->irq_source_hpd_rx =
1167 dal_irq_get_rx_source(hpd_gpio);
1170 case CONNECTOR_ID_LVDS:
1171 link->connector_signal = SIGNAL_TYPE_LVDS;
1174 DC_LOG_WARNING("Unsupported Connector type:%d!\n", link->link_id.id);
1178 if (hpd_gpio != NULL) {
1179 dal_gpio_destroy_irq(&hpd_gpio);
1183 /* TODO: #DAL3 Implement id to str function.*/
1184 LINK_INFO("Connector[%d] description:"
1186 init_params->connector_index,
1187 link->connector_signal);
1189 ddc_service_init_data.ctx = link->ctx;
1190 ddc_service_init_data.id = link->link_id;
1191 ddc_service_init_data.link = link;
1192 link->ddc = dal_ddc_service_create(&ddc_service_init_data);
1194 if (link->ddc == NULL) {
1195 DC_ERROR("Failed to create ddc_service!\n");
1196 goto ddc_create_fail;
1201 dal_ddc_service_get_ddc_pin(link->ddc));
1203 enc_init_data.ctx = dc_ctx;
1204 bp_funcs->get_src_obj(dc_ctx->dc_bios, link->link_id, 0, &enc_init_data.encoder);
1205 enc_init_data.connector = link->link_id;
1206 enc_init_data.channel = get_ddc_line(link);
1207 enc_init_data.hpd_source = get_hpd_line(link);
1209 link->hpd_src = enc_init_data.hpd_source;
1211 enc_init_data.transmitter =
1212 translate_encoder_to_transmitter(enc_init_data.encoder);
1213 link->link_enc = link->dc->res_pool->funcs->link_enc_create(
1216 if( link->link_enc == NULL) {
1217 DC_ERROR("Failed to create link encoder!\n");
1218 goto link_enc_create_fail;
1221 link->link_enc_hw_inst = link->link_enc->transmitter;
1223 for (i = 0; i < 4; i++) {
1225 bp_funcs->get_device_tag(dc_ctx->dc_bios, link->link_id, i, &link->device_tag)) {
1226 DC_ERROR("Failed to find device tag!\n");
1227 goto device_tag_fail;
1230 /* Look for device tag that matches connector signal,
1231 * CRT for rgb, LCD for other supported signal tyes
1233 if (!bp_funcs->is_device_id_supported(dc_ctx->dc_bios, link->device_tag.dev_id))
1235 if (link->device_tag.dev_id.device_type == DEVICE_TYPE_CRT
1236 && link->connector_signal != SIGNAL_TYPE_RGB)
1238 if (link->device_tag.dev_id.device_type == DEVICE_TYPE_LCD
1239 && link->connector_signal == SIGNAL_TYPE_RGB)
1244 if (bios->integrated_info)
1245 info = *bios->integrated_info;
1247 /* Look for channel mapping corresponding to connector and device tag */
1248 for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; i++) {
1249 struct external_display_path *path =
1250 &info.ext_disp_conn_info.path[i];
1251 if (path->device_connector_id.enum_id == link->link_id.enum_id
1252 && path->device_connector_id.id == link->link_id.id
1253 && path->device_connector_id.type == link->link_id.type) {
1255 if (link->device_tag.acpi_device != 0
1256 && path->device_acpi_enum == link->device_tag.acpi_device) {
1257 link->ddi_channel_mapping = path->channel_mapping;
1258 link->chip_caps = path->caps;
1259 } else if (path->device_tag ==
1260 link->device_tag.dev_id.raw_device_tag) {
1261 link->ddi_channel_mapping = path->channel_mapping;
1262 link->chip_caps = path->caps;
1269 * TODO check if GPIO programmed correctly
1271 * If GPIO isn't programmed correctly HPD might not rise or drain
1272 * fast enough, leading to bounces.
1274 program_hpd_filter(link);
1278 link->link_enc->funcs->destroy(&link->link_enc);
1279 link_enc_create_fail:
1280 dal_ddc_service_destroy(&link->ddc);
1284 if (hpd_gpio != NULL) {
1285 dal_gpio_destroy_irq(&hpd_gpio);
1291 /*******************************************************************************
1293 ******************************************************************************/
1294 struct dc_link *link_create(const struct link_init_data *init_params)
1296 struct dc_link *link =
1297 kzalloc(sizeof(*link), GFP_KERNEL);
1302 if (false == construct(link, init_params))
1303 goto construct_fail;
1314 void link_destroy(struct dc_link **link)
1321 static void dpcd_configure_panel_mode(
1322 struct dc_link *link,
1323 enum dp_panel_mode panel_mode)
1325 union dpcd_edp_config edp_config_set;
1326 bool panel_mode_edp = false;
1327 DC_LOGGER_INIT(link->ctx->logger);
1329 memset(&edp_config_set, '\0', sizeof(union dpcd_edp_config));
1331 if (DP_PANEL_MODE_DEFAULT != panel_mode) {
1333 switch (panel_mode) {
1334 case DP_PANEL_MODE_EDP:
1335 case DP_PANEL_MODE_SPECIAL:
1336 panel_mode_edp = true;
1343 /*set edp panel mode in receiver*/
1344 core_link_read_dpcd(
1346 DP_EDP_CONFIGURATION_SET,
1347 &edp_config_set.raw,
1348 sizeof(edp_config_set.raw));
1350 if (edp_config_set.bits.PANEL_MODE_EDP
1351 != panel_mode_edp) {
1352 enum ddc_result result = DDC_RESULT_UNKNOWN;
1354 edp_config_set.bits.PANEL_MODE_EDP =
1356 result = core_link_write_dpcd(
1358 DP_EDP_CONFIGURATION_SET,
1359 &edp_config_set.raw,
1360 sizeof(edp_config_set.raw));
1362 ASSERT(result == DDC_RESULT_SUCESSFULL);
1365 DC_LOG_DETECTION_DP_CAPS("Link: %d eDP panel mode supported: %d "
1366 "eDP panel mode enabled: %d \n",
1368 link->dpcd_caps.panel_mode_edp,
1372 static void enable_stream_features(struct pipe_ctx *pipe_ctx)
1374 struct dc_stream_state *stream = pipe_ctx->stream;
1375 struct dc_link *link = stream->sink->link;
1376 union down_spread_ctrl old_downspread;
1377 union down_spread_ctrl new_downspread;
1379 core_link_read_dpcd(link, DP_DOWNSPREAD_CTRL,
1380 &old_downspread.raw, sizeof(old_downspread));
1382 new_downspread.raw = old_downspread.raw;
1384 new_downspread.bits.IGNORE_MSA_TIMING_PARAM =
1385 (stream->ignore_msa_timing_param) ? 1 : 0;
1387 if (new_downspread.raw != old_downspread.raw) {
1388 core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
1389 &new_downspread.raw, sizeof(new_downspread));
1393 static enum dc_status enable_link_dp(
1394 struct dc_state *state,
1395 struct pipe_ctx *pipe_ctx)
1397 struct dc_stream_state *stream = pipe_ctx->stream;
1398 enum dc_status status;
1399 bool skip_video_pattern;
1400 struct dc_link *link = stream->sink->link;
1401 struct dc_link_settings link_settings = {0};
1402 enum dp_panel_mode panel_mode;
1404 /* get link settings for video mode timing */
1405 decide_link_settings(stream, &link_settings);
1407 pipe_ctx->stream_res.pix_clk_params.requested_sym_clk =
1408 link_settings.link_rate * LINK_RATE_REF_FREQ_IN_KHZ;
1409 state->dccg->funcs->update_clocks(state->dccg, state, false);
1413 pipe_ctx->stream->signal,
1414 pipe_ctx->clock_source->id,
1417 if (stream->sink->edid_caps.panel_patch.dppowerup_delay > 0) {
1418 int delay_dp_power_up_in_ms = stream->sink->edid_caps.panel_patch.dppowerup_delay;
1420 msleep(delay_dp_power_up_in_ms);
1423 panel_mode = dp_get_panel_mode(link);
1424 dpcd_configure_panel_mode(link, panel_mode);
1426 skip_video_pattern = true;
1428 if (link_settings.link_rate == LINK_RATE_LOW)
1429 skip_video_pattern = false;
1431 if (perform_link_training_with_retries(
1435 LINK_TRAINING_ATTEMPTS)) {
1436 link->cur_link_settings = link_settings;
1440 status = DC_FAIL_DP_LINK_TRAINING;
1445 static enum dc_status enable_link_edp(
1446 struct dc_state *state,
1447 struct pipe_ctx *pipe_ctx)
1449 enum dc_status status;
1450 struct dc_stream_state *stream = pipe_ctx->stream;
1451 struct dc_link *link = stream->sink->link;
1452 /*in case it is not on*/
1453 link->dc->hwss.edp_power_control(link, true);
1454 link->dc->hwss.edp_wait_for_hpd_ready(link, true);
1456 status = enable_link_dp(state, pipe_ctx);
1462 static enum dc_status enable_link_dp_mst(
1463 struct dc_state *state,
1464 struct pipe_ctx *pipe_ctx)
1466 struct dc_link *link = pipe_ctx->stream->sink->link;
1468 /* sink signal type after MST branch is MST. Multiple MST sinks
1469 * share one link. Link DP PHY is enable or training only once.
1471 if (link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN)
1474 /* clear payload table */
1475 dm_helpers_dp_mst_clear_payload_allocation_table(link->ctx, link);
1477 /* set the sink to MST mode before enabling the link */
1478 dp_enable_mst_on_sink(link, true);
1480 return enable_link_dp(state, pipe_ctx);
1483 static bool get_ext_hdmi_settings(struct pipe_ctx *pipe_ctx,
1484 enum engine_id eng_id,
1485 struct ext_hdmi_settings *settings)
1487 bool result = false;
1489 struct integrated_info *integrated_info =
1490 pipe_ctx->stream->ctx->dc_bios->integrated_info;
1492 if (integrated_info == NULL)
1496 * Get retimer settings from sbios for passing SI eye test for DCE11
1497 * The setting values are varied based on board revision and port id
1498 * Therefore the setting values of each ports is passed by sbios.
1501 // Check if current bios contains ext Hdmi settings
1502 if (integrated_info->gpu_cap_info & 0x20) {
1504 case ENGINE_ID_DIGA:
1505 settings->slv_addr = integrated_info->dp0_ext_hdmi_slv_addr;
1506 settings->reg_num = integrated_info->dp0_ext_hdmi_6g_reg_num;
1507 settings->reg_num_6g = integrated_info->dp0_ext_hdmi_6g_reg_num;
1508 memmove(settings->reg_settings,
1509 integrated_info->dp0_ext_hdmi_reg_settings,
1510 sizeof(integrated_info->dp0_ext_hdmi_reg_settings));
1511 memmove(settings->reg_settings_6g,
1512 integrated_info->dp0_ext_hdmi_6g_reg_settings,
1513 sizeof(integrated_info->dp0_ext_hdmi_6g_reg_settings));
1516 case ENGINE_ID_DIGB:
1517 settings->slv_addr = integrated_info->dp1_ext_hdmi_slv_addr;
1518 settings->reg_num = integrated_info->dp1_ext_hdmi_6g_reg_num;
1519 settings->reg_num_6g = integrated_info->dp1_ext_hdmi_6g_reg_num;
1520 memmove(settings->reg_settings,
1521 integrated_info->dp1_ext_hdmi_reg_settings,
1522 sizeof(integrated_info->dp1_ext_hdmi_reg_settings));
1523 memmove(settings->reg_settings_6g,
1524 integrated_info->dp1_ext_hdmi_6g_reg_settings,
1525 sizeof(integrated_info->dp1_ext_hdmi_6g_reg_settings));
1528 case ENGINE_ID_DIGC:
1529 settings->slv_addr = integrated_info->dp2_ext_hdmi_slv_addr;
1530 settings->reg_num = integrated_info->dp2_ext_hdmi_6g_reg_num;
1531 settings->reg_num_6g = integrated_info->dp2_ext_hdmi_6g_reg_num;
1532 memmove(settings->reg_settings,
1533 integrated_info->dp2_ext_hdmi_reg_settings,
1534 sizeof(integrated_info->dp2_ext_hdmi_reg_settings));
1535 memmove(settings->reg_settings_6g,
1536 integrated_info->dp2_ext_hdmi_6g_reg_settings,
1537 sizeof(integrated_info->dp2_ext_hdmi_6g_reg_settings));
1540 case ENGINE_ID_DIGD:
1541 settings->slv_addr = integrated_info->dp3_ext_hdmi_slv_addr;
1542 settings->reg_num = integrated_info->dp3_ext_hdmi_6g_reg_num;
1543 settings->reg_num_6g = integrated_info->dp3_ext_hdmi_6g_reg_num;
1544 memmove(settings->reg_settings,
1545 integrated_info->dp3_ext_hdmi_reg_settings,
1546 sizeof(integrated_info->dp3_ext_hdmi_reg_settings));
1547 memmove(settings->reg_settings_6g,
1548 integrated_info->dp3_ext_hdmi_6g_reg_settings,
1549 sizeof(integrated_info->dp3_ext_hdmi_6g_reg_settings));
1556 if (result == true) {
1557 // Validate settings from bios integrated info table
1558 if (settings->slv_addr == 0)
1560 if (settings->reg_num > 9)
1562 if (settings->reg_num_6g > 3)
1565 for (i = 0; i < settings->reg_num; i++) {
1566 if (settings->reg_settings[i].i2c_reg_index > 0x20)
1570 for (i = 0; i < settings->reg_num_6g; i++) {
1571 if (settings->reg_settings_6g[i].i2c_reg_index > 0x20)
1580 static bool i2c_write(struct pipe_ctx *pipe_ctx,
1581 uint8_t address, uint8_t *buffer, uint32_t length)
1583 struct i2c_command cmd = {0};
1584 struct i2c_payload payload = {0};
1586 memset(&payload, 0, sizeof(payload));
1587 memset(&cmd, 0, sizeof(cmd));
1589 cmd.number_of_payloads = 1;
1590 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
1591 cmd.speed = pipe_ctx->stream->ctx->dc->caps.i2c_speed_in_khz;
1593 payload.address = address;
1594 payload.data = buffer;
1595 payload.length = length;
1596 payload.write = true;
1597 cmd.payloads = &payload;
1599 if (dm_helpers_submit_i2c(pipe_ctx->stream->ctx,
1600 pipe_ctx->stream->sink->link, &cmd))
1606 static void write_i2c_retimer_setting(
1607 struct pipe_ctx *pipe_ctx,
1609 bool is_over_340mhz,
1610 struct ext_hdmi_settings *settings)
1612 uint8_t slave_address = (settings->slv_addr >> 1);
1614 const uint8_t apply_rx_tx_change = 0x4;
1615 uint8_t offset = 0xA;
1618 bool i2c_success = false;
1619 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
1621 memset(&buffer, 0, sizeof(buffer));
1623 /* Start Ext-Hdmi programming*/
1625 for (i = 0; i < settings->reg_num; i++) {
1626 /* Apply 3G settings */
1627 if (settings->reg_settings[i].i2c_reg_index <= 0x20) {
1629 buffer[0] = settings->reg_settings[i].i2c_reg_index;
1630 buffer[1] = settings->reg_settings[i].i2c_reg_val;
1631 i2c_success = i2c_write(pipe_ctx, slave_address,
1632 buffer, sizeof(buffer));
1633 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
1634 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
1635 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1639 ASSERT(i2c_success);
1641 /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A
1642 * needs to be set to 1 on every 0xA-0xC write.
1644 if (settings->reg_settings[i].i2c_reg_index == 0xA ||
1645 settings->reg_settings[i].i2c_reg_index == 0xB ||
1646 settings->reg_settings[i].i2c_reg_index == 0xC) {
1648 /* Query current value from offset 0xA */
1649 if (settings->reg_settings[i].i2c_reg_index == 0xA)
1650 value = settings->reg_settings[i].i2c_reg_val;
1653 dal_ddc_service_query_ddc_data(
1654 pipe_ctx->stream->sink->link->ddc,
1655 slave_address, &offset, 1, &value, 1);
1658 ASSERT(i2c_success);
1662 /* Set APPLY_RX_TX_CHANGE bit to 1 */
1663 buffer[1] = value | apply_rx_tx_change;
1664 i2c_success = i2c_write(pipe_ctx, slave_address,
1665 buffer, sizeof(buffer));
1666 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
1667 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1668 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1671 ASSERT(i2c_success);
1676 /* Apply 3G settings */
1677 if (is_over_340mhz) {
1678 for (i = 0; i < settings->reg_num_6g; i++) {
1679 /* Apply 3G settings */
1680 if (settings->reg_settings[i].i2c_reg_index <= 0x20) {
1682 buffer[0] = settings->reg_settings_6g[i].i2c_reg_index;
1683 buffer[1] = settings->reg_settings_6g[i].i2c_reg_val;
1684 i2c_success = i2c_write(pipe_ctx, slave_address,
1685 buffer, sizeof(buffer));
1686 RETIMER_REDRIVER_INFO("above 340Mhz: retimer write to slave_address = 0x%x,\
1687 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1688 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1692 ASSERT(i2c_success);
1694 /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A
1695 * needs to be set to 1 on every 0xA-0xC write.
1697 if (settings->reg_settings_6g[i].i2c_reg_index == 0xA ||
1698 settings->reg_settings_6g[i].i2c_reg_index == 0xB ||
1699 settings->reg_settings_6g[i].i2c_reg_index == 0xC) {
1701 /* Query current value from offset 0xA */
1702 if (settings->reg_settings_6g[i].i2c_reg_index == 0xA)
1703 value = settings->reg_settings_6g[i].i2c_reg_val;
1706 dal_ddc_service_query_ddc_data(
1707 pipe_ctx->stream->sink->link->ddc,
1708 slave_address, &offset, 1, &value, 1);
1711 ASSERT(i2c_success);
1715 /* Set APPLY_RX_TX_CHANGE bit to 1 */
1716 buffer[1] = value | apply_rx_tx_change;
1717 i2c_success = i2c_write(pipe_ctx, slave_address,
1718 buffer, sizeof(buffer));
1719 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
1720 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1721 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1724 ASSERT(i2c_success);
1731 /* Program additional settings if using 640x480 resolution */
1733 /* Write offset 0xFF to 0x01 */
1736 i2c_success = i2c_write(pipe_ctx, slave_address,
1737 buffer, sizeof(buffer));
1738 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
1739 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1740 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1743 ASSERT(i2c_success);
1745 /* Write offset 0x00 to 0x23 */
1748 i2c_success = i2c_write(pipe_ctx, slave_address,
1749 buffer, sizeof(buffer));
1750 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
1751 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1752 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1755 ASSERT(i2c_success);
1757 /* Write offset 0xff to 0x00 */
1760 i2c_success = i2c_write(pipe_ctx, slave_address,
1761 buffer, sizeof(buffer));
1762 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
1763 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1764 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1767 ASSERT(i2c_success);
1772 static void write_i2c_default_retimer_setting(
1773 struct pipe_ctx *pipe_ctx,
1775 bool is_over_340mhz)
1777 uint8_t slave_address = (0xBA >> 1);
1779 bool i2c_success = false;
1780 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
1782 memset(&buffer, 0, sizeof(buffer));
1784 /* Program Slave Address for tuning single integrity */
1785 /* Write offset 0x0A to 0x13 */
1788 i2c_success = i2c_write(pipe_ctx, slave_address,
1789 buffer, sizeof(buffer));
1790 RETIMER_REDRIVER_INFO("retimer writes default setting to slave_address = 0x%x,\
1791 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1792 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1795 ASSERT(i2c_success);
1797 /* Write offset 0x0A to 0x17 */
1800 i2c_success = i2c_write(pipe_ctx, slave_address,
1801 buffer, sizeof(buffer));
1802 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
1803 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1804 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1807 ASSERT(i2c_success);
1809 /* Write offset 0x0B to 0xDA or 0xD8 */
1811 buffer[1] = is_over_340mhz ? 0xDA : 0xD8;
1812 i2c_success = i2c_write(pipe_ctx, slave_address,
1813 buffer, sizeof(buffer));
1814 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
1815 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1816 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1819 ASSERT(i2c_success);
1821 /* Write offset 0x0A to 0x17 */
1824 i2c_success = i2c_write(pipe_ctx, slave_address,
1825 buffer, sizeof(buffer));
1826 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
1827 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
1828 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1831 ASSERT(i2c_success);
1833 /* Write offset 0x0C to 0x1D or 0x91 */
1835 buffer[1] = is_over_340mhz ? 0x1D : 0x91;
1836 i2c_success = i2c_write(pipe_ctx, slave_address,
1837 buffer, sizeof(buffer));
1838 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
1839 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1840 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1843 ASSERT(i2c_success);
1845 /* Write offset 0x0A to 0x17 */
1848 i2c_success = i2c_write(pipe_ctx, slave_address,
1849 buffer, sizeof(buffer));
1850 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
1851 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1852 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1855 ASSERT(i2c_success);
1859 /* Program additional settings if using 640x480 resolution */
1861 /* Write offset 0xFF to 0x01 */
1864 i2c_success = i2c_write(pipe_ctx, slave_address,
1865 buffer, sizeof(buffer));
1866 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
1867 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1868 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1871 ASSERT(i2c_success);
1873 /* Write offset 0x00 to 0x23 */
1876 i2c_success = i2c_write(pipe_ctx, slave_address,
1877 buffer, sizeof(buffer));
1878 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
1879 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
1880 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1883 ASSERT(i2c_success);
1885 /* Write offset 0xff to 0x00 */
1888 i2c_success = i2c_write(pipe_ctx, slave_address,
1889 buffer, sizeof(buffer));
1890 RETIMER_REDRIVER_INFO("retimer write default setting to slave_addr = 0x%x,\
1891 offset = 0x%x, reg_val= 0x%x, i2c_success = %d end here\n",
1892 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1895 ASSERT(i2c_success);
1899 static void write_i2c_redriver_setting(
1900 struct pipe_ctx *pipe_ctx,
1901 bool is_over_340mhz)
1903 uint8_t slave_address = (0xF0 >> 1);
1905 bool i2c_success = false;
1906 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
1908 memset(&buffer, 0, sizeof(buffer));
1910 // Program Slave Address for tuning single integrity
1914 buffer[6] = is_over_340mhz ? 0x4E : 0x4A;
1916 i2c_success = i2c_write(pipe_ctx, slave_address,
1917 buffer, sizeof(buffer));
1918 RETIMER_REDRIVER_INFO("redriver write 0 to all 16 reg offset expect following:\n\
1919 \t slave_addr = 0x%x, offset[3] = 0x%x, offset[4] = 0x%x,\
1920 offset[5] = 0x%x,offset[6] is_over_340mhz = 0x%x,\
1921 i2c_success = %d\n",
1922 slave_address, buffer[3], buffer[4], buffer[5], buffer[6], i2c_success?1:0);
1926 ASSERT(i2c_success);
1929 static void enable_link_hdmi(struct pipe_ctx *pipe_ctx)
1931 struct dc_stream_state *stream = pipe_ctx->stream;
1932 struct dc_link *link = stream->sink->link;
1933 enum dc_color_depth display_color_depth;
1934 enum engine_id eng_id;
1935 struct ext_hdmi_settings settings = {0};
1936 bool is_over_340mhz = false;
1937 bool is_vga_mode = (stream->timing.h_addressable == 640)
1938 && (stream->timing.v_addressable == 480);
1940 if (stream->phy_pix_clk == 0)
1941 stream->phy_pix_clk = stream->timing.pix_clk_khz;
1942 if (stream->phy_pix_clk > 340000)
1943 is_over_340mhz = true;
1945 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {
1946 unsigned short masked_chip_caps = pipe_ctx->stream->sink->link->chip_caps &
1947 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK;
1948 if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) {
1949 /* DP159, Retimer settings */
1950 eng_id = pipe_ctx->stream_res.stream_enc->id;
1952 if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings)) {
1953 write_i2c_retimer_setting(pipe_ctx,
1954 is_vga_mode, is_over_340mhz, &settings);
1956 write_i2c_default_retimer_setting(pipe_ctx,
1957 is_vga_mode, is_over_340mhz);
1959 } else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) {
1960 /* PI3EQX1204, Redriver settings */
1961 write_i2c_redriver_setting(pipe_ctx, is_over_340mhz);
1965 if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
1966 dal_ddc_service_write_scdc_data(
1967 stream->sink->link->ddc,
1968 stream->phy_pix_clk,
1969 stream->timing.flags.LTE_340MCSC_SCRAMBLE);
1971 memset(&stream->sink->link->cur_link_settings, 0,
1972 sizeof(struct dc_link_settings));
1974 display_color_depth = stream->timing.display_color_depth;
1975 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
1976 display_color_depth = COLOR_DEPTH_888;
1978 link->link_enc->funcs->enable_tmds_output(
1980 pipe_ctx->clock_source->id,
1981 display_color_depth,
1982 pipe_ctx->stream->signal,
1983 stream->phy_pix_clk);
1985 if (pipe_ctx->stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
1986 dal_ddc_service_read_scdc_data(link->ddc);
1989 static void enable_link_lvds(struct pipe_ctx *pipe_ctx)
1991 struct dc_stream_state *stream = pipe_ctx->stream;
1992 struct dc_link *link = stream->sink->link;
1994 if (stream->phy_pix_clk == 0)
1995 stream->phy_pix_clk = stream->timing.pix_clk_khz;
1997 memset(&stream->sink->link->cur_link_settings, 0,
1998 sizeof(struct dc_link_settings));
2000 link->link_enc->funcs->enable_lvds_output(
2002 pipe_ctx->clock_source->id,
2003 stream->phy_pix_clk);
2007 /****************************enable_link***********************************/
2008 static enum dc_status enable_link(
2009 struct dc_state *state,
2010 struct pipe_ctx *pipe_ctx)
2012 enum dc_status status = DC_ERROR_UNEXPECTED;
2013 switch (pipe_ctx->stream->signal) {
2014 case SIGNAL_TYPE_DISPLAY_PORT:
2015 status = enable_link_dp(state, pipe_ctx);
2017 case SIGNAL_TYPE_EDP:
2018 status = enable_link_edp(state, pipe_ctx);
2020 case SIGNAL_TYPE_DISPLAY_PORT_MST:
2021 status = enable_link_dp_mst(state, pipe_ctx);
2024 case SIGNAL_TYPE_DVI_SINGLE_LINK:
2025 case SIGNAL_TYPE_DVI_DUAL_LINK:
2026 case SIGNAL_TYPE_HDMI_TYPE_A:
2027 enable_link_hdmi(pipe_ctx);
2030 case SIGNAL_TYPE_LVDS:
2031 enable_link_lvds(pipe_ctx);
2034 case SIGNAL_TYPE_VIRTUAL:
2044 static void disable_link(struct dc_link *link, enum signal_type signal)
2047 * TODO: implement call for dp_set_hw_test_pattern
2048 * it is needed for compliance testing
2051 /* here we need to specify that encoder output settings
2052 * need to be calculated as for the set mode,
2053 * it will lead to querying dynamic link capabilities
2054 * which should be done before enable output */
2056 if (dc_is_dp_signal(signal)) {
2058 if (dc_is_dp_sst_signal(signal))
2059 dp_disable_link_phy(link, signal);
2061 dp_disable_link_phy_mst(link, signal);
2063 link->link_enc->funcs->disable_output(link->link_enc, signal);
2066 static bool dp_active_dongle_validate_timing(
2067 const struct dc_crtc_timing *timing,
2068 const struct dpcd_caps *dpcd_caps)
2070 unsigned int required_pix_clk = timing->pix_clk_khz;
2071 const struct dc_dongle_caps *dongle_caps = &dpcd_caps->dongle_caps;
2073 switch (dpcd_caps->dongle_type) {
2074 case DISPLAY_DONGLE_DP_VGA_CONVERTER:
2075 case DISPLAY_DONGLE_DP_DVI_CONVERTER:
2076 case DISPLAY_DONGLE_DP_DVI_DONGLE:
2077 if (timing->pixel_encoding == PIXEL_ENCODING_RGB)
2085 if (dongle_caps->dongle_type != DISPLAY_DONGLE_DP_HDMI_CONVERTER ||
2086 dongle_caps->extendedCapValid == false)
2089 /* Check Pixel Encoding */
2090 switch (timing->pixel_encoding) {
2091 case PIXEL_ENCODING_RGB:
2092 case PIXEL_ENCODING_YCBCR444:
2094 case PIXEL_ENCODING_YCBCR422:
2095 if (!dongle_caps->is_dp_hdmi_ycbcr422_pass_through)
2098 case PIXEL_ENCODING_YCBCR420:
2099 if (!dongle_caps->is_dp_hdmi_ycbcr420_pass_through)
2103 /* Invalid Pixel Encoding*/
2108 /* Check Color Depth and Pixel Clock */
2109 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
2110 required_pix_clk /= 2;
2111 else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
2112 required_pix_clk = required_pix_clk * 2 / 3;
2114 switch (timing->display_color_depth) {
2115 case COLOR_DEPTH_666:
2116 case COLOR_DEPTH_888:
2117 /*888 and 666 should always be supported*/
2119 case COLOR_DEPTH_101010:
2120 if (dongle_caps->dp_hdmi_max_bpc < 10)
2122 required_pix_clk = required_pix_clk * 10 / 8;
2124 case COLOR_DEPTH_121212:
2125 if (dongle_caps->dp_hdmi_max_bpc < 12)
2127 required_pix_clk = required_pix_clk * 12 / 8;
2130 case COLOR_DEPTH_141414:
2131 case COLOR_DEPTH_161616:
2133 /* These color depths are currently not supported */
2137 if (required_pix_clk > dongle_caps->dp_hdmi_max_pixel_clk)
2143 enum dc_status dc_link_validate_mode_timing(
2144 const struct dc_stream_state *stream,
2145 struct dc_link *link,
2146 const struct dc_crtc_timing *timing)
2148 uint32_t max_pix_clk = stream->sink->dongle_max_pix_clk;
2149 struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
2151 /* A hack to avoid failing any modes for EDID override feature on
2152 * topology change such as lower quality cable for DP or different dongle
2154 if (link->remote_sinks[0])
2157 /* Passive Dongle */
2158 if (0 != max_pix_clk && timing->pix_clk_khz > max_pix_clk)
2159 return DC_EXCEED_DONGLE_CAP;
2162 if (!dp_active_dongle_validate_timing(timing, dpcd_caps))
2163 return DC_EXCEED_DONGLE_CAP;
2165 switch (stream->signal) {
2166 case SIGNAL_TYPE_EDP:
2167 case SIGNAL_TYPE_DISPLAY_PORT:
2168 if (!dp_validate_mode_timing(
2171 return DC_NO_DP_LINK_BANDWIDTH;
2181 int dc_link_get_backlight_level(const struct dc_link *link)
2183 struct abm *abm = link->ctx->dc->res_pool->abm;
2185 if (abm == NULL || abm->funcs->get_current_backlight == NULL)
2186 return DC_ERROR_UNEXPECTED;
2188 return (int) abm->funcs->get_current_backlight(abm);
2191 bool dc_link_set_backlight_level(const struct dc_link *link,
2192 uint32_t backlight_pwm_u16_16,
2193 uint32_t frame_ramp)
2195 struct dc *core_dc = link->ctx->dc;
2196 struct abm *abm = core_dc->res_pool->abm;
2197 struct dmcu *dmcu = core_dc->res_pool->dmcu;
2198 unsigned int controller_id = 0;
2199 bool use_smooth_brightness = true;
2201 DC_LOGGER_INIT(link->ctx->logger);
2203 if ((dmcu == NULL) ||
2205 (abm->funcs->set_backlight_level_pwm == NULL))
2208 use_smooth_brightness = dmcu->funcs->is_dmcu_initialized(dmcu);
2210 DC_LOG_BACKLIGHT("New Backlight level: %d (0x%X)\n",
2211 backlight_pwm_u16_16, backlight_pwm_u16_16);
2213 if (dc_is_embedded_signal(link->connector_signal)) {
2214 for (i = 0; i < MAX_PIPES; i++) {
2215 if (core_dc->current_state->res_ctx.pipe_ctx[i].stream) {
2216 if (core_dc->current_state->res_ctx.
2217 pipe_ctx[i].stream->sink->link
2219 /* DMCU -1 for all controller id values,
2223 core_dc->current_state->
2224 res_ctx.pipe_ctx[i].stream_res.tg->inst +
2228 abm->funcs->set_backlight_level_pwm(
2230 backlight_pwm_u16_16,
2233 use_smooth_brightness);
2239 bool dc_link_set_abm_disable(const struct dc_link *link)
2241 struct dc *core_dc = link->ctx->dc;
2242 struct abm *abm = core_dc->res_pool->abm;
2244 if ((abm == NULL) || (abm->funcs->set_backlight_level_pwm == NULL))
2247 abm->funcs->set_abm_immediate_disable(abm);
2252 bool dc_link_set_psr_enable(const struct dc_link *link, bool enable, bool wait)
2254 struct dc *core_dc = link->ctx->dc;
2255 struct dmcu *dmcu = core_dc->res_pool->dmcu;
2257 if ((dmcu != NULL && dmcu->funcs->is_dmcu_initialized(dmcu)) && link->psr_enabled)
2258 dmcu->funcs->set_psr_enable(dmcu, enable, wait);
2263 const struct dc_link_status *dc_link_get_status(const struct dc_link *link)
2265 return &link->link_status;
2268 void core_link_resume(struct dc_link *link)
2270 if (link->connector_signal != SIGNAL_TYPE_VIRTUAL)
2271 program_hpd_filter(link);
2274 static struct fixed31_32 get_pbn_per_slot(struct dc_stream_state *stream)
2276 struct dc_link_settings *link_settings =
2277 &stream->sink->link->cur_link_settings;
2278 uint32_t link_rate_in_mbps =
2279 link_settings->link_rate * LINK_RATE_REF_FREQ_IN_MHZ;
2280 struct fixed31_32 mbps = dc_fixpt_from_int(
2281 link_rate_in_mbps * link_settings->lane_count);
2283 return dc_fixpt_div_int(mbps, 54);
2286 static int get_color_depth(enum dc_color_depth color_depth)
2288 switch (color_depth) {
2289 case COLOR_DEPTH_666: return 6;
2290 case COLOR_DEPTH_888: return 8;
2291 case COLOR_DEPTH_101010: return 10;
2292 case COLOR_DEPTH_121212: return 12;
2293 case COLOR_DEPTH_141414: return 14;
2294 case COLOR_DEPTH_161616: return 16;
2299 static struct fixed31_32 get_pbn_from_timing(struct pipe_ctx *pipe_ctx)
2303 struct fixed31_32 peak_kbps;
2305 uint32_t denominator;
2307 bpc = get_color_depth(pipe_ctx->stream_res.pix_clk_params.color_depth);
2308 kbps = pipe_ctx->stream_res.pix_clk_params.requested_pix_clk * bpc * 3;
2311 * margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006
2312 * The unit of 54/64Mbytes/sec is an arbitrary unit chosen based on
2313 * common multiplier to render an integer PBN for all link rate/lane
2314 * counts combinations
2316 * peak_kbps *= (1006/1000)
2317 * peak_kbps *= (64/54)
2318 * peak_kbps *= 8 convert to bytes
2321 numerator = 64 * PEAK_FACTOR_X1000;
2322 denominator = 54 * 8 * 1000 * 1000;
2324 peak_kbps = dc_fixpt_from_fraction(kbps, denominator);
2329 static void update_mst_stream_alloc_table(
2330 struct dc_link *link,
2331 struct stream_encoder *stream_enc,
2332 const struct dp_mst_stream_allocation_table *proposed_table)
2334 struct link_mst_stream_allocation work_table[MAX_CONTROLLER_NUM] = {
2336 struct link_mst_stream_allocation *dc_alloc;
2341 /* if DRM proposed_table has more than one new payload */
2342 ASSERT(proposed_table->stream_count -
2343 link->mst_stream_alloc_table.stream_count < 2);
2345 /* copy proposed_table to link, add stream encoder */
2346 for (i = 0; i < proposed_table->stream_count; i++) {
2348 for (j = 0; j < link->mst_stream_alloc_table.stream_count; j++) {
2350 &link->mst_stream_alloc_table.stream_allocations[j];
2352 if (dc_alloc->vcp_id ==
2353 proposed_table->stream_allocations[i].vcp_id) {
2355 work_table[i] = *dc_alloc;
2356 break; /* exit j loop */
2361 if (j == link->mst_stream_alloc_table.stream_count) {
2362 work_table[i].vcp_id =
2363 proposed_table->stream_allocations[i].vcp_id;
2364 work_table[i].slot_count =
2365 proposed_table->stream_allocations[i].slot_count;
2366 work_table[i].stream_enc = stream_enc;
2370 /* update link->mst_stream_alloc_table with work_table */
2371 link->mst_stream_alloc_table.stream_count =
2372 proposed_table->stream_count;
2373 for (i = 0; i < MAX_CONTROLLER_NUM; i++)
2374 link->mst_stream_alloc_table.stream_allocations[i] =
2378 /* convert link_mst_stream_alloc_table to dm dp_mst_stream_alloc_table
2379 * because stream_encoder is not exposed to dm
2381 static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx)
2383 struct dc_stream_state *stream = pipe_ctx->stream;
2384 struct dc_link *link = stream->sink->link;
2385 struct link_encoder *link_encoder = link->link_enc;
2386 struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;
2387 struct dp_mst_stream_allocation_table proposed_table = {0};
2388 struct fixed31_32 avg_time_slots_per_mtp;
2389 struct fixed31_32 pbn;
2390 struct fixed31_32 pbn_per_slot;
2392 DC_LOGGER_INIT(link->ctx->logger);
2394 /* enable_link_dp_mst already check link->enabled_stream_count
2395 * and stream is in link->stream[]. This is called during set mode,
2396 * stream_enc is available.
2399 /* get calculate VC payload for stream: stream_alloc */
2400 if (dm_helpers_dp_mst_write_payload_allocation_table(
2405 update_mst_stream_alloc_table(
2406 link, pipe_ctx->stream_res.stream_enc, &proposed_table);
2409 DC_LOG_WARNING("Failed to update"
2410 "MST allocation table for"
2412 pipe_ctx->pipe_idx);
2415 "stream_count: %d: \n ",
2417 link->mst_stream_alloc_table.stream_count);
2419 for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
2420 DC_LOG_MST("stream_enc[%d]: %p "
2421 "stream[%d].vcp_id: %d "
2422 "stream[%d].slot_count: %d\n",
2424 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
2426 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
2428 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
2431 ASSERT(proposed_table.stream_count > 0);
2433 /* program DP source TX for payload */
2434 link_encoder->funcs->update_mst_stream_allocation_table(
2436 &link->mst_stream_alloc_table);
2438 /* send down message */
2439 dm_helpers_dp_mst_poll_for_allocation_change_trigger(
2443 dm_helpers_dp_mst_send_payload_allocation(
2448 /* slot X.Y for only current stream */
2449 pbn_per_slot = get_pbn_per_slot(stream);
2450 pbn = get_pbn_from_timing(pipe_ctx);
2451 avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot);
2453 stream_encoder->funcs->set_mst_bandwidth(
2455 avg_time_slots_per_mtp);
2461 static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx)
2463 struct dc_stream_state *stream = pipe_ctx->stream;
2464 struct dc_link *link = stream->sink->link;
2465 struct link_encoder *link_encoder = link->link_enc;
2466 struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;
2467 struct dp_mst_stream_allocation_table proposed_table = {0};
2468 struct fixed31_32 avg_time_slots_per_mtp = dc_fixpt_from_int(0);
2470 bool mst_mode = (link->type == dc_connection_mst_branch);
2471 DC_LOGGER_INIT(link->ctx->logger);
2473 /* deallocate_mst_payload is called before disable link. When mode or
2474 * disable/enable monitor, new stream is created which is not in link
2475 * stream[] yet. For this, payload is not allocated yet, so de-alloc
2476 * should not done. For new mode set, map_resources will get engine
2477 * for new stream, so stream_enc->id should be validated until here.
2481 stream_encoder->funcs->set_mst_bandwidth(
2483 avg_time_slots_per_mtp);
2485 /* TODO: which component is responsible for remove payload table? */
2487 if (dm_helpers_dp_mst_write_payload_allocation_table(
2493 update_mst_stream_alloc_table(
2494 link, pipe_ctx->stream_res.stream_enc, &proposed_table);
2497 DC_LOG_WARNING("Failed to update"
2498 "MST allocation table for"
2500 pipe_ctx->pipe_idx);
2505 "stream_count: %d: ",
2507 link->mst_stream_alloc_table.stream_count);
2509 for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
2510 DC_LOG_MST("stream_enc[%d]: %p "
2511 "stream[%d].vcp_id: %d "
2512 "stream[%d].slot_count: %d\n",
2514 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
2516 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
2518 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
2521 link_encoder->funcs->update_mst_stream_allocation_table(
2523 &link->mst_stream_alloc_table);
2526 dm_helpers_dp_mst_poll_for_allocation_change_trigger(
2530 dm_helpers_dp_mst_send_payload_allocation(
2539 void core_link_enable_stream(
2540 struct dc_state *state,
2541 struct pipe_ctx *pipe_ctx)
2543 struct dc *core_dc = pipe_ctx->stream->ctx->dc;
2544 struct dc_stream_state *stream = pipe_ctx->stream;
2545 enum dc_status status;
2546 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
2548 if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL) {
2549 stream->sink->link->link_enc->funcs->setup(
2550 stream->sink->link->link_enc,
2551 pipe_ctx->stream->signal);
2552 pipe_ctx->stream_res.stream_enc->funcs->setup_stereo_sync(
2553 pipe_ctx->stream_res.stream_enc,
2554 pipe_ctx->stream_res.tg->inst,
2555 stream->timing.timing_3d_format != TIMING_3D_FORMAT_NONE);
2558 if (dc_is_dp_signal(pipe_ctx->stream->signal))
2559 pipe_ctx->stream_res.stream_enc->funcs->dp_set_stream_attribute(
2560 pipe_ctx->stream_res.stream_enc,
2562 stream->output_color_space);
2564 if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
2565 pipe_ctx->stream_res.stream_enc->funcs->hdmi_set_stream_attribute(
2566 pipe_ctx->stream_res.stream_enc,
2568 stream->phy_pix_clk,
2569 pipe_ctx->stream_res.audio != NULL);
2571 if (dc_is_dvi_signal(pipe_ctx->stream->signal))
2572 pipe_ctx->stream_res.stream_enc->funcs->dvi_set_stream_attribute(
2573 pipe_ctx->stream_res.stream_enc,
2575 (pipe_ctx->stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK) ?
2578 if (dc_is_lvds_signal(pipe_ctx->stream->signal))
2579 pipe_ctx->stream_res.stream_enc->funcs->lvds_set_stream_attribute(
2580 pipe_ctx->stream_res.stream_enc,
2583 if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
2584 resource_build_info_frame(pipe_ctx);
2585 core_dc->hwss.update_info_frame(pipe_ctx);
2587 /* eDP lit up by bios already, no need to enable again. */
2588 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP &&
2589 pipe_ctx->stream->apply_edp_fast_boot_optimization) {
2590 pipe_ctx->stream->apply_edp_fast_boot_optimization = false;
2591 pipe_ctx->stream->dpms_off = false;
2595 if (pipe_ctx->stream->dpms_off)
2598 status = enable_link(state, pipe_ctx);
2600 if (status != DC_OK) {
2601 DC_LOG_WARNING("enabling link %u failed: %d\n",
2602 pipe_ctx->stream->sink->link->link_index,
2605 /* Abort stream enable *unless* the failure was due to
2606 * DP link training - some DP monitors will recover and
2607 * show the stream anyway. But MST displays can't proceed
2608 * without link training.
2610 if (status != DC_FAIL_DP_LINK_TRAINING ||
2611 pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
2612 BREAK_TO_DEBUGGER();
2617 core_dc->hwss.enable_audio_stream(pipe_ctx);
2619 /* turn off otg test pattern if enable */
2620 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
2621 pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
2622 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
2623 COLOR_DEPTH_UNDEFINED);
2625 core_dc->hwss.enable_stream(pipe_ctx);
2627 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
2628 allocate_mst_payload(pipe_ctx);
2630 core_dc->hwss.unblank_stream(pipe_ctx,
2631 &pipe_ctx->stream->sink->link->cur_link_settings);
2633 if (dc_is_dp_signal(pipe_ctx->stream->signal))
2634 enable_stream_features(pipe_ctx);
2639 void core_link_disable_stream(struct pipe_ctx *pipe_ctx, int option)
2641 struct dc *core_dc = pipe_ctx->stream->ctx->dc;
2643 core_dc->hwss.blank_stream(pipe_ctx);
2645 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
2646 deallocate_mst_payload(pipe_ctx);
2648 core_dc->hwss.disable_stream(pipe_ctx, option);
2650 disable_link(pipe_ctx->stream->sink->link, pipe_ctx->stream->signal);
2653 void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
2655 struct dc *core_dc = pipe_ctx->stream->ctx->dc;
2657 if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A)
2660 core_dc->hwss.set_avmute(pipe_ctx, enable);
2664 *****************************************************************************
2665 * Function: dc_link_enable_hpd_filter
2668 * If enable is true, programs HPD filter on associated HPD line using
2669 * delay_on_disconnect/delay_on_connect values dependent on
2670 * link->connector_signal
2672 * If enable is false, programs HPD filter on associated HPD line with no
2673 * delays on connect or disconnect
2675 * @param [in] link: pointer to the dc link
2676 * @param [in] enable: boolean specifying whether to enable hbd
2677 *****************************************************************************
2679 void dc_link_enable_hpd_filter(struct dc_link *link, bool enable)
2684 link->is_hpd_filter_disabled = false;
2685 program_hpd_filter(link);
2687 link->is_hpd_filter_disabled = true;
2688 /* Obtain HPD handle */
2689 hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
2694 /* Setup HPD filtering */
2695 if (dal_gpio_open(hpd, GPIO_MODE_INTERRUPT) == GPIO_RESULT_OK) {
2696 struct gpio_hpd_config config;
2698 config.delay_on_connect = 0;
2699 config.delay_on_disconnect = 0;
2701 dal_irq_setup_hpd_filter(hpd, &config);
2703 dal_gpio_close(hpd);
2705 ASSERT_CRITICAL(false);
2707 /* Release HPD handle */
2708 dal_gpio_destroy_irq(&hpd);