drivers/gpu/drm/amd/display/dc/core/dc_stream.c

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include <linux/delay.h>
  27 #include <linux/slab.h>
  28
  29 #include "dm_services.h"
  30 #include "basics/dc_common.h"
  31 #include "dc.h"
  32 #include "core_types.h"
  33 #include "resource.h"
  34 #include "ipp.h"
  35 #include "timing_generator.h"
  36
  37 #define DC_LOGGER dc->ctx->logger
  38
  39 /*******************************************************************************
  40  * Private functions
  41  ******************************************************************************/
  42 void update_stream_signal(struct dc_stream_state *stream, struct dc_sink *sink)
  43 {
  44         if (sink->sink_signal == SIGNAL_TYPE_NONE)
  45                 stream->signal = stream->link->connector_signal;
  46         else
  47                 stream->signal = sink->sink_signal;
  48
  49         if (dc_is_dvi_signal(stream->signal)) {
  50                 if (stream->ctx->dc->caps.dual_link_dvi &&
  51                         (stream->timing.pix_clk_100hz / 10) > TMDS_MAX_PIXEL_CLOCK &&
  52                         sink->sink_signal != SIGNAL_TYPE_DVI_SINGLE_LINK)
  53                         stream->signal = SIGNAL_TYPE_DVI_DUAL_LINK;
  54                 else
  55                         stream->signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
  56         }
  57 }
  58
  59 static void dc_stream_construct(struct dc_stream_state *stream,
  60         struct dc_sink *dc_sink_data)
  61 {
  62         uint32_t i = 0;
  63
  64         stream->sink = dc_sink_data;
  65         dc_sink_retain(dc_sink_data);
  66
  67         stream->ctx = dc_sink_data->ctx;
  68         stream->link = dc_sink_data->link;
  69         stream->sink_patches = dc_sink_data->edid_caps.panel_patch;
  70         stream->converter_disable_audio = dc_sink_data->converter_disable_audio;
  71         stream->qs_bit = dc_sink_data->edid_caps.qs_bit;
  72         stream->qy_bit = dc_sink_data->edid_caps.qy_bit;
  73
  74         /* Copy audio modes */
  75         /* TODO - Remove this translation */
  76         for (i = 0; i < (dc_sink_data->edid_caps.audio_mode_count); i++)
  77         {
  78                 stream->audio_info.modes[i].channel_count = dc_sink_data->edid_caps.audio_modes[i].channel_count;
  79                 stream->audio_info.modes[i].format_code = dc_sink_data->edid_caps.audio_modes[i].format_code;
  80                 stream->audio_info.modes[i].sample_rates.all = dc_sink_data->edid_caps.audio_modes[i].sample_rate;
  81                 stream->audio_info.modes[i].sample_size = dc_sink_data->edid_caps.audio_modes[i].sample_size;
  82         }
  83         stream->audio_info.mode_count = dc_sink_data->edid_caps.audio_mode_count;
  84         stream->audio_info.audio_latency = dc_sink_data->edid_caps.audio_latency;
  85         stream->audio_info.video_latency = dc_sink_data->edid_caps.video_latency;
  86         memmove(
  87                 stream->audio_info.display_name,
  88                 dc_sink_data->edid_caps.display_name,
  89                 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS);
  90         stream->audio_info.manufacture_id = dc_sink_data->edid_caps.manufacturer_id;
  91         stream->audio_info.product_id = dc_sink_data->edid_caps.product_id;
  92         stream->audio_info.flags.all = dc_sink_data->edid_caps.speaker_flags;
  93
  94         if (dc_sink_data->dc_container_id != NULL) {
  95                 struct dc_container_id *dc_container_id = dc_sink_data->dc_container_id;
  96
  97                 stream->audio_info.port_id[0] = dc_container_id->portId[0];
  98                 stream->audio_info.port_id[1] = dc_container_id->portId[1];
  99         } else {
 100                 /* TODO - WindowDM has implemented,
 101                 other DMs need Unhardcode port_id */
 102                 stream->audio_info.port_id[0] = 0x5558859e;
 103                 stream->audio_info.port_id[1] = 0xd989449;
 104         }
 105
 106         /* EDID CAP translation for HDMI 2.0 */
 107         stream->timing.flags.LTE_340MCSC_SCRAMBLE = dc_sink_data->edid_caps.lte_340mcsc_scramble;
 108
 109         memset(&stream->timing.dsc_cfg, 0, sizeof(stream->timing.dsc_cfg));
 110         stream->timing.dsc_cfg.num_slices_h = 0;
 111         stream->timing.dsc_cfg.num_slices_v = 0;
 112         stream->timing.dsc_cfg.bits_per_pixel = 128;
 113         stream->timing.dsc_cfg.block_pred_enable = 1;
 114         stream->timing.dsc_cfg.linebuf_depth = 9;
 115         stream->timing.dsc_cfg.version_minor = 2;
 116         stream->timing.dsc_cfg.ycbcr422_simple = 0;
 117
 118         update_stream_signal(stream, dc_sink_data);
 119
 120         stream->out_transfer_func = dc_create_transfer_func();
 121         stream->out_transfer_func->type = TF_TYPE_BYPASS;
 122         stream->out_transfer_func->ctx = stream->ctx;
 123
 124         stream->stream_id = stream->ctx->dc_stream_id_count;
 125         stream->ctx->dc_stream_id_count++;
 126 }
 127
 128 static void dc_stream_destruct(struct dc_stream_state *stream)
 129 {
 130         dc_sink_release(stream->sink);
 131         if (stream->out_transfer_func != NULL) {
 132                 dc_transfer_func_release(stream->out_transfer_func);
 133                 stream->out_transfer_func = NULL;
 134         }
 135 }
 136
 137 void dc_stream_retain(struct dc_stream_state *stream)
 138 {
 139         kref_get(&stream->refcount);
 140 }
 141
 142 static void dc_stream_free(struct kref *kref)
 143 {
 144         struct dc_stream_state *stream = container_of(kref, struct dc_stream_state, refcount);
 145
 146         dc_stream_destruct(stream);
 147         kfree(stream);
 148 }
 149
 150 void dc_stream_release(struct dc_stream_state *stream)
 151 {
 152         if (stream != NULL) {
 153                 kref_put(&stream->refcount, dc_stream_free);
 154         }
 155 }
 156
 157 struct dc_stream_state *dc_create_stream_for_sink(
 158                 struct dc_sink *sink)
 159 {
 160         struct dc_stream_state *stream;
 161
 162         if (sink == NULL)
 163                 return NULL;
 164
 165         stream = kzalloc(sizeof(struct dc_stream_state), GFP_KERNEL);
 166         if (stream == NULL)
 167                 return NULL;
 168
 169         dc_stream_construct(stream, sink);
 170
 171         kref_init(&stream->refcount);
 172
 173         return stream;
 174 }
 175
 176 struct dc_stream_state *dc_copy_stream(const struct dc_stream_state *stream)
 177 {
 178         struct dc_stream_state *new_stream;
 179
 180         new_stream = kmemdup(stream, sizeof(struct dc_stream_state), GFP_KERNEL);
 181         if (!new_stream)
 182                 return NULL;
 183
 184         if (new_stream->sink)
 185                 dc_sink_retain(new_stream->sink);
 186
 187         if (new_stream->out_transfer_func)
 188                 dc_transfer_func_retain(new_stream->out_transfer_func);
 189
 190         new_stream->stream_id = new_stream->ctx->dc_stream_id_count;
 191         new_stream->ctx->dc_stream_id_count++;
 192
 193         kref_init(&new_stream->refcount);
 194
 195         return new_stream;
 196 }
 197
 198 /**
 199  * dc_stream_get_status_from_state - Get stream status from given dc state
 200  * @state: DC state to find the stream status in
 201  * @stream: The stream to get the stream status for
 202  *
 203  * The given stream is expected to exist in the given dc state. Otherwise, NULL
 204  * will be returned.
 205  */
 206 struct dc_stream_status *dc_stream_get_status_from_state(
 207         struct dc_state *state,
 208         struct dc_stream_state *stream)
 209 {
 210         uint8_t i;
 211
 212         for (i = 0; i < state->stream_count; i++) {
 213                 if (stream == state->streams[i])
 214                         return &state->stream_status[i];
 215         }
 216
 217         return NULL;
 218 }
 219
 220 /**
 221  * dc_stream_get_status() - Get current stream status of the given stream state
 222  * @stream: The stream to get the stream status for.
 223  *
 224  * The given stream is expected to exist in dc->current_state. Otherwise, NULL
 225  * will be returned.
 226  */
 227 struct dc_stream_status *dc_stream_get_status(
 228         struct dc_stream_state *stream)
 229 {
 230         struct dc *dc = stream->ctx->dc;
 231         return dc_stream_get_status_from_state(dc->current_state, stream);
 232 }
 233
 234 static void delay_cursor_until_vupdate(struct pipe_ctx *pipe_ctx, struct dc *dc)
 235 {
 236 #if defined(CONFIG_DRM_AMD_DC_DCN)
 237         unsigned int vupdate_line;
 238         unsigned int lines_to_vupdate, us_to_vupdate, vpos, nvpos;
 239         struct dc_stream_state *stream = pipe_ctx->stream;
 240         unsigned int us_per_line;
 241
 242         if (stream->ctx->asic_id.chip_family == FAMILY_RV &&
 243                         ASICREV_IS_RAVEN(stream->ctx->asic_id.hw_internal_rev)) {
 244
 245                 vupdate_line = dc->hwss.get_vupdate_offset_from_vsync(pipe_ctx);
 246                 if (!dc_stream_get_crtc_position(dc, &stream, 1, &vpos, &nvpos))
 247                         return;
 248
 249                 if (vpos >= vupdate_line)
 250                         return;
 251
 252                 us_per_line = stream->timing.h_total * 10000 / stream->timing.pix_clk_100hz;
 253                 lines_to_vupdate = vupdate_line - vpos;
 254                 us_to_vupdate = lines_to_vupdate * us_per_line;
 255
 256                 /* 70 us is a conservative estimate of cursor update time*/
 257                 if (us_to_vupdate < 70)
 258                         udelay(us_to_vupdate);
 259         }
 260 #endif
 261 }
 262
 263 /**
 264  * dc_stream_set_cursor_attributes() - Update cursor attributes and set cursor surface address
 265  */
 266 bool dc_stream_set_cursor_attributes(
 267         struct dc_stream_state *stream,
 268         const struct dc_cursor_attributes *attributes)
 269 {
 270         int i;
 271         struct dc  *dc;
 272         struct resource_context *res_ctx;
 273         struct pipe_ctx *pipe_to_program = NULL;
 274
 275         if (NULL == stream) {
 276                 dm_error("DC: dc_stream is NULL!\n");
 277                 return false;
 278         }
 279         if (NULL == attributes) {
 280                 dm_error("DC: attributes is NULL!\n");
 281                 return false;
 282         }
 283
 284         if (attributes->address.quad_part == 0) {
 285                 dm_output_to_console("DC: Cursor address is 0!\n");
 286                 return false;
 287         }
 288
 289         dc = stream->ctx->dc;
 290         res_ctx = &dc->current_state->res_ctx;
 291         stream->cursor_attributes = *attributes;
 292
 293         for (i = 0; i < MAX_PIPES; i++) {
 294                 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
 295
 296                 if (pipe_ctx->stream != stream)
 297                         continue;
 298
 299                 if (!pipe_to_program) {
 300                         pipe_to_program = pipe_ctx;
 301
 302                         delay_cursor_until_vupdate(pipe_ctx, dc);
 303                         dc->hwss.pipe_control_lock(dc, pipe_to_program, true);
 304                 }
 305
 306                 dc->hwss.set_cursor_attribute(pipe_ctx);
 307                 if (dc->hwss.set_cursor_sdr_white_level)
 308                         dc->hwss.set_cursor_sdr_white_level(pipe_ctx);
 309         }
 310
 311         if (pipe_to_program)
 312                 dc->hwss.pipe_control_lock(dc, pipe_to_program, false);
 313
 314         return true;
 315 }
 316
 317 bool dc_stream_set_cursor_position(
 318         struct dc_stream_state *stream,
 319         const struct dc_cursor_position *position)
 320 {
 321         int i;
 322         struct dc  *dc;
 323         struct resource_context *res_ctx;
 324         struct pipe_ctx *pipe_to_program = NULL;
 325
 326         if (NULL == stream) {
 327                 dm_error("DC: dc_stream is NULL!\n");
 328                 return false;
 329         }
 330
 331         if (NULL == position) {
 332                 dm_error("DC: cursor position is NULL!\n");
 333                 return false;
 334         }
 335
 336         dc = stream->ctx->dc;
 337         res_ctx = &dc->current_state->res_ctx;
 338         stream->cursor_position = *position;
 339
 340         for (i = 0; i < MAX_PIPES; i++) {
 341                 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
 342
 343                 if (pipe_ctx->stream != stream ||
 344                                 (!pipe_ctx->plane_res.mi  && !pipe_ctx->plane_res.hubp) ||
 345                                 !pipe_ctx->plane_state ||
 346                                 (!pipe_ctx->plane_res.xfm && !pipe_ctx->plane_res.dpp) ||
 347                                 (!pipe_ctx->plane_res.ipp && !pipe_ctx->plane_res.dpp))
 348                         continue;
 349
 350                 if (!pipe_to_program) {
 351                         pipe_to_program = pipe_ctx;
 352
 353                         delay_cursor_until_vupdate(pipe_ctx, dc);
 354                         dc->hwss.pipe_control_lock(dc, pipe_to_program, true);
 355                 }
 356
 357                 dc->hwss.set_cursor_position(pipe_ctx);
 358         }
 359
 360         if (pipe_to_program)
 361                 dc->hwss.pipe_control_lock(dc, pipe_to_program, false);
 362
 363         return true;
 364 }
 365
 366 bool dc_stream_add_writeback(struct dc *dc,
 367                 struct dc_stream_state *stream,
 368                 struct dc_writeback_info *wb_info)
 369 {
 370         bool isDrc = false;
 371         int i = 0;
 372         struct dwbc *dwb;
 373
 374         if (stream == NULL) {
 375                 dm_error("DC: dc_stream is NULL!\n");
 376                 return false;
 377         }
 378
 379         if (wb_info == NULL) {
 380                 dm_error("DC: dc_writeback_info is NULL!\n");
 381                 return false;
 382         }
 383
 384         if (wb_info->dwb_pipe_inst >= MAX_DWB_PIPES) {
 385                 dm_error("DC: writeback pipe is invalid!\n");
 386                 return false;
 387         }
 388
 389         wb_info->dwb_params.out_transfer_func = stream->out_transfer_func;
 390
 391         dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
 392         dwb->dwb_is_drc = false;
 393
 394         /* recalculate and apply DML parameters */
 395
 396         for (i = 0; i < stream->num_wb_info; i++) {
 397                 /*dynamic update*/
 398                 if (stream->writeback_info[i].wb_enabled &&
 399                         stream->writeback_info[i].dwb_pipe_inst == wb_info->dwb_pipe_inst) {
 400                         stream->writeback_info[i] = *wb_info;
 401                         isDrc = true;
 402                 }
 403         }
 404
 405         if (!isDrc) {
 406                 stream->writeback_info[stream->num_wb_info++] = *wb_info;
 407         }
 408
 409         if (dc->hwss.enable_writeback) {
 410                 struct dc_stream_status *stream_status = dc_stream_get_status(stream);
 411                 struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
 412                 dwb->otg_inst = stream_status->primary_otg_inst;
 413         }
 414         if (IS_DIAG_DC(dc->ctx->dce_environment)) {
 415                 if (!dc->hwss.update_bandwidth(dc, dc->current_state)) {
 416                         dm_error("DC: update_bandwidth failed!\n");
 417                         return false;
 418                 }
 419
 420                 /* enable writeback */
 421                 if (dc->hwss.enable_writeback) {
 422                         struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
 423
 424                         if (dwb->funcs->is_enabled(dwb)) {
 425                                 /* writeback pipe already enabled, only need to update */
 426                                 dc->hwss.update_writeback(dc, wb_info, dc->current_state);
 427                         } else {
 428                                 /* Enable writeback pipe from scratch*/
 429                                 dc->hwss.enable_writeback(dc, wb_info, dc->current_state);
 430                         }
 431                 }
 432         }
 433         return true;
 434 }
 435
 436 bool dc_stream_remove_writeback(struct dc *dc,
 437                 struct dc_stream_state *stream,
 438                 uint32_t dwb_pipe_inst)
 439 {
 440         int i = 0, j = 0;
 441         if (stream == NULL) {
 442                 dm_error("DC: dc_stream is NULL!\n");
 443                 return false;
 444         }
 445
 446         if (dwb_pipe_inst >= MAX_DWB_PIPES) {
 447                 dm_error("DC: writeback pipe is invalid!\n");
 448                 return false;
 449         }
 450
 451 //      stream->writeback_info[dwb_pipe_inst].wb_enabled = false;
 452         for (i = 0; i < stream->num_wb_info; i++) {
 453                 /*dynamic update*/
 454                 if (stream->writeback_info[i].wb_enabled &&
 455                         stream->writeback_info[i].dwb_pipe_inst == dwb_pipe_inst) {
 456                         stream->writeback_info[i].wb_enabled = false;
 457                 }
 458         }
 459
 460         /* remove writeback info for disabled writeback pipes from stream */
 461         for (i = 0, j = 0; i < stream->num_wb_info; i++) {
 462                 if (stream->writeback_info[i].wb_enabled) {
 463                         if (i != j)
 464                                 /* trim the array */
 465                                 stream->writeback_info[j] = stream->writeback_info[i];
 466                         j++;
 467                 }
 468         }
 469         stream->num_wb_info = j;
 470
 471         if (IS_DIAG_DC(dc->ctx->dce_environment)) {
 472                 /* recalculate and apply DML parameters */
 473                 if (!dc->hwss.update_bandwidth(dc, dc->current_state)) {
 474                         dm_error("DC: update_bandwidth failed!\n");
 475                         return false;
 476                 }
 477
 478                 /* disable writeback */
 479                 if (dc->hwss.disable_writeback)
 480                         dc->hwss.disable_writeback(dc, dwb_pipe_inst);
 481         }
 482         return true;
 483 }
 484
 485 bool dc_stream_warmup_writeback(struct dc *dc,
 486                 int num_dwb,
 487                 struct dc_writeback_info *wb_info)
 488 {
 489         if (dc->hwss.mmhubbub_warmup)
 490                 return dc->hwss.mmhubbub_warmup(dc, num_dwb, wb_info);
 491         else
 492                 return false;
 493 }
 494 uint32_t dc_stream_get_vblank_counter(const struct dc_stream_state *stream)
 495 {
 496         uint8_t i;
 497         struct dc  *dc = stream->ctx->dc;
 498         struct resource_context *res_ctx =
 499                 &dc->current_state->res_ctx;
 500
 501         for (i = 0; i < MAX_PIPES; i++) {
 502                 struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg;
 503
 504                 if (res_ctx->pipe_ctx[i].stream != stream)
 505                         continue;
 506
 507                 return tg->funcs->get_frame_count(tg);
 508         }
 509
 510         return 0;
 511 }
 512
 513 bool dc_stream_send_dp_sdp(const struct dc_stream_state *stream,
 514                 const uint8_t *custom_sdp_message,
 515                 unsigned int sdp_message_size)
 516 {
 517         int i;
 518         struct dc  *dc;
 519         struct resource_context *res_ctx;
 520
 521         if (stream == NULL) {
 522                 dm_error("DC: dc_stream is NULL!\n");
 523                 return false;
 524         }
 525
 526         dc = stream->ctx->dc;
 527         res_ctx = &dc->current_state->res_ctx;
 528
 529         for (i = 0; i < MAX_PIPES; i++) {
 530                 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
 531
 532                 if (pipe_ctx->stream != stream)
 533                         continue;
 534
 535                 if (dc->hwss.send_immediate_sdp_message != NULL)
 536                         dc->hwss.send_immediate_sdp_message(pipe_ctx,
 537                                                                 custom_sdp_message,
 538                                                                 sdp_message_size);
 539                 else
 540                         DC_LOG_WARNING("%s:send_immediate_sdp_message not implemented on this ASIC\n",
 541                         __func__);
 542
 543         }
 544
 545         return true;
 546 }
 547
 548 bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream,
 549                                   uint32_t *v_blank_start,
 550                                   uint32_t *v_blank_end,
 551                                   uint32_t *h_position,
 552                                   uint32_t *v_position)
 553 {
 554         uint8_t i;
 555         bool ret = false;
 556         struct dc  *dc = stream->ctx->dc;
 557         struct resource_context *res_ctx =
 558                 &dc->current_state->res_ctx;
 559
 560         for (i = 0; i < MAX_PIPES; i++) {
 561                 struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg;
 562
 563                 if (res_ctx->pipe_ctx[i].stream != stream)
 564                         continue;
 565
 566                 tg->funcs->get_scanoutpos(tg,
 567                                           v_blank_start,
 568                                           v_blank_end,
 569                                           h_position,
 570                                           v_position);
 571
 572                 ret = true;
 573                 break;
 574         }
 575
 576         return ret;
 577 }
 578
 579 bool dc_stream_dmdata_status_done(struct dc *dc, struct dc_stream_state *stream)
 580 {
 581         struct pipe_ctx *pipe = NULL;
 582         int i;
 583
 584         if (!dc->hwss.dmdata_status_done)
 585                 return false;
 586
 587         for (i = 0; i < MAX_PIPES; i++) {
 588                 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 589                 if (pipe->stream == stream)
 590                         break;
 591         }
 592         /* Stream not found, by default we'll assume HUBP fetched dm data */
 593         if (i == MAX_PIPES)
 594                 return true;
 595
 596         return dc->hwss.dmdata_status_done(pipe);
 597 }
 598
 599 bool dc_stream_set_dynamic_metadata(struct dc *dc,
 600                 struct dc_stream_state *stream,
 601                 struct dc_dmdata_attributes *attr)
 602 {
 603         struct pipe_ctx *pipe_ctx = NULL;
 604         struct hubp *hubp;
 605         int i;
 606
 607         /* Dynamic metadata is only supported on HDMI or DP */
 608         if (!dc_is_hdmi_signal(stream->signal) && !dc_is_dp_signal(stream->signal))
 609                 return false;
 610
 611         /* Check hardware support */
 612         if (!dc->hwss.program_dmdata_engine)
 613                 return false;
 614
 615         for (i = 0; i < MAX_PIPES; i++) {
 616                 pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
 617                 if (pipe_ctx->stream == stream)
 618                         break;
 619         }
 620
 621         if (i == MAX_PIPES)
 622                 return false;
 623
 624         hubp = pipe_ctx->plane_res.hubp;
 625         if (hubp == NULL)
 626                 return false;
 627
 628         pipe_ctx->stream->dmdata_address = attr->address;
 629
 630         dc->hwss.program_dmdata_engine(pipe_ctx);
 631
 632         if (hubp->funcs->dmdata_set_attributes != NULL &&
 633                         pipe_ctx->stream->dmdata_address.quad_part != 0) {
 634                 hubp->funcs->dmdata_set_attributes(hubp, attr);
 635         }
 636
 637         return true;
 638 }
 639
 640 void dc_stream_log(const struct dc *dc, const struct dc_stream_state *stream)
 641 {
 642         DC_LOG_DC(
 643                         "core_stream 0x%p: src: %d, %d, %d, %d; dst: %d, %d, %d, %d, colorSpace:%d\n",
 644                         stream,
 645                         stream->src.x,
 646                         stream->src.y,
 647                         stream->src.width,
 648                         stream->src.height,
 649                         stream->dst.x,
 650                         stream->dst.y,
 651                         stream->dst.width,
 652                         stream->dst.height,
 653                         stream->output_color_space);
 654         DC_LOG_DC(
 655                         "\tpix_clk_khz: %d, h_total: %d, v_total: %d, pixelencoder:%d, displaycolorDepth:%d\n",
 656                         stream->timing.pix_clk_100hz / 10,
 657                         stream->timing.h_total,
 658                         stream->timing.v_total,
 659                         stream->timing.pixel_encoding,
 660                         stream->timing.display_color_depth);
 661         DC_LOG_DC(
 662                         "\tlink: %d\n",
 663                         stream->link->link_index);
 664 }