2 * Copyright 2016 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include "dm_services.h"
27 #include "core_types.h"
29 #include "custom_float.h"
30 #include "dcn10_hw_sequencer.h"
31 #include "dce110/dce110_hw_sequencer.h"
32 #include "dce/dce_hwseq.h"
35 #include "dcn10_optc.h"
36 #include "dcn10/dcn10_dpp.h"
37 #include "dcn10/dcn10_mpc.h"
38 #include "timing_generator.h"
42 #include "reg_helper.h"
43 #include "custom_float.h"
44 #include "dcn10_hubp.h"
45 #include "dcn10_hubbub.h"
46 #include "dcn10_cm_common.h"
47 #include "dc_link_dp.h"
50 #define DC_LOGGER_INIT(logger)
58 #define FN(reg_name, field_name) \
59 hws->shifts->field_name, hws->masks->field_name
61 /*print is 17 wide, first two characters are spaces*/
62 #define DTN_INFO_MICRO_SEC(ref_cycle) \
63 print_microsec(dc_ctx, log_ctx, ref_cycle)
65 void print_microsec(struct dc_context *dc_ctx,
66 struct dc_log_buffer_ctx *log_ctx,
69 const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clock_inKhz / 1000;
70 static const unsigned int frac = 1000;
71 uint32_t us_x10 = (ref_cycle * frac) / ref_clk_mhz;
73 DTN_INFO(" %11d.%03d",
78 static void log_mpc_crc(struct dc *dc,
79 struct dc_log_buffer_ctx *log_ctx)
81 struct dc_context *dc_ctx = dc->ctx;
82 struct dce_hwseq *hws = dc->hwseq;
84 if (REG(MPC_CRC_RESULT_GB))
85 DTN_INFO("MPC_CRC_RESULT_GB:%d MPC_CRC_RESULT_C:%d MPC_CRC_RESULT_AR:%d\n",
86 REG_READ(MPC_CRC_RESULT_GB), REG_READ(MPC_CRC_RESULT_C), REG_READ(MPC_CRC_RESULT_AR));
87 if (REG(DPP_TOP0_DPP_CRC_VAL_B_A))
88 DTN_INFO("DPP_TOP0_DPP_CRC_VAL_B_A:%d DPP_TOP0_DPP_CRC_VAL_R_G:%d\n",
89 REG_READ(DPP_TOP0_DPP_CRC_VAL_B_A), REG_READ(DPP_TOP0_DPP_CRC_VAL_R_G));
92 void dcn10_log_hubbub_state(struct dc *dc, struct dc_log_buffer_ctx *log_ctx)
94 struct dc_context *dc_ctx = dc->ctx;
95 struct dcn_hubbub_wm wm = {0};
98 hubbub1_wm_read_state(dc->res_pool->hubbub, &wm);
100 DTN_INFO("HUBBUB WM: data_urgent pte_meta_urgent"
101 " sr_enter sr_exit dram_clk_change\n");
103 for (i = 0; i < 4; i++) {
104 struct dcn_hubbub_wm_set *s;
107 DTN_INFO("WM_Set[%d]:", s->wm_set);
108 DTN_INFO_MICRO_SEC(s->data_urgent);
109 DTN_INFO_MICRO_SEC(s->pte_meta_urgent);
110 DTN_INFO_MICRO_SEC(s->sr_enter);
111 DTN_INFO_MICRO_SEC(s->sr_exit);
112 DTN_INFO_MICRO_SEC(s->dram_clk_chanage);
119 static void dcn10_log_hubp_states(struct dc *dc, void *log_ctx)
121 struct dc_context *dc_ctx = dc->ctx;
122 struct resource_pool *pool = dc->res_pool;
125 DTN_INFO("HUBP: format addr_hi width height"
126 " rot mir sw_mode dcc_en blank_en ttu_dis underflow"
127 " min_ttu_vblank qos_low_wm qos_high_wm\n");
128 for (i = 0; i < pool->pipe_count; i++) {
129 struct hubp *hubp = pool->hubps[i];
130 struct dcn_hubp_state *s = &(TO_DCN10_HUBP(hubp)->state);
132 hubp->funcs->hubp_read_state(hubp);
135 DTN_INFO("[%2d]: %5xh %6xh %5d %6d %2xh %2xh %6xh"
148 s->underflow_status);
149 DTN_INFO_MICRO_SEC(s->min_ttu_vblank);
150 DTN_INFO_MICRO_SEC(s->qos_level_low_wm);
151 DTN_INFO_MICRO_SEC(s->qos_level_high_wm);
156 DTN_INFO("\n=========RQ========\n");
157 DTN_INFO("HUBP: drq_exp_m prq_exp_m mrq_exp_m crq_exp_m plane1_ba L:chunk_s min_chu_s meta_ch_s"
158 " min_m_c_s dpte_gr_s mpte_gr_s swath_hei pte_row_h C:chunk_s min_chu_s meta_ch_s"
159 " min_m_c_s dpte_gr_s mpte_gr_s swath_hei pte_row_h\n");
160 for (i = 0; i < pool->pipe_count; i++) {
161 struct dcn_hubp_state *s = &(TO_DCN10_HUBP(pool->hubps[i])->state);
162 struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs;
165 DTN_INFO("[%2d]: %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh\n",
166 pool->hubps[i]->inst, rq_regs->drq_expansion_mode, rq_regs->prq_expansion_mode, rq_regs->mrq_expansion_mode,
167 rq_regs->crq_expansion_mode, rq_regs->plane1_base_address, rq_regs->rq_regs_l.chunk_size,
168 rq_regs->rq_regs_l.min_chunk_size, rq_regs->rq_regs_l.meta_chunk_size,
169 rq_regs->rq_regs_l.min_meta_chunk_size, rq_regs->rq_regs_l.dpte_group_size,
170 rq_regs->rq_regs_l.mpte_group_size, rq_regs->rq_regs_l.swath_height,
171 rq_regs->rq_regs_l.pte_row_height_linear, rq_regs->rq_regs_c.chunk_size, rq_regs->rq_regs_c.min_chunk_size,
172 rq_regs->rq_regs_c.meta_chunk_size, rq_regs->rq_regs_c.min_meta_chunk_size,
173 rq_regs->rq_regs_c.dpte_group_size, rq_regs->rq_regs_c.mpte_group_size,
174 rq_regs->rq_regs_c.swath_height, rq_regs->rq_regs_c.pte_row_height_linear);
177 DTN_INFO("========DLG========\n");
178 DTN_INFO("HUBP: rc_hbe dlg_vbe min_d_y_n rc_per_ht rc_x_a_s "
179 " dst_y_a_s dst_y_pf dst_y_vvb dst_y_rvb dst_y_vfl dst_y_rfl rf_pix_fq"
180 " vratio_pf vrat_pf_c rc_pg_vbl rc_pg_vbc rc_mc_vbl rc_mc_vbc rc_pg_fll"
181 " rc_pg_flc rc_mc_fll rc_mc_flc pr_nom_l pr_nom_c rc_pg_nl rc_pg_nc "
182 " mr_nom_l mr_nom_c rc_mc_nl rc_mc_nc rc_ld_pl rc_ld_pc rc_ld_l "
183 " rc_ld_c cha_cur0 ofst_cur1 cha_cur1 vr_af_vc0 ddrq_limt x_rt_dlay"
184 " x_rp_dlay x_rr_sfl\n");
185 for (i = 0; i < pool->pipe_count; i++) {
186 struct dcn_hubp_state *s = &(TO_DCN10_HUBP(pool->hubps[i])->state);
187 struct _vcs_dpi_display_dlg_regs_st *dlg_regs = &s->dlg_attr;
190 DTN_INFO("[%2d]: %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh"
191 "% 8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh"
192 " %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh\n",
193 pool->hubps[i]->inst, dlg_regs->refcyc_h_blank_end, dlg_regs->dlg_vblank_end, dlg_regs->min_dst_y_next_start,
194 dlg_regs->refcyc_per_htotal, dlg_regs->refcyc_x_after_scaler, dlg_regs->dst_y_after_scaler,
195 dlg_regs->dst_y_prefetch, dlg_regs->dst_y_per_vm_vblank, dlg_regs->dst_y_per_row_vblank,
196 dlg_regs->dst_y_per_vm_flip, dlg_regs->dst_y_per_row_flip, dlg_regs->ref_freq_to_pix_freq,
197 dlg_regs->vratio_prefetch, dlg_regs->vratio_prefetch_c, dlg_regs->refcyc_per_pte_group_vblank_l,
198 dlg_regs->refcyc_per_pte_group_vblank_c, dlg_regs->refcyc_per_meta_chunk_vblank_l,
199 dlg_regs->refcyc_per_meta_chunk_vblank_c, dlg_regs->refcyc_per_pte_group_flip_l,
200 dlg_regs->refcyc_per_pte_group_flip_c, dlg_regs->refcyc_per_meta_chunk_flip_l,
201 dlg_regs->refcyc_per_meta_chunk_flip_c, dlg_regs->dst_y_per_pte_row_nom_l,
202 dlg_regs->dst_y_per_pte_row_nom_c, dlg_regs->refcyc_per_pte_group_nom_l,
203 dlg_regs->refcyc_per_pte_group_nom_c, dlg_regs->dst_y_per_meta_row_nom_l,
204 dlg_regs->dst_y_per_meta_row_nom_c, dlg_regs->refcyc_per_meta_chunk_nom_l,
205 dlg_regs->refcyc_per_meta_chunk_nom_c, dlg_regs->refcyc_per_line_delivery_pre_l,
206 dlg_regs->refcyc_per_line_delivery_pre_c, dlg_regs->refcyc_per_line_delivery_l,
207 dlg_regs->refcyc_per_line_delivery_c, dlg_regs->chunk_hdl_adjust_cur0, dlg_regs->dst_y_offset_cur1,
208 dlg_regs->chunk_hdl_adjust_cur1, dlg_regs->vready_after_vcount0, dlg_regs->dst_y_delta_drq_limit,
209 dlg_regs->xfc_reg_transfer_delay, dlg_regs->xfc_reg_precharge_delay,
210 dlg_regs->xfc_reg_remote_surface_flip_latency);
213 DTN_INFO("========TTU========\n");
214 DTN_INFO("HUBP: qos_ll_wm qos_lh_wm mn_ttu_vb qos_l_flp rc_rd_p_l rc_rd_l rc_rd_p_c"
215 " rc_rd_c rc_rd_c0 rc_rd_pc0 rc_rd_c1 rc_rd_pc1 qos_lf_l qos_rds_l"
216 " qos_lf_c qos_rds_c qos_lf_c0 qos_rds_c0 qos_lf_c1 qos_rds_c1\n");
217 for (i = 0; i < pool->pipe_count; i++) {
218 struct dcn_hubp_state *s = &(TO_DCN10_HUBP(pool->hubps[i])->state);
219 struct _vcs_dpi_display_ttu_regs_st *ttu_regs = &s->ttu_attr;
222 DTN_INFO("[%2d]: %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh\n",
223 pool->hubps[i]->inst, ttu_regs->qos_level_low_wm, ttu_regs->qos_level_high_wm, ttu_regs->min_ttu_vblank,
224 ttu_regs->qos_level_flip, ttu_regs->refcyc_per_req_delivery_pre_l, ttu_regs->refcyc_per_req_delivery_l,
225 ttu_regs->refcyc_per_req_delivery_pre_c, ttu_regs->refcyc_per_req_delivery_c, ttu_regs->refcyc_per_req_delivery_cur0,
226 ttu_regs->refcyc_per_req_delivery_pre_cur0, ttu_regs->refcyc_per_req_delivery_cur1,
227 ttu_regs->refcyc_per_req_delivery_pre_cur1, ttu_regs->qos_level_fixed_l, ttu_regs->qos_ramp_disable_l,
228 ttu_regs->qos_level_fixed_c, ttu_regs->qos_ramp_disable_c, ttu_regs->qos_level_fixed_cur0,
229 ttu_regs->qos_ramp_disable_cur0, ttu_regs->qos_level_fixed_cur1, ttu_regs->qos_ramp_disable_cur1);
234 void dcn10_log_hw_state(struct dc *dc,
235 struct dc_log_buffer_ctx *log_ctx)
237 struct dc_context *dc_ctx = dc->ctx;
238 struct resource_pool *pool = dc->res_pool;
243 dcn10_log_hubbub_state(dc, log_ctx);
245 dcn10_log_hubp_states(dc, log_ctx);
247 DTN_INFO("DPP: IGAM format IGAM mode DGAM mode RGAM mode"
248 " GAMUT mode C11 C12 C13 C14 C21 C22 C23 C24 "
249 "C31 C32 C33 C34\n");
250 for (i = 0; i < pool->pipe_count; i++) {
251 struct dpp *dpp = pool->dpps[i];
252 struct dcn_dpp_state s = {0};
254 dpp->funcs->dpp_read_state(dpp, &s);
259 DTN_INFO("[%2d]: %11xh %-11s %-11s %-11s"
260 "%8x %08xh %08xh %08xh %08xh %08xh %08xh",
263 (s.igam_lut_mode == 0) ? "BypassFixed" :
264 ((s.igam_lut_mode == 1) ? "BypassFloat" :
265 ((s.igam_lut_mode == 2) ? "RAM" :
266 ((s.igam_lut_mode == 3) ? "RAM" :
268 (s.dgam_lut_mode == 0) ? "Bypass" :
269 ((s.dgam_lut_mode == 1) ? "sRGB" :
270 ((s.dgam_lut_mode == 2) ? "Ycc" :
271 ((s.dgam_lut_mode == 3) ? "RAM" :
272 ((s.dgam_lut_mode == 4) ? "RAM" :
274 (s.rgam_lut_mode == 0) ? "Bypass" :
275 ((s.rgam_lut_mode == 1) ? "sRGB" :
276 ((s.rgam_lut_mode == 2) ? "Ycc" :
277 ((s.rgam_lut_mode == 3) ? "RAM" :
278 ((s.rgam_lut_mode == 4) ? "RAM" :
281 s.gamut_remap_c11_c12,
282 s.gamut_remap_c13_c14,
283 s.gamut_remap_c21_c22,
284 s.gamut_remap_c23_c24,
285 s.gamut_remap_c31_c32,
286 s.gamut_remap_c33_c34);
291 DTN_INFO("MPCC: OPP DPP MPCCBOT MODE ALPHA_MODE PREMULT OVERLAP_ONLY IDLE\n");
292 for (i = 0; i < pool->pipe_count; i++) {
293 struct mpcc_state s = {0};
295 pool->mpc->funcs->read_mpcc_state(pool->mpc, i, &s);
297 DTN_INFO("[%2d]: %2xh %2xh %6xh %4d %10d %7d %12d %4d\n",
298 i, s.opp_id, s.dpp_id, s.bot_mpcc_id,
299 s.mode, s.alpha_mode, s.pre_multiplied_alpha, s.overlap_only,
304 DTN_INFO("OTG: v_bs v_be v_ss v_se vpol vmax vmin vmax_sel vmin_sel"
305 " h_bs h_be h_ss h_se hpol htot vtot underflow\n");
307 for (i = 0; i < pool->timing_generator_count; i++) {
308 struct timing_generator *tg = pool->timing_generators[i];
309 struct dcn_otg_state s = {0};
311 optc1_read_otg_state(DCN10TG_FROM_TG(tg), &s);
313 //only print if OTG master is enabled
314 if ((s.otg_enabled & 1) == 0)
317 DTN_INFO("[%d]: %5d %5d %5d %5d %5d %5d %5d %9d %9d %5d %5d %5d"
318 " %5d %5d %5d %5d %9d\n",
336 s.underflow_occurred_status);
338 // Clear underflow for debug purposes
339 // We want to keep underflow sticky bit on for the longevity tests outside of test environment.
340 // This function is called only from Windows or Diags test environment, hence it's safe to clear
341 // it from here without affecting the original intent.
342 tg->funcs->clear_optc_underflow(tg);
346 DTN_INFO("\nCALCULATED Clocks: dcfclk_khz:%d dcfclk_deep_sleep_khz:%d dispclk_khz:%d\n"
347 "dppclk_khz:%d max_supported_dppclk_khz:%d fclk_khz:%d socclk_khz:%d\n\n",
348 dc->current_state->bw.dcn.clk.dcfclk_khz,
349 dc->current_state->bw.dcn.clk.dcfclk_deep_sleep_khz,
350 dc->current_state->bw.dcn.clk.dispclk_khz,
351 dc->current_state->bw.dcn.clk.dppclk_khz,
352 dc->current_state->bw.dcn.clk.max_supported_dppclk_khz,
353 dc->current_state->bw.dcn.clk.fclk_khz,
354 dc->current_state->bw.dcn.clk.socclk_khz);
356 log_mpc_crc(dc, log_ctx);
361 static void enable_power_gating_plane(
362 struct dce_hwseq *hws,
365 bool force_on = 1; /* disable power gating */
371 REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, force_on);
372 REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, force_on);
373 REG_UPDATE(DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, force_on);
374 REG_UPDATE(DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, force_on);
377 REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, force_on);
378 REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, force_on);
379 REG_UPDATE(DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, force_on);
380 REG_UPDATE(DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, force_on);
383 static void disable_vga(
384 struct dce_hwseq *hws)
386 unsigned int in_vga1_mode = 0;
387 unsigned int in_vga2_mode = 0;
388 unsigned int in_vga3_mode = 0;
389 unsigned int in_vga4_mode = 0;
391 REG_GET(D1VGA_CONTROL, D1VGA_MODE_ENABLE, &in_vga1_mode);
392 REG_GET(D2VGA_CONTROL, D2VGA_MODE_ENABLE, &in_vga2_mode);
393 REG_GET(D3VGA_CONTROL, D3VGA_MODE_ENABLE, &in_vga3_mode);
394 REG_GET(D4VGA_CONTROL, D4VGA_MODE_ENABLE, &in_vga4_mode);
396 if (in_vga1_mode == 0 && in_vga2_mode == 0 &&
397 in_vga3_mode == 0 && in_vga4_mode == 0)
400 REG_WRITE(D1VGA_CONTROL, 0);
401 REG_WRITE(D2VGA_CONTROL, 0);
402 REG_WRITE(D3VGA_CONTROL, 0);
403 REG_WRITE(D4VGA_CONTROL, 0);
405 /* HW Engineer's Notes:
406 * During switch from vga->extended, if we set the VGA_TEST_ENABLE and
407 * then hit the VGA_TEST_RENDER_START, then the DCHUBP timing gets updated correctly.
409 * Then vBIOS will have it poll for the VGA_TEST_RENDER_DONE and unset
410 * VGA_TEST_ENABLE, to leave it in the same state as before.
412 REG_UPDATE(VGA_TEST_CONTROL, VGA_TEST_ENABLE, 1);
413 REG_UPDATE(VGA_TEST_CONTROL, VGA_TEST_RENDER_START, 1);
416 static void dpp_pg_control(
417 struct dce_hwseq *hws,
418 unsigned int dpp_inst,
421 uint32_t power_gate = power_on ? 0 : 1;
422 uint32_t pwr_status = power_on ? 0 : 2;
424 if (hws->ctx->dc->debug.disable_dpp_power_gate)
426 if (REG(DOMAIN1_PG_CONFIG) == 0)
431 REG_UPDATE(DOMAIN1_PG_CONFIG,
432 DOMAIN1_POWER_GATE, power_gate);
434 REG_WAIT(DOMAIN1_PG_STATUS,
435 DOMAIN1_PGFSM_PWR_STATUS, pwr_status,
439 REG_UPDATE(DOMAIN3_PG_CONFIG,
440 DOMAIN3_POWER_GATE, power_gate);
442 REG_WAIT(DOMAIN3_PG_STATUS,
443 DOMAIN3_PGFSM_PWR_STATUS, pwr_status,
447 REG_UPDATE(DOMAIN5_PG_CONFIG,
448 DOMAIN5_POWER_GATE, power_gate);
450 REG_WAIT(DOMAIN5_PG_STATUS,
451 DOMAIN5_PGFSM_PWR_STATUS, pwr_status,
455 REG_UPDATE(DOMAIN7_PG_CONFIG,
456 DOMAIN7_POWER_GATE, power_gate);
458 REG_WAIT(DOMAIN7_PG_STATUS,
459 DOMAIN7_PGFSM_PWR_STATUS, pwr_status,
468 static void hubp_pg_control(
469 struct dce_hwseq *hws,
470 unsigned int hubp_inst,
473 uint32_t power_gate = power_on ? 0 : 1;
474 uint32_t pwr_status = power_on ? 0 : 2;
476 if (hws->ctx->dc->debug.disable_hubp_power_gate)
478 if (REG(DOMAIN0_PG_CONFIG) == 0)
482 case 0: /* DCHUBP0 */
483 REG_UPDATE(DOMAIN0_PG_CONFIG,
484 DOMAIN0_POWER_GATE, power_gate);
486 REG_WAIT(DOMAIN0_PG_STATUS,
487 DOMAIN0_PGFSM_PWR_STATUS, pwr_status,
490 case 1: /* DCHUBP1 */
491 REG_UPDATE(DOMAIN2_PG_CONFIG,
492 DOMAIN2_POWER_GATE, power_gate);
494 REG_WAIT(DOMAIN2_PG_STATUS,
495 DOMAIN2_PGFSM_PWR_STATUS, pwr_status,
498 case 2: /* DCHUBP2 */
499 REG_UPDATE(DOMAIN4_PG_CONFIG,
500 DOMAIN4_POWER_GATE, power_gate);
502 REG_WAIT(DOMAIN4_PG_STATUS,
503 DOMAIN4_PGFSM_PWR_STATUS, pwr_status,
506 case 3: /* DCHUBP3 */
507 REG_UPDATE(DOMAIN6_PG_CONFIG,
508 DOMAIN6_POWER_GATE, power_gate);
510 REG_WAIT(DOMAIN6_PG_STATUS,
511 DOMAIN6_PGFSM_PWR_STATUS, pwr_status,
520 static void power_on_plane(
521 struct dce_hwseq *hws,
524 DC_LOGGER_INIT(hws->ctx->logger);
525 if (REG(DC_IP_REQUEST_CNTL)) {
526 REG_SET(DC_IP_REQUEST_CNTL, 0,
528 dpp_pg_control(hws, plane_id, true);
529 hubp_pg_control(hws, plane_id, true);
530 REG_SET(DC_IP_REQUEST_CNTL, 0,
533 "Un-gated front end for pipe %d\n", plane_id);
537 static void undo_DEGVIDCN10_253_wa(struct dc *dc)
539 struct dce_hwseq *hws = dc->hwseq;
540 struct hubp *hubp = dc->res_pool->hubps[0];
542 if (!hws->wa_state.DEGVIDCN10_253_applied)
545 hubp->funcs->set_blank(hubp, true);
547 REG_SET(DC_IP_REQUEST_CNTL, 0,
550 hubp_pg_control(hws, 0, false);
551 REG_SET(DC_IP_REQUEST_CNTL, 0,
554 hws->wa_state.DEGVIDCN10_253_applied = false;
557 static void apply_DEGVIDCN10_253_wa(struct dc *dc)
559 struct dce_hwseq *hws = dc->hwseq;
560 struct hubp *hubp = dc->res_pool->hubps[0];
563 if (dc->debug.disable_stutter)
566 if (!hws->wa.DEGVIDCN10_253)
569 for (i = 0; i < dc->res_pool->pipe_count; i++) {
570 if (!dc->res_pool->hubps[i]->power_gated)
574 /* all pipe power gated, apply work around to enable stutter. */
576 REG_SET(DC_IP_REQUEST_CNTL, 0,
579 hubp_pg_control(hws, 0, true);
580 REG_SET(DC_IP_REQUEST_CNTL, 0,
583 hubp->funcs->set_hubp_blank_en(hubp, false);
584 hws->wa_state.DEGVIDCN10_253_applied = true;
587 static void bios_golden_init(struct dc *dc)
589 struct dc_bios *bp = dc->ctx->dc_bios;
592 /* initialize dcn global */
593 bp->funcs->enable_disp_power_gating(bp,
594 CONTROLLER_ID_D0, ASIC_PIPE_INIT);
596 for (i = 0; i < dc->res_pool->pipe_count; i++) {
597 /* initialize dcn per pipe */
598 bp->funcs->enable_disp_power_gating(bp,
599 CONTROLLER_ID_D0 + i, ASIC_PIPE_DISABLE);
603 static void false_optc_underflow_wa(
605 const struct dc_stream_state *stream,
606 struct timing_generator *tg)
611 if (!dc->hwseq->wa.false_optc_underflow)
614 underflow = tg->funcs->is_optc_underflow_occurred(tg);
616 for (i = 0; i < dc->res_pool->pipe_count; i++) {
617 struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
619 if (old_pipe_ctx->stream != stream)
622 dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, old_pipe_ctx);
625 tg->funcs->set_blank_data_double_buffer(tg, true);
627 if (tg->funcs->is_optc_underflow_occurred(tg) && !underflow)
628 tg->funcs->clear_optc_underflow(tg);
631 static enum dc_status dcn10_enable_stream_timing(
632 struct pipe_ctx *pipe_ctx,
633 struct dc_state *context,
636 struct dc_stream_state *stream = pipe_ctx->stream;
637 enum dc_color_space color_space;
638 struct tg_color black_color = {0};
639 struct drr_params params = {0};
640 unsigned int event_triggers = 0;
642 /* by upper caller loop, pipe0 is parent pipe and be called first.
643 * back end is set up by for pipe0. Other children pipe share back end
644 * with pipe 0. No program is needed.
646 if (pipe_ctx->top_pipe != NULL)
649 /* TODO check if timing_changed, disable stream if timing changed */
651 /* HW program guide assume display already disable
652 * by unplug sequence. OTG assume stop.
654 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true);
656 if (false == pipe_ctx->clock_source->funcs->program_pix_clk(
657 pipe_ctx->clock_source,
658 &pipe_ctx->stream_res.pix_clk_params,
659 &pipe_ctx->pll_settings)) {
661 return DC_ERROR_UNEXPECTED;
663 pipe_ctx->stream_res.tg->dlg_otg_param.vready_offset = pipe_ctx->pipe_dlg_param.vready_offset;
664 pipe_ctx->stream_res.tg->dlg_otg_param.vstartup_start = pipe_ctx->pipe_dlg_param.vstartup_start;
665 pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_offset = pipe_ctx->pipe_dlg_param.vupdate_offset;
666 pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_width = pipe_ctx->pipe_dlg_param.vupdate_width;
668 pipe_ctx->stream_res.tg->dlg_otg_param.signal = pipe_ctx->stream->signal;
670 pipe_ctx->stream_res.tg->funcs->program_timing(
671 pipe_ctx->stream_res.tg,
675 #if 0 /* move to after enable_crtc */
676 /* TODO: OPP FMT, ABM. etc. should be done here. */
677 /* or FPGA now. instance 0 only. TODO: move to opp.c */
679 inst_offset = reg_offsets[pipe_ctx->stream_res.tg->inst].fmt;
681 pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
682 pipe_ctx->stream_res.opp,
683 &stream->bit_depth_params,
686 /* program otg blank color */
687 color_space = stream->output_color_space;
688 color_space_to_black_color(dc, color_space, &black_color);
690 if (pipe_ctx->stream_res.tg->funcs->set_blank_color)
691 pipe_ctx->stream_res.tg->funcs->set_blank_color(
692 pipe_ctx->stream_res.tg,
695 if (pipe_ctx->stream_res.tg->funcs->is_blanked &&
696 !pipe_ctx->stream_res.tg->funcs->is_blanked(pipe_ctx->stream_res.tg)) {
697 pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true);
698 hwss_wait_for_blank_complete(pipe_ctx->stream_res.tg);
699 false_optc_underflow_wa(dc, pipe_ctx->stream, pipe_ctx->stream_res.tg);
702 /* VTG is within DCHUB command block. DCFCLK is always on */
703 if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(pipe_ctx->stream_res.tg)) {
705 return DC_ERROR_UNEXPECTED;
708 params.vertical_total_min = stream->adjust.v_total_min;
709 params.vertical_total_max = stream->adjust.v_total_max;
710 if (pipe_ctx->stream_res.tg->funcs->set_drr)
711 pipe_ctx->stream_res.tg->funcs->set_drr(
712 pipe_ctx->stream_res.tg, ¶ms);
714 // DRR should set trigger event to monitor surface update event
715 if (stream->adjust.v_total_min != 0 && stream->adjust.v_total_max != 0)
716 event_triggers = 0x80;
717 if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control)
718 pipe_ctx->stream_res.tg->funcs->set_static_screen_control(
719 pipe_ctx->stream_res.tg, event_triggers);
721 /* TODO program crtc source select for non-virtual signal*/
722 /* TODO program FMT */
723 /* TODO setup link_enc */
724 /* TODO set stream attributes */
725 /* TODO program audio */
726 /* TODO enable stream if timing changed */
727 /* TODO unblank stream if DP */
732 static void reset_back_end_for_pipe(
734 struct pipe_ctx *pipe_ctx,
735 struct dc_state *context)
738 DC_LOGGER_INIT(dc->ctx->logger);
739 if (pipe_ctx->stream_res.stream_enc == NULL) {
740 pipe_ctx->stream = NULL;
744 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
745 /* DPMS may already disable */
746 if (!pipe_ctx->stream->dpms_off)
747 core_link_disable_stream(pipe_ctx, FREE_ACQUIRED_RESOURCE);
748 else if (pipe_ctx->stream_res.audio) {
749 dc->hwss.disable_audio_stream(pipe_ctx, FREE_ACQUIRED_RESOURCE);
754 /* by upper caller loop, parent pipe: pipe0, will be reset last.
755 * back end share by all pipes and will be disable only when disable
758 if (pipe_ctx->top_pipe == NULL) {
759 pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg);
761 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false);
764 for (i = 0; i < dc->res_pool->pipe_count; i++)
765 if (&dc->current_state->res_ctx.pipe_ctx[i] == pipe_ctx)
768 if (i == dc->res_pool->pipe_count)
771 pipe_ctx->stream = NULL;
772 DC_LOG_DEBUG("Reset back end for pipe %d, tg:%d\n",
773 pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst);
776 static bool dcn10_hw_wa_force_recovery(struct dc *dc)
780 bool need_recover = true;
782 if (!dc->debug.recovery_enabled)
785 for (i = 0; i < dc->res_pool->pipe_count; i++) {
786 struct pipe_ctx *pipe_ctx =
787 &dc->current_state->res_ctx.pipe_ctx[i];
788 if (pipe_ctx != NULL) {
789 hubp = pipe_ctx->plane_res.hubp;
790 if (hubp != NULL && hubp->funcs->hubp_get_underflow_status) {
791 if (hubp->funcs->hubp_get_underflow_status(hubp) != 0) {
792 /* one pipe underflow, we will reset all the pipes*/
801 DCHUBP_CNTL:HUBP_BLANK_EN=1
802 DCHUBBUB_SOFT_RESET:DCHUBBUB_GLOBAL_SOFT_RESET=1
803 DCHUBP_CNTL:HUBP_DISABLE=1
804 DCHUBP_CNTL:HUBP_DISABLE=0
805 DCHUBBUB_SOFT_RESET:DCHUBBUB_GLOBAL_SOFT_RESET=0
806 DCSURF_PRIMARY_SURFACE_ADDRESS
807 DCHUBP_CNTL:HUBP_BLANK_EN=0
810 for (i = 0; i < dc->res_pool->pipe_count; i++) {
811 struct pipe_ctx *pipe_ctx =
812 &dc->current_state->res_ctx.pipe_ctx[i];
813 if (pipe_ctx != NULL) {
814 hubp = pipe_ctx->plane_res.hubp;
815 /*DCHUBP_CNTL:HUBP_BLANK_EN=1*/
816 if (hubp != NULL && hubp->funcs->set_hubp_blank_en)
817 hubp->funcs->set_hubp_blank_en(hubp, true);
820 /*DCHUBBUB_SOFT_RESET:DCHUBBUB_GLOBAL_SOFT_RESET=1*/
821 hubbub1_soft_reset(dc->res_pool->hubbub, true);
823 for (i = 0; i < dc->res_pool->pipe_count; i++) {
824 struct pipe_ctx *pipe_ctx =
825 &dc->current_state->res_ctx.pipe_ctx[i];
826 if (pipe_ctx != NULL) {
827 hubp = pipe_ctx->plane_res.hubp;
828 /*DCHUBP_CNTL:HUBP_DISABLE=1*/
829 if (hubp != NULL && hubp->funcs->hubp_disable_control)
830 hubp->funcs->hubp_disable_control(hubp, true);
833 for (i = 0; i < dc->res_pool->pipe_count; i++) {
834 struct pipe_ctx *pipe_ctx =
835 &dc->current_state->res_ctx.pipe_ctx[i];
836 if (pipe_ctx != NULL) {
837 hubp = pipe_ctx->plane_res.hubp;
838 /*DCHUBP_CNTL:HUBP_DISABLE=0*/
839 if (hubp != NULL && hubp->funcs->hubp_disable_control)
840 hubp->funcs->hubp_disable_control(hubp, true);
843 /*DCHUBBUB_SOFT_RESET:DCHUBBUB_GLOBAL_SOFT_RESET=0*/
844 hubbub1_soft_reset(dc->res_pool->hubbub, false);
845 for (i = 0; i < dc->res_pool->pipe_count; i++) {
846 struct pipe_ctx *pipe_ctx =
847 &dc->current_state->res_ctx.pipe_ctx[i];
848 if (pipe_ctx != NULL) {
849 hubp = pipe_ctx->plane_res.hubp;
850 /*DCHUBP_CNTL:HUBP_BLANK_EN=0*/
851 if (hubp != NULL && hubp->funcs->set_hubp_blank_en)
852 hubp->funcs->set_hubp_blank_en(hubp, true);
860 void dcn10_verify_allow_pstate_change_high(struct dc *dc)
862 static bool should_log_hw_state; /* prevent hw state log by default */
864 if (!hubbub1_verify_allow_pstate_change_high(dc->res_pool->hubbub)) {
865 if (should_log_hw_state) {
866 dcn10_log_hw_state(dc, NULL);
869 if (dcn10_hw_wa_force_recovery(dc)) {
871 if (!hubbub1_verify_allow_pstate_change_high(dc->res_pool->hubbub))
877 /* trigger HW to start disconnect plane from stream on the next vsync */
878 void hwss1_plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx)
880 struct hubp *hubp = pipe_ctx->plane_res.hubp;
881 int dpp_id = pipe_ctx->plane_res.dpp->inst;
882 struct mpc *mpc = dc->res_pool->mpc;
883 struct mpc_tree *mpc_tree_params;
884 struct mpcc *mpcc_to_remove = NULL;
885 struct output_pixel_processor *opp = pipe_ctx->stream_res.opp;
887 mpc_tree_params = &(opp->mpc_tree_params);
888 mpcc_to_remove = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, dpp_id);
891 if (mpcc_to_remove == NULL)
894 mpc->funcs->remove_mpcc(mpc, mpc_tree_params, mpcc_to_remove);
896 opp->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
898 dc->optimized_required = true;
900 if (hubp->funcs->hubp_disconnect)
901 hubp->funcs->hubp_disconnect(hubp);
903 if (dc->debug.sanity_checks)
904 dcn10_verify_allow_pstate_change_high(dc);
907 static void plane_atomic_power_down(struct dc *dc, struct pipe_ctx *pipe_ctx)
909 struct dce_hwseq *hws = dc->hwseq;
910 struct dpp *dpp = pipe_ctx->plane_res.dpp;
911 DC_LOGGER_INIT(dc->ctx->logger);
913 if (REG(DC_IP_REQUEST_CNTL)) {
914 REG_SET(DC_IP_REQUEST_CNTL, 0,
916 dpp_pg_control(hws, dpp->inst, false);
917 hubp_pg_control(hws, pipe_ctx->plane_res.hubp->inst, false);
918 dpp->funcs->dpp_reset(dpp);
919 REG_SET(DC_IP_REQUEST_CNTL, 0,
922 "Power gated front end %d\n", pipe_ctx->pipe_idx);
926 /* disable HW used by plane.
927 * note: cannot disable until disconnect is complete
929 static void plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
931 struct hubp *hubp = pipe_ctx->plane_res.hubp;
932 struct dpp *dpp = pipe_ctx->plane_res.dpp;
933 int opp_id = hubp->opp_id;
935 dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx);
937 hubp->funcs->hubp_clk_cntl(hubp, false);
939 dpp->funcs->dpp_dppclk_control(dpp, false, false);
941 if (opp_id != 0xf && pipe_ctx->stream_res.opp->mpc_tree_params.opp_list == NULL)
942 pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(
943 pipe_ctx->stream_res.opp,
946 hubp->power_gated = true;
947 dc->optimized_required = false; /* We're powering off, no need to optimize */
949 plane_atomic_power_down(dc, pipe_ctx);
951 pipe_ctx->stream = NULL;
952 memset(&pipe_ctx->stream_res, 0, sizeof(pipe_ctx->stream_res));
953 memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res));
954 pipe_ctx->top_pipe = NULL;
955 pipe_ctx->bottom_pipe = NULL;
956 pipe_ctx->plane_state = NULL;
959 static void dcn10_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx)
961 DC_LOGGER_INIT(dc->ctx->logger);
963 if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated)
966 plane_atomic_disable(dc, pipe_ctx);
968 apply_DEGVIDCN10_253_wa(dc);
970 DC_LOG_DC("Power down front end %d\n",
974 static void dcn10_init_hw(struct dc *dc)
977 struct abm *abm = dc->res_pool->abm;
978 struct dmcu *dmcu = dc->res_pool->dmcu;
979 struct dce_hwseq *hws = dc->hwseq;
980 struct dc_bios *dcb = dc->ctx->dc_bios;
981 struct dc_state *context = dc->current_state;
983 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
984 REG_WRITE(REFCLK_CNTL, 0);
985 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
986 REG_WRITE(DIO_MEM_PWR_CTRL, 0);
988 if (!dc->debug.disable_clock_gate) {
989 /* enable all DCN clock gating */
990 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
992 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
994 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
997 enable_power_gating_plane(dc->hwseq, true);
1000 if (!dcb->funcs->is_accelerated_mode(dcb)) {
1001 bool allow_self_fresh_force_enable =
1002 hububu1_is_allow_self_refresh_enabled(dc->res_pool->hubbub);
1004 bios_golden_init(dc);
1006 /* WA for making DF sleep when idle after resume from S0i3.
1007 * DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE is set to 1 by
1008 * command table, if DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE = 0
1009 * before calling command table and it changed to 1 after,
1010 * it should be set back to 0.
1012 if (allow_self_fresh_force_enable == false &&
1013 hububu1_is_allow_self_refresh_enabled(dc->res_pool->hubbub))
1014 hubbub1_disable_allow_self_refresh(dc->res_pool->hubbub);
1016 disable_vga(dc->hwseq);
1019 for (i = 0; i < dc->link_count; i++) {
1020 /* Power up AND update implementation according to the
1021 * required signal (which may be different from the
1022 * default signal on connector).
1024 struct dc_link *link = dc->links[i];
1026 if (link->link_enc->connector.id == CONNECTOR_ID_EDP)
1027 dc->hwss.edp_power_control(link, true);
1029 link->link_enc->funcs->hw_init(link->link_enc);
1033 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1034 struct timing_generator *tg = dc->res_pool->timing_generators[i];
1036 if (tg->funcs->is_tg_enabled(tg))
1037 tg->funcs->lock(tg);
1040 /* Blank controller using driver code instead of
1043 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1044 struct timing_generator *tg = dc->res_pool->timing_generators[i];
1046 if (tg->funcs->is_tg_enabled(tg)) {
1047 tg->funcs->set_blank(tg, true);
1048 hwss_wait_for_blank_complete(tg);
1052 /* Reset all MPCC muxes */
1053 dc->res_pool->mpc->funcs->mpc_init(dc->res_pool->mpc);
1055 for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
1056 struct timing_generator *tg = dc->res_pool->timing_generators[i];
1057 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1058 struct hubp *hubp = dc->res_pool->hubps[i];
1059 struct dpp *dpp = dc->res_pool->dpps[i];
1061 pipe_ctx->stream_res.tg = tg;
1062 pipe_ctx->pipe_idx = i;
1064 pipe_ctx->plane_res.hubp = hubp;
1065 pipe_ctx->plane_res.dpp = dpp;
1066 pipe_ctx->plane_res.mpcc_inst = dpp->inst;
1067 hubp->mpcc_id = dpp->inst;
1069 hubp->power_gated = false;
1071 dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst;
1072 dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL;
1073 dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
1074 pipe_ctx->stream_res.opp = dc->res_pool->opps[i];
1076 hwss1_plane_atomic_disconnect(dc, pipe_ctx);
1079 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1080 struct timing_generator *tg = dc->res_pool->timing_generators[i];
1082 if (tg->funcs->is_tg_enabled(tg))
1083 tg->funcs->unlock(tg);
1086 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1087 struct timing_generator *tg = dc->res_pool->timing_generators[i];
1088 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1090 dcn10_disable_plane(dc, pipe_ctx);
1092 pipe_ctx->stream_res.tg = NULL;
1093 pipe_ctx->plane_res.hubp = NULL;
1095 tg->funcs->tg_init(tg);
1098 /* end of FPGA. Below if real ASIC */
1099 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
1102 for (i = 0; i < dc->res_pool->audio_count; i++) {
1103 struct audio *audio = dc->res_pool->audios[i];
1105 audio->funcs->hw_init(audio);
1109 abm->funcs->init_backlight(abm);
1110 abm->funcs->abm_init(abm);
1114 dmcu->funcs->dmcu_init(dmcu);
1116 /* power AFMT HDMI memory TODO: may move to dis/en output save power*/
1117 REG_WRITE(DIO_MEM_PWR_CTRL, 0);
1119 if (!dc->debug.disable_clock_gate) {
1120 /* enable all DCN clock gating */
1121 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
1123 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
1125 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
1128 enable_power_gating_plane(dc->hwseq, true);
1130 memset(&dc->res_pool->clk_mgr->clks, 0, sizeof(dc->res_pool->clk_mgr->clks));
1133 static void reset_hw_ctx_wrap(
1135 struct dc_state *context)
1140 for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {
1141 struct pipe_ctx *pipe_ctx_old =
1142 &dc->current_state->res_ctx.pipe_ctx[i];
1143 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1145 if (!pipe_ctx_old->stream)
1148 if (pipe_ctx_old->top_pipe)
1151 if (!pipe_ctx->stream ||
1152 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
1153 struct clock_source *old_clk = pipe_ctx_old->clock_source;
1155 reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state);
1157 old_clk->funcs->cs_power_down(old_clk);
1163 static bool patch_address_for_sbs_tb_stereo(
1164 struct pipe_ctx *pipe_ctx, PHYSICAL_ADDRESS_LOC *addr)
1166 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
1167 bool sec_split = pipe_ctx->top_pipe &&
1168 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;
1169 if (sec_split && plane_state->address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
1170 (pipe_ctx->stream->timing.timing_3d_format ==
1171 TIMING_3D_FORMAT_SIDE_BY_SIDE ||
1172 pipe_ctx->stream->timing.timing_3d_format ==
1173 TIMING_3D_FORMAT_TOP_AND_BOTTOM)) {
1174 *addr = plane_state->address.grph_stereo.left_addr;
1175 plane_state->address.grph_stereo.left_addr =
1176 plane_state->address.grph_stereo.right_addr;
1179 if (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_NONE &&
1180 plane_state->address.type != PLN_ADDR_TYPE_GRPH_STEREO) {
1181 plane_state->address.type = PLN_ADDR_TYPE_GRPH_STEREO;
1182 plane_state->address.grph_stereo.right_addr =
1183 plane_state->address.grph_stereo.left_addr;
1191 static void dcn10_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx)
1193 bool addr_patched = false;
1194 PHYSICAL_ADDRESS_LOC addr;
1195 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
1197 if (plane_state == NULL)
1200 addr_patched = patch_address_for_sbs_tb_stereo(pipe_ctx, &addr);
1202 pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr(
1203 pipe_ctx->plane_res.hubp,
1204 &plane_state->address,
1205 plane_state->flip_immediate);
1207 plane_state->status.requested_address = plane_state->address;
1209 if (plane_state->flip_immediate)
1210 plane_state->status.current_address = plane_state->address;
1213 pipe_ctx->plane_state->address.grph_stereo.left_addr = addr;
1216 static bool dcn10_set_input_transfer_func(struct pipe_ctx *pipe_ctx,
1217 const struct dc_plane_state *plane_state)
1219 struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
1220 const struct dc_transfer_func *tf = NULL;
1223 if (dpp_base == NULL)
1226 if (plane_state->in_transfer_func)
1227 tf = plane_state->in_transfer_func;
1229 if (plane_state->gamma_correction &&
1230 !dpp_base->ctx->dc->debug.always_use_regamma
1231 && !plane_state->gamma_correction->is_identity
1232 && dce_use_lut(plane_state->format))
1233 dpp_base->funcs->dpp_program_input_lut(dpp_base, plane_state->gamma_correction);
1236 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS);
1237 else if (tf->type == TF_TYPE_PREDEFINED) {
1239 case TRANSFER_FUNCTION_SRGB:
1240 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_HW_sRGB);
1242 case TRANSFER_FUNCTION_BT709:
1243 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_HW_xvYCC);
1245 case TRANSFER_FUNCTION_LINEAR:
1246 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS);
1248 case TRANSFER_FUNCTION_PQ:
1253 } else if (tf->type == TF_TYPE_BYPASS) {
1254 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS);
1256 cm_helper_translate_curve_to_degamma_hw_format(tf,
1257 &dpp_base->degamma_params);
1258 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base,
1259 &dpp_base->degamma_params);
1271 dcn10_set_output_transfer_func(struct pipe_ctx *pipe_ctx,
1272 const struct dc_stream_state *stream)
1274 struct dpp *dpp = pipe_ctx->plane_res.dpp;
1279 dpp->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM;
1281 if (stream->out_transfer_func &&
1282 stream->out_transfer_func->type == TF_TYPE_PREDEFINED &&
1283 stream->out_transfer_func->tf == TRANSFER_FUNCTION_SRGB)
1284 dpp->funcs->dpp_program_regamma_pwl(dpp, NULL, OPP_REGAMMA_SRGB);
1286 /* dcn10_translate_regamma_to_hw_format takes 750us, only do it when full
1289 else if (cm_helper_translate_curve_to_hw_format(
1290 stream->out_transfer_func,
1291 &dpp->regamma_params, false)) {
1292 dpp->funcs->dpp_program_regamma_pwl(
1294 &dpp->regamma_params, OPP_REGAMMA_USER);
1296 dpp->funcs->dpp_program_regamma_pwl(dpp, NULL, OPP_REGAMMA_BYPASS);
1301 static void dcn10_pipe_control_lock(
1303 struct pipe_ctx *pipe,
1306 /* use TG master update lock to lock everything on the TG
1307 * therefore only top pipe need to lock
1312 if (dc->debug.sanity_checks)
1313 dcn10_verify_allow_pstate_change_high(dc);
1316 pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg);
1318 pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg);
1320 if (dc->debug.sanity_checks)
1321 dcn10_verify_allow_pstate_change_high(dc);
1324 static bool wait_for_reset_trigger_to_occur(
1325 struct dc_context *dc_ctx,
1326 struct timing_generator *tg)
1330 /* To avoid endless loop we wait at most
1331 * frames_to_wait_on_triggered_reset frames for the reset to occur. */
1332 const uint32_t frames_to_wait_on_triggered_reset = 10;
1335 for (i = 0; i < frames_to_wait_on_triggered_reset; i++) {
1337 if (!tg->funcs->is_counter_moving(tg)) {
1338 DC_ERROR("TG counter is not moving!\n");
1342 if (tg->funcs->did_triggered_reset_occur(tg)) {
1344 /* usually occurs at i=1 */
1345 DC_SYNC_INFO("GSL: reset occurred at wait count: %d\n",
1350 /* Wait for one frame. */
1351 tg->funcs->wait_for_state(tg, CRTC_STATE_VACTIVE);
1352 tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK);
1356 DC_ERROR("GSL: Timeout on reset trigger!\n");
1361 static void dcn10_enable_timing_synchronization(
1365 struct pipe_ctx *grouped_pipes[])
1367 struct dc_context *dc_ctx = dc->ctx;
1370 DC_SYNC_INFO("Setting up OTG reset trigger\n");
1372 for (i = 1; i < group_size; i++)
1373 grouped_pipes[i]->stream_res.tg->funcs->enable_reset_trigger(
1374 grouped_pipes[i]->stream_res.tg,
1375 grouped_pipes[0]->stream_res.tg->inst);
1377 DC_SYNC_INFO("Waiting for trigger\n");
1379 /* Need to get only check 1 pipe for having reset as all the others are
1380 * synchronized. Look at last pipe programmed to reset.
1383 wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[1]->stream_res.tg);
1384 for (i = 1; i < group_size; i++)
1385 grouped_pipes[i]->stream_res.tg->funcs->disable_reset_trigger(
1386 grouped_pipes[i]->stream_res.tg);
1388 DC_SYNC_INFO("Sync complete\n");
1391 static void dcn10_enable_per_frame_crtc_position_reset(
1394 struct pipe_ctx *grouped_pipes[])
1396 struct dc_context *dc_ctx = dc->ctx;
1399 DC_SYNC_INFO("Setting up\n");
1400 for (i = 0; i < group_size; i++)
1401 if (grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset)
1402 grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset(
1403 grouped_pipes[i]->stream_res.tg,
1405 &grouped_pipes[i]->stream->triggered_crtc_reset);
1407 DC_SYNC_INFO("Waiting for trigger\n");
1409 for (i = 0; i < group_size; i++)
1410 wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg);
1412 DC_SYNC_INFO("Multi-display sync is complete\n");
1415 /*static void print_rq_dlg_ttu(
1417 struct pipe_ctx *pipe_ctx)
1419 DC_LOG_BANDWIDTH_CALCS(core_dc->ctx->logger,
1420 "\n============== DML TTU Output parameters [%d] ==============\n"
1421 "qos_level_low_wm: %d, \n"
1422 "qos_level_high_wm: %d, \n"
1423 "min_ttu_vblank: %d, \n"
1424 "qos_level_flip: %d, \n"
1425 "refcyc_per_req_delivery_l: %d, \n"
1426 "qos_level_fixed_l: %d, \n"
1427 "qos_ramp_disable_l: %d, \n"
1428 "refcyc_per_req_delivery_pre_l: %d, \n"
1429 "refcyc_per_req_delivery_c: %d, \n"
1430 "qos_level_fixed_c: %d, \n"
1431 "qos_ramp_disable_c: %d, \n"
1432 "refcyc_per_req_delivery_pre_c: %d\n"
1433 "=============================================================\n",
1435 pipe_ctx->ttu_regs.qos_level_low_wm,
1436 pipe_ctx->ttu_regs.qos_level_high_wm,
1437 pipe_ctx->ttu_regs.min_ttu_vblank,
1438 pipe_ctx->ttu_regs.qos_level_flip,
1439 pipe_ctx->ttu_regs.refcyc_per_req_delivery_l,
1440 pipe_ctx->ttu_regs.qos_level_fixed_l,
1441 pipe_ctx->ttu_regs.qos_ramp_disable_l,
1442 pipe_ctx->ttu_regs.refcyc_per_req_delivery_pre_l,
1443 pipe_ctx->ttu_regs.refcyc_per_req_delivery_c,
1444 pipe_ctx->ttu_regs.qos_level_fixed_c,
1445 pipe_ctx->ttu_regs.qos_ramp_disable_c,
1446 pipe_ctx->ttu_regs.refcyc_per_req_delivery_pre_c
1449 DC_LOG_BANDWIDTH_CALCS(core_dc->ctx->logger,
1450 "\n============== DML DLG Output parameters [%d] ==============\n"
1451 "refcyc_h_blank_end: %d, \n"
1452 "dlg_vblank_end: %d, \n"
1453 "min_dst_y_next_start: %d, \n"
1454 "refcyc_per_htotal: %d, \n"
1455 "refcyc_x_after_scaler: %d, \n"
1456 "dst_y_after_scaler: %d, \n"
1457 "dst_y_prefetch: %d, \n"
1458 "dst_y_per_vm_vblank: %d, \n"
1459 "dst_y_per_row_vblank: %d, \n"
1460 "ref_freq_to_pix_freq: %d, \n"
1461 "vratio_prefetch: %d, \n"
1462 "refcyc_per_pte_group_vblank_l: %d, \n"
1463 "refcyc_per_meta_chunk_vblank_l: %d, \n"
1464 "dst_y_per_pte_row_nom_l: %d, \n"
1465 "refcyc_per_pte_group_nom_l: %d, \n",
1467 pipe_ctx->dlg_regs.refcyc_h_blank_end,
1468 pipe_ctx->dlg_regs.dlg_vblank_end,
1469 pipe_ctx->dlg_regs.min_dst_y_next_start,
1470 pipe_ctx->dlg_regs.refcyc_per_htotal,
1471 pipe_ctx->dlg_regs.refcyc_x_after_scaler,
1472 pipe_ctx->dlg_regs.dst_y_after_scaler,
1473 pipe_ctx->dlg_regs.dst_y_prefetch,
1474 pipe_ctx->dlg_regs.dst_y_per_vm_vblank,
1475 pipe_ctx->dlg_regs.dst_y_per_row_vblank,
1476 pipe_ctx->dlg_regs.ref_freq_to_pix_freq,
1477 pipe_ctx->dlg_regs.vratio_prefetch,
1478 pipe_ctx->dlg_regs.refcyc_per_pte_group_vblank_l,
1479 pipe_ctx->dlg_regs.refcyc_per_meta_chunk_vblank_l,
1480 pipe_ctx->dlg_regs.dst_y_per_pte_row_nom_l,
1481 pipe_ctx->dlg_regs.refcyc_per_pte_group_nom_l
1484 DC_LOG_BANDWIDTH_CALCS(core_dc->ctx->logger,
1485 "\ndst_y_per_meta_row_nom_l: %d, \n"
1486 "refcyc_per_meta_chunk_nom_l: %d, \n"
1487 "refcyc_per_line_delivery_pre_l: %d, \n"
1488 "refcyc_per_line_delivery_l: %d, \n"
1489 "vratio_prefetch_c: %d, \n"
1490 "refcyc_per_pte_group_vblank_c: %d, \n"
1491 "refcyc_per_meta_chunk_vblank_c: %d, \n"
1492 "dst_y_per_pte_row_nom_c: %d, \n"
1493 "refcyc_per_pte_group_nom_c: %d, \n"
1494 "dst_y_per_meta_row_nom_c: %d, \n"
1495 "refcyc_per_meta_chunk_nom_c: %d, \n"
1496 "refcyc_per_line_delivery_pre_c: %d, \n"
1497 "refcyc_per_line_delivery_c: %d \n"
1498 "========================================================\n",
1499 pipe_ctx->dlg_regs.dst_y_per_meta_row_nom_l,
1500 pipe_ctx->dlg_regs.refcyc_per_meta_chunk_nom_l,
1501 pipe_ctx->dlg_regs.refcyc_per_line_delivery_pre_l,
1502 pipe_ctx->dlg_regs.refcyc_per_line_delivery_l,
1503 pipe_ctx->dlg_regs.vratio_prefetch_c,
1504 pipe_ctx->dlg_regs.refcyc_per_pte_group_vblank_c,
1505 pipe_ctx->dlg_regs.refcyc_per_meta_chunk_vblank_c,
1506 pipe_ctx->dlg_regs.dst_y_per_pte_row_nom_c,
1507 pipe_ctx->dlg_regs.refcyc_per_pte_group_nom_c,
1508 pipe_ctx->dlg_regs.dst_y_per_meta_row_nom_c,
1509 pipe_ctx->dlg_regs.refcyc_per_meta_chunk_nom_c,
1510 pipe_ctx->dlg_regs.refcyc_per_line_delivery_pre_c,
1511 pipe_ctx->dlg_regs.refcyc_per_line_delivery_c
1514 DC_LOG_BANDWIDTH_CALCS(core_dc->ctx->logger,
1515 "\n============== DML RQ Output parameters [%d] ==============\n"
1517 "min_chunk_size: %d \n"
1518 "meta_chunk_size: %d \n"
1519 "min_meta_chunk_size: %d \n"
1520 "dpte_group_size: %d \n"
1521 "mpte_group_size: %d \n"
1522 "swath_height: %d \n"
1523 "pte_row_height_linear: %d \n"
1524 "========================================================\n",
1526 pipe_ctx->rq_regs.rq_regs_l.chunk_size,
1527 pipe_ctx->rq_regs.rq_regs_l.min_chunk_size,
1528 pipe_ctx->rq_regs.rq_regs_l.meta_chunk_size,
1529 pipe_ctx->rq_regs.rq_regs_l.min_meta_chunk_size,
1530 pipe_ctx->rq_regs.rq_regs_l.dpte_group_size,
1531 pipe_ctx->rq_regs.rq_regs_l.mpte_group_size,
1532 pipe_ctx->rq_regs.rq_regs_l.swath_height,
1533 pipe_ctx->rq_regs.rq_regs_l.pte_row_height_linear
1538 static void mmhub_read_vm_system_aperture_settings(struct dcn10_hubp *hubp1,
1539 struct vm_system_aperture_param *apt,
1540 struct dce_hwseq *hws)
1542 PHYSICAL_ADDRESS_LOC physical_page_number;
1543 uint32_t logical_addr_low;
1544 uint32_t logical_addr_high;
1546 REG_GET(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
1547 PHYSICAL_PAGE_NUMBER_MSB, &physical_page_number.high_part);
1548 REG_GET(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
1549 PHYSICAL_PAGE_NUMBER_LSB, &physical_page_number.low_part);
1551 REG_GET(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1552 LOGICAL_ADDR, &logical_addr_low);
1554 REG_GET(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1555 LOGICAL_ADDR, &logical_addr_high);
1557 apt->sys_default.quad_part = physical_page_number.quad_part << 12;
1558 apt->sys_low.quad_part = (int64_t)logical_addr_low << 18;
1559 apt->sys_high.quad_part = (int64_t)logical_addr_high << 18;
1562 /* Temporary read settings, future will get values from kmd directly */
1563 static void mmhub_read_vm_context0_settings(struct dcn10_hubp *hubp1,
1564 struct vm_context0_param *vm0,
1565 struct dce_hwseq *hws)
1567 PHYSICAL_ADDRESS_LOC fb_base;
1568 PHYSICAL_ADDRESS_LOC fb_offset;
1569 uint32_t fb_base_value;
1570 uint32_t fb_offset_value;
1572 REG_GET(DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, &fb_base_value);
1573 REG_GET(DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, &fb_offset_value);
1575 REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
1576 PAGE_DIRECTORY_ENTRY_HI32, &vm0->pte_base.high_part);
1577 REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
1578 PAGE_DIRECTORY_ENTRY_LO32, &vm0->pte_base.low_part);
1580 REG_GET(VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
1581 LOGICAL_PAGE_NUMBER_HI4, &vm0->pte_start.high_part);
1582 REG_GET(VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
1583 LOGICAL_PAGE_NUMBER_LO32, &vm0->pte_start.low_part);
1585 REG_GET(VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
1586 LOGICAL_PAGE_NUMBER_HI4, &vm0->pte_end.high_part);
1587 REG_GET(VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
1588 LOGICAL_PAGE_NUMBER_LO32, &vm0->pte_end.low_part);
1590 REG_GET(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
1591 PHYSICAL_PAGE_ADDR_HI4, &vm0->fault_default.high_part);
1592 REG_GET(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
1593 PHYSICAL_PAGE_ADDR_LO32, &vm0->fault_default.low_part);
1596 * The values in VM_CONTEXT0_PAGE_TABLE_BASE_ADDR is in UMA space.
1597 * Therefore we need to do
1598 * DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR = VM_CONTEXT0_PAGE_TABLE_BASE_ADDR
1599 * - DCHUBBUB_SDPIF_FB_OFFSET + DCHUBBUB_SDPIF_FB_BASE
1601 fb_base.quad_part = (uint64_t)fb_base_value << 24;
1602 fb_offset.quad_part = (uint64_t)fb_offset_value << 24;
1603 vm0->pte_base.quad_part += fb_base.quad_part;
1604 vm0->pte_base.quad_part -= fb_offset.quad_part;
1608 void dcn10_program_pte_vm(struct dce_hwseq *hws, struct hubp *hubp)
1610 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
1611 struct vm_system_aperture_param apt = { {{ 0 } } };
1612 struct vm_context0_param vm0 = { { { 0 } } };
1614 mmhub_read_vm_system_aperture_settings(hubp1, &apt, hws);
1615 mmhub_read_vm_context0_settings(hubp1, &vm0, hws);
1617 hubp->funcs->hubp_set_vm_system_aperture_settings(hubp, &apt);
1618 hubp->funcs->hubp_set_vm_context0_settings(hubp, &vm0);
1621 static void dcn10_enable_plane(
1623 struct pipe_ctx *pipe_ctx,
1624 struct dc_state *context)
1626 struct dce_hwseq *hws = dc->hwseq;
1628 if (dc->debug.sanity_checks) {
1629 dcn10_verify_allow_pstate_change_high(dc);
1632 undo_DEGVIDCN10_253_wa(dc);
1634 power_on_plane(dc->hwseq,
1635 pipe_ctx->plane_res.hubp->inst);
1637 /* enable DCFCLK current DCHUB */
1638 pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true);
1640 /* make sure OPP_PIPE_CLOCK_EN = 1 */
1641 pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(
1642 pipe_ctx->stream_res.opp,
1645 /* TODO: enable/disable in dm as per update type.
1647 DC_LOG_DC(dc->ctx->logger,
1648 "Pipe:%d 0x%x: addr hi:0x%x, "
1651 " %d; dst: %d, %d, %d, %d;\n",
1654 plane_state->address.grph.addr.high_part,
1655 plane_state->address.grph.addr.low_part,
1656 plane_state->src_rect.x,
1657 plane_state->src_rect.y,
1658 plane_state->src_rect.width,
1659 plane_state->src_rect.height,
1660 plane_state->dst_rect.x,
1661 plane_state->dst_rect.y,
1662 plane_state->dst_rect.width,
1663 plane_state->dst_rect.height);
1665 DC_LOG_DC(dc->ctx->logger,
1666 "Pipe %d: width, height, x, y format:%d\n"
1667 "viewport:%d, %d, %d, %d\n"
1668 "recout: %d, %d, %d, %d\n",
1670 plane_state->format,
1671 pipe_ctx->plane_res.scl_data.viewport.width,
1672 pipe_ctx->plane_res.scl_data.viewport.height,
1673 pipe_ctx->plane_res.scl_data.viewport.x,
1674 pipe_ctx->plane_res.scl_data.viewport.y,
1675 pipe_ctx->plane_res.scl_data.recout.width,
1676 pipe_ctx->plane_res.scl_data.recout.height,
1677 pipe_ctx->plane_res.scl_data.recout.x,
1678 pipe_ctx->plane_res.scl_data.recout.y);
1679 print_rq_dlg_ttu(dc, pipe_ctx);
1682 if (dc->config.gpu_vm_support)
1683 dcn10_program_pte_vm(hws, pipe_ctx->plane_res.hubp);
1685 if (dc->debug.sanity_checks) {
1686 dcn10_verify_allow_pstate_change_high(dc);
1690 static void program_gamut_remap(struct pipe_ctx *pipe_ctx)
1693 struct dpp_grph_csc_adjustment adjust;
1694 memset(&adjust, 0, sizeof(adjust));
1695 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
1698 if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
1699 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
1700 for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++)
1701 adjust.temperature_matrix[i] =
1702 pipe_ctx->stream->gamut_remap_matrix.matrix[i];
1705 pipe_ctx->plane_res.dpp->funcs->dpp_set_gamut_remap(pipe_ctx->plane_res.dpp, &adjust);
1708 static void dcn10_program_output_csc(struct dc *dc,
1709 struct pipe_ctx *pipe_ctx,
1710 enum dc_color_space colorspace,
1714 if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) {
1715 if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment != NULL)
1716 pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment(pipe_ctx->plane_res.dpp, matrix);
1718 if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_default != NULL)
1719 pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_default(pipe_ctx->plane_res.dpp, colorspace);
1723 bool is_lower_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
1725 if (pipe_ctx->plane_state->visible)
1727 if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe))
1732 bool is_upper_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
1734 if (pipe_ctx->plane_state->visible)
1736 if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe))
1741 bool is_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
1743 if (pipe_ctx->plane_state->visible)
1745 if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe))
1747 if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe))
1752 bool is_rgb_cspace(enum dc_color_space output_color_space)
1754 switch (output_color_space) {
1755 case COLOR_SPACE_SRGB:
1756 case COLOR_SPACE_SRGB_LIMITED:
1757 case COLOR_SPACE_2020_RGB_FULLRANGE:
1758 case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
1759 case COLOR_SPACE_ADOBERGB:
1761 case COLOR_SPACE_YCBCR601:
1762 case COLOR_SPACE_YCBCR709:
1763 case COLOR_SPACE_YCBCR601_LIMITED:
1764 case COLOR_SPACE_YCBCR709_LIMITED:
1765 case COLOR_SPACE_2020_YCBCR:
1768 /* Add a case to switch */
1769 BREAK_TO_DEBUGGER();
1774 void dcn10_get_surface_visual_confirm_color(
1775 const struct pipe_ctx *pipe_ctx,
1776 struct tg_color *color)
1778 uint32_t color_value = MAX_TG_COLOR_VALUE;
1780 switch (pipe_ctx->plane_res.scl_data.format) {
1781 case PIXEL_FORMAT_ARGB8888:
1782 /* set boarder color to red */
1783 color->color_r_cr = color_value;
1786 case PIXEL_FORMAT_ARGB2101010:
1787 /* set boarder color to blue */
1788 color->color_b_cb = color_value;
1790 case PIXEL_FORMAT_420BPP8:
1791 /* set boarder color to green */
1792 color->color_g_y = color_value;
1794 case PIXEL_FORMAT_420BPP10:
1795 /* set boarder color to yellow */
1796 color->color_g_y = color_value;
1797 color->color_r_cr = color_value;
1799 case PIXEL_FORMAT_FP16:
1800 /* set boarder color to white */
1801 color->color_r_cr = color_value;
1802 color->color_b_cb = color_value;
1803 color->color_g_y = color_value;
1810 void dcn10_get_hdr_visual_confirm_color(
1811 struct pipe_ctx *pipe_ctx,
1812 struct tg_color *color)
1814 uint32_t color_value = MAX_TG_COLOR_VALUE;
1816 // Determine the overscan color based on the top-most (desktop) plane's context
1817 struct pipe_ctx *top_pipe_ctx = pipe_ctx;
1819 while (top_pipe_ctx->top_pipe != NULL)
1820 top_pipe_ctx = top_pipe_ctx->top_pipe;
1822 switch (top_pipe_ctx->plane_res.scl_data.format) {
1823 case PIXEL_FORMAT_ARGB2101010:
1824 if (top_pipe_ctx->stream->out_transfer_func->tf == TRANSFER_FUNCTION_UNITY) {
1825 /* HDR10, ARGB2101010 - set boarder color to red */
1826 color->color_r_cr = color_value;
1829 case PIXEL_FORMAT_FP16:
1830 if (top_pipe_ctx->stream->out_transfer_func->tf == TRANSFER_FUNCTION_PQ) {
1831 /* HDR10, FP16 - set boarder color to blue */
1832 color->color_b_cb = color_value;
1833 } else if (top_pipe_ctx->stream->out_transfer_func->tf == TRANSFER_FUNCTION_GAMMA22) {
1834 /* FreeSync 2 HDR - set boarder color to green */
1835 color->color_g_y = color_value;
1839 /* SDR - set boarder color to Gray */
1840 color->color_r_cr = color_value/2;
1841 color->color_b_cb = color_value/2;
1842 color->color_g_y = color_value/2;
1847 static uint16_t fixed_point_to_int_frac(
1848 struct fixed31_32 arg,
1849 uint8_t integer_bits,
1850 uint8_t fractional_bits)
1853 int32_t divisor = 1 << fractional_bits;
1857 uint16_t d = (uint16_t)dc_fixpt_floor(
1861 if (d <= (uint16_t)(1 << integer_bits) - (1 / (uint16_t)divisor))
1862 numerator = (uint16_t)dc_fixpt_floor(
1867 numerator = dc_fixpt_floor(
1870 1LL << integer_bits),
1877 result = (uint16_t)numerator;
1879 result = (uint16_t)(
1880 (1 << (integer_bits + fractional_bits + 1)) + numerator);
1882 if ((result != 0) && dc_fixpt_lt(
1883 arg, dc_fixpt_zero))
1884 result |= 1 << (integer_bits + fractional_bits);
1889 void build_prescale_params(struct dc_bias_and_scale *bias_and_scale,
1890 const struct dc_plane_state *plane_state)
1892 if (plane_state->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN
1893 && plane_state->format != SURFACE_PIXEL_FORMAT_INVALID
1894 && plane_state->input_csc_color_matrix.enable_adjustment
1895 && plane_state->coeff_reduction_factor.value != 0) {
1896 bias_and_scale->scale_blue = fixed_point_to_int_frac(
1897 dc_fixpt_mul(plane_state->coeff_reduction_factor,
1898 dc_fixpt_from_fraction(256, 255)),
1901 bias_and_scale->scale_red = bias_and_scale->scale_blue;
1902 bias_and_scale->scale_green = bias_and_scale->scale_blue;
1904 bias_and_scale->scale_blue = 0x2000;
1905 bias_and_scale->scale_red = 0x2000;
1906 bias_and_scale->scale_green = 0x2000;
1910 static void update_dpp(struct dpp *dpp, struct dc_plane_state *plane_state)
1912 struct dc_bias_and_scale bns_params = {0};
1914 // program the input csc
1915 dpp->funcs->dpp_setup(dpp,
1916 plane_state->format,
1917 EXPANSION_MODE_ZERO,
1918 plane_state->input_csc_color_matrix,
1919 COLOR_SPACE_YCBCR601_LIMITED);
1921 //set scale and bias registers
1922 build_prescale_params(&bns_params, plane_state);
1923 if (dpp->funcs->dpp_program_bias_and_scale)
1924 dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params);
1927 static void dcn10_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
1929 struct hubp *hubp = pipe_ctx->plane_res.hubp;
1930 struct mpcc_blnd_cfg blnd_cfg = {{0}};
1931 bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe;
1933 struct mpcc *new_mpcc;
1934 struct mpc *mpc = dc->res_pool->mpc;
1935 struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params);
1937 if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR) {
1938 dcn10_get_hdr_visual_confirm_color(
1939 pipe_ctx, &blnd_cfg.black_color);
1940 } else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE) {
1941 dcn10_get_surface_visual_confirm_color(
1942 pipe_ctx, &blnd_cfg.black_color);
1944 color_space_to_black_color(
1945 dc, pipe_ctx->stream->output_color_space,
1946 &blnd_cfg.black_color);
1949 if (per_pixel_alpha)
1950 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA;
1952 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA;
1954 blnd_cfg.overlap_only = false;
1955 blnd_cfg.global_gain = 0xff;
1957 if (pipe_ctx->plane_state->global_alpha)
1958 blnd_cfg.global_alpha = pipe_ctx->plane_state->global_alpha_value;
1960 blnd_cfg.global_alpha = 0xff;
1962 /* DCN1.0 has output CM before MPC which seems to screw with
1963 * pre-multiplied alpha.
1965 blnd_cfg.pre_multiplied_alpha = is_rgb_cspace(
1966 pipe_ctx->stream->output_color_space)
1972 * Note: currently there is a bug in init_hw such that
1973 * on resume from hibernate, BIOS sets up MPCC0, and
1974 * we do mpcc_remove but the mpcc cannot go to idle
1975 * after remove. This cause us to pick mpcc1 here,
1976 * which causes a pstate hang for yet unknown reason.
1978 mpcc_id = hubp->inst;
1980 /* If there is no full update, don't need to touch MPC tree*/
1981 if (!pipe_ctx->plane_state->update_flags.bits.full_update) {
1982 mpc->funcs->update_blending(mpc, &blnd_cfg, mpcc_id);
1986 /* check if this MPCC is already being used */
1987 new_mpcc = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, mpcc_id);
1988 /* remove MPCC if being used */
1989 if (new_mpcc != NULL)
1990 mpc->funcs->remove_mpcc(mpc, mpc_tree_params, new_mpcc);
1992 if (dc->debug.sanity_checks)
1993 mpc->funcs->assert_mpcc_idle_before_connect(
1994 dc->res_pool->mpc, mpcc_id);
1996 /* Call MPC to insert new plane */
1997 new_mpcc = mpc->funcs->insert_plane(dc->res_pool->mpc,
2005 ASSERT(new_mpcc != NULL);
2007 hubp->opp_id = pipe_ctx->stream_res.opp->inst;
2008 hubp->mpcc_id = mpcc_id;
2011 static void update_scaler(struct pipe_ctx *pipe_ctx)
2013 bool per_pixel_alpha =
2014 pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe;
2016 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = per_pixel_alpha;
2017 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;
2018 /* scaler configuration */
2019 pipe_ctx->plane_res.dpp->funcs->dpp_set_scaler(
2020 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data);
2023 void update_dchubp_dpp(
2025 struct pipe_ctx *pipe_ctx,
2026 struct dc_state *context)
2028 struct hubp *hubp = pipe_ctx->plane_res.hubp;
2029 struct dpp *dpp = pipe_ctx->plane_res.dpp;
2030 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2031 union plane_size size = plane_state->plane_size;
2032 unsigned int compat_level = 0;
2034 /* depends on DML calculation, DPP clock value may change dynamically */
2035 /* If request max dpp clk is lower than current dispclk, no need to
2038 if (plane_state->update_flags.bits.full_update) {
2039 bool should_divided_by_2 = context->bw.dcn.clk.dppclk_khz <=
2040 dc->res_pool->clk_mgr->clks.dispclk_khz / 2;
2042 dpp->funcs->dpp_dppclk_control(
2044 should_divided_by_2,
2047 if (dc->res_pool->dccg)
2048 dc->res_pool->dccg->funcs->update_dpp_dto(
2051 pipe_ctx->plane_res.bw.calc.dppclk_khz);
2053 dc->res_pool->clk_mgr->clks.dppclk_khz = should_divided_by_2 ?
2054 dc->res_pool->clk_mgr->clks.dispclk_khz / 2 :
2055 dc->res_pool->clk_mgr->clks.dispclk_khz;
2058 /* TODO: Need input parameter to tell current DCHUB pipe tie to which OTG
2059 * VTG is within DCHUBBUB which is commond block share by each pipe HUBP.
2060 * VTG is 1:1 mapping with OTG. Each pipe HUBP will select which VTG
2062 if (plane_state->update_flags.bits.full_update) {
2063 hubp->funcs->hubp_vtg_sel(hubp, pipe_ctx->stream_res.tg->inst);
2065 hubp->funcs->hubp_setup(
2067 &pipe_ctx->dlg_regs,
2068 &pipe_ctx->ttu_regs,
2070 &pipe_ctx->pipe_dlg_param);
2071 hubp->funcs->hubp_setup_interdependent(
2073 &pipe_ctx->dlg_regs,
2074 &pipe_ctx->ttu_regs);
2077 size.grph.surface_size = pipe_ctx->plane_res.scl_data.viewport;
2079 if (plane_state->update_flags.bits.full_update ||
2080 plane_state->update_flags.bits.bpp_change)
2081 update_dpp(dpp, plane_state);
2083 if (plane_state->update_flags.bits.full_update ||
2084 plane_state->update_flags.bits.per_pixel_alpha_change ||
2085 plane_state->update_flags.bits.global_alpha_change)
2086 dc->hwss.update_mpcc(dc, pipe_ctx);
2088 if (plane_state->update_flags.bits.full_update ||
2089 plane_state->update_flags.bits.per_pixel_alpha_change ||
2090 plane_state->update_flags.bits.global_alpha_change ||
2091 plane_state->update_flags.bits.scaling_change ||
2092 plane_state->update_flags.bits.position_change) {
2093 update_scaler(pipe_ctx);
2096 if (plane_state->update_flags.bits.full_update ||
2097 plane_state->update_flags.bits.scaling_change ||
2098 plane_state->update_flags.bits.position_change) {
2099 hubp->funcs->mem_program_viewport(
2101 &pipe_ctx->plane_res.scl_data.viewport,
2102 &pipe_ctx->plane_res.scl_data.viewport_c);
2105 if (pipe_ctx->stream->cursor_attributes.address.quad_part != 0) {
2106 dc->hwss.set_cursor_position(pipe_ctx);
2107 dc->hwss.set_cursor_attribute(pipe_ctx);
2110 if (plane_state->update_flags.bits.full_update) {
2112 program_gamut_remap(pipe_ctx);
2114 dc->hwss.program_output_csc(dc,
2116 pipe_ctx->stream->output_color_space,
2117 pipe_ctx->stream->csc_color_matrix.matrix,
2121 if (plane_state->update_flags.bits.full_update ||
2122 plane_state->update_flags.bits.pixel_format_change ||
2123 plane_state->update_flags.bits.horizontal_mirror_change ||
2124 plane_state->update_flags.bits.rotation_change ||
2125 plane_state->update_flags.bits.swizzle_change ||
2126 plane_state->update_flags.bits.dcc_change ||
2127 plane_state->update_flags.bits.bpp_change ||
2128 plane_state->update_flags.bits.scaling_change) {
2129 hubp->funcs->hubp_program_surface_config(
2131 plane_state->format,
2132 &plane_state->tiling_info,
2134 plane_state->rotation,
2136 plane_state->horizontal_mirror,
2140 hubp->power_gated = false;
2142 dc->hwss.update_plane_addr(dc, pipe_ctx);
2144 if (is_pipe_tree_visible(pipe_ctx))
2145 hubp->funcs->set_blank(hubp, false);
2148 static void dcn10_blank_pixel_data(
2150 struct pipe_ctx *pipe_ctx,
2153 enum dc_color_space color_space;
2154 struct tg_color black_color = {0};
2155 struct stream_resource *stream_res = &pipe_ctx->stream_res;
2156 struct dc_stream_state *stream = pipe_ctx->stream;
2158 /* program otg blank color */
2159 color_space = stream->output_color_space;
2160 color_space_to_black_color(dc, color_space, &black_color);
2163 * The way 420 is packed, 2 channels carry Y component, 1 channel
2164 * alternate between Cb and Cr, so both channels need the pixel
2167 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
2168 black_color.color_r_cr = black_color.color_g_y;
2171 if (stream_res->tg->funcs->set_blank_color)
2172 stream_res->tg->funcs->set_blank_color(
2177 if (stream_res->tg->funcs->set_blank)
2178 stream_res->tg->funcs->set_blank(stream_res->tg, blank);
2179 if (stream_res->abm)
2180 stream_res->abm->funcs->set_abm_level(stream_res->abm, stream->abm_level);
2182 if (stream_res->abm)
2183 stream_res->abm->funcs->set_abm_immediate_disable(stream_res->abm);
2184 if (stream_res->tg->funcs->set_blank)
2185 stream_res->tg->funcs->set_blank(stream_res->tg, blank);
2189 void set_hdr_multiplier(struct pipe_ctx *pipe_ctx)
2191 struct fixed31_32 multiplier = dc_fixpt_from_fraction(
2192 pipe_ctx->plane_state->sdr_white_level, 80);
2193 uint32_t hw_mult = 0x1f000; // 1.0 default multiplier
2194 struct custom_float_format fmt;
2196 fmt.exponenta_bits = 6;
2197 fmt.mantissa_bits = 12;
2200 if (pipe_ctx->plane_state->sdr_white_level > 80)
2201 convert_to_custom_float_format(multiplier, &fmt, &hw_mult);
2203 pipe_ctx->plane_res.dpp->funcs->dpp_set_hdr_multiplier(
2204 pipe_ctx->plane_res.dpp, hw_mult);
2207 void dcn10_program_pipe(
2209 struct pipe_ctx *pipe_ctx,
2210 struct dc_state *context)
2212 if (pipe_ctx->plane_state->update_flags.bits.full_update)
2213 dcn10_enable_plane(dc, pipe_ctx, context);
2215 update_dchubp_dpp(dc, pipe_ctx, context);
2217 set_hdr_multiplier(pipe_ctx);
2219 if (pipe_ctx->plane_state->update_flags.bits.full_update ||
2220 pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||
2221 pipe_ctx->plane_state->update_flags.bits.gamma_change)
2222 dc->hwss.set_input_transfer_func(pipe_ctx, pipe_ctx->plane_state);
2224 /* dcn10_translate_regamma_to_hw_format takes 750us to finish
2225 * only do gamma programming for full update.
2226 * TODO: This can be further optimized/cleaned up
2227 * Always call this for now since it does memcmp inside before
2228 * doing heavy calculation and programming
2230 if (pipe_ctx->plane_state->update_flags.bits.full_update)
2231 dc->hwss.set_output_transfer_func(pipe_ctx, pipe_ctx->stream);
2234 static void program_all_pipe_in_tree(
2236 struct pipe_ctx *pipe_ctx,
2237 struct dc_state *context)
2239 if (pipe_ctx->top_pipe == NULL) {
2240 bool blank = !is_pipe_tree_visible(pipe_ctx);
2242 pipe_ctx->stream_res.tg->dlg_otg_param.vready_offset = pipe_ctx->pipe_dlg_param.vready_offset;
2243 pipe_ctx->stream_res.tg->dlg_otg_param.vstartup_start = pipe_ctx->pipe_dlg_param.vstartup_start;
2244 pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_offset = pipe_ctx->pipe_dlg_param.vupdate_offset;
2245 pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_width = pipe_ctx->pipe_dlg_param.vupdate_width;
2246 pipe_ctx->stream_res.tg->dlg_otg_param.signal = pipe_ctx->stream->signal;
2248 pipe_ctx->stream_res.tg->funcs->program_global_sync(
2249 pipe_ctx->stream_res.tg);
2251 dc->hwss.blank_pixel_data(dc, pipe_ctx, blank);
2255 if (pipe_ctx->plane_state != NULL) {
2256 dcn10_program_pipe(dc, pipe_ctx, context);
2259 if (pipe_ctx->bottom_pipe != NULL && pipe_ctx->bottom_pipe != pipe_ctx) {
2260 program_all_pipe_in_tree(dc, pipe_ctx->bottom_pipe, context);
2264 struct pipe_ctx *find_top_pipe_for_stream(
2266 struct dc_state *context,
2267 const struct dc_stream_state *stream)
2271 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2272 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2273 struct pipe_ctx *old_pipe_ctx =
2274 &dc->current_state->res_ctx.pipe_ctx[i];
2276 if (!pipe_ctx->plane_state && !old_pipe_ctx->plane_state)
2279 if (pipe_ctx->stream != stream)
2282 if (!pipe_ctx->top_pipe)
2288 static void dcn10_apply_ctx_for_surface(
2290 const struct dc_stream_state *stream,
2292 struct dc_state *context)
2295 struct timing_generator *tg;
2296 bool removed_pipe[4] = { false };
2297 struct pipe_ctx *top_pipe_to_program =
2298 find_top_pipe_for_stream(dc, context, stream);
2299 DC_LOGGER_INIT(dc->ctx->logger);
2301 if (!top_pipe_to_program)
2304 tg = top_pipe_to_program->stream_res.tg;
2306 dcn10_pipe_control_lock(dc, top_pipe_to_program, true);
2308 if (num_planes == 0) {
2309 /* OTG blank before remove all front end */
2310 dc->hwss.blank_pixel_data(dc, top_pipe_to_program, true);
2313 /* Disconnect unused mpcc */
2314 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2315 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2316 struct pipe_ctx *old_pipe_ctx =
2317 &dc->current_state->res_ctx.pipe_ctx[i];
2319 * Powergate reused pipes that are not powergated
2320 * fairly hacky right now, using opp_id as indicator
2321 * TODO: After move dc_post to dc_update, this will
2324 if (pipe_ctx->plane_state && !old_pipe_ctx->plane_state) {
2325 if (old_pipe_ctx->stream_res.tg == tg &&
2326 old_pipe_ctx->plane_res.hubp &&
2327 old_pipe_ctx->plane_res.hubp->opp_id != 0xf) {
2328 dcn10_disable_plane(dc, old_pipe_ctx);
2330 * power down fe will unlock when calling reset, need
2331 * to lock it back here. Messy, need rework.
2333 pipe_ctx->stream_res.tg->funcs->lock(pipe_ctx->stream_res.tg);
2337 if (!pipe_ctx->plane_state &&
2338 old_pipe_ctx->plane_state &&
2339 old_pipe_ctx->stream_res.tg == tg) {
2341 dc->hwss.plane_atomic_disconnect(dc, old_pipe_ctx);
2342 removed_pipe[i] = true;
2344 DC_LOG_DC("Reset mpcc for pipe %d\n",
2345 old_pipe_ctx->pipe_idx);
2350 program_all_pipe_in_tree(dc, top_pipe_to_program, context);
2352 dcn10_pipe_control_lock(dc, top_pipe_to_program, false);
2354 if (top_pipe_to_program->plane_state &&
2355 top_pipe_to_program->plane_state->update_flags.bits.full_update)
2356 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2357 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2359 /* Skip inactive pipes and ones already updated */
2360 if (!pipe_ctx->stream || pipe_ctx->stream == stream
2361 || !pipe_ctx->plane_state)
2364 pipe_ctx->stream_res.tg->funcs->lock(pipe_ctx->stream_res.tg);
2366 pipe_ctx->plane_res.hubp->funcs->hubp_setup_interdependent(
2367 pipe_ctx->plane_res.hubp,
2368 &pipe_ctx->dlg_regs,
2369 &pipe_ctx->ttu_regs);
2372 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2373 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2375 if (!pipe_ctx->stream || pipe_ctx->stream == stream
2376 || !pipe_ctx->plane_state)
2379 dcn10_pipe_control_lock(dc, pipe_ctx, false);
2382 if (num_planes == 0)
2383 false_optc_underflow_wa(dc, stream, tg);
2385 for (i = 0; i < dc->res_pool->pipe_count; i++)
2386 if (removed_pipe[i])
2387 dcn10_disable_plane(dc, &dc->current_state->res_ctx.pipe_ctx[i]);
2389 if (dc->hwseq->wa.DEGVIDCN10_254)
2390 hubbub1_wm_change_req_wa(dc->res_pool->hubbub);
2393 static void dcn10_prepare_bandwidth(
2395 struct dc_state *context)
2397 if (dc->debug.sanity_checks)
2398 dcn10_verify_allow_pstate_change_high(dc);
2400 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
2401 if (context->stream_count == 0)
2402 context->bw.dcn.clk.phyclk_khz = 0;
2404 dc->res_pool->clk_mgr->funcs->update_clocks(
2405 dc->res_pool->clk_mgr,
2410 hubbub1_program_watermarks(dc->res_pool->hubbub,
2411 &context->bw.dcn.watermarks,
2412 dc->res_pool->ref_clock_inKhz / 1000,
2415 if (dc->debug.pplib_wm_report_mode == WM_REPORT_OVERRIDE)
2416 dcn_bw_notify_pplib_of_wm_ranges(dc);
2418 if (dc->debug.sanity_checks)
2419 dcn10_verify_allow_pstate_change_high(dc);
2422 static void dcn10_optimize_bandwidth(
2424 struct dc_state *context)
2426 if (dc->debug.sanity_checks)
2427 dcn10_verify_allow_pstate_change_high(dc);
2429 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
2430 if (context->stream_count == 0)
2431 context->bw.dcn.clk.phyclk_khz = 0;
2433 dc->res_pool->clk_mgr->funcs->update_clocks(
2434 dc->res_pool->clk_mgr,
2439 hubbub1_program_watermarks(dc->res_pool->hubbub,
2440 &context->bw.dcn.watermarks,
2441 dc->res_pool->ref_clock_inKhz / 1000,
2444 if (dc->debug.pplib_wm_report_mode == WM_REPORT_OVERRIDE)
2445 dcn_bw_notify_pplib_of_wm_ranges(dc);
2447 if (dc->debug.sanity_checks)
2448 dcn10_verify_allow_pstate_change_high(dc);
2451 static void set_drr(struct pipe_ctx **pipe_ctx,
2452 int num_pipes, int vmin, int vmax)
2455 struct drr_params params = {0};
2456 // DRR should set trigger event to monitor surface update event
2457 unsigned int event_triggers = 0x80;
2459 params.vertical_total_max = vmax;
2460 params.vertical_total_min = vmin;
2462 /* TODO: If multiple pipes are to be supported, you need
2463 * some GSL stuff. Static screen triggers may be programmed differently
2466 for (i = 0; i < num_pipes; i++) {
2467 pipe_ctx[i]->stream_res.tg->funcs->set_drr(
2468 pipe_ctx[i]->stream_res.tg, ¶ms);
2469 if (vmax != 0 && vmin != 0)
2470 pipe_ctx[i]->stream_res.tg->funcs->set_static_screen_control(
2471 pipe_ctx[i]->stream_res.tg,
2476 static void get_position(struct pipe_ctx **pipe_ctx,
2478 struct crtc_position *position)
2482 /* TODO: handle pipes > 1
2484 for (i = 0; i < num_pipes; i++)
2485 pipe_ctx[i]->stream_res.tg->funcs->get_position(pipe_ctx[i]->stream_res.tg, position);
2488 static void set_static_screen_control(struct pipe_ctx **pipe_ctx,
2489 int num_pipes, const struct dc_static_screen_events *events)
2492 unsigned int value = 0;
2494 if (events->surface_update)
2496 if (events->cursor_update)
2498 if (events->force_trigger)
2501 for (i = 0; i < num_pipes; i++)
2502 pipe_ctx[i]->stream_res.tg->funcs->
2503 set_static_screen_control(pipe_ctx[i]->stream_res.tg, value);
2506 static void dcn10_config_stereo_parameters(
2507 struct dc_stream_state *stream, struct crtc_stereo_flags *flags)
2509 enum view_3d_format view_format = stream->view_format;
2510 enum dc_timing_3d_format timing_3d_format =\
2511 stream->timing.timing_3d_format;
2512 bool non_stereo_timing = false;
2514 if (timing_3d_format == TIMING_3D_FORMAT_NONE ||
2515 timing_3d_format == TIMING_3D_FORMAT_SIDE_BY_SIDE ||
2516 timing_3d_format == TIMING_3D_FORMAT_TOP_AND_BOTTOM)
2517 non_stereo_timing = true;
2519 if (non_stereo_timing == false &&
2520 view_format == VIEW_3D_FORMAT_FRAME_SEQUENTIAL) {
2522 flags->PROGRAM_STEREO = 1;
2523 flags->PROGRAM_POLARITY = 1;
2524 if (timing_3d_format == TIMING_3D_FORMAT_INBAND_FA ||
2525 timing_3d_format == TIMING_3D_FORMAT_DP_HDMI_INBAND_FA ||
2526 timing_3d_format == TIMING_3D_FORMAT_SIDEBAND_FA) {
2527 enum display_dongle_type dongle = \
2528 stream->sink->link->ddc->dongle_type;
2529 if (dongle == DISPLAY_DONGLE_DP_VGA_CONVERTER ||
2530 dongle == DISPLAY_DONGLE_DP_DVI_CONVERTER ||
2531 dongle == DISPLAY_DONGLE_DP_HDMI_CONVERTER)
2532 flags->DISABLE_STEREO_DP_SYNC = 1;
2534 flags->RIGHT_EYE_POLARITY =\
2535 stream->timing.flags.RIGHT_EYE_3D_POLARITY;
2536 if (timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
2537 flags->FRAME_PACKED = 1;
2543 static void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct dc *dc)
2545 struct crtc_stereo_flags flags = { 0 };
2546 struct dc_stream_state *stream = pipe_ctx->stream;
2548 dcn10_config_stereo_parameters(stream, &flags);
2550 pipe_ctx->stream_res.opp->funcs->opp_program_stereo(
2551 pipe_ctx->stream_res.opp,
2552 flags.PROGRAM_STEREO == 1 ? true:false,
2555 pipe_ctx->stream_res.tg->funcs->program_stereo(
2556 pipe_ctx->stream_res.tg,
2563 static struct hubp *get_hubp_by_inst(struct resource_pool *res_pool, int mpcc_inst)
2567 for (i = 0; i < res_pool->pipe_count; i++) {
2568 if (res_pool->hubps[i]->inst == mpcc_inst)
2569 return res_pool->hubps[i];
2575 static void dcn10_wait_for_mpcc_disconnect(
2577 struct resource_pool *res_pool,
2578 struct pipe_ctx *pipe_ctx)
2582 if (dc->debug.sanity_checks) {
2583 dcn10_verify_allow_pstate_change_high(dc);
2586 if (!pipe_ctx->stream_res.opp)
2589 for (mpcc_inst = 0; mpcc_inst < MAX_PIPES; mpcc_inst++) {
2590 if (pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst]) {
2591 struct hubp *hubp = get_hubp_by_inst(res_pool, mpcc_inst);
2593 res_pool->mpc->funcs->wait_for_idle(res_pool->mpc, mpcc_inst);
2594 pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst] = false;
2595 hubp->funcs->set_blank(hubp, true);
2596 /*DC_LOG_ERROR(dc->ctx->logger,
2597 "[debug_mpo: wait_for_mpcc finished waiting on mpcc %d]\n",
2602 if (dc->debug.sanity_checks) {
2603 dcn10_verify_allow_pstate_change_high(dc);
2608 static bool dcn10_dummy_display_power_gating(
2610 uint8_t controller_id,
2611 struct dc_bios *dcb,
2612 enum pipe_gating_control power_gating)
2617 static void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx)
2619 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2620 struct timing_generator *tg = pipe_ctx->stream_res.tg;
2623 if (plane_state == NULL)
2626 flip_pending = pipe_ctx->plane_res.hubp->funcs->hubp_is_flip_pending(
2627 pipe_ctx->plane_res.hubp);
2629 plane_state->status.is_flip_pending = flip_pending;
2632 plane_state->status.current_address = plane_state->status.requested_address;
2634 if (plane_state->status.current_address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
2635 tg->funcs->is_stereo_left_eye) {
2636 plane_state->status.is_right_eye =
2637 !tg->funcs->is_stereo_left_eye(pipe_ctx->stream_res.tg);
2641 static void dcn10_update_dchub(struct dce_hwseq *hws, struct dchub_init_data *dh_data)
2643 if (hws->ctx->dc->res_pool->hubbub != NULL) {
2644 struct hubp *hubp = hws->ctx->dc->res_pool->hubps[0];
2646 if (hubp->funcs->hubp_update_dchub)
2647 hubp->funcs->hubp_update_dchub(hubp, dh_data);
2649 hubbub1_update_dchub(hws->ctx->dc->res_pool->hubbub, dh_data);
2653 static void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx)
2655 struct dc_cursor_position pos_cpy = pipe_ctx->stream->cursor_position;
2656 struct hubp *hubp = pipe_ctx->plane_res.hubp;
2657 struct dpp *dpp = pipe_ctx->plane_res.dpp;
2658 struct dc_cursor_mi_param param = {
2659 .pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_khz,
2660 .ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clock_inKhz,
2661 .viewport = pipe_ctx->plane_res.scl_data.viewport,
2662 .h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz,
2663 .v_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.vert,
2664 .rotation = pipe_ctx->plane_state->rotation,
2665 .mirror = pipe_ctx->plane_state->horizontal_mirror
2668 pos_cpy.x -= pipe_ctx->plane_state->dst_rect.x;
2669 pos_cpy.y -= pipe_ctx->plane_state->dst_rect.y;
2671 if (pipe_ctx->plane_state->address.type
2672 == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
2673 pos_cpy.enable = false;
2675 hubp->funcs->set_cursor_position(hubp, &pos_cpy, ¶m);
2676 dpp->funcs->set_cursor_position(dpp, &pos_cpy, ¶m, hubp->curs_attr.width, hubp->curs_attr.height);
2679 static void dcn10_set_cursor_attribute(struct pipe_ctx *pipe_ctx)
2681 struct dc_cursor_attributes *attributes = &pipe_ctx->stream->cursor_attributes;
2683 pipe_ctx->plane_res.hubp->funcs->set_cursor_attributes(
2684 pipe_ctx->plane_res.hubp, attributes);
2685 pipe_ctx->plane_res.dpp->funcs->set_cursor_attributes(
2686 pipe_ctx->plane_res.dpp, attributes->color_format);
2689 static void dcn10_set_cursor_sdr_white_level(struct pipe_ctx *pipe_ctx)
2691 uint32_t sdr_white_level = pipe_ctx->stream->cursor_attributes.sdr_white_level;
2692 struct fixed31_32 multiplier;
2693 struct dpp_cursor_attributes opt_attr = { 0 };
2694 uint32_t hw_scale = 0x3c00; // 1.0 default multiplier
2695 struct custom_float_format fmt;
2697 if (!pipe_ctx->plane_res.dpp->funcs->set_optional_cursor_attributes)
2700 fmt.exponenta_bits = 5;
2701 fmt.mantissa_bits = 10;
2704 if (sdr_white_level > 80) {
2705 multiplier = dc_fixpt_from_fraction(sdr_white_level, 80);
2706 convert_to_custom_float_format(multiplier, &fmt, &hw_scale);
2709 opt_attr.scale = hw_scale;
2712 pipe_ctx->plane_res.dpp->funcs->set_optional_cursor_attributes(
2713 pipe_ctx->plane_res.dpp, &opt_attr);
2716 static const struct hw_sequencer_funcs dcn10_funcs = {
2717 .program_gamut_remap = program_gamut_remap,
2718 .init_hw = dcn10_init_hw,
2719 .apply_ctx_to_hw = dce110_apply_ctx_to_hw,
2720 .apply_ctx_for_surface = dcn10_apply_ctx_for_surface,
2721 .update_plane_addr = dcn10_update_plane_addr,
2722 .plane_atomic_disconnect = hwss1_plane_atomic_disconnect,
2723 .update_dchub = dcn10_update_dchub,
2724 .update_mpcc = dcn10_update_mpcc,
2725 .update_pending_status = dcn10_update_pending_status,
2726 .set_input_transfer_func = dcn10_set_input_transfer_func,
2727 .set_output_transfer_func = dcn10_set_output_transfer_func,
2728 .program_output_csc = dcn10_program_output_csc,
2729 .power_down = dce110_power_down,
2730 .enable_accelerated_mode = dce110_enable_accelerated_mode,
2731 .enable_timing_synchronization = dcn10_enable_timing_synchronization,
2732 .enable_per_frame_crtc_position_reset = dcn10_enable_per_frame_crtc_position_reset,
2733 .update_info_frame = dce110_update_info_frame,
2734 .enable_stream = dce110_enable_stream,
2735 .disable_stream = dce110_disable_stream,
2736 .unblank_stream = dce110_unblank_stream,
2737 .blank_stream = dce110_blank_stream,
2738 .enable_audio_stream = dce110_enable_audio_stream,
2739 .disable_audio_stream = dce110_disable_audio_stream,
2740 .enable_display_power_gating = dcn10_dummy_display_power_gating,
2741 .disable_plane = dcn10_disable_plane,
2742 .blank_pixel_data = dcn10_blank_pixel_data,
2743 .pipe_control_lock = dcn10_pipe_control_lock,
2744 .prepare_bandwidth = dcn10_prepare_bandwidth,
2745 .optimize_bandwidth = dcn10_optimize_bandwidth,
2746 .reset_hw_ctx_wrap = reset_hw_ctx_wrap,
2747 .enable_stream_timing = dcn10_enable_stream_timing,
2749 .get_position = get_position,
2750 .set_static_screen_control = set_static_screen_control,
2751 .setup_stereo = dcn10_setup_stereo,
2752 .set_avmute = dce110_set_avmute,
2753 .log_hw_state = dcn10_log_hw_state,
2754 .get_hw_state = dcn10_get_hw_state,
2755 .clear_status_bits = dcn10_clear_status_bits,
2756 .wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect,
2757 .edp_backlight_control = hwss_edp_backlight_control,
2758 .edp_power_control = hwss_edp_power_control,
2759 .edp_wait_for_hpd_ready = hwss_edp_wait_for_hpd_ready,
2760 .set_cursor_position = dcn10_set_cursor_position,
2761 .set_cursor_attribute = dcn10_set_cursor_attribute,
2762 .set_cursor_sdr_white_level = dcn10_set_cursor_sdr_white_level
2766 void dcn10_hw_sequencer_construct(struct dc *dc)
2768 dc->hwss = dcn10_funcs;