drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h

   1 /*
   2 * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #ifndef __DC_HWSS_DCN10_H__
  27 #define __DC_HWSS_DCN10_H__
  28
  29 #include "core_types.h"
  30 #include "hw_sequencer_private.h"
  31
  32 struct dc;
  33
  34 void dcn10_hw_sequencer_construct(struct dc *dc);
  35
  36 int dcn10_get_vupdate_offset_from_vsync(struct pipe_ctx *pipe_ctx);
  37 void dcn10_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx);
  38 enum dc_status dcn10_enable_stream_timing(
  39                 struct pipe_ctx *pipe_ctx,
  40                 struct dc_state *context,
  41                 struct dc *dc);
  42 void dcn10_optimize_bandwidth(
  43                 struct dc *dc,
  44                 struct dc_state *context);
  45 void dcn10_prepare_bandwidth(
  46                 struct dc *dc,
  47                 struct dc_state *context);
  48 void dcn10_pipe_control_lock(
  49         struct dc *dc,
  50         struct pipe_ctx *pipe,
  51         bool lock);
  52 void dcn10_blank_pixel_data(
  53                 struct dc *dc,
  54                 struct pipe_ctx *pipe_ctx,
  55                 bool blank);
  56 void dcn10_unblank_stream(struct pipe_ctx *pipe_ctx,
  57                 struct dc_link_settings *link_settings);
  58 void dcn10_program_output_csc(struct dc *dc,
  59                 struct pipe_ctx *pipe_ctx,
  60                 enum dc_color_space colorspace,
  61                 uint16_t *matrix,
  62                 int opp_id);
  63 bool dcn10_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
  64                                 const struct dc_stream_state *stream);
  65 bool dcn10_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
  66                         const struct dc_plane_state *plane_state);
  67 void dcn10_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx);
  68 void dcn10_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx);
  69 void dcn10_reset_hw_ctx_wrap(
  70                 struct dc *dc,
  71                 struct dc_state *context);
  72 void dcn10_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx);
  73 void dcn10_lock_all_pipes(
  74                 struct dc *dc,
  75                 struct dc_state *context,
  76                 bool lock);
  77 void dcn10_apply_ctx_for_surface(
  78                 struct dc *dc,
  79                 const struct dc_stream_state *stream,
  80                 int num_planes,
  81                 struct dc_state *context);
  82 void dcn10_post_unlock_program_front_end(
  83                 struct dc *dc,
  84                 struct dc_state *context);
  85 void dcn10_hubp_pg_control(
  86                 struct dce_hwseq *hws,
  87                 unsigned int hubp_inst,
  88                 bool power_on);
  89 void dcn10_dpp_pg_control(
  90                 struct dce_hwseq *hws,
  91                 unsigned int dpp_inst,
  92                 bool power_on);
  93 void dcn10_enable_power_gating_plane(
  94         struct dce_hwseq *hws,
  95         bool enable);
  96 void dcn10_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx);
  97 void dcn10_disable_vga(
  98         struct dce_hwseq *hws);
  99 void dcn10_program_pipe(
 100                 struct dc *dc,
 101                 struct pipe_ctx *pipe_ctx,
 102                 struct dc_state *context);
 103 void dcn10_program_gamut_remap(struct pipe_ctx *pipe_ctx);
 104 void dcn10_init_hw(struct dc *dc);
 105 void dcn10_init_pipes(struct dc *dc, struct dc_state *context);
 106 enum dc_status dce110_apply_ctx_to_hw(
 107                 struct dc *dc,
 108                 struct dc_state *context);
 109 void dcn10_plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx);
 110 void dcn10_update_dchub(struct dce_hwseq *hws, struct dchub_init_data *dh_data);
 111 void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx);
 112 void dce110_power_down(struct dc *dc);
 113 void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context);
 114 void dcn10_enable_timing_synchronization(
 115                 struct dc *dc,
 116                 int group_index,
 117                 int group_size,
 118                 struct pipe_ctx *grouped_pipes[]);
 119 void dcn10_enable_per_frame_crtc_position_reset(
 120                 struct dc *dc,
 121                 int group_size,
 122                 struct pipe_ctx *grouped_pipes[]);
 123 void dce110_update_info_frame(struct pipe_ctx *pipe_ctx);
 124 void dcn10_send_immediate_sdp_message(struct pipe_ctx *pipe_ctx,
 125                 const uint8_t *custom_sdp_message,
 126                 unsigned int sdp_message_size);
 127 void dce110_blank_stream(struct pipe_ctx *pipe_ctx);
 128 void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx);
 129 void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx);
 130 bool dcn10_dummy_display_power_gating(
 131                 struct dc *dc,
 132                 uint8_t controller_id,
 133                 struct dc_bios *dcb,
 134                 enum pipe_gating_control power_gating);
 135 void dcn10_set_drr(struct pipe_ctx **pipe_ctx,
 136                 int num_pipes, unsigned int vmin, unsigned int vmax,
 137                 unsigned int vmid, unsigned int vmid_frame_number);
 138 void dcn10_get_position(struct pipe_ctx **pipe_ctx,
 139                 int num_pipes,
 140                 struct crtc_position *position);
 141 void dcn10_set_static_screen_control(struct pipe_ctx **pipe_ctx,
 142                 int num_pipes, const struct dc_static_screen_params *params);
 143 void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct dc *dc);
 144 void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool enable);
 145 void dcn10_log_hw_state(struct dc *dc,
 146                 struct dc_log_buffer_ctx *log_ctx);
 147 void dcn10_get_hw_state(struct dc *dc,
 148                 char *pBuf,
 149                 unsigned int bufSize,
 150                 unsigned int mask);
 151 void dcn10_clear_status_bits(struct dc *dc, unsigned int mask);
 152 void dcn10_wait_for_mpcc_disconnect(
 153                 struct dc *dc,
 154                 struct resource_pool *res_pool,
 155                 struct pipe_ctx *pipe_ctx);
 156 void dce110_edp_backlight_control(
 157                 struct dc_link *link,
 158                 bool enable);
 159 void dce110_edp_power_control(
 160                 struct dc_link *link,
 161                 bool power_up);
 162 void dce110_edp_wait_for_hpd_ready(
 163                 struct dc_link *link,
 164                 bool power_up);
 165 void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx);
 166 void dcn10_set_cursor_attribute(struct pipe_ctx *pipe_ctx);
 167 void dcn10_set_cursor_sdr_white_level(struct pipe_ctx *pipe_ctx);
 168 void dcn10_setup_periodic_interrupt(
 169                 struct dc *dc,
 170                 struct pipe_ctx *pipe_ctx,
 171                 enum vline_select vline);
 172 enum dc_status dcn10_set_clock(struct dc *dc,
 173                 enum dc_clock_type clock_type,
 174                 uint32_t clk_khz,
 175                 uint32_t stepping);
 176 void dcn10_get_clock(struct dc *dc,
 177                 enum dc_clock_type clock_type,
 178                 struct dc_clock_config *clock_cfg);
 179 bool dcn10_did_underflow_occur(struct dc *dc, struct pipe_ctx *pipe_ctx);
 180 void dcn10_bios_golden_init(struct dc *dc);
 181 void dcn10_plane_atomic_power_down(struct dc *dc,
 182                 struct dpp *dpp,
 183                 struct hubp *hubp);
 184 void dcn10_get_surface_visual_confirm_color(
 185                 const struct pipe_ctx *pipe_ctx,
 186                 struct tg_color *color);
 187 void dcn10_get_hdr_visual_confirm_color(
 188                 struct pipe_ctx *pipe_ctx,
 189                 struct tg_color *color);
 190 void dcn10_set_hdr_multiplier(struct pipe_ctx *pipe_ctx);
 191 void dcn10_verify_allow_pstate_change_high(struct dc *dc);
 192
 193 #endif /* __DC_HWSS_DCN10_H__ */