drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c

   1 /*
   2 * Copyright 2016 Advanced Micro Devices, Inc.
   3  * Copyright 2019 Raptor Engineering, LLC
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: AMD
  24  *
  25  */
  26
  27 #include <linux/slab.h>
  28
  29 #include "dm_services.h"
  30 #include "dc.h"
  31
  32 #include "dcn20_init.h"
  33
  34 #include "resource.h"
  35 #include "include/irq_service_interface.h"
  36 #include "dcn20/dcn20_resource.h"
  37
  38 #include "dcn10/dcn10_hubp.h"
  39 #include "dcn10/dcn10_ipp.h"
  40 #include "dcn20_hubbub.h"
  41 #include "dcn20_mpc.h"
  42 #include "dcn20_hubp.h"
  43 #include "irq/dcn20/irq_service_dcn20.h"
  44 #include "dcn20_dpp.h"
  45 #include "dcn20_optc.h"
  46 #include "dcn20_hwseq.h"
  47 #include "dce110/dce110_hw_sequencer.h"
  48 #include "dcn10/dcn10_resource.h"
  49 #include "dcn20_opp.h"
  50
  51 #include "dcn20_dsc.h"
  52
  53 #include "dcn20_link_encoder.h"
  54 #include "dcn20_stream_encoder.h"
  55 #include "dce/dce_clock_source.h"
  56 #include "dce/dce_audio.h"
  57 #include "dce/dce_hwseq.h"
  58 #include "virtual/virtual_stream_encoder.h"
  59 #include "dce110/dce110_resource.h"
  60 #include "dml/display_mode_vba.h"
  61 #include "dcn20_dccg.h"
  62 #include "dcn20_vmid.h"
  63 #include "dc_link_ddc.h"
  64
  65 #include "navi10_ip_offset.h"
  66
  67 #include "dcn/dcn_2_0_0_offset.h"
  68 #include "dcn/dcn_2_0_0_sh_mask.h"
  69 #include "dpcs/dpcs_2_0_0_offset.h"
  70 #include "dpcs/dpcs_2_0_0_sh_mask.h"
  71
  72 #include "nbio/nbio_2_3_offset.h"
  73
  74 #include "dcn20/dcn20_dwb.h"
  75 #include "dcn20/dcn20_mmhubbub.h"
  76
  77 #include "mmhub/mmhub_2_0_0_offset.h"
  78 #include "mmhub/mmhub_2_0_0_sh_mask.h"
  79
  80 #include "reg_helper.h"
  81 #include "dce/dce_abm.h"
  82 #include "dce/dce_dmcu.h"
  83 #include "dce/dce_aux.h"
  84 #include "dce/dce_i2c.h"
  85 #include "vm_helper.h"
  86
  87 #include "amdgpu_socbb.h"
  88
  89 #define DC_LOGGER_INIT(logger)
  90
  91 struct _vcs_dpi_ip_params_st dcn2_0_ip = {
  92         .odm_capable = 1,
  93         .gpuvm_enable = 0,
  94         .hostvm_enable = 0,
  95         .gpuvm_max_page_table_levels = 4,
  96         .hostvm_max_page_table_levels = 4,
  97         .hostvm_cached_page_table_levels = 0,
  98         .pte_group_size_bytes = 2048,
  99         .num_dsc = 6,
 100         .rob_buffer_size_kbytes = 168,
 101         .det_buffer_size_kbytes = 164,
 102         .dpte_buffer_size_in_pte_reqs_luma = 84,
 103         .pde_proc_buffer_size_64k_reqs = 48,
 104         .dpp_output_buffer_pixels = 2560,
 105         .opp_output_buffer_lines = 1,
 106         .pixel_chunk_size_kbytes = 8,
 107         .pte_chunk_size_kbytes = 2,
 108         .meta_chunk_size_kbytes = 2,
 109         .writeback_chunk_size_kbytes = 2,
 110         .line_buffer_size_bits = 789504,
 111         .is_line_buffer_bpp_fixed = 0,
 112         .line_buffer_fixed_bpp = 0,
 113         .dcc_supported = true,
 114         .max_line_buffer_lines = 12,
 115         .writeback_luma_buffer_size_kbytes = 12,
 116         .writeback_chroma_buffer_size_kbytes = 8,
 117         .writeback_chroma_line_buffer_width_pixels = 4,
 118         .writeback_max_hscl_ratio = 1,
 119         .writeback_max_vscl_ratio = 1,
 120         .writeback_min_hscl_ratio = 1,
 121         .writeback_min_vscl_ratio = 1,
 122         .writeback_max_hscl_taps = 12,
 123         .writeback_max_vscl_taps = 12,
 124         .writeback_line_buffer_luma_buffer_size = 0,
 125         .writeback_line_buffer_chroma_buffer_size = 14643,
 126         .cursor_buffer_size = 8,
 127         .cursor_chunk_size = 2,
 128         .max_num_otg = 6,
 129         .max_num_dpp = 6,
 130         .max_num_wb = 1,
 131         .max_dchub_pscl_bw_pix_per_clk = 4,
 132         .max_pscl_lb_bw_pix_per_clk = 2,
 133         .max_lb_vscl_bw_pix_per_clk = 4,
 134         .max_vscl_hscl_bw_pix_per_clk = 4,
 135         .max_hscl_ratio = 8,
 136         .max_vscl_ratio = 8,
 137         .hscl_mults = 4,
 138         .vscl_mults = 4,
 139         .max_hscl_taps = 8,
 140         .max_vscl_taps = 8,
 141         .dispclk_ramp_margin_percent = 1,
 142         .underscan_factor = 1.10,
 143         .min_vblank_lines = 32, //
 144         .dppclk_delay_subtotal = 77, //
 145         .dppclk_delay_scl_lb_only = 16,
 146         .dppclk_delay_scl = 50,
 147         .dppclk_delay_cnvc_formatter = 8,
 148         .dppclk_delay_cnvc_cursor = 6,
 149         .dispclk_delay_subtotal = 87, //
 150         .dcfclk_cstate_latency = 10, // SRExitTime
 151         .max_inter_dcn_tile_repeaters = 8,
 152
 153         .xfc_supported = true,
 154         .xfc_fill_bw_overhead_percent = 10.0,
 155         .xfc_fill_constant_bytes = 0,
 156 };
 157
 158 struct _vcs_dpi_ip_params_st dcn2_0_nv14_ip = {
 159         .odm_capable = 1,
 160         .gpuvm_enable = 0,
 161         .hostvm_enable = 0,
 162         .gpuvm_max_page_table_levels = 4,
 163         .hostvm_max_page_table_levels = 4,
 164         .hostvm_cached_page_table_levels = 0,
 165         .num_dsc = 5,
 166         .rob_buffer_size_kbytes = 168,
 167         .det_buffer_size_kbytes = 164,
 168         .dpte_buffer_size_in_pte_reqs_luma = 84,
 169         .dpte_buffer_size_in_pte_reqs_chroma = 42,//todo
 170         .dpp_output_buffer_pixels = 2560,
 171         .opp_output_buffer_lines = 1,
 172         .pixel_chunk_size_kbytes = 8,
 173         .pte_enable = 1,
 174         .max_page_table_levels = 4,
 175         .pte_chunk_size_kbytes = 2,
 176         .meta_chunk_size_kbytes = 2,
 177         .writeback_chunk_size_kbytes = 2,
 178         .line_buffer_size_bits = 789504,
 179         .is_line_buffer_bpp_fixed = 0,
 180         .line_buffer_fixed_bpp = 0,
 181         .dcc_supported = true,
 182         .max_line_buffer_lines = 12,
 183         .writeback_luma_buffer_size_kbytes = 12,
 184         .writeback_chroma_buffer_size_kbytes = 8,
 185         .writeback_chroma_line_buffer_width_pixels = 4,
 186         .writeback_max_hscl_ratio = 1,
 187         .writeback_max_vscl_ratio = 1,
 188         .writeback_min_hscl_ratio = 1,
 189         .writeback_min_vscl_ratio = 1,
 190         .writeback_max_hscl_taps = 12,
 191         .writeback_max_vscl_taps = 12,
 192         .writeback_line_buffer_luma_buffer_size = 0,
 193         .writeback_line_buffer_chroma_buffer_size = 14643,
 194         .cursor_buffer_size = 8,
 195         .cursor_chunk_size = 2,
 196         .max_num_otg = 5,
 197         .max_num_dpp = 5,
 198         .max_num_wb = 1,
 199         .max_dchub_pscl_bw_pix_per_clk = 4,
 200         .max_pscl_lb_bw_pix_per_clk = 2,
 201         .max_lb_vscl_bw_pix_per_clk = 4,
 202         .max_vscl_hscl_bw_pix_per_clk = 4,
 203         .max_hscl_ratio = 8,
 204         .max_vscl_ratio = 8,
 205         .hscl_mults = 4,
 206         .vscl_mults = 4,
 207         .max_hscl_taps = 8,
 208         .max_vscl_taps = 8,
 209         .dispclk_ramp_margin_percent = 1,
 210         .underscan_factor = 1.10,
 211         .min_vblank_lines = 32, //
 212         .dppclk_delay_subtotal = 77, //
 213         .dppclk_delay_scl_lb_only = 16,
 214         .dppclk_delay_scl = 50,
 215         .dppclk_delay_cnvc_formatter = 8,
 216         .dppclk_delay_cnvc_cursor = 6,
 217         .dispclk_delay_subtotal = 87, //
 218         .dcfclk_cstate_latency = 10, // SRExitTime
 219         .max_inter_dcn_tile_repeaters = 8,
 220         .xfc_supported = true,
 221         .xfc_fill_bw_overhead_percent = 10.0,
 222         .xfc_fill_constant_bytes = 0,
 223         .ptoi_supported = 0
 224 };
 225
 226 struct _vcs_dpi_soc_bounding_box_st dcn2_0_soc = {
 227         /* Defaults that get patched on driver load from firmware. */
 228         .clock_limits = {
 229                         {
 230                                 .state = 0,
 231                                 .dcfclk_mhz = 560.0,
 232                                 .fabricclk_mhz = 560.0,
 233                                 .dispclk_mhz = 513.0,
 234                                 .dppclk_mhz = 513.0,
 235                                 .phyclk_mhz = 540.0,
 236                                 .socclk_mhz = 560.0,
 237                                 .dscclk_mhz = 171.0,
 238                                 .dram_speed_mts = 8960.0,
 239                         },
 240                         {
 241                                 .state = 1,
 242                                 .dcfclk_mhz = 694.0,
 243                                 .fabricclk_mhz = 694.0,
 244                                 .dispclk_mhz = 642.0,
 245                                 .dppclk_mhz = 642.0,
 246                                 .phyclk_mhz = 600.0,
 247                                 .socclk_mhz = 694.0,
 248                                 .dscclk_mhz = 214.0,
 249                                 .dram_speed_mts = 11104.0,
 250                         },
 251                         {
 252                                 .state = 2,
 253                                 .dcfclk_mhz = 875.0,
 254                                 .fabricclk_mhz = 875.0,
 255                                 .dispclk_mhz = 734.0,
 256                                 .dppclk_mhz = 734.0,
 257                                 .phyclk_mhz = 810.0,
 258                                 .socclk_mhz = 875.0,
 259                                 .dscclk_mhz = 245.0,
 260                                 .dram_speed_mts = 14000.0,
 261                         },
 262                         {
 263                                 .state = 3,
 264                                 .dcfclk_mhz = 1000.0,
 265                                 .fabricclk_mhz = 1000.0,
 266                                 .dispclk_mhz = 1100.0,
 267                                 .dppclk_mhz = 1100.0,
 268                                 .phyclk_mhz = 810.0,
 269                                 .socclk_mhz = 1000.0,
 270                                 .dscclk_mhz = 367.0,
 271                                 .dram_speed_mts = 16000.0,
 272                         },
 273                         {
 274                                 .state = 4,
 275                                 .dcfclk_mhz = 1200.0,
 276                                 .fabricclk_mhz = 1200.0,
 277                                 .dispclk_mhz = 1284.0,
 278                                 .dppclk_mhz = 1284.0,
 279                                 .phyclk_mhz = 810.0,
 280                                 .socclk_mhz = 1200.0,
 281                                 .dscclk_mhz = 428.0,
 282                                 .dram_speed_mts = 16000.0,
 283                         },
 284                         /*Extra state, no dispclk ramping*/
 285                         {
 286                                 .state = 5,
 287                                 .dcfclk_mhz = 1200.0,
 288                                 .fabricclk_mhz = 1200.0,
 289                                 .dispclk_mhz = 1284.0,
 290                                 .dppclk_mhz = 1284.0,
 291                                 .phyclk_mhz = 810.0,
 292                                 .socclk_mhz = 1200.0,
 293                                 .dscclk_mhz = 428.0,
 294                                 .dram_speed_mts = 16000.0,
 295                         },
 296                 },
 297         .num_states = 5,
 298         .sr_exit_time_us = 8.6,
 299         .sr_enter_plus_exit_time_us = 10.9,
 300         .urgent_latency_us = 4.0,
 301         .urgent_latency_pixel_data_only_us = 4.0,
 302         .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
 303         .urgent_latency_vm_data_only_us = 4.0,
 304         .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
 305         .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
 306         .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
 307         .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 40.0,
 308         .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 40.0,
 309         .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
 310         .max_avg_sdp_bw_use_normal_percent = 40.0,
 311         .max_avg_dram_bw_use_normal_percent = 40.0,
 312         .writeback_latency_us = 12.0,
 313         .ideal_dram_bw_after_urgent_percent = 40.0,
 314         .max_request_size_bytes = 256,
 315         .dram_channel_width_bytes = 2,
 316         .fabric_datapath_to_dcn_data_return_bytes = 64,
 317         .dcn_downspread_percent = 0.5,
 318         .downspread_percent = 0.38,
 319         .dram_page_open_time_ns = 50.0,
 320         .dram_rw_turnaround_time_ns = 17.5,
 321         .dram_return_buffer_per_channel_bytes = 8192,
 322         .round_trip_ping_latency_dcfclk_cycles = 131,
 323         .urgent_out_of_order_return_per_channel_bytes = 256,
 324         .channel_interleave_bytes = 256,
 325         .num_banks = 8,
 326         .num_chans = 16,
 327         .vmm_page_size_bytes = 4096,
 328         .dram_clock_change_latency_us = 404.0,
 329         .dummy_pstate_latency_us = 5.0,
 330         .writeback_dram_clock_change_latency_us = 23.0,
 331         .return_bus_width_bytes = 64,
 332         .dispclk_dppclk_vco_speed_mhz = 3850,
 333         .xfc_bus_transport_time_us = 20,
 334         .xfc_xbuf_latency_tolerance_us = 4,
 335         .use_urgent_burst_bw = 0
 336 };
 337
 338 struct _vcs_dpi_soc_bounding_box_st dcn2_0_nv14_soc = {
 339         .clock_limits = {
 340                         {
 341                                 .state = 0,
 342                                 .dcfclk_mhz = 560.0,
 343                                 .fabricclk_mhz = 560.0,
 344                                 .dispclk_mhz = 513.0,
 345                                 .dppclk_mhz = 513.0,
 346                                 .phyclk_mhz = 540.0,
 347                                 .socclk_mhz = 560.0,
 348                                 .dscclk_mhz = 171.0,
 349                                 .dram_speed_mts = 8960.0,
 350                         },
 351                         {
 352                                 .state = 1,
 353                                 .dcfclk_mhz = 694.0,
 354                                 .fabricclk_mhz = 694.0,
 355                                 .dispclk_mhz = 642.0,
 356                                 .dppclk_mhz = 642.0,
 357                                 .phyclk_mhz = 600.0,
 358                                 .socclk_mhz = 694.0,
 359                                 .dscclk_mhz = 214.0,
 360                                 .dram_speed_mts = 11104.0,
 361                         },
 362                         {
 363                                 .state = 2,
 364                                 .dcfclk_mhz = 875.0,
 365                                 .fabricclk_mhz = 875.0,
 366                                 .dispclk_mhz = 734.0,
 367                                 .dppclk_mhz = 734.0,
 368                                 .phyclk_mhz = 810.0,
 369                                 .socclk_mhz = 875.0,
 370                                 .dscclk_mhz = 245.0,
 371                                 .dram_speed_mts = 14000.0,
 372                         },
 373                         {
 374                                 .state = 3,
 375                                 .dcfclk_mhz = 1000.0,
 376                                 .fabricclk_mhz = 1000.0,
 377                                 .dispclk_mhz = 1100.0,
 378                                 .dppclk_mhz = 1100.0,
 379                                 .phyclk_mhz = 810.0,
 380                                 .socclk_mhz = 1000.0,
 381                                 .dscclk_mhz = 367.0,
 382                                 .dram_speed_mts = 16000.0,
 383                         },
 384                         {
 385                                 .state = 4,
 386                                 .dcfclk_mhz = 1200.0,
 387                                 .fabricclk_mhz = 1200.0,
 388                                 .dispclk_mhz = 1284.0,
 389                                 .dppclk_mhz = 1284.0,
 390                                 .phyclk_mhz = 810.0,
 391                                 .socclk_mhz = 1200.0,
 392                                 .dscclk_mhz = 428.0,
 393                                 .dram_speed_mts = 16000.0,
 394                         },
 395                         /*Extra state, no dispclk ramping*/
 396                         {
 397                                 .state = 5,
 398                                 .dcfclk_mhz = 1200.0,
 399                                 .fabricclk_mhz = 1200.0,
 400                                 .dispclk_mhz = 1284.0,
 401                                 .dppclk_mhz = 1284.0,
 402                                 .phyclk_mhz = 810.0,
 403                                 .socclk_mhz = 1200.0,
 404                                 .dscclk_mhz = 428.0,
 405                                 .dram_speed_mts = 16000.0,
 406                         },
 407                 },
 408         .num_states = 5,
 409         .sr_exit_time_us = 8.6,
 410         .sr_enter_plus_exit_time_us = 10.9,
 411         .urgent_latency_us = 4.0,
 412         .urgent_latency_pixel_data_only_us = 4.0,
 413         .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
 414         .urgent_latency_vm_data_only_us = 4.0,
 415         .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
 416         .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
 417         .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
 418         .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 40.0,
 419         .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 40.0,
 420         .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
 421         .max_avg_sdp_bw_use_normal_percent = 40.0,
 422         .max_avg_dram_bw_use_normal_percent = 40.0,
 423         .writeback_latency_us = 12.0,
 424         .ideal_dram_bw_after_urgent_percent = 40.0,
 425         .max_request_size_bytes = 256,
 426         .dram_channel_width_bytes = 2,
 427         .fabric_datapath_to_dcn_data_return_bytes = 64,
 428         .dcn_downspread_percent = 0.5,
 429         .downspread_percent = 0.38,
 430         .dram_page_open_time_ns = 50.0,
 431         .dram_rw_turnaround_time_ns = 17.5,
 432         .dram_return_buffer_per_channel_bytes = 8192,
 433         .round_trip_ping_latency_dcfclk_cycles = 131,
 434         .urgent_out_of_order_return_per_channel_bytes = 256,
 435         .channel_interleave_bytes = 256,
 436         .num_banks = 8,
 437         .num_chans = 8,
 438         .vmm_page_size_bytes = 4096,
 439         .dram_clock_change_latency_us = 404.0,
 440         .dummy_pstate_latency_us = 5.0,
 441         .writeback_dram_clock_change_latency_us = 23.0,
 442         .return_bus_width_bytes = 64,
 443         .dispclk_dppclk_vco_speed_mhz = 3850,
 444         .xfc_bus_transport_time_us = 20,
 445         .xfc_xbuf_latency_tolerance_us = 4,
 446         .use_urgent_burst_bw = 0
 447 };
 448
 449 struct _vcs_dpi_soc_bounding_box_st dcn2_0_nv12_soc = { 0 };
 450
 451 #ifndef mmDP0_DP_DPHY_INTERNAL_CTRL
 452         #define mmDP0_DP_DPHY_INTERNAL_CTRL             0x210f
 453         #define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX    2
 454         #define mmDP1_DP_DPHY_INTERNAL_CTRL             0x220f
 455         #define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX    2
 456         #define mmDP2_DP_DPHY_INTERNAL_CTRL             0x230f
 457         #define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX    2
 458         #define mmDP3_DP_DPHY_INTERNAL_CTRL             0x240f
 459         #define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX    2
 460         #define mmDP4_DP_DPHY_INTERNAL_CTRL             0x250f
 461         #define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX    2
 462         #define mmDP5_DP_DPHY_INTERNAL_CTRL             0x260f
 463         #define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX    2
 464         #define mmDP6_DP_DPHY_INTERNAL_CTRL             0x270f
 465         #define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX    2
 466 #endif
 467
 468
 469 enum dcn20_clk_src_array_id {
 470         DCN20_CLK_SRC_PLL0,
 471         DCN20_CLK_SRC_PLL1,
 472         DCN20_CLK_SRC_PLL2,
 473         DCN20_CLK_SRC_PLL3,
 474         DCN20_CLK_SRC_PLL4,
 475         DCN20_CLK_SRC_PLL5,
 476         DCN20_CLK_SRC_TOTAL
 477 };
 478
 479 /* begin *********************
 480  * macros to expend register list macro defined in HW object header file */
 481
 482 /* DCN */
 483 /* TODO awful hack. fixup dcn20_dwb.h */
 484 #undef BASE_INNER
 485 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
 486
 487 #define BASE(seg) BASE_INNER(seg)
 488
 489 #define SR(reg_name)\
 490                 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) +  \
 491                                         mm ## reg_name
 492
 493 #define SRI(reg_name, block, id)\
 494         .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 495                                         mm ## block ## id ## _ ## reg_name
 496
 497 #define SRIR(var_name, reg_name, block, id)\
 498         .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 499                                         mm ## block ## id ## _ ## reg_name
 500
 501 #define SRII(reg_name, block, id)\
 502         .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 503                                         mm ## block ## id ## _ ## reg_name
 504
 505 #define DCCG_SRII(reg_name, block, id)\
 506         .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 507                                         mm ## block ## id ## _ ## reg_name
 508
 509 /* NBIO */
 510 #define NBIO_BASE_INNER(seg) \
 511         NBIO_BASE__INST0_SEG ## seg
 512
 513 #define NBIO_BASE(seg) \
 514         NBIO_BASE_INNER(seg)
 515
 516 #define NBIO_SR(reg_name)\
 517                 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
 518                                         mm ## reg_name
 519
 520 /* MMHUB */
 521 #define MMHUB_BASE_INNER(seg) \
 522         MMHUB_BASE__INST0_SEG ## seg
 523
 524 #define MMHUB_BASE(seg) \
 525         MMHUB_BASE_INNER(seg)
 526
 527 #define MMHUB_SR(reg_name)\
 528                 .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \
 529                                         mmMM ## reg_name
 530
 531 static const struct bios_registers bios_regs = {
 532                 NBIO_SR(BIOS_SCRATCH_3),
 533                 NBIO_SR(BIOS_SCRATCH_6)
 534 };
 535
 536 #define clk_src_regs(index, pllid)\
 537 [index] = {\
 538         CS_COMMON_REG_LIST_DCN2_0(index, pllid),\
 539 }
 540
 541 static const struct dce110_clk_src_regs clk_src_regs[] = {
 542         clk_src_regs(0, A),
 543         clk_src_regs(1, B),
 544         clk_src_regs(2, C),
 545         clk_src_regs(3, D),
 546         clk_src_regs(4, E),
 547         clk_src_regs(5, F)
 548 };
 549
 550 static const struct dce110_clk_src_shift cs_shift = {
 551                 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
 552 };
 553
 554 static const struct dce110_clk_src_mask cs_mask = {
 555                 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
 556 };
 557
 558 static const struct dce_dmcu_registers dmcu_regs = {
 559                 DMCU_DCN10_REG_LIST()
 560 };
 561
 562 static const struct dce_dmcu_shift dmcu_shift = {
 563                 DMCU_MASK_SH_LIST_DCN10(__SHIFT)
 564 };
 565
 566 static const struct dce_dmcu_mask dmcu_mask = {
 567                 DMCU_MASK_SH_LIST_DCN10(_MASK)
 568 };
 569
 570 static const struct dce_abm_registers abm_regs = {
 571                 ABM_DCN20_REG_LIST()
 572 };
 573
 574 static const struct dce_abm_shift abm_shift = {
 575                 ABM_MASK_SH_LIST_DCN20(__SHIFT)
 576 };
 577
 578 static const struct dce_abm_mask abm_mask = {
 579                 ABM_MASK_SH_LIST_DCN20(_MASK)
 580 };
 581
 582 #define audio_regs(id)\
 583 [id] = {\
 584                 AUD_COMMON_REG_LIST(id)\
 585 }
 586
 587 static const struct dce_audio_registers audio_regs[] = {
 588         audio_regs(0),
 589         audio_regs(1),
 590         audio_regs(2),
 591         audio_regs(3),
 592         audio_regs(4),
 593         audio_regs(5),
 594         audio_regs(6),
 595 };
 596
 597 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
 598                 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
 599                 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
 600                 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
 601
 602 static const struct dce_audio_shift audio_shift = {
 603                 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
 604 };
 605
 606 static const struct dce_audio_mask audio_mask = {
 607                 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
 608 };
 609
 610 #define stream_enc_regs(id)\
 611 [id] = {\
 612         SE_DCN2_REG_LIST(id)\
 613 }
 614
 615 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
 616         stream_enc_regs(0),
 617         stream_enc_regs(1),
 618         stream_enc_regs(2),
 619         stream_enc_regs(3),
 620         stream_enc_regs(4),
 621         stream_enc_regs(5),
 622 };
 623
 624 static const struct dcn10_stream_encoder_shift se_shift = {
 625                 SE_COMMON_MASK_SH_LIST_DCN20(__SHIFT)
 626 };
 627
 628 static const struct dcn10_stream_encoder_mask se_mask = {
 629                 SE_COMMON_MASK_SH_LIST_DCN20(_MASK)
 630 };
 631
 632
 633 #define aux_regs(id)\
 634 [id] = {\
 635         DCN2_AUX_REG_LIST(id)\
 636 }
 637
 638 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
 639                 aux_regs(0),
 640                 aux_regs(1),
 641                 aux_regs(2),
 642                 aux_regs(3),
 643                 aux_regs(4),
 644                 aux_regs(5)
 645 };
 646
 647 #define hpd_regs(id)\
 648 [id] = {\
 649         HPD_REG_LIST(id)\
 650 }
 651
 652 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
 653                 hpd_regs(0),
 654                 hpd_regs(1),
 655                 hpd_regs(2),
 656                 hpd_regs(3),
 657                 hpd_regs(4),
 658                 hpd_regs(5)
 659 };
 660
 661 #define link_regs(id, phyid)\
 662 [id] = {\
 663         LE_DCN10_REG_LIST(id), \
 664         UNIPHY_DCN2_REG_LIST(phyid), \
 665         DPCS_DCN2_REG_LIST(id), \
 666         SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
 667 }
 668
 669 static const struct dcn10_link_enc_registers link_enc_regs[] = {
 670         link_regs(0, A),
 671         link_regs(1, B),
 672         link_regs(2, C),
 673         link_regs(3, D),
 674         link_regs(4, E),
 675         link_regs(5, F)
 676 };
 677
 678 static const struct dcn10_link_enc_shift le_shift = {
 679         LINK_ENCODER_MASK_SH_LIST_DCN20(__SHIFT),\
 680         DPCS_DCN2_MASK_SH_LIST(__SHIFT)
 681 };
 682
 683 static const struct dcn10_link_enc_mask le_mask = {
 684         LINK_ENCODER_MASK_SH_LIST_DCN20(_MASK),\
 685         DPCS_DCN2_MASK_SH_LIST(_MASK)
 686 };
 687
 688 #define ipp_regs(id)\
 689 [id] = {\
 690         IPP_REG_LIST_DCN20(id),\
 691 }
 692
 693 static const struct dcn10_ipp_registers ipp_regs[] = {
 694         ipp_regs(0),
 695         ipp_regs(1),
 696         ipp_regs(2),
 697         ipp_regs(3),
 698         ipp_regs(4),
 699         ipp_regs(5),
 700 };
 701
 702 static const struct dcn10_ipp_shift ipp_shift = {
 703                 IPP_MASK_SH_LIST_DCN20(__SHIFT)
 704 };
 705
 706 static const struct dcn10_ipp_mask ipp_mask = {
 707                 IPP_MASK_SH_LIST_DCN20(_MASK),
 708 };
 709
 710 #define opp_regs(id)\
 711 [id] = {\
 712         OPP_REG_LIST_DCN20(id),\
 713 }
 714
 715 static const struct dcn20_opp_registers opp_regs[] = {
 716         opp_regs(0),
 717         opp_regs(1),
 718         opp_regs(2),
 719         opp_regs(3),
 720         opp_regs(4),
 721         opp_regs(5),
 722 };
 723
 724 static const struct dcn20_opp_shift opp_shift = {
 725                 OPP_MASK_SH_LIST_DCN20(__SHIFT)
 726 };
 727
 728 static const struct dcn20_opp_mask opp_mask = {
 729                 OPP_MASK_SH_LIST_DCN20(_MASK)
 730 };
 731
 732 #define aux_engine_regs(id)\
 733 [id] = {\
 734         AUX_COMMON_REG_LIST0(id), \
 735         .AUXN_IMPCAL = 0, \
 736         .AUXP_IMPCAL = 0, \
 737         .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
 738 }
 739
 740 static const struct dce110_aux_registers aux_engine_regs[] = {
 741                 aux_engine_regs(0),
 742                 aux_engine_regs(1),
 743                 aux_engine_regs(2),
 744                 aux_engine_regs(3),
 745                 aux_engine_regs(4),
 746                 aux_engine_regs(5)
 747 };
 748
 749 #define tf_regs(id)\
 750 [id] = {\
 751         TF_REG_LIST_DCN20(id),\
 752         TF_REG_LIST_DCN20_COMMON_APPEND(id),\
 753 }
 754
 755 static const struct dcn2_dpp_registers tf_regs[] = {
 756         tf_regs(0),
 757         tf_regs(1),
 758         tf_regs(2),
 759         tf_regs(3),
 760         tf_regs(4),
 761         tf_regs(5),
 762 };
 763
 764 static const struct dcn2_dpp_shift tf_shift = {
 765                 TF_REG_LIST_SH_MASK_DCN20(__SHIFT),
 766                 TF_DEBUG_REG_LIST_SH_DCN20
 767 };
 768
 769 static const struct dcn2_dpp_mask tf_mask = {
 770                 TF_REG_LIST_SH_MASK_DCN20(_MASK),
 771                 TF_DEBUG_REG_LIST_MASK_DCN20
 772 };
 773
 774 #define dwbc_regs_dcn2(id)\
 775 [id] = {\
 776         DWBC_COMMON_REG_LIST_DCN2_0(id),\
 777                 }
 778
 779 static const struct dcn20_dwbc_registers dwbc20_regs[] = {
 780         dwbc_regs_dcn2(0),
 781 };
 782
 783 static const struct dcn20_dwbc_shift dwbc20_shift = {
 784         DWBC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
 785 };
 786
 787 static const struct dcn20_dwbc_mask dwbc20_mask = {
 788         DWBC_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
 789 };
 790
 791 #define mcif_wb_regs_dcn2(id)\
 792 [id] = {\
 793         MCIF_WB_COMMON_REG_LIST_DCN2_0(id),\
 794                 }
 795
 796 static const struct dcn20_mmhubbub_registers mcif_wb20_regs[] = {
 797         mcif_wb_regs_dcn2(0),
 798 };
 799
 800 static const struct dcn20_mmhubbub_shift mcif_wb20_shift = {
 801         MCIF_WB_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
 802 };
 803
 804 static const struct dcn20_mmhubbub_mask mcif_wb20_mask = {
 805         MCIF_WB_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
 806 };
 807
 808 static const struct dcn20_mpc_registers mpc_regs = {
 809                 MPC_REG_LIST_DCN2_0(0),
 810                 MPC_REG_LIST_DCN2_0(1),
 811                 MPC_REG_LIST_DCN2_0(2),
 812                 MPC_REG_LIST_DCN2_0(3),
 813                 MPC_REG_LIST_DCN2_0(4),
 814                 MPC_REG_LIST_DCN2_0(5),
 815                 MPC_OUT_MUX_REG_LIST_DCN2_0(0),
 816                 MPC_OUT_MUX_REG_LIST_DCN2_0(1),
 817                 MPC_OUT_MUX_REG_LIST_DCN2_0(2),
 818                 MPC_OUT_MUX_REG_LIST_DCN2_0(3),
 819                 MPC_OUT_MUX_REG_LIST_DCN2_0(4),
 820                 MPC_OUT_MUX_REG_LIST_DCN2_0(5),
 821                 MPC_DBG_REG_LIST_DCN2_0()
 822 };
 823
 824 static const struct dcn20_mpc_shift mpc_shift = {
 825         MPC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT),
 826         MPC_DEBUG_REG_LIST_SH_DCN20
 827 };
 828
 829 static const struct dcn20_mpc_mask mpc_mask = {
 830         MPC_COMMON_MASK_SH_LIST_DCN2_0(_MASK),
 831         MPC_DEBUG_REG_LIST_MASK_DCN20
 832 };
 833
 834 #define tg_regs(id)\
 835 [id] = {TG_COMMON_REG_LIST_DCN2_0(id)}
 836
 837
 838 static const struct dcn_optc_registers tg_regs[] = {
 839         tg_regs(0),
 840         tg_regs(1),
 841         tg_regs(2),
 842         tg_regs(3),
 843         tg_regs(4),
 844         tg_regs(5)
 845 };
 846
 847 static const struct dcn_optc_shift tg_shift = {
 848         TG_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
 849 };
 850
 851 static const struct dcn_optc_mask tg_mask = {
 852         TG_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
 853 };
 854
 855 #define hubp_regs(id)\
 856 [id] = {\
 857         HUBP_REG_LIST_DCN20(id)\
 858 }
 859
 860 static const struct dcn_hubp2_registers hubp_regs[] = {
 861                 hubp_regs(0),
 862                 hubp_regs(1),
 863                 hubp_regs(2),
 864                 hubp_regs(3),
 865                 hubp_regs(4),
 866                 hubp_regs(5)
 867 };
 868
 869 static const struct dcn_hubp2_shift hubp_shift = {
 870                 HUBP_MASK_SH_LIST_DCN20(__SHIFT)
 871 };
 872
 873 static const struct dcn_hubp2_mask hubp_mask = {
 874                 HUBP_MASK_SH_LIST_DCN20(_MASK)
 875 };
 876
 877 static const struct dcn_hubbub_registers hubbub_reg = {
 878                 HUBBUB_REG_LIST_DCN20(0)
 879 };
 880
 881 static const struct dcn_hubbub_shift hubbub_shift = {
 882                 HUBBUB_MASK_SH_LIST_DCN20(__SHIFT)
 883 };
 884
 885 static const struct dcn_hubbub_mask hubbub_mask = {
 886                 HUBBUB_MASK_SH_LIST_DCN20(_MASK)
 887 };
 888
 889 #define vmid_regs(id)\
 890 [id] = {\
 891                 DCN20_VMID_REG_LIST(id)\
 892 }
 893
 894 static const struct dcn_vmid_registers vmid_regs[] = {
 895         vmid_regs(0),
 896         vmid_regs(1),
 897         vmid_regs(2),
 898         vmid_regs(3),
 899         vmid_regs(4),
 900         vmid_regs(5),
 901         vmid_regs(6),
 902         vmid_regs(7),
 903         vmid_regs(8),
 904         vmid_regs(9),
 905         vmid_regs(10),
 906         vmid_regs(11),
 907         vmid_regs(12),
 908         vmid_regs(13),
 909         vmid_regs(14),
 910         vmid_regs(15)
 911 };
 912
 913 static const struct dcn20_vmid_shift vmid_shifts = {
 914                 DCN20_VMID_MASK_SH_LIST(__SHIFT)
 915 };
 916
 917 static const struct dcn20_vmid_mask vmid_masks = {
 918                 DCN20_VMID_MASK_SH_LIST(_MASK)
 919 };
 920
 921 static const struct dce110_aux_registers_shift aux_shift = {
 922                 DCN_AUX_MASK_SH_LIST(__SHIFT)
 923 };
 924
 925 static const struct dce110_aux_registers_mask aux_mask = {
 926                 DCN_AUX_MASK_SH_LIST(_MASK)
 927 };
 928
 929 static int map_transmitter_id_to_phy_instance(
 930         enum transmitter transmitter)
 931 {
 932         switch (transmitter) {
 933         case TRANSMITTER_UNIPHY_A:
 934                 return 0;
 935         break;
 936         case TRANSMITTER_UNIPHY_B:
 937                 return 1;
 938         break;
 939         case TRANSMITTER_UNIPHY_C:
 940                 return 2;
 941         break;
 942         case TRANSMITTER_UNIPHY_D:
 943                 return 3;
 944         break;
 945         case TRANSMITTER_UNIPHY_E:
 946                 return 4;
 947         break;
 948         case TRANSMITTER_UNIPHY_F:
 949                 return 5;
 950         break;
 951         default:
 952                 ASSERT(0);
 953                 return 0;
 954         }
 955 }
 956
 957 #define dsc_regsDCN20(id)\
 958 [id] = {\
 959         DSC_REG_LIST_DCN20(id)\
 960 }
 961
 962 static const struct dcn20_dsc_registers dsc_regs[] = {
 963         dsc_regsDCN20(0),
 964         dsc_regsDCN20(1),
 965         dsc_regsDCN20(2),
 966         dsc_regsDCN20(3),
 967         dsc_regsDCN20(4),
 968         dsc_regsDCN20(5)
 969 };
 970
 971 static const struct dcn20_dsc_shift dsc_shift = {
 972         DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
 973 };
 974
 975 static const struct dcn20_dsc_mask dsc_mask = {
 976         DSC_REG_LIST_SH_MASK_DCN20(_MASK)
 977 };
 978
 979 static const struct dccg_registers dccg_regs = {
 980                 DCCG_REG_LIST_DCN2()
 981 };
 982
 983 static const struct dccg_shift dccg_shift = {
 984                 DCCG_MASK_SH_LIST_DCN2(__SHIFT)
 985 };
 986
 987 static const struct dccg_mask dccg_mask = {
 988                 DCCG_MASK_SH_LIST_DCN2(_MASK)
 989 };
 990
 991 static const struct resource_caps res_cap_nv10 = {
 992                 .num_timing_generator = 6,
 993                 .num_opp = 6,
 994                 .num_video_plane = 6,
 995                 .num_audio = 7,
 996                 .num_stream_encoder = 6,
 997                 .num_pll = 6,
 998                 .num_dwb = 1,
 999                 .num_ddc = 6,
1000                 .num_vmid = 16,
1001                 .num_dsc = 6,
1002 };
1003
1004 static const struct dc_plane_cap plane_cap = {
1005         .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
1006         .blends_with_above = true,
1007         .blends_with_below = true,
1008         .per_pixel_alpha = true,
1009
1010         .pixel_format_support = {
1011                         .argb8888 = true,
1012                         .nv12 = true,
1013                         .fp16 = true
1014         },
1015
1016         .max_upscale_factor = {
1017                         .argb8888 = 16000,
1018                         .nv12 = 16000,
1019                         .fp16 = 1
1020         },
1021
1022         .max_downscale_factor = {
1023                         .argb8888 = 250,
1024                         .nv12 = 250,
1025                         .fp16 = 1
1026         }
1027 };
1028 static const struct resource_caps res_cap_nv14 = {
1029                 .num_timing_generator = 5,
1030                 .num_opp = 5,
1031                 .num_video_plane = 5,
1032                 .num_audio = 6,
1033                 .num_stream_encoder = 5,
1034                 .num_pll = 5,
1035                 .num_dwb = 1,
1036                 .num_ddc = 5,
1037                 .num_vmid = 16,
1038                 .num_dsc = 5,
1039 };
1040
1041 static const struct dc_debug_options debug_defaults_drv = {
1042                 .disable_dmcu = true,
1043                 .force_abm_enable = false,
1044                 .timing_trace = false,
1045                 .clock_trace = true,
1046                 .disable_pplib_clock_request = true,
1047                 .pipe_split_policy = MPC_SPLIT_DYNAMIC,
1048                 .force_single_disp_pipe_split = false,
1049                 .disable_dcc = DCC_ENABLE,
1050                 .vsr_support = true,
1051                 .performance_trace = false,
1052                 .max_downscale_src_width = 5120,/*upto 5K*/
1053                 .disable_pplib_wm_range = false,
1054                 .scl_reset_length10 = true,
1055                 .sanity_checks = false,
1056                 .disable_tri_buf = true,
1057                 .underflow_assert_delay_us = 0xFFFFFFFF,
1058 };
1059
1060 static const struct dc_debug_options debug_defaults_diags = {
1061                 .disable_dmcu = true,
1062                 .force_abm_enable = false,
1063                 .timing_trace = true,
1064                 .clock_trace = true,
1065                 .disable_dpp_power_gate = true,
1066                 .disable_hubp_power_gate = true,
1067                 .disable_clock_gate = true,
1068                 .disable_pplib_clock_request = true,
1069                 .disable_pplib_wm_range = true,
1070                 .disable_stutter = true,
1071                 .scl_reset_length10 = true,
1072                 .underflow_assert_delay_us = 0xFFFFFFFF,
1073 };
1074
1075 void dcn20_dpp_destroy(struct dpp **dpp)
1076 {
1077         kfree(TO_DCN20_DPP(*dpp));
1078         *dpp = NULL;
1079 }
1080
1081 struct dpp *dcn20_dpp_create(
1082         struct dc_context *ctx,
1083         uint32_t inst)
1084 {
1085         struct dcn20_dpp *dpp =
1086                 kzalloc(sizeof(struct dcn20_dpp), GFP_KERNEL);
1087
1088         if (!dpp)
1089                 return NULL;
1090
1091         if (dpp2_construct(dpp, ctx, inst,
1092                         &tf_regs[inst], &tf_shift, &tf_mask))
1093                 return &dpp->base;
1094
1095         BREAK_TO_DEBUGGER();
1096         kfree(dpp);
1097         return NULL;
1098 }
1099
1100 struct input_pixel_processor *dcn20_ipp_create(
1101         struct dc_context *ctx, uint32_t inst)
1102 {
1103         struct dcn10_ipp *ipp =
1104                 kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL);
1105
1106         if (!ipp) {
1107                 BREAK_TO_DEBUGGER();
1108                 return NULL;
1109         }
1110
1111         dcn20_ipp_construct(ipp, ctx, inst,
1112                         &ipp_regs[inst], &ipp_shift, &ipp_mask);
1113         return &ipp->base;
1114 }
1115
1116
1117 struct output_pixel_processor *dcn20_opp_create(
1118         struct dc_context *ctx, uint32_t inst)
1119 {
1120         struct dcn20_opp *opp =
1121                 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
1122
1123         if (!opp) {
1124                 BREAK_TO_DEBUGGER();
1125                 return NULL;
1126         }
1127
1128         dcn20_opp_construct(opp, ctx, inst,
1129                         &opp_regs[inst], &opp_shift, &opp_mask);
1130         return &opp->base;
1131 }
1132
1133 struct dce_aux *dcn20_aux_engine_create(
1134         struct dc_context *ctx,
1135         uint32_t inst)
1136 {
1137         struct aux_engine_dce110 *aux_engine =
1138                 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
1139
1140         if (!aux_engine)
1141                 return NULL;
1142
1143         dce110_aux_engine_construct(aux_engine, ctx, inst,
1144                                     SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
1145                                     &aux_engine_regs[inst],
1146                                         &aux_mask,
1147                                         &aux_shift,
1148                                         ctx->dc->caps.extended_aux_timeout_support);
1149
1150         return &aux_engine->base;
1151 }
1152 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
1153
1154 static const struct dce_i2c_registers i2c_hw_regs[] = {
1155                 i2c_inst_regs(1),
1156                 i2c_inst_regs(2),
1157                 i2c_inst_regs(3),
1158                 i2c_inst_regs(4),
1159                 i2c_inst_regs(5),
1160                 i2c_inst_regs(6),
1161 };
1162
1163 static const struct dce_i2c_shift i2c_shifts = {
1164                 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT)
1165 };
1166
1167 static const struct dce_i2c_mask i2c_masks = {
1168                 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
1169 };
1170
1171 struct dce_i2c_hw *dcn20_i2c_hw_create(
1172         struct dc_context *ctx,
1173         uint32_t inst)
1174 {
1175         struct dce_i2c_hw *dce_i2c_hw =
1176                 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
1177
1178         if (!dce_i2c_hw)
1179                 return NULL;
1180
1181         dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
1182                                     &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
1183
1184         return dce_i2c_hw;
1185 }
1186 struct mpc *dcn20_mpc_create(struct dc_context *ctx)
1187 {
1188         struct dcn20_mpc *mpc20 = kzalloc(sizeof(struct dcn20_mpc),
1189                                           GFP_KERNEL);
1190
1191         if (!mpc20)
1192                 return NULL;
1193
1194         dcn20_mpc_construct(mpc20, ctx,
1195                         &mpc_regs,
1196                         &mpc_shift,
1197                         &mpc_mask,
1198                         6);
1199
1200         return &mpc20->base;
1201 }
1202
1203 struct hubbub *dcn20_hubbub_create(struct dc_context *ctx)
1204 {
1205         int i;
1206         struct dcn20_hubbub *hubbub = kzalloc(sizeof(struct dcn20_hubbub),
1207                                           GFP_KERNEL);
1208
1209         if (!hubbub)
1210                 return NULL;
1211
1212         hubbub2_construct(hubbub, ctx,
1213                         &hubbub_reg,
1214                         &hubbub_shift,
1215                         &hubbub_mask);
1216
1217         for (i = 0; i < res_cap_nv10.num_vmid; i++) {
1218                 struct dcn20_vmid *vmid = &hubbub->vmid[i];
1219
1220                 vmid->ctx = ctx;
1221
1222                 vmid->regs = &vmid_regs[i];
1223                 vmid->shifts = &vmid_shifts;
1224                 vmid->masks = &vmid_masks;
1225         }
1226
1227         return &hubbub->base;
1228 }
1229
1230 struct timing_generator *dcn20_timing_generator_create(
1231                 struct dc_context *ctx,
1232                 uint32_t instance)
1233 {
1234         struct optc *tgn10 =
1235                 kzalloc(sizeof(struct optc), GFP_KERNEL);
1236
1237         if (!tgn10)
1238                 return NULL;
1239
1240         tgn10->base.inst = instance;
1241         tgn10->base.ctx = ctx;
1242
1243         tgn10->tg_regs = &tg_regs[instance];
1244         tgn10->tg_shift = &tg_shift;
1245         tgn10->tg_mask = &tg_mask;
1246
1247         dcn20_timing_generator_init(tgn10);
1248
1249         return &tgn10->base;
1250 }
1251
1252 static const struct encoder_feature_support link_enc_feature = {
1253                 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1254                 .max_hdmi_pixel_clock = 600000,
1255                 .hdmi_ycbcr420_supported = true,
1256                 .dp_ycbcr420_supported = true,
1257                 .flags.bits.IS_HBR2_CAPABLE = true,
1258                 .flags.bits.IS_HBR3_CAPABLE = true,
1259                 .flags.bits.IS_TPS3_CAPABLE = true,
1260                 .flags.bits.IS_TPS4_CAPABLE = true
1261 };
1262
1263 struct link_encoder *dcn20_link_encoder_create(
1264         const struct encoder_init_data *enc_init_data)
1265 {
1266         struct dcn20_link_encoder *enc20 =
1267                 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1268         int link_regs_id;
1269
1270         if (!enc20)
1271                 return NULL;
1272
1273         link_regs_id =
1274                 map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
1275
1276         dcn20_link_encoder_construct(enc20,
1277                                       enc_init_data,
1278                                       &link_enc_feature,
1279                                       &link_enc_regs[link_regs_id],
1280                                       &link_enc_aux_regs[enc_init_data->channel - 1],
1281                                       &link_enc_hpd_regs[enc_init_data->hpd_source],
1282                                       &le_shift,
1283                                       &le_mask);
1284
1285         return &enc20->enc10.base;
1286 }
1287
1288 struct clock_source *dcn20_clock_source_create(
1289         struct dc_context *ctx,
1290         struct dc_bios *bios,
1291         enum clock_source_id id,
1292         const struct dce110_clk_src_regs *regs,
1293         bool dp_clk_src)
1294 {
1295         struct dce110_clk_src *clk_src =
1296                 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1297
1298         if (!clk_src)
1299                 return NULL;
1300
1301         if (dcn20_clk_src_construct(clk_src, ctx, bios, id,
1302                         regs, &cs_shift, &cs_mask)) {
1303                 clk_src->base.dp_clk_src = dp_clk_src;
1304                 return &clk_src->base;
1305         }
1306
1307         kfree(clk_src);
1308         BREAK_TO_DEBUGGER();
1309         return NULL;
1310 }
1311
1312 static void read_dce_straps(
1313         struct dc_context *ctx,
1314         struct resource_straps *straps)
1315 {
1316         generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
1317                 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1318 }
1319
1320 static struct audio *dcn20_create_audio(
1321                 struct dc_context *ctx, unsigned int inst)
1322 {
1323         return dce_audio_create(ctx, inst,
1324                         &audio_regs[inst], &audio_shift, &audio_mask);
1325 }
1326
1327 struct stream_encoder *dcn20_stream_encoder_create(
1328         enum engine_id eng_id,
1329         struct dc_context *ctx)
1330 {
1331         struct dcn10_stream_encoder *enc1 =
1332                 kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1333
1334         if (!enc1)
1335                 return NULL;
1336
1337         if (ASICREV_IS_NAVI14_M(ctx->asic_id.hw_internal_rev)) {
1338                 if (eng_id >= ENGINE_ID_DIGD)
1339                         eng_id++;
1340         }
1341
1342         dcn20_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id,
1343                                         &stream_enc_regs[eng_id],
1344                                         &se_shift, &se_mask);
1345
1346         return &enc1->base;
1347 }
1348
1349 static const struct dce_hwseq_registers hwseq_reg = {
1350                 HWSEQ_DCN2_REG_LIST()
1351 };
1352
1353 static const struct dce_hwseq_shift hwseq_shift = {
1354                 HWSEQ_DCN2_MASK_SH_LIST(__SHIFT)
1355 };
1356
1357 static const struct dce_hwseq_mask hwseq_mask = {
1358                 HWSEQ_DCN2_MASK_SH_LIST(_MASK)
1359 };
1360
1361 struct dce_hwseq *dcn20_hwseq_create(
1362         struct dc_context *ctx)
1363 {
1364         struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1365
1366         if (hws) {
1367                 hws->ctx = ctx;
1368                 hws->regs = &hwseq_reg;
1369                 hws->shifts = &hwseq_shift;
1370                 hws->masks = &hwseq_mask;
1371         }
1372         return hws;
1373 }
1374
1375 static const struct resource_create_funcs res_create_funcs = {
1376         .read_dce_straps = read_dce_straps,
1377         .create_audio = dcn20_create_audio,
1378         .create_stream_encoder = dcn20_stream_encoder_create,
1379         .create_hwseq = dcn20_hwseq_create,
1380 };
1381
1382 static const struct resource_create_funcs res_create_maximus_funcs = {
1383         .read_dce_straps = NULL,
1384         .create_audio = NULL,
1385         .create_stream_encoder = NULL,
1386         .create_hwseq = dcn20_hwseq_create,
1387 };
1388
1389 static void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu);
1390
1391 void dcn20_clock_source_destroy(struct clock_source **clk_src)
1392 {
1393         kfree(TO_DCE110_CLK_SRC(*clk_src));
1394         *clk_src = NULL;
1395 }
1396
1397
1398 struct display_stream_compressor *dcn20_dsc_create(
1399         struct dc_context *ctx, uint32_t inst)
1400 {
1401         struct dcn20_dsc *dsc =
1402                 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1403
1404         if (!dsc) {
1405                 BREAK_TO_DEBUGGER();
1406                 return NULL;
1407         }
1408
1409         dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1410         return &dsc->base;
1411 }
1412
1413 void dcn20_dsc_destroy(struct display_stream_compressor **dsc)
1414 {
1415         kfree(container_of(*dsc, struct dcn20_dsc, base));
1416         *dsc = NULL;
1417 }
1418
1419
1420 static void dcn20_resource_destruct(struct dcn20_resource_pool *pool)
1421 {
1422         unsigned int i;
1423
1424         for (i = 0; i < pool->base.stream_enc_count; i++) {
1425                 if (pool->base.stream_enc[i] != NULL) {
1426                         kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1427                         pool->base.stream_enc[i] = NULL;
1428                 }
1429         }
1430
1431         for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1432                 if (pool->base.dscs[i] != NULL)
1433                         dcn20_dsc_destroy(&pool->base.dscs[i]);
1434         }
1435
1436         if (pool->base.mpc != NULL) {
1437                 kfree(TO_DCN20_MPC(pool->base.mpc));
1438                 pool->base.mpc = NULL;
1439         }
1440         if (pool->base.hubbub != NULL) {
1441                 kfree(pool->base.hubbub);
1442                 pool->base.hubbub = NULL;
1443         }
1444         for (i = 0; i < pool->base.pipe_count; i++) {
1445                 if (pool->base.dpps[i] != NULL)
1446                         dcn20_dpp_destroy(&pool->base.dpps[i]);
1447
1448                 if (pool->base.ipps[i] != NULL)
1449                         pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1450
1451                 if (pool->base.hubps[i] != NULL) {
1452                         kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1453                         pool->base.hubps[i] = NULL;
1454                 }
1455
1456                 if (pool->base.irqs != NULL) {
1457                         dal_irq_service_destroy(&pool->base.irqs);
1458                 }
1459         }
1460
1461         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1462                 if (pool->base.engines[i] != NULL)
1463                         dce110_engine_destroy(&pool->base.engines[i]);
1464                 if (pool->base.hw_i2cs[i] != NULL) {
1465                         kfree(pool->base.hw_i2cs[i]);
1466                         pool->base.hw_i2cs[i] = NULL;
1467                 }
1468                 if (pool->base.sw_i2cs[i] != NULL) {
1469                         kfree(pool->base.sw_i2cs[i]);
1470                         pool->base.sw_i2cs[i] = NULL;
1471                 }
1472         }
1473
1474         for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1475                 if (pool->base.opps[i] != NULL)
1476                         pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1477         }
1478
1479         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1480                 if (pool->base.timing_generators[i] != NULL)    {
1481                         kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1482                         pool->base.timing_generators[i] = NULL;
1483                 }
1484         }
1485
1486         for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1487                 if (pool->base.dwbc[i] != NULL) {
1488                         kfree(TO_DCN20_DWBC(pool->base.dwbc[i]));
1489                         pool->base.dwbc[i] = NULL;
1490                 }
1491                 if (pool->base.mcif_wb[i] != NULL) {
1492                         kfree(TO_DCN20_MMHUBBUB(pool->base.mcif_wb[i]));
1493                         pool->base.mcif_wb[i] = NULL;
1494                 }
1495         }
1496
1497         for (i = 0; i < pool->base.audio_count; i++) {
1498                 if (pool->base.audios[i])
1499                         dce_aud_destroy(&pool->base.audios[i]);
1500         }
1501
1502         for (i = 0; i < pool->base.clk_src_count; i++) {
1503                 if (pool->base.clock_sources[i] != NULL) {
1504                         dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1505                         pool->base.clock_sources[i] = NULL;
1506                 }
1507         }
1508
1509         if (pool->base.dp_clock_source != NULL) {
1510                 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1511                 pool->base.dp_clock_source = NULL;
1512         }
1513
1514
1515         if (pool->base.abm != NULL)
1516                 dce_abm_destroy(&pool->base.abm);
1517
1518         if (pool->base.dmcu != NULL)
1519                 dce_dmcu_destroy(&pool->base.dmcu);
1520
1521         if (pool->base.dccg != NULL)
1522                 dcn_dccg_destroy(&pool->base.dccg);
1523
1524         if (pool->base.pp_smu != NULL)
1525                 dcn20_pp_smu_destroy(&pool->base.pp_smu);
1526
1527         if (pool->base.oem_device != NULL)
1528                 dal_ddc_service_destroy(&pool->base.oem_device);
1529 }
1530
1531 struct hubp *dcn20_hubp_create(
1532         struct dc_context *ctx,
1533         uint32_t inst)
1534 {
1535         struct dcn20_hubp *hubp2 =
1536                 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
1537
1538         if (!hubp2)
1539                 return NULL;
1540
1541         if (hubp2_construct(hubp2, ctx, inst,
1542                         &hubp_regs[inst], &hubp_shift, &hubp_mask))
1543                 return &hubp2->base;
1544
1545         BREAK_TO_DEBUGGER();
1546         kfree(hubp2);
1547         return NULL;
1548 }
1549
1550 static void get_pixel_clock_parameters(
1551         struct pipe_ctx *pipe_ctx,
1552         struct pixel_clk_params *pixel_clk_params)
1553 {
1554         const struct dc_stream_state *stream = pipe_ctx->stream;
1555         struct pipe_ctx *odm_pipe;
1556         int opp_cnt = 1;
1557
1558         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
1559                 opp_cnt++;
1560
1561         pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz;
1562         pixel_clk_params->encoder_object_id = stream->link->link_enc->id;
1563         pixel_clk_params->signal_type = pipe_ctx->stream->signal;
1564         pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;
1565         /* TODO: un-hardcode*/
1566         pixel_clk_params->requested_sym_clk = LINK_RATE_LOW *
1567                 LINK_RATE_REF_FREQ_IN_KHZ;
1568         pixel_clk_params->flags.ENABLE_SS = 0;
1569         pixel_clk_params->color_depth =
1570                 stream->timing.display_color_depth;
1571         pixel_clk_params->flags.DISPLAY_BLANKED = 1;
1572         pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding;
1573
1574         if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
1575                 pixel_clk_params->color_depth = COLOR_DEPTH_888;
1576
1577         if (opp_cnt == 4)
1578                 pixel_clk_params->requested_pix_clk_100hz /= 4;
1579         else if (optc2_is_two_pixels_per_containter(&stream->timing) || opp_cnt == 2)
1580                 pixel_clk_params->requested_pix_clk_100hz /= 2;
1581
1582         if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
1583                 pixel_clk_params->requested_pix_clk_100hz *= 2;
1584
1585 }
1586
1587 static void build_clamping_params(struct dc_stream_state *stream)
1588 {
1589         stream->clamping.clamping_level = CLAMPING_FULL_RANGE;
1590         stream->clamping.c_depth = stream->timing.display_color_depth;
1591         stream->clamping.pixel_encoding = stream->timing.pixel_encoding;
1592 }
1593
1594 static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx)
1595 {
1596
1597         get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params);
1598
1599         pipe_ctx->clock_source->funcs->get_pix_clk_dividers(
1600                 pipe_ctx->clock_source,
1601                 &pipe_ctx->stream_res.pix_clk_params,
1602                 &pipe_ctx->pll_settings);
1603
1604         pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding;
1605
1606         resource_build_bit_depth_reduction_params(pipe_ctx->stream,
1607                                         &pipe_ctx->stream->bit_depth_params);
1608         build_clamping_params(pipe_ctx->stream);
1609
1610         return DC_OK;
1611 }
1612
1613 enum dc_status dcn20_build_mapped_resource(const struct dc *dc, struct dc_state *context, struct dc_stream_state *stream)
1614 {
1615         enum dc_status status = DC_OK;
1616         struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream);
1617
1618         /*TODO Seems unneeded anymore */
1619         /*      if (old_context && resource_is_stream_unchanged(old_context, stream)) {
1620                         if (stream != NULL && old_context->streams[i] != NULL) {
1621                                  todo: shouldn't have to copy missing parameter here
1622                                 resource_build_bit_depth_reduction_params(stream,
1623                                                 &stream->bit_depth_params);
1624                                 stream->clamping.pixel_encoding =
1625                                                 stream->timing.pixel_encoding;
1626
1627                                 resource_build_bit_depth_reduction_params(stream,
1628                                                                 &stream->bit_depth_params);
1629                                 build_clamping_params(stream);
1630
1631                                 continue;
1632                         }
1633                 }
1634         */
1635
1636         if (!pipe_ctx)
1637                 return DC_ERROR_UNEXPECTED;
1638
1639
1640         status = build_pipe_hw_param(pipe_ctx);
1641
1642         return status;
1643 }
1644
1645
1646 static void acquire_dsc(struct resource_context *res_ctx,
1647                         const struct resource_pool *pool,
1648                         struct display_stream_compressor **dsc,
1649                         int pipe_idx)
1650 {
1651         int i;
1652
1653         ASSERT(*dsc == NULL);
1654         *dsc = NULL;
1655
1656         if (pool->res_cap->num_dsc == pool->res_cap->num_opp) {
1657                 *dsc = pool->dscs[pipe_idx];
1658                 res_ctx->is_dsc_acquired[pipe_idx] = true;
1659                 return;
1660         }
1661
1662         /* Find first free DSC */
1663         for (i = 0; i < pool->res_cap->num_dsc; i++)
1664                 if (!res_ctx->is_dsc_acquired[i]) {
1665                         *dsc = pool->dscs[i];
1666                         res_ctx->is_dsc_acquired[i] = true;
1667                         break;
1668                 }
1669 }
1670
1671 static void release_dsc(struct resource_context *res_ctx,
1672                         const struct resource_pool *pool,
1673                         struct display_stream_compressor **dsc)
1674 {
1675         int i;
1676
1677         for (i = 0; i < pool->res_cap->num_dsc; i++)
1678                 if (pool->dscs[i] == *dsc) {
1679                         res_ctx->is_dsc_acquired[i] = false;
1680                         *dsc = NULL;
1681                         break;
1682                 }
1683 }
1684
1685
1686
1687 enum dc_status dcn20_add_dsc_to_stream_resource(struct dc *dc,
1688                 struct dc_state *dc_ctx,
1689                 struct dc_stream_state *dc_stream)
1690 {
1691         enum dc_status result = DC_OK;
1692         int i;
1693         const struct resource_pool *pool = dc->res_pool;
1694
1695         /* Get a DSC if required and available */
1696         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1697                 struct pipe_ctx *pipe_ctx = &dc_ctx->res_ctx.pipe_ctx[i];
1698
1699                 if (pipe_ctx->stream != dc_stream)
1700                         continue;
1701
1702                 if (pipe_ctx->stream_res.dsc)
1703                         continue;
1704
1705                 acquire_dsc(&dc_ctx->res_ctx, pool, &pipe_ctx->stream_res.dsc, i);
1706
1707                 /* The number of DSCs can be less than the number of pipes */
1708                 if (!pipe_ctx->stream_res.dsc) {
1709                         result = DC_NO_DSC_RESOURCE;
1710                 }
1711
1712                 break;
1713         }
1714
1715         return result;
1716 }
1717
1718
1719 static enum dc_status remove_dsc_from_stream_resource(struct dc *dc,
1720                 struct dc_state *new_ctx,
1721                 struct dc_stream_state *dc_stream)
1722 {
1723         struct pipe_ctx *pipe_ctx = NULL;
1724         int i;
1725
1726         for (i = 0; i < MAX_PIPES; i++) {
1727                 if (new_ctx->res_ctx.pipe_ctx[i].stream == dc_stream && !new_ctx->res_ctx.pipe_ctx[i].top_pipe) {
1728                         pipe_ctx = &new_ctx->res_ctx.pipe_ctx[i];
1729
1730                         if (pipe_ctx->stream_res.dsc)
1731                                 release_dsc(&new_ctx->res_ctx, dc->res_pool, &pipe_ctx->stream_res.dsc);
1732                 }
1733         }
1734
1735         if (!pipe_ctx)
1736                 return DC_ERROR_UNEXPECTED;
1737         else
1738                 return DC_OK;
1739 }
1740
1741
1742 enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream)
1743 {
1744         enum dc_status result = DC_ERROR_UNEXPECTED;
1745
1746         result = resource_map_pool_resources(dc, new_ctx, dc_stream);
1747
1748         if (result == DC_OK)
1749                 result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream);
1750
1751         /* Get a DSC if required and available */
1752         if (result == DC_OK && dc_stream->timing.flags.DSC)
1753                 result = dcn20_add_dsc_to_stream_resource(dc, new_ctx, dc_stream);
1754
1755         if (result == DC_OK)
1756                 result = dcn20_build_mapped_resource(dc, new_ctx, dc_stream);
1757
1758         return result;
1759 }
1760
1761
1762 enum dc_status dcn20_remove_stream_from_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream)
1763 {
1764         enum dc_status result = DC_OK;
1765
1766         result = remove_dsc_from_stream_resource(dc, new_ctx, dc_stream);
1767
1768         return result;
1769 }
1770
1771
1772 static void swizzle_to_dml_params(
1773                 enum swizzle_mode_values swizzle,
1774                 unsigned int *sw_mode)
1775 {
1776         switch (swizzle) {
1777         case DC_SW_LINEAR:
1778                 *sw_mode = dm_sw_linear;
1779                 break;
1780         case DC_SW_4KB_S:
1781                 *sw_mode = dm_sw_4kb_s;
1782                 break;
1783         case DC_SW_4KB_S_X:
1784                 *sw_mode = dm_sw_4kb_s_x;
1785                 break;
1786         case DC_SW_4KB_D:
1787                 *sw_mode = dm_sw_4kb_d;
1788                 break;
1789         case DC_SW_4KB_D_X:
1790                 *sw_mode = dm_sw_4kb_d_x;
1791                 break;
1792         case DC_SW_64KB_S:
1793                 *sw_mode = dm_sw_64kb_s;
1794                 break;
1795         case DC_SW_64KB_S_X:
1796                 *sw_mode = dm_sw_64kb_s_x;
1797                 break;
1798         case DC_SW_64KB_S_T:
1799                 *sw_mode = dm_sw_64kb_s_t;
1800                 break;
1801         case DC_SW_64KB_D:
1802                 *sw_mode = dm_sw_64kb_d;
1803                 break;
1804         case DC_SW_64KB_D_X:
1805                 *sw_mode = dm_sw_64kb_d_x;
1806                 break;
1807         case DC_SW_64KB_D_T:
1808                 *sw_mode = dm_sw_64kb_d_t;
1809                 break;
1810         case DC_SW_64KB_R_X:
1811                 *sw_mode = dm_sw_64kb_r_x;
1812                 break;
1813         case DC_SW_VAR_S:
1814                 *sw_mode = dm_sw_var_s;
1815                 break;
1816         case DC_SW_VAR_S_X:
1817                 *sw_mode = dm_sw_var_s_x;
1818                 break;
1819         case DC_SW_VAR_D:
1820                 *sw_mode = dm_sw_var_d;
1821                 break;
1822         case DC_SW_VAR_D_X:
1823                 *sw_mode = dm_sw_var_d_x;
1824                 break;
1825
1826         default:
1827                 ASSERT(0); /* Not supported */
1828                 break;
1829         }
1830 }
1831
1832 bool dcn20_split_stream_for_odm(
1833                 struct resource_context *res_ctx,
1834                 const struct resource_pool *pool,
1835                 struct pipe_ctx *prev_odm_pipe,
1836                 struct pipe_ctx *next_odm_pipe)
1837 {
1838         int pipe_idx = next_odm_pipe->pipe_idx;
1839
1840         *next_odm_pipe = *prev_odm_pipe;
1841
1842         next_odm_pipe->pipe_idx = pipe_idx;
1843         next_odm_pipe->plane_res.mi = pool->mis[next_odm_pipe->pipe_idx];
1844         next_odm_pipe->plane_res.hubp = pool->hubps[next_odm_pipe->pipe_idx];
1845         next_odm_pipe->plane_res.ipp = pool->ipps[next_odm_pipe->pipe_idx];
1846         next_odm_pipe->plane_res.xfm = pool->transforms[next_odm_pipe->pipe_idx];
1847         next_odm_pipe->plane_res.dpp = pool->dpps[next_odm_pipe->pipe_idx];
1848         next_odm_pipe->plane_res.mpcc_inst = pool->dpps[next_odm_pipe->pipe_idx]->inst;
1849         next_odm_pipe->stream_res.dsc = NULL;
1850         if (prev_odm_pipe->next_odm_pipe && prev_odm_pipe->next_odm_pipe != next_odm_pipe) {
1851                 next_odm_pipe->next_odm_pipe = prev_odm_pipe->next_odm_pipe;
1852                 next_odm_pipe->next_odm_pipe->prev_odm_pipe = next_odm_pipe;
1853         }
1854         prev_odm_pipe->next_odm_pipe = next_odm_pipe;
1855         next_odm_pipe->prev_odm_pipe = prev_odm_pipe;
1856         ASSERT(next_odm_pipe->top_pipe == NULL);
1857
1858         if (prev_odm_pipe->plane_state) {
1859                 struct scaler_data *sd = &prev_odm_pipe->plane_res.scl_data;
1860                 int new_width;
1861
1862                 /* HACTIVE halved for odm combine */
1863                 sd->h_active /= 2;
1864                 /* Calculate new vp and recout for left pipe */
1865                 /* Need at least 16 pixels width per side */
1866                 if (sd->recout.x + 16 >= sd->h_active)
1867                         return false;
1868                 new_width = sd->h_active - sd->recout.x;
1869                 sd->viewport.width -= dc_fixpt_floor(dc_fixpt_mul_int(
1870                                 sd->ratios.horz, sd->recout.width - new_width));
1871                 sd->viewport_c.width -= dc_fixpt_floor(dc_fixpt_mul_int(
1872                                 sd->ratios.horz_c, sd->recout.width - new_width));
1873                 sd->recout.width = new_width;
1874
1875                 /* Calculate new vp and recout for right pipe */
1876                 sd = &next_odm_pipe->plane_res.scl_data;
1877                 /* HACTIVE halved for odm combine */
1878                 sd->h_active /= 2;
1879                 /* Need at least 16 pixels width per side */
1880                 if (new_width <= 16)
1881                         return false;
1882                 new_width = sd->recout.width + sd->recout.x - sd->h_active;
1883                 sd->viewport.width -= dc_fixpt_floor(dc_fixpt_mul_int(
1884                                 sd->ratios.horz, sd->recout.width - new_width));
1885                 sd->viewport_c.width -= dc_fixpt_floor(dc_fixpt_mul_int(
1886                                 sd->ratios.horz_c, sd->recout.width - new_width));
1887                 sd->recout.width = new_width;
1888                 sd->viewport.x += dc_fixpt_floor(dc_fixpt_mul_int(
1889                                 sd->ratios.horz, sd->h_active - sd->recout.x));
1890                 sd->viewport_c.x += dc_fixpt_floor(dc_fixpt_mul_int(
1891                                 sd->ratios.horz_c, sd->h_active - sd->recout.x));
1892                 sd->recout.x = 0;
1893         }
1894         next_odm_pipe->stream_res.opp = pool->opps[next_odm_pipe->pipe_idx];
1895         if (next_odm_pipe->stream->timing.flags.DSC == 1) {
1896                 acquire_dsc(res_ctx, pool, &next_odm_pipe->stream_res.dsc, next_odm_pipe->pipe_idx);
1897                 ASSERT(next_odm_pipe->stream_res.dsc);
1898                 if (next_odm_pipe->stream_res.dsc == NULL)
1899                         return false;
1900         }
1901
1902         return true;
1903 }
1904
1905 void dcn20_split_stream_for_mpc(
1906                 struct resource_context *res_ctx,
1907                 const struct resource_pool *pool,
1908                 struct pipe_ctx *primary_pipe,
1909                 struct pipe_ctx *secondary_pipe)
1910 {
1911         int pipe_idx = secondary_pipe->pipe_idx;
1912         struct pipe_ctx *sec_bot_pipe = secondary_pipe->bottom_pipe;
1913
1914         *secondary_pipe = *primary_pipe;
1915         secondary_pipe->bottom_pipe = sec_bot_pipe;
1916
1917         secondary_pipe->pipe_idx = pipe_idx;
1918         secondary_pipe->plane_res.mi = pool->mis[secondary_pipe->pipe_idx];
1919         secondary_pipe->plane_res.hubp = pool->hubps[secondary_pipe->pipe_idx];
1920         secondary_pipe->plane_res.ipp = pool->ipps[secondary_pipe->pipe_idx];
1921         secondary_pipe->plane_res.xfm = pool->transforms[secondary_pipe->pipe_idx];
1922         secondary_pipe->plane_res.dpp = pool->dpps[secondary_pipe->pipe_idx];
1923         secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst;
1924         secondary_pipe->stream_res.dsc = NULL;
1925         if (primary_pipe->bottom_pipe && primary_pipe->bottom_pipe != secondary_pipe) {
1926                 ASSERT(!secondary_pipe->bottom_pipe);
1927                 secondary_pipe->bottom_pipe = primary_pipe->bottom_pipe;
1928                 secondary_pipe->bottom_pipe->top_pipe = secondary_pipe;
1929         }
1930         primary_pipe->bottom_pipe = secondary_pipe;
1931         secondary_pipe->top_pipe = primary_pipe;
1932
1933         ASSERT(primary_pipe->plane_state);
1934         resource_build_scaling_params(primary_pipe);
1935         resource_build_scaling_params(secondary_pipe);
1936 }
1937
1938 void dcn20_populate_dml_writeback_from_context(
1939                 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes)
1940 {
1941         int pipe_cnt, i;
1942
1943         for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1944                 struct dc_writeback_info *wb_info = &res_ctx->pipe_ctx[i].stream->writeback_info[0];
1945
1946                 if (!res_ctx->pipe_ctx[i].stream)
1947                         continue;
1948
1949                 /* Set writeback information */
1950                 pipes[pipe_cnt].dout.wb_enable = (wb_info->wb_enabled == true) ? 1 : 0;
1951                 pipes[pipe_cnt].dout.num_active_wb++;
1952                 pipes[pipe_cnt].dout.wb.wb_src_height = wb_info->dwb_params.cnv_params.crop_height;
1953                 pipes[pipe_cnt].dout.wb.wb_src_width = wb_info->dwb_params.cnv_params.crop_width;
1954                 pipes[pipe_cnt].dout.wb.wb_dst_width = wb_info->dwb_params.dest_width;
1955                 pipes[pipe_cnt].dout.wb.wb_dst_height = wb_info->dwb_params.dest_height;
1956                 pipes[pipe_cnt].dout.wb.wb_htaps_luma = 1;
1957                 pipes[pipe_cnt].dout.wb.wb_vtaps_luma = 1;
1958                 pipes[pipe_cnt].dout.wb.wb_htaps_chroma = wb_info->dwb_params.scaler_taps.h_taps_c;
1959                 pipes[pipe_cnt].dout.wb.wb_vtaps_chroma = wb_info->dwb_params.scaler_taps.v_taps_c;
1960                 pipes[pipe_cnt].dout.wb.wb_hratio = 1.0;
1961                 pipes[pipe_cnt].dout.wb.wb_vratio = 1.0;
1962                 if (wb_info->dwb_params.out_format == dwb_scaler_mode_yuv420) {
1963                         if (wb_info->dwb_params.output_depth == DWB_OUTPUT_PIXEL_DEPTH_8BPC)
1964                                 pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_420_8;
1965                         else
1966                                 pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_420_10;
1967                 } else
1968                         pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_444_32;
1969
1970                 pipe_cnt++;
1971         }
1972
1973 }
1974
1975 static int get_num_odm_heads(struct pipe_ctx *pipe)
1976 {
1977         int odm_head_count = 0;
1978         struct pipe_ctx *next_pipe = pipe->next_odm_pipe;
1979         while (next_pipe) {
1980                 odm_head_count++;
1981                 next_pipe = next_pipe->next_odm_pipe;
1982         }
1983         pipe = pipe->prev_odm_pipe;
1984         while (pipe) {
1985                 odm_head_count++;
1986                 pipe = pipe->prev_odm_pipe;
1987         }
1988         return odm_head_count ? odm_head_count + 1 : 0;
1989 }
1990
1991 int dcn20_populate_dml_pipes_from_context(
1992                 struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes)
1993 {
1994         int pipe_cnt, i;
1995         bool synchronized_vblank = true;
1996         struct resource_context *res_ctx = &context->res_ctx;
1997
1998         for (i = 0, pipe_cnt = -1; i < dc->res_pool->pipe_count; i++) {
1999                 if (!res_ctx->pipe_ctx[i].stream)
2000                         continue;
2001
2002                 if (pipe_cnt < 0) {
2003                         pipe_cnt = i;
2004                         continue;
2005                 }
2006                 if (dc->debug.disable_timing_sync || !resource_are_streams_timing_synchronizable(
2007                                 res_ctx->pipe_ctx[pipe_cnt].stream,
2008                                 res_ctx->pipe_ctx[i].stream)) {
2009                         synchronized_vblank = false;
2010                         break;
2011                 }
2012         }
2013
2014         for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
2015                 struct dc_crtc_timing *timing = &res_ctx->pipe_ctx[i].stream->timing;
2016                 unsigned int v_total;
2017                 unsigned int front_porch;
2018                 int output_bpc;
2019
2020                 if (!res_ctx->pipe_ctx[i].stream)
2021                         continue;
2022
2023                 v_total = timing->v_total;
2024                 front_porch = timing->v_front_porch;
2025                 /* todo:
2026                 pipes[pipe_cnt].pipe.src.dynamic_metadata_enable = 0;
2027                 pipes[pipe_cnt].pipe.src.dcc = 0;
2028                 pipes[pipe_cnt].pipe.src.vm = 0;*/
2029
2030                 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
2031
2032                 pipes[pipe_cnt].dout.dsc_enable = res_ctx->pipe_ctx[i].stream->timing.flags.DSC;
2033                 /* todo: rotation?*/
2034                 pipes[pipe_cnt].dout.dsc_slices = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.num_slices_h;
2035                 if (res_ctx->pipe_ctx[i].stream->use_dynamic_meta) {
2036                         pipes[pipe_cnt].pipe.src.dynamic_metadata_enable = true;
2037                         /* 1/2 vblank */
2038                         pipes[pipe_cnt].pipe.src.dynamic_metadata_lines_before_active =
2039                                 (v_total - timing->v_addressable
2040                                         - timing->v_border_top - timing->v_border_bottom) / 2;
2041                         /* 36 bytes dp, 32 hdmi */
2042                         pipes[pipe_cnt].pipe.src.dynamic_metadata_xmit_bytes =
2043                                 dc_is_dp_signal(res_ctx->pipe_ctx[i].stream->signal) ? 36 : 32;
2044                 }
2045                 pipes[pipe_cnt].pipe.src.dcc = false;
2046                 pipes[pipe_cnt].pipe.src.dcc_rate = 1;
2047                 pipes[pipe_cnt].pipe.dest.synchronized_vblank_all_planes = synchronized_vblank;
2048                 pipes[pipe_cnt].pipe.dest.hblank_start = timing->h_total - timing->h_front_porch;
2049                 pipes[pipe_cnt].pipe.dest.hblank_end = pipes[pipe_cnt].pipe.dest.hblank_start
2050                                 - timing->h_addressable
2051                                 - timing->h_border_left
2052                                 - timing->h_border_right;
2053                 pipes[pipe_cnt].pipe.dest.vblank_start = v_total - front_porch;
2054                 pipes[pipe_cnt].pipe.dest.vblank_end = pipes[pipe_cnt].pipe.dest.vblank_start
2055                                 - timing->v_addressable
2056                                 - timing->v_border_top
2057                                 - timing->v_border_bottom;
2058                 pipes[pipe_cnt].pipe.dest.htotal = timing->h_total;
2059                 pipes[pipe_cnt].pipe.dest.vtotal = v_total;
2060                 pipes[pipe_cnt].pipe.dest.hactive = timing->h_addressable;
2061                 pipes[pipe_cnt].pipe.dest.vactive = timing->v_addressable;
2062                 pipes[pipe_cnt].pipe.dest.interlaced = timing->flags.INTERLACE;
2063                 pipes[pipe_cnt].pipe.dest.pixel_rate_mhz = timing->pix_clk_100hz/10000.0;
2064                 if (timing->timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
2065                         pipes[pipe_cnt].pipe.dest.pixel_rate_mhz *= 2;
2066                 pipes[pipe_cnt].pipe.dest.otg_inst = res_ctx->pipe_ctx[i].stream_res.tg->inst;
2067                 pipes[pipe_cnt].dout.dp_lanes = 4;
2068                 pipes[pipe_cnt].pipe.dest.vtotal_min = res_ctx->pipe_ctx[i].stream->adjust.v_total_min;
2069                 pipes[pipe_cnt].pipe.dest.vtotal_max = res_ctx->pipe_ctx[i].stream->adjust.v_total_max;
2070                 switch (get_num_odm_heads(&res_ctx->pipe_ctx[i])) {
2071                 case 2:
2072                         pipes[pipe_cnt].pipe.dest.odm_combine = dm_odm_combine_mode_2to1;
2073                         break;
2074                 default:
2075                         pipes[pipe_cnt].pipe.dest.odm_combine = dm_odm_combine_mode_disabled;
2076                 }
2077                 pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx;
2078                 if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state
2079                                 == res_ctx->pipe_ctx[i].plane_state)
2080                         pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].top_pipe->pipe_idx;
2081                 else if (res_ctx->pipe_ctx[i].prev_odm_pipe) {
2082                         struct pipe_ctx *first_pipe = res_ctx->pipe_ctx[i].prev_odm_pipe;
2083
2084                         while (first_pipe->prev_odm_pipe)
2085                                 first_pipe = first_pipe->prev_odm_pipe;
2086                         pipes[pipe_cnt].pipe.src.hsplit_grp = first_pipe->pipe_idx;
2087                 }
2088
2089                 switch (res_ctx->pipe_ctx[i].stream->signal) {
2090                 case SIGNAL_TYPE_DISPLAY_PORT_MST:
2091                 case SIGNAL_TYPE_DISPLAY_PORT:
2092                         pipes[pipe_cnt].dout.output_type = dm_dp;
2093                         break;
2094                 case SIGNAL_TYPE_EDP:
2095                         pipes[pipe_cnt].dout.output_type = dm_edp;
2096                         break;
2097                 case SIGNAL_TYPE_HDMI_TYPE_A:
2098                 case SIGNAL_TYPE_DVI_SINGLE_LINK:
2099                 case SIGNAL_TYPE_DVI_DUAL_LINK:
2100                         pipes[pipe_cnt].dout.output_type = dm_hdmi;
2101                         break;
2102                 default:
2103                         /* In case there is no signal, set dp with 4 lanes to allow max config */
2104                         pipes[pipe_cnt].dout.output_type = dm_dp;
2105                         pipes[pipe_cnt].dout.dp_lanes = 4;
2106                 }
2107
2108                 switch (res_ctx->pipe_ctx[i].stream->timing.display_color_depth) {
2109                 case COLOR_DEPTH_666:
2110                         output_bpc = 6;
2111                         break;
2112                 case COLOR_DEPTH_888:
2113                         output_bpc = 8;
2114                         break;
2115                 case COLOR_DEPTH_101010:
2116                         output_bpc = 10;
2117                         break;
2118                 case COLOR_DEPTH_121212:
2119                         output_bpc = 12;
2120                         break;
2121                 case COLOR_DEPTH_141414:
2122                         output_bpc = 14;
2123                         break;
2124                 case COLOR_DEPTH_161616:
2125                         output_bpc = 16;
2126                         break;
2127                 case COLOR_DEPTH_999:
2128                         output_bpc = 9;
2129                         break;
2130                 case COLOR_DEPTH_111111:
2131                         output_bpc = 11;
2132                         break;
2133                 default:
2134                         output_bpc = 8;
2135                         break;
2136                 }
2137
2138                 switch (res_ctx->pipe_ctx[i].stream->timing.pixel_encoding) {
2139                 case PIXEL_ENCODING_RGB:
2140                 case PIXEL_ENCODING_YCBCR444:
2141                         pipes[pipe_cnt].dout.output_format = dm_444;
2142                         pipes[pipe_cnt].dout.output_bpp = output_bpc * 3;
2143                         break;
2144                 case PIXEL_ENCODING_YCBCR420:
2145                         pipes[pipe_cnt].dout.output_format = dm_420;
2146                         pipes[pipe_cnt].dout.output_bpp = (output_bpc * 3.0) / 2;
2147                         break;
2148                 case PIXEL_ENCODING_YCBCR422:
2149                         if (true) /* todo */
2150                                 pipes[pipe_cnt].dout.output_format = dm_s422;
2151                         else
2152                                 pipes[pipe_cnt].dout.output_format = dm_n422;
2153                         pipes[pipe_cnt].dout.output_bpp = output_bpc * 2;
2154                         break;
2155                 default:
2156                         pipes[pipe_cnt].dout.output_format = dm_444;
2157                         pipes[pipe_cnt].dout.output_bpp = output_bpc * 3;
2158                 }
2159
2160                 if (res_ctx->pipe_ctx[i].stream->timing.flags.DSC)
2161                         pipes[pipe_cnt].dout.output_bpp = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.bits_per_pixel / 16.0;
2162
2163                 /* todo: default max for now, until there is logic reflecting this in dc*/
2164                 pipes[pipe_cnt].dout.output_bpc = 12;
2165                 /*
2166                  * Use max cursor settings for calculations to minimize
2167                  * bw calculations due to cursor on/off
2168                  */
2169                 pipes[pipe_cnt].pipe.src.num_cursors = 2;
2170                 pipes[pipe_cnt].pipe.src.cur0_src_width = 256;
2171                 pipes[pipe_cnt].pipe.src.cur0_bpp = dm_cur_32bit;
2172                 pipes[pipe_cnt].pipe.src.cur1_src_width = 256;
2173                 pipes[pipe_cnt].pipe.src.cur1_bpp = dm_cur_32bit;
2174
2175                 if (!res_ctx->pipe_ctx[i].plane_state) {
2176                         pipes[pipe_cnt].pipe.src.source_scan = dm_horz;
2177                         pipes[pipe_cnt].pipe.src.sw_mode = dm_sw_linear;
2178                         pipes[pipe_cnt].pipe.src.macro_tile_size = dm_64k_tile;
2179                         pipes[pipe_cnt].pipe.src.viewport_width = timing->h_addressable;
2180                         if (pipes[pipe_cnt].pipe.src.viewport_width > 1920)
2181                                 pipes[pipe_cnt].pipe.src.viewport_width = 1920;
2182                         pipes[pipe_cnt].pipe.src.viewport_height = timing->v_addressable;
2183                         if (pipes[pipe_cnt].pipe.src.viewport_height > 1080)
2184                                 pipes[pipe_cnt].pipe.src.viewport_height = 1080;
2185                         pipes[pipe_cnt].pipe.src.surface_height_y = pipes[pipe_cnt].pipe.src.viewport_height;
2186                         pipes[pipe_cnt].pipe.src.surface_width_y = pipes[pipe_cnt].pipe.src.viewport_width;
2187                         pipes[pipe_cnt].pipe.src.surface_height_c = pipes[pipe_cnt].pipe.src.viewport_height;
2188                         pipes[pipe_cnt].pipe.src.surface_width_c = pipes[pipe_cnt].pipe.src.viewport_width;
2189                         pipes[pipe_cnt].pipe.src.data_pitch = ((pipes[pipe_cnt].pipe.src.viewport_width + 63) / 64) * 64; /* linear sw only */
2190                         pipes[pipe_cnt].pipe.src.source_format = dm_444_32;
2191                         pipes[pipe_cnt].pipe.dest.recout_width = pipes[pipe_cnt].pipe.src.viewport_width; /*vp_width/hratio*/
2192                         pipes[pipe_cnt].pipe.dest.recout_height = pipes[pipe_cnt].pipe.src.viewport_height; /*vp_height/vratio*/
2193                         pipes[pipe_cnt].pipe.dest.full_recout_width = pipes[pipe_cnt].pipe.dest.recout_width;  /*when is_hsplit != 1*/
2194                         pipes[pipe_cnt].pipe.dest.full_recout_height = pipes[pipe_cnt].pipe.dest.recout_height; /*when is_hsplit != 1*/
2195                         pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_16;
2196                         pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio = 1.0;
2197                         pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio = 1.0;
2198                         pipes[pipe_cnt].pipe.scale_ratio_depth.scl_enable = 0; /*Lb only or Full scl*/
2199                         pipes[pipe_cnt].pipe.scale_taps.htaps = 1;
2200                         pipes[pipe_cnt].pipe.scale_taps.vtaps = 1;
2201                         pipes[pipe_cnt].pipe.src.is_hsplit = 0;
2202                         pipes[pipe_cnt].pipe.dest.odm_combine = 0;
2203                         pipes[pipe_cnt].pipe.dest.vtotal_min = v_total;
2204                         pipes[pipe_cnt].pipe.dest.vtotal_max = v_total;
2205                 } else {
2206                         struct dc_plane_state *pln = res_ctx->pipe_ctx[i].plane_state;
2207                         struct scaler_data *scl = &res_ctx->pipe_ctx[i].plane_res.scl_data;
2208
2209                         pipes[pipe_cnt].pipe.src.immediate_flip = pln->flip_immediate;
2210                         pipes[pipe_cnt].pipe.src.is_hsplit = (res_ctx->pipe_ctx[i].bottom_pipe
2211                                         && res_ctx->pipe_ctx[i].bottom_pipe->plane_state == pln)
2212                                         || (res_ctx->pipe_ctx[i].top_pipe
2213                                         && res_ctx->pipe_ctx[i].top_pipe->plane_state == pln);
2214                         pipes[pipe_cnt].pipe.src.source_scan = pln->rotation == ROTATION_ANGLE_90
2215                                         || pln->rotation == ROTATION_ANGLE_270 ? dm_vert : dm_horz;
2216                         pipes[pipe_cnt].pipe.src.viewport_y_y = scl->viewport.y;
2217                         pipes[pipe_cnt].pipe.src.viewport_y_c = scl->viewport_c.y;
2218                         pipes[pipe_cnt].pipe.src.viewport_width = scl->viewport.width;
2219                         pipes[pipe_cnt].pipe.src.viewport_width_c = scl->viewport_c.width;
2220                         pipes[pipe_cnt].pipe.src.viewport_height = scl->viewport.height;
2221                         pipes[pipe_cnt].pipe.src.viewport_height_c = scl->viewport_c.height;
2222                         pipes[pipe_cnt].pipe.src.surface_width_y = pln->plane_size.surface_size.width;
2223                         pipes[pipe_cnt].pipe.src.surface_height_y = pln->plane_size.surface_size.height;
2224                         pipes[pipe_cnt].pipe.src.surface_width_c = pln->plane_size.chroma_size.width;
2225                         pipes[pipe_cnt].pipe.src.surface_height_c = pln->plane_size.chroma_size.height;
2226                         if (pln->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
2227                                 pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.surface_pitch;
2228                                 pipes[pipe_cnt].pipe.src.data_pitch_c = pln->plane_size.chroma_pitch;
2229                                 pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.meta_pitch;
2230                                 pipes[pipe_cnt].pipe.src.meta_pitch_c = pln->dcc.meta_pitch_c;
2231                         } else {
2232                                 pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.surface_pitch;
2233                                 pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.meta_pitch;
2234                         }
2235                         pipes[pipe_cnt].pipe.src.dcc = pln->dcc.enable;
2236                         pipes[pipe_cnt].pipe.dest.recout_width = scl->recout.width;
2237                         pipes[pipe_cnt].pipe.dest.recout_height = scl->recout.height;
2238                         pipes[pipe_cnt].pipe.dest.full_recout_width = scl->recout.width;
2239                         pipes[pipe_cnt].pipe.dest.full_recout_height = scl->recout.height;
2240                         if (res_ctx->pipe_ctx[i].bottom_pipe && res_ctx->pipe_ctx[i].bottom_pipe->plane_state == pln) {
2241                                 pipes[pipe_cnt].pipe.dest.full_recout_width +=
2242                                                 res_ctx->pipe_ctx[i].bottom_pipe->plane_res.scl_data.recout.width;
2243                                 pipes[pipe_cnt].pipe.dest.full_recout_height +=
2244                                                 res_ctx->pipe_ctx[i].bottom_pipe->plane_res.scl_data.recout.height;
2245                         } else if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state == pln) {
2246                                 pipes[pipe_cnt].pipe.dest.full_recout_width +=
2247                                                 res_ctx->pipe_ctx[i].top_pipe->plane_res.scl_data.recout.width;
2248                                 pipes[pipe_cnt].pipe.dest.full_recout_height +=
2249                                                 res_ctx->pipe_ctx[i].top_pipe->plane_res.scl_data.recout.height;
2250                         }
2251
2252                         pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_16;
2253                         pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio = (double) scl->ratios.horz.value / (1ULL<<32);
2254                         pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio_c = (double) scl->ratios.horz_c.value / (1ULL<<32);
2255                         pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio = (double) scl->ratios.vert.value / (1ULL<<32);
2256                         pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio_c = (double) scl->ratios.vert_c.value / (1ULL<<32);
2257                         pipes[pipe_cnt].pipe.scale_ratio_depth.scl_enable =
2258                                         scl->ratios.vert.value != dc_fixpt_one.value
2259                                         || scl->ratios.horz.value != dc_fixpt_one.value
2260                                         || scl->ratios.vert_c.value != dc_fixpt_one.value
2261                                         || scl->ratios.horz_c.value != dc_fixpt_one.value /*Lb only or Full scl*/
2262                                         || dc->debug.always_scale; /*support always scale*/
2263                         pipes[pipe_cnt].pipe.scale_taps.htaps = scl->taps.h_taps;
2264                         pipes[pipe_cnt].pipe.scale_taps.htaps_c = scl->taps.h_taps_c;
2265                         pipes[pipe_cnt].pipe.scale_taps.vtaps = scl->taps.v_taps;
2266                         pipes[pipe_cnt].pipe.scale_taps.vtaps_c = scl->taps.v_taps_c;
2267
2268                         pipes[pipe_cnt].pipe.src.macro_tile_size =
2269                                         swizzle_mode_to_macro_tile_size(pln->tiling_info.gfx9.swizzle);
2270                         swizzle_to_dml_params(pln->tiling_info.gfx9.swizzle,
2271                                         &pipes[pipe_cnt].pipe.src.sw_mode);
2272
2273                         switch (pln->format) {
2274                         case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
2275                         case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
2276                                 pipes[pipe_cnt].pipe.src.source_format = dm_420_8;
2277                                 break;
2278                         case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
2279                         case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
2280                                 pipes[pipe_cnt].pipe.src.source_format = dm_420_10;
2281                                 break;
2282                         case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
2283                         case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
2284                         case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
2285                                 pipes[pipe_cnt].pipe.src.source_format = dm_444_64;
2286                                 break;
2287                         case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
2288                         case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
2289                                 pipes[pipe_cnt].pipe.src.source_format = dm_444_16;
2290                                 break;
2291                         case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
2292                                 pipes[pipe_cnt].pipe.src.source_format = dm_444_8;
2293                                 break;
2294                         default:
2295                                 pipes[pipe_cnt].pipe.src.source_format = dm_444_32;
2296                                 break;
2297                         }
2298                 }
2299
2300                 pipe_cnt++;
2301         }
2302
2303         /* populate writeback information */
2304         dc->res_pool->funcs->populate_dml_writeback_from_context(dc, res_ctx, pipes);
2305
2306         return pipe_cnt;
2307 }
2308
2309 unsigned int dcn20_calc_max_scaled_time(
2310                 unsigned int time_per_pixel,
2311                 enum mmhubbub_wbif_mode mode,
2312                 unsigned int urgent_watermark)
2313 {
2314         unsigned int time_per_byte = 0;
2315         unsigned int total_y_free_entry = 0x200; /* two memory piece for luma */
2316         unsigned int total_c_free_entry = 0x140; /* two memory piece for chroma */
2317         unsigned int small_free_entry, max_free_entry;
2318         unsigned int buf_lh_capability;
2319         unsigned int max_scaled_time;
2320
2321         if (mode == PACKED_444) /* packed mode */
2322                 time_per_byte = time_per_pixel/4;
2323         else if (mode == PLANAR_420_8BPC)
2324                 time_per_byte  = time_per_pixel;
2325         else if (mode == PLANAR_420_10BPC) /* p010 */
2326                 time_per_byte  = time_per_pixel * 819/1024;
2327
2328         if (time_per_byte == 0)
2329                 time_per_byte = 1;
2330
2331         small_free_entry  = (total_y_free_entry > total_c_free_entry) ? total_c_free_entry : total_y_free_entry;
2332         max_free_entry    = (mode == PACKED_444) ? total_y_free_entry + total_c_free_entry : small_free_entry;
2333         buf_lh_capability = max_free_entry*time_per_byte*32/16; /* there is 4bit fraction */
2334         max_scaled_time   = buf_lh_capability - urgent_watermark;
2335         return max_scaled_time;
2336 }
2337
2338 void dcn20_set_mcif_arb_params(
2339                 struct dc *dc,
2340                 struct dc_state *context,
2341                 display_e2e_pipe_params_st *pipes,
2342                 int pipe_cnt)
2343 {
2344         enum mmhubbub_wbif_mode wbif_mode;
2345         struct mcif_arb_params *wb_arb_params;
2346         int i, j, k, dwb_pipe;
2347
2348         /* Writeback MCIF_WB arbitration parameters */
2349         dwb_pipe = 0;
2350         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2351
2352                 if (!context->res_ctx.pipe_ctx[i].stream)
2353                         continue;
2354
2355                 for (j = 0; j < MAX_DWB_PIPES; j++) {
2356                         if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].wb_enabled == false)
2357                                 continue;
2358
2359                         //wb_arb_params = &context->res_ctx.pipe_ctx[i].stream->writeback_info[j].mcif_arb_params;
2360                         wb_arb_params = &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[dwb_pipe];
2361
2362                         if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].dwb_params.out_format == dwb_scaler_mode_yuv420) {
2363                                 if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].dwb_params.output_depth == DWB_OUTPUT_PIXEL_DEPTH_8BPC)
2364                                         wbif_mode = PLANAR_420_8BPC;
2365                                 else
2366                                         wbif_mode = PLANAR_420_10BPC;
2367                         } else
2368                                 wbif_mode = PACKED_444;
2369
2370                         for (k = 0; k < sizeof(wb_arb_params->cli_watermark)/sizeof(wb_arb_params->cli_watermark[0]); k++) {
2371                                 wb_arb_params->cli_watermark[k] = get_wm_writeback_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2372                                 wb_arb_params->pstate_watermark[k] = get_wm_writeback_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2373                         }
2374                         wb_arb_params->time_per_pixel = 16.0 / context->res_ctx.pipe_ctx[i].stream->phy_pix_clk; /* 4 bit fraction, ms */
2375                         wb_arb_params->slice_lines = 32;
2376                         wb_arb_params->arbitration_slice = 2;
2377                         wb_arb_params->max_scaled_time = dcn20_calc_max_scaled_time(wb_arb_params->time_per_pixel,
2378                                 wbif_mode,
2379                                 wb_arb_params->cli_watermark[0]); /* assume 4 watermark sets have the same value */
2380
2381                         dwb_pipe++;
2382
2383                         if (dwb_pipe >= MAX_DWB_PIPES)
2384                                 return;
2385                 }
2386                 if (dwb_pipe >= MAX_DWB_PIPES)
2387                         return;
2388         }
2389 }
2390
2391 bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx)
2392 {
2393         int i;
2394
2395         /* Validate DSC config, dsc count validation is already done */
2396         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2397                 struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[i];
2398                 struct dc_stream_state *stream = pipe_ctx->stream;
2399                 struct dsc_config dsc_cfg;
2400                 struct pipe_ctx *odm_pipe;
2401                 int opp_cnt = 1;
2402
2403                 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
2404                         opp_cnt++;
2405
2406                 /* Only need to validate top pipe */
2407                 if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe || !stream || !stream->timing.flags.DSC)
2408                         continue;
2409
2410                 dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left
2411                                 + stream->timing.h_border_right) / opp_cnt;
2412                 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top
2413                                 + stream->timing.v_border_bottom;
2414                 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding;
2415                 dsc_cfg.color_depth = stream->timing.display_color_depth;
2416                 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;
2417                 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt;
2418
2419                 if (!pipe_ctx->stream_res.dsc->funcs->dsc_validate_stream(pipe_ctx->stream_res.dsc, &dsc_cfg))
2420                         return false;
2421         }
2422         return true;
2423 }
2424
2425 struct pipe_ctx *dcn20_find_secondary_pipe(struct dc *dc,
2426                 struct resource_context *res_ctx,
2427                 const struct resource_pool *pool,
2428                 const struct pipe_ctx *primary_pipe)
2429 {
2430         struct pipe_ctx *secondary_pipe = NULL;
2431
2432         if (dc && primary_pipe) {
2433                 int j;
2434                 int preferred_pipe_idx = 0;
2435
2436                 /* first check the prev dc state:
2437                  * if this primary pipe has a bottom pipe in prev. state
2438                  * and if the bottom pipe is still available (which it should be),
2439                  * pick that pipe as secondary
2440                  * Same logic applies for ODM pipes. Since mpo is not allowed with odm
2441                  * check in else case.
2442                  */
2443                 if (dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].bottom_pipe) {
2444                         preferred_pipe_idx = dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].bottom_pipe->pipe_idx;
2445                         if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
2446                                 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
2447                                 secondary_pipe->pipe_idx = preferred_pipe_idx;
2448                         }
2449                 } else if (dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].next_odm_pipe) {
2450                         preferred_pipe_idx = dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].next_odm_pipe->pipe_idx;
2451                         if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
2452                                 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
2453                                 secondary_pipe->pipe_idx = preferred_pipe_idx;
2454                         }
2455                 }
2456
2457                 /*
2458                  * if this primary pipe does not have a bottom pipe in prev. state
2459                  * start backward and find a pipe that did not used to be a bottom pipe in
2460                  * prev. dc state. This way we make sure we keep the same assignment as
2461                  * last state and will not have to reprogram every pipe
2462                  */
2463                 if (secondary_pipe == NULL) {
2464                         for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) {
2465                                 if (dc->current_state->res_ctx.pipe_ctx[j].top_pipe == NULL
2466                                                 && dc->current_state->res_ctx.pipe_ctx[j].prev_odm_pipe == NULL) {
2467                                         preferred_pipe_idx = j;
2468
2469                                         if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
2470                                                 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
2471                                                 secondary_pipe->pipe_idx = preferred_pipe_idx;
2472                                                 break;
2473                                         }
2474                                 }
2475                         }
2476                 }
2477                 /*
2478                  * We should never hit this assert unless assignments are shuffled around
2479                  * if this happens we will prob. hit a vsync tdr
2480                  */
2481                 ASSERT(secondary_pipe);
2482                 /*
2483                  * search backwards for the second pipe to keep pipe
2484                  * assignment more consistent
2485                  */
2486                 if (secondary_pipe == NULL) {
2487                         for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) {
2488                                 preferred_pipe_idx = j;
2489
2490                                 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
2491                                         secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
2492                                         secondary_pipe->pipe_idx = preferred_pipe_idx;
2493                                         break;
2494                                 }
2495                         }
2496                 }
2497         }
2498
2499         return secondary_pipe;
2500 }
2501
2502 void dcn20_merge_pipes_for_validate(
2503                 struct dc *dc,
2504                 struct dc_state *context)
2505 {
2506         int i;
2507
2508         /* merge previously split odm pipes since mode support needs to make the decision */
2509         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2510                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2511                 struct pipe_ctx *odm_pipe = pipe->next_odm_pipe;
2512
2513                 if (pipe->prev_odm_pipe)
2514                         continue;
2515
2516                 pipe->next_odm_pipe = NULL;
2517                 while (odm_pipe) {
2518                         struct pipe_ctx *next_odm_pipe = odm_pipe->next_odm_pipe;
2519
2520                         odm_pipe->plane_state = NULL;
2521                         odm_pipe->stream = NULL;
2522                         odm_pipe->top_pipe = NULL;
2523                         odm_pipe->bottom_pipe = NULL;
2524                         odm_pipe->prev_odm_pipe = NULL;
2525                         odm_pipe->next_odm_pipe = NULL;
2526                         if (odm_pipe->stream_res.dsc)
2527                                 release_dsc(&context->res_ctx, dc->res_pool, &odm_pipe->stream_res.dsc);
2528                         /* Clear plane_res and stream_res */
2529                         memset(&odm_pipe->plane_res, 0, sizeof(odm_pipe->plane_res));
2530                         memset(&odm_pipe->stream_res, 0, sizeof(odm_pipe->stream_res));
2531                         odm_pipe = next_odm_pipe;
2532                 }
2533                 if (pipe->plane_state)
2534                         resource_build_scaling_params(pipe);
2535         }
2536
2537         /* merge previously mpc split pipes since mode support needs to make the decision */
2538         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2539                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2540                 struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;
2541
2542                 if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state)
2543                         continue;
2544
2545                 pipe->bottom_pipe = hsplit_pipe->bottom_pipe;
2546                 if (hsplit_pipe->bottom_pipe)
2547                         hsplit_pipe->bottom_pipe->top_pipe = pipe;
2548                 hsplit_pipe->plane_state = NULL;
2549                 hsplit_pipe->stream = NULL;
2550                 hsplit_pipe->top_pipe = NULL;
2551                 hsplit_pipe->bottom_pipe = NULL;
2552
2553                 /* Clear plane_res and stream_res */
2554                 memset(&hsplit_pipe->plane_res, 0, sizeof(hsplit_pipe->plane_res));
2555                 memset(&hsplit_pipe->stream_res, 0, sizeof(hsplit_pipe->stream_res));
2556                 if (pipe->plane_state)
2557                         resource_build_scaling_params(pipe);
2558         }
2559 }
2560
2561 int dcn20_validate_apply_pipe_split_flags(
2562                 struct dc *dc,
2563                 struct dc_state *context,
2564                 int vlevel,
2565                 bool *split)
2566 {
2567         int i, pipe_idx, vlevel_split;
2568         bool force_split = false;
2569         bool avoid_split = dc->debug.pipe_split_policy != MPC_SPLIT_DYNAMIC;
2570
2571         /* Single display loop, exits if there is more than one display */
2572         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2573                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2574                 bool exit_loop = false;
2575
2576                 if (!pipe->stream || pipe->top_pipe)
2577                         continue;
2578
2579                 if (dc->debug.force_single_disp_pipe_split) {
2580                         if (!force_split)
2581                                 force_split = true;
2582                         else {
2583                                 force_split = false;
2584                                 exit_loop = true;
2585                         }
2586                 }
2587                 if (dc->debug.pipe_split_policy == MPC_SPLIT_AVOID_MULT_DISP) {
2588                         if (avoid_split)
2589                                 avoid_split = false;
2590                         else {
2591                                 avoid_split = true;
2592                                 exit_loop = true;
2593                         }
2594                 }
2595                 if (exit_loop)
2596                         break;
2597         }
2598         /* TODO: fix dc bugs and remove this split threshold thing */
2599         if (context->stream_count > dc->res_pool->pipe_count / 2)
2600                 avoid_split = true;
2601
2602         /* Avoid split loop looks for lowest voltage level that allows most unsplit pipes possible */
2603         if (avoid_split) {
2604                 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
2605                         if (!context->res_ctx.pipe_ctx[i].stream)
2606                                 continue;
2607
2608                         for (vlevel_split = vlevel; vlevel <= context->bw_ctx.dml.soc.num_states; vlevel++)
2609                                 if (context->bw_ctx.dml.vba.NoOfDPP[vlevel][0][pipe_idx] == 1)
2610                                         break;
2611                         /* Impossible to not split this pipe */
2612                         if (vlevel > context->bw_ctx.dml.soc.num_states)
2613                                 vlevel = vlevel_split;
2614                         pipe_idx++;
2615                 }
2616                 context->bw_ctx.dml.vba.maxMpcComb = 0;
2617         }
2618
2619         /* Split loop sets which pipe should be split based on dml outputs and dc flags */
2620         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
2621                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2622
2623                 if (!context->res_ctx.pipe_ctx[i].stream)
2624                         continue;
2625
2626                 if (force_split || context->bw_ctx.dml.vba.NoOfDPP[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] > 1)
2627                         split[i] = true;
2628                 if ((pipe->stream->view_format ==
2629                                 VIEW_3D_FORMAT_SIDE_BY_SIDE ||
2630                                 pipe->stream->view_format ==
2631                                 VIEW_3D_FORMAT_TOP_AND_BOTTOM) &&
2632                                 (pipe->stream->timing.timing_3d_format ==
2633                                 TIMING_3D_FORMAT_TOP_AND_BOTTOM ||
2634                                  pipe->stream->timing.timing_3d_format ==
2635                                 TIMING_3D_FORMAT_SIDE_BY_SIDE))
2636                         split[i] = true;
2637                 if (dc->debug.force_odm_combine & (1 << pipe->stream_res.tg->inst)) {
2638                         split[i] = true;
2639                         context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_idx] = dm_odm_combine_mode_2to1;
2640                 }
2641                 context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx] =
2642                         context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_idx];
2643                 /* Adjust dppclk when split is forced, do not bother with dispclk */
2644                 if (split[i] && context->bw_ctx.dml.vba.NoOfDPP[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] == 1)
2645                         context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] /= 2;
2646                 pipe_idx++;
2647         }
2648
2649         return vlevel;
2650 }
2651
2652 bool dcn20_fast_validate_bw(
2653                 struct dc *dc,
2654                 struct dc_state *context,
2655                 display_e2e_pipe_params_st *pipes,
2656                 int *pipe_cnt_out,
2657                 int *pipe_split_from,
2658                 int *vlevel_out)
2659 {
2660         bool out = false;
2661         bool split[MAX_PIPES] = { false };
2662         int pipe_cnt, i, pipe_idx, vlevel;
2663
2664         ASSERT(pipes);
2665         if (!pipes)
2666                 return false;
2667
2668         dcn20_merge_pipes_for_validate(dc, context);
2669
2670         pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes);
2671
2672         *pipe_cnt_out = pipe_cnt;
2673
2674         if (!pipe_cnt) {
2675                 out = true;
2676                 goto validate_out;
2677         }
2678
2679         vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
2680
2681         if (vlevel > context->bw_ctx.dml.soc.num_states)
2682                 goto validate_fail;
2683
2684         vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split);
2685
2686         /*initialize pipe_just_split_from to invalid idx*/
2687         for (i = 0; i < MAX_PIPES; i++)
2688                 pipe_split_from[i] = -1;
2689
2690         for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) {
2691                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2692                 struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;
2693
2694                 if (!pipe->stream || pipe_split_from[i] >= 0)
2695                         continue;
2696
2697                 pipe_idx++;
2698
2699                 if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {
2700                         hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);
2701                         ASSERT(hsplit_pipe);
2702                         if (!dcn20_split_stream_for_odm(
2703                                         &context->res_ctx, dc->res_pool,
2704                                         pipe, hsplit_pipe))
2705                                 goto validate_fail;
2706                         pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx;
2707                         dcn20_build_mapped_resource(dc, context, pipe->stream);
2708                 }
2709
2710                 if (!pipe->plane_state)
2711                         continue;
2712                 /* Skip 2nd half of already split pipe */
2713                 if (pipe->top_pipe && pipe->plane_state == pipe->top_pipe->plane_state)
2714                         continue;
2715
2716                 /* We do not support mpo + odm at the moment */
2717                 if (hsplit_pipe && hsplit_pipe->plane_state != pipe->plane_state
2718                                 && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx])
2719                         goto validate_fail;
2720
2721                 if (split[i]) {
2722                         if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state) {
2723                                 /* pipe not split previously needs split */
2724                                 hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);
2725                                 ASSERT(hsplit_pipe);
2726                                 if (!hsplit_pipe) {
2727                                         context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] *= 2;
2728                                         continue;
2729                                 }
2730                                 if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {
2731                                         if (!dcn20_split_stream_for_odm(
2732                                                         &context->res_ctx, dc->res_pool,
2733                                                         pipe, hsplit_pipe))
2734                                                 goto validate_fail;
2735                                         dcn20_build_mapped_resource(dc, context, pipe->stream);
2736                                 } else
2737                                         dcn20_split_stream_for_mpc(
2738                                                 &context->res_ctx, dc->res_pool,
2739                                                 pipe, hsplit_pipe);
2740                                 pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx;
2741                         }
2742                 } else if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) {
2743                         /* merge should already have been done */
2744                         ASSERT(0);
2745                 }
2746         }
2747         /* Actual dsc count per stream dsc validation*/
2748         if (!dcn20_validate_dsc(dc, context)) {
2749                 context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] =
2750                                 DML_FAIL_DSC_VALIDATION_FAILURE;
2751                 goto validate_fail;
2752         }
2753
2754         *vlevel_out = vlevel;
2755
2756         out = true;
2757         goto validate_out;
2758
2759 validate_fail:
2760         out = false;
2761
2762 validate_out:
2763         return out;
2764 }
2765
2766 static void dcn20_calculate_wm(
2767                 struct dc *dc, struct dc_state *context,
2768                 display_e2e_pipe_params_st *pipes,
2769                 int *out_pipe_cnt,
2770                 int *pipe_split_from,
2771                 int vlevel)
2772 {
2773         int pipe_cnt, i, pipe_idx;
2774
2775         for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
2776                 if (!context->res_ctx.pipe_ctx[i].stream)
2777                         continue;
2778
2779                 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
2780                 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
2781
2782                 if (pipe_split_from[i] < 0) {
2783                         pipes[pipe_cnt].clks_cfg.dppclk_mhz =
2784                                         context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx];
2785                         if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx)
2786                                 pipes[pipe_cnt].pipe.dest.odm_combine =
2787                                                 context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx];
2788                         else
2789                                 pipes[pipe_cnt].pipe.dest.odm_combine = 0;
2790                         pipe_idx++;
2791                 } else {
2792                         pipes[pipe_cnt].clks_cfg.dppclk_mhz =
2793                                         context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]];
2794                         if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_split_from[i]] == pipe_split_from[i])
2795                                 pipes[pipe_cnt].pipe.dest.odm_combine =
2796                                                 context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_split_from[i]];
2797                         else
2798                                 pipes[pipe_cnt].pipe.dest.odm_combine = 0;
2799                 }
2800
2801                 if (dc->config.forced_clocks) {
2802                         pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz;
2803                         pipes[pipe_cnt].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz;
2804                 }
2805                 if (dc->debug.min_disp_clk_khz > pipes[pipe_cnt].clks_cfg.dispclk_mhz * 1000)
2806                         pipes[pipe_cnt].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0;
2807                 if (dc->debug.min_dpp_clk_khz > pipes[pipe_cnt].clks_cfg.dppclk_mhz * 1000)
2808                         pipes[pipe_cnt].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0;
2809
2810                 pipe_cnt++;
2811         }
2812
2813         if (pipe_cnt != pipe_idx) {
2814                 if (dc->res_pool->funcs->populate_dml_pipes)
2815                         pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,
2816                                 context, pipes);
2817                 else
2818                         pipe_cnt = dcn20_populate_dml_pipes_from_context(dc,
2819                                 context, pipes);
2820         }
2821
2822         *out_pipe_cnt = pipe_cnt;
2823
2824         pipes[0].clks_cfg.voltage = vlevel;
2825         pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz;
2826         pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
2827
2828         /* only pipe 0 is read for voltage and dcf/soc clocks */
2829         if (vlevel < 1) {
2830                 pipes[0].clks_cfg.voltage = 1;
2831                 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].dcfclk_mhz;
2832                 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].socclk_mhz;
2833         }
2834         context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2835         context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2836         context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2837         context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2838         context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2839         context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2840         context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2841         context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2842
2843         if (vlevel < 2) {
2844                 pipes[0].clks_cfg.voltage = 2;
2845                 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz;
2846                 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz;
2847         }
2848         context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2849         context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2850         context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2851         context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2852         context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2853         context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2854         context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2855
2856         if (vlevel < 3) {
2857                 pipes[0].clks_cfg.voltage = 3;
2858                 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz;
2859                 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz;
2860         }
2861         context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2862         context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2863         context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2864         context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2865         context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2866         context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2867         context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2868
2869         pipes[0].clks_cfg.voltage = vlevel;
2870         pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz;
2871         pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
2872         context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2873         context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2874         context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2875         context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2876         context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2877         context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2878         context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2879 }
2880
2881 void dcn20_calculate_dlg_params(
2882                 struct dc *dc, struct dc_state *context,
2883                 display_e2e_pipe_params_st *pipes,
2884                 int pipe_cnt,
2885                 int vlevel)
2886 {
2887         int i, j, pipe_idx, pipe_idx_unsplit;
2888         bool visited[MAX_PIPES] = { 0 };
2889
2890         /* Writeback MCIF_WB arbitration parameters */
2891         dc->res_pool->funcs->set_mcif_arb_params(dc, context, pipes, pipe_cnt);
2892
2893         context->bw_ctx.bw.dcn.clk.dispclk_khz = context->bw_ctx.dml.vba.DISPCLK * 1000;
2894         context->bw_ctx.bw.dcn.clk.dcfclk_khz = context->bw_ctx.dml.vba.DCFCLK * 1000;
2895         context->bw_ctx.bw.dcn.clk.socclk_khz = context->bw_ctx.dml.vba.SOCCLK * 1000;
2896         context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16;
2897         context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = context->bw_ctx.dml.vba.DCFCLKDeepSleep * 1000;
2898         context->bw_ctx.bw.dcn.clk.fclk_khz = context->bw_ctx.dml.vba.FabricClock * 1000;
2899         context->bw_ctx.bw.dcn.clk.p_state_change_support =
2900                 context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb]
2901                                                         != dm_dram_clock_change_unsupported;
2902         context->bw_ctx.bw.dcn.clk.dppclk_khz = 0;
2903
2904         /*
2905          * An artifact of dml pipe split/odm is that pipes get merged back together for
2906          * calculation. Therefore we need to only extract for first pipe in ascending index order
2907          * and copy into the other split half.
2908          */
2909         for (i = 0, pipe_idx = 0, pipe_idx_unsplit = 0; i < dc->res_pool->pipe_count; i++) {
2910                 if (!context->res_ctx.pipe_ctx[i].stream)
2911                         continue;
2912
2913                 if (!visited[pipe_idx]) {
2914                         display_pipe_source_params_st *src = &pipes[pipe_idx].pipe.src;
2915                         display_pipe_dest_params_st *dst = &pipes[pipe_idx].pipe.dest;
2916
2917                         dst->vstartup_start = context->bw_ctx.dml.vba.VStartup[pipe_idx_unsplit];
2918                         dst->vupdate_offset = context->bw_ctx.dml.vba.VUpdateOffsetPix[pipe_idx_unsplit];
2919                         dst->vupdate_width = context->bw_ctx.dml.vba.VUpdateWidthPix[pipe_idx_unsplit];
2920                         dst->vready_offset = context->bw_ctx.dml.vba.VReadyOffsetPix[pipe_idx_unsplit];
2921                         /*
2922                          * j iterates inside pipes array, unlike i which iterates inside
2923                          * pipe_ctx array
2924                          */
2925                         if (src->is_hsplit)
2926                                 for (j = pipe_idx + 1; j < pipe_cnt; j++) {
2927                                         display_pipe_source_params_st *src_j = &pipes[j].pipe.src;
2928                                         display_pipe_dest_params_st *dst_j = &pipes[j].pipe.dest;
2929
2930                                         if (src_j->is_hsplit && !visited[j]
2931                                                         && src->hsplit_grp == src_j->hsplit_grp) {
2932                                                 dst_j->vstartup_start = context->bw_ctx.dml.vba.VStartup[pipe_idx_unsplit];
2933                                                 dst_j->vupdate_offset = context->bw_ctx.dml.vba.VUpdateOffsetPix[pipe_idx_unsplit];
2934                                                 dst_j->vupdate_width = context->bw_ctx.dml.vba.VUpdateWidthPix[pipe_idx_unsplit];
2935                                                 dst_j->vready_offset = context->bw_ctx.dml.vba.VReadyOffsetPix[pipe_idx_unsplit];
2936                                                 visited[j] = true;
2937                                         }
2938                                 }
2939                         visited[pipe_idx] = true;
2940                         pipe_idx_unsplit++;
2941                 }
2942                 pipe_idx++;
2943         }
2944
2945         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
2946                 if (!context->res_ctx.pipe_ctx[i].stream)
2947                         continue;
2948                 if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)
2949                         context->bw_ctx.bw.dcn.clk.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
2950                 context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz =
2951                                                 pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
2952                 ASSERT(visited[pipe_idx]);
2953                 context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest;
2954                 pipe_idx++;
2955         }
2956         /*save a original dppclock copy*/
2957         context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz;
2958         context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz;
2959         context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dppclk_mhz * 1000;
2960         context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dispclk_mhz * 1000;
2961
2962         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
2963                 bool cstate_en = context->bw_ctx.dml.vba.PrefetchMode[vlevel][context->bw_ctx.dml.vba.maxMpcComb] != 2;
2964
2965                 if (!context->res_ctx.pipe_ctx[i].stream)
2966                         continue;
2967
2968                 context->bw_ctx.dml.funcs.rq_dlg_get_dlg_reg(&context->bw_ctx.dml,
2969                                 &context->res_ctx.pipe_ctx[i].dlg_regs,
2970                                 &context->res_ctx.pipe_ctx[i].ttu_regs,
2971                                 pipes,
2972                                 pipe_cnt,
2973                                 pipe_idx,
2974                                 cstate_en,
2975                                 context->bw_ctx.bw.dcn.clk.p_state_change_support,
2976                                 false, false, false);
2977
2978                 context->bw_ctx.dml.funcs.rq_dlg_get_rq_reg(&context->bw_ctx.dml,
2979                                 &context->res_ctx.pipe_ctx[i].rq_regs,
2980                                 pipes[pipe_idx].pipe);
2981                 pipe_idx++;
2982         }
2983 }
2984
2985 static bool dcn20_validate_bandwidth_internal(struct dc *dc, struct dc_state *context,
2986                 bool fast_validate)
2987 {
2988         bool out = false;
2989
2990         BW_VAL_TRACE_SETUP();
2991
2992         int vlevel = 0;
2993         int pipe_split_from[MAX_PIPES];
2994         int pipe_cnt = 0;
2995         display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
2996         DC_LOGGER_INIT(dc->ctx->logger);
2997
2998         BW_VAL_TRACE_COUNT();
2999
3000         out = dcn20_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel);
3001
3002         if (pipe_cnt == 0)
3003                 goto validate_out;
3004
3005         if (!out)
3006                 goto validate_fail;
3007
3008         BW_VAL_TRACE_END_VOLTAGE_LEVEL();
3009
3010         if (fast_validate) {
3011                 BW_VAL_TRACE_SKIP(fast);
3012                 goto validate_out;
3013         }
3014
3015         dcn20_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel);
3016         dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
3017
3018         BW_VAL_TRACE_END_WATERMARKS();
3019
3020         goto validate_out;
3021
3022 validate_fail:
3023         DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
3024                 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
3025
3026         BW_VAL_TRACE_SKIP(fail);
3027         out = false;
3028
3029 validate_out:
3030         kfree(pipes);
3031
3032         BW_VAL_TRACE_FINISH();
3033
3034         return out;
3035 }
3036
3037
3038 bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context,
3039                 bool fast_validate)
3040 {
3041         bool voltage_supported = false;
3042         bool full_pstate_supported = false;
3043         bool dummy_pstate_supported = false;
3044         double p_state_latency_us;
3045
3046         DC_FP_START();
3047         p_state_latency_us = context->bw_ctx.dml.soc.dram_clock_change_latency_us;
3048         context->bw_ctx.dml.soc.disable_dram_clock_change_vactive_support =
3049                 dc->debug.disable_dram_clock_change_vactive_support;
3050
3051         if (fast_validate) {
3052                 voltage_supported = dcn20_validate_bandwidth_internal(dc, context, true);
3053
3054                 DC_FP_END();
3055                 return voltage_supported;
3056         }
3057
3058         // Best case, we support full UCLK switch latency
3059         voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false);
3060         full_pstate_supported = context->bw_ctx.bw.dcn.clk.p_state_change_support;
3061
3062         if (context->bw_ctx.dml.soc.dummy_pstate_latency_us == 0 ||
3063                 (voltage_supported && full_pstate_supported)) {
3064                 context->bw_ctx.bw.dcn.clk.p_state_change_support = full_pstate_supported;
3065                 goto restore_dml_state;
3066         }
3067
3068         // Fallback: Try to only support G6 temperature read latency
3069         context->bw_ctx.dml.soc.dram_clock_change_latency_us = context->bw_ctx.dml.soc.dummy_pstate_latency_us;
3070
3071         voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false);
3072         dummy_pstate_supported = context->bw_ctx.bw.dcn.clk.p_state_change_support;
3073
3074         if (voltage_supported && dummy_pstate_supported) {
3075                 context->bw_ctx.bw.dcn.clk.p_state_change_support = false;
3076                 goto restore_dml_state;
3077         }
3078
3079         // ERROR: fallback is supposed to always work.
3080         ASSERT(false);
3081
3082 restore_dml_state:
3083         context->bw_ctx.dml.soc.dram_clock_change_latency_us = p_state_latency_us;
3084
3085         DC_FP_END();
3086         return voltage_supported;
3087 }
3088
3089 struct pipe_ctx *dcn20_acquire_idle_pipe_for_layer(
3090                 struct dc_state *state,
3091                 const struct resource_pool *pool,
3092                 struct dc_stream_state *stream)
3093 {
3094         struct resource_context *res_ctx = &state->res_ctx;
3095         struct pipe_ctx *head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream);
3096         struct pipe_ctx *idle_pipe = find_idle_secondary_pipe(res_ctx, pool, head_pipe);
3097
3098         if (!head_pipe)
3099                 ASSERT(0);
3100
3101         if (!idle_pipe)
3102                 return NULL;
3103
3104         idle_pipe->stream = head_pipe->stream;
3105         idle_pipe->stream_res.tg = head_pipe->stream_res.tg;
3106         idle_pipe->stream_res.opp = head_pipe->stream_res.opp;
3107
3108         idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx];
3109         idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx];
3110         idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx];
3111         idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst;
3112
3113         return idle_pipe;
3114 }
3115
3116 bool dcn20_get_dcc_compression_cap(const struct dc *dc,
3117                 const struct dc_dcc_surface_param *input,
3118                 struct dc_surface_dcc_cap *output)
3119 {
3120         return dc->res_pool->hubbub->funcs->get_dcc_compression_cap(
3121                         dc->res_pool->hubbub,
3122                         input,
3123                         output);
3124 }
3125
3126 static void dcn20_destroy_resource_pool(struct resource_pool **pool)
3127 {
3128         struct dcn20_resource_pool *dcn20_pool = TO_DCN20_RES_POOL(*pool);
3129
3130         dcn20_resource_destruct(dcn20_pool);
3131         kfree(dcn20_pool);
3132         *pool = NULL;
3133 }
3134
3135
3136 static struct dc_cap_funcs cap_funcs = {
3137         .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
3138 };
3139
3140
3141 enum dc_status dcn20_get_default_swizzle_mode(struct dc_plane_state *plane_state)
3142 {
3143         enum dc_status result = DC_OK;
3144
3145         enum surface_pixel_format surf_pix_format = plane_state->format;
3146         unsigned int bpp = resource_pixel_format_to_bpp(surf_pix_format);
3147
3148         enum swizzle_mode_values swizzle = DC_SW_LINEAR;
3149
3150         if (bpp == 64)
3151                 swizzle = DC_SW_64KB_D;
3152         else
3153                 swizzle = DC_SW_64KB_S;
3154
3155         plane_state->tiling_info.gfx9.swizzle = swizzle;
3156         return result;
3157 }
3158
3159 static struct resource_funcs dcn20_res_pool_funcs = {
3160         .destroy = dcn20_destroy_resource_pool,
3161         .link_enc_create = dcn20_link_encoder_create,
3162         .validate_bandwidth = dcn20_validate_bandwidth,
3163         .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
3164         .add_stream_to_ctx = dcn20_add_stream_to_ctx,
3165         .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
3166         .populate_dml_writeback_from_context = dcn20_populate_dml_writeback_from_context,
3167         .get_default_swizzle_mode = dcn20_get_default_swizzle_mode,
3168         .set_mcif_arb_params = dcn20_set_mcif_arb_params,
3169         .populate_dml_pipes = dcn20_populate_dml_pipes_from_context,
3170         .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link
3171 };
3172
3173 bool dcn20_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
3174 {
3175         int i;
3176         uint32_t pipe_count = pool->res_cap->num_dwb;
3177
3178         for (i = 0; i < pipe_count; i++) {
3179                 struct dcn20_dwbc *dwbc20 = kzalloc(sizeof(struct dcn20_dwbc),
3180                                                     GFP_KERNEL);
3181
3182                 if (!dwbc20) {
3183                         dm_error("DC: failed to create dwbc20!\n");
3184                         return false;
3185                 }
3186                 dcn20_dwbc_construct(dwbc20, ctx,
3187                                 &dwbc20_regs[i],
3188                                 &dwbc20_shift,
3189                                 &dwbc20_mask,
3190                                 i);
3191                 pool->dwbc[i] = &dwbc20->base;
3192         }
3193         return true;
3194 }
3195
3196 bool dcn20_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
3197 {
3198         int i;
3199         uint32_t pipe_count = pool->res_cap->num_dwb;
3200
3201         ASSERT(pipe_count > 0);
3202
3203         for (i = 0; i < pipe_count; i++) {
3204                 struct dcn20_mmhubbub *mcif_wb20 = kzalloc(sizeof(struct dcn20_mmhubbub),
3205                                                     GFP_KERNEL);
3206
3207                 if (!mcif_wb20) {
3208                         dm_error("DC: failed to create mcif_wb20!\n");
3209                         return false;
3210                 }
3211
3212                 dcn20_mmhubbub_construct(mcif_wb20, ctx,
3213                                 &mcif_wb20_regs[i],
3214                                 &mcif_wb20_shift,
3215                                 &mcif_wb20_mask,
3216                                 i);
3217
3218                 pool->mcif_wb[i] = &mcif_wb20->base;
3219         }
3220         return true;
3221 }
3222
3223 static struct pp_smu_funcs *dcn20_pp_smu_create(struct dc_context *ctx)
3224 {
3225         struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL);
3226
3227         if (!pp_smu)
3228                 return pp_smu;
3229
3230         dm_pp_get_funcs(ctx, pp_smu);
3231
3232         if (pp_smu->ctx.ver != PP_SMU_VER_NV)
3233                 pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs));
3234
3235         return pp_smu;
3236 }
3237
3238 static void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu)
3239 {
3240         if (pp_smu && *pp_smu) {
3241                 kfree(*pp_smu);
3242                 *pp_smu = NULL;
3243         }
3244 }
3245
3246 void dcn20_cap_soc_clocks(
3247                 struct _vcs_dpi_soc_bounding_box_st *bb,
3248                 struct pp_smu_nv_clock_table max_clocks)
3249 {
3250         int i;
3251
3252         // First pass - cap all clocks higher than the reported max
3253         for (i = 0; i < bb->num_states; i++) {
3254                 if ((bb->clock_limits[i].dcfclk_mhz > (max_clocks.dcfClockInKhz / 1000))
3255                                 && max_clocks.dcfClockInKhz != 0)
3256                         bb->clock_limits[i].dcfclk_mhz = (max_clocks.dcfClockInKhz / 1000);
3257
3258                 if ((bb->clock_limits[i].dram_speed_mts > (max_clocks.uClockInKhz / 1000) * 16)
3259                                                 && max_clocks.uClockInKhz != 0)
3260                         bb->clock_limits[i].dram_speed_mts = (max_clocks.uClockInKhz / 1000) * 16;
3261
3262                 if ((bb->clock_limits[i].fabricclk_mhz > (max_clocks.fabricClockInKhz / 1000))
3263                                                 && max_clocks.fabricClockInKhz != 0)
3264                         bb->clock_limits[i].fabricclk_mhz = (max_clocks.fabricClockInKhz / 1000);
3265
3266                 if ((bb->clock_limits[i].dispclk_mhz > (max_clocks.displayClockInKhz / 1000))
3267                                                 && max_clocks.displayClockInKhz != 0)
3268                         bb->clock_limits[i].dispclk_mhz = (max_clocks.displayClockInKhz / 1000);
3269
3270                 if ((bb->clock_limits[i].dppclk_mhz > (max_clocks.dppClockInKhz / 1000))
3271                                                 && max_clocks.dppClockInKhz != 0)
3272                         bb->clock_limits[i].dppclk_mhz = (max_clocks.dppClockInKhz / 1000);
3273
3274                 if ((bb->clock_limits[i].phyclk_mhz > (max_clocks.phyClockInKhz / 1000))
3275                                                 && max_clocks.phyClockInKhz != 0)
3276                         bb->clock_limits[i].phyclk_mhz = (max_clocks.phyClockInKhz / 1000);
3277
3278                 if ((bb->clock_limits[i].socclk_mhz > (max_clocks.socClockInKhz / 1000))
3279                                                 && max_clocks.socClockInKhz != 0)
3280                         bb->clock_limits[i].socclk_mhz = (max_clocks.socClockInKhz / 1000);
3281
3282                 if ((bb->clock_limits[i].dscclk_mhz > (max_clocks.dscClockInKhz / 1000))
3283                                                 && max_clocks.dscClockInKhz != 0)
3284                         bb->clock_limits[i].dscclk_mhz = (max_clocks.dscClockInKhz / 1000);
3285         }
3286
3287         // Second pass - remove all duplicate clock states
3288         for (i = bb->num_states - 1; i > 1; i--) {
3289                 bool duplicate = true;
3290
3291                 if (bb->clock_limits[i-1].dcfclk_mhz != bb->clock_limits[i].dcfclk_mhz)
3292                         duplicate = false;
3293                 if (bb->clock_limits[i-1].dispclk_mhz != bb->clock_limits[i].dispclk_mhz)
3294                         duplicate = false;
3295                 if (bb->clock_limits[i-1].dppclk_mhz != bb->clock_limits[i].dppclk_mhz)
3296                         duplicate = false;
3297                 if (bb->clock_limits[i-1].dram_speed_mts != bb->clock_limits[i].dram_speed_mts)
3298                         duplicate = false;
3299                 if (bb->clock_limits[i-1].dscclk_mhz != bb->clock_limits[i].dscclk_mhz)
3300                         duplicate = false;
3301                 if (bb->clock_limits[i-1].fabricclk_mhz != bb->clock_limits[i].fabricclk_mhz)
3302                         duplicate = false;
3303                 if (bb->clock_limits[i-1].phyclk_mhz != bb->clock_limits[i].phyclk_mhz)
3304                         duplicate = false;
3305                 if (bb->clock_limits[i-1].socclk_mhz != bb->clock_limits[i].socclk_mhz)
3306                         duplicate = false;
3307
3308                 if (duplicate)
3309                         bb->num_states--;
3310         }
3311 }
3312
3313 void dcn20_update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb,
3314                 struct pp_smu_nv_clock_table *max_clocks, unsigned int *uclk_states, unsigned int num_states)
3315 {
3316         struct _vcs_dpi_voltage_scaling_st calculated_states[MAX_CLOCK_LIMIT_STATES];
3317         int i;
3318         int num_calculated_states = 0;
3319         int min_dcfclk = 0;
3320
3321         if (num_states == 0)
3322                 return;
3323
3324         memset(calculated_states, 0, sizeof(calculated_states));
3325
3326         if (dc->bb_overrides.min_dcfclk_mhz > 0)
3327                 min_dcfclk = dc->bb_overrides.min_dcfclk_mhz;
3328         else {
3329                 if (ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev))
3330                         min_dcfclk = 310;
3331                 else
3332                         // Accounting for SOC/DCF relationship, we can go as high as
3333                         // 506Mhz in Vmin.
3334                         min_dcfclk = 506;
3335         }
3336
3337         for (i = 0; i < num_states; i++) {
3338                 int min_fclk_required_by_uclk;
3339                 calculated_states[i].state = i;
3340                 calculated_states[i].dram_speed_mts = uclk_states[i] * 16 / 1000;
3341
3342                 // FCLK:UCLK ratio is 1.08
3343                 min_fclk_required_by_uclk = mul_u64_u32_shr(BIT_ULL(32) * 1080 / 1000000, uclk_states[i], 32);
3344
3345                 calculated_states[i].fabricclk_mhz = (min_fclk_required_by_uclk < min_dcfclk) ?
3346                                 min_dcfclk : min_fclk_required_by_uclk;
3347
3348                 calculated_states[i].socclk_mhz = (calculated_states[i].fabricclk_mhz > max_clocks->socClockInKhz / 1000) ?
3349                                 max_clocks->socClockInKhz / 1000 : calculated_states[i].fabricclk_mhz;
3350
3351                 calculated_states[i].dcfclk_mhz = (calculated_states[i].fabricclk_mhz > max_clocks->dcfClockInKhz / 1000) ?
3352                                 max_clocks->dcfClockInKhz / 1000 : calculated_states[i].fabricclk_mhz;
3353
3354                 calculated_states[i].dispclk_mhz = max_clocks->displayClockInKhz / 1000;
3355                 calculated_states[i].dppclk_mhz = max_clocks->displayClockInKhz / 1000;
3356                 calculated_states[i].dscclk_mhz = max_clocks->displayClockInKhz / (1000 * 3);
3357
3358                 calculated_states[i].phyclk_mhz = max_clocks->phyClockInKhz / 1000;
3359
3360                 num_calculated_states++;
3361         }
3362
3363         calculated_states[num_calculated_states - 1].socclk_mhz = max_clocks->socClockInKhz / 1000;
3364         calculated_states[num_calculated_states - 1].fabricclk_mhz = max_clocks->socClockInKhz / 1000;
3365         calculated_states[num_calculated_states - 1].dcfclk_mhz = max_clocks->dcfClockInKhz / 1000;
3366
3367         memcpy(bb->clock_limits, calculated_states, sizeof(bb->clock_limits));
3368         bb->num_states = num_calculated_states;
3369
3370         // Duplicate the last state, DML always an extra state identical to max state to work
3371         memcpy(&bb->clock_limits[num_calculated_states], &bb->clock_limits[num_calculated_states - 1], sizeof(struct _vcs_dpi_voltage_scaling_st));
3372         bb->clock_limits[num_calculated_states].state = bb->num_states;
3373 }
3374
3375 void dcn20_patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb)
3376 {
3377         if ((int)(bb->sr_exit_time_us * 1000) != dc->bb_overrides.sr_exit_time_ns
3378                         && dc->bb_overrides.sr_exit_time_ns) {
3379                 bb->sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0;
3380         }
3381
3382         if ((int)(bb->sr_enter_plus_exit_time_us * 1000)
3383                                 != dc->bb_overrides.sr_enter_plus_exit_time_ns
3384                         && dc->bb_overrides.sr_enter_plus_exit_time_ns) {
3385                 bb->sr_enter_plus_exit_time_us =
3386                                 dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;
3387         }
3388
3389         if ((int)(bb->urgent_latency_us * 1000) != dc->bb_overrides.urgent_latency_ns
3390                         && dc->bb_overrides.urgent_latency_ns) {
3391                 bb->urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0;
3392         }
3393
3394         if ((int)(bb->dram_clock_change_latency_us * 1000)
3395                                 != dc->bb_overrides.dram_clock_change_latency_ns
3396                         && dc->bb_overrides.dram_clock_change_latency_ns) {
3397                 bb->dram_clock_change_latency_us =
3398                                 dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;
3399         }
3400 }
3401
3402 static struct _vcs_dpi_soc_bounding_box_st *get_asic_rev_soc_bb(
3403         uint32_t hw_internal_rev)
3404 {
3405         if (ASICREV_IS_NAVI14_M(hw_internal_rev))
3406                 return &dcn2_0_nv14_soc;
3407
3408         if (ASICREV_IS_NAVI12_P(hw_internal_rev))
3409                 return &dcn2_0_nv12_soc;
3410
3411         return &dcn2_0_soc;
3412 }
3413
3414 static struct _vcs_dpi_ip_params_st *get_asic_rev_ip_params(
3415         uint32_t hw_internal_rev)
3416 {
3417         /* NV14 */
3418         if (ASICREV_IS_NAVI14_M(hw_internal_rev))
3419                 return &dcn2_0_nv14_ip;
3420
3421         /* NV12 and NV10 */
3422         return &dcn2_0_ip;
3423 }
3424
3425 static enum dml_project get_dml_project_version(uint32_t hw_internal_rev)
3426 {
3427         return DML_PROJECT_NAVI10v2;
3428 }
3429
3430 #define fixed16_to_double(x) (((double) x) / ((double) (1 << 16)))
3431 #define fixed16_to_double_to_cpu(x) fixed16_to_double(le32_to_cpu(x))
3432
3433 static bool init_soc_bounding_box(struct dc *dc,
3434                                   struct dcn20_resource_pool *pool)
3435 {
3436         const struct gpu_info_soc_bounding_box_v1_0 *bb = dc->soc_bounding_box;
3437         struct _vcs_dpi_soc_bounding_box_st *loaded_bb =
3438                         get_asic_rev_soc_bb(dc->ctx->asic_id.hw_internal_rev);
3439         struct _vcs_dpi_ip_params_st *loaded_ip =
3440                         get_asic_rev_ip_params(dc->ctx->asic_id.hw_internal_rev);
3441
3442         DC_LOGGER_INIT(dc->ctx->logger);
3443
3444         /* TODO: upstream NV12 bounding box when its launched */
3445         if (!bb && ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev)) {
3446                 DC_LOG_ERROR("%s: not valid soc bounding box/n", __func__);
3447                 return false;
3448         }
3449
3450         if (bb && ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev)) {
3451                 int i;
3452
3453                 dcn2_0_nv12_soc.sr_exit_time_us =
3454                                 fixed16_to_double_to_cpu(bb->sr_exit_time_us);
3455                 dcn2_0_nv12_soc.sr_enter_plus_exit_time_us =
3456                                 fixed16_to_double_to_cpu(bb->sr_enter_plus_exit_time_us);
3457                 dcn2_0_nv12_soc.urgent_latency_us =
3458                                 fixed16_to_double_to_cpu(bb->urgent_latency_us);
3459                 dcn2_0_nv12_soc.urgent_latency_pixel_data_only_us =
3460                                 fixed16_to_double_to_cpu(bb->urgent_latency_pixel_data_only_us);
3461                 dcn2_0_nv12_soc.urgent_latency_pixel_mixed_with_vm_data_us =
3462                                 fixed16_to_double_to_cpu(bb->urgent_latency_pixel_mixed_with_vm_data_us);
3463                 dcn2_0_nv12_soc.urgent_latency_vm_data_only_us =
3464                                 fixed16_to_double_to_cpu(bb->urgent_latency_vm_data_only_us);
3465                 dcn2_0_nv12_soc.urgent_out_of_order_return_per_channel_pixel_only_bytes =
3466                                 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_pixel_only_bytes);
3467                 dcn2_0_nv12_soc.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes =
3468                                 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_pixel_and_vm_bytes);
3469                 dcn2_0_nv12_soc.urgent_out_of_order_return_per_channel_vm_only_bytes =
3470                                 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_vm_only_bytes);
3471                 dcn2_0_nv12_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only =
3472                                 fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_pixel_only);
3473                 dcn2_0_nv12_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm =
3474                                 fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm);
3475                 dcn2_0_nv12_soc.pct_ideal_dram_sdp_bw_after_urgent_vm_only =
3476                                 fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_vm_only);
3477                 dcn2_0_nv12_soc.max_avg_sdp_bw_use_normal_percent =
3478                                 fixed16_to_double_to_cpu(bb->max_avg_sdp_bw_use_normal_percent);
3479                 dcn2_0_nv12_soc.max_avg_dram_bw_use_normal_percent =
3480                                 fixed16_to_double_to_cpu(bb->max_avg_dram_bw_use_normal_percent);
3481                 dcn2_0_nv12_soc.writeback_latency_us =
3482                                 fixed16_to_double_to_cpu(bb->writeback_latency_us);
3483                 dcn2_0_nv12_soc.ideal_dram_bw_after_urgent_percent =
3484                                 fixed16_to_double_to_cpu(bb->ideal_dram_bw_after_urgent_percent);
3485                 dcn2_0_nv12_soc.max_request_size_bytes =
3486                                 le32_to_cpu(bb->max_request_size_bytes);
3487                 dcn2_0_nv12_soc.dram_channel_width_bytes =
3488                                 le32_to_cpu(bb->dram_channel_width_bytes);
3489                 dcn2_0_nv12_soc.fabric_datapath_to_dcn_data_return_bytes =
3490                                 le32_to_cpu(bb->fabric_datapath_to_dcn_data_return_bytes);
3491                 dcn2_0_nv12_soc.dcn_downspread_percent =
3492                                 fixed16_to_double_to_cpu(bb->dcn_downspread_percent);
3493                 dcn2_0_nv12_soc.downspread_percent =
3494                                 fixed16_to_double_to_cpu(bb->downspread_percent);
3495                 dcn2_0_nv12_soc.dram_page_open_time_ns =
3496                                 fixed16_to_double_to_cpu(bb->dram_page_open_time_ns);
3497                 dcn2_0_nv12_soc.dram_rw_turnaround_time_ns =
3498                                 fixed16_to_double_to_cpu(bb->dram_rw_turnaround_time_ns);
3499                 dcn2_0_nv12_soc.dram_return_buffer_per_channel_bytes =
3500                                 le32_to_cpu(bb->dram_return_buffer_per_channel_bytes);
3501                 dcn2_0_nv12_soc.round_trip_ping_latency_dcfclk_cycles =
3502                                 le32_to_cpu(bb->round_trip_ping_latency_dcfclk_cycles);
3503                 dcn2_0_nv12_soc.urgent_out_of_order_return_per_channel_bytes =
3504                                 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_bytes);
3505                 dcn2_0_nv12_soc.channel_interleave_bytes =
3506                                 le32_to_cpu(bb->channel_interleave_bytes);
3507                 dcn2_0_nv12_soc.num_banks =
3508                                 le32_to_cpu(bb->num_banks);
3509                 dcn2_0_nv12_soc.num_chans =
3510                                 le32_to_cpu(bb->num_chans);
3511                 dcn2_0_nv12_soc.vmm_page_size_bytes =
3512                                 le32_to_cpu(bb->vmm_page_size_bytes);
3513                 dcn2_0_nv12_soc.dram_clock_change_latency_us =
3514                                 fixed16_to_double_to_cpu(bb->dram_clock_change_latency_us);
3515                 // HACK!! Lower uclock latency switch time so we don't switch
3516                 dcn2_0_nv12_soc.dram_clock_change_latency_us = 10;
3517                 dcn2_0_nv12_soc.writeback_dram_clock_change_latency_us =
3518                                 fixed16_to_double_to_cpu(bb->writeback_dram_clock_change_latency_us);
3519                 dcn2_0_nv12_soc.return_bus_width_bytes =
3520                                 le32_to_cpu(bb->return_bus_width_bytes);
3521                 dcn2_0_nv12_soc.dispclk_dppclk_vco_speed_mhz =
3522                                 le32_to_cpu(bb->dispclk_dppclk_vco_speed_mhz);
3523                 dcn2_0_nv12_soc.xfc_bus_transport_time_us =
3524                                 le32_to_cpu(bb->xfc_bus_transport_time_us);
3525                 dcn2_0_nv12_soc.xfc_xbuf_latency_tolerance_us =
3526                                 le32_to_cpu(bb->xfc_xbuf_latency_tolerance_us);
3527                 dcn2_0_nv12_soc.use_urgent_burst_bw =
3528                                 le32_to_cpu(bb->use_urgent_burst_bw);
3529                 dcn2_0_nv12_soc.num_states =
3530                                 le32_to_cpu(bb->num_states);
3531
3532                 for (i = 0; i < dcn2_0_nv12_soc.num_states; i++) {
3533                         dcn2_0_nv12_soc.clock_limits[i].state =
3534                                         le32_to_cpu(bb->clock_limits[i].state);
3535                         dcn2_0_nv12_soc.clock_limits[i].dcfclk_mhz =
3536                                         fixed16_to_double_to_cpu(bb->clock_limits[i].dcfclk_mhz);
3537                         dcn2_0_nv12_soc.clock_limits[i].fabricclk_mhz =
3538                                         fixed16_to_double_to_cpu(bb->clock_limits[i].fabricclk_mhz);
3539                         dcn2_0_nv12_soc.clock_limits[i].dispclk_mhz =
3540                                         fixed16_to_double_to_cpu(bb->clock_limits[i].dispclk_mhz);
3541                         dcn2_0_nv12_soc.clock_limits[i].dppclk_mhz =
3542                                         fixed16_to_double_to_cpu(bb->clock_limits[i].dppclk_mhz);
3543                         dcn2_0_nv12_soc.clock_limits[i].phyclk_mhz =
3544                                         fixed16_to_double_to_cpu(bb->clock_limits[i].phyclk_mhz);
3545                         dcn2_0_nv12_soc.clock_limits[i].socclk_mhz =
3546                                         fixed16_to_double_to_cpu(bb->clock_limits[i].socclk_mhz);
3547                         dcn2_0_nv12_soc.clock_limits[i].dscclk_mhz =
3548                                         fixed16_to_double_to_cpu(bb->clock_limits[i].dscclk_mhz);
3549                         dcn2_0_nv12_soc.clock_limits[i].dram_speed_mts =
3550                                         fixed16_to_double_to_cpu(bb->clock_limits[i].dram_speed_mts);
3551                 }
3552         }
3553
3554         if (pool->base.pp_smu) {
3555                 struct pp_smu_nv_clock_table max_clocks = {0};
3556                 unsigned int uclk_states[8] = {0};
3557                 unsigned int num_states = 0;
3558                 enum pp_smu_status status;
3559                 bool clock_limits_available = false;
3560                 bool uclk_states_available = false;
3561
3562                 if (pool->base.pp_smu->nv_funcs.get_uclk_dpm_states) {
3563                         status = (pool->base.pp_smu->nv_funcs.get_uclk_dpm_states)
3564                                 (&pool->base.pp_smu->nv_funcs.pp_smu, uclk_states, &num_states);
3565
3566                         uclk_states_available = (status == PP_SMU_RESULT_OK);
3567                 }
3568
3569                 if (pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks) {
3570                         status = (*pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks)
3571                                         (&pool->base.pp_smu->nv_funcs.pp_smu, &max_clocks);
3572                         /* SMU cannot set DCF clock to anything equal to or higher than SOC clock
3573                          */
3574                         if (max_clocks.dcfClockInKhz >= max_clocks.socClockInKhz)
3575                                 max_clocks.dcfClockInKhz = max_clocks.socClockInKhz - 1000;
3576                         clock_limits_available = (status == PP_SMU_RESULT_OK);
3577                 }
3578
3579                 if (clock_limits_available && uclk_states_available && num_states)
3580                         dcn20_update_bounding_box(dc, loaded_bb, &max_clocks, uclk_states, num_states);
3581                 else if (clock_limits_available)
3582                         dcn20_cap_soc_clocks(loaded_bb, max_clocks);
3583         }
3584
3585         loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator;
3586         loaded_ip->max_num_dpp = pool->base.pipe_count;
3587         dcn20_patch_bounding_box(dc, loaded_bb);
3588
3589         return true;
3590 }
3591
3592 static bool dcn20_resource_construct(
3593         uint8_t num_virtual_links,
3594         struct dc *dc,
3595         struct dcn20_resource_pool *pool)
3596 {
3597         int i;
3598         struct dc_context *ctx = dc->ctx;
3599         struct irq_service_init_data init_data;
3600         struct ddc_service_init_data ddc_init_data;
3601         struct _vcs_dpi_soc_bounding_box_st *loaded_bb =
3602                         get_asic_rev_soc_bb(ctx->asic_id.hw_internal_rev);
3603         struct _vcs_dpi_ip_params_st *loaded_ip =
3604                         get_asic_rev_ip_params(ctx->asic_id.hw_internal_rev);
3605         enum dml_project dml_project_version =
3606                         get_dml_project_version(ctx->asic_id.hw_internal_rev);
3607
3608         DC_FP_START();
3609
3610         ctx->dc_bios->regs = &bios_regs;
3611         pool->base.funcs = &dcn20_res_pool_funcs;
3612
3613         if (ASICREV_IS_NAVI14_M(ctx->asic_id.hw_internal_rev)) {
3614                 pool->base.res_cap = &res_cap_nv14;
3615                 pool->base.pipe_count = 5;
3616                 pool->base.mpcc_count = 5;
3617         } else {
3618                 pool->base.res_cap = &res_cap_nv10;
3619                 pool->base.pipe_count = 6;
3620                 pool->base.mpcc_count = 6;
3621         }
3622         /*************************************************
3623          *  Resource + asic cap harcoding                *
3624          *************************************************/
3625         pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
3626
3627         dc->caps.max_downscale_ratio = 200;
3628         dc->caps.i2c_speed_in_khz = 100;
3629         dc->caps.max_cursor_size = 256;
3630         dc->caps.dmdata_alloc_size = 2048;
3631
3632         dc->caps.max_slave_planes = 1;
3633         dc->caps.post_blend_color_processing = true;
3634         dc->caps.force_dp_tps4_for_cp2520 = true;
3635         dc->caps.hw_3d_lut = true;
3636         dc->caps.extended_aux_timeout_support = true;
3637
3638         if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) {
3639                 dc->debug = debug_defaults_drv;
3640         } else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
3641                 pool->base.pipe_count = 4;
3642                 pool->base.mpcc_count = pool->base.pipe_count;
3643                 dc->debug = debug_defaults_diags;
3644         } else {
3645                 dc->debug = debug_defaults_diags;
3646         }
3647         //dcn2.0x
3648         dc->work_arounds.dedcn20_305_wa = true;
3649
3650         // Init the vm_helper
3651         if (dc->vm_helper)
3652                 vm_helper_init(dc->vm_helper, 16);
3653
3654         /*************************************************
3655          *  Create resources                             *
3656          *************************************************/
3657
3658         pool->base.clock_sources[DCN20_CLK_SRC_PLL0] =
3659                         dcn20_clock_source_create(ctx, ctx->dc_bios,
3660                                 CLOCK_SOURCE_COMBO_PHY_PLL0,
3661                                 &clk_src_regs[0], false);
3662         pool->base.clock_sources[DCN20_CLK_SRC_PLL1] =
3663                         dcn20_clock_source_create(ctx, ctx->dc_bios,
3664                                 CLOCK_SOURCE_COMBO_PHY_PLL1,
3665                                 &clk_src_regs[1], false);
3666         pool->base.clock_sources[DCN20_CLK_SRC_PLL2] =
3667                         dcn20_clock_source_create(ctx, ctx->dc_bios,
3668                                 CLOCK_SOURCE_COMBO_PHY_PLL2,
3669                                 &clk_src_regs[2], false);
3670         pool->base.clock_sources[DCN20_CLK_SRC_PLL3] =
3671                         dcn20_clock_source_create(ctx, ctx->dc_bios,
3672                                 CLOCK_SOURCE_COMBO_PHY_PLL3,
3673                                 &clk_src_regs[3], false);
3674         pool->base.clock_sources[DCN20_CLK_SRC_PLL4] =
3675                         dcn20_clock_source_create(ctx, ctx->dc_bios,
3676                                 CLOCK_SOURCE_COMBO_PHY_PLL4,
3677                                 &clk_src_regs[4], false);
3678         pool->base.clock_sources[DCN20_CLK_SRC_PLL5] =
3679                         dcn20_clock_source_create(ctx, ctx->dc_bios,
3680                                 CLOCK_SOURCE_COMBO_PHY_PLL5,
3681                                 &clk_src_regs[5], false);
3682         pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL;
3683         /* todo: not reuse phy_pll registers */
3684         pool->base.dp_clock_source =
3685                         dcn20_clock_source_create(ctx, ctx->dc_bios,
3686                                 CLOCK_SOURCE_ID_DP_DTO,
3687                                 &clk_src_regs[0], true);
3688
3689         for (i = 0; i < pool->base.clk_src_count; i++) {
3690                 if (pool->base.clock_sources[i] == NULL) {
3691                         dm_error("DC: failed to create clock sources!\n");
3692                         BREAK_TO_DEBUGGER();
3693                         goto create_fail;
3694                 }
3695         }
3696
3697         pool->base.dccg = dccg2_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
3698         if (pool->base.dccg == NULL) {
3699                 dm_error("DC: failed to create dccg!\n");
3700                 BREAK_TO_DEBUGGER();
3701                 goto create_fail;
3702         }
3703
3704         pool->base.dmcu = dcn20_dmcu_create(ctx,
3705                         &dmcu_regs,
3706                         &dmcu_shift,
3707                         &dmcu_mask);
3708         if (pool->base.dmcu == NULL) {
3709                 dm_error("DC: failed to create dmcu!\n");
3710                 BREAK_TO_DEBUGGER();
3711                 goto create_fail;
3712         }
3713
3714         pool->base.abm = dce_abm_create(ctx,
3715                         &abm_regs,
3716                         &abm_shift,
3717                         &abm_mask);
3718         if (pool->base.abm == NULL) {
3719                 dm_error("DC: failed to create abm!\n");
3720                 BREAK_TO_DEBUGGER();
3721                 goto create_fail;
3722         }
3723
3724         pool->base.pp_smu = dcn20_pp_smu_create(ctx);
3725
3726
3727         if (!init_soc_bounding_box(dc, pool)) {
3728                 dm_error("DC: failed to initialize soc bounding box!\n");
3729                 BREAK_TO_DEBUGGER();
3730                 goto create_fail;
3731         }
3732
3733         dml_init_instance(&dc->dml, loaded_bb, loaded_ip, dml_project_version);
3734
3735         if (!dc->debug.disable_pplib_wm_range) {
3736                 struct pp_smu_wm_range_sets ranges = {0};
3737                 int i = 0;
3738
3739                 ranges.num_reader_wm_sets = 0;
3740
3741                 if (loaded_bb->num_states == 1) {
3742                         ranges.reader_wm_sets[0].wm_inst = i;
3743                         ranges.reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3744                         ranges.reader_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3745                         ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3746                         ranges.reader_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3747
3748                         ranges.num_reader_wm_sets = 1;
3749                 } else if (loaded_bb->num_states > 1) {
3750                         for (i = 0; i < 4 && i < loaded_bb->num_states; i++) {
3751                                 ranges.reader_wm_sets[i].wm_inst = i;
3752                                 ranges.reader_wm_sets[i].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3753                                 ranges.reader_wm_sets[i].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3754                                 ranges.reader_wm_sets[i].min_fill_clk_mhz = (i > 0) ? (loaded_bb->clock_limits[i - 1].dram_speed_mts / 16) + 1 : 0;
3755                                 ranges.reader_wm_sets[i].max_fill_clk_mhz = loaded_bb->clock_limits[i].dram_speed_mts / 16;
3756
3757                                 ranges.num_reader_wm_sets = i + 1;
3758                         }
3759
3760                         ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3761                         ranges.reader_wm_sets[ranges.num_reader_wm_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3762                 }
3763
3764                 ranges.num_writer_wm_sets = 1;
3765
3766                 ranges.writer_wm_sets[0].wm_inst = 0;
3767                 ranges.writer_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3768                 ranges.writer_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3769                 ranges.writer_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3770                 ranges.writer_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3771
3772                 /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */
3773                 if (pool->base.pp_smu->nv_funcs.set_wm_ranges)
3774                         pool->base.pp_smu->nv_funcs.set_wm_ranges(&pool->base.pp_smu->nv_funcs.pp_smu, &ranges);
3775         }
3776
3777         init_data.ctx = dc->ctx;
3778         pool->base.irqs = dal_irq_service_dcn20_create(&init_data);
3779         if (!pool->base.irqs)
3780                 goto create_fail;
3781
3782         /* mem input -> ipp -> dpp -> opp -> TG */
3783         for (i = 0; i < pool->base.pipe_count; i++) {
3784                 pool->base.hubps[i] = dcn20_hubp_create(ctx, i);
3785                 if (pool->base.hubps[i] == NULL) {
3786                         BREAK_TO_DEBUGGER();
3787                         dm_error(
3788                                 "DC: failed to create memory input!\n");
3789                         goto create_fail;
3790                 }
3791
3792                 pool->base.ipps[i] = dcn20_ipp_create(ctx, i);
3793                 if (pool->base.ipps[i] == NULL) {
3794                         BREAK_TO_DEBUGGER();
3795                         dm_error(
3796                                 "DC: failed to create input pixel processor!\n");
3797                         goto create_fail;
3798                 }
3799
3800                 pool->base.dpps[i] = dcn20_dpp_create(ctx, i);
3801                 if (pool->base.dpps[i] == NULL) {
3802                         BREAK_TO_DEBUGGER();
3803                         dm_error(
3804                                 "DC: failed to create dpps!\n");
3805                         goto create_fail;
3806                 }
3807         }
3808         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
3809                 pool->base.engines[i] = dcn20_aux_engine_create(ctx, i);
3810                 if (pool->base.engines[i] == NULL) {
3811                         BREAK_TO_DEBUGGER();
3812                         dm_error(
3813                                 "DC:failed to create aux engine!!\n");
3814                         goto create_fail;
3815                 }
3816                 pool->base.hw_i2cs[i] = dcn20_i2c_hw_create(ctx, i);
3817                 if (pool->base.hw_i2cs[i] == NULL) {
3818                         BREAK_TO_DEBUGGER();
3819                         dm_error(
3820                                 "DC:failed to create hw i2c!!\n");
3821                         goto create_fail;
3822                 }
3823                 pool->base.sw_i2cs[i] = NULL;
3824         }
3825
3826         for (i = 0; i < pool->base.res_cap->num_opp; i++) {
3827                 pool->base.opps[i] = dcn20_opp_create(ctx, i);
3828                 if (pool->base.opps[i] == NULL) {
3829                         BREAK_TO_DEBUGGER();
3830                         dm_error(
3831                                 "DC: failed to create output pixel processor!\n");
3832                         goto create_fail;
3833                 }
3834         }
3835
3836         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
3837                 pool->base.timing_generators[i] = dcn20_timing_generator_create(
3838                                 ctx, i);
3839                 if (pool->base.timing_generators[i] == NULL) {
3840                         BREAK_TO_DEBUGGER();
3841                         dm_error("DC: failed to create tg!\n");
3842                         goto create_fail;
3843                 }
3844         }
3845
3846         pool->base.timing_generator_count = i;
3847
3848         pool->base.mpc = dcn20_mpc_create(ctx);
3849         if (pool->base.mpc == NULL) {
3850                 BREAK_TO_DEBUGGER();
3851                 dm_error("DC: failed to create mpc!\n");
3852                 goto create_fail;
3853         }
3854
3855         pool->base.hubbub = dcn20_hubbub_create(ctx);
3856         if (pool->base.hubbub == NULL) {
3857                 BREAK_TO_DEBUGGER();
3858                 dm_error("DC: failed to create hubbub!\n");
3859                 goto create_fail;
3860         }
3861
3862         for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
3863                 pool->base.dscs[i] = dcn20_dsc_create(ctx, i);
3864                 if (pool->base.dscs[i] == NULL) {
3865                         BREAK_TO_DEBUGGER();
3866                         dm_error("DC: failed to create display stream compressor %d!\n", i);
3867                         goto create_fail;
3868                 }
3869         }
3870
3871         if (!dcn20_dwbc_create(ctx, &pool->base)) {
3872                 BREAK_TO_DEBUGGER();
3873                 dm_error("DC: failed to create dwbc!\n");
3874                 goto create_fail;
3875         }
3876         if (!dcn20_mmhubbub_create(ctx, &pool->base)) {
3877                 BREAK_TO_DEBUGGER();
3878                 dm_error("DC: failed to create mcif_wb!\n");
3879                 goto create_fail;
3880         }
3881
3882         if (!resource_construct(num_virtual_links, dc, &pool->base,
3883                         (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
3884                         &res_create_funcs : &res_create_maximus_funcs)))
3885                         goto create_fail;
3886
3887         dcn20_hw_sequencer_construct(dc);
3888
3889         dc->caps.max_planes =  pool->base.pipe_count;
3890
3891         for (i = 0; i < dc->caps.max_planes; ++i)
3892                 dc->caps.planes[i] = plane_cap;
3893
3894         dc->cap_funcs = cap_funcs;
3895
3896         if (dc->ctx->dc_bios->fw_info.oem_i2c_present) {
3897                 ddc_init_data.ctx = dc->ctx;
3898                 ddc_init_data.link = NULL;
3899                 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id;
3900                 ddc_init_data.id.enum_id = 0;
3901                 ddc_init_data.id.type = OBJECT_TYPE_GENERIC;
3902                 pool->base.oem_device = dal_ddc_service_create(&ddc_init_data);
3903         } else {
3904                 pool->base.oem_device = NULL;
3905         }
3906
3907         DC_FP_END();
3908         return true;
3909
3910 create_fail:
3911
3912         DC_FP_END();
3913         dcn20_resource_destruct(pool);
3914
3915         return false;
3916 }
3917
3918 struct resource_pool *dcn20_create_resource_pool(
3919                 const struct dc_init_data *init_data,
3920                 struct dc *dc)
3921 {
3922         struct dcn20_resource_pool *pool =
3923                 kzalloc(sizeof(struct dcn20_resource_pool), GFP_KERNEL);
3924
3925         if (!pool)
3926                 return NULL;
3927
3928         if (dcn20_resource_construct(init_data->num_virtual_links, dc, pool))
3929                 return &pool->base;
3930
3931         BREAK_TO_DEBUGGER();
3932         kfree(pool);
3933         return NULL;
3934 }