drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26
  27 #include "dm_services.h"
  28 #include "dc.h"
  29
  30 #include "dcn31/dcn31_init.h"
  31
  32 #include "resource.h"
  33 #include "include/irq_service_interface.h"
  34 #include "dcn31_resource.h"
  35
  36 #include "dcn20/dcn20_resource.h"
  37 #include "dcn30/dcn30_resource.h"
  38
  39 #include "dcn10/dcn10_ipp.h"
  40 #include "dcn30/dcn30_hubbub.h"
  41 #include "dcn31/dcn31_hubbub.h"
  42 #include "dcn30/dcn30_mpc.h"
  43 #include "dcn31/dcn31_hubp.h"
  44 #include "irq/dcn31/irq_service_dcn31.h"
  45 #include "dcn30/dcn30_dpp.h"
  46 #include "dcn31/dcn31_optc.h"
  47 #include "dcn20/dcn20_hwseq.h"
  48 #include "dcn30/dcn30_hwseq.h"
  49 #include "dce110/dce110_hw_sequencer.h"
  50 #include "dcn30/dcn30_opp.h"
  51 #include "dcn20/dcn20_dsc.h"
  52 #include "dcn30/dcn30_vpg.h"
  53 #include "dcn30/dcn30_afmt.h"
  54 #include "dcn30/dcn30_dio_stream_encoder.h"
  55 #include "dcn31/dcn31_hpo_dp_stream_encoder.h"
  56 #include "dcn31/dcn31_hpo_dp_link_encoder.h"
  57 #include "dcn31/dcn31_apg.h"
  58 #include "dcn31/dcn31_dio_link_encoder.h"
  59 #include "dcn31/dcn31_vpg.h"
  60 #include "dcn31/dcn31_afmt.h"
  61 #include "dce/dce_clock_source.h"
  62 #include "dce/dce_audio.h"
  63 #include "dce/dce_hwseq.h"
  64 #include "clk_mgr.h"
  65 #include "virtual/virtual_stream_encoder.h"
  66 #include "dce110/dce110_resource.h"
  67 #include "dml/display_mode_vba.h"
  68 #include "dcn31/dcn31_dccg.h"
  69 #include "dcn10/dcn10_resource.h"
  70 #include "dcn31_panel_cntl.h"
  71
  72 #include "dcn30/dcn30_dwb.h"
  73 #include "dcn30/dcn30_mmhubbub.h"
  74
  75 // TODO: change include headers /amd/include/asic_reg after upstream
  76 #include "yellow_carp_offset.h"
  77 #include "dcn/dcn_3_1_2_offset.h"
  78 #include "dcn/dcn_3_1_2_sh_mask.h"
  79 #include "nbio/nbio_7_2_0_offset.h"
  80 #include "dpcs/dpcs_4_2_0_offset.h"
  81 #include "dpcs/dpcs_4_2_0_sh_mask.h"
  82 #include "mmhub/mmhub_2_3_0_offset.h"
  83 #include "mmhub/mmhub_2_3_0_sh_mask.h"
  84
  85
  86 #define regDCHUBBUB_DEBUG_CTRL_0                                              0x04d6
  87 #define regDCHUBBUB_DEBUG_CTRL_0_BASE_IDX                                     2
  88 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH__SHIFT                               0x10
  89 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH_MASK                                 0x01FF0000L
  90
  91 #include "reg_helper.h"
  92 #include "dce/dmub_abm.h"
  93 #include "dce/dmub_psr.h"
  94 #include "dce/dce_aux.h"
  95 #include "dce/dce_i2c.h"
  96
  97 #include "dml/dcn30/display_mode_vba_30.h"
  98 #include "vm_helper.h"
  99 #include "dcn20/dcn20_vmid.h"
 100
 101 #include "link_enc_cfg.h"
 102
 103 #define DC_LOGGER_INIT(logger)
 104
 105 #define DCN3_1_DEFAULT_DET_SIZE 384
 106
 107 struct _vcs_dpi_ip_params_st dcn3_1_ip = {
 108         .gpuvm_enable = 1,
 109         .gpuvm_max_page_table_levels = 1,
 110         .hostvm_enable = 1,
 111         .hostvm_max_page_table_levels = 2,
 112         .rob_buffer_size_kbytes = 64,
 113         .det_buffer_size_kbytes = DCN3_1_DEFAULT_DET_SIZE,
 114         .config_return_buffer_size_in_kbytes = 1792,
 115         .compressed_buffer_segment_size_in_kbytes = 64,
 116         .meta_fifo_size_in_kentries = 32,
 117         .zero_size_buffer_entries = 512,
 118         .compbuf_reserved_space_64b = 256,
 119         .compbuf_reserved_space_zs = 64,
 120         .dpp_output_buffer_pixels = 2560,
 121         .opp_output_buffer_lines = 1,
 122         .pixel_chunk_size_kbytes = 8,
 123         .meta_chunk_size_kbytes = 2,
 124         .min_meta_chunk_size_bytes = 256,
 125         .writeback_chunk_size_kbytes = 8,
 126         .ptoi_supported = false,
 127         .num_dsc = 3,
 128         .maximum_dsc_bits_per_component = 10,
 129         .dsc422_native_support = false,
 130         .is_line_buffer_bpp_fixed = true,
 131         .line_buffer_fixed_bpp = 48,
 132         .line_buffer_size_bits = 789504,
 133         .max_line_buffer_lines = 12,
 134         .writeback_interface_buffer_size_kbytes = 90,
 135         .max_num_dpp = 4,
 136         .max_num_otg = 4,
 137         .max_num_hdmi_frl_outputs = 1,
 138         .max_num_wb = 1,
 139         .max_dchub_pscl_bw_pix_per_clk = 4,
 140         .max_pscl_lb_bw_pix_per_clk = 2,
 141         .max_lb_vscl_bw_pix_per_clk = 4,
 142         .max_vscl_hscl_bw_pix_per_clk = 4,
 143         .max_hscl_ratio = 6,
 144         .max_vscl_ratio = 6,
 145         .max_hscl_taps = 8,
 146         .max_vscl_taps = 8,
 147         .dpte_buffer_size_in_pte_reqs_luma = 64,
 148         .dpte_buffer_size_in_pte_reqs_chroma = 34,
 149         .dispclk_ramp_margin_percent = 1,
 150         .max_inter_dcn_tile_repeaters = 8,
 151         .cursor_buffer_size = 16,
 152         .cursor_chunk_size = 2,
 153         .writeback_line_buffer_buffer_size = 0,
 154         .writeback_min_hscl_ratio = 1,
 155         .writeback_min_vscl_ratio = 1,
 156         .writeback_max_hscl_ratio = 1,
 157         .writeback_max_vscl_ratio = 1,
 158         .writeback_max_hscl_taps = 1,
 159         .writeback_max_vscl_taps = 1,
 160         .dppclk_delay_subtotal = 46,
 161         .dppclk_delay_scl = 50,
 162         .dppclk_delay_scl_lb_only = 16,
 163         .dppclk_delay_cnvc_formatter = 27,
 164         .dppclk_delay_cnvc_cursor = 6,
 165         .dispclk_delay_subtotal = 119,
 166         .dynamic_metadata_vm_enabled = false,
 167         .odm_combine_4to1_supported = false,
 168         .dcc_supported = true,
 169 };
 170
 171 struct _vcs_dpi_soc_bounding_box_st dcn3_1_soc = {
 172                 /*TODO: correct dispclk/dppclk voltage level determination*/
 173         .clock_limits = {
 174                 {
 175                         .state = 0,
 176                         .dispclk_mhz = 1200.0,
 177                         .dppclk_mhz = 1200.0,
 178                         .phyclk_mhz = 600.0,
 179                         .phyclk_d18_mhz = 667.0,
 180                         .dscclk_mhz = 186.0,
 181                         .dtbclk_mhz = 625.0,
 182                 },
 183                 {
 184                         .state = 1,
 185                         .dispclk_mhz = 1200.0,
 186                         .dppclk_mhz = 1200.0,
 187                         .phyclk_mhz = 810.0,
 188                         .phyclk_d18_mhz = 667.0,
 189                         .dscclk_mhz = 209.0,
 190                         .dtbclk_mhz = 625.0,
 191                 },
 192                 {
 193                         .state = 2,
 194                         .dispclk_mhz = 1200.0,
 195                         .dppclk_mhz = 1200.0,
 196                         .phyclk_mhz = 810.0,
 197                         .phyclk_d18_mhz = 667.0,
 198                         .dscclk_mhz = 209.0,
 199                         .dtbclk_mhz = 625.0,
 200                 },
 201                 {
 202                         .state = 3,
 203                         .dispclk_mhz = 1200.0,
 204                         .dppclk_mhz = 1200.0,
 205                         .phyclk_mhz = 810.0,
 206                         .phyclk_d18_mhz = 667.0,
 207                         .dscclk_mhz = 371.0,
 208                         .dtbclk_mhz = 625.0,
 209                 },
 210                 {
 211                         .state = 4,
 212                         .dispclk_mhz = 1200.0,
 213                         .dppclk_mhz = 1200.0,
 214                         .phyclk_mhz = 810.0,
 215                         .phyclk_d18_mhz = 667.0,
 216                         .dscclk_mhz = 417.0,
 217                         .dtbclk_mhz = 625.0,
 218                 },
 219         },
 220         .num_states = 5,
 221         .sr_exit_time_us = 9.0,
 222         .sr_enter_plus_exit_time_us = 11.0,
 223         .sr_exit_z8_time_us = 442.0,
 224         .sr_enter_plus_exit_z8_time_us = 560.0,
 225         .writeback_latency_us = 12.0,
 226         .dram_channel_width_bytes = 4,
 227         .round_trip_ping_latency_dcfclk_cycles = 106,
 228         .urgent_latency_pixel_data_only_us = 4.0,
 229         .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
 230         .urgent_latency_vm_data_only_us = 4.0,
 231         .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
 232         .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
 233         .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
 234         .pct_ideal_sdp_bw_after_urgent = 80.0,
 235         .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 65.0,
 236         .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0,
 237         .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 30.0,
 238         .max_avg_sdp_bw_use_normal_percent = 60.0,
 239         .max_avg_dram_bw_use_normal_percent = 60.0,
 240         .fabric_datapath_to_dcn_data_return_bytes = 32,
 241         .return_bus_width_bytes = 64,
 242         .downspread_percent = 0.38,
 243         .dcn_downspread_percent = 0.5,
 244         .gpuvm_min_page_size_bytes = 4096,
 245         .hostvm_min_page_size_bytes = 4096,
 246         .do_urgent_latency_adjustment = false,
 247         .urgent_latency_adjustment_fabric_clock_component_us = 0,
 248         .urgent_latency_adjustment_fabric_clock_reference_mhz = 0,
 249 };
 250
 251 enum dcn31_clk_src_array_id {
 252         DCN31_CLK_SRC_PLL0,
 253         DCN31_CLK_SRC_PLL1,
 254         DCN31_CLK_SRC_PLL2,
 255         DCN31_CLK_SRC_PLL3,
 256         DCN31_CLK_SRC_PLL4,
 257         DCN30_CLK_SRC_TOTAL
 258 };
 259
 260 /* begin *********************
 261  * macros to expend register list macro defined in HW object header file
 262  */
 263
 264 /* DCN */
 265 /* TODO awful hack. fixup dcn20_dwb.h */
 266 #undef BASE_INNER
 267 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
 268
 269 #define BASE(seg) BASE_INNER(seg)
 270
 271 #define SR(reg_name)\
 272                 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) +  \
 273                                         reg ## reg_name
 274
 275 #define SRI(reg_name, block, id)\
 276         .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 277                                         reg ## block ## id ## _ ## reg_name
 278
 279 #define SRI2(reg_name, block, id)\
 280         .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
 281                                         reg ## reg_name
 282
 283 #define SRIR(var_name, reg_name, block, id)\
 284         .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 285                                         reg ## block ## id ## _ ## reg_name
 286
 287 #define SRII(reg_name, block, id)\
 288         .reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 289                                         reg ## block ## id ## _ ## reg_name
 290
 291 #define SRII_MPC_RMU(reg_name, block, id)\
 292         .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 293                                         reg ## block ## id ## _ ## reg_name
 294
 295 #define SRII_DWB(reg_name, temp_name, block, id)\
 296         .reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
 297                                         reg ## block ## id ## _ ## temp_name
 298
 299 #define DCCG_SRII(reg_name, block, id)\
 300         .block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 301                                         reg ## block ## id ## _ ## reg_name
 302
 303 #define VUPDATE_SRII(reg_name, block, id)\
 304         .reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
 305                                         reg ## reg_name ## _ ## block ## id
 306
 307 /* NBIO */
 308 #define NBIO_BASE_INNER(seg) \
 309         NBIO_BASE__INST0_SEG ## seg
 310
 311 #define NBIO_BASE(seg) \
 312         NBIO_BASE_INNER(seg)
 313
 314 #define NBIO_SR(reg_name)\
 315                 .reg_name = NBIO_BASE(regBIF_BX1_ ## reg_name ## _BASE_IDX) + \
 316                                         regBIF_BX1_ ## reg_name
 317
 318 /* MMHUB */
 319 #define MMHUB_BASE_INNER(seg) \
 320         MMHUB_BASE__INST0_SEG ## seg
 321
 322 #define MMHUB_BASE(seg) \
 323         MMHUB_BASE_INNER(seg)
 324
 325 #define MMHUB_SR(reg_name)\
 326                 .reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) + \
 327                                         mm ## reg_name
 328
 329 /* CLOCK */
 330 #define CLK_BASE_INNER(seg) \
 331         CLK_BASE__INST0_SEG ## seg
 332
 333 #define CLK_BASE(seg) \
 334         CLK_BASE_INNER(seg)
 335
 336 #define CLK_SRI(reg_name, block, inst)\
 337         .reg_name = CLK_BASE(reg ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
 338                                         reg ## block ## _ ## inst ## _ ## reg_name
 339
 340
 341 static const struct bios_registers bios_regs = {
 342                 NBIO_SR(BIOS_SCRATCH_3),
 343                 NBIO_SR(BIOS_SCRATCH_6)
 344 };
 345
 346 #define clk_src_regs(index, pllid)\
 347 [index] = {\
 348         CS_COMMON_REG_LIST_DCN3_0(index, pllid),\
 349 }
 350
 351 static const struct dce110_clk_src_regs clk_src_regs[] = {
 352         clk_src_regs(0, A),
 353         clk_src_regs(1, B),
 354         clk_src_regs(2, C),
 355         clk_src_regs(3, D),
 356         clk_src_regs(4, E)
 357 };
 358
 359 static const struct dce110_clk_src_shift cs_shift = {
 360                 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
 361 };
 362
 363 static const struct dce110_clk_src_mask cs_mask = {
 364                 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
 365 };
 366
 367 #define abm_regs(id)\
 368 [id] = {\
 369                 ABM_DCN302_REG_LIST(id)\
 370 }
 371
 372 static const struct dce_abm_registers abm_regs[] = {
 373                 abm_regs(0),
 374                 abm_regs(1),
 375                 abm_regs(2),
 376                 abm_regs(3),
 377 };
 378
 379 static const struct dce_abm_shift abm_shift = {
 380                 ABM_MASK_SH_LIST_DCN30(__SHIFT)
 381 };
 382
 383 static const struct dce_abm_mask abm_mask = {
 384                 ABM_MASK_SH_LIST_DCN30(_MASK)
 385 };
 386
 387 #define audio_regs(id)\
 388 [id] = {\
 389                 AUD_COMMON_REG_LIST(id)\
 390 }
 391
 392 static const struct dce_audio_registers audio_regs[] = {
 393         audio_regs(0),
 394         audio_regs(1),
 395         audio_regs(2),
 396         audio_regs(3),
 397         audio_regs(4),
 398         audio_regs(5),
 399         audio_regs(6)
 400 };
 401
 402 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
 403                 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
 404                 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
 405                 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
 406
 407 static const struct dce_audio_shift audio_shift = {
 408                 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
 409 };
 410
 411 static const struct dce_audio_mask audio_mask = {
 412                 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
 413 };
 414
 415 #define vpg_regs(id)\
 416 [id] = {\
 417         VPG_DCN31_REG_LIST(id)\
 418 }
 419
 420 static const struct dcn31_vpg_registers vpg_regs[] = {
 421         vpg_regs(0),
 422         vpg_regs(1),
 423         vpg_regs(2),
 424         vpg_regs(3),
 425         vpg_regs(4),
 426         vpg_regs(5),
 427         vpg_regs(6),
 428         vpg_regs(7),
 429         vpg_regs(8),
 430         vpg_regs(9),
 431 };
 432
 433 static const struct dcn31_vpg_shift vpg_shift = {
 434         DCN31_VPG_MASK_SH_LIST(__SHIFT)
 435 };
 436
 437 static const struct dcn31_vpg_mask vpg_mask = {
 438         DCN31_VPG_MASK_SH_LIST(_MASK)
 439 };
 440
 441 #define afmt_regs(id)\
 442 [id] = {\
 443         AFMT_DCN31_REG_LIST(id)\
 444 }
 445
 446 static const struct dcn31_afmt_registers afmt_regs[] = {
 447         afmt_regs(0),
 448         afmt_regs(1),
 449         afmt_regs(2),
 450         afmt_regs(3),
 451         afmt_regs(4),
 452         afmt_regs(5)
 453 };
 454
 455 static const struct dcn31_afmt_shift afmt_shift = {
 456         DCN31_AFMT_MASK_SH_LIST(__SHIFT)
 457 };
 458
 459 static const struct dcn31_afmt_mask afmt_mask = {
 460         DCN31_AFMT_MASK_SH_LIST(_MASK)
 461 };
 462
 463 #define apg_regs(id)\
 464 [id] = {\
 465         APG_DCN31_REG_LIST(id)\
 466 }
 467
 468 static const struct dcn31_apg_registers apg_regs[] = {
 469         apg_regs(0),
 470         apg_regs(1),
 471         apg_regs(2),
 472         apg_regs(3)
 473 };
 474
 475 static const struct dcn31_apg_shift apg_shift = {
 476         DCN31_APG_MASK_SH_LIST(__SHIFT)
 477 };
 478
 479 static const struct dcn31_apg_mask apg_mask = {
 480                 DCN31_APG_MASK_SH_LIST(_MASK)
 481 };
 482
 483 #define stream_enc_regs(id)\
 484 [id] = {\
 485         SE_DCN3_REG_LIST(id)\
 486 }
 487
 488 /* Some encoders won't be initialized here - but they're logical, not physical. */
 489 static const struct dcn10_stream_enc_registers stream_enc_regs[ENGINE_ID_COUNT] = {
 490         stream_enc_regs(0),
 491         stream_enc_regs(1),
 492         stream_enc_regs(2),
 493         stream_enc_regs(3),
 494         stream_enc_regs(4)
 495 };
 496
 497 static const struct dcn10_stream_encoder_shift se_shift = {
 498                 SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 499 };
 500
 501 static const struct dcn10_stream_encoder_mask se_mask = {
 502                 SE_COMMON_MASK_SH_LIST_DCN30(_MASK)
 503 };
 504
 505
 506 #define aux_regs(id)\
 507 [id] = {\
 508         DCN2_AUX_REG_LIST(id)\
 509 }
 510
 511 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
 512                 aux_regs(0),
 513                 aux_regs(1),
 514                 aux_regs(2),
 515                 aux_regs(3),
 516                 aux_regs(4)
 517 };
 518
 519 #define hpd_regs(id)\
 520 [id] = {\
 521         HPD_REG_LIST(id)\
 522 }
 523
 524 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
 525                 hpd_regs(0),
 526                 hpd_regs(1),
 527                 hpd_regs(2),
 528                 hpd_regs(3),
 529                 hpd_regs(4)
 530 };
 531
 532 #define link_regs(id, phyid)\
 533 [id] = {\
 534         LE_DCN31_REG_LIST(id), \
 535         UNIPHY_DCN2_REG_LIST(phyid), \
 536         DPCS_DCN31_REG_LIST(id), \
 537 }
 538
 539 static const struct dce110_aux_registers_shift aux_shift = {
 540         DCN_AUX_MASK_SH_LIST(__SHIFT)
 541 };
 542
 543 static const struct dce110_aux_registers_mask aux_mask = {
 544         DCN_AUX_MASK_SH_LIST(_MASK)
 545 };
 546
 547 static const struct dcn10_link_enc_registers link_enc_regs[] = {
 548         link_regs(0, A),
 549         link_regs(1, B),
 550         link_regs(2, C),
 551         link_regs(3, D),
 552         link_regs(4, E)
 553 };
 554
 555 static const struct dcn10_link_enc_shift le_shift = {
 556         LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), \
 557         DPCS_DCN31_MASK_SH_LIST(__SHIFT)
 558 };
 559
 560 static const struct dcn10_link_enc_mask le_mask = {
 561         LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \
 562         DPCS_DCN31_MASK_SH_LIST(_MASK)
 563 };
 564
 565 #define hpo_dp_stream_encoder_reg_list(id)\
 566 [id] = {\
 567         DCN3_1_HPO_DP_STREAM_ENC_REG_LIST(id)\
 568 }
 569
 570 static const struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[] = {
 571         hpo_dp_stream_encoder_reg_list(0),
 572         hpo_dp_stream_encoder_reg_list(1),
 573         hpo_dp_stream_encoder_reg_list(2),
 574         hpo_dp_stream_encoder_reg_list(3),
 575 };
 576
 577 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = {
 578         DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT)
 579 };
 580
 581 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = {
 582         DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)
 583 };
 584
 585 #define hpo_dp_link_encoder_reg_list(id)\
 586 [id] = {\
 587         DCN3_1_HPO_DP_LINK_ENC_REG_LIST(id),\
 588         DCN3_1_RDPCSTX_REG_LIST(0),\
 589         DCN3_1_RDPCSTX_REG_LIST(1),\
 590         DCN3_1_RDPCSTX_REG_LIST(2),\
 591         DCN3_1_RDPCSTX_REG_LIST(3),\
 592         DCN3_1_RDPCSTX_REG_LIST(4)\
 593 }
 594
 595 static const struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[] = {
 596         hpo_dp_link_encoder_reg_list(0),
 597         hpo_dp_link_encoder_reg_list(1),
 598 };
 599
 600 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = {
 601         DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT)
 602 };
 603
 604 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = {
 605         DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK)
 606 };
 607
 608 #define dpp_regs(id)\
 609 [id] = {\
 610         DPP_REG_LIST_DCN30(id),\
 611 }
 612
 613 static const struct dcn3_dpp_registers dpp_regs[] = {
 614         dpp_regs(0),
 615         dpp_regs(1),
 616         dpp_regs(2),
 617         dpp_regs(3)
 618 };
 619
 620 static const struct dcn3_dpp_shift tf_shift = {
 621                 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT)
 622 };
 623
 624 static const struct dcn3_dpp_mask tf_mask = {
 625                 DPP_REG_LIST_SH_MASK_DCN30(_MASK)
 626 };
 627
 628 #define opp_regs(id)\
 629 [id] = {\
 630         OPP_REG_LIST_DCN30(id),\
 631 }
 632
 633 static const struct dcn20_opp_registers opp_regs[] = {
 634         opp_regs(0),
 635         opp_regs(1),
 636         opp_regs(2),
 637         opp_regs(3)
 638 };
 639
 640 static const struct dcn20_opp_shift opp_shift = {
 641         OPP_MASK_SH_LIST_DCN20(__SHIFT)
 642 };
 643
 644 static const struct dcn20_opp_mask opp_mask = {
 645         OPP_MASK_SH_LIST_DCN20(_MASK)
 646 };
 647
 648 #define aux_engine_regs(id)\
 649 [id] = {\
 650         AUX_COMMON_REG_LIST0(id), \
 651         .AUXN_IMPCAL = 0, \
 652         .AUXP_IMPCAL = 0, \
 653         .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
 654 }
 655
 656 static const struct dce110_aux_registers aux_engine_regs[] = {
 657                 aux_engine_regs(0),
 658                 aux_engine_regs(1),
 659                 aux_engine_regs(2),
 660                 aux_engine_regs(3),
 661                 aux_engine_regs(4)
 662 };
 663
 664 #define dwbc_regs_dcn3(id)\
 665 [id] = {\
 666         DWBC_COMMON_REG_LIST_DCN30(id),\
 667 }
 668
 669 static const struct dcn30_dwbc_registers dwbc30_regs[] = {
 670         dwbc_regs_dcn3(0),
 671 };
 672
 673 static const struct dcn30_dwbc_shift dwbc30_shift = {
 674         DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 675 };
 676
 677 static const struct dcn30_dwbc_mask dwbc30_mask = {
 678         DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
 679 };
 680
 681 #define mcif_wb_regs_dcn3(id)\
 682 [id] = {\
 683         MCIF_WB_COMMON_REG_LIST_DCN30(id),\
 684 }
 685
 686 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = {
 687         mcif_wb_regs_dcn3(0)
 688 };
 689
 690 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
 691         MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 692 };
 693
 694 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
 695         MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK)
 696 };
 697
 698 #define dsc_regsDCN20(id)\
 699 [id] = {\
 700         DSC_REG_LIST_DCN20(id)\
 701 }
 702
 703 static const struct dcn20_dsc_registers dsc_regs[] = {
 704         dsc_regsDCN20(0),
 705         dsc_regsDCN20(1),
 706         dsc_regsDCN20(2)
 707 };
 708
 709 static const struct dcn20_dsc_shift dsc_shift = {
 710         DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
 711 };
 712
 713 static const struct dcn20_dsc_mask dsc_mask = {
 714         DSC_REG_LIST_SH_MASK_DCN20(_MASK)
 715 };
 716
 717 static const struct dcn30_mpc_registers mpc_regs = {
 718                 MPC_REG_LIST_DCN3_0(0),
 719                 MPC_REG_LIST_DCN3_0(1),
 720                 MPC_REG_LIST_DCN3_0(2),
 721                 MPC_REG_LIST_DCN3_0(3),
 722                 MPC_OUT_MUX_REG_LIST_DCN3_0(0),
 723                 MPC_OUT_MUX_REG_LIST_DCN3_0(1),
 724                 MPC_OUT_MUX_REG_LIST_DCN3_0(2),
 725                 MPC_OUT_MUX_REG_LIST_DCN3_0(3),
 726                 MPC_RMU_GLOBAL_REG_LIST_DCN3AG,
 727                 MPC_RMU_REG_LIST_DCN3AG(0),
 728                 MPC_RMU_REG_LIST_DCN3AG(1),
 729                 //MPC_RMU_REG_LIST_DCN3AG(2),
 730                 MPC_DWB_MUX_REG_LIST_DCN3_0(0),
 731 };
 732
 733 static const struct dcn30_mpc_shift mpc_shift = {
 734         MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 735 };
 736
 737 static const struct dcn30_mpc_mask mpc_mask = {
 738         MPC_COMMON_MASK_SH_LIST_DCN30(_MASK)
 739 };
 740
 741 #define optc_regs(id)\
 742 [id] = {OPTC_COMMON_REG_LIST_DCN3_1(id)}
 743
 744 static const struct dcn_optc_registers optc_regs[] = {
 745         optc_regs(0),
 746         optc_regs(1),
 747         optc_regs(2),
 748         optc_regs(3)
 749 };
 750
 751 static const struct dcn_optc_shift optc_shift = {
 752         OPTC_COMMON_MASK_SH_LIST_DCN3_1(__SHIFT)
 753 };
 754
 755 static const struct dcn_optc_mask optc_mask = {
 756         OPTC_COMMON_MASK_SH_LIST_DCN3_1(_MASK)
 757 };
 758
 759 #define hubp_regs(id)\
 760 [id] = {\
 761         HUBP_REG_LIST_DCN30(id)\
 762 }
 763
 764 static const struct dcn_hubp2_registers hubp_regs[] = {
 765                 hubp_regs(0),
 766                 hubp_regs(1),
 767                 hubp_regs(2),
 768                 hubp_regs(3)
 769 };
 770
 771
 772 static const struct dcn_hubp2_shift hubp_shift = {
 773                 HUBP_MASK_SH_LIST_DCN31(__SHIFT)
 774 };
 775
 776 static const struct dcn_hubp2_mask hubp_mask = {
 777                 HUBP_MASK_SH_LIST_DCN31(_MASK)
 778 };
 779 static const struct dcn_hubbub_registers hubbub_reg = {
 780                 HUBBUB_REG_LIST_DCN31(0)
 781 };
 782
 783 static const struct dcn_hubbub_shift hubbub_shift = {
 784                 HUBBUB_MASK_SH_LIST_DCN31(__SHIFT)
 785 };
 786
 787 static const struct dcn_hubbub_mask hubbub_mask = {
 788                 HUBBUB_MASK_SH_LIST_DCN31(_MASK)
 789 };
 790
 791 static const struct dccg_registers dccg_regs = {
 792                 DCCG_REG_LIST_DCN31()
 793 };
 794
 795 static const struct dccg_shift dccg_shift = {
 796                 DCCG_MASK_SH_LIST_DCN31(__SHIFT)
 797 };
 798
 799 static const struct dccg_mask dccg_mask = {
 800                 DCCG_MASK_SH_LIST_DCN31(_MASK)
 801 };
 802
 803
 804 #define SRII2(reg_name_pre, reg_name_post, id)\
 805         .reg_name_pre ## _ ##  reg_name_post[id] = BASE(reg ## reg_name_pre \
 806                         ## id ## _ ## reg_name_post ## _BASE_IDX) + \
 807                         reg ## reg_name_pre ## id ## _ ## reg_name_post
 808
 809
 810 #define HWSEQ_DCN31_REG_LIST()\
 811         SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
 812         SR(DCHUBBUB_ARB_HOSTVM_CNTL), \
 813         SR(DIO_MEM_PWR_CTRL), \
 814         SR(ODM_MEM_PWR_CTRL3), \
 815         SR(DMU_MEM_PWR_CNTL), \
 816         SR(MMHUBBUB_MEM_PWR_CNTL), \
 817         SR(DCCG_GATE_DISABLE_CNTL), \
 818         SR(DCCG_GATE_DISABLE_CNTL2), \
 819         SR(DCFCLK_CNTL),\
 820         SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
 821         SRII(PIXEL_RATE_CNTL, OTG, 0), \
 822         SRII(PIXEL_RATE_CNTL, OTG, 1),\
 823         SRII(PIXEL_RATE_CNTL, OTG, 2),\
 824         SRII(PIXEL_RATE_CNTL, OTG, 3),\
 825         SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
 826         SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
 827         SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
 828         SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
 829         SR(MICROSECOND_TIME_BASE_DIV), \
 830         SR(MILLISECOND_TIME_BASE_DIV), \
 831         SR(DISPCLK_FREQ_CHANGE_CNTL), \
 832         SR(RBBMIF_TIMEOUT_DIS), \
 833         SR(RBBMIF_TIMEOUT_DIS_2), \
 834         SR(DCHUBBUB_CRC_CTRL), \
 835         SR(DPP_TOP0_DPP_CRC_CTRL), \
 836         SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
 837         SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
 838         SR(MPC_CRC_CTRL), \
 839         SR(MPC_CRC_RESULT_GB), \
 840         SR(MPC_CRC_RESULT_C), \
 841         SR(MPC_CRC_RESULT_AR), \
 842         SR(DOMAIN0_PG_CONFIG), \
 843         SR(DOMAIN1_PG_CONFIG), \
 844         SR(DOMAIN2_PG_CONFIG), \
 845         SR(DOMAIN3_PG_CONFIG), \
 846         SR(DOMAIN16_PG_CONFIG), \
 847         SR(DOMAIN17_PG_CONFIG), \
 848         SR(DOMAIN18_PG_CONFIG), \
 849         SR(DOMAIN0_PG_STATUS), \
 850         SR(DOMAIN1_PG_STATUS), \
 851         SR(DOMAIN2_PG_STATUS), \
 852         SR(DOMAIN3_PG_STATUS), \
 853         SR(DOMAIN16_PG_STATUS), \
 854         SR(DOMAIN17_PG_STATUS), \
 855         SR(DOMAIN18_PG_STATUS), \
 856         SR(D1VGA_CONTROL), \
 857         SR(D2VGA_CONTROL), \
 858         SR(D3VGA_CONTROL), \
 859         SR(D4VGA_CONTROL), \
 860         SR(D5VGA_CONTROL), \
 861         SR(D6VGA_CONTROL), \
 862         SR(DC_IP_REQUEST_CNTL), \
 863         SR(AZALIA_AUDIO_DTO), \
 864         SR(AZALIA_CONTROLLER_CLOCK_GATING), \
 865         SR(HPO_TOP_HW_CONTROL)
 866
 867 static const struct dce_hwseq_registers hwseq_reg = {
 868                 HWSEQ_DCN31_REG_LIST()
 869 };
 870
 871 #define HWSEQ_DCN31_MASK_SH_LIST(mask_sh)\
 872         HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
 873         HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
 874         HWS_SF(, DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, mask_sh), \
 875         HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 876         HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 877         HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 878         HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 879         HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 880         HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 881         HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 882         HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 883         HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 884         HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 885         HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 886         HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 887         HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 888         HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 889         HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 890         HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 891         HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 892         HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 893         HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 894         HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 895         HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 896         HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
 897         HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \
 898         HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \
 899         HWS_SF(, DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, mask_sh), \
 900         HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \
 901         HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \
 902         HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh), \
 903         HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \
 904         HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh)
 905
 906 static const struct dce_hwseq_shift hwseq_shift = {
 907                 HWSEQ_DCN31_MASK_SH_LIST(__SHIFT)
 908 };
 909
 910 static const struct dce_hwseq_mask hwseq_mask = {
 911                 HWSEQ_DCN31_MASK_SH_LIST(_MASK)
 912 };
 913 #define vmid_regs(id)\
 914 [id] = {\
 915                 DCN20_VMID_REG_LIST(id)\
 916 }
 917
 918 static const struct dcn_vmid_registers vmid_regs[] = {
 919         vmid_regs(0),
 920         vmid_regs(1),
 921         vmid_regs(2),
 922         vmid_regs(3),
 923         vmid_regs(4),
 924         vmid_regs(5),
 925         vmid_regs(6),
 926         vmid_regs(7),
 927         vmid_regs(8),
 928         vmid_regs(9),
 929         vmid_regs(10),
 930         vmid_regs(11),
 931         vmid_regs(12),
 932         vmid_regs(13),
 933         vmid_regs(14),
 934         vmid_regs(15)
 935 };
 936
 937 static const struct dcn20_vmid_shift vmid_shifts = {
 938                 DCN20_VMID_MASK_SH_LIST(__SHIFT)
 939 };
 940
 941 static const struct dcn20_vmid_mask vmid_masks = {
 942                 DCN20_VMID_MASK_SH_LIST(_MASK)
 943 };
 944
 945 static const struct resource_caps res_cap_dcn31 = {
 946         .num_timing_generator = 4,
 947         .num_opp = 4,
 948         .num_video_plane = 4,
 949         .num_audio = 5,
 950         .num_stream_encoder = 5,
 951         .num_dig_link_enc = 5,
 952         .num_hpo_dp_stream_encoder = 4,
 953         .num_hpo_dp_link_encoder = 2,
 954         .num_pll = 5,
 955         .num_dwb = 1,
 956         .num_ddc = 5,
 957         .num_vmid = 16,
 958         .num_mpc_3dlut = 2,
 959         .num_dsc = 3,
 960 };
 961
 962 static const struct dc_plane_cap plane_cap = {
 963         .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
 964         .blends_with_above = true,
 965         .blends_with_below = true,
 966         .per_pixel_alpha = true,
 967
 968         .pixel_format_support = {
 969                         .argb8888 = true,
 970                         .nv12 = true,
 971                         .fp16 = true,
 972                         .p010 = true,
 973                         .ayuv = false,
 974         },
 975
 976         .max_upscale_factor = {
 977                         .argb8888 = 16000,
 978                         .nv12 = 16000,
 979                         .fp16 = 16000
 980         },
 981
 982         // 6:1 downscaling ratio: 1000/6 = 166.666
 983         .max_downscale_factor = {
 984                         .argb8888 = 167,
 985                         .nv12 = 167,
 986                         .fp16 = 167
 987         },
 988         64,
 989         64
 990 };
 991
 992 static const struct dc_debug_options debug_defaults_drv = {
 993         .disable_dmcu = true,
 994         .force_abm_enable = false,
 995         .timing_trace = false,
 996         .clock_trace = true,
 997         .disable_pplib_clock_request = false,
 998         .pipe_split_policy = MPC_SPLIT_AVOID,
 999         .force_single_disp_pipe_split = false,
1000         .disable_dcc = DCC_ENABLE,
1001         .vsr_support = true,
1002         .performance_trace = false,
1003         .max_downscale_src_width = 4096,/*upto true 4K*/
1004         .disable_pplib_wm_range = false,
1005         .scl_reset_length10 = true,
1006         .sanity_checks = false,
1007         .underflow_assert_delay_us = 0xFFFFFFFF,
1008         .dwb_fi_phase = -1, // -1 = disable,
1009         .dmub_command_table = true,
1010         .pstate_enabled = true,
1011         .use_max_lb = true,
1012         .enable_mem_low_power = {
1013                 .bits = {
1014                         .vga = true,
1015                         .i2c = true,
1016                         .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled
1017                         .dscl = true,
1018                         .cm = true,
1019                         .mpc = true,
1020                         .optc = true,
1021                         .vpg = true,
1022                         .afmt = true,
1023                 }
1024         },
1025         .optimize_edp_link_rate = true,
1026         .enable_sw_cntl_psr = true,
1027         .apply_vendor_specific_lttpr_wa = true,
1028 };
1029
1030 static const struct dc_debug_options debug_defaults_diags = {
1031         .disable_dmcu = true,
1032         .force_abm_enable = false,
1033         .timing_trace = true,
1034         .clock_trace = true,
1035         .disable_dpp_power_gate = true,
1036         .disable_hubp_power_gate = true,
1037         .disable_clock_gate = true,
1038         .disable_pplib_clock_request = true,
1039         .disable_pplib_wm_range = true,
1040         .disable_stutter = false,
1041         .scl_reset_length10 = true,
1042         .dwb_fi_phase = -1, // -1 = disable
1043         .dmub_command_table = true,
1044         .enable_tri_buf = true,
1045         .use_max_lb = true
1046 };
1047
1048 static void dcn31_dpp_destroy(struct dpp **dpp)
1049 {
1050         kfree(TO_DCN20_DPP(*dpp));
1051         *dpp = NULL;
1052 }
1053
1054 static struct dpp *dcn31_dpp_create(
1055         struct dc_context *ctx,
1056         uint32_t inst)
1057 {
1058         struct dcn3_dpp *dpp =
1059                 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);
1060
1061         if (!dpp)
1062                 return NULL;
1063
1064         if (dpp3_construct(dpp, ctx, inst,
1065                         &dpp_regs[inst], &tf_shift, &tf_mask))
1066                 return &dpp->base;
1067
1068         BREAK_TO_DEBUGGER();
1069         kfree(dpp);
1070         return NULL;
1071 }
1072
1073 static struct output_pixel_processor *dcn31_opp_create(
1074         struct dc_context *ctx, uint32_t inst)
1075 {
1076         struct dcn20_opp *opp =
1077                 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
1078
1079         if (!opp) {
1080                 BREAK_TO_DEBUGGER();
1081                 return NULL;
1082         }
1083
1084         dcn20_opp_construct(opp, ctx, inst,
1085                         &opp_regs[inst], &opp_shift, &opp_mask);
1086         return &opp->base;
1087 }
1088
1089 static struct dce_aux *dcn31_aux_engine_create(
1090         struct dc_context *ctx,
1091         uint32_t inst)
1092 {
1093         struct aux_engine_dce110 *aux_engine =
1094                 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
1095
1096         if (!aux_engine)
1097                 return NULL;
1098
1099         dce110_aux_engine_construct(aux_engine, ctx, inst,
1100                                     SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
1101                                     &aux_engine_regs[inst],
1102                                         &aux_mask,
1103                                         &aux_shift,
1104                                         ctx->dc->caps.extended_aux_timeout_support);
1105
1106         return &aux_engine->base;
1107 }
1108 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) }
1109
1110 static const struct dce_i2c_registers i2c_hw_regs[] = {
1111                 i2c_inst_regs(1),
1112                 i2c_inst_regs(2),
1113                 i2c_inst_regs(3),
1114                 i2c_inst_regs(4),
1115                 i2c_inst_regs(5),
1116 };
1117
1118 static const struct dce_i2c_shift i2c_shifts = {
1119                 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
1120 };
1121
1122 static const struct dce_i2c_mask i2c_masks = {
1123                 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK)
1124 };
1125
1126 static struct dce_i2c_hw *dcn31_i2c_hw_create(
1127         struct dc_context *ctx,
1128         uint32_t inst)
1129 {
1130         struct dce_i2c_hw *dce_i2c_hw =
1131                 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
1132
1133         if (!dce_i2c_hw)
1134                 return NULL;
1135
1136         dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
1137                                     &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
1138
1139         return dce_i2c_hw;
1140 }
1141 static struct mpc *dcn31_mpc_create(
1142                 struct dc_context *ctx,
1143                 int num_mpcc,
1144                 int num_rmu)
1145 {
1146         struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc),
1147                                           GFP_KERNEL);
1148
1149         if (!mpc30)
1150                 return NULL;
1151
1152         dcn30_mpc_construct(mpc30, ctx,
1153                         &mpc_regs,
1154                         &mpc_shift,
1155                         &mpc_mask,
1156                         num_mpcc,
1157                         num_rmu);
1158
1159         return &mpc30->base;
1160 }
1161
1162 static struct hubbub *dcn31_hubbub_create(struct dc_context *ctx)
1163 {
1164         int i;
1165
1166         struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub),
1167                                           GFP_KERNEL);
1168
1169         if (!hubbub3)
1170                 return NULL;
1171
1172         hubbub31_construct(hubbub3, ctx,
1173                         &hubbub_reg,
1174                         &hubbub_shift,
1175                         &hubbub_mask,
1176                         dcn3_1_ip.det_buffer_size_kbytes,
1177                         dcn3_1_ip.pixel_chunk_size_kbytes,
1178                         dcn3_1_ip.config_return_buffer_size_in_kbytes);
1179
1180
1181         for (i = 0; i < res_cap_dcn31.num_vmid; i++) {
1182                 struct dcn20_vmid *vmid = &hubbub3->vmid[i];
1183
1184                 vmid->ctx = ctx;
1185
1186                 vmid->regs = &vmid_regs[i];
1187                 vmid->shifts = &vmid_shifts;
1188                 vmid->masks = &vmid_masks;
1189         }
1190
1191         return &hubbub3->base;
1192 }
1193
1194 static struct timing_generator *dcn31_timing_generator_create(
1195                 struct dc_context *ctx,
1196                 uint32_t instance)
1197 {
1198         struct optc *tgn10 =
1199                 kzalloc(sizeof(struct optc), GFP_KERNEL);
1200
1201         if (!tgn10)
1202                 return NULL;
1203
1204         tgn10->base.inst = instance;
1205         tgn10->base.ctx = ctx;
1206
1207         tgn10->tg_regs = &optc_regs[instance];
1208         tgn10->tg_shift = &optc_shift;
1209         tgn10->tg_mask = &optc_mask;
1210
1211         dcn31_timing_generator_init(tgn10);
1212
1213         return &tgn10->base;
1214 }
1215
1216 static const struct encoder_feature_support link_enc_feature = {
1217                 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1218                 .max_hdmi_pixel_clock = 600000,
1219                 .hdmi_ycbcr420_supported = true,
1220                 .dp_ycbcr420_supported = true,
1221                 .fec_supported = true,
1222                 .flags.bits.IS_HBR2_CAPABLE = true,
1223                 .flags.bits.IS_HBR3_CAPABLE = true,
1224                 .flags.bits.IS_TPS3_CAPABLE = true,
1225                 .flags.bits.IS_TPS4_CAPABLE = true
1226 };
1227
1228 static struct link_encoder *dcn31_link_encoder_create(
1229         const struct encoder_init_data *enc_init_data)
1230 {
1231         struct dcn20_link_encoder *enc20 =
1232                 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1233
1234         if (!enc20)
1235                 return NULL;
1236
1237         dcn31_link_encoder_construct(enc20,
1238                         enc_init_data,
1239                         &link_enc_feature,
1240                         &link_enc_regs[enc_init_data->transmitter],
1241                         &link_enc_aux_regs[enc_init_data->channel - 1],
1242                         &link_enc_hpd_regs[enc_init_data->hpd_source],
1243                         &le_shift,
1244                         &le_mask);
1245
1246         return &enc20->enc10.base;
1247 }
1248
1249 /* Create a minimal link encoder object not associated with a particular
1250  * physical connector.
1251  * resource_funcs.link_enc_create_minimal
1252  */
1253 static struct link_encoder *dcn31_link_enc_create_minimal(
1254                 struct dc_context *ctx, enum engine_id eng_id)
1255 {
1256         struct dcn20_link_encoder *enc20;
1257
1258         if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)
1259                 return NULL;
1260
1261         enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1262         if (!enc20)
1263                 return NULL;
1264
1265         dcn31_link_encoder_construct_minimal(
1266                         enc20,
1267                         ctx,
1268                         &link_enc_feature,
1269                         &link_enc_regs[eng_id - ENGINE_ID_DIGA],
1270                         eng_id);
1271
1272         return &enc20->enc10.base;
1273 }
1274
1275 struct panel_cntl *dcn31_panel_cntl_create(const struct panel_cntl_init_data *init_data)
1276 {
1277         struct dcn31_panel_cntl *panel_cntl =
1278                 kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL);
1279
1280         if (!panel_cntl)
1281                 return NULL;
1282
1283         dcn31_panel_cntl_construct(panel_cntl, init_data);
1284
1285         return &panel_cntl->base;
1286 }
1287
1288 static void read_dce_straps(
1289         struct dc_context *ctx,
1290         struct resource_straps *straps)
1291 {
1292         generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX),
1293                 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1294
1295 }
1296
1297 static struct audio *dcn31_create_audio(
1298                 struct dc_context *ctx, unsigned int inst)
1299 {
1300         return dce_audio_create(ctx, inst,
1301                         &audio_regs[inst], &audio_shift, &audio_mask);
1302 }
1303
1304 static struct vpg *dcn31_vpg_create(
1305         struct dc_context *ctx,
1306         uint32_t inst)
1307 {
1308         struct dcn31_vpg *vpg31 = kzalloc(sizeof(struct dcn31_vpg), GFP_KERNEL);
1309
1310         if (!vpg31)
1311                 return NULL;
1312
1313         vpg31_construct(vpg31, ctx, inst,
1314                         &vpg_regs[inst],
1315                         &vpg_shift,
1316                         &vpg_mask);
1317
1318         return &vpg31->base;
1319 }
1320
1321 static struct afmt *dcn31_afmt_create(
1322         struct dc_context *ctx,
1323         uint32_t inst)
1324 {
1325         struct dcn31_afmt *afmt31 = kzalloc(sizeof(struct dcn31_afmt), GFP_KERNEL);
1326
1327         if (!afmt31)
1328                 return NULL;
1329
1330         afmt31_construct(afmt31, ctx, inst,
1331                         &afmt_regs[inst],
1332                         &afmt_shift,
1333                         &afmt_mask);
1334
1335         // Light sleep by default, no need to power down here
1336
1337         return &afmt31->base;
1338 }
1339
1340 static struct apg *dcn31_apg_create(
1341         struct dc_context *ctx,
1342         uint32_t inst)
1343 {
1344         struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL);
1345
1346         if (!apg31)
1347                 return NULL;
1348
1349         apg31_construct(apg31, ctx, inst,
1350                         &apg_regs[inst],
1351                         &apg_shift,
1352                         &apg_mask);
1353
1354         return &apg31->base;
1355 }
1356
1357 static struct stream_encoder *dcn31_stream_encoder_create(
1358         enum engine_id eng_id,
1359         struct dc_context *ctx)
1360 {
1361         struct dcn10_stream_encoder *enc1;
1362         struct vpg *vpg;
1363         struct afmt *afmt;
1364         int vpg_inst;
1365         int afmt_inst;
1366
1367         /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
1368         if (eng_id <= ENGINE_ID_DIGF) {
1369                 vpg_inst = eng_id;
1370                 afmt_inst = eng_id;
1371         } else
1372                 return NULL;
1373
1374         enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1375         vpg = dcn31_vpg_create(ctx, vpg_inst);
1376         afmt = dcn31_afmt_create(ctx, afmt_inst);
1377
1378         if (!enc1 || !vpg || !afmt) {
1379                 kfree(enc1);
1380                 kfree(vpg);
1381                 kfree(afmt);
1382                 return NULL;
1383         }
1384
1385         if (ctx->asic_id.chip_family == FAMILY_YELLOW_CARP &&
1386                         ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0) {
1387                 if ((eng_id == ENGINE_ID_DIGC) || (eng_id == ENGINE_ID_DIGD))
1388                         eng_id = eng_id + 3; // For B0 only. C->F, D->G.
1389         }
1390
1391         dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
1392                                         eng_id, vpg, afmt,
1393                                         &stream_enc_regs[eng_id],
1394                                         &se_shift, &se_mask);
1395
1396         return &enc1->base;
1397 }
1398
1399 static struct hpo_dp_stream_encoder *dcn31_hpo_dp_stream_encoder_create(
1400         enum engine_id eng_id,
1401         struct dc_context *ctx)
1402 {
1403         struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31;
1404         struct vpg *vpg;
1405         struct apg *apg;
1406         uint32_t hpo_dp_inst;
1407         uint32_t vpg_inst;
1408         uint32_t apg_inst;
1409
1410         ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3));
1411         hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0;
1412
1413         /* Mapping of VPG register blocks to HPO DP block instance:
1414          * VPG[6] -> HPO_DP[0]
1415          * VPG[7] -> HPO_DP[1]
1416          * VPG[8] -> HPO_DP[2]
1417          * VPG[9] -> HPO_DP[3]
1418          */
1419         vpg_inst = hpo_dp_inst + 6;
1420
1421         /* Mapping of APG register blocks to HPO DP block instance:
1422          * APG[0] -> HPO_DP[0]
1423          * APG[1] -> HPO_DP[1]
1424          * APG[2] -> HPO_DP[2]
1425          * APG[3] -> HPO_DP[3]
1426          */
1427         apg_inst = hpo_dp_inst;
1428
1429         /* allocate HPO stream encoder and create VPG sub-block */
1430         hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL);
1431         vpg = dcn31_vpg_create(ctx, vpg_inst);
1432         apg = dcn31_apg_create(ctx, apg_inst);
1433
1434         if (!hpo_dp_enc31 || !vpg || !apg) {
1435                 kfree(hpo_dp_enc31);
1436                 kfree(vpg);
1437                 kfree(apg);
1438                 return NULL;
1439         }
1440
1441         dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios,
1442                                         hpo_dp_inst, eng_id, vpg, apg,
1443                                         &hpo_dp_stream_enc_regs[hpo_dp_inst],
1444                                         &hpo_dp_se_shift, &hpo_dp_se_mask);
1445
1446         return &hpo_dp_enc31->base;
1447 }
1448
1449 static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create(
1450         uint8_t inst,
1451         struct dc_context *ctx)
1452 {
1453         struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31;
1454
1455         /* allocate HPO link encoder */
1456         hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL);
1457
1458         hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst,
1459                                         &hpo_dp_link_enc_regs[inst],
1460                                         &hpo_dp_le_shift, &hpo_dp_le_mask);
1461
1462         return &hpo_dp_enc31->base;
1463 }
1464
1465 static struct dce_hwseq *dcn31_hwseq_create(
1466         struct dc_context *ctx)
1467 {
1468         struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1469
1470         if (hws) {
1471                 hws->ctx = ctx;
1472                 hws->regs = &hwseq_reg;
1473                 hws->shifts = &hwseq_shift;
1474                 hws->masks = &hwseq_mask;
1475                 /* DCN3.1 FPGA Workaround
1476                  * Need to enable HPO DP Stream Encoder before setting OTG master enable.
1477                  * To do so, move calling function enable_stream_timing to only be done AFTER calling
1478                  * function core_link_enable_stream
1479                  */
1480                 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment))
1481                         hws->wa.dp_hpo_and_otg_sequence = true;
1482         }
1483         return hws;
1484 }
1485 static const struct resource_create_funcs res_create_funcs = {
1486         .read_dce_straps = read_dce_straps,
1487         .create_audio = dcn31_create_audio,
1488         .create_stream_encoder = dcn31_stream_encoder_create,
1489         .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create,
1490         .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create,
1491         .create_hwseq = dcn31_hwseq_create,
1492 };
1493
1494 static const struct resource_create_funcs res_create_maximus_funcs = {
1495         .read_dce_straps = NULL,
1496         .create_audio = NULL,
1497         .create_stream_encoder = NULL,
1498         .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create,
1499         .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create,
1500         .create_hwseq = dcn31_hwseq_create,
1501 };
1502
1503 static void dcn31_resource_destruct(struct dcn31_resource_pool *pool)
1504 {
1505         unsigned int i;
1506
1507         for (i = 0; i < pool->base.stream_enc_count; i++) {
1508                 if (pool->base.stream_enc[i] != NULL) {
1509                         if (pool->base.stream_enc[i]->vpg != NULL) {
1510                                 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1511                                 pool->base.stream_enc[i]->vpg = NULL;
1512                         }
1513                         if (pool->base.stream_enc[i]->afmt != NULL) {
1514                                 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
1515                                 pool->base.stream_enc[i]->afmt = NULL;
1516                         }
1517                         kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1518                         pool->base.stream_enc[i] = NULL;
1519                 }
1520         }
1521
1522         for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) {
1523                 if (pool->base.hpo_dp_stream_enc[i] != NULL) {
1524                         if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) {
1525                                 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg));
1526                                 pool->base.hpo_dp_stream_enc[i]->vpg = NULL;
1527                         }
1528                         if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) {
1529                                 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg));
1530                                 pool->base.hpo_dp_stream_enc[i]->apg = NULL;
1531                         }
1532                         kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i]));
1533                         pool->base.hpo_dp_stream_enc[i] = NULL;
1534                 }
1535         }
1536
1537         for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) {
1538                 if (pool->base.hpo_dp_link_enc[i] != NULL) {
1539                         kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i]));
1540                         pool->base.hpo_dp_link_enc[i] = NULL;
1541                 }
1542         }
1543
1544         for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1545                 if (pool->base.dscs[i] != NULL)
1546                         dcn20_dsc_destroy(&pool->base.dscs[i]);
1547         }
1548
1549         if (pool->base.mpc != NULL) {
1550                 kfree(TO_DCN20_MPC(pool->base.mpc));
1551                 pool->base.mpc = NULL;
1552         }
1553         if (pool->base.hubbub != NULL) {
1554                 kfree(pool->base.hubbub);
1555                 pool->base.hubbub = NULL;
1556         }
1557         for (i = 0; i < pool->base.pipe_count; i++) {
1558                 if (pool->base.dpps[i] != NULL)
1559                         dcn31_dpp_destroy(&pool->base.dpps[i]);
1560
1561                 if (pool->base.ipps[i] != NULL)
1562                         pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1563
1564                 if (pool->base.hubps[i] != NULL) {
1565                         kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1566                         pool->base.hubps[i] = NULL;
1567                 }
1568
1569                 if (pool->base.irqs != NULL) {
1570                         dal_irq_service_destroy(&pool->base.irqs);
1571                 }
1572         }
1573
1574         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1575                 if (pool->base.engines[i] != NULL)
1576                         dce110_engine_destroy(&pool->base.engines[i]);
1577                 if (pool->base.hw_i2cs[i] != NULL) {
1578                         kfree(pool->base.hw_i2cs[i]);
1579                         pool->base.hw_i2cs[i] = NULL;
1580                 }
1581                 if (pool->base.sw_i2cs[i] != NULL) {
1582                         kfree(pool->base.sw_i2cs[i]);
1583                         pool->base.sw_i2cs[i] = NULL;
1584                 }
1585         }
1586
1587         for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1588                 if (pool->base.opps[i] != NULL)
1589                         pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1590         }
1591
1592         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1593                 if (pool->base.timing_generators[i] != NULL)    {
1594                         kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1595                         pool->base.timing_generators[i] = NULL;
1596                 }
1597         }
1598
1599         for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1600                 if (pool->base.dwbc[i] != NULL) {
1601                         kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
1602                         pool->base.dwbc[i] = NULL;
1603                 }
1604                 if (pool->base.mcif_wb[i] != NULL) {
1605                         kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
1606                         pool->base.mcif_wb[i] = NULL;
1607                 }
1608         }
1609
1610         for (i = 0; i < pool->base.audio_count; i++) {
1611                 if (pool->base.audios[i])
1612                         dce_aud_destroy(&pool->base.audios[i]);
1613         }
1614
1615         for (i = 0; i < pool->base.clk_src_count; i++) {
1616                 if (pool->base.clock_sources[i] != NULL) {
1617                         dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1618                         pool->base.clock_sources[i] = NULL;
1619                 }
1620         }
1621
1622         for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
1623                 if (pool->base.mpc_lut[i] != NULL) {
1624                         dc_3dlut_func_release(pool->base.mpc_lut[i]);
1625                         pool->base.mpc_lut[i] = NULL;
1626                 }
1627                 if (pool->base.mpc_shaper[i] != NULL) {
1628                         dc_transfer_func_release(pool->base.mpc_shaper[i]);
1629                         pool->base.mpc_shaper[i] = NULL;
1630                 }
1631         }
1632
1633         if (pool->base.dp_clock_source != NULL) {
1634                 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1635                 pool->base.dp_clock_source = NULL;
1636         }
1637
1638         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1639                 if (pool->base.multiple_abms[i] != NULL)
1640                         dce_abm_destroy(&pool->base.multiple_abms[i]);
1641         }
1642
1643         if (pool->base.psr != NULL)
1644                 dmub_psr_destroy(&pool->base.psr);
1645
1646         if (pool->base.dccg != NULL)
1647                 dcn_dccg_destroy(&pool->base.dccg);
1648 }
1649
1650 static struct hubp *dcn31_hubp_create(
1651         struct dc_context *ctx,
1652         uint32_t inst)
1653 {
1654         struct dcn20_hubp *hubp2 =
1655                 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
1656
1657         if (!hubp2)
1658                 return NULL;
1659
1660         if (hubp31_construct(hubp2, ctx, inst,
1661                         &hubp_regs[inst], &hubp_shift, &hubp_mask))
1662                 return &hubp2->base;
1663
1664         BREAK_TO_DEBUGGER();
1665         kfree(hubp2);
1666         return NULL;
1667 }
1668
1669 static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1670 {
1671         int i;
1672         uint32_t pipe_count = pool->res_cap->num_dwb;
1673
1674         for (i = 0; i < pipe_count; i++) {
1675                 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc),
1676                                                     GFP_KERNEL);
1677
1678                 if (!dwbc30) {
1679                         dm_error("DC: failed to create dwbc30!\n");
1680                         return false;
1681                 }
1682
1683                 dcn30_dwbc_construct(dwbc30, ctx,
1684                                 &dwbc30_regs[i],
1685                                 &dwbc30_shift,
1686                                 &dwbc30_mask,
1687                                 i);
1688
1689                 pool->dwbc[i] = &dwbc30->base;
1690         }
1691         return true;
1692 }
1693
1694 static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1695 {
1696         int i;
1697         uint32_t pipe_count = pool->res_cap->num_dwb;
1698
1699         for (i = 0; i < pipe_count; i++) {
1700                 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub),
1701                                                     GFP_KERNEL);
1702
1703                 if (!mcif_wb30) {
1704                         dm_error("DC: failed to create mcif_wb30!\n");
1705                         return false;
1706                 }
1707
1708                 dcn30_mmhubbub_construct(mcif_wb30, ctx,
1709                                 &mcif_wb30_regs[i],
1710                                 &mcif_wb30_shift,
1711                                 &mcif_wb30_mask,
1712                                 i);
1713
1714                 pool->mcif_wb[i] = &mcif_wb30->base;
1715         }
1716         return true;
1717 }
1718
1719 static struct display_stream_compressor *dcn31_dsc_create(
1720         struct dc_context *ctx, uint32_t inst)
1721 {
1722         struct dcn20_dsc *dsc =
1723                 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1724
1725         if (!dsc) {
1726                 BREAK_TO_DEBUGGER();
1727                 return NULL;
1728         }
1729
1730         dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1731         return &dsc->base;
1732 }
1733
1734 static void dcn31_destroy_resource_pool(struct resource_pool **pool)
1735 {
1736         struct dcn31_resource_pool *dcn31_pool = TO_DCN31_RES_POOL(*pool);
1737
1738         dcn31_resource_destruct(dcn31_pool);
1739         kfree(dcn31_pool);
1740         *pool = NULL;
1741 }
1742
1743 static struct clock_source *dcn31_clock_source_create(
1744                 struct dc_context *ctx,
1745                 struct dc_bios *bios,
1746                 enum clock_source_id id,
1747                 const struct dce110_clk_src_regs *regs,
1748                 bool dp_clk_src)
1749 {
1750         struct dce110_clk_src *clk_src =
1751                 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1752
1753         if (!clk_src)
1754                 return NULL;
1755
1756         if (dcn3_clk_src_construct(clk_src, ctx, bios, id,
1757                         regs, &cs_shift, &cs_mask)) {
1758                 clk_src->base.dp_clk_src = dp_clk_src;
1759                 return &clk_src->base;
1760         }
1761
1762         BREAK_TO_DEBUGGER();
1763         return NULL;
1764 }
1765
1766 static bool is_dual_plane(enum surface_pixel_format format)
1767 {
1768         return format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN || format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA;
1769 }
1770
1771 static int dcn31_populate_dml_pipes_from_context(
1772         struct dc *dc, struct dc_state *context,
1773         display_e2e_pipe_params_st *pipes,
1774         bool fast_validate)
1775 {
1776         int i, pipe_cnt;
1777         struct resource_context *res_ctx = &context->res_ctx;
1778         struct pipe_ctx *pipe;
1779
1780         dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);
1781
1782         for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1783                 struct dc_crtc_timing *timing;
1784
1785                 if (!res_ctx->pipe_ctx[i].stream)
1786                         continue;
1787                 pipe = &res_ctx->pipe_ctx[i];
1788                 timing = &pipe->stream->timing;
1789
1790                 /*
1791                  * Immediate flip can be set dynamically after enabling the plane.
1792                  * We need to require support for immediate flip or underflow can be
1793                  * intermittently experienced depending on peak b/w requirements.
1794                  */
1795                 pipes[pipe_cnt].pipe.src.immediate_flip = true;
1796
1797                 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false;
1798                 pipes[pipe_cnt].pipe.src.gpuvm = true;
1799                 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_luma = 0;
1800                 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_chroma = 0;
1801                 pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch;
1802                 pipes[pipe_cnt].pipe.src.dcc_rate = 3;
1803                 pipes[pipe_cnt].dout.dsc_input_bpc = 0;
1804
1805                 if (pipes[pipe_cnt].dout.dsc_enable) {
1806                         switch (timing->display_color_depth) {
1807                         case COLOR_DEPTH_888:
1808                                 pipes[pipe_cnt].dout.dsc_input_bpc = 8;
1809                                 break;
1810                         case COLOR_DEPTH_101010:
1811                                 pipes[pipe_cnt].dout.dsc_input_bpc = 10;
1812                                 break;
1813                         case COLOR_DEPTH_121212:
1814                                 pipes[pipe_cnt].dout.dsc_input_bpc = 12;
1815                                 break;
1816                         default:
1817                                 ASSERT(0);
1818                                 break;
1819                         }
1820                 }
1821
1822                 pipe_cnt++;
1823         }
1824         context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_1_DEFAULT_DET_SIZE;
1825         dc->config.enable_4to1MPC = false;
1826         if (pipe_cnt == 1 && pipe->plane_state && !dc->debug.disable_z9_mpc) {
1827                 if (is_dual_plane(pipe->plane_state->format)
1828                                 && pipe->plane_state->src_rect.width <= 1920 && pipe->plane_state->src_rect.height <= 1080) {
1829                         dc->config.enable_4to1MPC = true;
1830                 } else if (!is_dual_plane(pipe->plane_state->format)) {
1831                         context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192;
1832                         pipes[0].pipe.src.unbounded_req_mode = true;
1833                 }
1834         } else if (context->stream_count >= dc->debug.crb_alloc_policy_min_disp_count
1835                         && dc->debug.crb_alloc_policy > DET_SIZE_DEFAULT) {
1836                 context->bw_ctx.dml.ip.det_buffer_size_kbytes = dc->debug.crb_alloc_policy * 64;
1837         }
1838
1839         return pipe_cnt;
1840 }
1841
1842 void dcn31_update_soc_for_wm_a(struct dc *dc, struct dc_state *context)
1843 {
1844         if (dc->clk_mgr->bw_params->wm_table.entries[WM_A].valid) {
1845                 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].pstate_latency_us;
1846                 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_enter_plus_exit_time_us;
1847                 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_exit_time_us;
1848         }
1849 }
1850
1851 static void dcn31_calculate_wm_and_dlg_fp(
1852                 struct dc *dc, struct dc_state *context,
1853                 display_e2e_pipe_params_st *pipes,
1854                 int pipe_cnt,
1855                 int vlevel)
1856 {
1857         int i, pipe_idx;
1858         double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
1859
1860         if (context->bw_ctx.dml.soc.min_dcfclk > dcfclk)
1861                 dcfclk = context->bw_ctx.dml.soc.min_dcfclk;
1862
1863         /* We don't recalculate clocks for 0 pipe configs, which can block
1864          * S0i3 as high clocks will block low power states
1865          * Override any clocks that can block S0i3 to min here
1866          */
1867         if (pipe_cnt == 0) {
1868                 context->bw_ctx.bw.dcn.clk.dcfclk_khz = dcfclk; // always should be vlevel 0
1869                 return;
1870         }
1871
1872         pipes[0].clks_cfg.voltage = vlevel;
1873         pipes[0].clks_cfg.dcfclk_mhz = dcfclk;
1874         pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
1875
1876 #if 0 // TODO
1877         /* Set B:
1878          * TODO
1879          */
1880         if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].valid) {
1881                 if (vlevel == 0) {
1882                         pipes[0].clks_cfg.voltage = 1;
1883                         pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dcfclk_mhz;
1884                 }
1885                 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_latency_us;
1886                 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us;
1887                 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us;
1888         }
1889         context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1890         context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1891         context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1892         context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_z8_ns = get_wm_z8_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1893         context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_z8_ns = get_wm_z8_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1894         context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1895         context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1896         context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1897         context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1898         context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1899
1900         pipes[0].clks_cfg.voltage = vlevel;
1901         pipes[0].clks_cfg.dcfclk_mhz = dcfclk;
1902
1903         /* Set C:
1904          * TODO
1905          */
1906         if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid) {
1907                 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.pstate_latency_us;
1908                 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us;
1909                 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us;
1910         }
1911         context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1912         context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1913         context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1914         context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_z8_ns = get_wm_z8_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1915         context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_z8_ns = get_wm_z8_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1916         context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1917         context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1918         context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1919         context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1920         context->bw_ctx.bw.dcn.watermarks.c.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1921
1922         /* Set D:
1923          * TODO
1924          */
1925         if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].valid) {
1926                 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.pstate_latency_us;
1927                 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_enter_plus_exit_time_us;
1928                 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_exit_time_us;
1929         }
1930         context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1931         context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1932         context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1933         context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1934         context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_z8_ns = get_wm_z8_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1935         context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_z8_ns = get_wm_z8_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1936         context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1937         context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1938         context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1939         context->bw_ctx.bw.dcn.watermarks.d.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1940 #endif
1941
1942         /* Set A:
1943          * All clocks min required
1944          *
1945          * Set A calculated last so that following calculations are based on Set A
1946          */
1947         dc->res_pool->funcs->update_soc_for_wm_a(dc, context);
1948         context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1949         context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1950         context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1951         context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1952         context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_z8_ns = get_wm_z8_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1953         context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_z8_ns = get_wm_z8_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1954         context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1955         context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1956         context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1957         context->bw_ctx.bw.dcn.watermarks.a.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1958         /* TODO: remove: */
1959         context->bw_ctx.bw.dcn.watermarks.b = context->bw_ctx.bw.dcn.watermarks.a;
1960         context->bw_ctx.bw.dcn.watermarks.c = context->bw_ctx.bw.dcn.watermarks.a;
1961         context->bw_ctx.bw.dcn.watermarks.d = context->bw_ctx.bw.dcn.watermarks.a;
1962         /* end remove*/
1963
1964         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
1965                 if (!context->res_ctx.pipe_ctx[i].stream)
1966                         continue;
1967
1968                 pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt);
1969                 pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
1970
1971                 if (dc->config.forced_clocks) {
1972                         pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz;
1973                         pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz;
1974                 }
1975                 if (dc->debug.min_disp_clk_khz > pipes[pipe_idx].clks_cfg.dispclk_mhz * 1000)
1976                         pipes[pipe_idx].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0;
1977                 if (dc->debug.min_dpp_clk_khz > pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)
1978                         pipes[pipe_idx].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0;
1979
1980                 pipe_idx++;
1981         }
1982
1983         dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
1984 }
1985
1986 void dcn31_calculate_wm_and_dlg(
1987                 struct dc *dc, struct dc_state *context,
1988                 display_e2e_pipe_params_st *pipes,
1989                 int pipe_cnt,
1990                 int vlevel)
1991 {
1992         DC_FP_START();
1993         dcn31_calculate_wm_and_dlg_fp(dc, context, pipes, pipe_cnt, vlevel);
1994         DC_FP_END();
1995 }
1996
1997 bool dcn31_validate_bandwidth(struct dc *dc,
1998                 struct dc_state *context,
1999                 bool fast_validate)
2000 {
2001         bool out = false;
2002
2003         BW_VAL_TRACE_SETUP();
2004
2005         int vlevel = 0;
2006         int pipe_cnt = 0;
2007         display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
2008         DC_LOGGER_INIT(dc->ctx->logger);
2009
2010         BW_VAL_TRACE_COUNT();
2011
2012         out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate);
2013
2014         // Disable fast_validate to set min dcfclk in alculate_wm_and_dlg
2015         if (pipe_cnt == 0)
2016                 fast_validate = false;
2017
2018         if (!out)
2019                 goto validate_fail;
2020
2021         BW_VAL_TRACE_END_VOLTAGE_LEVEL();
2022
2023         if (fast_validate) {
2024                 BW_VAL_TRACE_SKIP(fast);
2025                 goto validate_out;
2026         }
2027
2028         dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel);
2029
2030         BW_VAL_TRACE_END_WATERMARKS();
2031
2032         goto validate_out;
2033
2034 validate_fail:
2035         DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
2036                 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
2037
2038         BW_VAL_TRACE_SKIP(fail);
2039         out = false;
2040
2041 validate_out:
2042         kfree(pipes);
2043
2044         BW_VAL_TRACE_FINISH();
2045
2046         return out;
2047 }
2048
2049 static struct dc_cap_funcs cap_funcs = {
2050         .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
2051 };
2052
2053 static void dcn31_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
2054 {
2055         struct clk_limit_table *clk_table = &bw_params->clk_table;
2056         struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];
2057         unsigned int i, closest_clk_lvl;
2058         int j;
2059
2060         // Default clock levels are used for diags, which may lead to overclocking.
2061         if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
2062                 int max_dispclk_mhz = 0, max_dppclk_mhz = 0;
2063
2064                 dcn3_1_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator;
2065                 dcn3_1_ip.max_num_dpp = dc->res_pool->pipe_count;
2066                 dcn3_1_soc.num_chans = bw_params->num_channels;
2067
2068                 ASSERT(clk_table->num_entries);
2069
2070                 /* Prepass to find max clocks independent of voltage level. */
2071                 for (i = 0; i < clk_table->num_entries; ++i) {
2072                         if (clk_table->entries[i].dispclk_mhz > max_dispclk_mhz)
2073                                 max_dispclk_mhz = clk_table->entries[i].dispclk_mhz;
2074                         if (clk_table->entries[i].dppclk_mhz > max_dppclk_mhz)
2075                                 max_dppclk_mhz = clk_table->entries[i].dppclk_mhz;
2076                 }
2077
2078                 for (i = 0; i < clk_table->num_entries; i++) {
2079                         /* loop backwards*/
2080                         for (closest_clk_lvl = 0, j = dcn3_1_soc.num_states - 1; j >= 0; j--) {
2081                                 if ((unsigned int) dcn3_1_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) {
2082                                         closest_clk_lvl = j;
2083                                         break;
2084                                 }
2085                         }
2086
2087                         clock_limits[i].state = i;
2088
2089                         /* Clocks dependent on voltage level. */
2090                         clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
2091                         clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
2092                         clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz;
2093                         clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2 * clk_table->entries[i].wck_ratio;
2094
2095                         /* Clocks independent of voltage level. */
2096                         clock_limits[i].dispclk_mhz = max_dispclk_mhz ? max_dispclk_mhz :
2097                                 dcn3_1_soc.clock_limits[closest_clk_lvl].dispclk_mhz;
2098
2099                         clock_limits[i].dppclk_mhz = max_dppclk_mhz ? max_dppclk_mhz :
2100                                 dcn3_1_soc.clock_limits[closest_clk_lvl].dppclk_mhz;
2101
2102                         clock_limits[i].dram_bw_per_chan_gbps = dcn3_1_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
2103                         clock_limits[i].dscclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
2104                         clock_limits[i].dtbclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
2105                         clock_limits[i].phyclk_d18_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
2106                         clock_limits[i].phyclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
2107                 }
2108                 for (i = 0; i < clk_table->num_entries; i++)
2109                         dcn3_1_soc.clock_limits[i] = clock_limits[i];
2110                 if (clk_table->num_entries) {
2111                         dcn3_1_soc.num_states = clk_table->num_entries;
2112                 }
2113         }
2114
2115         dcn3_1_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
2116         dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
2117
2118         if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
2119                 dml_init_instance(&dc->dml, &dcn3_1_soc, &dcn3_1_ip, DML_PROJECT_DCN31);
2120         else
2121                 dml_init_instance(&dc->dml, &dcn3_1_soc, &dcn3_1_ip, DML_PROJECT_DCN31_FPGA);
2122 }
2123
2124 static struct resource_funcs dcn31_res_pool_funcs = {
2125         .destroy = dcn31_destroy_resource_pool,
2126         .link_enc_create = dcn31_link_encoder_create,
2127         .link_enc_create_minimal = dcn31_link_enc_create_minimal,
2128         .link_encs_assign = link_enc_cfg_link_encs_assign,
2129         .link_enc_unassign = link_enc_cfg_link_enc_unassign,
2130         .panel_cntl_create = dcn31_panel_cntl_create,
2131         .validate_bandwidth = dcn31_validate_bandwidth,
2132         .calculate_wm_and_dlg = dcn31_calculate_wm_and_dlg,
2133         .update_soc_for_wm_a = dcn31_update_soc_for_wm_a,
2134         .populate_dml_pipes = dcn31_populate_dml_pipes_from_context,
2135         .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
2136         .add_stream_to_ctx = dcn30_add_stream_to_ctx,
2137         .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
2138         .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
2139         .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
2140         .set_mcif_arb_params = dcn30_set_mcif_arb_params,
2141         .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
2142         .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
2143         .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
2144         .update_bw_bounding_box = dcn31_update_bw_bounding_box,
2145         .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
2146 };
2147
2148 static struct clock_source *dcn30_clock_source_create(
2149                 struct dc_context *ctx,
2150                 struct dc_bios *bios,
2151                 enum clock_source_id id,
2152                 const struct dce110_clk_src_regs *regs,
2153                 bool dp_clk_src)
2154 {
2155         struct dce110_clk_src *clk_src =
2156                 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
2157
2158         if (!clk_src)
2159                 return NULL;
2160
2161         if (dcn3_clk_src_construct(clk_src, ctx, bios, id,
2162                         regs, &cs_shift, &cs_mask)) {
2163                 clk_src->base.dp_clk_src = dp_clk_src;
2164                 return &clk_src->base;
2165         }
2166
2167         BREAK_TO_DEBUGGER();
2168         return NULL;
2169 }
2170
2171 static bool dcn31_resource_construct(
2172         uint8_t num_virtual_links,
2173         struct dc *dc,
2174         struct dcn31_resource_pool *pool)
2175 {
2176         int i;
2177         struct dc_context *ctx = dc->ctx;
2178         struct irq_service_init_data init_data;
2179
2180         DC_FP_START();
2181
2182         ctx->dc_bios->regs = &bios_regs;
2183
2184         pool->base.res_cap = &res_cap_dcn31;
2185
2186         pool->base.funcs = &dcn31_res_pool_funcs;
2187
2188         /*************************************************
2189          *  Resource + asic cap harcoding                *
2190          *************************************************/
2191         pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
2192         pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
2193         pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
2194         dc->caps.max_downscale_ratio = 600;
2195         dc->caps.i2c_speed_in_khz = 100;
2196         dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by default*/
2197         dc->caps.max_cursor_size = 256;
2198         dc->caps.min_horizontal_blanking_period = 80;
2199         dc->caps.dmdata_alloc_size = 2048;
2200
2201         dc->caps.max_slave_planes = 1;
2202         dc->caps.max_slave_yuv_planes = 1;
2203         dc->caps.max_slave_rgb_planes = 1;
2204         dc->caps.post_blend_color_processing = true;
2205         dc->caps.force_dp_tps4_for_cp2520 = true;
2206         dc->caps.dp_hpo = true;
2207         dc->caps.hdmi_frl_pcon_support = true;
2208         dc->caps.edp_dsc_support = true;
2209         dc->caps.extended_aux_timeout_support = true;
2210         dc->caps.dmcub_support = true;
2211         dc->caps.is_apu = true;
2212
2213         /* Color pipeline capabilities */
2214         dc->caps.color.dpp.dcn_arch = 1;
2215         dc->caps.color.dpp.input_lut_shared = 0;
2216         dc->caps.color.dpp.icsc = 1;
2217         dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
2218         dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
2219         dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
2220         dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
2221         dc->caps.color.dpp.dgam_rom_caps.pq = 1;
2222         dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
2223         dc->caps.color.dpp.post_csc = 1;
2224         dc->caps.color.dpp.gamma_corr = 1;
2225         dc->caps.color.dpp.dgam_rom_for_yuv = 0;
2226
2227         dc->caps.color.dpp.hw_3d_lut = 1;
2228         dc->caps.color.dpp.ogam_ram = 1;
2229         // no OGAM ROM on DCN301
2230         dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
2231         dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
2232         dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
2233         dc->caps.color.dpp.ogam_rom_caps.pq = 0;
2234         dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
2235         dc->caps.color.dpp.ocsc = 0;
2236
2237         dc->caps.color.mpc.gamut_remap = 1;
2238         dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2
2239         dc->caps.color.mpc.ogam_ram = 1;
2240         dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
2241         dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
2242         dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
2243         dc->caps.color.mpc.ogam_rom_caps.pq = 0;
2244         dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
2245         dc->caps.color.mpc.ocsc = 1;
2246
2247         /* Use pipe context based otg sync logic */
2248         dc->config.use_pipe_ctx_sync_logic = true;
2249
2250         /* read VBIOS LTTPR caps */
2251         {
2252                 if (ctx->dc_bios->funcs->get_lttpr_caps) {
2253                         enum bp_result bp_query_result;
2254                         uint8_t is_vbios_lttpr_enable = 0;
2255
2256                         bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
2257                         dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
2258                 }
2259
2260                 /* interop bit is implicit */
2261                 {
2262                         dc->caps.vbios_lttpr_aware = true;
2263                 }
2264         }
2265
2266         if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
2267                 dc->debug = debug_defaults_drv;
2268         else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
2269                 dc->debug = debug_defaults_diags;
2270         } else
2271                 dc->debug = debug_defaults_diags;
2272         // Init the vm_helper
2273         if (dc->vm_helper)
2274                 vm_helper_init(dc->vm_helper, 16);
2275
2276         /*************************************************
2277          *  Create resources                             *
2278          *************************************************/
2279
2280         /* Clock Sources for Pixel Clock*/
2281         pool->base.clock_sources[DCN31_CLK_SRC_PLL0] =
2282                         dcn30_clock_source_create(ctx, ctx->dc_bios,
2283                                 CLOCK_SOURCE_COMBO_PHY_PLL0,
2284                                 &clk_src_regs[0], false);
2285         pool->base.clock_sources[DCN31_CLK_SRC_PLL1] =
2286                         dcn30_clock_source_create(ctx, ctx->dc_bios,
2287                                 CLOCK_SOURCE_COMBO_PHY_PLL1,
2288                                 &clk_src_regs[1], false);
2289         pool->base.clock_sources[DCN31_CLK_SRC_PLL2] =
2290                         dcn30_clock_source_create(ctx, ctx->dc_bios,
2291                                 CLOCK_SOURCE_COMBO_PHY_PLL2,
2292                                 &clk_src_regs[2], false);
2293         pool->base.clock_sources[DCN31_CLK_SRC_PLL3] =
2294                         dcn30_clock_source_create(ctx, ctx->dc_bios,
2295                                 CLOCK_SOURCE_COMBO_PHY_PLL3,
2296                                 &clk_src_regs[3], false);
2297         pool->base.clock_sources[DCN31_CLK_SRC_PLL4] =
2298                         dcn30_clock_source_create(ctx, ctx->dc_bios,
2299                                 CLOCK_SOURCE_COMBO_PHY_PLL4,
2300                                 &clk_src_regs[4], false);
2301
2302         pool->base.clk_src_count = DCN30_CLK_SRC_TOTAL;
2303
2304         /* todo: not reuse phy_pll registers */
2305         pool->base.dp_clock_source =
2306                         dcn31_clock_source_create(ctx, ctx->dc_bios,
2307                                 CLOCK_SOURCE_ID_DP_DTO,
2308                                 &clk_src_regs[0], true);
2309
2310         for (i = 0; i < pool->base.clk_src_count; i++) {
2311                 if (pool->base.clock_sources[i] == NULL) {
2312                         dm_error("DC: failed to create clock sources!\n");
2313                         BREAK_TO_DEBUGGER();
2314                         goto create_fail;
2315                 }
2316         }
2317
2318         /* TODO: DCCG */
2319         pool->base.dccg = dccg31_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
2320         if (pool->base.dccg == NULL) {
2321                 dm_error("DC: failed to create dccg!\n");
2322                 BREAK_TO_DEBUGGER();
2323                 goto create_fail;
2324         }
2325
2326         /* TODO: IRQ */
2327         init_data.ctx = dc->ctx;
2328         pool->base.irqs = dal_irq_service_dcn31_create(&init_data);
2329         if (!pool->base.irqs)
2330                 goto create_fail;
2331
2332         /* HUBBUB */
2333         pool->base.hubbub = dcn31_hubbub_create(ctx);
2334         if (pool->base.hubbub == NULL) {
2335                 BREAK_TO_DEBUGGER();
2336                 dm_error("DC: failed to create hubbub!\n");
2337                 goto create_fail;
2338         }
2339
2340         /* HUBPs, DPPs, OPPs and TGs */
2341         for (i = 0; i < pool->base.pipe_count; i++) {
2342                 pool->base.hubps[i] = dcn31_hubp_create(ctx, i);
2343                 if (pool->base.hubps[i] == NULL) {
2344                         BREAK_TO_DEBUGGER();
2345                         dm_error(
2346                                 "DC: failed to create hubps!\n");
2347                         goto create_fail;
2348                 }
2349
2350                 pool->base.dpps[i] = dcn31_dpp_create(ctx, i);
2351                 if (pool->base.dpps[i] == NULL) {
2352                         BREAK_TO_DEBUGGER();
2353                         dm_error(
2354                                 "DC: failed to create dpps!\n");
2355                         goto create_fail;
2356                 }
2357         }
2358
2359         for (i = 0; i < pool->base.res_cap->num_opp; i++) {
2360                 pool->base.opps[i] = dcn31_opp_create(ctx, i);
2361                 if (pool->base.opps[i] == NULL) {
2362                         BREAK_TO_DEBUGGER();
2363                         dm_error(
2364                                 "DC: failed to create output pixel processor!\n");
2365                         goto create_fail;
2366                 }
2367         }
2368
2369         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2370                 pool->base.timing_generators[i] = dcn31_timing_generator_create(
2371                                 ctx, i);
2372                 if (pool->base.timing_generators[i] == NULL) {
2373                         BREAK_TO_DEBUGGER();
2374                         dm_error("DC: failed to create tg!\n");
2375                         goto create_fail;
2376                 }
2377         }
2378         pool->base.timing_generator_count = i;
2379
2380         /* PSR */
2381         pool->base.psr = dmub_psr_create(ctx);
2382         if (pool->base.psr == NULL) {
2383                 dm_error("DC: failed to create psr obj!\n");
2384                 BREAK_TO_DEBUGGER();
2385                 goto create_fail;
2386         }
2387
2388         /* ABM */
2389         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2390                 pool->base.multiple_abms[i] = dmub_abm_create(ctx,
2391                                 &abm_regs[i],
2392                                 &abm_shift,
2393                                 &abm_mask);
2394                 if (pool->base.multiple_abms[i] == NULL) {
2395                         dm_error("DC: failed to create abm for pipe %d!\n", i);
2396                         BREAK_TO_DEBUGGER();
2397                         goto create_fail;
2398                 }
2399         }
2400
2401         /* MPC and DSC */
2402         pool->base.mpc = dcn31_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);
2403         if (pool->base.mpc == NULL) {
2404                 BREAK_TO_DEBUGGER();
2405                 dm_error("DC: failed to create mpc!\n");
2406                 goto create_fail;
2407         }
2408
2409         for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
2410                 pool->base.dscs[i] = dcn31_dsc_create(ctx, i);
2411                 if (pool->base.dscs[i] == NULL) {
2412                         BREAK_TO_DEBUGGER();
2413                         dm_error("DC: failed to create display stream compressor %d!\n", i);
2414                         goto create_fail;
2415                 }
2416         }
2417
2418         /* DWB and MMHUBBUB */
2419         if (!dcn31_dwbc_create(ctx, &pool->base)) {
2420                 BREAK_TO_DEBUGGER();
2421                 dm_error("DC: failed to create dwbc!\n");
2422                 goto create_fail;
2423         }
2424
2425         if (!dcn31_mmhubbub_create(ctx, &pool->base)) {
2426                 BREAK_TO_DEBUGGER();
2427                 dm_error("DC: failed to create mcif_wb!\n");
2428                 goto create_fail;
2429         }
2430
2431         /* AUX and I2C */
2432         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
2433                 pool->base.engines[i] = dcn31_aux_engine_create(ctx, i);
2434                 if (pool->base.engines[i] == NULL) {
2435                         BREAK_TO_DEBUGGER();
2436                         dm_error(
2437                                 "DC:failed to create aux engine!!\n");
2438                         goto create_fail;
2439                 }
2440                 pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i);
2441                 if (pool->base.hw_i2cs[i] == NULL) {
2442                         BREAK_TO_DEBUGGER();
2443                         dm_error(
2444                                 "DC:failed to create hw i2c!!\n");
2445                         goto create_fail;
2446                 }
2447                 pool->base.sw_i2cs[i] = NULL;
2448         }
2449
2450         if (dc->ctx->asic_id.chip_family == FAMILY_YELLOW_CARP &&
2451             dc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0 &&
2452             !dc->debug.dpia_debug.bits.disable_dpia) {
2453                 /* YELLOW CARP B0 has 4 DPIA's */
2454                 pool->base.usb4_dpia_count = 4;
2455         }
2456
2457         /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */
2458         if (!resource_construct(num_virtual_links, dc, &pool->base,
2459                         (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
2460                         &res_create_funcs : &res_create_maximus_funcs)))
2461                         goto create_fail;
2462
2463         /* HW Sequencer and Plane caps */
2464         dcn31_hw_sequencer_construct(dc);
2465
2466         dc->caps.max_planes =  pool->base.pipe_count;
2467
2468         for (i = 0; i < dc->caps.max_planes; ++i)
2469                 dc->caps.planes[i] = plane_cap;
2470
2471         dc->cap_funcs = cap_funcs;
2472
2473         dc->dcn_ip->max_num_dpp = dcn3_1_ip.max_num_dpp;
2474
2475         DC_FP_END();
2476
2477         return true;
2478
2479 create_fail:
2480
2481         DC_FP_END();
2482         dcn31_resource_destruct(pool);
2483
2484         return false;
2485 }
2486
2487 struct resource_pool *dcn31_create_resource_pool(
2488                 const struct dc_init_data *init_data,
2489                 struct dc *dc)
2490 {
2491         struct dcn31_resource_pool *pool =
2492                 kzalloc(sizeof(struct dcn31_resource_pool), GFP_KERNEL);
2493
2494         if (!pool)
2495                 return NULL;
2496
2497         if (dcn31_resource_construct(init_data->num_virtual_links, dc, pool))
2498                 return &pool->base;
2499
2500         BREAK_TO_DEBUGGER();
2501         kfree(pool);
2502         return NULL;
2503 }