drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_offset.h

   1 /*
   2  * Copyright (C) 2018  Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included
  12  * in all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  15  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
  18  * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  19  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  */
  21 #ifndef _df_3_6_OFFSET_HEADER
  22 #define _df_3_6_OFFSET_HEADER
  23
  24 #define mmFabricConfigAccessControl                                                                     0x0410
  25 #define mmFabricConfigAccessControl_BASE_IDX                                                            0
  26
  27 #define mmDF_PIE_AON0_DfGlobalClkGater                                                                  0x00fc
  28 #define mmDF_PIE_AON0_DfGlobalClkGater_BASE_IDX                                                         0
  29
  30 #define mmDF_CS_UMC_AON0_DfGlobalCtrl                                                                   0x00fe
  31 #define mmDF_CS_UMC_AON0_DfGlobalCtrl_BASE_IDX                                                          0
  32
  33 #define mmDF_CS_UMC_AON0_DramBaseAddress0                                                               0x0044
  34 #define mmDF_CS_UMC_AON0_DramBaseAddress0_BASE_IDX                                                      0
  35
  36 #define smnPerfMonCtlLo0                                        0x01d440UL
  37 #define smnPerfMonCtlHi0                                        0x01d444UL
  38 #define smnPerfMonCtlLo1                                        0x01d450UL
  39 #define smnPerfMonCtlHi1                                        0x01d454UL
  40 #define smnPerfMonCtlLo2                                        0x01d460UL
  41 #define smnPerfMonCtlHi2                                        0x01d464UL
  42 #define smnPerfMonCtlLo3                                        0x01d470UL
  43 #define smnPerfMonCtlHi3                                        0x01d474UL
  44 #define smnPerfMonCtlLo4                                        0x01d880UL
  45 #define smnPerfMonCtlHi4                                        0x01d884UL
  46 #define smnPerfMonCtlLo5                                        0x01d888UL
  47 #define smnPerfMonCtlHi5                                        0x01d88cUL
  48 #define smnPerfMonCtlLo6                                        0x01d890UL
  49 #define smnPerfMonCtlHi6                                        0x01d894UL
  50 #define smnPerfMonCtlLo7                                        0x01d898UL
  51 #define smnPerfMonCtlHi7                                        0x01d89cUL
  52
  53 #define smnPerfMonCtrLo0                                        0x01d448UL
  54 #define smnPerfMonCtrHi0                                        0x01d44cUL
  55 #define smnPerfMonCtrLo1                                        0x01d458UL
  56 #define smnPerfMonCtrHi1                                        0x01d45cUL
  57 #define smnPerfMonCtrLo2                                        0x01d468UL
  58 #define smnPerfMonCtrHi2                                        0x01d46cUL
  59 #define smnPerfMonCtrLo3                                        0x01d478UL
  60 #define smnPerfMonCtrHi3                                        0x01d47cUL
  61 #define smnPerfMonCtrLo4                                        0x01d790UL
  62 #define smnPerfMonCtrHi4                                        0x01d794UL
  63 #define smnPerfMonCtrLo5                                        0x01d798UL
  64 #define smnPerfMonCtrHi5                                        0x01d79cUL
  65 #define smnPerfMonCtrLo6                                        0x01d7a0UL
  66 #define smnPerfMonCtrHi6                                        0x01d7a4UL
  67 #define smnPerfMonCtrLo7                                        0x01d7a8UL
  68 #define smnPerfMonCtrHi7                                        0x01d7acUL
  69
  70 #define smnDF_PIE_AON_FabricIndirectConfigAccessAddress3        0x1d05cUL
  71 #define smnDF_PIE_AON_FabricIndirectConfigAccessDataLo3         0x1d098UL
  72 #define smnDF_PIE_AON_FabricIndirectConfigAccessDataHi3         0x1d09cUL
  73
  74 #endif