2 * Copyright (C) 2018 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
21 #ifndef _cyan_skillfish_ip_offset_HEADER
22 #define _cyan_skillfish_ip_offset_HEADER
24 #define MAX_INSTANCE 6
28 struct IP_BASE_INSTANCE
30 unsigned int segment[MAX_SEGMENT];
35 struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
39 static const struct IP_BASE ATHUB_BASE ={ { { { 0x00000C00, 0, 0, 0, 0 } },
40 { { 0, 0, 0, 0, 0 } },
41 { { 0, 0, 0, 0, 0 } },
42 { { 0, 0, 0, 0, 0 } },
43 { { 0, 0, 0, 0, 0 } },
44 { { 0, 0, 0, 0, 0 } } } };
45 static const struct IP_BASE CLK_BASE ={ { { { 0x00016C00, 0, 0, 0, 0 } },
46 { { 0x00016E00, 0, 0, 0, 0 } },
47 { { 0x00017000, 0, 0, 0, 0 } },
48 { { 0x00017200, 0, 0, 0, 0 } },
49 { { 0x00017E00, 0, 0, 0, 0 } },
50 { { 0x0001B000, 0, 0, 0, 0 } } } };
51 static const struct IP_BASE DF_BASE ={ { { { 0x00007000, 0, 0, 0, 0 } },
52 { { 0, 0, 0, 0, 0 } },
53 { { 0, 0, 0, 0, 0 } },
54 { { 0, 0, 0, 0, 0 } },
55 { { 0, 0, 0, 0, 0 } },
56 { { 0, 0, 0, 0, 0 } } } };
57 static const struct IP_BASE DMU_BASE ={ { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0 } },
58 { { 0, 0, 0, 0, 0 } },
59 { { 0, 0, 0, 0, 0 } },
60 { { 0, 0, 0, 0, 0 } },
61 { { 0, 0, 0, 0, 0 } },
62 { { 0, 0, 0, 0, 0 } } } };
63 static const struct IP_BASE FUSE_BASE ={ { { { 0x00017400, 0, 0, 0, 0 } },
64 { { 0, 0, 0, 0, 0 } },
65 { { 0, 0, 0, 0, 0 } },
66 { { 0, 0, 0, 0, 0 } },
67 { { 0, 0, 0, 0, 0 } },
68 { { 0, 0, 0, 0, 0 } } } };
69 static const struct IP_BASE GC_BASE ={ { { { 0x00001260, 0x0000A000, 0, 0, 0 } },
70 { { 0, 0, 0, 0, 0 } },
71 { { 0, 0, 0, 0, 0 } },
72 { { 0, 0, 0, 0, 0 } },
73 { { 0, 0, 0, 0, 0 } },
74 { { 0, 0, 0, 0, 0 } } } };
75 static const struct IP_BASE HDP_BASE ={ { { { 0x00000F20, 0, 0, 0, 0 } },
76 { { 0, 0, 0, 0, 0 } },
77 { { 0, 0, 0, 0, 0 } },
78 { { 0, 0, 0, 0, 0 } },
79 { { 0, 0, 0, 0, 0 } },
80 { { 0, 0, 0, 0, 0 } } } };
81 static const struct IP_BASE MMHUB_BASE ={ { { { 0x0001A000, 0, 0, 0, 0 } },
82 { { 0, 0, 0, 0, 0 } },
83 { { 0, 0, 0, 0, 0 } },
84 { { 0, 0, 0, 0, 0 } },
85 { { 0, 0, 0, 0, 0 } },
86 { { 0, 0, 0, 0, 0 } } } };
87 static const struct IP_BASE MP0_BASE ={ { { { 0x00016000, 0, 0, 0, 0 } },
88 { { 0, 0, 0, 0, 0 } },
89 { { 0, 0, 0, 0, 0 } },
90 { { 0, 0, 0, 0, 0 } },
91 { { 0, 0, 0, 0, 0 } },
92 { { 0, 0, 0, 0, 0 } } } };
93 static const struct IP_BASE MP1_BASE ={ { { { 0x00016000, 0, 0, 0, 0 } },
94 { { 0, 0, 0, 0, 0 } },
95 { { 0, 0, 0, 0, 0 } },
96 { { 0, 0, 0, 0, 0 } },
97 { { 0, 0, 0, 0, 0 } },
98 { { 0, 0, 0, 0, 0 } } } };
99 static const struct IP_BASE NBIO_BASE ={ { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0 } },
100 { { 0, 0, 0, 0, 0 } },
101 { { 0, 0, 0, 0, 0 } },
102 { { 0, 0, 0, 0, 0 } },
103 { { 0, 0, 0, 0, 0 } },
104 { { 0, 0, 0, 0, 0 } } } };
105 static const struct IP_BASE OSSSYS_BASE ={ { { { 0x000010A0, 0, 0, 0, 0 } },
106 { { 0, 0, 0, 0, 0 } },
107 { { 0, 0, 0, 0, 0 } },
108 { { 0, 0, 0, 0, 0 } },
109 { { 0, 0, 0, 0, 0 } },
110 { { 0, 0, 0, 0, 0 } } } };
111 static const struct IP_BASE SMUIO_BASE ={ { { { 0x00016800, 0x00016A00, 0, 0, 0 } },
112 { { 0, 0, 0, 0, 0 } },
113 { { 0, 0, 0, 0, 0 } },
114 { { 0, 0, 0, 0, 0 } },
115 { { 0, 0, 0, 0, 0 } },
116 { { 0, 0, 0, 0, 0 } } } };
117 static const struct IP_BASE THM_BASE ={ { { { 0x00016600, 0, 0, 0, 0 } },
118 { { 0, 0, 0, 0, 0 } },
119 { { 0, 0, 0, 0, 0 } },
120 { { 0, 0, 0, 0, 0 } },
121 { { 0, 0, 0, 0, 0 } },
122 { { 0, 0, 0, 0, 0 } } } };
123 static const struct IP_BASE UMC0_BASE ={ { { { 0x00014000, 0, 0, 0, 0 } },
124 { { 0, 0, 0, 0, 0 } },
125 { { 0, 0, 0, 0, 0 } },
126 { { 0, 0, 0, 0, 0 } },
127 { { 0, 0, 0, 0, 0 } },
128 { { 0, 0, 0, 0, 0 } } } };
129 static const struct IP_BASE UVD0_BASE ={ { { { 0x00007800, 0x00007E00, 0, 0, 0 } },
130 { { 0, 0, 0, 0, 0 } },
131 { { 0, 0, 0, 0, 0 } },
132 { { 0, 0, 0, 0, 0 } },
133 { { 0, 0, 0, 0, 0 } },
134 { { 0, 0, 0, 0, 0 } } } };
137 #define ATHUB_BASE__INST0_SEG0 0x00000C00
138 #define ATHUB_BASE__INST0_SEG1 0
139 #define ATHUB_BASE__INST0_SEG2 0
140 #define ATHUB_BASE__INST0_SEG3 0
141 #define ATHUB_BASE__INST0_SEG4 0
143 #define ATHUB_BASE__INST1_SEG0 0
144 #define ATHUB_BASE__INST1_SEG1 0
145 #define ATHUB_BASE__INST1_SEG2 0
146 #define ATHUB_BASE__INST1_SEG3 0
147 #define ATHUB_BASE__INST1_SEG4 0
149 #define ATHUB_BASE__INST2_SEG0 0
150 #define ATHUB_BASE__INST2_SEG1 0
151 #define ATHUB_BASE__INST2_SEG2 0
152 #define ATHUB_BASE__INST2_SEG3 0
153 #define ATHUB_BASE__INST2_SEG4 0
155 #define ATHUB_BASE__INST3_SEG0 0
156 #define ATHUB_BASE__INST3_SEG1 0
157 #define ATHUB_BASE__INST3_SEG2 0
158 #define ATHUB_BASE__INST3_SEG3 0
159 #define ATHUB_BASE__INST3_SEG4 0
161 #define ATHUB_BASE__INST4_SEG0 0
162 #define ATHUB_BASE__INST4_SEG1 0
163 #define ATHUB_BASE__INST4_SEG2 0
164 #define ATHUB_BASE__INST4_SEG3 0
165 #define ATHUB_BASE__INST4_SEG4 0
167 #define ATHUB_BASE__INST5_SEG0 0
168 #define ATHUB_BASE__INST5_SEG1 0
169 #define ATHUB_BASE__INST5_SEG2 0
170 #define ATHUB_BASE__INST5_SEG3 0
171 #define ATHUB_BASE__INST5_SEG4 0
173 #define CLK_BASE__INST0_SEG0 0x00016C00
174 #define CLK_BASE__INST0_SEG1 0
175 #define CLK_BASE__INST0_SEG2 0
176 #define CLK_BASE__INST0_SEG3 0
177 #define CLK_BASE__INST0_SEG4 0
179 #define CLK_BASE__INST1_SEG0 0x00016E00
180 #define CLK_BASE__INST1_SEG1 0
181 #define CLK_BASE__INST1_SEG2 0
182 #define CLK_BASE__INST1_SEG3 0
183 #define CLK_BASE__INST1_SEG4 0
185 #define CLK_BASE__INST2_SEG0 0x00017000
186 #define CLK_BASE__INST2_SEG1 0
187 #define CLK_BASE__INST2_SEG2 0
188 #define CLK_BASE__INST2_SEG3 0
189 #define CLK_BASE__INST2_SEG4 0
191 #define CLK_BASE__INST3_SEG0 0x00017200
192 #define CLK_BASE__INST3_SEG1 0
193 #define CLK_BASE__INST3_SEG2 0
194 #define CLK_BASE__INST3_SEG3 0
195 #define CLK_BASE__INST3_SEG4 0
197 #define CLK_BASE__INST4_SEG0 0x00017E00
198 #define CLK_BASE__INST4_SEG1 0
199 #define CLK_BASE__INST4_SEG2 0
200 #define CLK_BASE__INST4_SEG3 0
201 #define CLK_BASE__INST4_SEG4 0
203 #define CLK_BASE__INST5_SEG0 0x0001B000
204 #define CLK_BASE__INST5_SEG1 0
205 #define CLK_BASE__INST5_SEG2 0
206 #define CLK_BASE__INST5_SEG3 0
207 #define CLK_BASE__INST5_SEG4 0
209 #define DF_BASE__INST0_SEG0 0x00007000
210 #define DF_BASE__INST0_SEG1 0
211 #define DF_BASE__INST0_SEG2 0
212 #define DF_BASE__INST0_SEG3 0
213 #define DF_BASE__INST0_SEG4 0
215 #define DF_BASE__INST1_SEG0 0
216 #define DF_BASE__INST1_SEG1 0
217 #define DF_BASE__INST1_SEG2 0
218 #define DF_BASE__INST1_SEG3 0
219 #define DF_BASE__INST1_SEG4 0
221 #define DF_BASE__INST2_SEG0 0
222 #define DF_BASE__INST2_SEG1 0
223 #define DF_BASE__INST2_SEG2 0
224 #define DF_BASE__INST2_SEG3 0
225 #define DF_BASE__INST2_SEG4 0
227 #define DF_BASE__INST3_SEG0 0
228 #define DF_BASE__INST3_SEG1 0
229 #define DF_BASE__INST3_SEG2 0
230 #define DF_BASE__INST3_SEG3 0
231 #define DF_BASE__INST3_SEG4 0
233 #define DF_BASE__INST4_SEG0 0
234 #define DF_BASE__INST4_SEG1 0
235 #define DF_BASE__INST4_SEG2 0
236 #define DF_BASE__INST4_SEG3 0
237 #define DF_BASE__INST4_SEG4 0
239 #define DF_BASE__INST5_SEG0 0
240 #define DF_BASE__INST5_SEG1 0
241 #define DF_BASE__INST5_SEG2 0
242 #define DF_BASE__INST5_SEG3 0
243 #define DF_BASE__INST5_SEG4 0
245 #define DMU_BASE__INST0_SEG0 0x00000012
246 #define DMU_BASE__INST0_SEG1 0x000000C0
247 #define DMU_BASE__INST0_SEG2 0x000034C0
248 #define DMU_BASE__INST0_SEG3 0x00009000
249 #define DMU_BASE__INST0_SEG4 0
251 #define DMU_BASE__INST1_SEG0 0
252 #define DMU_BASE__INST1_SEG1 0
253 #define DMU_BASE__INST1_SEG2 0
254 #define DMU_BASE__INST1_SEG3 0
255 #define DMU_BASE__INST1_SEG4 0
257 #define DMU_BASE__INST2_SEG0 0
258 #define DMU_BASE__INST2_SEG1 0
259 #define DMU_BASE__INST2_SEG2 0
260 #define DMU_BASE__INST2_SEG3 0
261 #define DMU_BASE__INST2_SEG4 0
263 #define DMU_BASE__INST3_SEG0 0
264 #define DMU_BASE__INST3_SEG1 0
265 #define DMU_BASE__INST3_SEG2 0
266 #define DMU_BASE__INST3_SEG3 0
267 #define DMU_BASE__INST3_SEG4 0
269 #define DMU_BASE__INST4_SEG0 0
270 #define DMU_BASE__INST4_SEG1 0
271 #define DMU_BASE__INST4_SEG2 0
272 #define DMU_BASE__INST4_SEG3 0
273 #define DMU_BASE__INST4_SEG4 0
275 #define DMU_BASE__INST5_SEG0 0
276 #define DMU_BASE__INST5_SEG1 0
277 #define DMU_BASE__INST5_SEG2 0
278 #define DMU_BASE__INST5_SEG3 0
279 #define DMU_BASE__INST5_SEG4 0
281 #define FUSE_BASE__INST0_SEG0 0x00017400
282 #define FUSE_BASE__INST0_SEG1 0
283 #define FUSE_BASE__INST0_SEG2 0
284 #define FUSE_BASE__INST0_SEG3 0
285 #define FUSE_BASE__INST0_SEG4 0
287 #define FUSE_BASE__INST1_SEG0 0
288 #define FUSE_BASE__INST1_SEG1 0
289 #define FUSE_BASE__INST1_SEG2 0
290 #define FUSE_BASE__INST1_SEG3 0
291 #define FUSE_BASE__INST1_SEG4 0
293 #define FUSE_BASE__INST2_SEG0 0
294 #define FUSE_BASE__INST2_SEG1 0
295 #define FUSE_BASE__INST2_SEG2 0
296 #define FUSE_BASE__INST2_SEG3 0
297 #define FUSE_BASE__INST2_SEG4 0
299 #define FUSE_BASE__INST3_SEG0 0
300 #define FUSE_BASE__INST3_SEG1 0
301 #define FUSE_BASE__INST3_SEG2 0
302 #define FUSE_BASE__INST3_SEG3 0
303 #define FUSE_BASE__INST3_SEG4 0
305 #define FUSE_BASE__INST4_SEG0 0
306 #define FUSE_BASE__INST4_SEG1 0
307 #define FUSE_BASE__INST4_SEG2 0
308 #define FUSE_BASE__INST4_SEG3 0
309 #define FUSE_BASE__INST4_SEG4 0
311 #define FUSE_BASE__INST5_SEG0 0
312 #define FUSE_BASE__INST5_SEG1 0
313 #define FUSE_BASE__INST5_SEG2 0
314 #define FUSE_BASE__INST5_SEG3 0
315 #define FUSE_BASE__INST5_SEG4 0
317 #define GC_BASE__INST0_SEG0 0x00001260
318 #define GC_BASE__INST0_SEG1 0x0000A000
319 #define GC_BASE__INST0_SEG2 0
320 #define GC_BASE__INST0_SEG3 0
321 #define GC_BASE__INST0_SEG4 0
323 #define GC_BASE__INST1_SEG0 0
324 #define GC_BASE__INST1_SEG1 0
325 #define GC_BASE__INST1_SEG2 0
326 #define GC_BASE__INST1_SEG3 0
327 #define GC_BASE__INST1_SEG4 0
329 #define GC_BASE__INST2_SEG0 0
330 #define GC_BASE__INST2_SEG1 0
331 #define GC_BASE__INST2_SEG2 0
332 #define GC_BASE__INST2_SEG3 0
333 #define GC_BASE__INST2_SEG4 0
335 #define GC_BASE__INST3_SEG0 0
336 #define GC_BASE__INST3_SEG1 0
337 #define GC_BASE__INST3_SEG2 0
338 #define GC_BASE__INST3_SEG3 0
339 #define GC_BASE__INST3_SEG4 0
341 #define GC_BASE__INST4_SEG0 0
342 #define GC_BASE__INST4_SEG1 0
343 #define GC_BASE__INST4_SEG2 0
344 #define GC_BASE__INST4_SEG3 0
345 #define GC_BASE__INST4_SEG4 0
347 #define GC_BASE__INST5_SEG0 0
348 #define GC_BASE__INST5_SEG1 0
349 #define GC_BASE__INST5_SEG2 0
350 #define GC_BASE__INST5_SEG3 0
351 #define GC_BASE__INST5_SEG4 0
353 #define HDP_BASE__INST0_SEG0 0x00000F20
354 #define HDP_BASE__INST0_SEG1 0
355 #define HDP_BASE__INST0_SEG2 0
356 #define HDP_BASE__INST0_SEG3 0
357 #define HDP_BASE__INST0_SEG4 0
359 #define HDP_BASE__INST1_SEG0 0
360 #define HDP_BASE__INST1_SEG1 0
361 #define HDP_BASE__INST1_SEG2 0
362 #define HDP_BASE__INST1_SEG3 0
363 #define HDP_BASE__INST1_SEG4 0
365 #define HDP_BASE__INST2_SEG0 0
366 #define HDP_BASE__INST2_SEG1 0
367 #define HDP_BASE__INST2_SEG2 0
368 #define HDP_BASE__INST2_SEG3 0
369 #define HDP_BASE__INST2_SEG4 0
371 #define HDP_BASE__INST3_SEG0 0
372 #define HDP_BASE__INST3_SEG1 0
373 #define HDP_BASE__INST3_SEG2 0
374 #define HDP_BASE__INST3_SEG3 0
375 #define HDP_BASE__INST3_SEG4 0
377 #define HDP_BASE__INST4_SEG0 0
378 #define HDP_BASE__INST4_SEG1 0
379 #define HDP_BASE__INST4_SEG2 0
380 #define HDP_BASE__INST4_SEG3 0
381 #define HDP_BASE__INST4_SEG4 0
383 #define HDP_BASE__INST5_SEG0 0
384 #define HDP_BASE__INST5_SEG1 0
385 #define HDP_BASE__INST5_SEG2 0
386 #define HDP_BASE__INST5_SEG3 0
387 #define HDP_BASE__INST5_SEG4 0
389 #define MMHUB_BASE__INST0_SEG0 0x0001A000
390 #define MMHUB_BASE__INST0_SEG1 0
391 #define MMHUB_BASE__INST0_SEG2 0
392 #define MMHUB_BASE__INST0_SEG3 0
393 #define MMHUB_BASE__INST0_SEG4 0
395 #define MMHUB_BASE__INST1_SEG0 0
396 #define MMHUB_BASE__INST1_SEG1 0
397 #define MMHUB_BASE__INST1_SEG2 0
398 #define MMHUB_BASE__INST1_SEG3 0
399 #define MMHUB_BASE__INST1_SEG4 0
401 #define MMHUB_BASE__INST2_SEG0 0
402 #define MMHUB_BASE__INST2_SEG1 0
403 #define MMHUB_BASE__INST2_SEG2 0
404 #define MMHUB_BASE__INST2_SEG3 0
405 #define MMHUB_BASE__INST2_SEG4 0
407 #define MMHUB_BASE__INST3_SEG0 0
408 #define MMHUB_BASE__INST3_SEG1 0
409 #define MMHUB_BASE__INST3_SEG2 0
410 #define MMHUB_BASE__INST3_SEG3 0
411 #define MMHUB_BASE__INST3_SEG4 0
413 #define MMHUB_BASE__INST4_SEG0 0
414 #define MMHUB_BASE__INST4_SEG1 0
415 #define MMHUB_BASE__INST4_SEG2 0
416 #define MMHUB_BASE__INST4_SEG3 0
417 #define MMHUB_BASE__INST4_SEG4 0
419 #define MMHUB_BASE__INST5_SEG0 0
420 #define MMHUB_BASE__INST5_SEG1 0
421 #define MMHUB_BASE__INST5_SEG2 0
422 #define MMHUB_BASE__INST5_SEG3 0
423 #define MMHUB_BASE__INST5_SEG4 0
425 #define MP0_BASE__INST0_SEG0 0x00016000
426 #define MP0_BASE__INST0_SEG1 0
427 #define MP0_BASE__INST0_SEG2 0
428 #define MP0_BASE__INST0_SEG3 0
429 #define MP0_BASE__INST0_SEG4 0
431 #define MP0_BASE__INST1_SEG0 0
432 #define MP0_BASE__INST1_SEG1 0
433 #define MP0_BASE__INST1_SEG2 0
434 #define MP0_BASE__INST1_SEG3 0
435 #define MP0_BASE__INST1_SEG4 0
437 #define MP0_BASE__INST2_SEG0 0
438 #define MP0_BASE__INST2_SEG1 0
439 #define MP0_BASE__INST2_SEG2 0
440 #define MP0_BASE__INST2_SEG3 0
441 #define MP0_BASE__INST2_SEG4 0
443 #define MP0_BASE__INST3_SEG0 0
444 #define MP0_BASE__INST3_SEG1 0
445 #define MP0_BASE__INST3_SEG2 0
446 #define MP0_BASE__INST3_SEG3 0
447 #define MP0_BASE__INST3_SEG4 0
449 #define MP0_BASE__INST4_SEG0 0
450 #define MP0_BASE__INST4_SEG1 0
451 #define MP0_BASE__INST4_SEG2 0
452 #define MP0_BASE__INST4_SEG3 0
453 #define MP0_BASE__INST4_SEG4 0
455 #define MP0_BASE__INST5_SEG0 0
456 #define MP0_BASE__INST5_SEG1 0
457 #define MP0_BASE__INST5_SEG2 0
458 #define MP0_BASE__INST5_SEG3 0
459 #define MP0_BASE__INST5_SEG4 0
461 #define MP1_BASE__INST0_SEG0 0x00016000
462 #define MP1_BASE__INST0_SEG1 0
463 #define MP1_BASE__INST0_SEG2 0
464 #define MP1_BASE__INST0_SEG3 0
465 #define MP1_BASE__INST0_SEG4 0
467 #define MP1_BASE__INST1_SEG0 0
468 #define MP1_BASE__INST1_SEG1 0
469 #define MP1_BASE__INST1_SEG2 0
470 #define MP1_BASE__INST1_SEG3 0
471 #define MP1_BASE__INST1_SEG4 0
473 #define MP1_BASE__INST2_SEG0 0
474 #define MP1_BASE__INST2_SEG1 0
475 #define MP1_BASE__INST2_SEG2 0
476 #define MP1_BASE__INST2_SEG3 0
477 #define MP1_BASE__INST2_SEG4 0
479 #define MP1_BASE__INST3_SEG0 0
480 #define MP1_BASE__INST3_SEG1 0
481 #define MP1_BASE__INST3_SEG2 0
482 #define MP1_BASE__INST3_SEG3 0
483 #define MP1_BASE__INST3_SEG4 0
485 #define MP1_BASE__INST4_SEG0 0
486 #define MP1_BASE__INST4_SEG1 0
487 #define MP1_BASE__INST4_SEG2 0
488 #define MP1_BASE__INST4_SEG3 0
489 #define MP1_BASE__INST4_SEG4 0
491 #define MP1_BASE__INST5_SEG0 0
492 #define MP1_BASE__INST5_SEG1 0
493 #define MP1_BASE__INST5_SEG2 0
494 #define MP1_BASE__INST5_SEG3 0
495 #define MP1_BASE__INST5_SEG4 0
497 #define NBIO_BASE__INST0_SEG0 0x00000000
498 #define NBIO_BASE__INST0_SEG1 0x00000014
499 #define NBIO_BASE__INST0_SEG2 0x00000D20
500 #define NBIO_BASE__INST0_SEG3 0x00010400
501 #define NBIO_BASE__INST0_SEG4 0
503 #define NBIO_BASE__INST1_SEG0 0
504 #define NBIO_BASE__INST1_SEG1 0
505 #define NBIO_BASE__INST1_SEG2 0
506 #define NBIO_BASE__INST1_SEG3 0
507 #define NBIO_BASE__INST1_SEG4 0
509 #define NBIO_BASE__INST2_SEG0 0
510 #define NBIO_BASE__INST2_SEG1 0
511 #define NBIO_BASE__INST2_SEG2 0
512 #define NBIO_BASE__INST2_SEG3 0
513 #define NBIO_BASE__INST2_SEG4 0
515 #define NBIO_BASE__INST3_SEG0 0
516 #define NBIO_BASE__INST3_SEG1 0
517 #define NBIO_BASE__INST3_SEG2 0
518 #define NBIO_BASE__INST3_SEG3 0
519 #define NBIO_BASE__INST3_SEG4 0
521 #define NBIO_BASE__INST4_SEG0 0
522 #define NBIO_BASE__INST4_SEG1 0
523 #define NBIO_BASE__INST4_SEG2 0
524 #define NBIO_BASE__INST4_SEG3 0
525 #define NBIO_BASE__INST4_SEG4 0
527 #define NBIO_BASE__INST5_SEG0 0
528 #define NBIO_BASE__INST5_SEG1 0
529 #define NBIO_BASE__INST5_SEG2 0
530 #define NBIO_BASE__INST5_SEG3 0
531 #define NBIO_BASE__INST5_SEG4 0
533 #define OSSSYS_BASE__INST0_SEG0 0x000010A0
534 #define OSSSYS_BASE__INST0_SEG1 0
535 #define OSSSYS_BASE__INST0_SEG2 0
536 #define OSSSYS_BASE__INST0_SEG3 0
537 #define OSSSYS_BASE__INST0_SEG4 0
539 #define OSSSYS_BASE__INST1_SEG0 0
540 #define OSSSYS_BASE__INST1_SEG1 0
541 #define OSSSYS_BASE__INST1_SEG2 0
542 #define OSSSYS_BASE__INST1_SEG3 0
543 #define OSSSYS_BASE__INST1_SEG4 0
545 #define OSSSYS_BASE__INST2_SEG0 0
546 #define OSSSYS_BASE__INST2_SEG1 0
547 #define OSSSYS_BASE__INST2_SEG2 0
548 #define OSSSYS_BASE__INST2_SEG3 0
549 #define OSSSYS_BASE__INST2_SEG4 0
551 #define OSSSYS_BASE__INST3_SEG0 0
552 #define OSSSYS_BASE__INST3_SEG1 0
553 #define OSSSYS_BASE__INST3_SEG2 0
554 #define OSSSYS_BASE__INST3_SEG3 0
555 #define OSSSYS_BASE__INST3_SEG4 0
557 #define OSSSYS_BASE__INST4_SEG0 0
558 #define OSSSYS_BASE__INST4_SEG1 0
559 #define OSSSYS_BASE__INST4_SEG2 0
560 #define OSSSYS_BASE__INST4_SEG3 0
561 #define OSSSYS_BASE__INST4_SEG4 0
563 #define OSSSYS_BASE__INST5_SEG0 0
564 #define OSSSYS_BASE__INST5_SEG1 0
565 #define OSSSYS_BASE__INST5_SEG2 0
566 #define OSSSYS_BASE__INST5_SEG3 0
567 #define OSSSYS_BASE__INST5_SEG4 0
569 #define SMUIO_BASE__INST0_SEG0 0x00016800
570 #define SMUIO_BASE__INST0_SEG1 0x00016A00
571 #define SMUIO_BASE__INST0_SEG2 0
572 #define SMUIO_BASE__INST0_SEG3 0
573 #define SMUIO_BASE__INST0_SEG4 0
575 #define SMUIO_BASE__INST1_SEG0 0
576 #define SMUIO_BASE__INST1_SEG1 0
577 #define SMUIO_BASE__INST1_SEG2 0
578 #define SMUIO_BASE__INST1_SEG3 0
579 #define SMUIO_BASE__INST1_SEG4 0
581 #define SMUIO_BASE__INST2_SEG0 0
582 #define SMUIO_BASE__INST2_SEG1 0
583 #define SMUIO_BASE__INST2_SEG2 0
584 #define SMUIO_BASE__INST2_SEG3 0
585 #define SMUIO_BASE__INST2_SEG4 0
587 #define SMUIO_BASE__INST3_SEG0 0
588 #define SMUIO_BASE__INST3_SEG1 0
589 #define SMUIO_BASE__INST3_SEG2 0
590 #define SMUIO_BASE__INST3_SEG3 0
591 #define SMUIO_BASE__INST3_SEG4 0
593 #define SMUIO_BASE__INST4_SEG0 0
594 #define SMUIO_BASE__INST4_SEG1 0
595 #define SMUIO_BASE__INST4_SEG2 0
596 #define SMUIO_BASE__INST4_SEG3 0
597 #define SMUIO_BASE__INST4_SEG4 0
599 #define SMUIO_BASE__INST5_SEG0 0
600 #define SMUIO_BASE__INST5_SEG1 0
601 #define SMUIO_BASE__INST5_SEG2 0
602 #define SMUIO_BASE__INST5_SEG3 0
603 #define SMUIO_BASE__INST5_SEG4 0
605 #define THM_BASE__INST0_SEG0 0x00016600
606 #define THM_BASE__INST0_SEG1 0
607 #define THM_BASE__INST0_SEG2 0
608 #define THM_BASE__INST0_SEG3 0
609 #define THM_BASE__INST0_SEG4 0
611 #define THM_BASE__INST1_SEG0 0
612 #define THM_BASE__INST1_SEG1 0
613 #define THM_BASE__INST1_SEG2 0
614 #define THM_BASE__INST1_SEG3 0
615 #define THM_BASE__INST1_SEG4 0
617 #define THM_BASE__INST2_SEG0 0
618 #define THM_BASE__INST2_SEG1 0
619 #define THM_BASE__INST2_SEG2 0
620 #define THM_BASE__INST2_SEG3 0
621 #define THM_BASE__INST2_SEG4 0
623 #define THM_BASE__INST3_SEG0 0
624 #define THM_BASE__INST3_SEG1 0
625 #define THM_BASE__INST3_SEG2 0
626 #define THM_BASE__INST3_SEG3 0
627 #define THM_BASE__INST3_SEG4 0
629 #define THM_BASE__INST4_SEG0 0
630 #define THM_BASE__INST4_SEG1 0
631 #define THM_BASE__INST4_SEG2 0
632 #define THM_BASE__INST4_SEG3 0
633 #define THM_BASE__INST4_SEG4 0
635 #define THM_BASE__INST5_SEG0 0
636 #define THM_BASE__INST5_SEG1 0
637 #define THM_BASE__INST5_SEG2 0
638 #define THM_BASE__INST5_SEG3 0
639 #define THM_BASE__INST5_SEG4 0
641 #define UMC0_BASE__INST0_SEG0 0x00014000
642 #define UMC0_BASE__INST0_SEG1 0
643 #define UMC0_BASE__INST0_SEG2 0
644 #define UMC0_BASE__INST0_SEG3 0
645 #define UMC0_BASE__INST0_SEG4 0
647 #define UMC0_BASE__INST1_SEG0 0
648 #define UMC0_BASE__INST1_SEG1 0
649 #define UMC0_BASE__INST1_SEG2 0
650 #define UMC0_BASE__INST1_SEG3 0
651 #define UMC0_BASE__INST1_SEG4 0
653 #define UMC0_BASE__INST2_SEG0 0
654 #define UMC0_BASE__INST2_SEG1 0
655 #define UMC0_BASE__INST2_SEG2 0
656 #define UMC0_BASE__INST2_SEG3 0
657 #define UMC0_BASE__INST2_SEG4 0
659 #define UMC0_BASE__INST3_SEG0 0
660 #define UMC0_BASE__INST3_SEG1 0
661 #define UMC0_BASE__INST3_SEG2 0
662 #define UMC0_BASE__INST3_SEG3 0
663 #define UMC0_BASE__INST3_SEG4 0
665 #define UMC0_BASE__INST4_SEG0 0
666 #define UMC0_BASE__INST4_SEG1 0
667 #define UMC0_BASE__INST4_SEG2 0
668 #define UMC0_BASE__INST4_SEG3 0
669 #define UMC0_BASE__INST4_SEG4 0
671 #define UMC0_BASE__INST5_SEG0 0
672 #define UMC0_BASE__INST5_SEG1 0
673 #define UMC0_BASE__INST5_SEG2 0
674 #define UMC0_BASE__INST5_SEG3 0
675 #define UMC0_BASE__INST5_SEG4 0
677 #define UVD0_BASE__INST0_SEG0 0x00007800
678 #define UVD0_BASE__INST0_SEG1 0x00007E00
679 #define UVD0_BASE__INST0_SEG2 0
680 #define UVD0_BASE__INST0_SEG3 0
681 #define UVD0_BASE__INST0_SEG4 0
683 #define UVD0_BASE__INST1_SEG0 0
684 #define UVD0_BASE__INST1_SEG1 0
685 #define UVD0_BASE__INST1_SEG2 0
686 #define UVD0_BASE__INST1_SEG3 0
687 #define UVD0_BASE__INST1_SEG4 0
689 #define UVD0_BASE__INST2_SEG0 0
690 #define UVD0_BASE__INST2_SEG1 0
691 #define UVD0_BASE__INST2_SEG2 0
692 #define UVD0_BASE__INST2_SEG3 0
693 #define UVD0_BASE__INST2_SEG4 0
695 #define UVD0_BASE__INST3_SEG0 0
696 #define UVD0_BASE__INST3_SEG1 0
697 #define UVD0_BASE__INST3_SEG2 0
698 #define UVD0_BASE__INST3_SEG3 0
699 #define UVD0_BASE__INST3_SEG4 0
701 #define UVD0_BASE__INST4_SEG0 0
702 #define UVD0_BASE__INST4_SEG1 0
703 #define UVD0_BASE__INST4_SEG2 0
704 #define UVD0_BASE__INST4_SEG3 0
705 #define UVD0_BASE__INST4_SEG4 0
707 #define UVD0_BASE__INST5_SEG0 0
708 #define UVD0_BASE__INST5_SEG1 0
709 #define UVD0_BASE__INST5_SEG2 0
710 #define UVD0_BASE__INST5_SEG3 0
711 #define UVD0_BASE__INST5_SEG4 0