drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

   1 /*
   2  * Copyright 2020 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include <linux/firmware.h>
  24 #include <linux/module.h>
  25 #include <linux/pci.h>
  26 #include <linux/reboot.h>
  27
  28 #define SMU_13_0_PARTIAL_PPTABLE
  29 #define SWSMU_CODE_LAYER_L3
  30
  31 #include "amdgpu.h"
  32 #include "amdgpu_smu.h"
  33 #include "atomfirmware.h"
  34 #include "amdgpu_atomfirmware.h"
  35 #include "amdgpu_atombios.h"
  36 #include "smu_v13_0.h"
  37 #include "soc15_common.h"
  38 #include "atom.h"
  39 #include "amdgpu_ras.h"
  40 #include "smu_cmn.h"
  41
  42 #include "asic_reg/thm/thm_13_0_2_offset.h"
  43 #include "asic_reg/thm/thm_13_0_2_sh_mask.h"
  44 #include "asic_reg/mp/mp_13_0_2_offset.h"
  45 #include "asic_reg/mp/mp_13_0_2_sh_mask.h"
  46 #include "asic_reg/smuio/smuio_13_0_2_offset.h"
  47 #include "asic_reg/smuio/smuio_13_0_2_sh_mask.h"
  48
  49 /*
  50  * DO NOT use these for err/warn/info/debug messages.
  51  * Use dev_err, dev_warn, dev_info and dev_dbg instead.
  52  * They are more MGPU friendly.
  53  */
  54 #undef pr_err
  55 #undef pr_warn
  56 #undef pr_info
  57 #undef pr_debug
  58
  59 MODULE_FIRMWARE("amdgpu/aldebaran_smc.bin");
  60 MODULE_FIRMWARE("amdgpu/smu_13_0_0.bin");
  61 MODULE_FIRMWARE("amdgpu/smu_13_0_7.bin");
  62 MODULE_FIRMWARE("amdgpu/smu_13_0_10.bin");
  63
  64 #define mmMP1_SMN_C2PMSG_66                                                                            0x0282
  65 #define mmMP1_SMN_C2PMSG_66_BASE_IDX                                                                   0
  66
  67 #define mmMP1_SMN_C2PMSG_82                                                                            0x0292
  68 #define mmMP1_SMN_C2PMSG_82_BASE_IDX                                                                   0
  69
  70 #define mmMP1_SMN_C2PMSG_90                                                                            0x029a
  71 #define mmMP1_SMN_C2PMSG_90_BASE_IDX                                                                   0
  72
  73 #define SMU13_VOLTAGE_SCALE 4
  74
  75 #define LINK_WIDTH_MAX                          6
  76 #define LINK_SPEED_MAX                          3
  77
  78 #define smnPCIE_LC_LINK_WIDTH_CNTL              0x11140288
  79 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L
  80 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
  81 #define smnPCIE_LC_SPEED_CNTL                   0x11140290
  82 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0xC000
  83 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xE
  84
  85 static const int link_width[] = {0, 1, 2, 4, 8, 12, 16};
  86
  87 const int pmfw_decoded_link_speed[5] = {1, 2, 3, 4, 5};
  88 const int pmfw_decoded_link_width[7] = {0, 1, 2, 4, 8, 12, 16};
  89
  90 int smu_v13_0_init_microcode(struct smu_context *smu)
  91 {
  92         struct amdgpu_device *adev = smu->adev;
  93         char fw_name[30];
  94         char ucode_prefix[30];
  95         int err = 0;
  96         const struct smc_firmware_header_v1_0 *hdr;
  97         const struct common_firmware_header *header;
  98         struct amdgpu_firmware_info *ucode = NULL;
  99
 100         /* doesn't need to load smu firmware in IOV mode */
 101         if (amdgpu_sriov_vf(adev))
 102                 return 0;
 103
 104         amdgpu_ucode_ip_version_decode(adev, MP1_HWIP, ucode_prefix, sizeof(ucode_prefix));
 105
 106         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s.bin", ucode_prefix);
 107
 108         err = amdgpu_ucode_request(adev, &adev->pm.fw, fw_name);
 109         if (err)
 110                 goto out;
 111
 112         hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 113         amdgpu_ucode_print_smc_hdr(&hdr->header);
 114         adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
 115
 116         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 117                 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
 118                 ucode->ucode_id = AMDGPU_UCODE_ID_SMC;
 119                 ucode->fw = adev->pm.fw;
 120                 header = (const struct common_firmware_header *)ucode->fw->data;
 121                 adev->firmware.fw_size +=
 122                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 123         }
 124
 125 out:
 126         if (err)
 127                 amdgpu_ucode_release(&adev->pm.fw);
 128         return err;
 129 }
 130
 131 void smu_v13_0_fini_microcode(struct smu_context *smu)
 132 {
 133         struct amdgpu_device *adev = smu->adev;
 134
 135         amdgpu_ucode_release(&adev->pm.fw);
 136         adev->pm.fw_version = 0;
 137 }
 138
 139 int smu_v13_0_load_microcode(struct smu_context *smu)
 140 {
 141 #if 0
 142         struct amdgpu_device *adev = smu->adev;
 143         const uint32_t *src;
 144         const struct smc_firmware_header_v1_0 *hdr;
 145         uint32_t addr_start = MP1_SRAM;
 146         uint32_t i;
 147         uint32_t smc_fw_size;
 148         uint32_t mp1_fw_flags;
 149
 150         hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 151         src = (const uint32_t *)(adev->pm.fw->data +
 152                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 153         smc_fw_size = hdr->header.ucode_size_bytes;
 154
 155         for (i = 1; i < smc_fw_size/4 - 1; i++) {
 156                 WREG32_PCIE(addr_start, src[i]);
 157                 addr_start += 4;
 158         }
 159
 160         WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
 161                     1 & MP1_SMN_PUB_CTRL__RESET_MASK);
 162         WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
 163                     1 & ~MP1_SMN_PUB_CTRL__RESET_MASK);
 164
 165         for (i = 0; i < adev->usec_timeout; i++) {
 166                 mp1_fw_flags = RREG32_PCIE(MP1_Public |
 167                                            (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
 168                 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
 169                     MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
 170                         break;
 171                 udelay(1);
 172         }
 173
 174         if (i == adev->usec_timeout)
 175                 return -ETIME;
 176 #endif
 177
 178         return 0;
 179 }
 180
 181 int smu_v13_0_init_pptable_microcode(struct smu_context *smu)
 182 {
 183         struct amdgpu_device *adev = smu->adev;
 184         struct amdgpu_firmware_info *ucode = NULL;
 185         uint32_t size = 0, pptable_id = 0;
 186         int ret = 0;
 187         void *table;
 188
 189         /* doesn't need to load smu firmware in IOV mode */
 190         if (amdgpu_sriov_vf(adev))
 191                 return 0;
 192
 193         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
 194                 return 0;
 195
 196         if (!adev->scpm_enabled)
 197                 return 0;
 198
 199         if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 7)) ||
 200             (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 0)) ||
 201             (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 10)))
 202                 return 0;
 203
 204         /* override pptable_id from driver parameter */
 205         if (amdgpu_smu_pptable_id >= 0) {
 206                 pptable_id = amdgpu_smu_pptable_id;
 207                 dev_info(adev->dev, "override pptable id %d\n", pptable_id);
 208         } else {
 209                 pptable_id = smu->smu_table.boot_values.pp_table_id;
 210         }
 211
 212         /* "pptable_id == 0" means vbios carries the pptable. */
 213         if (!pptable_id)
 214                 return 0;
 215
 216         ret = smu_v13_0_get_pptable_from_firmware(smu, &table, &size, pptable_id);
 217         if (ret)
 218                 return ret;
 219
 220         smu->pptable_firmware.data = table;
 221         smu->pptable_firmware.size = size;
 222
 223         ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_PPTABLE];
 224         ucode->ucode_id = AMDGPU_UCODE_ID_PPTABLE;
 225         ucode->fw = &smu->pptable_firmware;
 226         adev->firmware.fw_size +=
 227                 ALIGN(smu->pptable_firmware.size, PAGE_SIZE);
 228
 229         return 0;
 230 }
 231
 232 int smu_v13_0_check_fw_status(struct smu_context *smu)
 233 {
 234         struct amdgpu_device *adev = smu->adev;
 235         uint32_t mp1_fw_flags;
 236
 237         switch (adev->ip_versions[MP1_HWIP][0]) {
 238         case IP_VERSION(13, 0, 4):
 239         case IP_VERSION(13, 0, 11):
 240                 mp1_fw_flags = RREG32_PCIE(MP1_Public |
 241                                            (smnMP1_V13_0_4_FIRMWARE_FLAGS & 0xffffffff));
 242                 break;
 243         default:
 244                 mp1_fw_flags = RREG32_PCIE(MP1_Public |
 245                                            (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
 246                 break;
 247         }
 248
 249         if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
 250             MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
 251                 return 0;
 252
 253         return -EIO;
 254 }
 255
 256 int smu_v13_0_check_fw_version(struct smu_context *smu)
 257 {
 258         struct amdgpu_device *adev = smu->adev;
 259         uint32_t if_version = 0xff, smu_version = 0xff;
 260         uint8_t smu_program, smu_major, smu_minor, smu_debug;
 261         int ret = 0;
 262
 263         ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version);
 264         if (ret)
 265                 return ret;
 266
 267         smu_program = (smu_version >> 24) & 0xff;
 268         smu_major = (smu_version >> 16) & 0xff;
 269         smu_minor = (smu_version >> 8) & 0xff;
 270         smu_debug = (smu_version >> 0) & 0xff;
 271         if (smu->is_apu ||
 272             adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 6))
 273                 adev->pm.fw_version = smu_version;
 274
 275         /* only for dGPU w/ SMU13*/
 276         if (adev->pm.fw)
 277                 dev_dbg(smu->adev->dev, "smu fw reported program %d, version = 0x%08x (%d.%d.%d)\n",
 278                          smu_program, smu_version, smu_major, smu_minor, smu_debug);
 279
 280         /*
 281          * 1. if_version mismatch is not critical as our fw is designed
 282          * to be backward compatible.
 283          * 2. New fw usually brings some optimizations. But that's visible
 284          * only on the paired driver.
 285          * Considering above, we just leave user a verbal message instead
 286          * of halt driver loading.
 287          */
 288         if (if_version != smu->smc_driver_if_version) {
 289                 dev_info(adev->dev, "smu driver if version = 0x%08x, smu fw if version = 0x%08x, "
 290                          "smu fw program = %d, smu fw version = 0x%08x (%d.%d.%d)\n",
 291                          smu->smc_driver_if_version, if_version,
 292                          smu_program, smu_version, smu_major, smu_minor, smu_debug);
 293                 dev_info(adev->dev, "SMU driver if version not matched\n");
 294         }
 295
 296         return ret;
 297 }
 298
 299 static int smu_v13_0_set_pptable_v2_0(struct smu_context *smu, void **table, uint32_t *size)
 300 {
 301         struct amdgpu_device *adev = smu->adev;
 302         uint32_t ppt_offset_bytes;
 303         const struct smc_firmware_header_v2_0 *v2;
 304
 305         v2 = (const struct smc_firmware_header_v2_0 *) adev->pm.fw->data;
 306
 307         ppt_offset_bytes = le32_to_cpu(v2->ppt_offset_bytes);
 308         *size = le32_to_cpu(v2->ppt_size_bytes);
 309         *table = (uint8_t *)v2 + ppt_offset_bytes;
 310
 311         return 0;
 312 }
 313
 314 static int smu_v13_0_set_pptable_v2_1(struct smu_context *smu, void **table,
 315                                       uint32_t *size, uint32_t pptable_id)
 316 {
 317         struct amdgpu_device *adev = smu->adev;
 318         const struct smc_firmware_header_v2_1 *v2_1;
 319         struct smc_soft_pptable_entry *entries;
 320         uint32_t pptable_count = 0;
 321         int i = 0;
 322
 323         v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data;
 324         entries = (struct smc_soft_pptable_entry *)
 325                 ((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset));
 326         pptable_count = le32_to_cpu(v2_1->pptable_count);
 327         for (i = 0; i < pptable_count; i++) {
 328                 if (le32_to_cpu(entries[i].id) == pptable_id) {
 329                         *table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes));
 330                         *size = le32_to_cpu(entries[i].ppt_size_bytes);
 331                         break;
 332                 }
 333         }
 334
 335         if (i == pptable_count)
 336                 return -EINVAL;
 337
 338         return 0;
 339 }
 340
 341 static int smu_v13_0_get_pptable_from_vbios(struct smu_context *smu, void **table, uint32_t *size)
 342 {
 343         struct amdgpu_device *adev = smu->adev;
 344         uint16_t atom_table_size;
 345         uint8_t frev, crev;
 346         int ret, index;
 347
 348         dev_info(adev->dev, "use vbios provided pptable\n");
 349         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 350                                             powerplayinfo);
 351
 352         ret = amdgpu_atombios_get_data_table(adev, index, &atom_table_size, &frev, &crev,
 353                                              (uint8_t **)table);
 354         if (ret)
 355                 return ret;
 356
 357         if (size)
 358                 *size = atom_table_size;
 359
 360         return 0;
 361 }
 362
 363 int smu_v13_0_get_pptable_from_firmware(struct smu_context *smu,
 364                                         void **table,
 365                                         uint32_t *size,
 366                                         uint32_t pptable_id)
 367 {
 368         const struct smc_firmware_header_v1_0 *hdr;
 369         struct amdgpu_device *adev = smu->adev;
 370         uint16_t version_major, version_minor;
 371         int ret;
 372
 373         hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 374         if (!hdr)
 375                 return -EINVAL;
 376
 377         dev_info(adev->dev, "use driver provided pptable %d\n", pptable_id);
 378
 379         version_major = le16_to_cpu(hdr->header.header_version_major);
 380         version_minor = le16_to_cpu(hdr->header.header_version_minor);
 381         if (version_major != 2) {
 382                 dev_err(adev->dev, "Unsupported smu firmware version %d.%d\n",
 383                         version_major, version_minor);
 384                 return -EINVAL;
 385         }
 386
 387         switch (version_minor) {
 388         case 0:
 389                 ret = smu_v13_0_set_pptable_v2_0(smu, table, size);
 390                 break;
 391         case 1:
 392                 ret = smu_v13_0_set_pptable_v2_1(smu, table, size, pptable_id);
 393                 break;
 394         default:
 395                 ret = -EINVAL;
 396                 break;
 397         }
 398
 399         return ret;
 400 }
 401
 402 int smu_v13_0_setup_pptable(struct smu_context *smu)
 403 {
 404         struct amdgpu_device *adev = smu->adev;
 405         uint32_t size = 0, pptable_id = 0;
 406         void *table;
 407         int ret = 0;
 408
 409         /* override pptable_id from driver parameter */
 410         if (amdgpu_smu_pptable_id >= 0) {
 411                 pptable_id = amdgpu_smu_pptable_id;
 412                 dev_info(adev->dev, "override pptable id %d\n", pptable_id);
 413         } else {
 414                 pptable_id = smu->smu_table.boot_values.pp_table_id;
 415         }
 416
 417         /* force using vbios pptable in sriov mode */
 418         if ((amdgpu_sriov_vf(adev) || !pptable_id) && (amdgpu_emu_mode != 1))
 419                 ret = smu_v13_0_get_pptable_from_vbios(smu, &table, &size);
 420         else
 421                 ret = smu_v13_0_get_pptable_from_firmware(smu, &table, &size, pptable_id);
 422
 423         if (ret)
 424                 return ret;
 425
 426         if (!smu->smu_table.power_play_table)
 427                 smu->smu_table.power_play_table = table;
 428         if (!smu->smu_table.power_play_table_size)
 429                 smu->smu_table.power_play_table_size = size;
 430
 431         return 0;
 432 }
 433
 434 int smu_v13_0_init_smc_tables(struct smu_context *smu)
 435 {
 436         struct smu_table_context *smu_table = &smu->smu_table;
 437         struct smu_table *tables = smu_table->tables;
 438         int ret = 0;
 439
 440         smu_table->driver_pptable =
 441                 kzalloc(tables[SMU_TABLE_PPTABLE].size, GFP_KERNEL);
 442         if (!smu_table->driver_pptable) {
 443                 ret = -ENOMEM;
 444                 goto err0_out;
 445         }
 446
 447         smu_table->max_sustainable_clocks =
 448                 kzalloc(sizeof(struct smu_13_0_max_sustainable_clocks), GFP_KERNEL);
 449         if (!smu_table->max_sustainable_clocks) {
 450                 ret = -ENOMEM;
 451                 goto err1_out;
 452         }
 453
 454         /* Aldebaran does not support OVERDRIVE */
 455         if (tables[SMU_TABLE_OVERDRIVE].size) {
 456                 smu_table->overdrive_table =
 457                         kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
 458                 if (!smu_table->overdrive_table) {
 459                         ret = -ENOMEM;
 460                         goto err2_out;
 461                 }
 462
 463                 smu_table->boot_overdrive_table =
 464                         kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
 465                 if (!smu_table->boot_overdrive_table) {
 466                         ret = -ENOMEM;
 467                         goto err3_out;
 468                 }
 469
 470                 smu_table->user_overdrive_table =
 471                         kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
 472                 if (!smu_table->user_overdrive_table) {
 473                         ret = -ENOMEM;
 474                         goto err4_out;
 475                 }
 476         }
 477
 478         smu_table->combo_pptable =
 479                 kzalloc(tables[SMU_TABLE_COMBO_PPTABLE].size, GFP_KERNEL);
 480         if (!smu_table->combo_pptable) {
 481                 ret = -ENOMEM;
 482                 goto err5_out;
 483         }
 484
 485         return 0;
 486
 487 err5_out:
 488         kfree(smu_table->user_overdrive_table);
 489 err4_out:
 490         kfree(smu_table->boot_overdrive_table);
 491 err3_out:
 492         kfree(smu_table->overdrive_table);
 493 err2_out:
 494         kfree(smu_table->max_sustainable_clocks);
 495 err1_out:
 496         kfree(smu_table->driver_pptable);
 497 err0_out:
 498         return ret;
 499 }
 500
 501 int smu_v13_0_fini_smc_tables(struct smu_context *smu)
 502 {
 503         struct smu_table_context *smu_table = &smu->smu_table;
 504         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 505
 506         kfree(smu_table->gpu_metrics_table);
 507         kfree(smu_table->combo_pptable);
 508         kfree(smu_table->user_overdrive_table);
 509         kfree(smu_table->boot_overdrive_table);
 510         kfree(smu_table->overdrive_table);
 511         kfree(smu_table->max_sustainable_clocks);
 512         kfree(smu_table->driver_pptable);
 513         smu_table->gpu_metrics_table = NULL;
 514         smu_table->combo_pptable = NULL;
 515         smu_table->user_overdrive_table = NULL;
 516         smu_table->boot_overdrive_table = NULL;
 517         smu_table->overdrive_table = NULL;
 518         smu_table->max_sustainable_clocks = NULL;
 519         smu_table->driver_pptable = NULL;
 520         kfree(smu_table->hardcode_pptable);
 521         smu_table->hardcode_pptable = NULL;
 522
 523         kfree(smu_table->ecc_table);
 524         kfree(smu_table->metrics_table);
 525         kfree(smu_table->watermarks_table);
 526         smu_table->ecc_table = NULL;
 527         smu_table->metrics_table = NULL;
 528         smu_table->watermarks_table = NULL;
 529         smu_table->metrics_time = 0;
 530
 531         kfree(smu_dpm->dpm_context);
 532         kfree(smu_dpm->golden_dpm_context);
 533         kfree(smu_dpm->dpm_current_power_state);
 534         kfree(smu_dpm->dpm_request_power_state);
 535         smu_dpm->dpm_context = NULL;
 536         smu_dpm->golden_dpm_context = NULL;
 537         smu_dpm->dpm_context_size = 0;
 538         smu_dpm->dpm_current_power_state = NULL;
 539         smu_dpm->dpm_request_power_state = NULL;
 540
 541         return 0;
 542 }
 543
 544 int smu_v13_0_init_power(struct smu_context *smu)
 545 {
 546         struct smu_power_context *smu_power = &smu->smu_power;
 547
 548         if (smu_power->power_context || smu_power->power_context_size != 0)
 549                 return -EINVAL;
 550
 551         smu_power->power_context = kzalloc(sizeof(struct smu_13_0_power_context),
 552                                            GFP_KERNEL);
 553         if (!smu_power->power_context)
 554                 return -ENOMEM;
 555         smu_power->power_context_size = sizeof(struct smu_13_0_power_context);
 556
 557         return 0;
 558 }
 559
 560 int smu_v13_0_fini_power(struct smu_context *smu)
 561 {
 562         struct smu_power_context *smu_power = &smu->smu_power;
 563
 564         if (!smu_power->power_context || smu_power->power_context_size == 0)
 565                 return -EINVAL;
 566
 567         kfree(smu_power->power_context);
 568         smu_power->power_context = NULL;
 569         smu_power->power_context_size = 0;
 570
 571         return 0;
 572 }
 573
 574 int smu_v13_0_get_vbios_bootup_values(struct smu_context *smu)
 575 {
 576         int ret, index;
 577         uint16_t size;
 578         uint8_t frev, crev;
 579         struct atom_common_table_header *header;
 580         struct atom_firmware_info_v3_4 *v_3_4;
 581         struct atom_firmware_info_v3_3 *v_3_3;
 582         struct atom_firmware_info_v3_1 *v_3_1;
 583         struct atom_smu_info_v3_6 *smu_info_v3_6;
 584         struct atom_smu_info_v4_0 *smu_info_v4_0;
 585
 586         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 587                                             firmwareinfo);
 588
 589         ret = amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev,
 590                                              (uint8_t **)&header);
 591         if (ret)
 592                 return ret;
 593
 594         if (header->format_revision != 3) {
 595                 dev_err(smu->adev->dev, "unknown atom_firmware_info version! for smu13\n");
 596                 return -EINVAL;
 597         }
 598
 599         switch (header->content_revision) {
 600         case 0:
 601         case 1:
 602         case 2:
 603                 v_3_1 = (struct atom_firmware_info_v3_1 *)header;
 604                 smu->smu_table.boot_values.revision = v_3_1->firmware_revision;
 605                 smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz;
 606                 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz;
 607                 smu->smu_table.boot_values.socclk = 0;
 608                 smu->smu_table.boot_values.dcefclk = 0;
 609                 smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv;
 610                 smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv;
 611                 smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv;
 612                 smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv;
 613                 smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id;
 614                 smu->smu_table.boot_values.pp_table_id = 0;
 615                 break;
 616         case 3:
 617                 v_3_3 = (struct atom_firmware_info_v3_3 *)header;
 618                 smu->smu_table.boot_values.revision = v_3_3->firmware_revision;
 619                 smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz;
 620                 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz;
 621                 smu->smu_table.boot_values.socclk = 0;
 622                 smu->smu_table.boot_values.dcefclk = 0;
 623                 smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv;
 624                 smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv;
 625                 smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv;
 626                 smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv;
 627                 smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id;
 628                 smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id;
 629                 break;
 630         case 4:
 631         default:
 632                 v_3_4 = (struct atom_firmware_info_v3_4 *)header;
 633                 smu->smu_table.boot_values.revision = v_3_4->firmware_revision;
 634                 smu->smu_table.boot_values.gfxclk = v_3_4->bootup_sclk_in10khz;
 635                 smu->smu_table.boot_values.uclk = v_3_4->bootup_mclk_in10khz;
 636                 smu->smu_table.boot_values.socclk = 0;
 637                 smu->smu_table.boot_values.dcefclk = 0;
 638                 smu->smu_table.boot_values.vddc = v_3_4->bootup_vddc_mv;
 639                 smu->smu_table.boot_values.vddci = v_3_4->bootup_vddci_mv;
 640                 smu->smu_table.boot_values.mvddc = v_3_4->bootup_mvddc_mv;
 641                 smu->smu_table.boot_values.vdd_gfx = v_3_4->bootup_vddgfx_mv;
 642                 smu->smu_table.boot_values.cooling_id = v_3_4->coolingsolution_id;
 643                 smu->smu_table.boot_values.pp_table_id = v_3_4->pplib_pptable_id;
 644                 break;
 645         }
 646
 647         smu->smu_table.boot_values.format_revision = header->format_revision;
 648         smu->smu_table.boot_values.content_revision = header->content_revision;
 649
 650         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 651                                             smu_info);
 652         if (!amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev,
 653                                             (uint8_t **)&header)) {
 654
 655                 if ((frev == 3) && (crev == 6)) {
 656                         smu_info_v3_6 = (struct atom_smu_info_v3_6 *)header;
 657
 658                         smu->smu_table.boot_values.socclk = smu_info_v3_6->bootup_socclk_10khz;
 659                         smu->smu_table.boot_values.vclk = smu_info_v3_6->bootup_vclk_10khz;
 660                         smu->smu_table.boot_values.dclk = smu_info_v3_6->bootup_dclk_10khz;
 661                         smu->smu_table.boot_values.fclk = smu_info_v3_6->bootup_fclk_10khz;
 662                 } else if ((frev == 3) && (crev == 1)) {
 663                         return 0;
 664                 } else if ((frev == 4) && (crev == 0)) {
 665                         smu_info_v4_0 = (struct atom_smu_info_v4_0 *)header;
 666
 667                         smu->smu_table.boot_values.socclk = smu_info_v4_0->bootup_socclk_10khz;
 668                         smu->smu_table.boot_values.dcefclk = smu_info_v4_0->bootup_dcefclk_10khz;
 669                         smu->smu_table.boot_values.vclk = smu_info_v4_0->bootup_vclk0_10khz;
 670                         smu->smu_table.boot_values.dclk = smu_info_v4_0->bootup_dclk0_10khz;
 671                         smu->smu_table.boot_values.fclk = smu_info_v4_0->bootup_fclk_10khz;
 672                 } else {
 673                         dev_warn(smu->adev->dev, "Unexpected and unhandled version: %d.%d\n",
 674                                                 (uint32_t)frev, (uint32_t)crev);
 675                 }
 676         }
 677
 678         return 0;
 679 }
 680
 681
 682 int smu_v13_0_notify_memory_pool_location(struct smu_context *smu)
 683 {
 684         struct smu_table_context *smu_table = &smu->smu_table;
 685         struct smu_table *memory_pool = &smu_table->memory_pool;
 686         int ret = 0;
 687         uint64_t address;
 688         uint32_t address_low, address_high;
 689
 690         if (memory_pool->size == 0 || memory_pool->cpu_addr == NULL)
 691                 return ret;
 692
 693         address = memory_pool->mc_address;
 694         address_high = (uint32_t)upper_32_bits(address);
 695         address_low  = (uint32_t)lower_32_bits(address);
 696
 697         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrHigh,
 698                                               address_high, NULL);
 699         if (ret)
 700                 return ret;
 701         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrLow,
 702                                               address_low, NULL);
 703         if (ret)
 704                 return ret;
 705         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramSize,
 706                                               (uint32_t)memory_pool->size, NULL);
 707         if (ret)
 708                 return ret;
 709
 710         return ret;
 711 }
 712
 713 int smu_v13_0_set_min_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk)
 714 {
 715         int ret;
 716
 717         ret = smu_cmn_send_smc_msg_with_param(smu,
 718                                               SMU_MSG_SetMinDeepSleepDcefclk, clk, NULL);
 719         if (ret)
 720                 dev_err(smu->adev->dev, "SMU13 attempt to set divider for DCEFCLK Failed!");
 721
 722         return ret;
 723 }
 724
 725 int smu_v13_0_set_driver_table_location(struct smu_context *smu)
 726 {
 727         struct smu_table *driver_table = &smu->smu_table.driver_table;
 728         int ret = 0;
 729
 730         if (driver_table->mc_address) {
 731                 ret = smu_cmn_send_smc_msg_with_param(smu,
 732                                                       SMU_MSG_SetDriverDramAddrHigh,
 733                                                       upper_32_bits(driver_table->mc_address),
 734                                                       NULL);
 735                 if (!ret)
 736                         ret = smu_cmn_send_smc_msg_with_param(smu,
 737                                                               SMU_MSG_SetDriverDramAddrLow,
 738                                                               lower_32_bits(driver_table->mc_address),
 739                                                               NULL);
 740         }
 741
 742         return ret;
 743 }
 744
 745 int smu_v13_0_set_tool_table_location(struct smu_context *smu)
 746 {
 747         int ret = 0;
 748         struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG];
 749
 750         if (tool_table->mc_address) {
 751                 ret = smu_cmn_send_smc_msg_with_param(smu,
 752                                                       SMU_MSG_SetToolsDramAddrHigh,
 753                                                       upper_32_bits(tool_table->mc_address),
 754                                                       NULL);
 755                 if (!ret)
 756                         ret = smu_cmn_send_smc_msg_with_param(smu,
 757                                                               SMU_MSG_SetToolsDramAddrLow,
 758                                                               lower_32_bits(tool_table->mc_address),
 759                                                               NULL);
 760         }
 761
 762         return ret;
 763 }
 764
 765 int smu_v13_0_init_display_count(struct smu_context *smu, uint32_t count)
 766 {
 767         int ret = 0;
 768
 769         if (!smu->pm_enabled)
 770                 return ret;
 771
 772         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, count, NULL);
 773
 774         return ret;
 775 }
 776
 777 int smu_v13_0_set_allowed_mask(struct smu_context *smu)
 778 {
 779         struct smu_feature *feature = &smu->smu_feature;
 780         int ret = 0;
 781         uint32_t feature_mask[2];
 782
 783         if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) ||
 784             feature->feature_num < 64)
 785                 return -EINVAL;
 786
 787         bitmap_to_arr32(feature_mask, feature->allowed, 64);
 788
 789         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh,
 790                                               feature_mask[1], NULL);
 791         if (ret)
 792                 return ret;
 793
 794         return smu_cmn_send_smc_msg_with_param(smu,
 795                                                SMU_MSG_SetAllowedFeaturesMaskLow,
 796                                                feature_mask[0],
 797                                                NULL);
 798 }
 799
 800 int smu_v13_0_gfx_off_control(struct smu_context *smu, bool enable)
 801 {
 802         int ret = 0;
 803         struct amdgpu_device *adev = smu->adev;
 804
 805         switch (adev->ip_versions[MP1_HWIP][0]) {
 806         case IP_VERSION(13, 0, 0):
 807         case IP_VERSION(13, 0, 1):
 808         case IP_VERSION(13, 0, 3):
 809         case IP_VERSION(13, 0, 4):
 810         case IP_VERSION(13, 0, 5):
 811         case IP_VERSION(13, 0, 7):
 812         case IP_VERSION(13, 0, 8):
 813         case IP_VERSION(13, 0, 10):
 814         case IP_VERSION(13, 0, 11):
 815                 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
 816                         return 0;
 817                 if (enable)
 818                         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_AllowGfxOff, NULL);
 819                 else
 820                         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_DisallowGfxOff, NULL);
 821                 break;
 822         default:
 823                 break;
 824         }
 825
 826         return ret;
 827 }
 828
 829 int smu_v13_0_system_features_control(struct smu_context *smu,
 830                                       bool en)
 831 {
 832         return smu_cmn_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures :
 833                                           SMU_MSG_DisableAllSmuFeatures), NULL);
 834 }
 835
 836 int smu_v13_0_notify_display_change(struct smu_context *smu)
 837 {
 838         int ret = 0;
 839
 840         if (!smu->pm_enabled)
 841                 return ret;
 842
 843         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
 844             smu->adev->gmc.vram_type == AMDGPU_VRAM_TYPE_HBM)
 845                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetUclkFastSwitch, 1, NULL);
 846
 847         return ret;
 848 }
 849
 850         static int
 851 smu_v13_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock,
 852                                     enum smu_clk_type clock_select)
 853 {
 854         int ret = 0;
 855         int clk_id;
 856
 857         if ((smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetDcModeMaxDpmFreq) < 0) ||
 858             (smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetMaxDpmFreq) < 0))
 859                 return 0;
 860
 861         clk_id = smu_cmn_to_asic_specific_index(smu,
 862                                                 CMN2ASIC_MAPPING_CLK,
 863                                                 clock_select);
 864         if (clk_id < 0)
 865                 return -EINVAL;
 866
 867         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetDcModeMaxDpmFreq,
 868                                               clk_id << 16, clock);
 869         if (ret) {
 870                 dev_err(smu->adev->dev, "[GetMaxSustainableClock] Failed to get max DC clock from SMC!");
 871                 return ret;
 872         }
 873
 874         if (*clock != 0)
 875                 return 0;
 876
 877         /* if DC limit is zero, return AC limit */
 878         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq,
 879                                               clk_id << 16, clock);
 880         if (ret) {
 881                 dev_err(smu->adev->dev, "[GetMaxSustainableClock] failed to get max AC clock from SMC!");
 882                 return ret;
 883         }
 884
 885         return 0;
 886 }
 887
 888 int smu_v13_0_init_max_sustainable_clocks(struct smu_context *smu)
 889 {
 890         struct smu_13_0_max_sustainable_clocks *max_sustainable_clocks =
 891                 smu->smu_table.max_sustainable_clocks;
 892         int ret = 0;
 893
 894         max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100;
 895         max_sustainable_clocks->soc_clock = smu->smu_table.boot_values.socclk / 100;
 896         max_sustainable_clocks->dcef_clock = smu->smu_table.boot_values.dcefclk / 100;
 897         max_sustainable_clocks->display_clock = 0xFFFFFFFF;
 898         max_sustainable_clocks->phy_clock = 0xFFFFFFFF;
 899         max_sustainable_clocks->pixel_clock = 0xFFFFFFFF;
 900
 901         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 902                 ret = smu_v13_0_get_max_sustainable_clock(smu,
 903                                                           &(max_sustainable_clocks->uclock),
 904                                                           SMU_UCLK);
 905                 if (ret) {
 906                         dev_err(smu->adev->dev, "[%s] failed to get max UCLK from SMC!",
 907                                 __func__);
 908                         return ret;
 909                 }
 910         }
 911
 912         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
 913                 ret = smu_v13_0_get_max_sustainable_clock(smu,
 914                                                           &(max_sustainable_clocks->soc_clock),
 915                                                           SMU_SOCCLK);
 916                 if (ret) {
 917                         dev_err(smu->adev->dev, "[%s] failed to get max SOCCLK from SMC!",
 918                                 __func__);
 919                         return ret;
 920                 }
 921         }
 922
 923         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
 924                 ret = smu_v13_0_get_max_sustainable_clock(smu,
 925                                                           &(max_sustainable_clocks->dcef_clock),
 926                                                           SMU_DCEFCLK);
 927                 if (ret) {
 928                         dev_err(smu->adev->dev, "[%s] failed to get max DCEFCLK from SMC!",
 929                                 __func__);
 930                         return ret;
 931                 }
 932
 933                 ret = smu_v13_0_get_max_sustainable_clock(smu,
 934                                                           &(max_sustainable_clocks->display_clock),
 935                                                           SMU_DISPCLK);
 936                 if (ret) {
 937                         dev_err(smu->adev->dev, "[%s] failed to get max DISPCLK from SMC!",
 938                                 __func__);
 939                         return ret;
 940                 }
 941                 ret = smu_v13_0_get_max_sustainable_clock(smu,
 942                                                           &(max_sustainable_clocks->phy_clock),
 943                                                           SMU_PHYCLK);
 944                 if (ret) {
 945                         dev_err(smu->adev->dev, "[%s] failed to get max PHYCLK from SMC!",
 946                                 __func__);
 947                         return ret;
 948                 }
 949                 ret = smu_v13_0_get_max_sustainable_clock(smu,
 950                                                           &(max_sustainable_clocks->pixel_clock),
 951                                                           SMU_PIXCLK);
 952                 if (ret) {
 953                         dev_err(smu->adev->dev, "[%s] failed to get max PIXCLK from SMC!",
 954                                 __func__);
 955                         return ret;
 956                 }
 957         }
 958
 959         if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock)
 960                 max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock;
 961
 962         return 0;
 963 }
 964
 965 int smu_v13_0_get_current_power_limit(struct smu_context *smu,
 966                                       uint32_t *power_limit)
 967 {
 968         int power_src;
 969         int ret = 0;
 970
 971         if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT))
 972                 return -EINVAL;
 973
 974         power_src = smu_cmn_to_asic_specific_index(smu,
 975                                                    CMN2ASIC_MAPPING_PWR,
 976                                                    smu->adev->pm.ac_power ?
 977                                                    SMU_POWER_SOURCE_AC :
 978                                                    SMU_POWER_SOURCE_DC);
 979         if (power_src < 0)
 980                 return -EINVAL;
 981
 982         ret = smu_cmn_send_smc_msg_with_param(smu,
 983                                               SMU_MSG_GetPptLimit,
 984                                               power_src << 16,
 985                                               power_limit);
 986         if (ret)
 987                 dev_err(smu->adev->dev, "[%s] get PPT limit failed!", __func__);
 988
 989         return ret;
 990 }
 991
 992 int smu_v13_0_set_power_limit(struct smu_context *smu,
 993                               enum smu_ppt_limit_type limit_type,
 994                               uint32_t limit)
 995 {
 996         int ret = 0;
 997
 998         if (limit_type != SMU_DEFAULT_PPT_LIMIT)
 999                 return -EINVAL;
1000
1001         if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
1002                 dev_err(smu->adev->dev, "Setting new power limit is not supported!\n");
1003                 return -EOPNOTSUPP;
1004         }
1005
1006         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, limit, NULL);
1007         if (ret) {
1008                 dev_err(smu->adev->dev, "[%s] Set power limit Failed!\n", __func__);
1009                 return ret;
1010         }
1011
1012         smu->current_power_limit = limit;
1013
1014         return 0;
1015 }
1016
1017 static int smu_v13_0_allow_ih_interrupt(struct smu_context *smu)
1018 {
1019         return smu_cmn_send_smc_msg(smu,
1020                                     SMU_MSG_AllowIHHostInterrupt,
1021                                     NULL);
1022 }
1023
1024 static int smu_v13_0_process_pending_interrupt(struct smu_context *smu)
1025 {
1026         int ret = 0;
1027
1028         if (smu->dc_controlled_by_gpio &&
1029             smu_cmn_feature_is_enabled(smu, SMU_FEATURE_ACDC_BIT))
1030                 ret = smu_v13_0_allow_ih_interrupt(smu);
1031
1032         return ret;
1033 }
1034
1035 int smu_v13_0_enable_thermal_alert(struct smu_context *smu)
1036 {
1037         int ret = 0;
1038
1039         if (!smu->irq_source.num_types)
1040                 return 0;
1041
1042         ret = amdgpu_irq_get(smu->adev, &smu->irq_source, 0);
1043         if (ret)
1044                 return ret;
1045
1046         return smu_v13_0_process_pending_interrupt(smu);
1047 }
1048
1049 int smu_v13_0_disable_thermal_alert(struct smu_context *smu)
1050 {
1051         if (!smu->irq_source.num_types)
1052                 return 0;
1053
1054         return amdgpu_irq_put(smu->adev, &smu->irq_source, 0);
1055 }
1056
1057 static uint16_t convert_to_vddc(uint8_t vid)
1058 {
1059         return (uint16_t) ((6200 - (vid * 25)) / SMU13_VOLTAGE_SCALE);
1060 }
1061
1062 int smu_v13_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value)
1063 {
1064         struct amdgpu_device *adev = smu->adev;
1065         uint32_t vdd = 0, val_vid = 0;
1066
1067         if (!value)
1068                 return -EINVAL;
1069         val_vid = (RREG32_SOC15(SMUIO, 0, regSMUSVI0_TEL_PLANE0) &
1070                    SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >>
1071                 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT;
1072
1073         vdd = (uint32_t)convert_to_vddc((uint8_t)val_vid);
1074
1075         *value = vdd;
1076
1077         return 0;
1078
1079 }
1080
1081 int
1082 smu_v13_0_display_clock_voltage_request(struct smu_context *smu,
1083                                         struct pp_display_clock_request
1084                                         *clock_req)
1085 {
1086         enum amd_pp_clock_type clk_type = clock_req->clock_type;
1087         int ret = 0;
1088         enum smu_clk_type clk_select = 0;
1089         uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
1090
1091         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) ||
1092             smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1093                 switch (clk_type) {
1094                 case amd_pp_dcef_clock:
1095                         clk_select = SMU_DCEFCLK;
1096                         break;
1097                 case amd_pp_disp_clock:
1098                         clk_select = SMU_DISPCLK;
1099                         break;
1100                 case amd_pp_pixel_clock:
1101                         clk_select = SMU_PIXCLK;
1102                         break;
1103                 case amd_pp_phy_clock:
1104                         clk_select = SMU_PHYCLK;
1105                         break;
1106                 case amd_pp_mem_clock:
1107                         clk_select = SMU_UCLK;
1108                         break;
1109                 default:
1110                         dev_info(smu->adev->dev, "[%s] Invalid Clock Type!", __func__);
1111                         ret = -EINVAL;
1112                         break;
1113                 }
1114
1115                 if (ret)
1116                         goto failed;
1117
1118                 if (clk_select == SMU_UCLK && smu->disable_uclk_switch)
1119                         return 0;
1120
1121                 ret = smu_v13_0_set_hard_freq_limited_range(smu, clk_select, clk_freq, 0);
1122
1123                 if (clk_select == SMU_UCLK)
1124                         smu->hard_min_uclk_req_from_dal = clk_freq;
1125         }
1126
1127 failed:
1128         return ret;
1129 }
1130
1131 uint32_t smu_v13_0_get_fan_control_mode(struct smu_context *smu)
1132 {
1133         if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1134                 return AMD_FAN_CTRL_MANUAL;
1135         else
1136                 return AMD_FAN_CTRL_AUTO;
1137 }
1138
1139         static int
1140 smu_v13_0_auto_fan_control(struct smu_context *smu, bool auto_fan_control)
1141 {
1142         int ret = 0;
1143
1144         if (!smu_cmn_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1145                 return 0;
1146
1147         ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, auto_fan_control);
1148         if (ret)
1149                 dev_err(smu->adev->dev, "[%s]%s smc FAN CONTROL feature failed!",
1150                         __func__, (auto_fan_control ? "Start" : "Stop"));
1151
1152         return ret;
1153 }
1154
1155         static int
1156 smu_v13_0_set_fan_static_mode(struct smu_context *smu, uint32_t mode)
1157 {
1158         struct amdgpu_device *adev = smu->adev;
1159
1160         WREG32_SOC15(THM, 0, regCG_FDO_CTRL2,
1161                      REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL2),
1162                                    CG_FDO_CTRL2, TMIN, 0));
1163         WREG32_SOC15(THM, 0, regCG_FDO_CTRL2,
1164                      REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL2),
1165                                    CG_FDO_CTRL2, FDO_PWM_MODE, mode));
1166
1167         return 0;
1168 }
1169
1170 int smu_v13_0_set_fan_speed_pwm(struct smu_context *smu,
1171                                 uint32_t speed)
1172 {
1173         struct amdgpu_device *adev = smu->adev;
1174         uint32_t duty100, duty;
1175         uint64_t tmp64;
1176
1177         speed = MIN(speed, 255);
1178
1179         if (smu_v13_0_auto_fan_control(smu, 0))
1180                 return -EINVAL;
1181
1182         duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL1),
1183                                 CG_FDO_CTRL1, FMAX_DUTY100);
1184         if (!duty100)
1185                 return -EINVAL;
1186
1187         tmp64 = (uint64_t)speed * duty100;
1188         do_div(tmp64, 255);
1189         duty = (uint32_t)tmp64;
1190
1191         WREG32_SOC15(THM, 0, regCG_FDO_CTRL0,
1192                      REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_FDO_CTRL0),
1193                                    CG_FDO_CTRL0, FDO_STATIC_DUTY, duty));
1194
1195         return smu_v13_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC);
1196 }
1197
1198         int
1199 smu_v13_0_set_fan_control_mode(struct smu_context *smu,
1200                                uint32_t mode)
1201 {
1202         int ret = 0;
1203
1204         switch (mode) {
1205         case AMD_FAN_CTRL_NONE:
1206                 ret = smu_v13_0_set_fan_speed_pwm(smu, 255);
1207                 break;
1208         case AMD_FAN_CTRL_MANUAL:
1209                 ret = smu_v13_0_auto_fan_control(smu, 0);
1210                 break;
1211         case AMD_FAN_CTRL_AUTO:
1212                 ret = smu_v13_0_auto_fan_control(smu, 1);
1213                 break;
1214         default:
1215                 break;
1216         }
1217
1218         if (ret) {
1219                 dev_err(smu->adev->dev, "[%s]Set fan control mode failed!", __func__);
1220                 return -EINVAL;
1221         }
1222
1223         return ret;
1224 }
1225
1226 int smu_v13_0_set_fan_speed_rpm(struct smu_context *smu,
1227                                 uint32_t speed)
1228 {
1229         struct amdgpu_device *adev = smu->adev;
1230         uint32_t crystal_clock_freq = 2500;
1231         uint32_t tach_period;
1232         int ret;
1233
1234         if (!speed)
1235                 return -EINVAL;
1236
1237         ret = smu_v13_0_auto_fan_control(smu, 0);
1238         if (ret)
1239                 return ret;
1240
1241         tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
1242         WREG32_SOC15(THM, 0, regCG_TACH_CTRL,
1243                      REG_SET_FIELD(RREG32_SOC15(THM, 0, regCG_TACH_CTRL),
1244                                    CG_TACH_CTRL, TARGET_PERIOD,
1245                                    tach_period));
1246
1247         return smu_v13_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM);
1248 }
1249
1250 int smu_v13_0_set_xgmi_pstate(struct smu_context *smu,
1251                               uint32_t pstate)
1252 {
1253         int ret = 0;
1254         ret = smu_cmn_send_smc_msg_with_param(smu,
1255                                               SMU_MSG_SetXgmiMode,
1256                                               pstate ? XGMI_MODE_PSTATE_D0 : XGMI_MODE_PSTATE_D3,
1257                                               NULL);
1258         return ret;
1259 }
1260
1261 static int smu_v13_0_set_irq_state(struct amdgpu_device *adev,
1262                                    struct amdgpu_irq_src *source,
1263                                    unsigned tyep,
1264                                    enum amdgpu_interrupt_state state)
1265 {
1266         struct smu_context *smu = adev->powerplay.pp_handle;
1267         uint32_t low, high;
1268         uint32_t val = 0;
1269
1270         switch (state) {
1271         case AMDGPU_IRQ_STATE_DISABLE:
1272                 /* For THM irqs */
1273                 val = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);
1274                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 1);
1275                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 1);
1276                 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, val);
1277
1278                 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_ENA, 0);
1279
1280                 /* For MP1 SW irqs */
1281                 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1282                 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);
1283                 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);
1284
1285                 break;
1286         case AMDGPU_IRQ_STATE_ENABLE:
1287                 /* For THM irqs */
1288                 low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP,
1289                           smu->thermal_range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES);
1290                 high = min(SMU_THERMAL_MAXIMUM_ALERT_TEMP,
1291                            smu->thermal_range.software_shutdown_temp);
1292
1293                 val = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);
1294                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
1295                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
1296                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0);
1297                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0);
1298                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff));
1299                 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff));
1300                 val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
1301                 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, val);
1302
1303                 val = (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
1304                 val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
1305                 val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
1306                 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_ENA, val);
1307
1308                 /* For MP1 SW irqs */
1309                 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT);
1310                 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE);
1311                 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0);
1312                 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT, val);
1313
1314                 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1315                 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0);
1316                 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);
1317
1318                 break;
1319         default:
1320                 break;
1321         }
1322
1323         return 0;
1324 }
1325
1326 static int smu_v13_0_ack_ac_dc_interrupt(struct smu_context *smu)
1327 {
1328         return smu_cmn_send_smc_msg(smu,
1329                                     SMU_MSG_ReenableAcDcInterrupt,
1330                                     NULL);
1331 }
1332
1333 #define THM_11_0__SRCID__THM_DIG_THERM_L2H              0               /* ASIC_TEMP > CG_THERMAL_INT.DIG_THERM_INTH  */
1334 #define THM_11_0__SRCID__THM_DIG_THERM_H2L              1               /* ASIC_TEMP < CG_THERMAL_INT.DIG_THERM_INTL  */
1335 #define SMUIO_11_0__SRCID__SMUIO_GPIO19                 83
1336
1337 static int smu_v13_0_irq_process(struct amdgpu_device *adev,
1338                                  struct amdgpu_irq_src *source,
1339                                  struct amdgpu_iv_entry *entry)
1340 {
1341         struct smu_context *smu = adev->powerplay.pp_handle;
1342         uint32_t client_id = entry->client_id;
1343         uint32_t src_id = entry->src_id;
1344         /*
1345          * ctxid is used to distinguish different
1346          * events for SMCToHost interrupt.
1347          */
1348         uint32_t ctxid = entry->src_data[0];
1349         uint32_t data;
1350         uint32_t high;
1351
1352         if (client_id == SOC15_IH_CLIENTID_THM) {
1353                 switch (src_id) {
1354                 case THM_11_0__SRCID__THM_DIG_THERM_L2H:
1355                         schedule_delayed_work(&smu->swctf_delayed_work,
1356                                               msecs_to_jiffies(AMDGPU_SWCTF_EXTRA_DELAY));
1357                         break;
1358                 case THM_11_0__SRCID__THM_DIG_THERM_H2L:
1359                         dev_emerg(adev->dev, "ERROR: GPU under temperature range detected\n");
1360                         break;
1361                 default:
1362                         dev_emerg(adev->dev, "ERROR: GPU under temperature range unknown src id (%d)\n",
1363                                   src_id);
1364                         break;
1365                 }
1366         } else if (client_id == SOC15_IH_CLIENTID_ROM_SMUIO) {
1367                 dev_emerg(adev->dev, "ERROR: GPU HW Critical Temperature Fault(aka CTF) detected!\n");
1368                 /*
1369                  * HW CTF just occurred. Shutdown to prevent further damage.
1370                  */
1371                 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU HW CTF!\n");
1372                 orderly_poweroff(true);
1373         } else if (client_id == SOC15_IH_CLIENTID_MP1) {
1374                 if (src_id == 0xfe) {
1375                         /* ACK SMUToHost interrupt */
1376                         data = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1377                         data = REG_SET_FIELD(data, MP1_SMN_IH_SW_INT_CTRL, INT_ACK, 1);
1378                         WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, data);
1379
1380                         switch (ctxid) {
1381                         case 0x3:
1382                                 dev_dbg(adev->dev, "Switched to AC mode!\n");
1383                                 smu_v13_0_ack_ac_dc_interrupt(smu);
1384                                 break;
1385                         case 0x4:
1386                                 dev_dbg(adev->dev, "Switched to DC mode!\n");
1387                                 smu_v13_0_ack_ac_dc_interrupt(smu);
1388                                 break;
1389                         case 0x7:
1390                                 /*
1391                                  * Increment the throttle interrupt counter
1392                                  */
1393                                 atomic64_inc(&smu->throttle_int_counter);
1394
1395                                 if (!atomic_read(&adev->throttling_logging_enabled))
1396                                         return 0;
1397
1398                                 if (__ratelimit(&adev->throttling_logging_rs))
1399                                         schedule_work(&smu->throttling_logging_work);
1400
1401                                 break;
1402                         case 0x8:
1403                                 high = smu->thermal_range.software_shutdown_temp +
1404                                         smu->thermal_range.software_shutdown_temp_offset;
1405                                 high = min_t(typeof(high),
1406                                              SMU_THERMAL_MAXIMUM_ALERT_TEMP,
1407                                              high);
1408                                 dev_emerg(adev->dev, "Reduce soft CTF limit to %d (by an offset %d)\n",
1409                                                         high,
1410                                                         smu->thermal_range.software_shutdown_temp_offset);
1411
1412                                 data = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);
1413                                 data = REG_SET_FIELD(data, THM_THERMAL_INT_CTRL,
1414                                                         DIG_THERM_INTH,
1415                                                         (high & 0xff));
1416                                 data = data & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
1417                                 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, data);
1418                                 break;
1419                         case 0x9:
1420                                 high = min_t(typeof(high),
1421                                              SMU_THERMAL_MAXIMUM_ALERT_TEMP,
1422                                              smu->thermal_range.software_shutdown_temp);
1423                                 dev_emerg(adev->dev, "Recover soft CTF limit to %d\n", high);
1424
1425                                 data = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);
1426                                 data = REG_SET_FIELD(data, THM_THERMAL_INT_CTRL,
1427                                                         DIG_THERM_INTH,
1428                                                         (high & 0xff));
1429                                 data = data & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
1430                                 WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, data);
1431                                 break;
1432                         }
1433                 }
1434         }
1435
1436         return 0;
1437 }
1438
1439 static const struct amdgpu_irq_src_funcs smu_v13_0_irq_funcs = {
1440         .set = smu_v13_0_set_irq_state,
1441         .process = smu_v13_0_irq_process,
1442 };
1443
1444 int smu_v13_0_register_irq_handler(struct smu_context *smu)
1445 {
1446         struct amdgpu_device *adev = smu->adev;
1447         struct amdgpu_irq_src *irq_src = &smu->irq_source;
1448         int ret = 0;
1449
1450         if (amdgpu_sriov_vf(adev))
1451                 return 0;
1452
1453         irq_src->num_types = 1;
1454         irq_src->funcs = &smu_v13_0_irq_funcs;
1455
1456         ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1457                                 THM_11_0__SRCID__THM_DIG_THERM_L2H,
1458                                 irq_src);
1459         if (ret)
1460                 return ret;
1461
1462         ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1463                                 THM_11_0__SRCID__THM_DIG_THERM_H2L,
1464                                 irq_src);
1465         if (ret)
1466                 return ret;
1467
1468         /* Register CTF(GPIO_19) interrupt */
1469         ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_ROM_SMUIO,
1470                                 SMUIO_11_0__SRCID__SMUIO_GPIO19,
1471                                 irq_src);
1472         if (ret)
1473                 return ret;
1474
1475         ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_MP1,
1476                                 0xfe,
1477                                 irq_src);
1478         if (ret)
1479                 return ret;
1480
1481         return ret;
1482 }
1483
1484 int smu_v13_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
1485                                                struct pp_smu_nv_clock_table *max_clocks)
1486 {
1487         struct smu_table_context *table_context = &smu->smu_table;
1488         struct smu_13_0_max_sustainable_clocks *sustainable_clocks = NULL;
1489
1490         if (!max_clocks || !table_context->max_sustainable_clocks)
1491                 return -EINVAL;
1492
1493         sustainable_clocks = table_context->max_sustainable_clocks;
1494
1495         max_clocks->dcfClockInKhz =
1496                 (unsigned int) sustainable_clocks->dcef_clock * 1000;
1497         max_clocks->displayClockInKhz =
1498                 (unsigned int) sustainable_clocks->display_clock * 1000;
1499         max_clocks->phyClockInKhz =
1500                 (unsigned int) sustainable_clocks->phy_clock * 1000;
1501         max_clocks->pixelClockInKhz =
1502                 (unsigned int) sustainable_clocks->pixel_clock * 1000;
1503         max_clocks->uClockInKhz =
1504                 (unsigned int) sustainable_clocks->uclock * 1000;
1505         max_clocks->socClockInKhz =
1506                 (unsigned int) sustainable_clocks->soc_clock * 1000;
1507         max_clocks->dscClockInKhz = 0;
1508         max_clocks->dppClockInKhz = 0;
1509         max_clocks->fabricClockInKhz = 0;
1510
1511         return 0;
1512 }
1513
1514 int smu_v13_0_set_azalia_d3_pme(struct smu_context *smu)
1515 {
1516         int ret = 0;
1517
1518         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_BacoAudioD3PME, NULL);
1519
1520         return ret;
1521 }
1522
1523 static int smu_v13_0_wait_for_reset_complete(struct smu_context *smu,
1524                                              uint64_t event_arg)
1525 {
1526         int ret = 0;
1527
1528         dev_dbg(smu->adev->dev, "waiting for smu reset complete\n");
1529         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GfxDriverResetRecovery, NULL);
1530
1531         return ret;
1532 }
1533
1534 int smu_v13_0_wait_for_event(struct smu_context *smu, enum smu_event_type event,
1535                              uint64_t event_arg)
1536 {
1537         int ret = -EINVAL;
1538
1539         switch (event) {
1540         case SMU_EVENT_RESET_COMPLETE:
1541                 ret = smu_v13_0_wait_for_reset_complete(smu, event_arg);
1542                 break;
1543         default:
1544                 break;
1545         }
1546
1547         return ret;
1548 }
1549
1550 int smu_v13_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
1551                                     uint32_t *min, uint32_t *max)
1552 {
1553         int ret = 0, clk_id = 0;
1554         uint32_t param = 0;
1555         uint32_t clock_limit;
1556
1557         if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) {
1558                 switch (clk_type) {
1559                 case SMU_MCLK:
1560                 case SMU_UCLK:
1561                         clock_limit = smu->smu_table.boot_values.uclk;
1562                         break;
1563                 case SMU_GFXCLK:
1564                 case SMU_SCLK:
1565                         clock_limit = smu->smu_table.boot_values.gfxclk;
1566                         break;
1567                 case SMU_SOCCLK:
1568                         clock_limit = smu->smu_table.boot_values.socclk;
1569                         break;
1570                 default:
1571                         clock_limit = 0;
1572                         break;
1573                 }
1574
1575                 /* clock in Mhz unit */
1576                 if (min)
1577                         *min = clock_limit / 100;
1578                 if (max)
1579                         *max = clock_limit / 100;
1580
1581                 return 0;
1582         }
1583
1584         clk_id = smu_cmn_to_asic_specific_index(smu,
1585                                                 CMN2ASIC_MAPPING_CLK,
1586                                                 clk_type);
1587         if (clk_id < 0) {
1588                 ret = -EINVAL;
1589                 goto failed;
1590         }
1591         param = (clk_id & 0xffff) << 16;
1592
1593         if (max) {
1594                 if (smu->adev->pm.ac_power)
1595                         ret = smu_cmn_send_smc_msg_with_param(smu,
1596                                                               SMU_MSG_GetMaxDpmFreq,
1597                                                               param,
1598                                                               max);
1599                 else
1600                         ret = smu_cmn_send_smc_msg_with_param(smu,
1601                                                               SMU_MSG_GetDcModeMaxDpmFreq,
1602                                                               param,
1603                                                               max);
1604                 if (ret)
1605                         goto failed;
1606         }
1607
1608         if (min) {
1609                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq, param, min);
1610                 if (ret)
1611                         goto failed;
1612         }
1613
1614 failed:
1615         return ret;
1616 }
1617
1618 int smu_v13_0_set_soft_freq_limited_range(struct smu_context *smu,
1619                                           enum smu_clk_type clk_type,
1620                                           uint32_t min,
1621                                           uint32_t max)
1622 {
1623         int ret = 0, clk_id = 0;
1624         uint32_t param;
1625
1626         if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1627                 return 0;
1628
1629         clk_id = smu_cmn_to_asic_specific_index(smu,
1630                                                 CMN2ASIC_MAPPING_CLK,
1631                                                 clk_type);
1632         if (clk_id < 0)
1633                 return clk_id;
1634
1635         if (max > 0) {
1636                 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1637                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq,
1638                                                       param, NULL);
1639                 if (ret)
1640                         goto out;
1641         }
1642
1643         if (min > 0) {
1644                 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1645                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinByFreq,
1646                                                       param, NULL);
1647                 if (ret)
1648                         goto out;
1649         }
1650
1651 out:
1652         return ret;
1653 }
1654
1655 int smu_v13_0_set_hard_freq_limited_range(struct smu_context *smu,
1656                                           enum smu_clk_type clk_type,
1657                                           uint32_t min,
1658                                           uint32_t max)
1659 {
1660         int ret = 0, clk_id = 0;
1661         uint32_t param;
1662
1663         if (min <= 0 && max <= 0)
1664                 return -EINVAL;
1665
1666         if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1667                 return 0;
1668
1669         clk_id = smu_cmn_to_asic_specific_index(smu,
1670                                                 CMN2ASIC_MAPPING_CLK,
1671                                                 clk_type);
1672         if (clk_id < 0)
1673                 return clk_id;
1674
1675         if (max > 0) {
1676                 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1677                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMaxByFreq,
1678                                                       param, NULL);
1679                 if (ret)
1680                         return ret;
1681         }
1682
1683         if (min > 0) {
1684                 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1685                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq,
1686                                                       param, NULL);
1687                 if (ret)
1688                         return ret;
1689         }
1690
1691         return ret;
1692 }
1693
1694 int smu_v13_0_set_performance_level(struct smu_context *smu,
1695                                     enum amd_dpm_forced_level level)
1696 {
1697         struct smu_13_0_dpm_context *dpm_context =
1698                 smu->smu_dpm.dpm_context;
1699         struct smu_13_0_dpm_table *gfx_table =
1700                 &dpm_context->dpm_tables.gfx_table;
1701         struct smu_13_0_dpm_table *mem_table =
1702                 &dpm_context->dpm_tables.uclk_table;
1703         struct smu_13_0_dpm_table *soc_table =
1704                 &dpm_context->dpm_tables.soc_table;
1705         struct smu_13_0_dpm_table *vclk_table =
1706                 &dpm_context->dpm_tables.vclk_table;
1707         struct smu_13_0_dpm_table *dclk_table =
1708                 &dpm_context->dpm_tables.dclk_table;
1709         struct smu_13_0_dpm_table *fclk_table =
1710                 &dpm_context->dpm_tables.fclk_table;
1711         struct smu_umd_pstate_table *pstate_table =
1712                 &smu->pstate_table;
1713         struct amdgpu_device *adev = smu->adev;
1714         uint32_t sclk_min = 0, sclk_max = 0;
1715         uint32_t mclk_min = 0, mclk_max = 0;
1716         uint32_t socclk_min = 0, socclk_max = 0;
1717         uint32_t vclk_min = 0, vclk_max = 0;
1718         uint32_t dclk_min = 0, dclk_max = 0;
1719         uint32_t fclk_min = 0, fclk_max = 0;
1720         int ret = 0, i;
1721
1722         switch (level) {
1723         case AMD_DPM_FORCED_LEVEL_HIGH:
1724                 sclk_min = sclk_max = gfx_table->max;
1725                 mclk_min = mclk_max = mem_table->max;
1726                 socclk_min = socclk_max = soc_table->max;
1727                 vclk_min = vclk_max = vclk_table->max;
1728                 dclk_min = dclk_max = dclk_table->max;
1729                 fclk_min = fclk_max = fclk_table->max;
1730                 break;
1731         case AMD_DPM_FORCED_LEVEL_LOW:
1732                 sclk_min = sclk_max = gfx_table->min;
1733                 mclk_min = mclk_max = mem_table->min;
1734                 socclk_min = socclk_max = soc_table->min;
1735                 vclk_min = vclk_max = vclk_table->min;
1736                 dclk_min = dclk_max = dclk_table->min;
1737                 fclk_min = fclk_max = fclk_table->min;
1738                 break;
1739         case AMD_DPM_FORCED_LEVEL_AUTO:
1740                 sclk_min = gfx_table->min;
1741                 sclk_max = gfx_table->max;
1742                 mclk_min = mem_table->min;
1743                 mclk_max = mem_table->max;
1744                 socclk_min = soc_table->min;
1745                 socclk_max = soc_table->max;
1746                 vclk_min = vclk_table->min;
1747                 vclk_max = vclk_table->max;
1748                 dclk_min = dclk_table->min;
1749                 dclk_max = dclk_table->max;
1750                 fclk_min = fclk_table->min;
1751                 fclk_max = fclk_table->max;
1752                 break;
1753         case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1754                 sclk_min = sclk_max = pstate_table->gfxclk_pstate.standard;
1755                 mclk_min = mclk_max = pstate_table->uclk_pstate.standard;
1756                 socclk_min = socclk_max = pstate_table->socclk_pstate.standard;
1757                 vclk_min = vclk_max = pstate_table->vclk_pstate.standard;
1758                 dclk_min = dclk_max = pstate_table->dclk_pstate.standard;
1759                 fclk_min = fclk_max = pstate_table->fclk_pstate.standard;
1760                 break;
1761         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1762                 sclk_min = sclk_max = pstate_table->gfxclk_pstate.min;
1763                 break;
1764         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1765                 mclk_min = mclk_max = pstate_table->uclk_pstate.min;
1766                 break;
1767         case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1768                 sclk_min = sclk_max = pstate_table->gfxclk_pstate.peak;
1769                 mclk_min = mclk_max = pstate_table->uclk_pstate.peak;
1770                 socclk_min = socclk_max = pstate_table->socclk_pstate.peak;
1771                 vclk_min = vclk_max = pstate_table->vclk_pstate.peak;
1772                 dclk_min = dclk_max = pstate_table->dclk_pstate.peak;
1773                 fclk_min = fclk_max = pstate_table->fclk_pstate.peak;
1774                 break;
1775         case AMD_DPM_FORCED_LEVEL_MANUAL:
1776         case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1777                 return 0;
1778         default:
1779                 dev_err(adev->dev, "Invalid performance level %d\n", level);
1780                 return -EINVAL;
1781         }
1782
1783         /*
1784          * Unset those settings for SMU 13.0.2. As soft limits settings
1785          * for those clock domains are not supported.
1786          */
1787         if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2)) {
1788                 mclk_min = mclk_max = 0;
1789                 socclk_min = socclk_max = 0;
1790                 vclk_min = vclk_max = 0;
1791                 dclk_min = dclk_max = 0;
1792                 fclk_min = fclk_max = 0;
1793         }
1794
1795         if (sclk_min && sclk_max) {
1796                 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1797                                                             SMU_GFXCLK,
1798                                                             sclk_min,
1799                                                             sclk_max);
1800                 if (ret)
1801                         return ret;
1802
1803                 pstate_table->gfxclk_pstate.curr.min = sclk_min;
1804                 pstate_table->gfxclk_pstate.curr.max = sclk_max;
1805         }
1806
1807         if (mclk_min && mclk_max) {
1808                 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1809                                                             SMU_MCLK,
1810                                                             mclk_min,
1811                                                             mclk_max);
1812                 if (ret)
1813                         return ret;
1814
1815                 pstate_table->uclk_pstate.curr.min = mclk_min;
1816                 pstate_table->uclk_pstate.curr.max = mclk_max;
1817         }
1818
1819         if (socclk_min && socclk_max) {
1820                 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1821                                                             SMU_SOCCLK,
1822                                                             socclk_min,
1823                                                             socclk_max);
1824                 if (ret)
1825                         return ret;
1826
1827                 pstate_table->socclk_pstate.curr.min = socclk_min;
1828                 pstate_table->socclk_pstate.curr.max = socclk_max;
1829         }
1830
1831         if (vclk_min && vclk_max) {
1832                 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1833                         if (adev->vcn.harvest_config & (1 << i))
1834                                 continue;
1835                         ret = smu_v13_0_set_soft_freq_limited_range(smu,
1836                                                                     i ? SMU_VCLK1 : SMU_VCLK,
1837                                                                     vclk_min,
1838                                                                     vclk_max);
1839                         if (ret)
1840                                 return ret;
1841                 }
1842                 pstate_table->vclk_pstate.curr.min = vclk_min;
1843                 pstate_table->vclk_pstate.curr.max = vclk_max;
1844         }
1845
1846         if (dclk_min && dclk_max) {
1847                 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1848                         if (adev->vcn.harvest_config & (1 << i))
1849                                 continue;
1850                         ret = smu_v13_0_set_soft_freq_limited_range(smu,
1851                                                                     i ? SMU_DCLK1 : SMU_DCLK,
1852                                                                     dclk_min,
1853                                                                     dclk_max);
1854                         if (ret)
1855                                 return ret;
1856                 }
1857                 pstate_table->dclk_pstate.curr.min = dclk_min;
1858                 pstate_table->dclk_pstate.curr.max = dclk_max;
1859         }
1860
1861         if (fclk_min && fclk_max) {
1862                 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1863                                                             SMU_FCLK,
1864                                                             fclk_min,
1865                                                             fclk_max);
1866                 if (ret)
1867                         return ret;
1868
1869                 pstate_table->fclk_pstate.curr.min = fclk_min;
1870                 pstate_table->fclk_pstate.curr.max = fclk_max;
1871         }
1872
1873         return ret;
1874 }
1875
1876 int smu_v13_0_set_power_source(struct smu_context *smu,
1877                                enum smu_power_src_type power_src)
1878 {
1879         int pwr_source;
1880
1881         pwr_source = smu_cmn_to_asic_specific_index(smu,
1882                                                     CMN2ASIC_MAPPING_PWR,
1883                                                     (uint32_t)power_src);
1884         if (pwr_source < 0)
1885                 return -EINVAL;
1886
1887         return smu_cmn_send_smc_msg_with_param(smu,
1888                                                SMU_MSG_NotifyPowerSource,
1889                                                pwr_source,
1890                                                NULL);
1891 }
1892
1893 int smu_v13_0_get_dpm_freq_by_index(struct smu_context *smu,
1894                                     enum smu_clk_type clk_type, uint16_t level,
1895                                     uint32_t *value)
1896 {
1897         int ret = 0, clk_id = 0;
1898         uint32_t param;
1899
1900         if (!value)
1901                 return -EINVAL;
1902
1903         if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1904                 return 0;
1905
1906         clk_id = smu_cmn_to_asic_specific_index(smu,
1907                                                 CMN2ASIC_MAPPING_CLK,
1908                                                 clk_type);
1909         if (clk_id < 0)
1910                 return clk_id;
1911
1912         param = (uint32_t)(((clk_id & 0xffff) << 16) | (level & 0xffff));
1913
1914         ret = smu_cmn_send_smc_msg_with_param(smu,
1915                                               SMU_MSG_GetDpmFreqByIndex,
1916                                               param,
1917                                               value);
1918         if (ret)
1919                 return ret;
1920
1921         *value = *value & 0x7fffffff;
1922
1923         return ret;
1924 }
1925
1926 static int smu_v13_0_get_dpm_level_count(struct smu_context *smu,
1927                                          enum smu_clk_type clk_type,
1928                                          uint32_t *value)
1929 {
1930         int ret;
1931
1932         ret = smu_v13_0_get_dpm_freq_by_index(smu, clk_type, 0xff, value);
1933         /* SMU v13.0.2 FW returns 0 based max level, increment by one for it */
1934         if ((smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2)) && (!ret && value))
1935                 ++(*value);
1936
1937         return ret;
1938 }
1939
1940 static int smu_v13_0_get_fine_grained_status(struct smu_context *smu,
1941                                              enum smu_clk_type clk_type,
1942                                              bool *is_fine_grained_dpm)
1943 {
1944         int ret = 0, clk_id = 0;
1945         uint32_t param;
1946         uint32_t value;
1947
1948         if (!is_fine_grained_dpm)
1949                 return -EINVAL;
1950
1951         if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1952                 return 0;
1953
1954         clk_id = smu_cmn_to_asic_specific_index(smu,
1955                                                 CMN2ASIC_MAPPING_CLK,
1956                                                 clk_type);
1957         if (clk_id < 0)
1958                 return clk_id;
1959
1960         param = (uint32_t)(((clk_id & 0xffff) << 16) | 0xff);
1961
1962         ret = smu_cmn_send_smc_msg_with_param(smu,
1963                                               SMU_MSG_GetDpmFreqByIndex,
1964                                               param,
1965                                               &value);
1966         if (ret)
1967                 return ret;
1968
1969         /*
1970          * BIT31:  1 - Fine grained DPM, 0 - Dicrete DPM
1971          * now, we un-support it
1972          */
1973         *is_fine_grained_dpm = value & 0x80000000;
1974
1975         return 0;
1976 }
1977
1978 int smu_v13_0_set_single_dpm_table(struct smu_context *smu,
1979                                    enum smu_clk_type clk_type,
1980                                    struct smu_13_0_dpm_table *single_dpm_table)
1981 {
1982         int ret = 0;
1983         uint32_t clk;
1984         int i;
1985
1986         ret = smu_v13_0_get_dpm_level_count(smu,
1987                                             clk_type,
1988                                             &single_dpm_table->count);
1989         if (ret) {
1990                 dev_err(smu->adev->dev, "[%s] failed to get dpm levels!\n", __func__);
1991                 return ret;
1992         }
1993
1994         if (smu->adev->ip_versions[MP1_HWIP][0] != IP_VERSION(13, 0, 2)) {
1995                 ret = smu_v13_0_get_fine_grained_status(smu,
1996                                                         clk_type,
1997                                                         &single_dpm_table->is_fine_grained);
1998                 if (ret) {
1999                         dev_err(smu->adev->dev, "[%s] failed to get fine grained status!\n", __func__);
2000                         return ret;
2001                 }
2002         }
2003
2004         for (i = 0; i < single_dpm_table->count; i++) {
2005                 ret = smu_v13_0_get_dpm_freq_by_index(smu,
2006                                                       clk_type,
2007                                                       i,
2008                                                       &clk);
2009                 if (ret) {
2010                         dev_err(smu->adev->dev, "[%s] failed to get dpm freq by index!\n", __func__);
2011                         return ret;
2012                 }
2013
2014                 single_dpm_table->dpm_levels[i].value = clk;
2015                 single_dpm_table->dpm_levels[i].enabled = true;
2016
2017                 if (i == 0)
2018                         single_dpm_table->min = clk;
2019                 else if (i == single_dpm_table->count - 1)
2020                         single_dpm_table->max = clk;
2021         }
2022
2023         return 0;
2024 }
2025
2026 int smu_v13_0_get_current_pcie_link_width_level(struct smu_context *smu)
2027 {
2028         struct amdgpu_device *adev = smu->adev;
2029
2030         return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
2031                 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
2032                 >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
2033 }
2034
2035 int smu_v13_0_get_current_pcie_link_width(struct smu_context *smu)
2036 {
2037         uint32_t width_level;
2038
2039         width_level = smu_v13_0_get_current_pcie_link_width_level(smu);
2040         if (width_level > LINK_WIDTH_MAX)
2041                 width_level = 0;
2042
2043         return link_width[width_level];
2044 }
2045
2046 int smu_v13_0_get_current_pcie_link_speed_level(struct smu_context *smu)
2047 {
2048         struct amdgpu_device *adev = smu->adev;
2049
2050         return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
2051                 PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
2052                 >> PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
2053 }
2054
2055 int smu_v13_0_get_current_pcie_link_speed(struct smu_context *smu)
2056 {
2057         uint32_t speed_level;
2058
2059         speed_level = smu_v13_0_get_current_pcie_link_speed_level(smu);
2060         if (speed_level > LINK_SPEED_MAX)
2061                 speed_level = 0;
2062
2063         return link_speed[speed_level];
2064 }
2065
2066 int smu_v13_0_set_vcn_enable(struct smu_context *smu,
2067                              bool enable)
2068 {
2069         struct amdgpu_device *adev = smu->adev;
2070         int i, ret = 0;
2071
2072         for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
2073                 if (adev->vcn.harvest_config & (1 << i))
2074                         continue;
2075
2076                 ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
2077                                                       SMU_MSG_PowerUpVcn : SMU_MSG_PowerDownVcn,
2078                                                       i << 16U, NULL);
2079                 if (ret)
2080                         return ret;
2081         }
2082
2083         return ret;
2084 }
2085
2086 int smu_v13_0_set_jpeg_enable(struct smu_context *smu,
2087                               bool enable)
2088 {
2089         return smu_cmn_send_smc_msg_with_param(smu, enable ?
2090                                                SMU_MSG_PowerUpJpeg : SMU_MSG_PowerDownJpeg,
2091                                                0, NULL);
2092 }
2093
2094 int smu_v13_0_run_btc(struct smu_context *smu)
2095 {
2096         int res;
2097
2098         res = smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
2099         if (res)
2100                 dev_err(smu->adev->dev, "RunDcBtc failed!\n");
2101
2102         return res;
2103 }
2104
2105 int smu_v13_0_gpo_control(struct smu_context *smu,
2106                           bool enablement)
2107 {
2108         int res;
2109
2110         res = smu_cmn_send_smc_msg_with_param(smu,
2111                                               SMU_MSG_AllowGpo,
2112                                               enablement ? 1 : 0,
2113                                               NULL);
2114         if (res)
2115                 dev_err(smu->adev->dev, "SetGpoAllow %d failed!\n", enablement);
2116
2117         return res;
2118 }
2119
2120 int smu_v13_0_deep_sleep_control(struct smu_context *smu,
2121                                  bool enablement)
2122 {
2123         struct amdgpu_device *adev = smu->adev;
2124         int ret = 0;
2125
2126         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_GFXCLK_BIT)) {
2127                 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_GFXCLK_BIT, enablement);
2128                 if (ret) {
2129                         dev_err(adev->dev, "Failed to %s GFXCLK DS!\n", enablement ? "enable" : "disable");
2130                         return ret;
2131                 }
2132         }
2133
2134         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_UCLK_BIT)) {
2135                 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_UCLK_BIT, enablement);
2136                 if (ret) {
2137                         dev_err(adev->dev, "Failed to %s UCLK DS!\n", enablement ? "enable" : "disable");
2138                         return ret;
2139                 }
2140         }
2141
2142         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_FCLK_BIT)) {
2143                 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_FCLK_BIT, enablement);
2144                 if (ret) {
2145                         dev_err(adev->dev, "Failed to %s FCLK DS!\n", enablement ? "enable" : "disable");
2146                         return ret;
2147                 }
2148         }
2149
2150         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_SOCCLK_BIT)) {
2151                 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_SOCCLK_BIT, enablement);
2152                 if (ret) {
2153                         dev_err(adev->dev, "Failed to %s SOCCLK DS!\n", enablement ? "enable" : "disable");
2154                         return ret;
2155                 }
2156         }
2157
2158         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_LCLK_BIT)) {
2159                 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_LCLK_BIT, enablement);
2160                 if (ret) {
2161                         dev_err(adev->dev, "Failed to %s LCLK DS!\n", enablement ? "enable" : "disable");
2162                         return ret;
2163                 }
2164         }
2165
2166         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_VCN_BIT)) {
2167                 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_VCN_BIT, enablement);
2168                 if (ret) {
2169                         dev_err(adev->dev, "Failed to %s VCN DS!\n", enablement ? "enable" : "disable");
2170                         return ret;
2171                 }
2172         }
2173
2174         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_MP0CLK_BIT)) {
2175                 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_MP0CLK_BIT, enablement);
2176                 if (ret) {
2177                         dev_err(adev->dev, "Failed to %s MP0/MPIOCLK DS!\n", enablement ? "enable" : "disable");
2178                         return ret;
2179                 }
2180         }
2181
2182         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_MP1CLK_BIT)) {
2183                 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_MP1CLK_BIT, enablement);
2184                 if (ret) {
2185                         dev_err(adev->dev, "Failed to %s MP1CLK DS!\n", enablement ? "enable" : "disable");
2186                         return ret;
2187                 }
2188         }
2189
2190         return ret;
2191 }
2192
2193 int smu_v13_0_gfx_ulv_control(struct smu_context *smu,
2194                               bool enablement)
2195 {
2196         int ret = 0;
2197
2198         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_GFX_ULV_BIT))
2199                 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_GFX_ULV_BIT, enablement);
2200
2201         return ret;
2202 }
2203
2204 int smu_v13_0_baco_set_armd3_sequence(struct smu_context *smu,
2205                                       enum smu_baco_seq baco_seq)
2206 {
2207         struct smu_baco_context *smu_baco = &smu->smu_baco;
2208         int ret;
2209
2210         ret = smu_cmn_send_smc_msg_with_param(smu,
2211                                               SMU_MSG_ArmD3,
2212                                               baco_seq,
2213                                               NULL);
2214         if (ret)
2215                 return ret;
2216
2217         if (baco_seq == BACO_SEQ_BAMACO ||
2218             baco_seq == BACO_SEQ_BACO)
2219                 smu_baco->state = SMU_BACO_STATE_ENTER;
2220         else
2221                 smu_baco->state = SMU_BACO_STATE_EXIT;
2222
2223         return 0;
2224 }
2225
2226 bool smu_v13_0_baco_is_support(struct smu_context *smu)
2227 {
2228         struct smu_baco_context *smu_baco = &smu->smu_baco;
2229
2230         if (amdgpu_sriov_vf(smu->adev) ||
2231             !smu_baco->platform_support)
2232                 return false;
2233
2234         /* return true if ASIC is in BACO state already */
2235         if (smu_v13_0_baco_get_state(smu) == SMU_BACO_STATE_ENTER)
2236                 return true;
2237
2238         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_BACO_BIT) &&
2239             !smu_cmn_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT))
2240                 return false;
2241
2242         return true;
2243 }
2244
2245 enum smu_baco_state smu_v13_0_baco_get_state(struct smu_context *smu)
2246 {
2247         struct smu_baco_context *smu_baco = &smu->smu_baco;
2248
2249         return smu_baco->state;
2250 }
2251
2252 int smu_v13_0_baco_set_state(struct smu_context *smu,
2253                              enum smu_baco_state state)
2254 {
2255         struct smu_baco_context *smu_baco = &smu->smu_baco;
2256         struct amdgpu_device *adev = smu->adev;
2257         int ret = 0;
2258
2259         if (smu_v13_0_baco_get_state(smu) == state)
2260                 return 0;
2261
2262         if (state == SMU_BACO_STATE_ENTER) {
2263                 ret = smu_cmn_send_smc_msg_with_param(smu,
2264                                                       SMU_MSG_EnterBaco,
2265                                                       (smu_baco->maco_support && amdgpu_runtime_pm != 1) ?
2266                                                       BACO_SEQ_BAMACO : BACO_SEQ_BACO,
2267                                                       NULL);
2268         } else {
2269                 ret = smu_cmn_send_smc_msg(smu,
2270                                            SMU_MSG_ExitBaco,
2271                                            NULL);
2272                 if (ret)
2273                         return ret;
2274
2275                 /* clear vbios scratch 6 and 7 for coming asic reinit */
2276                 WREG32(adev->bios_scratch_reg_offset + 6, 0);
2277                 WREG32(adev->bios_scratch_reg_offset + 7, 0);
2278         }
2279
2280         if (!ret)
2281                 smu_baco->state = state;
2282
2283         return ret;
2284 }
2285
2286 int smu_v13_0_baco_enter(struct smu_context *smu)
2287 {
2288         int ret = 0;
2289
2290         ret = smu_v13_0_baco_set_state(smu,
2291                                        SMU_BACO_STATE_ENTER);
2292         if (ret)
2293                 return ret;
2294
2295         msleep(10);
2296
2297         return ret;
2298 }
2299
2300 int smu_v13_0_baco_exit(struct smu_context *smu)
2301 {
2302         return smu_v13_0_baco_set_state(smu,
2303                                         SMU_BACO_STATE_EXIT);
2304 }
2305
2306 int smu_v13_0_set_gfx_power_up_by_imu(struct smu_context *smu)
2307 {
2308         uint16_t index;
2309
2310         index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG,
2311                                                SMU_MSG_EnableGfxImu);
2312         /* Param 1 to tell PMFW to enable GFXOFF feature */
2313         return smu_cmn_send_msg_without_waiting(smu, index, 1);
2314 }
2315
2316 int smu_v13_0_od_edit_dpm_table(struct smu_context *smu,
2317                                 enum PP_OD_DPM_TABLE_COMMAND type,
2318                                 long input[], uint32_t size)
2319 {
2320         struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
2321         int ret = 0;
2322
2323         /* Only allowed in manual mode */
2324         if (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
2325                 return -EINVAL;
2326
2327         switch (type) {
2328         case PP_OD_EDIT_SCLK_VDDC_TABLE:
2329                 if (size != 2) {
2330                         dev_err(smu->adev->dev, "Input parameter number not correct\n");
2331                         return -EINVAL;
2332                 }
2333
2334                 if (input[0] == 0) {
2335                         if (input[1] < smu->gfx_default_hard_min_freq) {
2336                                 dev_warn(smu->adev->dev,
2337                                          "Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n",
2338                                          input[1], smu->gfx_default_hard_min_freq);
2339                                 return -EINVAL;
2340                         }
2341                         smu->gfx_actual_hard_min_freq = input[1];
2342                 } else if (input[0] == 1) {
2343                         if (input[1] > smu->gfx_default_soft_max_freq) {
2344                                 dev_warn(smu->adev->dev,
2345                                          "Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n",
2346                                          input[1], smu->gfx_default_soft_max_freq);
2347                                 return -EINVAL;
2348                         }
2349                         smu->gfx_actual_soft_max_freq = input[1];
2350                 } else {
2351                         return -EINVAL;
2352                 }
2353                 break;
2354         case PP_OD_RESTORE_DEFAULT_TABLE:
2355                 if (size != 0) {
2356                         dev_err(smu->adev->dev, "Input parameter number not correct\n");
2357                         return -EINVAL;
2358                 }
2359                 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
2360                 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
2361                 break;
2362         case PP_OD_COMMIT_DPM_TABLE:
2363                 if (size != 0) {
2364                         dev_err(smu->adev->dev, "Input parameter number not correct\n");
2365                         return -EINVAL;
2366                 }
2367                 if (smu->gfx_actual_hard_min_freq > smu->gfx_actual_soft_max_freq) {
2368                         dev_err(smu->adev->dev,
2369                                 "The setting minimum sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n",
2370                                 smu->gfx_actual_hard_min_freq,
2371                                 smu->gfx_actual_soft_max_freq);
2372                         return -EINVAL;
2373                 }
2374
2375                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk,
2376                                                       smu->gfx_actual_hard_min_freq,
2377                                                       NULL);
2378                 if (ret) {
2379                         dev_err(smu->adev->dev, "Set hard min sclk failed!");
2380                         return ret;
2381                 }
2382
2383                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
2384                                                       smu->gfx_actual_soft_max_freq,
2385                                                       NULL);
2386                 if (ret) {
2387                         dev_err(smu->adev->dev, "Set soft max sclk failed!");
2388                         return ret;
2389                 }
2390                 break;
2391         default:
2392                 return -ENOSYS;
2393         }
2394
2395         return ret;
2396 }
2397
2398 int smu_v13_0_set_default_dpm_tables(struct smu_context *smu)
2399 {
2400         struct smu_table_context *smu_table = &smu->smu_table;
2401
2402         return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0,
2403                                     smu_table->clocks_table, false);
2404 }
2405
2406 void smu_v13_0_set_smu_mailbox_registers(struct smu_context *smu)
2407 {
2408         struct amdgpu_device *adev = smu->adev;
2409
2410         smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82);
2411         smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66);
2412         smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
2413 }
2414
2415 int smu_v13_0_mode1_reset(struct smu_context *smu)
2416 {
2417         int ret = 0;
2418
2419         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_Mode1Reset, NULL);
2420         if (!ret)
2421                 msleep(SMU13_MODE1_RESET_WAIT_TIME_IN_MS);
2422
2423         return ret;
2424 }
2425
2426 int smu_v13_0_update_pcie_parameters(struct smu_context *smu,
2427                                      uint32_t pcie_gen_cap,
2428                                      uint32_t pcie_width_cap)
2429 {
2430         struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
2431         struct smu_13_0_pcie_table *pcie_table =
2432                                 &dpm_context->dpm_tables.pcie_table;
2433         int num_of_levels = pcie_table->num_of_link_levels;
2434         uint32_t smu_pcie_arg;
2435         int ret, i;
2436
2437         if (!amdgpu_device_pcie_dynamic_switching_supported()) {
2438                 if (pcie_table->pcie_gen[num_of_levels - 1] < pcie_gen_cap)
2439                         pcie_gen_cap = pcie_table->pcie_gen[num_of_levels - 1];
2440
2441                 if (pcie_table->pcie_lane[num_of_levels - 1] < pcie_width_cap)
2442                         pcie_width_cap = pcie_table->pcie_lane[num_of_levels - 1];
2443
2444                 /* Force all levels to use the same settings */
2445                 for (i = 0; i < num_of_levels; i++) {
2446                         pcie_table->pcie_gen[i] = pcie_gen_cap;
2447                         pcie_table->pcie_lane[i] = pcie_width_cap;
2448                 }
2449         } else {
2450                 for (i = 0; i < num_of_levels; i++) {
2451                         if (pcie_table->pcie_gen[i] > pcie_gen_cap)
2452                                 pcie_table->pcie_gen[i] = pcie_gen_cap;
2453                         if (pcie_table->pcie_lane[i] > pcie_width_cap)
2454                                 pcie_table->pcie_lane[i] = pcie_width_cap;
2455                 }
2456         }
2457
2458         for (i = 0; i < num_of_levels; i++) {
2459                 smu_pcie_arg = i << 16;
2460                 smu_pcie_arg |= pcie_table->pcie_gen[i] << 8;
2461                 smu_pcie_arg |= pcie_table->pcie_lane[i];
2462
2463                 ret = smu_cmn_send_smc_msg_with_param(smu,
2464                                                       SMU_MSG_OverridePcieParameters,
2465                                                       smu_pcie_arg,
2466                                                       NULL);
2467                 if (ret)
2468                         return ret;
2469         }
2470
2471         return 0;
2472 }