drivers/gpu/drm/amd/powerplay/arcturus_ppt.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include "amdgpu.h"
  26 #include "amdgpu_smu.h"
  27 #include "smu_internal.h"
  28 #include "atomfirmware.h"
  29 #include "amdgpu_atomfirmware.h"
  30 #include "smu_v11_0.h"
  31 #include "smu11_driver_if_arcturus.h"
  32 #include "soc15_common.h"
  33 #include "atom.h"
  34 #include "power_state.h"
  35 #include "arcturus_ppt.h"
  36 #include "smu_v11_0_pptable.h"
  37 #include "arcturus_ppsmc.h"
  38 #include "nbio/nbio_7_4_offset.h"
  39 #include "nbio/nbio_7_4_sh_mask.h"
  40 #include "amdgpu_xgmi.h"
  41 #include <linux/i2c.h>
  42 #include <linux/pci.h>
  43 #include "amdgpu_ras.h"
  44
  45 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c))
  46
  47 #define CTF_OFFSET_EDGE                 5
  48 #define CTF_OFFSET_HOTSPOT              5
  49 #define CTF_OFFSET_HBM                  5
  50
  51 #define MSG_MAP(msg, index) \
  52         [SMU_MSG_##msg] = {1, (index)}
  53 #define ARCTURUS_FEA_MAP(smu_feature, arcturus_feature) \
  54         [smu_feature] = {1, (arcturus_feature)}
  55
  56 #define SMU_FEATURES_LOW_MASK        0x00000000FFFFFFFF
  57 #define SMU_FEATURES_LOW_SHIFT       0
  58 #define SMU_FEATURES_HIGH_MASK       0xFFFFFFFF00000000
  59 #define SMU_FEATURES_HIGH_SHIFT      32
  60
  61 #define SMC_DPM_FEATURE ( \
  62         FEATURE_DPM_PREFETCHER_MASK | \
  63         FEATURE_DPM_GFXCLK_MASK | \
  64         FEATURE_DPM_UCLK_MASK | \
  65         FEATURE_DPM_SOCCLK_MASK | \
  66         FEATURE_DPM_MP0CLK_MASK | \
  67         FEATURE_DPM_FCLK_MASK | \
  68         FEATURE_DPM_XGMI_MASK)
  69
  70 /* possible frequency drift (1Mhz) */
  71 #define EPSILON                         1
  72
  73 static struct smu_11_0_cmn2aisc_mapping arcturus_message_map[SMU_MSG_MAX_COUNT] = {
  74         MSG_MAP(TestMessage,                         PPSMC_MSG_TestMessage),
  75         MSG_MAP(GetSmuVersion,                       PPSMC_MSG_GetSmuVersion),
  76         MSG_MAP(GetDriverIfVersion,                  PPSMC_MSG_GetDriverIfVersion),
  77         MSG_MAP(SetAllowedFeaturesMaskLow,           PPSMC_MSG_SetAllowedFeaturesMaskLow),
  78         MSG_MAP(SetAllowedFeaturesMaskHigh,          PPSMC_MSG_SetAllowedFeaturesMaskHigh),
  79         MSG_MAP(EnableAllSmuFeatures,                PPSMC_MSG_EnableAllSmuFeatures),
  80         MSG_MAP(DisableAllSmuFeatures,               PPSMC_MSG_DisableAllSmuFeatures),
  81         MSG_MAP(EnableSmuFeaturesLow,                PPSMC_MSG_EnableSmuFeaturesLow),
  82         MSG_MAP(EnableSmuFeaturesHigh,               PPSMC_MSG_EnableSmuFeaturesHigh),
  83         MSG_MAP(DisableSmuFeaturesLow,               PPSMC_MSG_DisableSmuFeaturesLow),
  84         MSG_MAP(DisableSmuFeaturesHigh,              PPSMC_MSG_DisableSmuFeaturesHigh),
  85         MSG_MAP(GetEnabledSmuFeaturesLow,            PPSMC_MSG_GetEnabledSmuFeaturesLow),
  86         MSG_MAP(GetEnabledSmuFeaturesHigh,           PPSMC_MSG_GetEnabledSmuFeaturesHigh),
  87         MSG_MAP(SetDriverDramAddrHigh,               PPSMC_MSG_SetDriverDramAddrHigh),
  88         MSG_MAP(SetDriverDramAddrLow,                PPSMC_MSG_SetDriverDramAddrLow),
  89         MSG_MAP(SetToolsDramAddrHigh,                PPSMC_MSG_SetToolsDramAddrHigh),
  90         MSG_MAP(SetToolsDramAddrLow,                 PPSMC_MSG_SetToolsDramAddrLow),
  91         MSG_MAP(TransferTableSmu2Dram,               PPSMC_MSG_TransferTableSmu2Dram),
  92         MSG_MAP(TransferTableDram2Smu,               PPSMC_MSG_TransferTableDram2Smu),
  93         MSG_MAP(UseDefaultPPTable,                   PPSMC_MSG_UseDefaultPPTable),
  94         MSG_MAP(UseBackupPPTable,                    PPSMC_MSG_UseBackupPPTable),
  95         MSG_MAP(SetSystemVirtualDramAddrHigh,        PPSMC_MSG_SetSystemVirtualDramAddrHigh),
  96         MSG_MAP(SetSystemVirtualDramAddrLow,         PPSMC_MSG_SetSystemVirtualDramAddrLow),
  97         MSG_MAP(EnterBaco,                           PPSMC_MSG_EnterBaco),
  98         MSG_MAP(ExitBaco,                            PPSMC_MSG_ExitBaco),
  99         MSG_MAP(ArmD3,                               PPSMC_MSG_ArmD3),
 100         MSG_MAP(SetSoftMinByFreq,                    PPSMC_MSG_SetSoftMinByFreq),
 101         MSG_MAP(SetSoftMaxByFreq,                    PPSMC_MSG_SetSoftMaxByFreq),
 102         MSG_MAP(SetHardMinByFreq,                    PPSMC_MSG_SetHardMinByFreq),
 103         MSG_MAP(SetHardMaxByFreq,                    PPSMC_MSG_SetHardMaxByFreq),
 104         MSG_MAP(GetMinDpmFreq,                       PPSMC_MSG_GetMinDpmFreq),
 105         MSG_MAP(GetMaxDpmFreq,                       PPSMC_MSG_GetMaxDpmFreq),
 106         MSG_MAP(GetDpmFreqByIndex,                   PPSMC_MSG_GetDpmFreqByIndex),
 107         MSG_MAP(SetWorkloadMask,                     PPSMC_MSG_SetWorkloadMask),
 108         MSG_MAP(SetDfSwitchType,                     PPSMC_MSG_SetDfSwitchType),
 109         MSG_MAP(GetVoltageByDpm,                     PPSMC_MSG_GetVoltageByDpm),
 110         MSG_MAP(GetVoltageByDpmOverdrive,            PPSMC_MSG_GetVoltageByDpmOverdrive),
 111         MSG_MAP(SetPptLimit,                         PPSMC_MSG_SetPptLimit),
 112         MSG_MAP(GetPptLimit,                         PPSMC_MSG_GetPptLimit),
 113         MSG_MAP(PowerUpVcn0,                         PPSMC_MSG_PowerUpVcn0),
 114         MSG_MAP(PowerDownVcn0,                       PPSMC_MSG_PowerDownVcn0),
 115         MSG_MAP(PowerUpVcn1,                         PPSMC_MSG_PowerUpVcn1),
 116         MSG_MAP(PowerDownVcn1,                       PPSMC_MSG_PowerDownVcn1),
 117         MSG_MAP(PrepareMp1ForUnload,                 PPSMC_MSG_PrepareMp1ForUnload),
 118         MSG_MAP(PrepareMp1ForReset,                  PPSMC_MSG_PrepareMp1ForReset),
 119         MSG_MAP(PrepareMp1ForShutdown,               PPSMC_MSG_PrepareMp1ForShutdown),
 120         MSG_MAP(SoftReset,                           PPSMC_MSG_SoftReset),
 121         MSG_MAP(RunAfllBtc,                          PPSMC_MSG_RunAfllBtc),
 122         MSG_MAP(RunDcBtc,                            PPSMC_MSG_RunDcBtc),
 123         MSG_MAP(DramLogSetDramAddrHigh,              PPSMC_MSG_DramLogSetDramAddrHigh),
 124         MSG_MAP(DramLogSetDramAddrLow,               PPSMC_MSG_DramLogSetDramAddrLow),
 125         MSG_MAP(DramLogSetDramSize,                  PPSMC_MSG_DramLogSetDramSize),
 126         MSG_MAP(GetDebugData,                        PPSMC_MSG_GetDebugData),
 127         MSG_MAP(WaflTest,                            PPSMC_MSG_WaflTest),
 128         MSG_MAP(SetXgmiMode,                         PPSMC_MSG_SetXgmiMode),
 129         MSG_MAP(SetMemoryChannelEnable,              PPSMC_MSG_SetMemoryChannelEnable),
 130         MSG_MAP(DFCstateControl,                     PPSMC_MSG_DFCstateControl),
 131 };
 132
 133 static struct smu_11_0_cmn2aisc_mapping arcturus_clk_map[SMU_CLK_COUNT] = {
 134         CLK_MAP(GFXCLK, PPCLK_GFXCLK),
 135         CLK_MAP(SCLK,   PPCLK_GFXCLK),
 136         CLK_MAP(SOCCLK, PPCLK_SOCCLK),
 137         CLK_MAP(FCLK, PPCLK_FCLK),
 138         CLK_MAP(UCLK, PPCLK_UCLK),
 139         CLK_MAP(MCLK, PPCLK_UCLK),
 140         CLK_MAP(DCLK, PPCLK_DCLK),
 141         CLK_MAP(VCLK, PPCLK_VCLK),
 142 };
 143
 144 static struct smu_11_0_cmn2aisc_mapping arcturus_feature_mask_map[SMU_FEATURE_COUNT] = {
 145         FEA_MAP(DPM_PREFETCHER),
 146         FEA_MAP(DPM_GFXCLK),
 147         FEA_MAP(DPM_UCLK),
 148         FEA_MAP(DPM_SOCCLK),
 149         FEA_MAP(DPM_FCLK),
 150         FEA_MAP(DPM_MP0CLK),
 151         ARCTURUS_FEA_MAP(SMU_FEATURE_XGMI_BIT, FEATURE_DPM_XGMI_BIT),
 152         FEA_MAP(DS_GFXCLK),
 153         FEA_MAP(DS_SOCCLK),
 154         FEA_MAP(DS_LCLK),
 155         FEA_MAP(DS_FCLK),
 156         FEA_MAP(DS_UCLK),
 157         FEA_MAP(GFX_ULV),
 158         ARCTURUS_FEA_MAP(SMU_FEATURE_VCN_PG_BIT, FEATURE_DPM_VCN_BIT),
 159         FEA_MAP(RSMU_SMN_CG),
 160         FEA_MAP(WAFL_CG),
 161         FEA_MAP(PPT),
 162         FEA_MAP(TDC),
 163         FEA_MAP(APCC_PLUS),
 164         FEA_MAP(VR0HOT),
 165         FEA_MAP(VR1HOT),
 166         FEA_MAP(FW_CTF),
 167         FEA_MAP(FAN_CONTROL),
 168         FEA_MAP(THERMAL),
 169         FEA_MAP(OUT_OF_BAND_MONITOR),
 170         FEA_MAP(TEMP_DEPENDENT_VMIN),
 171 };
 172
 173 static struct smu_11_0_cmn2aisc_mapping arcturus_table_map[SMU_TABLE_COUNT] = {
 174         TAB_MAP(PPTABLE),
 175         TAB_MAP(AVFS),
 176         TAB_MAP(AVFS_PSM_DEBUG),
 177         TAB_MAP(AVFS_FUSE_OVERRIDE),
 178         TAB_MAP(PMSTATUSLOG),
 179         TAB_MAP(SMU_METRICS),
 180         TAB_MAP(DRIVER_SMU_CONFIG),
 181         TAB_MAP(OVERDRIVE),
 182         TAB_MAP(I2C_COMMANDS),
 183         TAB_MAP(ACTIVITY_MONITOR_COEFF),
 184 };
 185
 186 static struct smu_11_0_cmn2aisc_mapping arcturus_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
 187         PWR_MAP(AC),
 188         PWR_MAP(DC),
 189 };
 190
 191 static struct smu_11_0_cmn2aisc_mapping arcturus_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
 192         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT,       WORKLOAD_PPLIB_DEFAULT_BIT),
 193         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING,          WORKLOAD_PPLIB_POWER_SAVING_BIT),
 194         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO,                WORKLOAD_PPLIB_VIDEO_BIT),
 195         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE,              WORKLOAD_PPLIB_COMPUTE_BIT),
 196         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,               WORKLOAD_PPLIB_CUSTOM_BIT),
 197 };
 198
 199 static int arcturus_get_smu_msg_index(struct smu_context *smc, uint32_t index)
 200 {
 201         struct smu_11_0_cmn2aisc_mapping mapping;
 202
 203         if (index >= SMU_MSG_MAX_COUNT)
 204                 return -EINVAL;
 205
 206         mapping = arcturus_message_map[index];
 207         if (!(mapping.valid_mapping))
 208                 return -EINVAL;
 209
 210         return mapping.map_to;
 211 }
 212
 213 static int arcturus_get_smu_clk_index(struct smu_context *smc, uint32_t index)
 214 {
 215         struct smu_11_0_cmn2aisc_mapping mapping;
 216
 217         if (index >= SMU_CLK_COUNT)
 218                 return -EINVAL;
 219
 220         mapping = arcturus_clk_map[index];
 221         if (!(mapping.valid_mapping)) {
 222                 pr_warn("Unsupported SMU clk: %d\n", index);
 223                 return -EINVAL;
 224         }
 225
 226         return mapping.map_to;
 227 }
 228
 229 static int arcturus_get_smu_feature_index(struct smu_context *smc, uint32_t index)
 230 {
 231         struct smu_11_0_cmn2aisc_mapping mapping;
 232
 233         if (index >= SMU_FEATURE_COUNT)
 234                 return -EINVAL;
 235
 236         mapping = arcturus_feature_mask_map[index];
 237         if (!(mapping.valid_mapping)) {
 238                 return -EINVAL;
 239         }
 240
 241         return mapping.map_to;
 242 }
 243
 244 static int arcturus_get_smu_table_index(struct smu_context *smc, uint32_t index)
 245 {
 246         struct smu_11_0_cmn2aisc_mapping mapping;
 247
 248         if (index >= SMU_TABLE_COUNT)
 249                 return -EINVAL;
 250
 251         mapping = arcturus_table_map[index];
 252         if (!(mapping.valid_mapping)) {
 253                 pr_warn("Unsupported SMU table: %d\n", index);
 254                 return -EINVAL;
 255         }
 256
 257         return mapping.map_to;
 258 }
 259
 260 static int arcturus_get_pwr_src_index(struct smu_context *smc, uint32_t index)
 261 {
 262         struct smu_11_0_cmn2aisc_mapping mapping;
 263
 264         if (index >= SMU_POWER_SOURCE_COUNT)
 265                 return -EINVAL;
 266
 267         mapping = arcturus_pwr_src_map[index];
 268         if (!(mapping.valid_mapping)) {
 269                 pr_warn("Unsupported SMU power source: %d\n", index);
 270                 return -EINVAL;
 271         }
 272
 273         return mapping.map_to;
 274 }
 275
 276
 277 static int arcturus_get_workload_type(struct smu_context *smu, enum PP_SMC_POWER_PROFILE profile)
 278 {
 279         struct smu_11_0_cmn2aisc_mapping mapping;
 280
 281         if (profile > PP_SMC_POWER_PROFILE_CUSTOM)
 282                 return -EINVAL;
 283
 284         mapping = arcturus_workload_map[profile];
 285         if (!(mapping.valid_mapping))
 286                 return -EINVAL;
 287
 288         return mapping.map_to;
 289 }
 290
 291 static int arcturus_tables_init(struct smu_context *smu, struct smu_table *tables)
 292 {
 293         struct smu_table_context *smu_table = &smu->smu_table;
 294
 295         SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
 296                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 297
 298         SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
 299                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 300
 301         SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
 302                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 303
 304         SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
 305                                PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 306
 307         SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
 308                        sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE,
 309                        AMDGPU_GEM_DOMAIN_VRAM);
 310
 311         smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
 312         if (!smu_table->metrics_table)
 313                 return -ENOMEM;
 314         smu_table->metrics_time = 0;
 315
 316         return 0;
 317 }
 318
 319 static int arcturus_allocate_dpm_context(struct smu_context *smu)
 320 {
 321         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 322
 323         if (smu_dpm->dpm_context)
 324                 return -EINVAL;
 325
 326         smu_dpm->dpm_context = kzalloc(sizeof(struct arcturus_dpm_table),
 327                                        GFP_KERNEL);
 328         if (!smu_dpm->dpm_context)
 329                 return -ENOMEM;
 330
 331         if (smu_dpm->golden_dpm_context)
 332                 return -EINVAL;
 333
 334         smu_dpm->golden_dpm_context = kzalloc(sizeof(struct arcturus_dpm_table),
 335                                               GFP_KERNEL);
 336         if (!smu_dpm->golden_dpm_context)
 337                 return -ENOMEM;
 338
 339         smu_dpm->dpm_context_size = sizeof(struct arcturus_dpm_table);
 340
 341         smu_dpm->dpm_current_power_state = kzalloc(sizeof(struct smu_power_state),
 342                                        GFP_KERNEL);
 343         if (!smu_dpm->dpm_current_power_state)
 344                 return -ENOMEM;
 345
 346         smu_dpm->dpm_request_power_state = kzalloc(sizeof(struct smu_power_state),
 347                                        GFP_KERNEL);
 348         if (!smu_dpm->dpm_request_power_state)
 349                 return -ENOMEM;
 350
 351         return 0;
 352 }
 353
 354 static int
 355 arcturus_get_allowed_feature_mask(struct smu_context *smu,
 356                                   uint32_t *feature_mask, uint32_t num)
 357 {
 358         if (num > 2)
 359                 return -EINVAL;
 360
 361         /* pptable will handle the features to enable */
 362         memset(feature_mask, 0xFF, sizeof(uint32_t) * num);
 363
 364         return 0;
 365 }
 366
 367 static int
 368 arcturus_set_single_dpm_table(struct smu_context *smu,
 369                             struct arcturus_single_dpm_table *single_dpm_table,
 370                             PPCLK_e clk_id)
 371 {
 372         int ret = 0;
 373         uint32_t i, num_of_levels = 0, clk;
 374
 375         ret = smu_send_smc_msg_with_param(smu,
 376                         SMU_MSG_GetDpmFreqByIndex,
 377                         (clk_id << 16 | 0xFF),
 378                         &num_of_levels);
 379         if (ret) {
 380                 pr_err("[%s] failed to get dpm levels!\n", __func__);
 381                 return ret;
 382         }
 383
 384         if (!num_of_levels) {
 385                 pr_err("[%s] number of clk levels is invalid!\n", __func__);
 386                 return -EINVAL;
 387         }
 388
 389         single_dpm_table->count = num_of_levels;
 390         for (i = 0; i < num_of_levels; i++) {
 391                 ret = smu_send_smc_msg_with_param(smu,
 392                                 SMU_MSG_GetDpmFreqByIndex,
 393                                 (clk_id << 16 | i),
 394                                 &clk);
 395                 if (ret) {
 396                         pr_err("[%s] failed to get dpm freq by index!\n", __func__);
 397                         return ret;
 398                 }
 399                 if (!clk) {
 400                         pr_err("[%s] clk value is invalid!\n", __func__);
 401                         return -EINVAL;
 402                 }
 403                 single_dpm_table->dpm_levels[i].value = clk;
 404                 single_dpm_table->dpm_levels[i].enabled = true;
 405         }
 406         return 0;
 407 }
 408
 409 static void arcturus_init_single_dpm_state(struct arcturus_dpm_state *dpm_state)
 410 {
 411         dpm_state->soft_min_level = 0x0;
 412         dpm_state->soft_max_level = 0xffff;
 413         dpm_state->hard_min_level = 0x0;
 414         dpm_state->hard_max_level = 0xffff;
 415 }
 416
 417 static int arcturus_set_default_dpm_table(struct smu_context *smu)
 418 {
 419         int ret;
 420
 421         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 422         struct arcturus_dpm_table *dpm_table = NULL;
 423         struct arcturus_single_dpm_table *single_dpm_table;
 424
 425         dpm_table = smu_dpm->dpm_context;
 426
 427         /* socclk */
 428         single_dpm_table = &(dpm_table->soc_table);
 429         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
 430                 ret = arcturus_set_single_dpm_table(smu, single_dpm_table,
 431                                                   PPCLK_SOCCLK);
 432                 if (ret) {
 433                         pr_err("[%s] failed to get socclk dpm levels!\n", __func__);
 434                         return ret;
 435                 }
 436         } else {
 437                 single_dpm_table->count = 1;
 438                 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
 439         }
 440         arcturus_init_single_dpm_state(&(single_dpm_table->dpm_state));
 441
 442         /* gfxclk */
 443         single_dpm_table = &(dpm_table->gfx_table);
 444         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
 445                 ret = arcturus_set_single_dpm_table(smu, single_dpm_table,
 446                                                   PPCLK_GFXCLK);
 447                 if (ret) {
 448                         pr_err("[SetupDefaultDpmTable] failed to get gfxclk dpm levels!");
 449                         return ret;
 450                 }
 451         } else {
 452                 single_dpm_table->count = 1;
 453                 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
 454         }
 455         arcturus_init_single_dpm_state(&(single_dpm_table->dpm_state));
 456
 457         /* memclk */
 458         single_dpm_table = &(dpm_table->mem_table);
 459         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 460                 ret = arcturus_set_single_dpm_table(smu, single_dpm_table,
 461                                                   PPCLK_UCLK);
 462                 if (ret) {
 463                         pr_err("[SetupDefaultDpmTable] failed to get memclk dpm levels!");
 464                         return ret;
 465                 }
 466         } else {
 467                 single_dpm_table->count = 1;
 468                 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
 469         }
 470         arcturus_init_single_dpm_state(&(single_dpm_table->dpm_state));
 471
 472         /* fclk */
 473         single_dpm_table = &(dpm_table->fclk_table);
 474         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
 475                 ret = arcturus_set_single_dpm_table(smu, single_dpm_table,
 476                                                   PPCLK_FCLK);
 477                 if (ret) {
 478                         pr_err("[SetupDefaultDpmTable] failed to get fclk dpm levels!");
 479                         return ret;
 480                 }
 481         } else {
 482                 single_dpm_table->count = 1;
 483                 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
 484         }
 485         arcturus_init_single_dpm_state(&(single_dpm_table->dpm_state));
 486
 487         memcpy(smu_dpm->golden_dpm_context, dpm_table,
 488                sizeof(struct arcturus_dpm_table));
 489
 490         return 0;
 491 }
 492
 493 static int arcturus_check_powerplay_table(struct smu_context *smu)
 494 {
 495         return 0;
 496 }
 497
 498 static int arcturus_store_powerplay_table(struct smu_context *smu)
 499 {
 500         struct smu_11_0_powerplay_table *powerplay_table = NULL;
 501         struct smu_table_context *table_context = &smu->smu_table;
 502         struct smu_baco_context *smu_baco = &smu->smu_baco;
 503         int ret = 0;
 504
 505         if (!table_context->power_play_table)
 506                 return -EINVAL;
 507
 508         powerplay_table = table_context->power_play_table;
 509
 510         memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
 511                sizeof(PPTable_t));
 512
 513         table_context->thermal_controller_type = powerplay_table->thermal_controller_type;
 514
 515         mutex_lock(&smu_baco->mutex);
 516         if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_BACO ||
 517             powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO)
 518                 smu_baco->platform_support = true;
 519         mutex_unlock(&smu_baco->mutex);
 520
 521         return ret;
 522 }
 523
 524 static int arcturus_append_powerplay_table(struct smu_context *smu)
 525 {
 526         struct smu_table_context *table_context = &smu->smu_table;
 527         PPTable_t *smc_pptable = table_context->driver_pptable;
 528         struct atom_smc_dpm_info_v4_6 *smc_dpm_table;
 529         int index, ret;
 530
 531         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 532                                            smc_dpm_info);
 533
 534         ret = smu_get_atom_data_table(smu, index, NULL, NULL, NULL,
 535                                       (uint8_t **)&smc_dpm_table);
 536         if (ret)
 537                 return ret;
 538
 539         pr_info("smc_dpm_info table revision(format.content): %d.%d\n",
 540                         smc_dpm_table->table_header.format_revision,
 541                         smc_dpm_table->table_header.content_revision);
 542
 543         if ((smc_dpm_table->table_header.format_revision == 4) &&
 544             (smc_dpm_table->table_header.content_revision == 6))
 545                 memcpy(&smc_pptable->MaxVoltageStepGfx,
 546                        &smc_dpm_table->maxvoltagestepgfx,
 547                        sizeof(*smc_dpm_table) - offsetof(struct atom_smc_dpm_info_v4_6, maxvoltagestepgfx));
 548
 549         return 0;
 550 }
 551
 552 static int arcturus_run_btc(struct smu_context *smu)
 553 {
 554         int ret = 0;
 555
 556         ret = smu_send_smc_msg(smu, SMU_MSG_RunAfllBtc, NULL);
 557         if (ret) {
 558                 pr_err("RunAfllBtc failed!\n");
 559                 return ret;
 560         }
 561
 562         return smu_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
 563 }
 564
 565 static int arcturus_populate_umd_state_clk(struct smu_context *smu)
 566 {
 567         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 568         struct arcturus_dpm_table *dpm_table = NULL;
 569         struct arcturus_single_dpm_table *gfx_table = NULL;
 570         struct arcturus_single_dpm_table *mem_table = NULL;
 571
 572         dpm_table = smu_dpm->dpm_context;
 573         gfx_table = &(dpm_table->gfx_table);
 574         mem_table = &(dpm_table->mem_table);
 575
 576         smu->pstate_sclk = gfx_table->dpm_levels[0].value;
 577         smu->pstate_mclk = mem_table->dpm_levels[0].value;
 578
 579         if (gfx_table->count > ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL &&
 580             mem_table->count > ARCTURUS_UMD_PSTATE_MCLK_LEVEL) {
 581                 smu->pstate_sclk = gfx_table->dpm_levels[ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL].value;
 582                 smu->pstate_mclk = mem_table->dpm_levels[ARCTURUS_UMD_PSTATE_MCLK_LEVEL].value;
 583         }
 584
 585         smu->pstate_sclk = smu->pstate_sclk * 100;
 586         smu->pstate_mclk = smu->pstate_mclk * 100;
 587
 588         return 0;
 589 }
 590
 591 static int arcturus_get_clk_table(struct smu_context *smu,
 592                         struct pp_clock_levels_with_latency *clocks,
 593                         struct arcturus_single_dpm_table *dpm_table)
 594 {
 595         int i, count;
 596
 597         count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
 598         clocks->num_levels = count;
 599
 600         for (i = 0; i < count; i++) {
 601                 clocks->data[i].clocks_in_khz =
 602                         dpm_table->dpm_levels[i].value * 1000;
 603                 clocks->data[i].latency_in_us = 0;
 604         }
 605
 606         return 0;
 607 }
 608
 609 static int arcturus_freqs_in_same_level(int32_t frequency1,
 610                                         int32_t frequency2)
 611 {
 612         return (abs(frequency1 - frequency2) <= EPSILON);
 613 }
 614
 615 static int arcturus_print_clk_levels(struct smu_context *smu,
 616                         enum smu_clk_type type, char *buf)
 617 {
 618         int i, now, size = 0;
 619         int ret = 0;
 620         struct pp_clock_levels_with_latency clocks;
 621         struct arcturus_single_dpm_table *single_dpm_table;
 622         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 623         struct arcturus_dpm_table *dpm_table = NULL;
 624
 625         dpm_table = smu_dpm->dpm_context;
 626
 627         switch (type) {
 628         case SMU_SCLK:
 629                 ret = smu_get_current_clk_freq(smu, SMU_GFXCLK, &now);
 630                 if (ret) {
 631                         pr_err("Attempt to get current gfx clk Failed!");
 632                         return ret;
 633                 }
 634
 635                 single_dpm_table = &(dpm_table->gfx_table);
 636                 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
 637                 if (ret) {
 638                         pr_err("Attempt to get gfx clk levels Failed!");
 639                         return ret;
 640                 }
 641
 642                 /*
 643                  * For DPM disabled case, there will be only one clock level.
 644                  * And it's safe to assume that is always the current clock.
 645                  */
 646                 for (i = 0; i < clocks.num_levels; i++)
 647                         size += sprintf(buf + size, "%d: %uMhz %s\n", i,
 648                                         clocks.data[i].clocks_in_khz / 1000,
 649                                         (clocks.num_levels == 1) ? "*" :
 650                                         (arcturus_freqs_in_same_level(
 651                                         clocks.data[i].clocks_in_khz / 1000,
 652                                         now / 100) ? "*" : ""));
 653                 break;
 654
 655         case SMU_MCLK:
 656                 ret = smu_get_current_clk_freq(smu, SMU_UCLK, &now);
 657                 if (ret) {
 658                         pr_err("Attempt to get current mclk Failed!");
 659                         return ret;
 660                 }
 661
 662                 single_dpm_table = &(dpm_table->mem_table);
 663                 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
 664                 if (ret) {
 665                         pr_err("Attempt to get memory clk levels Failed!");
 666                         return ret;
 667                 }
 668
 669                 for (i = 0; i < clocks.num_levels; i++)
 670                         size += sprintf(buf + size, "%d: %uMhz %s\n",
 671                                 i, clocks.data[i].clocks_in_khz / 1000,
 672                                 (clocks.num_levels == 1) ? "*" :
 673                                 (arcturus_freqs_in_same_level(
 674                                 clocks.data[i].clocks_in_khz / 1000,
 675                                 now / 100) ? "*" : ""));
 676                 break;
 677
 678         case SMU_SOCCLK:
 679                 ret = smu_get_current_clk_freq(smu, SMU_SOCCLK, &now);
 680                 if (ret) {
 681                         pr_err("Attempt to get current socclk Failed!");
 682                         return ret;
 683                 }
 684
 685                 single_dpm_table = &(dpm_table->soc_table);
 686                 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
 687                 if (ret) {
 688                         pr_err("Attempt to get socclk levels Failed!");
 689                         return ret;
 690                 }
 691
 692                 for (i = 0; i < clocks.num_levels; i++)
 693                         size += sprintf(buf + size, "%d: %uMhz %s\n",
 694                                 i, clocks.data[i].clocks_in_khz / 1000,
 695                                 (clocks.num_levels == 1) ? "*" :
 696                                 (arcturus_freqs_in_same_level(
 697                                 clocks.data[i].clocks_in_khz / 1000,
 698                                 now / 100) ? "*" : ""));
 699                 break;
 700
 701         case SMU_FCLK:
 702                 ret = smu_get_current_clk_freq(smu, SMU_FCLK, &now);
 703                 if (ret) {
 704                         pr_err("Attempt to get current fclk Failed!");
 705                         return ret;
 706                 }
 707
 708                 single_dpm_table = &(dpm_table->fclk_table);
 709                 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
 710                 if (ret) {
 711                         pr_err("Attempt to get fclk levels Failed!");
 712                         return ret;
 713                 }
 714
 715                 for (i = 0; i < single_dpm_table->count; i++)
 716                         size += sprintf(buf + size, "%d: %uMhz %s\n",
 717                                 i, single_dpm_table->dpm_levels[i].value,
 718                                 (clocks.num_levels == 1) ? "*" :
 719                                 (arcturus_freqs_in_same_level(
 720                                 clocks.data[i].clocks_in_khz / 1000,
 721                                 now / 100) ? "*" : ""));
 722                 break;
 723
 724         default:
 725                 break;
 726         }
 727
 728         return size;
 729 }
 730
 731 static int arcturus_upload_dpm_level(struct smu_context *smu, bool max,
 732                                      uint32_t feature_mask)
 733 {
 734         struct arcturus_single_dpm_table *single_dpm_table;
 735         struct arcturus_dpm_table *dpm_table =
 736                         smu->smu_dpm.dpm_context;
 737         uint32_t freq;
 738         int ret = 0;
 739
 740         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
 741             (feature_mask & FEATURE_DPM_GFXCLK_MASK)) {
 742                 single_dpm_table = &(dpm_table->gfx_table);
 743                 freq = max ? single_dpm_table->dpm_state.soft_max_level :
 744                         single_dpm_table->dpm_state.soft_min_level;
 745                 ret = smu_send_smc_msg_with_param(smu,
 746                         (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
 747                         (PPCLK_GFXCLK << 16) | (freq & 0xffff),
 748                         NULL);
 749                 if (ret) {
 750                         pr_err("Failed to set soft %s gfxclk !\n",
 751                                                 max ? "max" : "min");
 752                         return ret;
 753                 }
 754         }
 755
 756         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
 757             (feature_mask & FEATURE_DPM_UCLK_MASK)) {
 758                 single_dpm_table = &(dpm_table->mem_table);
 759                 freq = max ? single_dpm_table->dpm_state.soft_max_level :
 760                         single_dpm_table->dpm_state.soft_min_level;
 761                 ret = smu_send_smc_msg_with_param(smu,
 762                         (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
 763                         (PPCLK_UCLK << 16) | (freq & 0xffff),
 764                         NULL);
 765                 if (ret) {
 766                         pr_err("Failed to set soft %s memclk !\n",
 767                                                 max ? "max" : "min");
 768                         return ret;
 769                 }
 770         }
 771
 772         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT) &&
 773             (feature_mask & FEATURE_DPM_SOCCLK_MASK)) {
 774                 single_dpm_table = &(dpm_table->soc_table);
 775                 freq = max ? single_dpm_table->dpm_state.soft_max_level :
 776                         single_dpm_table->dpm_state.soft_min_level;
 777                 ret = smu_send_smc_msg_with_param(smu,
 778                         (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
 779                         (PPCLK_SOCCLK << 16) | (freq & 0xffff),
 780                         NULL);
 781                 if (ret) {
 782                         pr_err("Failed to set soft %s socclk !\n",
 783                                                 max ? "max" : "min");
 784                         return ret;
 785                 }
 786         }
 787
 788         return ret;
 789 }
 790
 791 static int arcturus_force_clk_levels(struct smu_context *smu,
 792                         enum smu_clk_type type, uint32_t mask)
 793 {
 794         struct arcturus_dpm_table *dpm_table;
 795         struct arcturus_single_dpm_table *single_dpm_table;
 796         uint32_t soft_min_level, soft_max_level;
 797         uint32_t smu_version;
 798         int ret = 0;
 799
 800         ret = smu_get_smc_version(smu, NULL, &smu_version);
 801         if (ret) {
 802                 pr_err("Failed to get smu version!\n");
 803                 return ret;
 804         }
 805
 806         if (smu_version >= 0x361200) {
 807                 pr_err("Forcing clock level is not supported with "
 808                        "54.18 and onwards SMU firmwares\n");
 809                 return -EOPNOTSUPP;
 810         }
 811
 812         soft_min_level = mask ? (ffs(mask) - 1) : 0;
 813         soft_max_level = mask ? (fls(mask) - 1) : 0;
 814
 815         dpm_table = smu->smu_dpm.dpm_context;
 816
 817         switch (type) {
 818         case SMU_SCLK:
 819                 single_dpm_table = &(dpm_table->gfx_table);
 820
 821                 if (soft_max_level >= single_dpm_table->count) {
 822                         pr_err("Clock level specified %d is over max allowed %d\n",
 823                                         soft_max_level, single_dpm_table->count - 1);
 824                         ret = -EINVAL;
 825                         break;
 826                 }
 827
 828                 single_dpm_table->dpm_state.soft_min_level =
 829                         single_dpm_table->dpm_levels[soft_min_level].value;
 830                 single_dpm_table->dpm_state.soft_max_level =
 831                         single_dpm_table->dpm_levels[soft_max_level].value;
 832
 833                 ret = arcturus_upload_dpm_level(smu, false, FEATURE_DPM_GFXCLK_MASK);
 834                 if (ret) {
 835                         pr_err("Failed to upload boot level to lowest!\n");
 836                         break;
 837                 }
 838
 839                 ret = arcturus_upload_dpm_level(smu, true, FEATURE_DPM_GFXCLK_MASK);
 840                 if (ret)
 841                         pr_err("Failed to upload dpm max level to highest!\n");
 842
 843                 break;
 844
 845         case SMU_MCLK:
 846         case SMU_SOCCLK:
 847         case SMU_FCLK:
 848                 /*
 849                  * Should not arrive here since Arcturus does not
 850                  * support mclk/socclk/fclk softmin/softmax settings
 851                  */
 852                 ret = -EINVAL;
 853                 break;
 854
 855         default:
 856                 break;
 857         }
 858
 859         return ret;
 860 }
 861
 862 static int arcturus_get_thermal_temperature_range(struct smu_context *smu,
 863                                                 struct smu_temperature_range *range)
 864 {
 865         PPTable_t *pptable = smu->smu_table.driver_pptable;
 866
 867         if (!range)
 868                 return -EINVAL;
 869
 870         range->max = pptable->TedgeLimit *
 871                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 872         range->edge_emergency_max = (pptable->TedgeLimit + CTF_OFFSET_EDGE) *
 873                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 874         range->hotspot_crit_max = pptable->ThotspotLimit *
 875                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 876         range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) *
 877                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 878         range->mem_crit_max = pptable->TmemLimit *
 879                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 880         range->mem_emergency_max = (pptable->TmemLimit + CTF_OFFSET_HBM)*
 881                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 882
 883         return 0;
 884 }
 885
 886 static int arcturus_get_metrics_table(struct smu_context *smu,
 887                                       SmuMetrics_t *metrics_table)
 888 {
 889         struct smu_table_context *smu_table= &smu->smu_table;
 890         int ret = 0;
 891
 892         mutex_lock(&smu->metrics_lock);
 893         if (!smu_table->metrics_time ||
 894              time_after(jiffies, smu_table->metrics_time + HZ / 1000)) {
 895                 ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
 896                                 (void *)smu_table->metrics_table, false);
 897                 if (ret) {
 898                         pr_info("Failed to export SMU metrics table!\n");
 899                         mutex_unlock(&smu->metrics_lock);
 900                         return ret;
 901                 }
 902                 smu_table->metrics_time = jiffies;
 903         }
 904
 905         memcpy(metrics_table, smu_table->metrics_table, sizeof(SmuMetrics_t));
 906         mutex_unlock(&smu->metrics_lock);
 907
 908         return ret;
 909 }
 910
 911 static int arcturus_get_current_activity_percent(struct smu_context *smu,
 912                                                  enum amd_pp_sensors sensor,
 913                                                  uint32_t *value)
 914 {
 915         SmuMetrics_t metrics;
 916         int ret = 0;
 917
 918         if (!value)
 919                 return -EINVAL;
 920
 921         ret = arcturus_get_metrics_table(smu, &metrics);
 922         if (ret)
 923                 return ret;
 924
 925         switch (sensor) {
 926         case AMDGPU_PP_SENSOR_GPU_LOAD:
 927                 *value = metrics.AverageGfxActivity;
 928                 break;
 929         case AMDGPU_PP_SENSOR_MEM_LOAD:
 930                 *value = metrics.AverageUclkActivity;
 931                 break;
 932         default:
 933                 pr_err("Invalid sensor for retrieving clock activity\n");
 934                 return -EINVAL;
 935         }
 936
 937         return 0;
 938 }
 939
 940 static int arcturus_get_gpu_power(struct smu_context *smu, uint32_t *value)
 941 {
 942         SmuMetrics_t metrics;
 943         int ret = 0;
 944
 945         if (!value)
 946                 return -EINVAL;
 947
 948         ret = arcturus_get_metrics_table(smu, &metrics);
 949         if (ret)
 950                 return ret;
 951
 952         *value = metrics.AverageSocketPower << 8;
 953
 954         return 0;
 955 }
 956
 957 static int arcturus_thermal_get_temperature(struct smu_context *smu,
 958                                             enum amd_pp_sensors sensor,
 959                                             uint32_t *value)
 960 {
 961         SmuMetrics_t metrics;
 962         int ret = 0;
 963
 964         if (!value)
 965                 return -EINVAL;
 966
 967         ret = arcturus_get_metrics_table(smu, &metrics);
 968         if (ret)
 969                 return ret;
 970
 971         switch (sensor) {
 972         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
 973                 *value = metrics.TemperatureHotspot *
 974                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 975                 break;
 976         case AMDGPU_PP_SENSOR_EDGE_TEMP:
 977                 *value = metrics.TemperatureEdge *
 978                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 979                 break;
 980         case AMDGPU_PP_SENSOR_MEM_TEMP:
 981                 *value = metrics.TemperatureHBM *
 982                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 983                 break;
 984         default:
 985                 pr_err("Invalid sensor for retrieving temp\n");
 986                 return -EINVAL;
 987         }
 988
 989         return 0;
 990 }
 991
 992 static int arcturus_read_sensor(struct smu_context *smu,
 993                                 enum amd_pp_sensors sensor,
 994                                 void *data, uint32_t *size)
 995 {
 996         struct smu_table_context *table_context = &smu->smu_table;
 997         PPTable_t *pptable = table_context->driver_pptable;
 998         int ret = 0;
 999
1000         if (!data || !size)
1001                 return -EINVAL;
1002
1003         mutex_lock(&smu->sensor_lock);
1004         switch (sensor) {
1005         case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
1006                 *(uint32_t *)data = pptable->FanMaximumRpm;
1007                 *size = 4;
1008                 break;
1009         case AMDGPU_PP_SENSOR_MEM_LOAD:
1010         case AMDGPU_PP_SENSOR_GPU_LOAD:
1011                 ret = arcturus_get_current_activity_percent(smu,
1012                                                             sensor,
1013                                                 (uint32_t *)data);
1014                 *size = 4;
1015                 break;
1016         case AMDGPU_PP_SENSOR_GPU_POWER:
1017                 ret = arcturus_get_gpu_power(smu, (uint32_t *)data);
1018                 *size = 4;
1019                 break;
1020         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1021         case AMDGPU_PP_SENSOR_EDGE_TEMP:
1022         case AMDGPU_PP_SENSOR_MEM_TEMP:
1023                 ret = arcturus_thermal_get_temperature(smu, sensor,
1024                                                 (uint32_t *)data);
1025                 *size = 4;
1026                 break;
1027         default:
1028                 ret = smu_v11_0_read_sensor(smu, sensor, data, size);
1029         }
1030         mutex_unlock(&smu->sensor_lock);
1031
1032         return ret;
1033 }
1034
1035 static int arcturus_get_fan_speed_rpm(struct smu_context *smu,
1036                                       uint32_t *speed)
1037 {
1038         SmuMetrics_t metrics;
1039         int ret = 0;
1040
1041         if (!speed)
1042                 return -EINVAL;
1043
1044         ret = arcturus_get_metrics_table(smu, &metrics);
1045         if (ret)
1046                 return ret;
1047
1048         *speed = metrics.CurrFanSpeed;
1049
1050         return ret;
1051 }
1052
1053 static int arcturus_get_fan_speed_percent(struct smu_context *smu,
1054                                           uint32_t *speed)
1055 {
1056         PPTable_t *pptable = smu->smu_table.driver_pptable;
1057         uint32_t percent, current_rpm;
1058         int ret = 0;
1059
1060         if (!speed)
1061                 return -EINVAL;
1062
1063         ret = arcturus_get_fan_speed_rpm(smu, &current_rpm);
1064         if (ret)
1065                 return ret;
1066
1067         percent = current_rpm * 100 / pptable->FanMaximumRpm;
1068         *speed = percent > 100 ? 100 : percent;
1069
1070         return ret;
1071 }
1072
1073 static int arcturus_get_current_clk_freq_by_table(struct smu_context *smu,
1074                                        enum smu_clk_type clk_type,
1075                                        uint32_t *value)
1076 {
1077         static SmuMetrics_t metrics;
1078         int ret = 0, clk_id = 0;
1079
1080         if (!value)
1081                 return -EINVAL;
1082
1083         clk_id = smu_clk_get_index(smu, clk_type);
1084         if (clk_id < 0)
1085                 return -EINVAL;
1086
1087         ret = arcturus_get_metrics_table(smu, &metrics);
1088         if (ret)
1089                 return ret;
1090
1091         switch (clk_id) {
1092         case PPCLK_GFXCLK:
1093                 /*
1094                  * CurrClock[clk_id] can provide accurate
1095                  *   output only when the dpm feature is enabled.
1096                  * We can use Average_* for dpm disabled case.
1097                  *   But this is available for gfxclk/uclk/socclk.
1098                  */
1099                 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT))
1100                         *value = metrics.CurrClock[PPCLK_GFXCLK];
1101                 else
1102                         *value = metrics.AverageGfxclkFrequency;
1103                 break;
1104         case PPCLK_UCLK:
1105                 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT))
1106                         *value = metrics.CurrClock[PPCLK_UCLK];
1107                 else
1108                         *value = metrics.AverageUclkFrequency;
1109                 break;
1110         case PPCLK_SOCCLK:
1111                 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT))
1112                         *value = metrics.CurrClock[PPCLK_SOCCLK];
1113                 else
1114                         *value = metrics.AverageSocclkFrequency;
1115                 break;
1116         default:
1117                 *value = metrics.CurrClock[clk_id];
1118                 break;
1119         }
1120
1121         return ret;
1122 }
1123
1124 static uint32_t arcturus_find_lowest_dpm_level(struct arcturus_single_dpm_table *table)
1125 {
1126         uint32_t i;
1127
1128         for (i = 0; i < table->count; i++) {
1129                 if (table->dpm_levels[i].enabled)
1130                         break;
1131         }
1132         if (i >= table->count) {
1133                 i = 0;
1134                 table->dpm_levels[i].enabled = true;
1135         }
1136
1137         return i;
1138 }
1139
1140 static uint32_t arcturus_find_highest_dpm_level(struct arcturus_single_dpm_table *table)
1141 {
1142         int i = 0;
1143
1144         if (table->count <= 0) {
1145                 pr_err("[%s] DPM Table has no entry!", __func__);
1146                 return 0;
1147         }
1148         if (table->count > MAX_DPM_NUMBER) {
1149                 pr_err("[%s] DPM Table has too many entries!", __func__);
1150                 return MAX_DPM_NUMBER - 1;
1151         }
1152
1153         for (i = table->count - 1; i >= 0; i--) {
1154                 if (table->dpm_levels[i].enabled)
1155                         break;
1156         }
1157         if (i < 0) {
1158                 i = 0;
1159                 table->dpm_levels[i].enabled = true;
1160         }
1161
1162         return i;
1163 }
1164
1165
1166
1167 static int arcturus_force_dpm_limit_value(struct smu_context *smu, bool highest)
1168 {
1169         struct arcturus_dpm_table *dpm_table =
1170                 (struct arcturus_dpm_table *)smu->smu_dpm.dpm_context;
1171         struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(smu->adev, 0);
1172         uint32_t soft_level;
1173         int ret = 0;
1174
1175         /* gfxclk */
1176         if (highest)
1177                 soft_level = arcturus_find_highest_dpm_level(&(dpm_table->gfx_table));
1178         else
1179                 soft_level = arcturus_find_lowest_dpm_level(&(dpm_table->gfx_table));
1180
1181         dpm_table->gfx_table.dpm_state.soft_min_level =
1182                 dpm_table->gfx_table.dpm_state.soft_max_level =
1183                 dpm_table->gfx_table.dpm_levels[soft_level].value;
1184
1185         ret = arcturus_upload_dpm_level(smu, false, FEATURE_DPM_GFXCLK_MASK);
1186         if (ret) {
1187                 pr_err("Failed to upload boot level to %s!\n",
1188                                 highest ? "highest" : "lowest");
1189                 return ret;
1190         }
1191
1192         ret = arcturus_upload_dpm_level(smu, true, FEATURE_DPM_GFXCLK_MASK);
1193         if (ret) {
1194                 pr_err("Failed to upload dpm max level to %s!\n!",
1195                                 highest ? "highest" : "lowest");
1196                 return ret;
1197         }
1198
1199         if (hive)
1200                 /*
1201                  * Force XGMI Pstate to highest or lowest
1202                  * TODO: revise this when xgmi dpm is functional
1203                  */
1204                 ret = smu_v11_0_set_xgmi_pstate(smu, highest ? 1 : 0);
1205
1206         return ret;
1207 }
1208
1209 static int arcturus_unforce_dpm_levels(struct smu_context *smu)
1210 {
1211         struct arcturus_dpm_table *dpm_table =
1212                 (struct arcturus_dpm_table *)smu->smu_dpm.dpm_context;
1213         struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(smu->adev, 0);
1214         uint32_t soft_min_level, soft_max_level;
1215         int ret = 0;
1216
1217         /* gfxclk */
1218         soft_min_level = arcturus_find_lowest_dpm_level(&(dpm_table->gfx_table));
1219         soft_max_level = arcturus_find_highest_dpm_level(&(dpm_table->gfx_table));
1220         dpm_table->gfx_table.dpm_state.soft_min_level =
1221                 dpm_table->gfx_table.dpm_levels[soft_min_level].value;
1222         dpm_table->gfx_table.dpm_state.soft_max_level =
1223                 dpm_table->gfx_table.dpm_levels[soft_max_level].value;
1224
1225         ret = arcturus_upload_dpm_level(smu, false, FEATURE_DPM_GFXCLK_MASK);
1226         if (ret) {
1227                 pr_err("Failed to upload DPM Bootup Levels!");
1228                 return ret;
1229         }
1230
1231         ret = arcturus_upload_dpm_level(smu, true, FEATURE_DPM_GFXCLK_MASK);
1232         if (ret) {
1233                 pr_err("Failed to upload DPM Max Levels!");
1234                 return ret;
1235         }
1236
1237         if (hive)
1238                 /*
1239                  * Reset XGMI Pstate back to default
1240                  * TODO: revise this when xgmi dpm is functional
1241                  */
1242                 ret = smu_v11_0_set_xgmi_pstate(smu, 0);
1243
1244         return ret;
1245 }
1246
1247 static int
1248 arcturus_get_profiling_clk_mask(struct smu_context *smu,
1249                                 enum amd_dpm_forced_level level,
1250                                 uint32_t *sclk_mask,
1251                                 uint32_t *mclk_mask,
1252                                 uint32_t *soc_mask)
1253 {
1254         struct arcturus_dpm_table *dpm_table =
1255                 (struct arcturus_dpm_table *)smu->smu_dpm.dpm_context;
1256         struct arcturus_single_dpm_table *gfx_dpm_table;
1257         struct arcturus_single_dpm_table *mem_dpm_table;
1258         struct arcturus_single_dpm_table *soc_dpm_table;
1259
1260         if (!smu->smu_dpm.dpm_context)
1261                 return -EINVAL;
1262
1263         gfx_dpm_table = &dpm_table->gfx_table;
1264         mem_dpm_table = &dpm_table->mem_table;
1265         soc_dpm_table = &dpm_table->soc_table;
1266
1267         *sclk_mask = 0;
1268         *mclk_mask = 0;
1269         *soc_mask  = 0;
1270
1271         if (gfx_dpm_table->count > ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL &&
1272             mem_dpm_table->count > ARCTURUS_UMD_PSTATE_MCLK_LEVEL &&
1273             soc_dpm_table->count > ARCTURUS_UMD_PSTATE_SOCCLK_LEVEL) {
1274                 *sclk_mask = ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL;
1275                 *mclk_mask = ARCTURUS_UMD_PSTATE_MCLK_LEVEL;
1276                 *soc_mask  = ARCTURUS_UMD_PSTATE_SOCCLK_LEVEL;
1277         }
1278
1279         if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
1280                 *sclk_mask = 0;
1281         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
1282                 *mclk_mask = 0;
1283         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
1284                 *sclk_mask = gfx_dpm_table->count - 1;
1285                 *mclk_mask = mem_dpm_table->count - 1;
1286                 *soc_mask  = soc_dpm_table->count - 1;
1287         }
1288
1289         return 0;
1290 }
1291
1292 static int arcturus_get_power_limit(struct smu_context *smu,
1293                                      uint32_t *limit,
1294                                      bool cap)
1295 {
1296         PPTable_t *pptable = smu->smu_table.driver_pptable;
1297         uint32_t asic_default_power_limit = 0;
1298         int ret = 0;
1299         int power_src;
1300
1301         if (!smu->power_limit) {
1302                 if (smu_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
1303                         power_src = smu_power_get_index(smu, SMU_POWER_SOURCE_AC);
1304                         if (power_src < 0)
1305                                 return -EINVAL;
1306
1307                         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetPptLimit,
1308                                 power_src << 16, &asic_default_power_limit);
1309                         if (ret) {
1310                                 pr_err("[%s] get PPT limit failed!", __func__);
1311                                 return ret;
1312                         }
1313                 } else {
1314                         /* the last hope to figure out the ppt limit */
1315                         if (!pptable) {
1316                                 pr_err("Cannot get PPT limit due to pptable missing!");
1317                                 return -EINVAL;
1318                         }
1319                         asic_default_power_limit =
1320                                 pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
1321                 }
1322
1323                 smu->power_limit = asic_default_power_limit;
1324         }
1325
1326         if (cap)
1327                 *limit = smu_v11_0_get_max_power_limit(smu);
1328         else
1329                 *limit = smu->power_limit;
1330
1331         return 0;
1332 }
1333
1334 static int arcturus_get_power_profile_mode(struct smu_context *smu,
1335                                            char *buf)
1336 {
1337         struct amdgpu_device *adev = smu->adev;
1338         DpmActivityMonitorCoeffInt_t activity_monitor;
1339         static const char *profile_name[] = {
1340                                         "BOOTUP_DEFAULT",
1341                                         "3D_FULL_SCREEN",
1342                                         "POWER_SAVING",
1343                                         "VIDEO",
1344                                         "VR",
1345                                         "COMPUTE",
1346                                         "CUSTOM"};
1347         static const char *title[] = {
1348                         "PROFILE_INDEX(NAME)",
1349                         "CLOCK_TYPE(NAME)",
1350                         "FPS",
1351                         "UseRlcBusy",
1352                         "MinActiveFreqType",
1353                         "MinActiveFreq",
1354                         "BoosterFreqType",
1355                         "BoosterFreq",
1356                         "PD_Data_limit_c",
1357                         "PD_Data_error_coeff",
1358                         "PD_Data_error_rate_coeff"};
1359         uint32_t i, size = 0;
1360         int16_t workload_type = 0;
1361         int result = 0;
1362         uint32_t smu_version;
1363
1364         if (!buf)
1365                 return -EINVAL;
1366
1367         result = smu_get_smc_version(smu, NULL, &smu_version);
1368         if (result)
1369                 return result;
1370
1371         if (smu_version >= 0x360d00 && !amdgpu_sriov_vf(adev))
1372                 size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
1373                         title[0], title[1], title[2], title[3], title[4], title[5],
1374                         title[6], title[7], title[8], title[9], title[10]);
1375         else
1376                 size += sprintf(buf + size, "%16s\n",
1377                         title[0]);
1378
1379         for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1380                 /*
1381                  * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT
1382                  * Not all profile modes are supported on arcturus.
1383                  */
1384                 workload_type = smu_workload_get_type(smu, i);
1385                 if (workload_type < 0)
1386                         continue;
1387
1388                 if (smu_version >= 0x360d00 && !amdgpu_sriov_vf(adev)) {
1389                         result = smu_update_table(smu,
1390                                                   SMU_TABLE_ACTIVITY_MONITOR_COEFF,
1391                                                   workload_type,
1392                                                   (void *)(&activity_monitor),
1393                                                   false);
1394                         if (result) {
1395                                 pr_err("[%s] Failed to get activity monitor!", __func__);
1396                                 return result;
1397                         }
1398                 }
1399
1400                 size += sprintf(buf + size, "%2d %14s%s\n",
1401                         i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1402
1403                 if (smu_version >= 0x360d00 && !amdgpu_sriov_vf(adev)) {
1404                         size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1405                                 " ",
1406                                 0,
1407                                 "GFXCLK",
1408                                 activity_monitor.Gfx_FPS,
1409                                 activity_monitor.Gfx_UseRlcBusy,
1410                                 activity_monitor.Gfx_MinActiveFreqType,
1411                                 activity_monitor.Gfx_MinActiveFreq,
1412                                 activity_monitor.Gfx_BoosterFreqType,
1413                                 activity_monitor.Gfx_BoosterFreq,
1414                                 activity_monitor.Gfx_PD_Data_limit_c,
1415                                 activity_monitor.Gfx_PD_Data_error_coeff,
1416                                 activity_monitor.Gfx_PD_Data_error_rate_coeff);
1417
1418                         size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1419                                 " ",
1420                                 1,
1421                                 "UCLK",
1422                                 activity_monitor.Mem_FPS,
1423                                 activity_monitor.Mem_UseRlcBusy,
1424                                 activity_monitor.Mem_MinActiveFreqType,
1425                                 activity_monitor.Mem_MinActiveFreq,
1426                                 activity_monitor.Mem_BoosterFreqType,
1427                                 activity_monitor.Mem_BoosterFreq,
1428                                 activity_monitor.Mem_PD_Data_limit_c,
1429                                 activity_monitor.Mem_PD_Data_error_coeff,
1430                                 activity_monitor.Mem_PD_Data_error_rate_coeff);
1431                 }
1432         }
1433
1434         return size;
1435 }
1436
1437 static int arcturus_set_power_profile_mode(struct smu_context *smu,
1438                                            long *input,
1439                                            uint32_t size)
1440 {
1441         DpmActivityMonitorCoeffInt_t activity_monitor;
1442         int workload_type = 0;
1443         uint32_t profile_mode = input[size];
1444         int ret = 0;
1445         uint32_t smu_version;
1446
1447         if (profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1448                 pr_err("Invalid power profile mode %d\n", profile_mode);
1449                 return -EINVAL;
1450         }
1451
1452         ret = smu_get_smc_version(smu, NULL, &smu_version);
1453         if (ret)
1454                 return ret;
1455
1456         if ((profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) &&
1457              (smu_version >=0x360d00)) {
1458                 ret = smu_update_table(smu,
1459                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF,
1460                                        WORKLOAD_PPLIB_CUSTOM_BIT,
1461                                        (void *)(&activity_monitor),
1462                                        false);
1463                 if (ret) {
1464                         pr_err("[%s] Failed to get activity monitor!", __func__);
1465                         return ret;
1466                 }
1467
1468                 switch (input[0]) {
1469                 case 0: /* Gfxclk */
1470                         activity_monitor.Gfx_FPS = input[1];
1471                         activity_monitor.Gfx_UseRlcBusy = input[2];
1472                         activity_monitor.Gfx_MinActiveFreqType = input[3];
1473                         activity_monitor.Gfx_MinActiveFreq = input[4];
1474                         activity_monitor.Gfx_BoosterFreqType = input[5];
1475                         activity_monitor.Gfx_BoosterFreq = input[6];
1476                         activity_monitor.Gfx_PD_Data_limit_c = input[7];
1477                         activity_monitor.Gfx_PD_Data_error_coeff = input[8];
1478                         activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9];
1479                         break;
1480                 case 1: /* Uclk */
1481                         activity_monitor.Mem_FPS = input[1];
1482                         activity_monitor.Mem_UseRlcBusy = input[2];
1483                         activity_monitor.Mem_MinActiveFreqType = input[3];
1484                         activity_monitor.Mem_MinActiveFreq = input[4];
1485                         activity_monitor.Mem_BoosterFreqType = input[5];
1486                         activity_monitor.Mem_BoosterFreq = input[6];
1487                         activity_monitor.Mem_PD_Data_limit_c = input[7];
1488                         activity_monitor.Mem_PD_Data_error_coeff = input[8];
1489                         activity_monitor.Mem_PD_Data_error_rate_coeff = input[9];
1490                         break;
1491                 }
1492
1493                 ret = smu_update_table(smu,
1494                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF,
1495                                        WORKLOAD_PPLIB_CUSTOM_BIT,
1496                                        (void *)(&activity_monitor),
1497                                        true);
1498                 if (ret) {
1499                         pr_err("[%s] Failed to set activity monitor!", __func__);
1500                         return ret;
1501                 }
1502         }
1503
1504         /*
1505          * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT
1506          * Not all profile modes are supported on arcturus.
1507          */
1508         workload_type = smu_workload_get_type(smu, profile_mode);
1509         if (workload_type < 0) {
1510                 pr_err("Unsupported power profile mode %d on arcturus\n", profile_mode);
1511                 return -EINVAL;
1512         }
1513
1514         ret = smu_send_smc_msg_with_param(smu,
1515                                           SMU_MSG_SetWorkloadMask,
1516                                           1 << workload_type,
1517                                           NULL);
1518         if (ret) {
1519                 pr_err("Fail to set workload type %d\n", workload_type);
1520                 return ret;
1521         }
1522
1523         smu->power_profile_mode = profile_mode;
1524
1525         return 0;
1526 }
1527
1528 static int arcturus_set_performance_level(struct smu_context *smu,
1529                                           enum amd_dpm_forced_level level)
1530 {
1531         uint32_t smu_version;
1532         int ret;
1533
1534         ret = smu_get_smc_version(smu, NULL, &smu_version);
1535         if (ret) {
1536                 pr_err("Failed to get smu version!\n");
1537                 return ret;
1538         }
1539
1540         switch (level) {
1541         case AMD_DPM_FORCED_LEVEL_HIGH:
1542         case AMD_DPM_FORCED_LEVEL_LOW:
1543         case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1544         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1545         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1546         case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1547                 if (smu_version >= 0x361200) {
1548                         pr_err("Forcing clock level is not supported with "
1549                                "54.18 and onwards SMU firmwares\n");
1550                         return -EOPNOTSUPP;
1551                 }
1552                 break;
1553         default:
1554                 break;
1555         }
1556
1557         return smu_v11_0_set_performance_level(smu, level);
1558 }
1559
1560 static void arcturus_dump_pptable(struct smu_context *smu)
1561 {
1562         struct smu_table_context *table_context = &smu->smu_table;
1563         PPTable_t *pptable = table_context->driver_pptable;
1564         int i;
1565
1566         pr_info("Dumped PPTable:\n");
1567
1568         pr_info("Version = 0x%08x\n", pptable->Version);
1569
1570         pr_info("FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
1571         pr_info("FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
1572
1573         for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
1574                 pr_info("SocketPowerLimitAc[%d] = %d\n", i, pptable->SocketPowerLimitAc[i]);
1575                 pr_info("SocketPowerLimitAcTau[%d] = %d\n", i, pptable->SocketPowerLimitAcTau[i]);
1576         }
1577
1578         pr_info("TdcLimitSoc = %d\n", pptable->TdcLimitSoc);
1579         pr_info("TdcLimitSocTau = %d\n", pptable->TdcLimitSocTau);
1580         pr_info("TdcLimitGfx = %d\n", pptable->TdcLimitGfx);
1581         pr_info("TdcLimitGfxTau = %d\n", pptable->TdcLimitGfxTau);
1582
1583         pr_info("TedgeLimit = %d\n", pptable->TedgeLimit);
1584         pr_info("ThotspotLimit = %d\n", pptable->ThotspotLimit);
1585         pr_info("TmemLimit = %d\n", pptable->TmemLimit);
1586         pr_info("Tvr_gfxLimit = %d\n", pptable->Tvr_gfxLimit);
1587         pr_info("Tvr_memLimit = %d\n", pptable->Tvr_memLimit);
1588         pr_info("Tvr_socLimit = %d\n", pptable->Tvr_socLimit);
1589         pr_info("FitLimit = %d\n", pptable->FitLimit);
1590
1591         pr_info("PpmPowerLimit = %d\n", pptable->PpmPowerLimit);
1592         pr_info("PpmTemperatureThreshold = %d\n", pptable->PpmTemperatureThreshold);
1593
1594         pr_info("ThrottlerControlMask = %d\n", pptable->ThrottlerControlMask);
1595
1596         pr_info("UlvVoltageOffsetGfx = %d\n", pptable->UlvVoltageOffsetGfx);
1597         pr_info("UlvPadding = 0x%08x\n", pptable->UlvPadding);
1598
1599         pr_info("UlvGfxclkBypass = %d\n", pptable->UlvGfxclkBypass);
1600         pr_info("Padding234[0] = 0x%02x\n", pptable->Padding234[0]);
1601         pr_info("Padding234[1] = 0x%02x\n", pptable->Padding234[1]);
1602         pr_info("Padding234[2] = 0x%02x\n", pptable->Padding234[2]);
1603
1604         pr_info("MinVoltageGfx = %d\n", pptable->MinVoltageGfx);
1605         pr_info("MinVoltageSoc = %d\n", pptable->MinVoltageSoc);
1606         pr_info("MaxVoltageGfx = %d\n", pptable->MaxVoltageGfx);
1607         pr_info("MaxVoltageSoc = %d\n", pptable->MaxVoltageSoc);
1608
1609         pr_info("LoadLineResistanceGfx = %d\n", pptable->LoadLineResistanceGfx);
1610         pr_info("LoadLineResistanceSoc = %d\n", pptable->LoadLineResistanceSoc);
1611
1612         pr_info("[PPCLK_GFXCLK]\n"
1613                         "  .VoltageMode          = 0x%02x\n"
1614                         "  .SnapToDiscrete       = 0x%02x\n"
1615                         "  .NumDiscreteLevels    = 0x%02x\n"
1616                         "  .padding              = 0x%02x\n"
1617                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1618                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1619                         "  .SsFmin               = 0x%04x\n"
1620                         "  .Padding_16           = 0x%04x\n",
1621                         pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
1622                         pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
1623                         pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
1624                         pptable->DpmDescriptor[PPCLK_GFXCLK].padding,
1625                         pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
1626                         pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
1627                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
1628                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
1629                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
1630                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
1631                         pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
1632
1633         pr_info("[PPCLK_VCLK]\n"
1634                         "  .VoltageMode          = 0x%02x\n"
1635                         "  .SnapToDiscrete       = 0x%02x\n"
1636                         "  .NumDiscreteLevels    = 0x%02x\n"
1637                         "  .padding              = 0x%02x\n"
1638                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1639                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1640                         "  .SsFmin               = 0x%04x\n"
1641                         "  .Padding_16           = 0x%04x\n",
1642                         pptable->DpmDescriptor[PPCLK_VCLK].VoltageMode,
1643                         pptable->DpmDescriptor[PPCLK_VCLK].SnapToDiscrete,
1644                         pptable->DpmDescriptor[PPCLK_VCLK].NumDiscreteLevels,
1645                         pptable->DpmDescriptor[PPCLK_VCLK].padding,
1646                         pptable->DpmDescriptor[PPCLK_VCLK].ConversionToAvfsClk.m,
1647                         pptable->DpmDescriptor[PPCLK_VCLK].ConversionToAvfsClk.b,
1648                         pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.a,
1649                         pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.b,
1650                         pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.c,
1651                         pptable->DpmDescriptor[PPCLK_VCLK].SsFmin,
1652                         pptable->DpmDescriptor[PPCLK_VCLK].Padding16);
1653
1654         pr_info("[PPCLK_DCLK]\n"
1655                         "  .VoltageMode          = 0x%02x\n"
1656                         "  .SnapToDiscrete       = 0x%02x\n"
1657                         "  .NumDiscreteLevels    = 0x%02x\n"
1658                         "  .padding              = 0x%02x\n"
1659                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1660                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1661                         "  .SsFmin               = 0x%04x\n"
1662                         "  .Padding_16           = 0x%04x\n",
1663                         pptable->DpmDescriptor[PPCLK_DCLK].VoltageMode,
1664                         pptable->DpmDescriptor[PPCLK_DCLK].SnapToDiscrete,
1665                         pptable->DpmDescriptor[PPCLK_DCLK].NumDiscreteLevels,
1666                         pptable->DpmDescriptor[PPCLK_DCLK].padding,
1667                         pptable->DpmDescriptor[PPCLK_DCLK].ConversionToAvfsClk.m,
1668                         pptable->DpmDescriptor[PPCLK_DCLK].ConversionToAvfsClk.b,
1669                         pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.a,
1670                         pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.b,
1671                         pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.c,
1672                         pptable->DpmDescriptor[PPCLK_DCLK].SsFmin,
1673                         pptable->DpmDescriptor[PPCLK_DCLK].Padding16);
1674
1675         pr_info("[PPCLK_SOCCLK]\n"
1676                         "  .VoltageMode          = 0x%02x\n"
1677                         "  .SnapToDiscrete       = 0x%02x\n"
1678                         "  .NumDiscreteLevels    = 0x%02x\n"
1679                         "  .padding              = 0x%02x\n"
1680                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1681                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1682                         "  .SsFmin               = 0x%04x\n"
1683                         "  .Padding_16           = 0x%04x\n",
1684                         pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
1685                         pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
1686                         pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
1687                         pptable->DpmDescriptor[PPCLK_SOCCLK].padding,
1688                         pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
1689                         pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
1690                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
1691                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
1692                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
1693                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
1694                         pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
1695
1696         pr_info("[PPCLK_UCLK]\n"
1697                         "  .VoltageMode          = 0x%02x\n"
1698                         "  .SnapToDiscrete       = 0x%02x\n"
1699                         "  .NumDiscreteLevels    = 0x%02x\n"
1700                         "  .padding              = 0x%02x\n"
1701                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1702                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1703                         "  .SsFmin               = 0x%04x\n"
1704                         "  .Padding_16           = 0x%04x\n",
1705                         pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
1706                         pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
1707                         pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
1708                         pptable->DpmDescriptor[PPCLK_UCLK].padding,
1709                         pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
1710                         pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
1711                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
1712                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
1713                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
1714                         pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
1715                         pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
1716
1717         pr_info("[PPCLK_FCLK]\n"
1718                         "  .VoltageMode          = 0x%02x\n"
1719                         "  .SnapToDiscrete       = 0x%02x\n"
1720                         "  .NumDiscreteLevels    = 0x%02x\n"
1721                         "  .padding              = 0x%02x\n"
1722                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1723                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1724                         "  .SsFmin               = 0x%04x\n"
1725                         "  .Padding_16           = 0x%04x\n",
1726                         pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
1727                         pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
1728                         pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
1729                         pptable->DpmDescriptor[PPCLK_FCLK].padding,
1730                         pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
1731                         pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
1732                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
1733                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
1734                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
1735                         pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
1736                         pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
1737
1738
1739         pr_info("FreqTableGfx\n");
1740         for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
1741                 pr_info("  .[%02d] = %d\n", i, pptable->FreqTableGfx[i]);
1742
1743         pr_info("FreqTableVclk\n");
1744         for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
1745                 pr_info("  .[%02d] = %d\n", i, pptable->FreqTableVclk[i]);
1746
1747         pr_info("FreqTableDclk\n");
1748         for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
1749                 pr_info("  .[%02d] = %d\n", i, pptable->FreqTableDclk[i]);
1750
1751         pr_info("FreqTableSocclk\n");
1752         for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
1753                 pr_info("  .[%02d] = %d\n", i, pptable->FreqTableSocclk[i]);
1754
1755         pr_info("FreqTableUclk\n");
1756         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
1757                 pr_info("  .[%02d] = %d\n", i, pptable->FreqTableUclk[i]);
1758
1759         pr_info("FreqTableFclk\n");
1760         for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
1761                 pr_info("  .[%02d] = %d\n", i, pptable->FreqTableFclk[i]);
1762
1763         pr_info("Mp0clkFreq\n");
1764         for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
1765                 pr_info("  .[%d] = %d\n", i, pptable->Mp0clkFreq[i]);
1766
1767         pr_info("Mp0DpmVoltage\n");
1768         for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
1769                 pr_info("  .[%d] = %d\n", i, pptable->Mp0DpmVoltage[i]);
1770
1771         pr_info("GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
1772         pr_info("GfxclkSlewRate = 0x%x\n", pptable->GfxclkSlewRate);
1773         pr_info("Padding567[0] = 0x%x\n", pptable->Padding567[0]);
1774         pr_info("Padding567[1] = 0x%x\n", pptable->Padding567[1]);
1775         pr_info("Padding567[2] = 0x%x\n", pptable->Padding567[2]);
1776         pr_info("Padding567[3] = 0x%x\n", pptable->Padding567[3]);
1777         pr_info("GfxclkDsMaxFreq = %d\n", pptable->GfxclkDsMaxFreq);
1778         pr_info("GfxclkSource = 0x%x\n", pptable->GfxclkSource);
1779         pr_info("Padding456 = 0x%x\n", pptable->Padding456);
1780
1781         pr_info("EnableTdpm = %d\n", pptable->EnableTdpm);
1782         pr_info("TdpmHighHystTemperature = %d\n", pptable->TdpmHighHystTemperature);
1783         pr_info("TdpmLowHystTemperature = %d\n", pptable->TdpmLowHystTemperature);
1784         pr_info("GfxclkFreqHighTempLimit = %d\n", pptable->GfxclkFreqHighTempLimit);
1785
1786         pr_info("FanStopTemp = %d\n", pptable->FanStopTemp);
1787         pr_info("FanStartTemp = %d\n", pptable->FanStartTemp);
1788
1789         pr_info("FanGainEdge = %d\n", pptable->FanGainEdge);
1790         pr_info("FanGainHotspot = %d\n", pptable->FanGainHotspot);
1791         pr_info("FanGainVrGfx = %d\n", pptable->FanGainVrGfx);
1792         pr_info("FanGainVrSoc = %d\n", pptable->FanGainVrSoc);
1793         pr_info("FanGainVrMem = %d\n", pptable->FanGainVrMem);
1794         pr_info("FanGainHbm = %d\n", pptable->FanGainHbm);
1795
1796         pr_info("FanPwmMin = %d\n", pptable->FanPwmMin);
1797         pr_info("FanAcousticLimitRpm = %d\n", pptable->FanAcousticLimitRpm);
1798         pr_info("FanThrottlingRpm = %d\n", pptable->FanThrottlingRpm);
1799         pr_info("FanMaximumRpm = %d\n", pptable->FanMaximumRpm);
1800         pr_info("FanTargetTemperature = %d\n", pptable->FanTargetTemperature);
1801         pr_info("FanTargetGfxclk = %d\n", pptable->FanTargetGfxclk);
1802         pr_info("FanZeroRpmEnable = %d\n", pptable->FanZeroRpmEnable);
1803         pr_info("FanTachEdgePerRev = %d\n", pptable->FanTachEdgePerRev);
1804         pr_info("FanTempInputSelect = %d\n", pptable->FanTempInputSelect);
1805
1806         pr_info("FuzzyFan_ErrorSetDelta = %d\n", pptable->FuzzyFan_ErrorSetDelta);
1807         pr_info("FuzzyFan_ErrorRateSetDelta = %d\n", pptable->FuzzyFan_ErrorRateSetDelta);
1808         pr_info("FuzzyFan_PwmSetDelta = %d\n", pptable->FuzzyFan_PwmSetDelta);
1809         pr_info("FuzzyFan_Reserved = %d\n", pptable->FuzzyFan_Reserved);
1810
1811         pr_info("OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
1812         pr_info("OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
1813         pr_info("Padding8_Avfs[0] = %d\n", pptable->Padding8_Avfs[0]);
1814         pr_info("Padding8_Avfs[1] = %d\n", pptable->Padding8_Avfs[1]);
1815
1816         pr_info("dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
1817                         pptable->dBtcGbGfxPll.a,
1818                         pptable->dBtcGbGfxPll.b,
1819                         pptable->dBtcGbGfxPll.c);
1820         pr_info("dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
1821                         pptable->dBtcGbGfxAfll.a,
1822                         pptable->dBtcGbGfxAfll.b,
1823                         pptable->dBtcGbGfxAfll.c);
1824         pr_info("dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
1825                         pptable->dBtcGbSoc.a,
1826                         pptable->dBtcGbSoc.b,
1827                         pptable->dBtcGbSoc.c);
1828
1829         pr_info("qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
1830                         pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
1831                         pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
1832         pr_info("qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
1833                         pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
1834                         pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
1835
1836         pr_info("qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
1837                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
1838                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
1839                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
1840         pr_info("qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
1841                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
1842                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
1843                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
1844
1845         pr_info("DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
1846         pr_info("DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
1847
1848         pr_info("DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
1849         pr_info("DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
1850         pr_info("Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
1851         pr_info("Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
1852
1853         pr_info("DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
1854         pr_info("DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
1855         pr_info("DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
1856         pr_info("DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
1857
1858         pr_info("DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
1859         pr_info("DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
1860
1861         pr_info("XgmiDpmPstates\n");
1862         for (i = 0; i < NUM_XGMI_LEVELS; i++)
1863                 pr_info("  .[%d] = %d\n", i, pptable->XgmiDpmPstates[i]);
1864         pr_info("XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
1865         pr_info("XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
1866
1867         pr_info("VDDGFX_TVmin = %d\n", pptable->VDDGFX_TVmin);
1868         pr_info("VDDSOC_TVmin = %d\n", pptable->VDDSOC_TVmin);
1869         pr_info("VDDGFX_Vmin_HiTemp = %d\n", pptable->VDDGFX_Vmin_HiTemp);
1870         pr_info("VDDGFX_Vmin_LoTemp = %d\n", pptable->VDDGFX_Vmin_LoTemp);
1871         pr_info("VDDSOC_Vmin_HiTemp = %d\n", pptable->VDDSOC_Vmin_HiTemp);
1872         pr_info("VDDSOC_Vmin_LoTemp = %d\n", pptable->VDDSOC_Vmin_LoTemp);
1873         pr_info("VDDGFX_TVminHystersis = %d\n", pptable->VDDGFX_TVminHystersis);
1874         pr_info("VDDSOC_TVminHystersis = %d\n", pptable->VDDSOC_TVminHystersis);
1875
1876         pr_info("DebugOverrides = 0x%x\n", pptable->DebugOverrides);
1877         pr_info("ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
1878                         pptable->ReservedEquation0.a,
1879                         pptable->ReservedEquation0.b,
1880                         pptable->ReservedEquation0.c);
1881         pr_info("ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
1882                         pptable->ReservedEquation1.a,
1883                         pptable->ReservedEquation1.b,
1884                         pptable->ReservedEquation1.c);
1885         pr_info("ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
1886                         pptable->ReservedEquation2.a,
1887                         pptable->ReservedEquation2.b,
1888                         pptable->ReservedEquation2.c);
1889         pr_info("ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
1890                         pptable->ReservedEquation3.a,
1891                         pptable->ReservedEquation3.b,
1892                         pptable->ReservedEquation3.c);
1893
1894         pr_info("MinVoltageUlvGfx = %d\n", pptable->MinVoltageUlvGfx);
1895         pr_info("PaddingUlv = %d\n", pptable->PaddingUlv);
1896
1897         pr_info("TotalPowerConfig = %d\n", pptable->TotalPowerConfig);
1898         pr_info("TotalPowerSpare1 = %d\n", pptable->TotalPowerSpare1);
1899         pr_info("TotalPowerSpare2 = %d\n", pptable->TotalPowerSpare2);
1900
1901         pr_info("PccThresholdLow = %d\n", pptable->PccThresholdLow);
1902         pr_info("PccThresholdHigh = %d\n", pptable->PccThresholdHigh);
1903
1904         pr_info("Board Parameters:\n");
1905         pr_info("MaxVoltageStepGfx = 0x%x\n", pptable->MaxVoltageStepGfx);
1906         pr_info("MaxVoltageStepSoc = 0x%x\n", pptable->MaxVoltageStepSoc);
1907
1908         pr_info("VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
1909         pr_info("VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
1910         pr_info("VddMemVrMapping = 0x%x\n", pptable->VddMemVrMapping);
1911         pr_info("BoardVrMapping = 0x%x\n", pptable->BoardVrMapping);
1912
1913         pr_info("GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
1914         pr_info("ExternalSensorPresent = 0x%x\n", pptable->ExternalSensorPresent);
1915
1916         pr_info("GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
1917         pr_info("GfxOffset = 0x%x\n", pptable->GfxOffset);
1918         pr_info("Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
1919
1920         pr_info("SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
1921         pr_info("SocOffset = 0x%x\n", pptable->SocOffset);
1922         pr_info("Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
1923
1924         pr_info("MemMaxCurrent = 0x%x\n", pptable->MemMaxCurrent);
1925         pr_info("MemOffset = 0x%x\n", pptable->MemOffset);
1926         pr_info("Padding_TelemetryMem = 0x%x\n", pptable->Padding_TelemetryMem);
1927
1928         pr_info("BoardMaxCurrent = 0x%x\n", pptable->BoardMaxCurrent);
1929         pr_info("BoardOffset = 0x%x\n", pptable->BoardOffset);
1930         pr_info("Padding_TelemetryBoardInput = 0x%x\n", pptable->Padding_TelemetryBoardInput);
1931
1932         pr_info("VR0HotGpio = %d\n", pptable->VR0HotGpio);
1933         pr_info("VR0HotPolarity = %d\n", pptable->VR0HotPolarity);
1934         pr_info("VR1HotGpio = %d\n", pptable->VR1HotGpio);
1935         pr_info("VR1HotPolarity = %d\n", pptable->VR1HotPolarity);
1936
1937         pr_info("PllGfxclkSpreadEnabled = %d\n", pptable->PllGfxclkSpreadEnabled);
1938         pr_info("PllGfxclkSpreadPercent = %d\n", pptable->PllGfxclkSpreadPercent);
1939         pr_info("PllGfxclkSpreadFreq = %d\n", pptable->PllGfxclkSpreadFreq);
1940
1941         pr_info("UclkSpreadEnabled = %d\n", pptable->UclkSpreadEnabled);
1942         pr_info("UclkSpreadPercent = %d\n", pptable->UclkSpreadPercent);
1943         pr_info("UclkSpreadFreq = %d\n", pptable->UclkSpreadFreq);
1944
1945         pr_info("FclkSpreadEnabled = %d\n", pptable->FclkSpreadEnabled);
1946         pr_info("FclkSpreadPercent = %d\n", pptable->FclkSpreadPercent);
1947         pr_info("FclkSpreadFreq = %d\n", pptable->FclkSpreadFreq);
1948
1949         pr_info("FllGfxclkSpreadEnabled = %d\n", pptable->FllGfxclkSpreadEnabled);
1950         pr_info("FllGfxclkSpreadPercent = %d\n", pptable->FllGfxclkSpreadPercent);
1951         pr_info("FllGfxclkSpreadFreq = %d\n", pptable->FllGfxclkSpreadFreq);
1952
1953         for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
1954                 pr_info("I2cControllers[%d]:\n", i);
1955                 pr_info("                   .Enabled = %d\n",
1956                                 pptable->I2cControllers[i].Enabled);
1957                 pr_info("                   .SlaveAddress = 0x%x\n",
1958                                 pptable->I2cControllers[i].SlaveAddress);
1959                 pr_info("                   .ControllerPort = %d\n",
1960                                 pptable->I2cControllers[i].ControllerPort);
1961                 pr_info("                   .ControllerName = %d\n",
1962                                 pptable->I2cControllers[i].ControllerName);
1963                 pr_info("                   .ThermalThrottler = %d\n",
1964                                 pptable->I2cControllers[i].ThermalThrotter);
1965                 pr_info("                   .I2cProtocol = %d\n",
1966                                 pptable->I2cControllers[i].I2cProtocol);
1967                 pr_info("                   .Speed = %d\n",
1968                                 pptable->I2cControllers[i].Speed);
1969         }
1970
1971         pr_info("MemoryChannelEnabled = %d\n", pptable->MemoryChannelEnabled);
1972         pr_info("DramBitWidth = %d\n", pptable->DramBitWidth);
1973
1974         pr_info("TotalBoardPower = %d\n", pptable->TotalBoardPower);
1975
1976         pr_info("XgmiLinkSpeed\n");
1977         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
1978                 pr_info("  .[%d] = %d\n", i, pptable->XgmiLinkSpeed[i]);
1979         pr_info("XgmiLinkWidth\n");
1980         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
1981                 pr_info("  .[%d] = %d\n", i, pptable->XgmiLinkWidth[i]);
1982         pr_info("XgmiFclkFreq\n");
1983         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
1984                 pr_info("  .[%d] = %d\n", i, pptable->XgmiFclkFreq[i]);
1985         pr_info("XgmiSocVoltage\n");
1986         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
1987                 pr_info("  .[%d] = %d\n", i, pptable->XgmiSocVoltage[i]);
1988
1989 }
1990
1991 static bool arcturus_is_dpm_running(struct smu_context *smu)
1992 {
1993         int ret = 0;
1994         uint32_t feature_mask[2];
1995         unsigned long feature_enabled;
1996         ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
1997         feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
1998                            ((uint64_t)feature_mask[1] << 32));
1999         return !!(feature_enabled & SMC_DPM_FEATURE);
2000 }
2001
2002 static int arcturus_dpm_set_uvd_enable(struct smu_context *smu, bool enable)
2003 {
2004         struct smu_power_context *smu_power = &smu->smu_power;
2005         struct smu_power_gate *power_gate = &smu_power->power_gate;
2006         int ret = 0;
2007
2008         if (enable) {
2009                 if (!smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
2010                         ret = smu_feature_set_enabled(smu, SMU_FEATURE_VCN_PG_BIT, 1);
2011                         if (ret) {
2012                                 pr_err("[EnableVCNDPM] failed!\n");
2013                                 return ret;
2014                         }
2015                 }
2016                 power_gate->vcn_gated = false;
2017         } else {
2018                 if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
2019                         ret = smu_feature_set_enabled(smu, SMU_FEATURE_VCN_PG_BIT, 0);
2020                         if (ret) {
2021                                 pr_err("[DisableVCNDPM] failed!\n");
2022                                 return ret;
2023                         }
2024                 }
2025                 power_gate->vcn_gated = true;
2026         }
2027
2028         return ret;
2029 }
2030
2031
2032 static void arcturus_fill_eeprom_i2c_req(SwI2cRequest_t  *req, bool write,
2033                                   uint8_t address, uint32_t numbytes,
2034                                   uint8_t *data)
2035 {
2036         int i;
2037
2038         BUG_ON(numbytes > MAX_SW_I2C_COMMANDS);
2039
2040         req->I2CcontrollerPort = 0;
2041         req->I2CSpeed = 2;
2042         req->SlaveAddress = address;
2043         req->NumCmds = numbytes;
2044
2045         for (i = 0; i < numbytes; i++) {
2046                 SwI2cCmd_t *cmd =  &req->SwI2cCmds[i];
2047
2048                 /* First 2 bytes are always write for lower 2b EEPROM address */
2049                 if (i < 2)
2050                         cmd->Cmd = 1;
2051                 else
2052                         cmd->Cmd = write;
2053
2054
2055                 /* Add RESTART for read  after address filled */
2056                 cmd->CmdConfig |= (i == 2 && !write) ? CMDCONFIG_RESTART_MASK : 0;
2057
2058                 /* Add STOP in the end */
2059                 cmd->CmdConfig |= (i == (numbytes - 1)) ? CMDCONFIG_STOP_MASK : 0;
2060
2061                 /* Fill with data regardless if read or write to simplify code */
2062                 cmd->RegisterAddr = data[i];
2063         }
2064 }
2065
2066 static int arcturus_i2c_eeprom_read_data(struct i2c_adapter *control,
2067                                                uint8_t address,
2068                                                uint8_t *data,
2069                                                uint32_t numbytes)
2070 {
2071         uint32_t  i, ret = 0;
2072         SwI2cRequest_t req;
2073         struct amdgpu_device *adev = to_amdgpu_device(control);
2074         struct smu_table_context *smu_table = &adev->smu.smu_table;
2075         struct smu_table *table = &smu_table->driver_table;
2076
2077         memset(&req, 0, sizeof(req));
2078         arcturus_fill_eeprom_i2c_req(&req, false, address, numbytes, data);
2079
2080         mutex_lock(&adev->smu.mutex);
2081         /* Now read data starting with that address */
2082         ret = smu_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, &req,
2083                                         true);
2084         mutex_unlock(&adev->smu.mutex);
2085
2086         if (!ret) {
2087                 SwI2cRequest_t *res = (SwI2cRequest_t *)table->cpu_addr;
2088
2089                 /* Assume SMU  fills res.SwI2cCmds[i].Data with read bytes */
2090                 for (i = 0; i < numbytes; i++)
2091                         data[i] = res->SwI2cCmds[i].Data;
2092
2093                 pr_debug("arcturus_i2c_eeprom_read_data, address = %x, bytes = %d, data :",
2094                                   (uint16_t)address, numbytes);
2095
2096                 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_NONE,
2097                                8, 1, data, numbytes, false);
2098         } else
2099                 pr_err("arcturus_i2c_eeprom_read_data - error occurred :%x", ret);
2100
2101         return ret;
2102 }
2103
2104 static int arcturus_i2c_eeprom_write_data(struct i2c_adapter *control,
2105                                                 uint8_t address,
2106                                                 uint8_t *data,
2107                                                 uint32_t numbytes)
2108 {
2109         uint32_t ret;
2110         SwI2cRequest_t req;
2111         struct amdgpu_device *adev = to_amdgpu_device(control);
2112
2113         memset(&req, 0, sizeof(req));
2114         arcturus_fill_eeprom_i2c_req(&req, true, address, numbytes, data);
2115
2116         mutex_lock(&adev->smu.mutex);
2117         ret = smu_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, &req, true);
2118         mutex_unlock(&adev->smu.mutex);
2119
2120         if (!ret) {
2121                 pr_debug("arcturus_i2c_write(), address = %x, bytes = %d , data: ",
2122                                          (uint16_t)address, numbytes);
2123
2124                 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_NONE,
2125                                8, 1, data, numbytes, false);
2126                 /*
2127                  * According to EEPROM spec there is a MAX of 10 ms required for
2128                  * EEPROM to flush internal RX buffer after STOP was issued at the
2129                  * end of write transaction. During this time the EEPROM will not be
2130                  * responsive to any more commands - so wait a bit more.
2131                  */
2132                 msleep(10);
2133
2134         } else
2135                 pr_err("arcturus_i2c_write- error occurred :%x", ret);
2136
2137         return ret;
2138 }
2139
2140 static int arcturus_i2c_eeprom_i2c_xfer(struct i2c_adapter *i2c_adap,
2141                               struct i2c_msg *msgs, int num)
2142 {
2143         uint32_t  i, j, ret, data_size, data_chunk_size, next_eeprom_addr = 0;
2144         uint8_t *data_ptr, data_chunk[MAX_SW_I2C_COMMANDS] = { 0 };
2145
2146         for (i = 0; i < num; i++) {
2147                 /*
2148                  * SMU interface allows at most MAX_SW_I2C_COMMANDS bytes of data at
2149                  * once and hence the data needs to be spliced into chunks and sent each
2150                  * chunk separately
2151                  */
2152                 data_size = msgs[i].len - 2;
2153                 data_chunk_size = MAX_SW_I2C_COMMANDS - 2;
2154                 next_eeprom_addr = (msgs[i].buf[0] << 8 & 0xff00) | (msgs[i].buf[1] & 0xff);
2155                 data_ptr = msgs[i].buf + 2;
2156
2157                 for (j = 0; j < data_size / data_chunk_size; j++) {
2158                         /* Insert the EEPROM dest addess, bits 0-15 */
2159                         data_chunk[0] = ((next_eeprom_addr >> 8) & 0xff);
2160                         data_chunk[1] = (next_eeprom_addr & 0xff);
2161
2162                         if (msgs[i].flags & I2C_M_RD) {
2163                                 ret = arcturus_i2c_eeprom_read_data(i2c_adap,
2164                                                                 (uint8_t)msgs[i].addr,
2165                                                                 data_chunk, MAX_SW_I2C_COMMANDS);
2166
2167                                 memcpy(data_ptr, data_chunk + 2, data_chunk_size);
2168                         } else {
2169
2170                                 memcpy(data_chunk + 2, data_ptr, data_chunk_size);
2171
2172                                 ret = arcturus_i2c_eeprom_write_data(i2c_adap,
2173                                                                  (uint8_t)msgs[i].addr,
2174                                                                  data_chunk, MAX_SW_I2C_COMMANDS);
2175                         }
2176
2177                         if (ret) {
2178                                 num = -EIO;
2179                                 goto fail;
2180                         }
2181
2182                         next_eeprom_addr += data_chunk_size;
2183                         data_ptr += data_chunk_size;
2184                 }
2185
2186                 if (data_size % data_chunk_size) {
2187                         data_chunk[0] = ((next_eeprom_addr >> 8) & 0xff);
2188                         data_chunk[1] = (next_eeprom_addr & 0xff);
2189
2190                         if (msgs[i].flags & I2C_M_RD) {
2191                                 ret = arcturus_i2c_eeprom_read_data(i2c_adap,
2192                                                                 (uint8_t)msgs[i].addr,
2193                                                                 data_chunk, (data_size % data_chunk_size) + 2);
2194
2195                                 memcpy(data_ptr, data_chunk + 2, data_size % data_chunk_size);
2196                         } else {
2197                                 memcpy(data_chunk + 2, data_ptr, data_size % data_chunk_size);
2198
2199                                 ret = arcturus_i2c_eeprom_write_data(i2c_adap,
2200                                                                  (uint8_t)msgs[i].addr,
2201                                                                  data_chunk, (data_size % data_chunk_size) + 2);
2202                         }
2203
2204                         if (ret) {
2205                                 num = -EIO;
2206                                 goto fail;
2207                         }
2208                 }
2209         }
2210
2211 fail:
2212         return num;
2213 }
2214
2215 static u32 arcturus_i2c_eeprom_i2c_func(struct i2c_adapter *adap)
2216 {
2217         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
2218 }
2219
2220
2221 static const struct i2c_algorithm arcturus_i2c_eeprom_i2c_algo = {
2222         .master_xfer = arcturus_i2c_eeprom_i2c_xfer,
2223         .functionality = arcturus_i2c_eeprom_i2c_func,
2224 };
2225
2226 static int arcturus_i2c_eeprom_control_init(struct i2c_adapter *control)
2227 {
2228         struct amdgpu_device *adev = to_amdgpu_device(control);
2229         struct smu_context *smu = &adev->smu;
2230         int res;
2231
2232         if (!smu->pm_enabled)
2233                 return -EOPNOTSUPP;
2234
2235         control->owner = THIS_MODULE;
2236         control->class = I2C_CLASS_SPD;
2237         control->dev.parent = &adev->pdev->dev;
2238         control->algo = &arcturus_i2c_eeprom_i2c_algo;
2239         snprintf(control->name, sizeof(control->name), "AMDGPU EEPROM");
2240
2241         res = i2c_add_adapter(control);
2242         if (res)
2243                 DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
2244
2245         return res;
2246 }
2247
2248 static void arcturus_i2c_eeprom_control_fini(struct i2c_adapter *control)
2249 {
2250         struct amdgpu_device *adev = to_amdgpu_device(control);
2251         struct smu_context *smu = &adev->smu;
2252
2253         if (!smu->pm_enabled)
2254                 return;
2255
2256         i2c_del_adapter(control);
2257 }
2258
2259 static bool arcturus_is_baco_supported(struct smu_context *smu)
2260 {
2261         struct amdgpu_device *adev = smu->adev;
2262         uint32_t val;
2263
2264         if (!smu_v11_0_baco_is_support(smu))
2265                 return false;
2266
2267         val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
2268         return (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true : false;
2269 }
2270
2271 static uint32_t arcturus_get_pptable_power_limit(struct smu_context *smu)
2272 {
2273         PPTable_t *pptable = smu->smu_table.driver_pptable;
2274
2275         return pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
2276 }
2277
2278 static int arcturus_set_df_cstate(struct smu_context *smu,
2279                                   enum pp_df_cstate state)
2280 {
2281         uint32_t smu_version;
2282         int ret;
2283
2284         ret = smu_get_smc_version(smu, NULL, &smu_version);
2285         if (ret) {
2286                 pr_err("Failed to get smu version!\n");
2287                 return ret;
2288         }
2289
2290         /* PPSMC_MSG_DFCstateControl is supported by 54.15.0 and onwards */
2291         if (smu_version < 0x360F00) {
2292                 pr_err("DFCstateControl is only supported by PMFW 54.15.0 and onwards\n");
2293                 return -EINVAL;
2294         }
2295
2296         return smu_send_smc_msg_with_param(smu, SMU_MSG_DFCstateControl, state, NULL);
2297 }
2298
2299 static const struct pptable_funcs arcturus_ppt_funcs = {
2300         /* translate smu index into arcturus specific index */
2301         .get_smu_msg_index = arcturus_get_smu_msg_index,
2302         .get_smu_clk_index = arcturus_get_smu_clk_index,
2303         .get_smu_feature_index = arcturus_get_smu_feature_index,
2304         .get_smu_table_index = arcturus_get_smu_table_index,
2305         .get_smu_power_index= arcturus_get_pwr_src_index,
2306         .get_workload_type = arcturus_get_workload_type,
2307         /* internal structurs allocations */
2308         .tables_init = arcturus_tables_init,
2309         .alloc_dpm_context = arcturus_allocate_dpm_context,
2310         /* pptable related */
2311         .check_powerplay_table = arcturus_check_powerplay_table,
2312         .store_powerplay_table = arcturus_store_powerplay_table,
2313         .append_powerplay_table = arcturus_append_powerplay_table,
2314         /* init dpm */
2315         .get_allowed_feature_mask = arcturus_get_allowed_feature_mask,
2316         /* btc */
2317         .run_btc = arcturus_run_btc,
2318         /* dpm/clk tables */
2319         .set_default_dpm_table = arcturus_set_default_dpm_table,
2320         .populate_umd_state_clk = arcturus_populate_umd_state_clk,
2321         .get_thermal_temperature_range = arcturus_get_thermal_temperature_range,
2322         .get_current_clk_freq_by_table = arcturus_get_current_clk_freq_by_table,
2323         .print_clk_levels = arcturus_print_clk_levels,
2324         .force_clk_levels = arcturus_force_clk_levels,
2325         .read_sensor = arcturus_read_sensor,
2326         .get_fan_speed_percent = arcturus_get_fan_speed_percent,
2327         .get_fan_speed_rpm = arcturus_get_fan_speed_rpm,
2328         .force_dpm_limit_value = arcturus_force_dpm_limit_value,
2329         .unforce_dpm_levels = arcturus_unforce_dpm_levels,
2330         .get_profiling_clk_mask = arcturus_get_profiling_clk_mask,
2331         .get_power_profile_mode = arcturus_get_power_profile_mode,
2332         .set_power_profile_mode = arcturus_set_power_profile_mode,
2333         .set_performance_level = arcturus_set_performance_level,
2334         /* debug (internal used) */
2335         .dump_pptable = arcturus_dump_pptable,
2336         .get_power_limit = arcturus_get_power_limit,
2337         .is_dpm_running = arcturus_is_dpm_running,
2338         .dpm_set_uvd_enable = arcturus_dpm_set_uvd_enable,
2339         .i2c_eeprom_init = arcturus_i2c_eeprom_control_init,
2340         .i2c_eeprom_fini = arcturus_i2c_eeprom_control_fini,
2341         .init_microcode = smu_v11_0_init_microcode,
2342         .load_microcode = smu_v11_0_load_microcode,
2343         .init_smc_tables = smu_v11_0_init_smc_tables,
2344         .fini_smc_tables = smu_v11_0_fini_smc_tables,
2345         .init_power = smu_v11_0_init_power,
2346         .fini_power = smu_v11_0_fini_power,
2347         .check_fw_status = smu_v11_0_check_fw_status,
2348         .setup_pptable = smu_v11_0_setup_pptable,
2349         .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
2350         .get_clk_info_from_vbios = smu_v11_0_get_clk_info_from_vbios,
2351         .check_pptable = smu_v11_0_check_pptable,
2352         .parse_pptable = smu_v11_0_parse_pptable,
2353         .populate_smc_tables = smu_v11_0_populate_smc_pptable,
2354         .check_fw_version = smu_v11_0_check_fw_version,
2355         .write_pptable = smu_v11_0_write_pptable,
2356         .set_min_dcef_deep_sleep = smu_v11_0_set_min_dcef_deep_sleep,
2357         .set_driver_table_location = smu_v11_0_set_driver_table_location,
2358         .set_tool_table_location = smu_v11_0_set_tool_table_location,
2359         .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
2360         .system_features_control = smu_v11_0_system_features_control,
2361         .send_smc_msg_with_param = smu_v11_0_send_msg_with_param,
2362         .init_display_count = smu_v11_0_init_display_count,
2363         .set_allowed_mask = smu_v11_0_set_allowed_mask,
2364         .get_enabled_mask = smu_v11_0_get_enabled_mask,
2365         .notify_display_change = smu_v11_0_notify_display_change,
2366         .set_power_limit = smu_v11_0_set_power_limit,
2367         .get_current_clk_freq = smu_v11_0_get_current_clk_freq,
2368         .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
2369         .start_thermal_control = smu_v11_0_start_thermal_control,
2370         .stop_thermal_control = smu_v11_0_stop_thermal_control,
2371         .set_deep_sleep_dcefclk = smu_v11_0_set_deep_sleep_dcefclk,
2372         .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
2373         .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
2374         .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
2375         .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
2376         .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
2377         .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
2378         .gfx_off_control = smu_v11_0_gfx_off_control,
2379         .register_irq_handler = smu_v11_0_register_irq_handler,
2380         .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
2381         .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
2382         .baco_is_support= arcturus_is_baco_supported,
2383         .baco_get_state = smu_v11_0_baco_get_state,
2384         .baco_set_state = smu_v11_0_baco_set_state,
2385         .baco_enter = smu_v11_0_baco_enter,
2386         .baco_exit = smu_v11_0_baco_exit,
2387         .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
2388         .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
2389         .override_pcie_parameters = smu_v11_0_override_pcie_parameters,
2390         .get_pptable_power_limit = arcturus_get_pptable_power_limit,
2391         .set_df_cstate = arcturus_set_df_cstate,
2392 };
2393
2394 void arcturus_set_ppt_funcs(struct smu_context *smu)
2395 {
2396         smu->ppt_funcs = &arcturus_ppt_funcs;
2397 }