drivers/gpu/drm/amd/powerplay/arcturus_ppt.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include "amdgpu.h"
  26 #include "amdgpu_smu.h"
  27 #include "smu_internal.h"
  28 #include "atomfirmware.h"
  29 #include "amdgpu_atomfirmware.h"
  30 #include "smu_v11_0.h"
  31 #include "smu11_driver_if_arcturus.h"
  32 #include "soc15_common.h"
  33 #include "atom.h"
  34 #include "power_state.h"
  35 #include "arcturus_ppt.h"
  36 #include "smu_v11_0_pptable.h"
  37 #include "arcturus_ppsmc.h"
  38 #include "nbio/nbio_7_4_offset.h"
  39 #include "nbio/nbio_7_4_sh_mask.h"
  40 #include "amdgpu_xgmi.h"
  41 #include <linux/i2c.h>
  42 #include <linux/pci.h>
  43 #include "amdgpu_ras.h"
  44
  45 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c))
  46
  47 #define CTF_OFFSET_EDGE                 5
  48 #define CTF_OFFSET_HOTSPOT              5
  49 #define CTF_OFFSET_HBM                  5
  50
  51 #define MSG_MAP(msg, index) \
  52         [SMU_MSG_##msg] = {1, (index)}
  53 #define ARCTURUS_FEA_MAP(smu_feature, arcturus_feature) \
  54         [smu_feature] = {1, (arcturus_feature)}
  55
  56 #define SMU_FEATURES_LOW_MASK        0x00000000FFFFFFFF
  57 #define SMU_FEATURES_LOW_SHIFT       0
  58 #define SMU_FEATURES_HIGH_MASK       0xFFFFFFFF00000000
  59 #define SMU_FEATURES_HIGH_SHIFT      32
  60
  61 #define SMC_DPM_FEATURE ( \
  62         FEATURE_DPM_PREFETCHER_MASK | \
  63         FEATURE_DPM_GFXCLK_MASK | \
  64         FEATURE_DPM_UCLK_MASK | \
  65         FEATURE_DPM_SOCCLK_MASK | \
  66         FEATURE_DPM_MP0CLK_MASK | \
  67         FEATURE_DPM_FCLK_MASK | \
  68         FEATURE_DPM_XGMI_MASK)
  69
  70 /* possible frequency drift (1Mhz) */
  71 #define EPSILON                         1
  72
  73 static struct smu_11_0_cmn2aisc_mapping arcturus_message_map[SMU_MSG_MAX_COUNT] = {
  74         MSG_MAP(TestMessage,                         PPSMC_MSG_TestMessage),
  75         MSG_MAP(GetSmuVersion,                       PPSMC_MSG_GetSmuVersion),
  76         MSG_MAP(GetDriverIfVersion,                  PPSMC_MSG_GetDriverIfVersion),
  77         MSG_MAP(SetAllowedFeaturesMaskLow,           PPSMC_MSG_SetAllowedFeaturesMaskLow),
  78         MSG_MAP(SetAllowedFeaturesMaskHigh,          PPSMC_MSG_SetAllowedFeaturesMaskHigh),
  79         MSG_MAP(EnableAllSmuFeatures,                PPSMC_MSG_EnableAllSmuFeatures),
  80         MSG_MAP(DisableAllSmuFeatures,               PPSMC_MSG_DisableAllSmuFeatures),
  81         MSG_MAP(EnableSmuFeaturesLow,                PPSMC_MSG_EnableSmuFeaturesLow),
  82         MSG_MAP(EnableSmuFeaturesHigh,               PPSMC_MSG_EnableSmuFeaturesHigh),
  83         MSG_MAP(DisableSmuFeaturesLow,               PPSMC_MSG_DisableSmuFeaturesLow),
  84         MSG_MAP(DisableSmuFeaturesHigh,              PPSMC_MSG_DisableSmuFeaturesHigh),
  85         MSG_MAP(GetEnabledSmuFeaturesLow,            PPSMC_MSG_GetEnabledSmuFeaturesLow),
  86         MSG_MAP(GetEnabledSmuFeaturesHigh,           PPSMC_MSG_GetEnabledSmuFeaturesHigh),
  87         MSG_MAP(SetDriverDramAddrHigh,               PPSMC_MSG_SetDriverDramAddrHigh),
  88         MSG_MAP(SetDriverDramAddrLow,                PPSMC_MSG_SetDriverDramAddrLow),
  89         MSG_MAP(SetToolsDramAddrHigh,                PPSMC_MSG_SetToolsDramAddrHigh),
  90         MSG_MAP(SetToolsDramAddrLow,                 PPSMC_MSG_SetToolsDramAddrLow),
  91         MSG_MAP(TransferTableSmu2Dram,               PPSMC_MSG_TransferTableSmu2Dram),
  92         MSG_MAP(TransferTableDram2Smu,               PPSMC_MSG_TransferTableDram2Smu),
  93         MSG_MAP(UseDefaultPPTable,                   PPSMC_MSG_UseDefaultPPTable),
  94         MSG_MAP(UseBackupPPTable,                    PPSMC_MSG_UseBackupPPTable),
  95         MSG_MAP(SetSystemVirtualDramAddrHigh,        PPSMC_MSG_SetSystemVirtualDramAddrHigh),
  96         MSG_MAP(SetSystemVirtualDramAddrLow,         PPSMC_MSG_SetSystemVirtualDramAddrLow),
  97         MSG_MAP(EnterBaco,                           PPSMC_MSG_EnterBaco),
  98         MSG_MAP(ExitBaco,                            PPSMC_MSG_ExitBaco),
  99         MSG_MAP(ArmD3,                               PPSMC_MSG_ArmD3),
 100         MSG_MAP(SetSoftMinByFreq,                    PPSMC_MSG_SetSoftMinByFreq),
 101         MSG_MAP(SetSoftMaxByFreq,                    PPSMC_MSG_SetSoftMaxByFreq),
 102         MSG_MAP(SetHardMinByFreq,                    PPSMC_MSG_SetHardMinByFreq),
 103         MSG_MAP(SetHardMaxByFreq,                    PPSMC_MSG_SetHardMaxByFreq),
 104         MSG_MAP(GetMinDpmFreq,                       PPSMC_MSG_GetMinDpmFreq),
 105         MSG_MAP(GetMaxDpmFreq,                       PPSMC_MSG_GetMaxDpmFreq),
 106         MSG_MAP(GetDpmFreqByIndex,                   PPSMC_MSG_GetDpmFreqByIndex),
 107         MSG_MAP(SetWorkloadMask,                     PPSMC_MSG_SetWorkloadMask),
 108         MSG_MAP(SetDfSwitchType,                     PPSMC_MSG_SetDfSwitchType),
 109         MSG_MAP(GetVoltageByDpm,                     PPSMC_MSG_GetVoltageByDpm),
 110         MSG_MAP(GetVoltageByDpmOverdrive,            PPSMC_MSG_GetVoltageByDpmOverdrive),
 111         MSG_MAP(SetPptLimit,                         PPSMC_MSG_SetPptLimit),
 112         MSG_MAP(GetPptLimit,                         PPSMC_MSG_GetPptLimit),
 113         MSG_MAP(PowerUpVcn0,                         PPSMC_MSG_PowerUpVcn0),
 114         MSG_MAP(PowerDownVcn0,                       PPSMC_MSG_PowerDownVcn0),
 115         MSG_MAP(PowerUpVcn1,                         PPSMC_MSG_PowerUpVcn1),
 116         MSG_MAP(PowerDownVcn1,                       PPSMC_MSG_PowerDownVcn1),
 117         MSG_MAP(PrepareMp1ForUnload,                 PPSMC_MSG_PrepareMp1ForUnload),
 118         MSG_MAP(PrepareMp1ForReset,                  PPSMC_MSG_PrepareMp1ForReset),
 119         MSG_MAP(PrepareMp1ForShutdown,               PPSMC_MSG_PrepareMp1ForShutdown),
 120         MSG_MAP(SoftReset,                           PPSMC_MSG_SoftReset),
 121         MSG_MAP(RunAfllBtc,                          PPSMC_MSG_RunAfllBtc),
 122         MSG_MAP(RunDcBtc,                            PPSMC_MSG_RunDcBtc),
 123         MSG_MAP(DramLogSetDramAddrHigh,              PPSMC_MSG_DramLogSetDramAddrHigh),
 124         MSG_MAP(DramLogSetDramAddrLow,               PPSMC_MSG_DramLogSetDramAddrLow),
 125         MSG_MAP(DramLogSetDramSize,                  PPSMC_MSG_DramLogSetDramSize),
 126         MSG_MAP(GetDebugData,                        PPSMC_MSG_GetDebugData),
 127         MSG_MAP(WaflTest,                            PPSMC_MSG_WaflTest),
 128         MSG_MAP(SetXgmiMode,                         PPSMC_MSG_SetXgmiMode),
 129         MSG_MAP(SetMemoryChannelEnable,              PPSMC_MSG_SetMemoryChannelEnable),
 130         MSG_MAP(DFCstateControl,                     PPSMC_MSG_DFCstateControl),
 131 };
 132
 133 static struct smu_11_0_cmn2aisc_mapping arcturus_clk_map[SMU_CLK_COUNT] = {
 134         CLK_MAP(GFXCLK, PPCLK_GFXCLK),
 135         CLK_MAP(SCLK,   PPCLK_GFXCLK),
 136         CLK_MAP(SOCCLK, PPCLK_SOCCLK),
 137         CLK_MAP(FCLK, PPCLK_FCLK),
 138         CLK_MAP(UCLK, PPCLK_UCLK),
 139         CLK_MAP(MCLK, PPCLK_UCLK),
 140         CLK_MAP(DCLK, PPCLK_DCLK),
 141         CLK_MAP(VCLK, PPCLK_VCLK),
 142 };
 143
 144 static struct smu_11_0_cmn2aisc_mapping arcturus_feature_mask_map[SMU_FEATURE_COUNT] = {
 145         FEA_MAP(DPM_PREFETCHER),
 146         FEA_MAP(DPM_GFXCLK),
 147         FEA_MAP(DPM_UCLK),
 148         FEA_MAP(DPM_SOCCLK),
 149         FEA_MAP(DPM_FCLK),
 150         FEA_MAP(DPM_MP0CLK),
 151         ARCTURUS_FEA_MAP(SMU_FEATURE_XGMI_BIT, FEATURE_DPM_XGMI_BIT),
 152         FEA_MAP(DS_GFXCLK),
 153         FEA_MAP(DS_SOCCLK),
 154         FEA_MAP(DS_LCLK),
 155         FEA_MAP(DS_FCLK),
 156         FEA_MAP(DS_UCLK),
 157         FEA_MAP(GFX_ULV),
 158         ARCTURUS_FEA_MAP(SMU_FEATURE_VCN_PG_BIT, FEATURE_DPM_VCN_BIT),
 159         FEA_MAP(RSMU_SMN_CG),
 160         FEA_MAP(WAFL_CG),
 161         FEA_MAP(PPT),
 162         FEA_MAP(TDC),
 163         FEA_MAP(APCC_PLUS),
 164         FEA_MAP(VR0HOT),
 165         FEA_MAP(VR1HOT),
 166         FEA_MAP(FW_CTF),
 167         FEA_MAP(FAN_CONTROL),
 168         FEA_MAP(THERMAL),
 169         FEA_MAP(OUT_OF_BAND_MONITOR),
 170         FEA_MAP(TEMP_DEPENDENT_VMIN),
 171 };
 172
 173 static struct smu_11_0_cmn2aisc_mapping arcturus_table_map[SMU_TABLE_COUNT] = {
 174         TAB_MAP(PPTABLE),
 175         TAB_MAP(AVFS),
 176         TAB_MAP(AVFS_PSM_DEBUG),
 177         TAB_MAP(AVFS_FUSE_OVERRIDE),
 178         TAB_MAP(PMSTATUSLOG),
 179         TAB_MAP(SMU_METRICS),
 180         TAB_MAP(DRIVER_SMU_CONFIG),
 181         TAB_MAP(OVERDRIVE),
 182         TAB_MAP(I2C_COMMANDS),
 183         TAB_MAP(ACTIVITY_MONITOR_COEFF),
 184 };
 185
 186 static struct smu_11_0_cmn2aisc_mapping arcturus_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
 187         PWR_MAP(AC),
 188         PWR_MAP(DC),
 189 };
 190
 191 static struct smu_11_0_cmn2aisc_mapping arcturus_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
 192         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT,       WORKLOAD_PPLIB_DEFAULT_BIT),
 193         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING,          WORKLOAD_PPLIB_POWER_SAVING_BIT),
 194         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO,                WORKLOAD_PPLIB_VIDEO_BIT),
 195         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE,              WORKLOAD_PPLIB_COMPUTE_BIT),
 196         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,               WORKLOAD_PPLIB_CUSTOM_BIT),
 197 };
 198
 199 static int arcturus_get_smu_msg_index(struct smu_context *smc, uint32_t index)
 200 {
 201         struct smu_11_0_cmn2aisc_mapping mapping;
 202
 203         if (index >= SMU_MSG_MAX_COUNT)
 204                 return -EINVAL;
 205
 206         mapping = arcturus_message_map[index];
 207         if (!(mapping.valid_mapping))
 208                 return -EINVAL;
 209
 210         return mapping.map_to;
 211 }
 212
 213 static int arcturus_get_smu_clk_index(struct smu_context *smc, uint32_t index)
 214 {
 215         struct smu_11_0_cmn2aisc_mapping mapping;
 216
 217         if (index >= SMU_CLK_COUNT)
 218                 return -EINVAL;
 219
 220         mapping = arcturus_clk_map[index];
 221         if (!(mapping.valid_mapping)) {
 222                 pr_warn("Unsupported SMU clk: %d\n", index);
 223                 return -EINVAL;
 224         }
 225
 226         return mapping.map_to;
 227 }
 228
 229 static int arcturus_get_smu_feature_index(struct smu_context *smc, uint32_t index)
 230 {
 231         struct smu_11_0_cmn2aisc_mapping mapping;
 232
 233         if (index >= SMU_FEATURE_COUNT)
 234                 return -EINVAL;
 235
 236         mapping = arcturus_feature_mask_map[index];
 237         if (!(mapping.valid_mapping)) {
 238                 return -EINVAL;
 239         }
 240
 241         return mapping.map_to;
 242 }
 243
 244 static int arcturus_get_smu_table_index(struct smu_context *smc, uint32_t index)
 245 {
 246         struct smu_11_0_cmn2aisc_mapping mapping;
 247
 248         if (index >= SMU_TABLE_COUNT)
 249                 return -EINVAL;
 250
 251         mapping = arcturus_table_map[index];
 252         if (!(mapping.valid_mapping)) {
 253                 pr_warn("Unsupported SMU table: %d\n", index);
 254                 return -EINVAL;
 255         }
 256
 257         return mapping.map_to;
 258 }
 259
 260 static int arcturus_get_pwr_src_index(struct smu_context *smc, uint32_t index)
 261 {
 262         struct smu_11_0_cmn2aisc_mapping mapping;
 263
 264         if (index >= SMU_POWER_SOURCE_COUNT)
 265                 return -EINVAL;
 266
 267         mapping = arcturus_pwr_src_map[index];
 268         if (!(mapping.valid_mapping)) {
 269                 pr_warn("Unsupported SMU power source: %d\n", index);
 270                 return -EINVAL;
 271         }
 272
 273         return mapping.map_to;
 274 }
 275
 276
 277 static int arcturus_get_workload_type(struct smu_context *smu, enum PP_SMC_POWER_PROFILE profile)
 278 {
 279         struct smu_11_0_cmn2aisc_mapping mapping;
 280
 281         if (profile > PP_SMC_POWER_PROFILE_CUSTOM)
 282                 return -EINVAL;
 283
 284         mapping = arcturus_workload_map[profile];
 285         if (!(mapping.valid_mapping))
 286                 return -EINVAL;
 287
 288         return mapping.map_to;
 289 }
 290
 291 static int arcturus_tables_init(struct smu_context *smu, struct smu_table *tables)
 292 {
 293         struct smu_table_context *smu_table = &smu->smu_table;
 294
 295         SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
 296                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 297
 298         SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
 299                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 300
 301         SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
 302                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 303
 304         SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
 305                                PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 306
 307         SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
 308                        sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE,
 309                        AMDGPU_GEM_DOMAIN_VRAM);
 310
 311         smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
 312         if (!smu_table->metrics_table)
 313                 return -ENOMEM;
 314         smu_table->metrics_time = 0;
 315
 316         return 0;
 317 }
 318
 319 static int arcturus_allocate_dpm_context(struct smu_context *smu)
 320 {
 321         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 322
 323         if (smu_dpm->dpm_context)
 324                 return -EINVAL;
 325
 326         smu_dpm->dpm_context = kzalloc(sizeof(struct arcturus_dpm_table),
 327                                        GFP_KERNEL);
 328         if (!smu_dpm->dpm_context)
 329                 return -ENOMEM;
 330
 331         if (smu_dpm->golden_dpm_context)
 332                 return -EINVAL;
 333
 334         smu_dpm->golden_dpm_context = kzalloc(sizeof(struct arcturus_dpm_table),
 335                                               GFP_KERNEL);
 336         if (!smu_dpm->golden_dpm_context)
 337                 return -ENOMEM;
 338
 339         smu_dpm->dpm_context_size = sizeof(struct arcturus_dpm_table);
 340
 341         smu_dpm->dpm_current_power_state = kzalloc(sizeof(struct smu_power_state),
 342                                        GFP_KERNEL);
 343         if (!smu_dpm->dpm_current_power_state)
 344                 return -ENOMEM;
 345
 346         smu_dpm->dpm_request_power_state = kzalloc(sizeof(struct smu_power_state),
 347                                        GFP_KERNEL);
 348         if (!smu_dpm->dpm_request_power_state)
 349                 return -ENOMEM;
 350
 351         return 0;
 352 }
 353
 354 static int
 355 arcturus_get_allowed_feature_mask(struct smu_context *smu,
 356                                   uint32_t *feature_mask, uint32_t num)
 357 {
 358         if (num > 2)
 359                 return -EINVAL;
 360
 361         /* pptable will handle the features to enable */
 362         memset(feature_mask, 0xFF, sizeof(uint32_t) * num);
 363
 364         return 0;
 365 }
 366
 367 static int
 368 arcturus_set_single_dpm_table(struct smu_context *smu,
 369                             struct arcturus_single_dpm_table *single_dpm_table,
 370                             PPCLK_e clk_id)
 371 {
 372         int ret = 0;
 373         uint32_t i, num_of_levels = 0, clk;
 374
 375         ret = smu_send_smc_msg_with_param(smu,
 376                         SMU_MSG_GetDpmFreqByIndex,
 377                         (clk_id << 16 | 0xFF),
 378                         &num_of_levels);
 379         if (ret) {
 380                 pr_err("[%s] failed to get dpm levels!\n", __func__);
 381                 return ret;
 382         }
 383
 384         if (!num_of_levels) {
 385                 pr_err("[%s] number of clk levels is invalid!\n", __func__);
 386                 return -EINVAL;
 387         }
 388
 389         single_dpm_table->count = num_of_levels;
 390         for (i = 0; i < num_of_levels; i++) {
 391                 ret = smu_send_smc_msg_with_param(smu,
 392                                 SMU_MSG_GetDpmFreqByIndex,
 393                                 (clk_id << 16 | i),
 394                                 &clk);
 395                 if (ret) {
 396                         pr_err("[%s] failed to get dpm freq by index!\n", __func__);
 397                         return ret;
 398                 }
 399                 if (!clk) {
 400                         pr_err("[%s] clk value is invalid!\n", __func__);
 401                         return -EINVAL;
 402                 }
 403                 single_dpm_table->dpm_levels[i].value = clk;
 404                 single_dpm_table->dpm_levels[i].enabled = true;
 405         }
 406         return 0;
 407 }
 408
 409 static void arcturus_init_single_dpm_state(struct arcturus_dpm_state *dpm_state)
 410 {
 411         dpm_state->soft_min_level = 0x0;
 412         dpm_state->soft_max_level = 0xffff;
 413         dpm_state->hard_min_level = 0x0;
 414         dpm_state->hard_max_level = 0xffff;
 415 }
 416
 417 static int arcturus_set_default_dpm_table(struct smu_context *smu)
 418 {
 419         int ret;
 420
 421         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 422         struct arcturus_dpm_table *dpm_table = NULL;
 423         struct arcturus_single_dpm_table *single_dpm_table;
 424
 425         dpm_table = smu_dpm->dpm_context;
 426
 427         /* socclk */
 428         single_dpm_table = &(dpm_table->soc_table);
 429         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
 430                 ret = arcturus_set_single_dpm_table(smu, single_dpm_table,
 431                                                   PPCLK_SOCCLK);
 432                 if (ret) {
 433                         pr_err("[%s] failed to get socclk dpm levels!\n", __func__);
 434                         return ret;
 435                 }
 436         } else {
 437                 single_dpm_table->count = 1;
 438                 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
 439         }
 440         arcturus_init_single_dpm_state(&(single_dpm_table->dpm_state));
 441
 442         /* gfxclk */
 443         single_dpm_table = &(dpm_table->gfx_table);
 444         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
 445                 ret = arcturus_set_single_dpm_table(smu, single_dpm_table,
 446                                                   PPCLK_GFXCLK);
 447                 if (ret) {
 448                         pr_err("[SetupDefaultDpmTable] failed to get gfxclk dpm levels!");
 449                         return ret;
 450                 }
 451         } else {
 452                 single_dpm_table->count = 1;
 453                 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
 454         }
 455         arcturus_init_single_dpm_state(&(single_dpm_table->dpm_state));
 456
 457         /* memclk */
 458         single_dpm_table = &(dpm_table->mem_table);
 459         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 460                 ret = arcturus_set_single_dpm_table(smu, single_dpm_table,
 461                                                   PPCLK_UCLK);
 462                 if (ret) {
 463                         pr_err("[SetupDefaultDpmTable] failed to get memclk dpm levels!");
 464                         return ret;
 465                 }
 466         } else {
 467                 single_dpm_table->count = 1;
 468                 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
 469         }
 470         arcturus_init_single_dpm_state(&(single_dpm_table->dpm_state));
 471
 472         /* fclk */
 473         single_dpm_table = &(dpm_table->fclk_table);
 474         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
 475                 ret = arcturus_set_single_dpm_table(smu, single_dpm_table,
 476                                                   PPCLK_FCLK);
 477                 if (ret) {
 478                         pr_err("[SetupDefaultDpmTable] failed to get fclk dpm levels!");
 479                         return ret;
 480                 }
 481         } else {
 482                 single_dpm_table->count = 1;
 483                 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
 484         }
 485         arcturus_init_single_dpm_state(&(single_dpm_table->dpm_state));
 486
 487         memcpy(smu_dpm->golden_dpm_context, dpm_table,
 488                sizeof(struct arcturus_dpm_table));
 489
 490         return 0;
 491 }
 492
 493 static int arcturus_check_powerplay_table(struct smu_context *smu)
 494 {
 495         return 0;
 496 }
 497
 498 static int arcturus_store_powerplay_table(struct smu_context *smu)
 499 {
 500         struct smu_11_0_powerplay_table *powerplay_table = NULL;
 501         struct smu_table_context *table_context = &smu->smu_table;
 502         struct smu_baco_context *smu_baco = &smu->smu_baco;
 503         int ret = 0;
 504
 505         if (!table_context->power_play_table)
 506                 return -EINVAL;
 507
 508         powerplay_table = table_context->power_play_table;
 509
 510         memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
 511                sizeof(PPTable_t));
 512
 513         table_context->thermal_controller_type = powerplay_table->thermal_controller_type;
 514
 515         mutex_lock(&smu_baco->mutex);
 516         if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_BACO ||
 517             powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO)
 518                 smu_baco->platform_support = true;
 519         mutex_unlock(&smu_baco->mutex);
 520
 521         return ret;
 522 }
 523
 524 static int arcturus_append_powerplay_table(struct smu_context *smu)
 525 {
 526         struct smu_table_context *table_context = &smu->smu_table;
 527         PPTable_t *smc_pptable = table_context->driver_pptable;
 528         struct atom_smc_dpm_info_v4_6 *smc_dpm_table;
 529         int index, ret;
 530
 531         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 532                                            smc_dpm_info);
 533
 534         ret = smu_get_atom_data_table(smu, index, NULL, NULL, NULL,
 535                                       (uint8_t **)&smc_dpm_table);
 536         if (ret)
 537                 return ret;
 538
 539         pr_info("smc_dpm_info table revision(format.content): %d.%d\n",
 540                         smc_dpm_table->table_header.format_revision,
 541                         smc_dpm_table->table_header.content_revision);
 542
 543         if ((smc_dpm_table->table_header.format_revision == 4) &&
 544             (smc_dpm_table->table_header.content_revision == 6))
 545                 memcpy(&smc_pptable->MaxVoltageStepGfx,
 546                        &smc_dpm_table->maxvoltagestepgfx,
 547                        sizeof(*smc_dpm_table) - offsetof(struct atom_smc_dpm_info_v4_6, maxvoltagestepgfx));
 548
 549         return 0;
 550 }
 551
 552 static int arcturus_run_btc(struct smu_context *smu)
 553 {
 554         int ret = 0;
 555
 556         ret = smu_send_smc_msg(smu, SMU_MSG_RunAfllBtc, NULL);
 557         if (ret) {
 558                 pr_err("RunAfllBtc failed!\n");
 559                 return ret;
 560         }
 561
 562         return smu_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
 563 }
 564
 565 static int arcturus_populate_umd_state_clk(struct smu_context *smu)
 566 {
 567         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 568         struct arcturus_dpm_table *dpm_table = NULL;
 569         struct arcturus_single_dpm_table *gfx_table = NULL;
 570         struct arcturus_single_dpm_table *mem_table = NULL;
 571
 572         dpm_table = smu_dpm->dpm_context;
 573         gfx_table = &(dpm_table->gfx_table);
 574         mem_table = &(dpm_table->mem_table);
 575
 576         smu->pstate_sclk = gfx_table->dpm_levels[0].value;
 577         smu->pstate_mclk = mem_table->dpm_levels[0].value;
 578
 579         if (gfx_table->count > ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL &&
 580             mem_table->count > ARCTURUS_UMD_PSTATE_MCLK_LEVEL) {
 581                 smu->pstate_sclk = gfx_table->dpm_levels[ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL].value;
 582                 smu->pstate_mclk = mem_table->dpm_levels[ARCTURUS_UMD_PSTATE_MCLK_LEVEL].value;
 583         }
 584
 585         smu->pstate_sclk = smu->pstate_sclk * 100;
 586         smu->pstate_mclk = smu->pstate_mclk * 100;
 587
 588         return 0;
 589 }
 590
 591 static int arcturus_get_clk_table(struct smu_context *smu,
 592                         struct pp_clock_levels_with_latency *clocks,
 593                         struct arcturus_single_dpm_table *dpm_table)
 594 {
 595         int i, count;
 596
 597         count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
 598         clocks->num_levels = count;
 599
 600         for (i = 0; i < count; i++) {
 601                 clocks->data[i].clocks_in_khz =
 602                         dpm_table->dpm_levels[i].value * 1000;
 603                 clocks->data[i].latency_in_us = 0;
 604         }
 605
 606         return 0;
 607 }
 608
 609 static int arcturus_freqs_in_same_level(int32_t frequency1,
 610                                         int32_t frequency2)
 611 {
 612         return (abs(frequency1 - frequency2) <= EPSILON);
 613 }
 614
 615 static int arcturus_print_clk_levels(struct smu_context *smu,
 616                         enum smu_clk_type type, char *buf)
 617 {
 618         int i, now, size = 0;
 619         int ret = 0;
 620         struct pp_clock_levels_with_latency clocks;
 621         struct arcturus_single_dpm_table *single_dpm_table;
 622         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 623         struct arcturus_dpm_table *dpm_table = NULL;
 624
 625         dpm_table = smu_dpm->dpm_context;
 626
 627         switch (type) {
 628         case SMU_SCLK:
 629                 ret = smu_get_current_clk_freq(smu, SMU_GFXCLK, &now);
 630                 if (ret) {
 631                         pr_err("Attempt to get current gfx clk Failed!");
 632                         return ret;
 633                 }
 634
 635                 single_dpm_table = &(dpm_table->gfx_table);
 636                 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
 637                 if (ret) {
 638                         pr_err("Attempt to get gfx clk levels Failed!");
 639                         return ret;
 640                 }
 641
 642                 /*
 643                  * For DPM disabled case, there will be only one clock level.
 644                  * And it's safe to assume that is always the current clock.
 645                  */
 646                 for (i = 0; i < clocks.num_levels; i++)
 647                         size += sprintf(buf + size, "%d: %uMhz %s\n", i,
 648                                         clocks.data[i].clocks_in_khz / 1000,
 649                                         (clocks.num_levels == 1) ? "*" :
 650                                         (arcturus_freqs_in_same_level(
 651                                         clocks.data[i].clocks_in_khz / 1000,
 652                                         now / 100) ? "*" : ""));
 653                 break;
 654
 655         case SMU_MCLK:
 656                 ret = smu_get_current_clk_freq(smu, SMU_UCLK, &now);
 657                 if (ret) {
 658                         pr_err("Attempt to get current mclk Failed!");
 659                         return ret;
 660                 }
 661
 662                 single_dpm_table = &(dpm_table->mem_table);
 663                 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
 664                 if (ret) {
 665                         pr_err("Attempt to get memory clk levels Failed!");
 666                         return ret;
 667                 }
 668
 669                 for (i = 0; i < clocks.num_levels; i++)
 670                         size += sprintf(buf + size, "%d: %uMhz %s\n",
 671                                 i, clocks.data[i].clocks_in_khz / 1000,
 672                                 (clocks.num_levels == 1) ? "*" :
 673                                 (arcturus_freqs_in_same_level(
 674                                 clocks.data[i].clocks_in_khz / 1000,
 675                                 now / 100) ? "*" : ""));
 676                 break;
 677
 678         case SMU_SOCCLK:
 679                 ret = smu_get_current_clk_freq(smu, SMU_SOCCLK, &now);
 680                 if (ret) {
 681                         pr_err("Attempt to get current socclk Failed!");
 682                         return ret;
 683                 }
 684
 685                 single_dpm_table = &(dpm_table->soc_table);
 686                 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
 687                 if (ret) {
 688                         pr_err("Attempt to get socclk levels Failed!");
 689                         return ret;
 690                 }
 691
 692                 for (i = 0; i < clocks.num_levels; i++)
 693                         size += sprintf(buf + size, "%d: %uMhz %s\n",
 694                                 i, clocks.data[i].clocks_in_khz / 1000,
 695                                 (clocks.num_levels == 1) ? "*" :
 696                                 (arcturus_freqs_in_same_level(
 697                                 clocks.data[i].clocks_in_khz / 1000,
 698                                 now / 100) ? "*" : ""));
 699                 break;
 700
 701         case SMU_FCLK:
 702                 ret = smu_get_current_clk_freq(smu, SMU_FCLK, &now);
 703                 if (ret) {
 704                         pr_err("Attempt to get current fclk Failed!");
 705                         return ret;
 706                 }
 707
 708                 single_dpm_table = &(dpm_table->fclk_table);
 709                 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
 710                 if (ret) {
 711                         pr_err("Attempt to get fclk levels Failed!");
 712                         return ret;
 713                 }
 714
 715                 for (i = 0; i < single_dpm_table->count; i++)
 716                         size += sprintf(buf + size, "%d: %uMhz %s\n",
 717                                 i, single_dpm_table->dpm_levels[i].value,
 718                                 (clocks.num_levels == 1) ? "*" :
 719                                 (arcturus_freqs_in_same_level(
 720                                 clocks.data[i].clocks_in_khz / 1000,
 721                                 now / 100) ? "*" : ""));
 722                 break;
 723
 724         default:
 725                 break;
 726         }
 727
 728         return size;
 729 }
 730
 731 static int arcturus_upload_dpm_level(struct smu_context *smu, bool max,
 732                                      uint32_t feature_mask)
 733 {
 734         struct arcturus_single_dpm_table *single_dpm_table;
 735         struct arcturus_dpm_table *dpm_table =
 736                         smu->smu_dpm.dpm_context;
 737         uint32_t freq;
 738         int ret = 0;
 739
 740         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
 741             (feature_mask & FEATURE_DPM_GFXCLK_MASK)) {
 742                 single_dpm_table = &(dpm_table->gfx_table);
 743                 freq = max ? single_dpm_table->dpm_state.soft_max_level :
 744                         single_dpm_table->dpm_state.soft_min_level;
 745                 ret = smu_send_smc_msg_with_param(smu,
 746                         (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
 747                         (PPCLK_GFXCLK << 16) | (freq & 0xffff),
 748                         NULL);
 749                 if (ret) {
 750                         pr_err("Failed to set soft %s gfxclk !\n",
 751                                                 max ? "max" : "min");
 752                         return ret;
 753                 }
 754         }
 755
 756         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
 757             (feature_mask & FEATURE_DPM_UCLK_MASK)) {
 758                 single_dpm_table = &(dpm_table->mem_table);
 759                 freq = max ? single_dpm_table->dpm_state.soft_max_level :
 760                         single_dpm_table->dpm_state.soft_min_level;
 761                 ret = smu_send_smc_msg_with_param(smu,
 762                         (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
 763                         (PPCLK_UCLK << 16) | (freq & 0xffff),
 764                         NULL);
 765                 if (ret) {
 766                         pr_err("Failed to set soft %s memclk !\n",
 767                                                 max ? "max" : "min");
 768                         return ret;
 769                 }
 770         }
 771
 772         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT) &&
 773             (feature_mask & FEATURE_DPM_SOCCLK_MASK)) {
 774                 single_dpm_table = &(dpm_table->soc_table);
 775                 freq = max ? single_dpm_table->dpm_state.soft_max_level :
 776                         single_dpm_table->dpm_state.soft_min_level;
 777                 ret = smu_send_smc_msg_with_param(smu,
 778                         (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
 779                         (PPCLK_SOCCLK << 16) | (freq & 0xffff),
 780                         NULL);
 781                 if (ret) {
 782                         pr_err("Failed to set soft %s socclk !\n",
 783                                                 max ? "max" : "min");
 784                         return ret;
 785                 }
 786         }
 787
 788         return ret;
 789 }
 790
 791 static int arcturus_force_clk_levels(struct smu_context *smu,
 792                         enum smu_clk_type type, uint32_t mask)
 793 {
 794         struct arcturus_dpm_table *dpm_table;
 795         struct arcturus_single_dpm_table *single_dpm_table;
 796         uint32_t soft_min_level, soft_max_level;
 797         int ret = 0;
 798
 799         soft_min_level = mask ? (ffs(mask) - 1) : 0;
 800         soft_max_level = mask ? (fls(mask) - 1) : 0;
 801
 802         dpm_table = smu->smu_dpm.dpm_context;
 803
 804         switch (type) {
 805         case SMU_SCLK:
 806                 single_dpm_table = &(dpm_table->gfx_table);
 807
 808                 if (soft_max_level >= single_dpm_table->count) {
 809                         pr_err("Clock level specified %d is over max allowed %d\n",
 810                                         soft_max_level, single_dpm_table->count - 1);
 811                         ret = -EINVAL;
 812                         break;
 813                 }
 814
 815                 single_dpm_table->dpm_state.soft_min_level =
 816                         single_dpm_table->dpm_levels[soft_min_level].value;
 817                 single_dpm_table->dpm_state.soft_max_level =
 818                         single_dpm_table->dpm_levels[soft_max_level].value;
 819
 820                 ret = arcturus_upload_dpm_level(smu, false, FEATURE_DPM_GFXCLK_MASK);
 821                 if (ret) {
 822                         pr_err("Failed to upload boot level to lowest!\n");
 823                         break;
 824                 }
 825
 826                 ret = arcturus_upload_dpm_level(smu, true, FEATURE_DPM_GFXCLK_MASK);
 827                 if (ret)
 828                         pr_err("Failed to upload dpm max level to highest!\n");
 829
 830                 break;
 831
 832         case SMU_MCLK:
 833         case SMU_SOCCLK:
 834         case SMU_FCLK:
 835                 /*
 836                  * Should not arrive here since Arcturus does not
 837                  * support mclk/socclk/fclk softmin/softmax settings
 838                  */
 839                 ret = -EINVAL;
 840                 break;
 841
 842         default:
 843                 break;
 844         }
 845
 846         return ret;
 847 }
 848
 849 static int arcturus_get_thermal_temperature_range(struct smu_context *smu,
 850                                                 struct smu_temperature_range *range)
 851 {
 852         PPTable_t *pptable = smu->smu_table.driver_pptable;
 853
 854         if (!range)
 855                 return -EINVAL;
 856
 857         range->max = pptable->TedgeLimit *
 858                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 859         range->edge_emergency_max = (pptable->TedgeLimit + CTF_OFFSET_EDGE) *
 860                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 861         range->hotspot_crit_max = pptable->ThotspotLimit *
 862                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 863         range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) *
 864                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 865         range->mem_crit_max = pptable->TmemLimit *
 866                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 867         range->mem_emergency_max = (pptable->TmemLimit + CTF_OFFSET_HBM)*
 868                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 869
 870         return 0;
 871 }
 872
 873 static int arcturus_get_metrics_table(struct smu_context *smu,
 874                                       SmuMetrics_t *metrics_table)
 875 {
 876         struct smu_table_context *smu_table= &smu->smu_table;
 877         int ret = 0;
 878
 879         mutex_lock(&smu->metrics_lock);
 880         if (!smu_table->metrics_time ||
 881              time_after(jiffies, smu_table->metrics_time + HZ / 1000)) {
 882                 ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
 883                                 (void *)smu_table->metrics_table, false);
 884                 if (ret) {
 885                         pr_info("Failed to export SMU metrics table!\n");
 886                         mutex_unlock(&smu->metrics_lock);
 887                         return ret;
 888                 }
 889                 smu_table->metrics_time = jiffies;
 890         }
 891
 892         memcpy(metrics_table, smu_table->metrics_table, sizeof(SmuMetrics_t));
 893         mutex_unlock(&smu->metrics_lock);
 894
 895         return ret;
 896 }
 897
 898 static int arcturus_get_current_activity_percent(struct smu_context *smu,
 899                                                  enum amd_pp_sensors sensor,
 900                                                  uint32_t *value)
 901 {
 902         SmuMetrics_t metrics;
 903         int ret = 0;
 904
 905         if (!value)
 906                 return -EINVAL;
 907
 908         ret = arcturus_get_metrics_table(smu, &metrics);
 909         if (ret)
 910                 return ret;
 911
 912         switch (sensor) {
 913         case AMDGPU_PP_SENSOR_GPU_LOAD:
 914                 *value = metrics.AverageGfxActivity;
 915                 break;
 916         case AMDGPU_PP_SENSOR_MEM_LOAD:
 917                 *value = metrics.AverageUclkActivity;
 918                 break;
 919         default:
 920                 pr_err("Invalid sensor for retrieving clock activity\n");
 921                 return -EINVAL;
 922         }
 923
 924         return 0;
 925 }
 926
 927 static int arcturus_get_gpu_power(struct smu_context *smu, uint32_t *value)
 928 {
 929         SmuMetrics_t metrics;
 930         int ret = 0;
 931
 932         if (!value)
 933                 return -EINVAL;
 934
 935         ret = arcturus_get_metrics_table(smu, &metrics);
 936         if (ret)
 937                 return ret;
 938
 939         *value = metrics.AverageSocketPower << 8;
 940
 941         return 0;
 942 }
 943
 944 static int arcturus_thermal_get_temperature(struct smu_context *smu,
 945                                             enum amd_pp_sensors sensor,
 946                                             uint32_t *value)
 947 {
 948         SmuMetrics_t metrics;
 949         int ret = 0;
 950
 951         if (!value)
 952                 return -EINVAL;
 953
 954         ret = arcturus_get_metrics_table(smu, &metrics);
 955         if (ret)
 956                 return ret;
 957
 958         switch (sensor) {
 959         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
 960                 *value = metrics.TemperatureHotspot *
 961                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 962                 break;
 963         case AMDGPU_PP_SENSOR_EDGE_TEMP:
 964                 *value = metrics.TemperatureEdge *
 965                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 966                 break;
 967         case AMDGPU_PP_SENSOR_MEM_TEMP:
 968                 *value = metrics.TemperatureHBM *
 969                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 970                 break;
 971         default:
 972                 pr_err("Invalid sensor for retrieving temp\n");
 973                 return -EINVAL;
 974         }
 975
 976         return 0;
 977 }
 978
 979 static int arcturus_read_sensor(struct smu_context *smu,
 980                                 enum amd_pp_sensors sensor,
 981                                 void *data, uint32_t *size)
 982 {
 983         struct smu_table_context *table_context = &smu->smu_table;
 984         PPTable_t *pptable = table_context->driver_pptable;
 985         int ret = 0;
 986
 987         if (!data || !size)
 988                 return -EINVAL;
 989
 990         mutex_lock(&smu->sensor_lock);
 991         switch (sensor) {
 992         case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
 993                 *(uint32_t *)data = pptable->FanMaximumRpm;
 994                 *size = 4;
 995                 break;
 996         case AMDGPU_PP_SENSOR_MEM_LOAD:
 997         case AMDGPU_PP_SENSOR_GPU_LOAD:
 998                 ret = arcturus_get_current_activity_percent(smu,
 999                                                             sensor,
1000                                                 (uint32_t *)data);
1001                 *size = 4;
1002                 break;
1003         case AMDGPU_PP_SENSOR_GPU_POWER:
1004                 ret = arcturus_get_gpu_power(smu, (uint32_t *)data);
1005                 *size = 4;
1006                 break;
1007         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1008         case AMDGPU_PP_SENSOR_EDGE_TEMP:
1009         case AMDGPU_PP_SENSOR_MEM_TEMP:
1010                 ret = arcturus_thermal_get_temperature(smu, sensor,
1011                                                 (uint32_t *)data);
1012                 *size = 4;
1013                 break;
1014         default:
1015                 ret = smu_v11_0_read_sensor(smu, sensor, data, size);
1016         }
1017         mutex_unlock(&smu->sensor_lock);
1018
1019         return ret;
1020 }
1021
1022 static int arcturus_get_fan_speed_rpm(struct smu_context *smu,
1023                                       uint32_t *speed)
1024 {
1025         SmuMetrics_t metrics;
1026         int ret = 0;
1027
1028         if (!speed)
1029                 return -EINVAL;
1030
1031         ret = arcturus_get_metrics_table(smu, &metrics);
1032         if (ret)
1033                 return ret;
1034
1035         *speed = metrics.CurrFanSpeed;
1036
1037         return ret;
1038 }
1039
1040 static int arcturus_get_fan_speed_percent(struct smu_context *smu,
1041                                           uint32_t *speed)
1042 {
1043         PPTable_t *pptable = smu->smu_table.driver_pptable;
1044         uint32_t percent, current_rpm;
1045         int ret = 0;
1046
1047         if (!speed)
1048                 return -EINVAL;
1049
1050         ret = arcturus_get_fan_speed_rpm(smu, &current_rpm);
1051         if (ret)
1052                 return ret;
1053
1054         percent = current_rpm * 100 / pptable->FanMaximumRpm;
1055         *speed = percent > 100 ? 100 : percent;
1056
1057         return ret;
1058 }
1059
1060 static int arcturus_get_current_clk_freq_by_table(struct smu_context *smu,
1061                                        enum smu_clk_type clk_type,
1062                                        uint32_t *value)
1063 {
1064         static SmuMetrics_t metrics;
1065         int ret = 0, clk_id = 0;
1066
1067         if (!value)
1068                 return -EINVAL;
1069
1070         clk_id = smu_clk_get_index(smu, clk_type);
1071         if (clk_id < 0)
1072                 return -EINVAL;
1073
1074         ret = arcturus_get_metrics_table(smu, &metrics);
1075         if (ret)
1076                 return ret;
1077
1078         switch (clk_id) {
1079         case PPCLK_GFXCLK:
1080                 /*
1081                  * CurrClock[clk_id] can provide accurate
1082                  *   output only when the dpm feature is enabled.
1083                  * We can use Average_* for dpm disabled case.
1084                  *   But this is available for gfxclk/uclk/socclk.
1085                  */
1086                 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT))
1087                         *value = metrics.CurrClock[PPCLK_GFXCLK];
1088                 else
1089                         *value = metrics.AverageGfxclkFrequency;
1090                 break;
1091         case PPCLK_UCLK:
1092                 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT))
1093                         *value = metrics.CurrClock[PPCLK_UCLK];
1094                 else
1095                         *value = metrics.AverageUclkFrequency;
1096                 break;
1097         case PPCLK_SOCCLK:
1098                 if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT))
1099                         *value = metrics.CurrClock[PPCLK_SOCCLK];
1100                 else
1101                         *value = metrics.AverageSocclkFrequency;
1102                 break;
1103         default:
1104                 *value = metrics.CurrClock[clk_id];
1105                 break;
1106         }
1107
1108         return ret;
1109 }
1110
1111 static uint32_t arcturus_find_lowest_dpm_level(struct arcturus_single_dpm_table *table)
1112 {
1113         uint32_t i;
1114
1115         for (i = 0; i < table->count; i++) {
1116                 if (table->dpm_levels[i].enabled)
1117                         break;
1118         }
1119         if (i >= table->count) {
1120                 i = 0;
1121                 table->dpm_levels[i].enabled = true;
1122         }
1123
1124         return i;
1125 }
1126
1127 static uint32_t arcturus_find_highest_dpm_level(struct arcturus_single_dpm_table *table)
1128 {
1129         int i = 0;
1130
1131         if (table->count <= 0) {
1132                 pr_err("[%s] DPM Table has no entry!", __func__);
1133                 return 0;
1134         }
1135         if (table->count > MAX_DPM_NUMBER) {
1136                 pr_err("[%s] DPM Table has too many entries!", __func__);
1137                 return MAX_DPM_NUMBER - 1;
1138         }
1139
1140         for (i = table->count - 1; i >= 0; i--) {
1141                 if (table->dpm_levels[i].enabled)
1142                         break;
1143         }
1144         if (i < 0) {
1145                 i = 0;
1146                 table->dpm_levels[i].enabled = true;
1147         }
1148
1149         return i;
1150 }
1151
1152
1153
1154 static int arcturus_force_dpm_limit_value(struct smu_context *smu, bool highest)
1155 {
1156         struct arcturus_dpm_table *dpm_table =
1157                 (struct arcturus_dpm_table *)smu->smu_dpm.dpm_context;
1158         struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(smu->adev, 0);
1159         uint32_t soft_level;
1160         int ret = 0;
1161
1162         /* gfxclk */
1163         if (highest)
1164                 soft_level = arcturus_find_highest_dpm_level(&(dpm_table->gfx_table));
1165         else
1166                 soft_level = arcturus_find_lowest_dpm_level(&(dpm_table->gfx_table));
1167
1168         dpm_table->gfx_table.dpm_state.soft_min_level =
1169                 dpm_table->gfx_table.dpm_state.soft_max_level =
1170                 dpm_table->gfx_table.dpm_levels[soft_level].value;
1171
1172         ret = arcturus_upload_dpm_level(smu, false, FEATURE_DPM_GFXCLK_MASK);
1173         if (ret) {
1174                 pr_err("Failed to upload boot level to %s!\n",
1175                                 highest ? "highest" : "lowest");
1176                 return ret;
1177         }
1178
1179         ret = arcturus_upload_dpm_level(smu, true, FEATURE_DPM_GFXCLK_MASK);
1180         if (ret) {
1181                 pr_err("Failed to upload dpm max level to %s!\n!",
1182                                 highest ? "highest" : "lowest");
1183                 return ret;
1184         }
1185
1186         if (hive)
1187                 /*
1188                  * Force XGMI Pstate to highest or lowest
1189                  * TODO: revise this when xgmi dpm is functional
1190                  */
1191                 ret = smu_v11_0_set_xgmi_pstate(smu, highest ? 1 : 0);
1192
1193         return ret;
1194 }
1195
1196 static int arcturus_unforce_dpm_levels(struct smu_context *smu)
1197 {
1198         struct arcturus_dpm_table *dpm_table =
1199                 (struct arcturus_dpm_table *)smu->smu_dpm.dpm_context;
1200         struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(smu->adev, 0);
1201         uint32_t soft_min_level, soft_max_level;
1202         int ret = 0;
1203
1204         /* gfxclk */
1205         soft_min_level = arcturus_find_lowest_dpm_level(&(dpm_table->gfx_table));
1206         soft_max_level = arcturus_find_highest_dpm_level(&(dpm_table->gfx_table));
1207         dpm_table->gfx_table.dpm_state.soft_min_level =
1208                 dpm_table->gfx_table.dpm_levels[soft_min_level].value;
1209         dpm_table->gfx_table.dpm_state.soft_max_level =
1210                 dpm_table->gfx_table.dpm_levels[soft_max_level].value;
1211
1212         ret = arcturus_upload_dpm_level(smu, false, FEATURE_DPM_GFXCLK_MASK);
1213         if (ret) {
1214                 pr_err("Failed to upload DPM Bootup Levels!");
1215                 return ret;
1216         }
1217
1218         ret = arcturus_upload_dpm_level(smu, true, FEATURE_DPM_GFXCLK_MASK);
1219         if (ret) {
1220                 pr_err("Failed to upload DPM Max Levels!");
1221                 return ret;
1222         }
1223
1224         if (hive)
1225                 /*
1226                  * Reset XGMI Pstate back to default
1227                  * TODO: revise this when xgmi dpm is functional
1228                  */
1229                 ret = smu_v11_0_set_xgmi_pstate(smu, 0);
1230
1231         return ret;
1232 }
1233
1234 static int
1235 arcturus_get_profiling_clk_mask(struct smu_context *smu,
1236                                 enum amd_dpm_forced_level level,
1237                                 uint32_t *sclk_mask,
1238                                 uint32_t *mclk_mask,
1239                                 uint32_t *soc_mask)
1240 {
1241         struct arcturus_dpm_table *dpm_table =
1242                 (struct arcturus_dpm_table *)smu->smu_dpm.dpm_context;
1243         struct arcturus_single_dpm_table *gfx_dpm_table;
1244         struct arcturus_single_dpm_table *mem_dpm_table;
1245         struct arcturus_single_dpm_table *soc_dpm_table;
1246
1247         if (!smu->smu_dpm.dpm_context)
1248                 return -EINVAL;
1249
1250         gfx_dpm_table = &dpm_table->gfx_table;
1251         mem_dpm_table = &dpm_table->mem_table;
1252         soc_dpm_table = &dpm_table->soc_table;
1253
1254         *sclk_mask = 0;
1255         *mclk_mask = 0;
1256         *soc_mask  = 0;
1257
1258         if (gfx_dpm_table->count > ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL &&
1259             mem_dpm_table->count > ARCTURUS_UMD_PSTATE_MCLK_LEVEL &&
1260             soc_dpm_table->count > ARCTURUS_UMD_PSTATE_SOCCLK_LEVEL) {
1261                 *sclk_mask = ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL;
1262                 *mclk_mask = ARCTURUS_UMD_PSTATE_MCLK_LEVEL;
1263                 *soc_mask  = ARCTURUS_UMD_PSTATE_SOCCLK_LEVEL;
1264         }
1265
1266         if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
1267                 *sclk_mask = 0;
1268         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
1269                 *mclk_mask = 0;
1270         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
1271                 *sclk_mask = gfx_dpm_table->count - 1;
1272                 *mclk_mask = mem_dpm_table->count - 1;
1273                 *soc_mask  = soc_dpm_table->count - 1;
1274         }
1275
1276         return 0;
1277 }
1278
1279 static int arcturus_get_power_limit(struct smu_context *smu,
1280                                      uint32_t *limit,
1281                                      bool cap)
1282 {
1283         PPTable_t *pptable = smu->smu_table.driver_pptable;
1284         uint32_t asic_default_power_limit = 0;
1285         int ret = 0;
1286         int power_src;
1287
1288         if (!smu->power_limit) {
1289                 if (smu_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
1290                         power_src = smu_power_get_index(smu, SMU_POWER_SOURCE_AC);
1291                         if (power_src < 0)
1292                                 return -EINVAL;
1293
1294                         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetPptLimit,
1295                                 power_src << 16, &asic_default_power_limit);
1296                         if (ret) {
1297                                 pr_err("[%s] get PPT limit failed!", __func__);
1298                                 return ret;
1299                         }
1300                 } else {
1301                         /* the last hope to figure out the ppt limit */
1302                         if (!pptable) {
1303                                 pr_err("Cannot get PPT limit due to pptable missing!");
1304                                 return -EINVAL;
1305                         }
1306                         asic_default_power_limit =
1307                                 pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
1308                 }
1309
1310                 smu->power_limit = asic_default_power_limit;
1311         }
1312
1313         if (cap)
1314                 *limit = smu_v11_0_get_max_power_limit(smu);
1315         else
1316                 *limit = smu->power_limit;
1317
1318         return 0;
1319 }
1320
1321 static int arcturus_get_power_profile_mode(struct smu_context *smu,
1322                                            char *buf)
1323 {
1324         struct amdgpu_device *adev = smu->adev;
1325         DpmActivityMonitorCoeffInt_t activity_monitor;
1326         static const char *profile_name[] = {
1327                                         "BOOTUP_DEFAULT",
1328                                         "3D_FULL_SCREEN",
1329                                         "POWER_SAVING",
1330                                         "VIDEO",
1331                                         "VR",
1332                                         "COMPUTE",
1333                                         "CUSTOM"};
1334         static const char *title[] = {
1335                         "PROFILE_INDEX(NAME)",
1336                         "CLOCK_TYPE(NAME)",
1337                         "FPS",
1338                         "UseRlcBusy",
1339                         "MinActiveFreqType",
1340                         "MinActiveFreq",
1341                         "BoosterFreqType",
1342                         "BoosterFreq",
1343                         "PD_Data_limit_c",
1344                         "PD_Data_error_coeff",
1345                         "PD_Data_error_rate_coeff"};
1346         uint32_t i, size = 0;
1347         int16_t workload_type = 0;
1348         int result = 0;
1349         uint32_t smu_version;
1350
1351         if (!buf)
1352                 return -EINVAL;
1353
1354         result = smu_get_smc_version(smu, NULL, &smu_version);
1355         if (result)
1356                 return result;
1357
1358         if (smu_version >= 0x360d00 && !amdgpu_sriov_vf(adev))
1359                 size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
1360                         title[0], title[1], title[2], title[3], title[4], title[5],
1361                         title[6], title[7], title[8], title[9], title[10]);
1362         else
1363                 size += sprintf(buf + size, "%16s\n",
1364                         title[0]);
1365
1366         for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1367                 /*
1368                  * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT
1369                  * Not all profile modes are supported on arcturus.
1370                  */
1371                 workload_type = smu_workload_get_type(smu, i);
1372                 if (workload_type < 0)
1373                         continue;
1374
1375                 if (smu_version >= 0x360d00 && !amdgpu_sriov_vf(adev)) {
1376                         result = smu_update_table(smu,
1377                                                   SMU_TABLE_ACTIVITY_MONITOR_COEFF,
1378                                                   workload_type,
1379                                                   (void *)(&activity_monitor),
1380                                                   false);
1381                         if (result) {
1382                                 pr_err("[%s] Failed to get activity monitor!", __func__);
1383                                 return result;
1384                         }
1385                 }
1386
1387                 size += sprintf(buf + size, "%2d %14s%s\n",
1388                         i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1389
1390                 if (smu_version >= 0x360d00 && !amdgpu_sriov_vf(adev)) {
1391                         size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1392                                 " ",
1393                                 0,
1394                                 "GFXCLK",
1395                                 activity_monitor.Gfx_FPS,
1396                                 activity_monitor.Gfx_UseRlcBusy,
1397                                 activity_monitor.Gfx_MinActiveFreqType,
1398                                 activity_monitor.Gfx_MinActiveFreq,
1399                                 activity_monitor.Gfx_BoosterFreqType,
1400                                 activity_monitor.Gfx_BoosterFreq,
1401                                 activity_monitor.Gfx_PD_Data_limit_c,
1402                                 activity_monitor.Gfx_PD_Data_error_coeff,
1403                                 activity_monitor.Gfx_PD_Data_error_rate_coeff);
1404
1405                         size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1406                                 " ",
1407                                 1,
1408                                 "UCLK",
1409                                 activity_monitor.Mem_FPS,
1410                                 activity_monitor.Mem_UseRlcBusy,
1411                                 activity_monitor.Mem_MinActiveFreqType,
1412                                 activity_monitor.Mem_MinActiveFreq,
1413                                 activity_monitor.Mem_BoosterFreqType,
1414                                 activity_monitor.Mem_BoosterFreq,
1415                                 activity_monitor.Mem_PD_Data_limit_c,
1416                                 activity_monitor.Mem_PD_Data_error_coeff,
1417                                 activity_monitor.Mem_PD_Data_error_rate_coeff);
1418                 }
1419         }
1420
1421         return size;
1422 }
1423
1424 static int arcturus_set_power_profile_mode(struct smu_context *smu,
1425                                            long *input,
1426                                            uint32_t size)
1427 {
1428         DpmActivityMonitorCoeffInt_t activity_monitor;
1429         int workload_type = 0;
1430         uint32_t profile_mode = input[size];
1431         int ret = 0;
1432         uint32_t smu_version;
1433
1434         if (profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1435                 pr_err("Invalid power profile mode %d\n", profile_mode);
1436                 return -EINVAL;
1437         }
1438
1439         ret = smu_get_smc_version(smu, NULL, &smu_version);
1440         if (ret)
1441                 return ret;
1442
1443         if ((profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) &&
1444              (smu_version >=0x360d00)) {
1445                 ret = smu_update_table(smu,
1446                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF,
1447                                        WORKLOAD_PPLIB_CUSTOM_BIT,
1448                                        (void *)(&activity_monitor),
1449                                        false);
1450                 if (ret) {
1451                         pr_err("[%s] Failed to get activity monitor!", __func__);
1452                         return ret;
1453                 }
1454
1455                 switch (input[0]) {
1456                 case 0: /* Gfxclk */
1457                         activity_monitor.Gfx_FPS = input[1];
1458                         activity_monitor.Gfx_UseRlcBusy = input[2];
1459                         activity_monitor.Gfx_MinActiveFreqType = input[3];
1460                         activity_monitor.Gfx_MinActiveFreq = input[4];
1461                         activity_monitor.Gfx_BoosterFreqType = input[5];
1462                         activity_monitor.Gfx_BoosterFreq = input[6];
1463                         activity_monitor.Gfx_PD_Data_limit_c = input[7];
1464                         activity_monitor.Gfx_PD_Data_error_coeff = input[8];
1465                         activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9];
1466                         break;
1467                 case 1: /* Uclk */
1468                         activity_monitor.Mem_FPS = input[1];
1469                         activity_monitor.Mem_UseRlcBusy = input[2];
1470                         activity_monitor.Mem_MinActiveFreqType = input[3];
1471                         activity_monitor.Mem_MinActiveFreq = input[4];
1472                         activity_monitor.Mem_BoosterFreqType = input[5];
1473                         activity_monitor.Mem_BoosterFreq = input[6];
1474                         activity_monitor.Mem_PD_Data_limit_c = input[7];
1475                         activity_monitor.Mem_PD_Data_error_coeff = input[8];
1476                         activity_monitor.Mem_PD_Data_error_rate_coeff = input[9];
1477                         break;
1478                 }
1479
1480                 ret = smu_update_table(smu,
1481                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF,
1482                                        WORKLOAD_PPLIB_CUSTOM_BIT,
1483                                        (void *)(&activity_monitor),
1484                                        true);
1485                 if (ret) {
1486                         pr_err("[%s] Failed to set activity monitor!", __func__);
1487                         return ret;
1488                 }
1489         }
1490
1491         /*
1492          * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT
1493          * Not all profile modes are supported on arcturus.
1494          */
1495         workload_type = smu_workload_get_type(smu, profile_mode);
1496         if (workload_type < 0) {
1497                 pr_err("Unsupported power profile mode %d on arcturus\n", profile_mode);
1498                 return -EINVAL;
1499         }
1500
1501         ret = smu_send_smc_msg_with_param(smu,
1502                                           SMU_MSG_SetWorkloadMask,
1503                                           1 << workload_type,
1504                                           NULL);
1505         if (ret) {
1506                 pr_err("Fail to set workload type %d\n", workload_type);
1507                 return ret;
1508         }
1509
1510         smu->power_profile_mode = profile_mode;
1511
1512         return 0;
1513 }
1514
1515 static void arcturus_dump_pptable(struct smu_context *smu)
1516 {
1517         struct smu_table_context *table_context = &smu->smu_table;
1518         PPTable_t *pptable = table_context->driver_pptable;
1519         int i;
1520
1521         pr_info("Dumped PPTable:\n");
1522
1523         pr_info("Version = 0x%08x\n", pptable->Version);
1524
1525         pr_info("FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
1526         pr_info("FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
1527
1528         for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
1529                 pr_info("SocketPowerLimitAc[%d] = %d\n", i, pptable->SocketPowerLimitAc[i]);
1530                 pr_info("SocketPowerLimitAcTau[%d] = %d\n", i, pptable->SocketPowerLimitAcTau[i]);
1531         }
1532
1533         pr_info("TdcLimitSoc = %d\n", pptable->TdcLimitSoc);
1534         pr_info("TdcLimitSocTau = %d\n", pptable->TdcLimitSocTau);
1535         pr_info("TdcLimitGfx = %d\n", pptable->TdcLimitGfx);
1536         pr_info("TdcLimitGfxTau = %d\n", pptable->TdcLimitGfxTau);
1537
1538         pr_info("TedgeLimit = %d\n", pptable->TedgeLimit);
1539         pr_info("ThotspotLimit = %d\n", pptable->ThotspotLimit);
1540         pr_info("TmemLimit = %d\n", pptable->TmemLimit);
1541         pr_info("Tvr_gfxLimit = %d\n", pptable->Tvr_gfxLimit);
1542         pr_info("Tvr_memLimit = %d\n", pptable->Tvr_memLimit);
1543         pr_info("Tvr_socLimit = %d\n", pptable->Tvr_socLimit);
1544         pr_info("FitLimit = %d\n", pptable->FitLimit);
1545
1546         pr_info("PpmPowerLimit = %d\n", pptable->PpmPowerLimit);
1547         pr_info("PpmTemperatureThreshold = %d\n", pptable->PpmTemperatureThreshold);
1548
1549         pr_info("ThrottlerControlMask = %d\n", pptable->ThrottlerControlMask);
1550
1551         pr_info("UlvVoltageOffsetGfx = %d\n", pptable->UlvVoltageOffsetGfx);
1552         pr_info("UlvPadding = 0x%08x\n", pptable->UlvPadding);
1553
1554         pr_info("UlvGfxclkBypass = %d\n", pptable->UlvGfxclkBypass);
1555         pr_info("Padding234[0] = 0x%02x\n", pptable->Padding234[0]);
1556         pr_info("Padding234[1] = 0x%02x\n", pptable->Padding234[1]);
1557         pr_info("Padding234[2] = 0x%02x\n", pptable->Padding234[2]);
1558
1559         pr_info("MinVoltageGfx = %d\n", pptable->MinVoltageGfx);
1560         pr_info("MinVoltageSoc = %d\n", pptable->MinVoltageSoc);
1561         pr_info("MaxVoltageGfx = %d\n", pptable->MaxVoltageGfx);
1562         pr_info("MaxVoltageSoc = %d\n", pptable->MaxVoltageSoc);
1563
1564         pr_info("LoadLineResistanceGfx = %d\n", pptable->LoadLineResistanceGfx);
1565         pr_info("LoadLineResistanceSoc = %d\n", pptable->LoadLineResistanceSoc);
1566
1567         pr_info("[PPCLK_GFXCLK]\n"
1568                         "  .VoltageMode          = 0x%02x\n"
1569                         "  .SnapToDiscrete       = 0x%02x\n"
1570                         "  .NumDiscreteLevels    = 0x%02x\n"
1571                         "  .padding              = 0x%02x\n"
1572                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1573                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1574                         "  .SsFmin               = 0x%04x\n"
1575                         "  .Padding_16           = 0x%04x\n",
1576                         pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
1577                         pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
1578                         pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
1579                         pptable->DpmDescriptor[PPCLK_GFXCLK].padding,
1580                         pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
1581                         pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
1582                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
1583                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
1584                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
1585                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
1586                         pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
1587
1588         pr_info("[PPCLK_VCLK]\n"
1589                         "  .VoltageMode          = 0x%02x\n"
1590                         "  .SnapToDiscrete       = 0x%02x\n"
1591                         "  .NumDiscreteLevels    = 0x%02x\n"
1592                         "  .padding              = 0x%02x\n"
1593                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1594                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1595                         "  .SsFmin               = 0x%04x\n"
1596                         "  .Padding_16           = 0x%04x\n",
1597                         pptable->DpmDescriptor[PPCLK_VCLK].VoltageMode,
1598                         pptable->DpmDescriptor[PPCLK_VCLK].SnapToDiscrete,
1599                         pptable->DpmDescriptor[PPCLK_VCLK].NumDiscreteLevels,
1600                         pptable->DpmDescriptor[PPCLK_VCLK].padding,
1601                         pptable->DpmDescriptor[PPCLK_VCLK].ConversionToAvfsClk.m,
1602                         pptable->DpmDescriptor[PPCLK_VCLK].ConversionToAvfsClk.b,
1603                         pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.a,
1604                         pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.b,
1605                         pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.c,
1606                         pptable->DpmDescriptor[PPCLK_VCLK].SsFmin,
1607                         pptable->DpmDescriptor[PPCLK_VCLK].Padding16);
1608
1609         pr_info("[PPCLK_DCLK]\n"
1610                         "  .VoltageMode          = 0x%02x\n"
1611                         "  .SnapToDiscrete       = 0x%02x\n"
1612                         "  .NumDiscreteLevels    = 0x%02x\n"
1613                         "  .padding              = 0x%02x\n"
1614                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1615                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1616                         "  .SsFmin               = 0x%04x\n"
1617                         "  .Padding_16           = 0x%04x\n",
1618                         pptable->DpmDescriptor[PPCLK_DCLK].VoltageMode,
1619                         pptable->DpmDescriptor[PPCLK_DCLK].SnapToDiscrete,
1620                         pptable->DpmDescriptor[PPCLK_DCLK].NumDiscreteLevels,
1621                         pptable->DpmDescriptor[PPCLK_DCLK].padding,
1622                         pptable->DpmDescriptor[PPCLK_DCLK].ConversionToAvfsClk.m,
1623                         pptable->DpmDescriptor[PPCLK_DCLK].ConversionToAvfsClk.b,
1624                         pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.a,
1625                         pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.b,
1626                         pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.c,
1627                         pptable->DpmDescriptor[PPCLK_DCLK].SsFmin,
1628                         pptable->DpmDescriptor[PPCLK_DCLK].Padding16);
1629
1630         pr_info("[PPCLK_SOCCLK]\n"
1631                         "  .VoltageMode          = 0x%02x\n"
1632                         "  .SnapToDiscrete       = 0x%02x\n"
1633                         "  .NumDiscreteLevels    = 0x%02x\n"
1634                         "  .padding              = 0x%02x\n"
1635                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1636                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1637                         "  .SsFmin               = 0x%04x\n"
1638                         "  .Padding_16           = 0x%04x\n",
1639                         pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
1640                         pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
1641                         pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
1642                         pptable->DpmDescriptor[PPCLK_SOCCLK].padding,
1643                         pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
1644                         pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
1645                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
1646                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
1647                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
1648                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
1649                         pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
1650
1651         pr_info("[PPCLK_UCLK]\n"
1652                         "  .VoltageMode          = 0x%02x\n"
1653                         "  .SnapToDiscrete       = 0x%02x\n"
1654                         "  .NumDiscreteLevels    = 0x%02x\n"
1655                         "  .padding              = 0x%02x\n"
1656                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1657                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1658                         "  .SsFmin               = 0x%04x\n"
1659                         "  .Padding_16           = 0x%04x\n",
1660                         pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
1661                         pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
1662                         pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
1663                         pptable->DpmDescriptor[PPCLK_UCLK].padding,
1664                         pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
1665                         pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
1666                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
1667                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
1668                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
1669                         pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
1670                         pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
1671
1672         pr_info("[PPCLK_FCLK]\n"
1673                         "  .VoltageMode          = 0x%02x\n"
1674                         "  .SnapToDiscrete       = 0x%02x\n"
1675                         "  .NumDiscreteLevels    = 0x%02x\n"
1676                         "  .padding              = 0x%02x\n"
1677                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1678                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1679                         "  .SsFmin               = 0x%04x\n"
1680                         "  .Padding_16           = 0x%04x\n",
1681                         pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
1682                         pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
1683                         pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
1684                         pptable->DpmDescriptor[PPCLK_FCLK].padding,
1685                         pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
1686                         pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
1687                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
1688                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
1689                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
1690                         pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
1691                         pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
1692
1693
1694         pr_info("FreqTableGfx\n");
1695         for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
1696                 pr_info("  .[%02d] = %d\n", i, pptable->FreqTableGfx[i]);
1697
1698         pr_info("FreqTableVclk\n");
1699         for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
1700                 pr_info("  .[%02d] = %d\n", i, pptable->FreqTableVclk[i]);
1701
1702         pr_info("FreqTableDclk\n");
1703         for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
1704                 pr_info("  .[%02d] = %d\n", i, pptable->FreqTableDclk[i]);
1705
1706         pr_info("FreqTableSocclk\n");
1707         for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
1708                 pr_info("  .[%02d] = %d\n", i, pptable->FreqTableSocclk[i]);
1709
1710         pr_info("FreqTableUclk\n");
1711         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
1712                 pr_info("  .[%02d] = %d\n", i, pptable->FreqTableUclk[i]);
1713
1714         pr_info("FreqTableFclk\n");
1715         for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
1716                 pr_info("  .[%02d] = %d\n", i, pptable->FreqTableFclk[i]);
1717
1718         pr_info("Mp0clkFreq\n");
1719         for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
1720                 pr_info("  .[%d] = %d\n", i, pptable->Mp0clkFreq[i]);
1721
1722         pr_info("Mp0DpmVoltage\n");
1723         for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
1724                 pr_info("  .[%d] = %d\n", i, pptable->Mp0DpmVoltage[i]);
1725
1726         pr_info("GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
1727         pr_info("GfxclkSlewRate = 0x%x\n", pptable->GfxclkSlewRate);
1728         pr_info("Padding567[0] = 0x%x\n", pptable->Padding567[0]);
1729         pr_info("Padding567[1] = 0x%x\n", pptable->Padding567[1]);
1730         pr_info("Padding567[2] = 0x%x\n", pptable->Padding567[2]);
1731         pr_info("Padding567[3] = 0x%x\n", pptable->Padding567[3]);
1732         pr_info("GfxclkDsMaxFreq = %d\n", pptable->GfxclkDsMaxFreq);
1733         pr_info("GfxclkSource = 0x%x\n", pptable->GfxclkSource);
1734         pr_info("Padding456 = 0x%x\n", pptable->Padding456);
1735
1736         pr_info("EnableTdpm = %d\n", pptable->EnableTdpm);
1737         pr_info("TdpmHighHystTemperature = %d\n", pptable->TdpmHighHystTemperature);
1738         pr_info("TdpmLowHystTemperature = %d\n", pptable->TdpmLowHystTemperature);
1739         pr_info("GfxclkFreqHighTempLimit = %d\n", pptable->GfxclkFreqHighTempLimit);
1740
1741         pr_info("FanStopTemp = %d\n", pptable->FanStopTemp);
1742         pr_info("FanStartTemp = %d\n", pptable->FanStartTemp);
1743
1744         pr_info("FanGainEdge = %d\n", pptable->FanGainEdge);
1745         pr_info("FanGainHotspot = %d\n", pptable->FanGainHotspot);
1746         pr_info("FanGainVrGfx = %d\n", pptable->FanGainVrGfx);
1747         pr_info("FanGainVrSoc = %d\n", pptable->FanGainVrSoc);
1748         pr_info("FanGainVrMem = %d\n", pptable->FanGainVrMem);
1749         pr_info("FanGainHbm = %d\n", pptable->FanGainHbm);
1750
1751         pr_info("FanPwmMin = %d\n", pptable->FanPwmMin);
1752         pr_info("FanAcousticLimitRpm = %d\n", pptable->FanAcousticLimitRpm);
1753         pr_info("FanThrottlingRpm = %d\n", pptable->FanThrottlingRpm);
1754         pr_info("FanMaximumRpm = %d\n", pptable->FanMaximumRpm);
1755         pr_info("FanTargetTemperature = %d\n", pptable->FanTargetTemperature);
1756         pr_info("FanTargetGfxclk = %d\n", pptable->FanTargetGfxclk);
1757         pr_info("FanZeroRpmEnable = %d\n", pptable->FanZeroRpmEnable);
1758         pr_info("FanTachEdgePerRev = %d\n", pptable->FanTachEdgePerRev);
1759         pr_info("FanTempInputSelect = %d\n", pptable->FanTempInputSelect);
1760
1761         pr_info("FuzzyFan_ErrorSetDelta = %d\n", pptable->FuzzyFan_ErrorSetDelta);
1762         pr_info("FuzzyFan_ErrorRateSetDelta = %d\n", pptable->FuzzyFan_ErrorRateSetDelta);
1763         pr_info("FuzzyFan_PwmSetDelta = %d\n", pptable->FuzzyFan_PwmSetDelta);
1764         pr_info("FuzzyFan_Reserved = %d\n", pptable->FuzzyFan_Reserved);
1765
1766         pr_info("OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
1767         pr_info("OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
1768         pr_info("Padding8_Avfs[0] = %d\n", pptable->Padding8_Avfs[0]);
1769         pr_info("Padding8_Avfs[1] = %d\n", pptable->Padding8_Avfs[1]);
1770
1771         pr_info("dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
1772                         pptable->dBtcGbGfxPll.a,
1773                         pptable->dBtcGbGfxPll.b,
1774                         pptable->dBtcGbGfxPll.c);
1775         pr_info("dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
1776                         pptable->dBtcGbGfxAfll.a,
1777                         pptable->dBtcGbGfxAfll.b,
1778                         pptable->dBtcGbGfxAfll.c);
1779         pr_info("dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
1780                         pptable->dBtcGbSoc.a,
1781                         pptable->dBtcGbSoc.b,
1782                         pptable->dBtcGbSoc.c);
1783
1784         pr_info("qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
1785                         pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
1786                         pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
1787         pr_info("qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
1788                         pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
1789                         pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
1790
1791         pr_info("qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
1792                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
1793                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
1794                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
1795         pr_info("qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
1796                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
1797                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
1798                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
1799
1800         pr_info("DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
1801         pr_info("DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
1802
1803         pr_info("DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
1804         pr_info("DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
1805         pr_info("Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
1806         pr_info("Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
1807
1808         pr_info("DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
1809         pr_info("DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
1810         pr_info("DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
1811         pr_info("DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
1812
1813         pr_info("DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
1814         pr_info("DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
1815
1816         pr_info("XgmiDpmPstates\n");
1817         for (i = 0; i < NUM_XGMI_LEVELS; i++)
1818                 pr_info("  .[%d] = %d\n", i, pptable->XgmiDpmPstates[i]);
1819         pr_info("XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
1820         pr_info("XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
1821
1822         pr_info("VDDGFX_TVmin = %d\n", pptable->VDDGFX_TVmin);
1823         pr_info("VDDSOC_TVmin = %d\n", pptable->VDDSOC_TVmin);
1824         pr_info("VDDGFX_Vmin_HiTemp = %d\n", pptable->VDDGFX_Vmin_HiTemp);
1825         pr_info("VDDGFX_Vmin_LoTemp = %d\n", pptable->VDDGFX_Vmin_LoTemp);
1826         pr_info("VDDSOC_Vmin_HiTemp = %d\n", pptable->VDDSOC_Vmin_HiTemp);
1827         pr_info("VDDSOC_Vmin_LoTemp = %d\n", pptable->VDDSOC_Vmin_LoTemp);
1828         pr_info("VDDGFX_TVminHystersis = %d\n", pptable->VDDGFX_TVminHystersis);
1829         pr_info("VDDSOC_TVminHystersis = %d\n", pptable->VDDSOC_TVminHystersis);
1830
1831         pr_info("DebugOverrides = 0x%x\n", pptable->DebugOverrides);
1832         pr_info("ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
1833                         pptable->ReservedEquation0.a,
1834                         pptable->ReservedEquation0.b,
1835                         pptable->ReservedEquation0.c);
1836         pr_info("ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
1837                         pptable->ReservedEquation1.a,
1838                         pptable->ReservedEquation1.b,
1839                         pptable->ReservedEquation1.c);
1840         pr_info("ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
1841                         pptable->ReservedEquation2.a,
1842                         pptable->ReservedEquation2.b,
1843                         pptable->ReservedEquation2.c);
1844         pr_info("ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
1845                         pptable->ReservedEquation3.a,
1846                         pptable->ReservedEquation3.b,
1847                         pptable->ReservedEquation3.c);
1848
1849         pr_info("MinVoltageUlvGfx = %d\n", pptable->MinVoltageUlvGfx);
1850         pr_info("PaddingUlv = %d\n", pptable->PaddingUlv);
1851
1852         pr_info("TotalPowerConfig = %d\n", pptable->TotalPowerConfig);
1853         pr_info("TotalPowerSpare1 = %d\n", pptable->TotalPowerSpare1);
1854         pr_info("TotalPowerSpare2 = %d\n", pptable->TotalPowerSpare2);
1855
1856         pr_info("PccThresholdLow = %d\n", pptable->PccThresholdLow);
1857         pr_info("PccThresholdHigh = %d\n", pptable->PccThresholdHigh);
1858
1859         pr_info("Board Parameters:\n");
1860         pr_info("MaxVoltageStepGfx = 0x%x\n", pptable->MaxVoltageStepGfx);
1861         pr_info("MaxVoltageStepSoc = 0x%x\n", pptable->MaxVoltageStepSoc);
1862
1863         pr_info("VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
1864         pr_info("VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
1865         pr_info("VddMemVrMapping = 0x%x\n", pptable->VddMemVrMapping);
1866         pr_info("BoardVrMapping = 0x%x\n", pptable->BoardVrMapping);
1867
1868         pr_info("GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
1869         pr_info("ExternalSensorPresent = 0x%x\n", pptable->ExternalSensorPresent);
1870
1871         pr_info("GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
1872         pr_info("GfxOffset = 0x%x\n", pptable->GfxOffset);
1873         pr_info("Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
1874
1875         pr_info("SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
1876         pr_info("SocOffset = 0x%x\n", pptable->SocOffset);
1877         pr_info("Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
1878
1879         pr_info("MemMaxCurrent = 0x%x\n", pptable->MemMaxCurrent);
1880         pr_info("MemOffset = 0x%x\n", pptable->MemOffset);
1881         pr_info("Padding_TelemetryMem = 0x%x\n", pptable->Padding_TelemetryMem);
1882
1883         pr_info("BoardMaxCurrent = 0x%x\n", pptable->BoardMaxCurrent);
1884         pr_info("BoardOffset = 0x%x\n", pptable->BoardOffset);
1885         pr_info("Padding_TelemetryBoardInput = 0x%x\n", pptable->Padding_TelemetryBoardInput);
1886
1887         pr_info("VR0HotGpio = %d\n", pptable->VR0HotGpio);
1888         pr_info("VR0HotPolarity = %d\n", pptable->VR0HotPolarity);
1889         pr_info("VR1HotGpio = %d\n", pptable->VR1HotGpio);
1890         pr_info("VR1HotPolarity = %d\n", pptable->VR1HotPolarity);
1891
1892         pr_info("PllGfxclkSpreadEnabled = %d\n", pptable->PllGfxclkSpreadEnabled);
1893         pr_info("PllGfxclkSpreadPercent = %d\n", pptable->PllGfxclkSpreadPercent);
1894         pr_info("PllGfxclkSpreadFreq = %d\n", pptable->PllGfxclkSpreadFreq);
1895
1896         pr_info("UclkSpreadEnabled = %d\n", pptable->UclkSpreadEnabled);
1897         pr_info("UclkSpreadPercent = %d\n", pptable->UclkSpreadPercent);
1898         pr_info("UclkSpreadFreq = %d\n", pptable->UclkSpreadFreq);
1899
1900         pr_info("FclkSpreadEnabled = %d\n", pptable->FclkSpreadEnabled);
1901         pr_info("FclkSpreadPercent = %d\n", pptable->FclkSpreadPercent);
1902         pr_info("FclkSpreadFreq = %d\n", pptable->FclkSpreadFreq);
1903
1904         pr_info("FllGfxclkSpreadEnabled = %d\n", pptable->FllGfxclkSpreadEnabled);
1905         pr_info("FllGfxclkSpreadPercent = %d\n", pptable->FllGfxclkSpreadPercent);
1906         pr_info("FllGfxclkSpreadFreq = %d\n", pptable->FllGfxclkSpreadFreq);
1907
1908         for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
1909                 pr_info("I2cControllers[%d]:\n", i);
1910                 pr_info("                   .Enabled = %d\n",
1911                                 pptable->I2cControllers[i].Enabled);
1912                 pr_info("                   .SlaveAddress = 0x%x\n",
1913                                 pptable->I2cControllers[i].SlaveAddress);
1914                 pr_info("                   .ControllerPort = %d\n",
1915                                 pptable->I2cControllers[i].ControllerPort);
1916                 pr_info("                   .ControllerName = %d\n",
1917                                 pptable->I2cControllers[i].ControllerName);
1918                 pr_info("                   .ThermalThrottler = %d\n",
1919                                 pptable->I2cControllers[i].ThermalThrotter);
1920                 pr_info("                   .I2cProtocol = %d\n",
1921                                 pptable->I2cControllers[i].I2cProtocol);
1922                 pr_info("                   .Speed = %d\n",
1923                                 pptable->I2cControllers[i].Speed);
1924         }
1925
1926         pr_info("MemoryChannelEnabled = %d\n", pptable->MemoryChannelEnabled);
1927         pr_info("DramBitWidth = %d\n", pptable->DramBitWidth);
1928
1929         pr_info("TotalBoardPower = %d\n", pptable->TotalBoardPower);
1930
1931         pr_info("XgmiLinkSpeed\n");
1932         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
1933                 pr_info("  .[%d] = %d\n", i, pptable->XgmiLinkSpeed[i]);
1934         pr_info("XgmiLinkWidth\n");
1935         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
1936                 pr_info("  .[%d] = %d\n", i, pptable->XgmiLinkWidth[i]);
1937         pr_info("XgmiFclkFreq\n");
1938         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
1939                 pr_info("  .[%d] = %d\n", i, pptable->XgmiFclkFreq[i]);
1940         pr_info("XgmiSocVoltage\n");
1941         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
1942                 pr_info("  .[%d] = %d\n", i, pptable->XgmiSocVoltage[i]);
1943
1944 }
1945
1946 static bool arcturus_is_dpm_running(struct smu_context *smu)
1947 {
1948         int ret = 0;
1949         uint32_t feature_mask[2];
1950         unsigned long feature_enabled;
1951         ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
1952         feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
1953                            ((uint64_t)feature_mask[1] << 32));
1954         return !!(feature_enabled & SMC_DPM_FEATURE);
1955 }
1956
1957 static int arcturus_dpm_set_uvd_enable(struct smu_context *smu, bool enable)
1958 {
1959         struct smu_power_context *smu_power = &smu->smu_power;
1960         struct smu_power_gate *power_gate = &smu_power->power_gate;
1961         int ret = 0;
1962
1963         if (enable) {
1964                 if (!smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
1965                         ret = smu_feature_set_enabled(smu, SMU_FEATURE_VCN_PG_BIT, 1);
1966                         if (ret) {
1967                                 pr_err("[EnableVCNDPM] failed!\n");
1968                                 return ret;
1969                         }
1970                 }
1971                 power_gate->vcn_gated = false;
1972         } else {
1973                 if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
1974                         ret = smu_feature_set_enabled(smu, SMU_FEATURE_VCN_PG_BIT, 0);
1975                         if (ret) {
1976                                 pr_err("[DisableVCNDPM] failed!\n");
1977                                 return ret;
1978                         }
1979                 }
1980                 power_gate->vcn_gated = true;
1981         }
1982
1983         return ret;
1984 }
1985
1986
1987 static void arcturus_fill_eeprom_i2c_req(SwI2cRequest_t  *req, bool write,
1988                                   uint8_t address, uint32_t numbytes,
1989                                   uint8_t *data)
1990 {
1991         int i;
1992
1993         BUG_ON(numbytes > MAX_SW_I2C_COMMANDS);
1994
1995         req->I2CcontrollerPort = 0;
1996         req->I2CSpeed = 2;
1997         req->SlaveAddress = address;
1998         req->NumCmds = numbytes;
1999
2000         for (i = 0; i < numbytes; i++) {
2001                 SwI2cCmd_t *cmd =  &req->SwI2cCmds[i];
2002
2003                 /* First 2 bytes are always write for lower 2b EEPROM address */
2004                 if (i < 2)
2005                         cmd->Cmd = 1;
2006                 else
2007                         cmd->Cmd = write;
2008
2009
2010                 /* Add RESTART for read  after address filled */
2011                 cmd->CmdConfig |= (i == 2 && !write) ? CMDCONFIG_RESTART_MASK : 0;
2012
2013                 /* Add STOP in the end */
2014                 cmd->CmdConfig |= (i == (numbytes - 1)) ? CMDCONFIG_STOP_MASK : 0;
2015
2016                 /* Fill with data regardless if read or write to simplify code */
2017                 cmd->RegisterAddr = data[i];
2018         }
2019 }
2020
2021 static int arcturus_i2c_eeprom_read_data(struct i2c_adapter *control,
2022                                                uint8_t address,
2023                                                uint8_t *data,
2024                                                uint32_t numbytes)
2025 {
2026         uint32_t  i, ret = 0;
2027         SwI2cRequest_t req;
2028         struct amdgpu_device *adev = to_amdgpu_device(control);
2029         struct smu_table_context *smu_table = &adev->smu.smu_table;
2030         struct smu_table *table = &smu_table->driver_table;
2031
2032         memset(&req, 0, sizeof(req));
2033         arcturus_fill_eeprom_i2c_req(&req, false, address, numbytes, data);
2034
2035         mutex_lock(&adev->smu.mutex);
2036         /* Now read data starting with that address */
2037         ret = smu_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, &req,
2038                                         true);
2039         mutex_unlock(&adev->smu.mutex);
2040
2041         if (!ret) {
2042                 SwI2cRequest_t *res = (SwI2cRequest_t *)table->cpu_addr;
2043
2044                 /* Assume SMU  fills res.SwI2cCmds[i].Data with read bytes */
2045                 for (i = 0; i < numbytes; i++)
2046                         data[i] = res->SwI2cCmds[i].Data;
2047
2048                 pr_debug("arcturus_i2c_eeprom_read_data, address = %x, bytes = %d, data :",
2049                                   (uint16_t)address, numbytes);
2050
2051                 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_NONE,
2052                                8, 1, data, numbytes, false);
2053         } else
2054                 pr_err("arcturus_i2c_eeprom_read_data - error occurred :%x", ret);
2055
2056         return ret;
2057 }
2058
2059 static int arcturus_i2c_eeprom_write_data(struct i2c_adapter *control,
2060                                                 uint8_t address,
2061                                                 uint8_t *data,
2062                                                 uint32_t numbytes)
2063 {
2064         uint32_t ret;
2065         SwI2cRequest_t req;
2066         struct amdgpu_device *adev = to_amdgpu_device(control);
2067
2068         memset(&req, 0, sizeof(req));
2069         arcturus_fill_eeprom_i2c_req(&req, true, address, numbytes, data);
2070
2071         mutex_lock(&adev->smu.mutex);
2072         ret = smu_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, &req, true);
2073         mutex_unlock(&adev->smu.mutex);
2074
2075         if (!ret) {
2076                 pr_debug("arcturus_i2c_write(), address = %x, bytes = %d , data: ",
2077                                          (uint16_t)address, numbytes);
2078
2079                 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_NONE,
2080                                8, 1, data, numbytes, false);
2081                 /*
2082                  * According to EEPROM spec there is a MAX of 10 ms required for
2083                  * EEPROM to flush internal RX buffer after STOP was issued at the
2084                  * end of write transaction. During this time the EEPROM will not be
2085                  * responsive to any more commands - so wait a bit more.
2086                  */
2087                 msleep(10);
2088
2089         } else
2090                 pr_err("arcturus_i2c_write- error occurred :%x", ret);
2091
2092         return ret;
2093 }
2094
2095 static int arcturus_i2c_eeprom_i2c_xfer(struct i2c_adapter *i2c_adap,
2096                               struct i2c_msg *msgs, int num)
2097 {
2098         uint32_t  i, j, ret, data_size, data_chunk_size, next_eeprom_addr = 0;
2099         uint8_t *data_ptr, data_chunk[MAX_SW_I2C_COMMANDS] = { 0 };
2100
2101         for (i = 0; i < num; i++) {
2102                 /*
2103                  * SMU interface allows at most MAX_SW_I2C_COMMANDS bytes of data at
2104                  * once and hence the data needs to be spliced into chunks and sent each
2105                  * chunk separately
2106                  */
2107                 data_size = msgs[i].len - 2;
2108                 data_chunk_size = MAX_SW_I2C_COMMANDS - 2;
2109                 next_eeprom_addr = (msgs[i].buf[0] << 8 & 0xff00) | (msgs[i].buf[1] & 0xff);
2110                 data_ptr = msgs[i].buf + 2;
2111
2112                 for (j = 0; j < data_size / data_chunk_size; j++) {
2113                         /* Insert the EEPROM dest addess, bits 0-15 */
2114                         data_chunk[0] = ((next_eeprom_addr >> 8) & 0xff);
2115                         data_chunk[1] = (next_eeprom_addr & 0xff);
2116
2117                         if (msgs[i].flags & I2C_M_RD) {
2118                                 ret = arcturus_i2c_eeprom_read_data(i2c_adap,
2119                                                                 (uint8_t)msgs[i].addr,
2120                                                                 data_chunk, MAX_SW_I2C_COMMANDS);
2121
2122                                 memcpy(data_ptr, data_chunk + 2, data_chunk_size);
2123                         } else {
2124
2125                                 memcpy(data_chunk + 2, data_ptr, data_chunk_size);
2126
2127                                 ret = arcturus_i2c_eeprom_write_data(i2c_adap,
2128                                                                  (uint8_t)msgs[i].addr,
2129                                                                  data_chunk, MAX_SW_I2C_COMMANDS);
2130                         }
2131
2132                         if (ret) {
2133                                 num = -EIO;
2134                                 goto fail;
2135                         }
2136
2137                         next_eeprom_addr += data_chunk_size;
2138                         data_ptr += data_chunk_size;
2139                 }
2140
2141                 if (data_size % data_chunk_size) {
2142                         data_chunk[0] = ((next_eeprom_addr >> 8) & 0xff);
2143                         data_chunk[1] = (next_eeprom_addr & 0xff);
2144
2145                         if (msgs[i].flags & I2C_M_RD) {
2146                                 ret = arcturus_i2c_eeprom_read_data(i2c_adap,
2147                                                                 (uint8_t)msgs[i].addr,
2148                                                                 data_chunk, (data_size % data_chunk_size) + 2);
2149
2150                                 memcpy(data_ptr, data_chunk + 2, data_size % data_chunk_size);
2151                         } else {
2152                                 memcpy(data_chunk + 2, data_ptr, data_size % data_chunk_size);
2153
2154                                 ret = arcturus_i2c_eeprom_write_data(i2c_adap,
2155                                                                  (uint8_t)msgs[i].addr,
2156                                                                  data_chunk, (data_size % data_chunk_size) + 2);
2157                         }
2158
2159                         if (ret) {
2160                                 num = -EIO;
2161                                 goto fail;
2162                         }
2163                 }
2164         }
2165
2166 fail:
2167         return num;
2168 }
2169
2170 static u32 arcturus_i2c_eeprom_i2c_func(struct i2c_adapter *adap)
2171 {
2172         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
2173 }
2174
2175
2176 static const struct i2c_algorithm arcturus_i2c_eeprom_i2c_algo = {
2177         .master_xfer = arcturus_i2c_eeprom_i2c_xfer,
2178         .functionality = arcturus_i2c_eeprom_i2c_func,
2179 };
2180
2181 static int arcturus_i2c_eeprom_control_init(struct i2c_adapter *control)
2182 {
2183         struct amdgpu_device *adev = to_amdgpu_device(control);
2184         struct smu_context *smu = &adev->smu;
2185         int res;
2186
2187         if (!smu->pm_enabled)
2188                 return -EOPNOTSUPP;
2189
2190         control->owner = THIS_MODULE;
2191         control->class = I2C_CLASS_SPD;
2192         control->dev.parent = &adev->pdev->dev;
2193         control->algo = &arcturus_i2c_eeprom_i2c_algo;
2194         snprintf(control->name, sizeof(control->name), "AMDGPU EEPROM");
2195
2196         res = i2c_add_adapter(control);
2197         if (res)
2198                 DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
2199
2200         return res;
2201 }
2202
2203 static void arcturus_i2c_eeprom_control_fini(struct i2c_adapter *control)
2204 {
2205         struct amdgpu_device *adev = to_amdgpu_device(control);
2206         struct smu_context *smu = &adev->smu;
2207
2208         if (!smu->pm_enabled)
2209                 return;
2210
2211         i2c_del_adapter(control);
2212 }
2213
2214 static bool arcturus_is_baco_supported(struct smu_context *smu)
2215 {
2216         struct amdgpu_device *adev = smu->adev;
2217         uint32_t val;
2218
2219         if (!smu_v11_0_baco_is_support(smu))
2220                 return false;
2221
2222         val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
2223         return (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true : false;
2224 }
2225
2226 static uint32_t arcturus_get_pptable_power_limit(struct smu_context *smu)
2227 {
2228         PPTable_t *pptable = smu->smu_table.driver_pptable;
2229
2230         return pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
2231 }
2232
2233 static int arcturus_set_df_cstate(struct smu_context *smu,
2234                                   enum pp_df_cstate state)
2235 {
2236         uint32_t smu_version;
2237         int ret;
2238
2239         ret = smu_get_smc_version(smu, NULL, &smu_version);
2240         if (ret) {
2241                 pr_err("Failed to get smu version!\n");
2242                 return ret;
2243         }
2244
2245         /* PPSMC_MSG_DFCstateControl is supported by 54.15.0 and onwards */
2246         if (smu_version < 0x360F00) {
2247                 pr_err("DFCstateControl is only supported by PMFW 54.15.0 and onwards\n");
2248                 return -EINVAL;
2249         }
2250
2251         return smu_send_smc_msg_with_param(smu, SMU_MSG_DFCstateControl, state, NULL);
2252 }
2253
2254 static const struct pptable_funcs arcturus_ppt_funcs = {
2255         /* translate smu index into arcturus specific index */
2256         .get_smu_msg_index = arcturus_get_smu_msg_index,
2257         .get_smu_clk_index = arcturus_get_smu_clk_index,
2258         .get_smu_feature_index = arcturus_get_smu_feature_index,
2259         .get_smu_table_index = arcturus_get_smu_table_index,
2260         .get_smu_power_index= arcturus_get_pwr_src_index,
2261         .get_workload_type = arcturus_get_workload_type,
2262         /* internal structurs allocations */
2263         .tables_init = arcturus_tables_init,
2264         .alloc_dpm_context = arcturus_allocate_dpm_context,
2265         /* pptable related */
2266         .check_powerplay_table = arcturus_check_powerplay_table,
2267         .store_powerplay_table = arcturus_store_powerplay_table,
2268         .append_powerplay_table = arcturus_append_powerplay_table,
2269         /* init dpm */
2270         .get_allowed_feature_mask = arcturus_get_allowed_feature_mask,
2271         /* btc */
2272         .run_btc = arcturus_run_btc,
2273         /* dpm/clk tables */
2274         .set_default_dpm_table = arcturus_set_default_dpm_table,
2275         .populate_umd_state_clk = arcturus_populate_umd_state_clk,
2276         .get_thermal_temperature_range = arcturus_get_thermal_temperature_range,
2277         .get_current_clk_freq_by_table = arcturus_get_current_clk_freq_by_table,
2278         .print_clk_levels = arcturus_print_clk_levels,
2279         .force_clk_levels = arcturus_force_clk_levels,
2280         .read_sensor = arcturus_read_sensor,
2281         .get_fan_speed_percent = arcturus_get_fan_speed_percent,
2282         .get_fan_speed_rpm = arcturus_get_fan_speed_rpm,
2283         .force_dpm_limit_value = arcturus_force_dpm_limit_value,
2284         .unforce_dpm_levels = arcturus_unforce_dpm_levels,
2285         .get_profiling_clk_mask = arcturus_get_profiling_clk_mask,
2286         .get_power_profile_mode = arcturus_get_power_profile_mode,
2287         .set_power_profile_mode = arcturus_set_power_profile_mode,
2288         .set_performance_level = smu_v11_0_set_performance_level,
2289         /* debug (internal used) */
2290         .dump_pptable = arcturus_dump_pptable,
2291         .get_power_limit = arcturus_get_power_limit,
2292         .is_dpm_running = arcturus_is_dpm_running,
2293         .dpm_set_uvd_enable = arcturus_dpm_set_uvd_enable,
2294         .i2c_eeprom_init = arcturus_i2c_eeprom_control_init,
2295         .i2c_eeprom_fini = arcturus_i2c_eeprom_control_fini,
2296         .init_microcode = smu_v11_0_init_microcode,
2297         .load_microcode = smu_v11_0_load_microcode,
2298         .init_smc_tables = smu_v11_0_init_smc_tables,
2299         .fini_smc_tables = smu_v11_0_fini_smc_tables,
2300         .init_power = smu_v11_0_init_power,
2301         .fini_power = smu_v11_0_fini_power,
2302         .check_fw_status = smu_v11_0_check_fw_status,
2303         .setup_pptable = smu_v11_0_setup_pptable,
2304         .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
2305         .get_clk_info_from_vbios = smu_v11_0_get_clk_info_from_vbios,
2306         .check_pptable = smu_v11_0_check_pptable,
2307         .parse_pptable = smu_v11_0_parse_pptable,
2308         .populate_smc_tables = smu_v11_0_populate_smc_pptable,
2309         .check_fw_version = smu_v11_0_check_fw_version,
2310         .write_pptable = smu_v11_0_write_pptable,
2311         .set_min_dcef_deep_sleep = smu_v11_0_set_min_dcef_deep_sleep,
2312         .set_driver_table_location = smu_v11_0_set_driver_table_location,
2313         .set_tool_table_location = smu_v11_0_set_tool_table_location,
2314         .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
2315         .system_features_control = smu_v11_0_system_features_control,
2316         .send_smc_msg_with_param = smu_v11_0_send_msg_with_param,
2317         .init_display_count = smu_v11_0_init_display_count,
2318         .set_allowed_mask = smu_v11_0_set_allowed_mask,
2319         .get_enabled_mask = smu_v11_0_get_enabled_mask,
2320         .notify_display_change = smu_v11_0_notify_display_change,
2321         .set_power_limit = smu_v11_0_set_power_limit,
2322         .get_current_clk_freq = smu_v11_0_get_current_clk_freq,
2323         .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
2324         .start_thermal_control = smu_v11_0_start_thermal_control,
2325         .stop_thermal_control = smu_v11_0_stop_thermal_control,
2326         .set_deep_sleep_dcefclk = smu_v11_0_set_deep_sleep_dcefclk,
2327         .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
2328         .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
2329         .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
2330         .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
2331         .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
2332         .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
2333         .gfx_off_control = smu_v11_0_gfx_off_control,
2334         .register_irq_handler = smu_v11_0_register_irq_handler,
2335         .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
2336         .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
2337         .baco_is_support= arcturus_is_baco_supported,
2338         .baco_get_state = smu_v11_0_baco_get_state,
2339         .baco_set_state = smu_v11_0_baco_set_state,
2340         .baco_enter = smu_v11_0_baco_enter,
2341         .baco_exit = smu_v11_0_baco_exit,
2342         .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
2343         .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
2344         .override_pcie_parameters = smu_v11_0_override_pcie_parameters,
2345         .get_pptable_power_limit = arcturus_get_pptable_power_limit,
2346         .set_df_cstate = arcturus_set_df_cstate,
2347 };
2348
2349 void arcturus_set_ppt_funcs(struct smu_context *smu)
2350 {
2351         smu->ppt_funcs = &arcturus_ppt_funcs;
2352 }