2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <linux/types.h>
25 #include <linux/kernel.h>
26 #include <linux/slab.h>
27 #include "atom-types.h"
29 #include "processpptables.h"
30 #include "cgs_common.h"
31 #include "smu/smu_8_0_d.h"
32 #include "smu8_fusion.h"
33 #include "smu/smu_8_0_sh_mask.h"
36 #include "hardwaremanager.h"
39 #include "power_state.h"
40 #include "cz_clockpowergating.h"
42 #define ixSMUSVI_NB_CURRENTVID 0xD8230044
43 #define CURRENT_NB_VID_MASK 0xff000000
44 #define CURRENT_NB_VID__SHIFT 24
45 #define ixSMUSVI_GFX_CURRENTVID 0xD8230048
46 #define CURRENT_GFX_VID_MASK 0xff000000
47 #define CURRENT_GFX_VID__SHIFT 24
49 static const unsigned long PhwCz_Magic = (unsigned long) PHM_Cz_Magic;
51 static struct cz_power_state *cast_PhwCzPowerState(struct pp_hw_power_state *hw_ps)
53 if (PhwCz_Magic != hw_ps->magic)
56 return (struct cz_power_state *)hw_ps;
59 static const struct cz_power_state *cast_const_PhwCzPowerState(
60 const struct pp_hw_power_state *hw_ps)
62 if (PhwCz_Magic != hw_ps->magic)
65 return (struct cz_power_state *)hw_ps;
68 static uint32_t cz_get_eclk_level(struct pp_hwmgr *hwmgr,
69 uint32_t clock, uint32_t msg)
72 struct phm_vce_clock_voltage_dependency_table *ptable =
73 hwmgr->dyn_state.vce_clock_voltage_dependency_table;
76 case PPSMC_MSG_SetEclkSoftMin:
77 case PPSMC_MSG_SetEclkHardMin:
78 for (i = 0; i < (int)ptable->count; i++) {
79 if (clock <= ptable->entries[i].ecclk)
84 case PPSMC_MSG_SetEclkSoftMax:
85 case PPSMC_MSG_SetEclkHardMax:
86 for (i = ptable->count - 1; i >= 0; i--) {
87 if (clock >= ptable->entries[i].ecclk)
99 static uint32_t cz_get_sclk_level(struct pp_hwmgr *hwmgr,
100 uint32_t clock, uint32_t msg)
103 struct phm_clock_voltage_dependency_table *table =
104 hwmgr->dyn_state.vddc_dependency_on_sclk;
107 case PPSMC_MSG_SetSclkSoftMin:
108 case PPSMC_MSG_SetSclkHardMin:
109 for (i = 0; i < (int)table->count; i++) {
110 if (clock <= table->entries[i].clk)
115 case PPSMC_MSG_SetSclkSoftMax:
116 case PPSMC_MSG_SetSclkHardMax:
117 for (i = table->count - 1; i >= 0; i--) {
118 if (clock >= table->entries[i].clk)
129 static uint32_t cz_get_uvd_level(struct pp_hwmgr *hwmgr,
130 uint32_t clock, uint32_t msg)
133 struct phm_uvd_clock_voltage_dependency_table *ptable =
134 hwmgr->dyn_state.uvd_clock_voltage_dependency_table;
137 case PPSMC_MSG_SetUvdSoftMin:
138 case PPSMC_MSG_SetUvdHardMin:
139 for (i = 0; i < (int)ptable->count; i++) {
140 if (clock <= ptable->entries[i].vclk)
145 case PPSMC_MSG_SetUvdSoftMax:
146 case PPSMC_MSG_SetUvdHardMax:
147 for (i = ptable->count - 1; i >= 0; i--) {
148 if (clock >= ptable->entries[i].vclk)
160 static uint32_t cz_get_max_sclk_level(struct pp_hwmgr *hwmgr)
162 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
164 if (cz_hwmgr->max_sclk_level == 0) {
165 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetMaxSclkLevel);
166 cz_hwmgr->max_sclk_level = smum_get_argument(hwmgr->smumgr) + 1;
169 return cz_hwmgr->max_sclk_level;
172 static int cz_initialize_dpm_defaults(struct pp_hwmgr *hwmgr)
174 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
176 struct cgs_system_info sys_info = {0};
179 cz_hwmgr->gfx_ramp_step = 256*25/100;
180 cz_hwmgr->gfx_ramp_delay = 1; /* by default, we delay 1us */
182 for (i = 0; i < CZ_MAX_HARDWARE_POWERLEVELS; i++)
183 cz_hwmgr->activity_target[i] = CZ_AT_DFLT;
185 cz_hwmgr->mgcg_cgtt_local0 = 0x00000000;
186 cz_hwmgr->mgcg_cgtt_local1 = 0x00000000;
187 cz_hwmgr->clock_slow_down_freq = 25000;
188 cz_hwmgr->skip_clock_slow_down = 1;
189 cz_hwmgr->enable_nb_ps_policy = 1; /* disable until UNB is ready, Enabled */
190 cz_hwmgr->voltage_drop_in_dce_power_gating = 0; /* disable until fully verified */
191 cz_hwmgr->voting_rights_clients = 0x00C00033;
192 cz_hwmgr->static_screen_threshold = 8;
193 cz_hwmgr->ddi_power_gating_disabled = 0;
194 cz_hwmgr->bapm_enabled = 1;
195 cz_hwmgr->voltage_drop_threshold = 0;
196 cz_hwmgr->gfx_power_gating_threshold = 500;
197 cz_hwmgr->vce_slow_sclk_threshold = 20000;
198 cz_hwmgr->dce_slow_sclk_threshold = 30000;
199 cz_hwmgr->disable_driver_thermal_policy = 1;
200 cz_hwmgr->disable_nb_ps3_in_battery = 0;
202 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
203 PHM_PlatformCaps_ABM);
205 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
206 PHM_PlatformCaps_NonABMSupportInPPLib);
208 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
209 PHM_PlatformCaps_DynamicM3Arbiter);
211 cz_hwmgr->override_dynamic_mgpg = 1;
213 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
214 PHM_PlatformCaps_DynamicPatchPowerState);
216 cz_hwmgr->thermal_auto_throttling_treshold = 0;
217 cz_hwmgr->tdr_clock = 0;
218 cz_hwmgr->disable_gfx_power_gating_in_uvd = 0;
220 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
221 PHM_PlatformCaps_DynamicUVDState);
223 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
224 PHM_PlatformCaps_UVDDPM);
225 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
226 PHM_PlatformCaps_VCEDPM);
228 cz_hwmgr->cc6_settings.cpu_cc6_disable = false;
229 cz_hwmgr->cc6_settings.cpu_pstate_disable = false;
230 cz_hwmgr->cc6_settings.nb_pstate_switch_disable = false;
231 cz_hwmgr->cc6_settings.cpu_pstate_separation_time = 0;
233 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
234 PHM_PlatformCaps_DisableVoltageIsland);
236 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
237 PHM_PlatformCaps_UVDPowerGating);
238 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
239 PHM_PlatformCaps_VCEPowerGating);
240 sys_info.size = sizeof(struct cgs_system_info);
241 sys_info.info_id = CGS_SYSTEM_INFO_PG_FLAGS;
242 result = cgs_query_system_info(hwmgr->device, &sys_info);
244 if (sys_info.value & AMD_PG_SUPPORT_UVD)
245 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
246 PHM_PlatformCaps_UVDPowerGating);
247 if (sys_info.value & AMD_PG_SUPPORT_VCE)
248 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
249 PHM_PlatformCaps_VCEPowerGating);
255 static uint32_t cz_convert_8Bit_index_to_voltage(
256 struct pp_hwmgr *hwmgr, uint16_t voltage)
258 return 6200 - (voltage * 25);
261 static int cz_construct_max_power_limits_table(struct pp_hwmgr *hwmgr,
262 struct phm_clock_and_voltage_limits *table)
264 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)hwmgr->backend;
265 struct cz_sys_info *sys_info = &cz_hwmgr->sys_info;
266 struct phm_clock_voltage_dependency_table *dep_table =
267 hwmgr->dyn_state.vddc_dependency_on_sclk;
269 if (dep_table->count > 0) {
270 table->sclk = dep_table->entries[dep_table->count-1].clk;
271 table->vddc = cz_convert_8Bit_index_to_voltage(hwmgr,
272 (uint16_t)dep_table->entries[dep_table->count-1].v);
274 table->mclk = sys_info->nbp_memory_clock[0];
278 static int cz_init_dynamic_state_adjustment_rule_settings(
279 struct pp_hwmgr *hwmgr,
280 ATOM_CLK_VOLT_CAPABILITY *disp_voltage_table)
282 uint32_t table_size =
283 sizeof(struct phm_clock_voltage_dependency_table) +
284 (7 * sizeof(struct phm_clock_voltage_dependency_record));
286 struct phm_clock_voltage_dependency_table *table_clk_vlt =
287 kzalloc(table_size, GFP_KERNEL);
289 if (NULL == table_clk_vlt) {
290 printk(KERN_ERR "[ powerplay ] Can not allocate memory!\n");
294 table_clk_vlt->count = 8;
295 table_clk_vlt->entries[0].clk = PP_DAL_POWERLEVEL_0;
296 table_clk_vlt->entries[0].v = 0;
297 table_clk_vlt->entries[1].clk = PP_DAL_POWERLEVEL_1;
298 table_clk_vlt->entries[1].v = 1;
299 table_clk_vlt->entries[2].clk = PP_DAL_POWERLEVEL_2;
300 table_clk_vlt->entries[2].v = 2;
301 table_clk_vlt->entries[3].clk = PP_DAL_POWERLEVEL_3;
302 table_clk_vlt->entries[3].v = 3;
303 table_clk_vlt->entries[4].clk = PP_DAL_POWERLEVEL_4;
304 table_clk_vlt->entries[4].v = 4;
305 table_clk_vlt->entries[5].clk = PP_DAL_POWERLEVEL_5;
306 table_clk_vlt->entries[5].v = 5;
307 table_clk_vlt->entries[6].clk = PP_DAL_POWERLEVEL_6;
308 table_clk_vlt->entries[6].v = 6;
309 table_clk_vlt->entries[7].clk = PP_DAL_POWERLEVEL_7;
310 table_clk_vlt->entries[7].v = 7;
311 hwmgr->dyn_state.vddc_dep_on_dal_pwrl = table_clk_vlt;
316 static int cz_get_system_info_data(struct pp_hwmgr *hwmgr)
318 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)hwmgr->backend;
319 ATOM_INTEGRATED_SYSTEM_INFO_V1_9 *info = NULL;
325 info = (ATOM_INTEGRATED_SYSTEM_INFO_V1_9 *) cgs_atom_get_data_table(
327 GetIndexIntoMasterTable(DATA, IntegratedSystemInfo),
328 &size, &frev, &crev);
331 printk(KERN_ERR "[ powerplay ] Unsupported IGP table: %d %d\n", frev, crev);
336 printk(KERN_ERR "[ powerplay ] Could not retrieve the Integrated System Info Table!\n");
340 cz_hwmgr->sys_info.bootup_uma_clock =
341 le32_to_cpu(info->ulBootUpUMAClock);
343 cz_hwmgr->sys_info.bootup_engine_clock =
344 le32_to_cpu(info->ulBootUpEngineClock);
346 cz_hwmgr->sys_info.dentist_vco_freq =
347 le32_to_cpu(info->ulDentistVCOFreq);
349 cz_hwmgr->sys_info.system_config =
350 le32_to_cpu(info->ulSystemConfig);
352 cz_hwmgr->sys_info.bootup_nb_voltage_index =
353 le16_to_cpu(info->usBootUpNBVoltage);
355 cz_hwmgr->sys_info.htc_hyst_lmt =
356 (info->ucHtcHystLmt == 0) ? 5 : info->ucHtcHystLmt;
358 cz_hwmgr->sys_info.htc_tmp_lmt =
359 (info->ucHtcTmpLmt == 0) ? 203 : info->ucHtcTmpLmt;
361 if (cz_hwmgr->sys_info.htc_tmp_lmt <=
362 cz_hwmgr->sys_info.htc_hyst_lmt) {
363 printk(KERN_ERR "[ powerplay ] The htcTmpLmt should be larger than htcHystLmt.\n");
367 cz_hwmgr->sys_info.nb_dpm_enable =
368 cz_hwmgr->enable_nb_ps_policy &&
369 (le32_to_cpu(info->ulSystemConfig) >> 3 & 0x1);
371 for (i = 0; i < CZ_NUM_NBPSTATES; i++) {
372 if (i < CZ_NUM_NBPMEMORYCLOCK) {
373 cz_hwmgr->sys_info.nbp_memory_clock[i] =
374 le32_to_cpu(info->ulNbpStateMemclkFreq[i]);
376 cz_hwmgr->sys_info.nbp_n_clock[i] =
377 le32_to_cpu(info->ulNbpStateNClkFreq[i]);
380 for (i = 0; i < MAX_DISPLAY_CLOCK_LEVEL; i++) {
381 cz_hwmgr->sys_info.display_clock[i] =
382 le32_to_cpu(info->sDispClkVoltageMapping[i].ulMaximumSupportedCLK);
385 /* Here use 4 levels, make sure not exceed */
386 for (i = 0; i < CZ_NUM_NBPSTATES; i++) {
387 cz_hwmgr->sys_info.nbp_voltage_index[i] =
388 le16_to_cpu(info->usNBPStateVoltage[i]);
391 if (!cz_hwmgr->sys_info.nb_dpm_enable) {
392 for (i = 1; i < CZ_NUM_NBPSTATES; i++) {
393 if (i < CZ_NUM_NBPMEMORYCLOCK) {
394 cz_hwmgr->sys_info.nbp_memory_clock[i] =
395 cz_hwmgr->sys_info.nbp_memory_clock[0];
397 cz_hwmgr->sys_info.nbp_n_clock[i] =
398 cz_hwmgr->sys_info.nbp_n_clock[0];
399 cz_hwmgr->sys_info.nbp_voltage_index[i] =
400 cz_hwmgr->sys_info.nbp_voltage_index[0];
404 if (le32_to_cpu(info->ulGPUCapInfo) &
405 SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS) {
406 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
407 PHM_PlatformCaps_EnableDFSBypass);
410 cz_hwmgr->sys_info.uma_channel_number = info->ucUMAChannelNumber;
412 cz_construct_max_power_limits_table (hwmgr,
413 &hwmgr->dyn_state.max_clock_voltage_on_ac);
415 cz_init_dynamic_state_adjustment_rule_settings(hwmgr,
416 &info->sDISPCLK_Voltage[0]);
421 static int cz_construct_boot_state(struct pp_hwmgr *hwmgr)
423 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
425 cz_hwmgr->boot_power_level.engineClock =
426 cz_hwmgr->sys_info.bootup_engine_clock;
428 cz_hwmgr->boot_power_level.vddcIndex =
429 (uint8_t)cz_hwmgr->sys_info.bootup_nb_voltage_index;
431 cz_hwmgr->boot_power_level.dsDividerIndex = 0;
432 cz_hwmgr->boot_power_level.ssDividerIndex = 0;
433 cz_hwmgr->boot_power_level.allowGnbSlow = 1;
434 cz_hwmgr->boot_power_level.forceNBPstate = 0;
435 cz_hwmgr->boot_power_level.hysteresis_up = 0;
436 cz_hwmgr->boot_power_level.numSIMDToPowerDown = 0;
437 cz_hwmgr->boot_power_level.display_wm = 0;
438 cz_hwmgr->boot_power_level.vce_wm = 0;
443 static int cz_tf_reset_active_process_mask(struct pp_hwmgr *hwmgr, void *input,
444 void *output, void *storage, int result)
449 static int cz_tf_upload_pptable_to_smu(struct pp_hwmgr *hwmgr, void *input,
450 void *output, void *storage, int result)
452 struct SMU8_Fusion_ClkTable *clock_table;
456 pp_atomctrl_clock_dividers_kong dividers;
458 struct phm_clock_voltage_dependency_table *vddc_table =
459 hwmgr->dyn_state.vddc_dependency_on_sclk;
460 struct phm_clock_voltage_dependency_table *vdd_gfx_table =
461 hwmgr->dyn_state.vdd_gfx_dependency_on_sclk;
462 struct phm_acp_clock_voltage_dependency_table *acp_table =
463 hwmgr->dyn_state.acp_clock_voltage_dependency_table;
464 struct phm_uvd_clock_voltage_dependency_table *uvd_table =
465 hwmgr->dyn_state.uvd_clock_voltage_dependency_table;
466 struct phm_vce_clock_voltage_dependency_table *vce_table =
467 hwmgr->dyn_state.vce_clock_voltage_dependency_table;
469 if (!hwmgr->need_pp_table_upload)
472 ret = smum_download_powerplay_table(hwmgr->smumgr, &table);
474 PP_ASSERT_WITH_CODE((0 == ret && NULL != table),
475 "Fail to get clock table from SMU!", return -EINVAL;);
477 clock_table = (struct SMU8_Fusion_ClkTable *)table;
479 /* patch clock table */
480 PP_ASSERT_WITH_CODE((vddc_table->count <= CZ_MAX_HARDWARE_POWERLEVELS),
481 "Dependency table entry exceeds max limit!", return -EINVAL;);
482 PP_ASSERT_WITH_CODE((vdd_gfx_table->count <= CZ_MAX_HARDWARE_POWERLEVELS),
483 "Dependency table entry exceeds max limit!", return -EINVAL;);
484 PP_ASSERT_WITH_CODE((acp_table->count <= CZ_MAX_HARDWARE_POWERLEVELS),
485 "Dependency table entry exceeds max limit!", return -EINVAL;);
486 PP_ASSERT_WITH_CODE((uvd_table->count <= CZ_MAX_HARDWARE_POWERLEVELS),
487 "Dependency table entry exceeds max limit!", return -EINVAL;);
488 PP_ASSERT_WITH_CODE((vce_table->count <= CZ_MAX_HARDWARE_POWERLEVELS),
489 "Dependency table entry exceeds max limit!", return -EINVAL;);
491 for (i = 0; i < CZ_MAX_HARDWARE_POWERLEVELS; i++) {
494 clock_table->SclkBreakdownTable.ClkLevel[i].GnbVid =
495 (i < vddc_table->count) ? (uint8_t)vddc_table->entries[i].v : 0;
496 clock_table->SclkBreakdownTable.ClkLevel[i].Frequency =
497 (i < vddc_table->count) ? vddc_table->entries[i].clk : 0;
499 atomctrl_get_engine_pll_dividers_kong(hwmgr,
500 clock_table->SclkBreakdownTable.ClkLevel[i].Frequency,
503 clock_table->SclkBreakdownTable.ClkLevel[i].DfsDid =
504 (uint8_t)dividers.pll_post_divider;
507 clock_table->SclkBreakdownTable.ClkLevel[i].GfxVid =
508 (i < vdd_gfx_table->count) ? (uint8_t)vdd_gfx_table->entries[i].v : 0;
511 clock_table->AclkBreakdownTable.ClkLevel[i].GfxVid =
512 (i < acp_table->count) ? (uint8_t)acp_table->entries[i].v : 0;
513 clock_table->AclkBreakdownTable.ClkLevel[i].Frequency =
514 (i < acp_table->count) ? acp_table->entries[i].acpclk : 0;
516 atomctrl_get_engine_pll_dividers_kong(hwmgr,
517 clock_table->AclkBreakdownTable.ClkLevel[i].Frequency,
520 clock_table->AclkBreakdownTable.ClkLevel[i].DfsDid =
521 (uint8_t)dividers.pll_post_divider;
525 clock_table->VclkBreakdownTable.ClkLevel[i].GfxVid =
526 (i < uvd_table->count) ? (uint8_t)uvd_table->entries[i].v : 0;
527 clock_table->VclkBreakdownTable.ClkLevel[i].Frequency =
528 (i < uvd_table->count) ? uvd_table->entries[i].vclk : 0;
530 atomctrl_get_engine_pll_dividers_kong(hwmgr,
531 clock_table->VclkBreakdownTable.ClkLevel[i].Frequency,
534 clock_table->VclkBreakdownTable.ClkLevel[i].DfsDid =
535 (uint8_t)dividers.pll_post_divider;
537 clock_table->DclkBreakdownTable.ClkLevel[i].GfxVid =
538 (i < uvd_table->count) ? (uint8_t)uvd_table->entries[i].v : 0;
539 clock_table->DclkBreakdownTable.ClkLevel[i].Frequency =
540 (i < uvd_table->count) ? uvd_table->entries[i].dclk : 0;
542 atomctrl_get_engine_pll_dividers_kong(hwmgr,
543 clock_table->DclkBreakdownTable.ClkLevel[i].Frequency,
546 clock_table->DclkBreakdownTable.ClkLevel[i].DfsDid =
547 (uint8_t)dividers.pll_post_divider;
550 clock_table->EclkBreakdownTable.ClkLevel[i].GfxVid =
551 (i < vce_table->count) ? (uint8_t)vce_table->entries[i].v : 0;
552 clock_table->EclkBreakdownTable.ClkLevel[i].Frequency =
553 (i < vce_table->count) ? vce_table->entries[i].ecclk : 0;
556 atomctrl_get_engine_pll_dividers_kong(hwmgr,
557 clock_table->EclkBreakdownTable.ClkLevel[i].Frequency,
560 clock_table->EclkBreakdownTable.ClkLevel[i].DfsDid =
561 (uint8_t)dividers.pll_post_divider;
564 ret = smum_upload_powerplay_table(hwmgr->smumgr);
569 static int cz_tf_init_sclk_limit(struct pp_hwmgr *hwmgr, void *input,
570 void *output, void *storage, int result)
572 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
573 struct phm_clock_voltage_dependency_table *table =
574 hwmgr->dyn_state.vddc_dependency_on_sclk;
575 unsigned long clock = 0, level;
577 if (NULL == table || table->count <= 0)
580 cz_hwmgr->sclk_dpm.soft_min_clk = table->entries[0].clk;
581 cz_hwmgr->sclk_dpm.hard_min_clk = table->entries[0].clk;
583 level = cz_get_max_sclk_level(hwmgr) - 1;
585 if (level < table->count)
586 clock = table->entries[level].clk;
588 clock = table->entries[table->count - 1].clk;
590 cz_hwmgr->sclk_dpm.soft_max_clk = clock;
591 cz_hwmgr->sclk_dpm.hard_max_clk = clock;
596 static int cz_tf_init_uvd_limit(struct pp_hwmgr *hwmgr, void *input,
597 void *output, void *storage, int result)
599 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
600 struct phm_uvd_clock_voltage_dependency_table *table =
601 hwmgr->dyn_state.uvd_clock_voltage_dependency_table;
602 unsigned long clock = 0, level;
604 if (NULL == table || table->count <= 0)
607 cz_hwmgr->uvd_dpm.soft_min_clk = 0;
608 cz_hwmgr->uvd_dpm.hard_min_clk = 0;
610 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetMaxUvdLevel);
611 level = smum_get_argument(hwmgr->smumgr);
613 if (level < table->count)
614 clock = table->entries[level].vclk;
616 clock = table->entries[table->count - 1].vclk;
618 cz_hwmgr->uvd_dpm.soft_max_clk = clock;
619 cz_hwmgr->uvd_dpm.hard_max_clk = clock;
624 static int cz_tf_init_vce_limit(struct pp_hwmgr *hwmgr, void *input,
625 void *output, void *storage, int result)
627 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
628 struct phm_vce_clock_voltage_dependency_table *table =
629 hwmgr->dyn_state.vce_clock_voltage_dependency_table;
630 unsigned long clock = 0, level;
632 if (NULL == table || table->count <= 0)
635 cz_hwmgr->vce_dpm.soft_min_clk = 0;
636 cz_hwmgr->vce_dpm.hard_min_clk = 0;
638 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetMaxEclkLevel);
639 level = smum_get_argument(hwmgr->smumgr);
641 if (level < table->count)
642 clock = table->entries[level].ecclk;
644 clock = table->entries[table->count - 1].ecclk;
646 cz_hwmgr->vce_dpm.soft_max_clk = clock;
647 cz_hwmgr->vce_dpm.hard_max_clk = clock;
652 static int cz_tf_init_acp_limit(struct pp_hwmgr *hwmgr, void *input,
653 void *output, void *storage, int result)
655 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
656 struct phm_acp_clock_voltage_dependency_table *table =
657 hwmgr->dyn_state.acp_clock_voltage_dependency_table;
658 unsigned long clock = 0, level;
660 if (NULL == table || table->count <= 0)
663 cz_hwmgr->acp_dpm.soft_min_clk = 0;
664 cz_hwmgr->acp_dpm.hard_min_clk = 0;
666 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetMaxAclkLevel);
667 level = smum_get_argument(hwmgr->smumgr);
669 if (level < table->count)
670 clock = table->entries[level].acpclk;
672 clock = table->entries[table->count - 1].acpclk;
674 cz_hwmgr->acp_dpm.soft_max_clk = clock;
675 cz_hwmgr->acp_dpm.hard_max_clk = clock;
679 static int cz_tf_init_power_gate_state(struct pp_hwmgr *hwmgr, void *input,
680 void *output, void *storage, int result)
682 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
684 cz_hwmgr->uvd_power_gated = false;
685 cz_hwmgr->vce_power_gated = false;
686 cz_hwmgr->samu_power_gated = false;
687 cz_hwmgr->acp_power_gated = false;
688 cz_hwmgr->pgacpinit = true;
693 static int cz_tf_init_sclk_threshold(struct pp_hwmgr *hwmgr, void *input,
694 void *output, void *storage, int result)
696 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
698 cz_hwmgr->low_sclk_interrupt_threshold = 0;
702 static int cz_tf_update_sclk_limit(struct pp_hwmgr *hwmgr,
703 void *input, void *output,
704 void *storage, int result)
706 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
707 struct phm_clock_voltage_dependency_table *table =
708 hwmgr->dyn_state.vddc_dependency_on_sclk;
710 unsigned long clock = 0;
712 unsigned long stable_pstate_sclk;
713 unsigned long percentage;
715 cz_hwmgr->sclk_dpm.soft_min_clk = table->entries[0].clk;
716 level = cz_get_max_sclk_level(hwmgr) - 1;
718 if (level < table->count)
719 cz_hwmgr->sclk_dpm.soft_max_clk = table->entries[level].clk;
721 cz_hwmgr->sclk_dpm.soft_max_clk = table->entries[table->count - 1].clk;
723 clock = hwmgr->display_config.min_core_set_clock;
725 printk(KERN_INFO "[ powerplay ] min_core_set_clock not set\n");
727 if (cz_hwmgr->sclk_dpm.hard_min_clk != clock) {
728 cz_hwmgr->sclk_dpm.hard_min_clk = clock;
730 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
731 PPSMC_MSG_SetSclkHardMin,
732 cz_get_sclk_level(hwmgr,
733 cz_hwmgr->sclk_dpm.hard_min_clk,
734 PPSMC_MSG_SetSclkHardMin));
737 clock = cz_hwmgr->sclk_dpm.soft_min_clk;
739 /* update minimum clocks for Stable P-State feature */
740 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
741 PHM_PlatformCaps_StablePState)) {
743 /*Sclk - calculate sclk value based on percentage and find FLOOR sclk from VddcDependencyOnSCLK table */
744 stable_pstate_sclk = (hwmgr->dyn_state.max_clock_voltage_on_ac.mclk *
747 if (clock < stable_pstate_sclk)
748 clock = stable_pstate_sclk;
750 if (clock < hwmgr->gfx_arbiter.sclk)
751 clock = hwmgr->gfx_arbiter.sclk;
754 if (cz_hwmgr->sclk_dpm.soft_min_clk != clock) {
755 cz_hwmgr->sclk_dpm.soft_min_clk = clock;
756 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
757 PPSMC_MSG_SetSclkSoftMin,
758 cz_get_sclk_level(hwmgr,
759 cz_hwmgr->sclk_dpm.soft_min_clk,
760 PPSMC_MSG_SetSclkSoftMin));
763 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
764 PHM_PlatformCaps_StablePState) &&
765 cz_hwmgr->sclk_dpm.soft_max_clk != clock) {
766 cz_hwmgr->sclk_dpm.soft_max_clk = clock;
767 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
768 PPSMC_MSG_SetSclkSoftMax,
769 cz_get_sclk_level(hwmgr,
770 cz_hwmgr->sclk_dpm.soft_max_clk,
771 PPSMC_MSG_SetSclkSoftMax));
777 static int cz_tf_set_deep_sleep_sclk_threshold(struct pp_hwmgr *hwmgr,
778 void *input, void *output,
779 void *storage, int result)
781 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
782 PHM_PlatformCaps_SclkDeepSleep)) {
783 uint32_t clks = hwmgr->display_config.min_core_set_clock_in_sr;
785 clks = CZ_MIN_DEEP_SLEEP_SCLK;
787 PP_DBG_LOG("Setting Deep Sleep Clock: %d\n", clks);
789 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
790 PPSMC_MSG_SetMinDeepSleepSclk,
797 static int cz_tf_set_watermark_threshold(struct pp_hwmgr *hwmgr,
798 void *input, void *output,
799 void *storage, int result)
801 struct cz_hwmgr *cz_hwmgr =
802 (struct cz_hwmgr *)(hwmgr->backend);
804 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
805 PPSMC_MSG_SetWatermarkFrequency,
806 cz_hwmgr->sclk_dpm.soft_max_clk);
811 static int cz_tf_set_enabled_levels(struct pp_hwmgr *hwmgr,
812 void *input, void *output,
813 void *storage, int result)
819 static int cz_tf_enable_nb_dpm(struct pp_hwmgr *hwmgr,
820 void *input, void *output,
821 void *storage, int result)
825 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
826 unsigned long dpm_features = 0;
828 if (!cz_hwmgr->is_nb_dpm_enabled) {
829 PP_DBG_LOG("enabling ALL SMU features.\n");
830 dpm_features |= NB_DPM_MASK;
831 ret = smum_send_msg_to_smc_with_parameter(
833 PPSMC_MSG_EnableAllSmuFeatures,
836 cz_hwmgr->is_nb_dpm_enabled = true;
842 static int cz_nbdpm_pstate_enable_disable(struct pp_hwmgr *hwmgr, bool enable, bool lock)
844 struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
846 if (hw_data->is_nb_dpm_enabled) {
848 PP_DBG_LOG("enable Low Memory PState.\n");
850 return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
851 PPSMC_MSG_EnableLowMemoryPstate,
854 PP_DBG_LOG("disable Low Memory PState.\n");
856 return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
857 PPSMC_MSG_DisableLowMemoryPstate,
865 static int cz_tf_update_low_mem_pstate(struct pp_hwmgr *hwmgr,
866 void *input, void *output,
867 void *storage, int result)
870 bool enable_low_mem_state;
871 struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
872 const struct phm_set_power_state_input *states = (struct phm_set_power_state_input *)input;
873 const struct cz_power_state *pnew_state = cast_const_PhwCzPowerState(states->pnew_state);
875 if (hw_data->sys_info.nb_dpm_enable) {
876 disable_switch = hw_data->cc6_settings.nb_pstate_switch_disable ? true : false;
877 enable_low_mem_state = hw_data->cc6_settings.nb_pstate_switch_disable ? false : true;
879 if (pnew_state->action == FORCE_HIGH)
880 cz_nbdpm_pstate_enable_disable(hwmgr, false, disable_switch);
881 else if (pnew_state->action == CANCEL_FORCE_HIGH)
882 cz_nbdpm_pstate_enable_disable(hwmgr, true, disable_switch);
884 cz_nbdpm_pstate_enable_disable(hwmgr, enable_low_mem_state, disable_switch);
889 static const struct phm_master_table_item cz_set_power_state_list[] = {
890 { .tableFunction = cz_tf_update_sclk_limit },
891 { .tableFunction = cz_tf_set_deep_sleep_sclk_threshold },
892 { .tableFunction = cz_tf_set_watermark_threshold },
893 { .tableFunction = cz_tf_set_enabled_levels },
894 { .tableFunction = cz_tf_enable_nb_dpm },
895 { .tableFunction = cz_tf_update_low_mem_pstate },
899 static const struct phm_master_table_header cz_set_power_state_master = {
901 PHM_MasterTableFlag_None,
902 cz_set_power_state_list
905 static const struct phm_master_table_item cz_setup_asic_list[] = {
906 { .tableFunction = cz_tf_reset_active_process_mask },
907 { .tableFunction = cz_tf_upload_pptable_to_smu },
908 { .tableFunction = cz_tf_init_sclk_limit },
909 { .tableFunction = cz_tf_init_uvd_limit },
910 { .tableFunction = cz_tf_init_vce_limit },
911 { .tableFunction = cz_tf_init_acp_limit },
912 { .tableFunction = cz_tf_init_power_gate_state },
913 { .tableFunction = cz_tf_init_sclk_threshold },
917 static const struct phm_master_table_header cz_setup_asic_master = {
919 PHM_MasterTableFlag_None,
923 static int cz_tf_power_up_display_clock_sys_pll(struct pp_hwmgr *hwmgr,
924 void *input, void *output,
925 void *storage, int result)
927 struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
928 hw_data->disp_clk_bypass_pending = false;
929 hw_data->disp_clk_bypass = false;
934 static int cz_tf_clear_nb_dpm_flag(struct pp_hwmgr *hwmgr,
935 void *input, void *output,
936 void *storage, int result)
938 struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
939 hw_data->is_nb_dpm_enabled = false;
944 static int cz_tf_reset_cc6_data(struct pp_hwmgr *hwmgr,
945 void *input, void *output,
946 void *storage, int result)
948 struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
950 hw_data->cc6_settings.cc6_setting_changed = false;
951 hw_data->cc6_settings.cpu_pstate_separation_time = 0;
952 hw_data->cc6_settings.cpu_cc6_disable = false;
953 hw_data->cc6_settings.cpu_pstate_disable = false;
958 static const struct phm_master_table_item cz_power_down_asic_list[] = {
959 { .tableFunction = cz_tf_power_up_display_clock_sys_pll },
960 { .tableFunction = cz_tf_clear_nb_dpm_flag },
961 { .tableFunction = cz_tf_reset_cc6_data },
965 static const struct phm_master_table_header cz_power_down_asic_master = {
967 PHM_MasterTableFlag_None,
968 cz_power_down_asic_list
971 static int cz_tf_program_voting_clients(struct pp_hwmgr *hwmgr, void *input,
972 void *output, void *storage, int result)
974 PHMCZ_WRITE_SMC_REGISTER(hwmgr->device, CG_FREQ_TRAN_VOTING_0,
975 PPCZ_VOTINGRIGHTSCLIENTS_DFLT0);
979 static int cz_tf_start_dpm(struct pp_hwmgr *hwmgr, void *input, void *output,
980 void *storage, int result)
983 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
984 unsigned long dpm_features = 0;
986 cz_hwmgr->dpm_flags |= DPMFlags_SCLK_Enabled;
987 dpm_features |= SCLK_DPM_MASK;
989 res = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
990 PPSMC_MSG_EnableAllSmuFeatures,
996 static int cz_tf_program_bootup_state(struct pp_hwmgr *hwmgr, void *input,
997 void *output, void *storage, int result)
999 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1001 cz_hwmgr->sclk_dpm.soft_min_clk = cz_hwmgr->sys_info.bootup_engine_clock;
1002 cz_hwmgr->sclk_dpm.soft_max_clk = cz_hwmgr->sys_info.bootup_engine_clock;
1004 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1005 PPSMC_MSG_SetSclkSoftMin,
1006 cz_get_sclk_level(hwmgr,
1007 cz_hwmgr->sclk_dpm.soft_min_clk,
1008 PPSMC_MSG_SetSclkSoftMin));
1010 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1011 PPSMC_MSG_SetSclkSoftMax,
1012 cz_get_sclk_level(hwmgr,
1013 cz_hwmgr->sclk_dpm.soft_max_clk,
1014 PPSMC_MSG_SetSclkSoftMax));
1019 static int cz_tf_reset_acp_boot_level(struct pp_hwmgr *hwmgr, void *input,
1020 void *output, void *storage, int result)
1022 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1024 cz_hwmgr->acp_boot_level = 0xff;
1028 static bool cz_dpm_check_smu_features(struct pp_hwmgr *hwmgr,
1029 unsigned long check_feature)
1032 unsigned long features;
1034 result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_GetFeatureStatus, 0);
1036 features = smum_get_argument(hwmgr->smumgr);
1037 if (features & check_feature)
1044 static int cz_tf_check_for_dpm_disabled(struct pp_hwmgr *hwmgr, void *input,
1045 void *output, void *storage, int result)
1047 if (cz_dpm_check_smu_features(hwmgr, SMU_EnabledFeatureScoreboard_SclkDpmOn))
1048 return PP_Result_TableImmediateExit;
1052 static int cz_tf_enable_didt(struct pp_hwmgr *hwmgr, void *input,
1053 void *output, void *storage, int result)
1059 static int cz_tf_check_for_dpm_enabled(struct pp_hwmgr *hwmgr,
1060 void *input, void *output,
1061 void *storage, int result)
1063 if (!cz_dpm_check_smu_features(hwmgr,
1064 SMU_EnabledFeatureScoreboard_SclkDpmOn))
1065 return PP_Result_TableImmediateExit;
1069 static const struct phm_master_table_item cz_disable_dpm_list[] = {
1070 { .tableFunction = cz_tf_check_for_dpm_enabled },
1075 static const struct phm_master_table_header cz_disable_dpm_master = {
1077 PHM_MasterTableFlag_None,
1081 static const struct phm_master_table_item cz_enable_dpm_list[] = {
1082 { .tableFunction = cz_tf_check_for_dpm_disabled },
1083 { .tableFunction = cz_tf_program_voting_clients },
1084 { .tableFunction = cz_tf_start_dpm },
1085 { .tableFunction = cz_tf_program_bootup_state },
1086 { .tableFunction = cz_tf_enable_didt },
1087 { .tableFunction = cz_tf_reset_acp_boot_level },
1091 static const struct phm_master_table_header cz_enable_dpm_master = {
1093 PHM_MasterTableFlag_None,
1097 static int cz_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
1098 struct pp_power_state *prequest_ps,
1099 const struct pp_power_state *pcurrent_ps)
1101 struct cz_power_state *cz_ps =
1102 cast_PhwCzPowerState(&prequest_ps->hardware);
1104 const struct cz_power_state *cz_current_ps =
1105 cast_const_PhwCzPowerState(&pcurrent_ps->hardware);
1107 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1108 struct PP_Clocks clocks = {0, 0, 0, 0};
1110 uint32_t num_of_active_displays = 0;
1111 struct cgs_display_info info = {0};
1113 cz_ps->evclk = hwmgr->vce_arbiter.evclk;
1114 cz_ps->ecclk = hwmgr->vce_arbiter.ecclk;
1116 cz_ps->need_dfs_bypass = true;
1118 cz_hwmgr->video_start = (hwmgr->uvd_arbiter.vclk != 0 || hwmgr->uvd_arbiter.dclk != 0 ||
1119 hwmgr->vce_arbiter.evclk != 0 || hwmgr->vce_arbiter.ecclk != 0);
1121 cz_hwmgr->battery_state = (PP_StateUILabel_Battery == prequest_ps->classification.ui_label);
1123 clocks.memoryClock = hwmgr->display_config.min_mem_set_clock != 0 ?
1124 hwmgr->display_config.min_mem_set_clock :
1125 cz_hwmgr->sys_info.nbp_memory_clock[1];
1127 cgs_get_active_displays_info(hwmgr->device, &info);
1128 num_of_active_displays = info.display_count;
1130 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState))
1131 clocks.memoryClock = hwmgr->dyn_state.max_clock_voltage_on_ac.mclk;
1133 if (clocks.memoryClock < hwmgr->gfx_arbiter.mclk)
1134 clocks.memoryClock = hwmgr->gfx_arbiter.mclk;
1136 force_high = (clocks.memoryClock > cz_hwmgr->sys_info.nbp_memory_clock[CZ_NUM_NBPMEMORYCLOCK - 1])
1137 || (num_of_active_displays >= 3);
1139 cz_ps->action = cz_current_ps->action;
1141 if (!force_high && (cz_ps->action == FORCE_HIGH))
1142 cz_ps->action = CANCEL_FORCE_HIGH;
1143 else if (force_high && (cz_ps->action != FORCE_HIGH))
1144 cz_ps->action = FORCE_HIGH;
1146 cz_ps->action = DO_NOTHING;
1151 static int cz_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
1154 struct cz_hwmgr *data;
1156 data = kzalloc(sizeof(struct cz_hwmgr), GFP_KERNEL);
1160 hwmgr->backend = data;
1162 result = cz_initialize_dpm_defaults(hwmgr);
1164 printk(KERN_ERR "[ powerplay ] cz_initialize_dpm_defaults failed\n");
1168 result = cz_get_system_info_data(hwmgr);
1170 printk(KERN_ERR "[ powerplay ] cz_get_system_info_data failed\n");
1174 cz_construct_boot_state(hwmgr);
1176 result = phm_construct_table(hwmgr, &cz_setup_asic_master,
1177 &(hwmgr->setup_asic));
1179 printk(KERN_ERR "[ powerplay ] Fail to construct setup ASIC\n");
1183 result = phm_construct_table(hwmgr, &cz_power_down_asic_master,
1184 &(hwmgr->power_down_asic));
1186 printk(KERN_ERR "[ powerplay ] Fail to construct power down ASIC\n");
1190 result = phm_construct_table(hwmgr, &cz_disable_dpm_master,
1191 &(hwmgr->disable_dynamic_state_management));
1193 printk(KERN_ERR "[ powerplay ] Fail to disable_dynamic_state\n");
1196 result = phm_construct_table(hwmgr, &cz_enable_dpm_master,
1197 &(hwmgr->enable_dynamic_state_management));
1199 printk(KERN_ERR "[ powerplay ] Fail to enable_dynamic_state\n");
1202 result = phm_construct_table(hwmgr, &cz_set_power_state_master,
1203 &(hwmgr->set_power_state));
1205 printk(KERN_ERR "[ powerplay ] Fail to construct set_power_state\n");
1208 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels = CZ_MAX_HARDWARE_POWERLEVELS;
1210 result = phm_construct_table(hwmgr, &cz_phm_enable_clock_power_gatings_master, &(hwmgr->enable_clock_power_gatings));
1212 printk(KERN_ERR "[ powerplay ] Fail to construct enable_clock_power_gatings\n");
1218 static int cz_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
1220 if (hwmgr != NULL && hwmgr->backend != NULL) {
1221 kfree(hwmgr->backend);
1227 static int cz_phm_force_dpm_highest(struct pp_hwmgr *hwmgr)
1229 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1231 if (cz_hwmgr->sclk_dpm.soft_min_clk !=
1232 cz_hwmgr->sclk_dpm.soft_max_clk)
1233 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1234 PPSMC_MSG_SetSclkSoftMin,
1235 cz_get_sclk_level(hwmgr,
1236 cz_hwmgr->sclk_dpm.soft_max_clk,
1237 PPSMC_MSG_SetSclkSoftMin));
1241 static int cz_phm_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
1243 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1244 struct phm_clock_voltage_dependency_table *table =
1245 hwmgr->dyn_state.vddc_dependency_on_sclk;
1246 unsigned long clock = 0, level;
1248 if (NULL == table || table->count <= 0)
1251 cz_hwmgr->sclk_dpm.soft_min_clk = table->entries[0].clk;
1252 cz_hwmgr->sclk_dpm.hard_min_clk = table->entries[0].clk;
1254 level = cz_get_max_sclk_level(hwmgr) - 1;
1256 if (level < table->count)
1257 clock = table->entries[level].clk;
1259 clock = table->entries[table->count - 1].clk;
1261 cz_hwmgr->sclk_dpm.soft_max_clk = clock;
1262 cz_hwmgr->sclk_dpm.hard_max_clk = clock;
1264 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1265 PPSMC_MSG_SetSclkSoftMin,
1266 cz_get_sclk_level(hwmgr,
1267 cz_hwmgr->sclk_dpm.soft_min_clk,
1268 PPSMC_MSG_SetSclkSoftMin));
1270 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1271 PPSMC_MSG_SetSclkSoftMax,
1272 cz_get_sclk_level(hwmgr,
1273 cz_hwmgr->sclk_dpm.soft_max_clk,
1274 PPSMC_MSG_SetSclkSoftMax));
1279 static int cz_phm_force_dpm_lowest(struct pp_hwmgr *hwmgr)
1281 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1283 if (cz_hwmgr->sclk_dpm.soft_min_clk !=
1284 cz_hwmgr->sclk_dpm.soft_max_clk) {
1285 cz_hwmgr->sclk_dpm.soft_max_clk =
1286 cz_hwmgr->sclk_dpm.soft_min_clk;
1288 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1289 PPSMC_MSG_SetSclkSoftMax,
1290 cz_get_sclk_level(hwmgr,
1291 cz_hwmgr->sclk_dpm.soft_max_clk,
1292 PPSMC_MSG_SetSclkSoftMax));
1298 static int cz_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
1299 enum amd_dpm_forced_level level)
1304 case AMD_DPM_FORCED_LEVEL_HIGH:
1305 ret = cz_phm_force_dpm_highest(hwmgr);
1309 case AMD_DPM_FORCED_LEVEL_LOW:
1310 ret = cz_phm_force_dpm_lowest(hwmgr);
1314 case AMD_DPM_FORCED_LEVEL_AUTO:
1315 ret = cz_phm_unforce_dpm_levels(hwmgr);
1323 hwmgr->dpm_level = level;
1328 int cz_dpm_powerdown_uvd(struct pp_hwmgr *hwmgr)
1330 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1331 PHM_PlatformCaps_UVDPowerGating))
1332 return smum_send_msg_to_smc(hwmgr->smumgr,
1333 PPSMC_MSG_UVDPowerOFF);
1337 int cz_dpm_powerup_uvd(struct pp_hwmgr *hwmgr)
1339 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1340 PHM_PlatformCaps_UVDPowerGating)) {
1341 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1342 PHM_PlatformCaps_UVDDynamicPowerGating)) {
1343 return smum_send_msg_to_smc_with_parameter(
1345 PPSMC_MSG_UVDPowerON, 1);
1347 return smum_send_msg_to_smc_with_parameter(
1349 PPSMC_MSG_UVDPowerON, 0);
1356 int cz_dpm_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate)
1358 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1359 struct phm_uvd_clock_voltage_dependency_table *ptable =
1360 hwmgr->dyn_state.uvd_clock_voltage_dependency_table;
1363 /* Stable Pstate is enabled and we need to set the UVD DPM to highest level */
1364 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1365 PHM_PlatformCaps_StablePState)) {
1366 cz_hwmgr->uvd_dpm.hard_min_clk =
1367 ptable->entries[ptable->count - 1].vclk;
1369 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1370 PPSMC_MSG_SetUvdHardMin,
1371 cz_get_uvd_level(hwmgr,
1372 cz_hwmgr->uvd_dpm.hard_min_clk,
1373 PPSMC_MSG_SetUvdHardMin));
1375 cz_enable_disable_uvd_dpm(hwmgr, true);
1377 cz_enable_disable_uvd_dpm(hwmgr, true);
1380 cz_enable_disable_uvd_dpm(hwmgr, false);
1386 int cz_dpm_update_vce_dpm(struct pp_hwmgr *hwmgr)
1388 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1389 struct phm_vce_clock_voltage_dependency_table *ptable =
1390 hwmgr->dyn_state.vce_clock_voltage_dependency_table;
1392 /* Stable Pstate is enabled and we need to set the VCE DPM to highest level */
1393 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1394 PHM_PlatformCaps_StablePState)) {
1395 cz_hwmgr->vce_dpm.hard_min_clk =
1396 ptable->entries[ptable->count - 1].ecclk;
1398 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1399 PPSMC_MSG_SetEclkHardMin,
1400 cz_get_eclk_level(hwmgr,
1401 cz_hwmgr->vce_dpm.hard_min_clk,
1402 PPSMC_MSG_SetEclkHardMin));
1404 /*Program HardMin based on the vce_arbiter.ecclk */
1405 if (hwmgr->vce_arbiter.ecclk == 0) {
1406 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1407 PPSMC_MSG_SetEclkHardMin, 0);
1408 /* disable ECLK DPM 0. Otherwise VCE could hang if
1409 * switching SCLK from DPM 0 to 6/7 */
1410 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1411 PPSMC_MSG_SetEclkSoftMin, 1);
1413 cz_hwmgr->vce_dpm.hard_min_clk = hwmgr->vce_arbiter.ecclk;
1414 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1415 PPSMC_MSG_SetEclkHardMin,
1416 cz_get_eclk_level(hwmgr,
1417 cz_hwmgr->vce_dpm.hard_min_clk,
1418 PPSMC_MSG_SetEclkHardMin));
1424 int cz_dpm_powerdown_vce(struct pp_hwmgr *hwmgr)
1426 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1427 PHM_PlatformCaps_VCEPowerGating))
1428 return smum_send_msg_to_smc(hwmgr->smumgr,
1429 PPSMC_MSG_VCEPowerOFF);
1433 int cz_dpm_powerup_vce(struct pp_hwmgr *hwmgr)
1435 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1436 PHM_PlatformCaps_VCEPowerGating))
1437 return smum_send_msg_to_smc(hwmgr->smumgr,
1438 PPSMC_MSG_VCEPowerON);
1442 static int cz_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
1444 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1446 return cz_hwmgr->sys_info.bootup_uma_clock;
1449 static int cz_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
1451 struct pp_power_state *ps;
1452 struct cz_power_state *cz_ps;
1457 ps = hwmgr->request_ps;
1462 cz_ps = cast_PhwCzPowerState(&ps->hardware);
1465 return cz_ps->levels[0].engineClock;
1467 return cz_ps->levels[cz_ps->level-1].engineClock;
1470 static int cz_dpm_patch_boot_state(struct pp_hwmgr *hwmgr,
1471 struct pp_hw_power_state *hw_ps)
1473 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1474 struct cz_power_state *cz_ps = cast_PhwCzPowerState(hw_ps);
1477 cz_ps->nbps_flags = 0;
1478 cz_ps->bapm_flags = 0;
1479 cz_ps->levels[0] = cz_hwmgr->boot_power_level;
1484 static int cz_dpm_get_pp_table_entry_callback(
1485 struct pp_hwmgr *hwmgr,
1486 struct pp_hw_power_state *hw_ps,
1488 const void *clock_info)
1490 struct cz_power_state *cz_ps = cast_PhwCzPowerState(hw_ps);
1492 const ATOM_PPLIB_CZ_CLOCK_INFO *cz_clock_info = clock_info;
1494 struct phm_clock_voltage_dependency_table *table =
1495 hwmgr->dyn_state.vddc_dependency_on_sclk;
1496 uint8_t clock_info_index = cz_clock_info->index;
1498 if (clock_info_index > (uint8_t)(hwmgr->platform_descriptor.hardwareActivityPerformanceLevels - 1))
1499 clock_info_index = (uint8_t)(hwmgr->platform_descriptor.hardwareActivityPerformanceLevels - 1);
1501 cz_ps->levels[index].engineClock = table->entries[clock_info_index].clk;
1502 cz_ps->levels[index].vddcIndex = (uint8_t)table->entries[clock_info_index].v;
1504 cz_ps->level = index + 1;
1506 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
1507 cz_ps->levels[index].dsDividerIndex = 5;
1508 cz_ps->levels[index].ssDividerIndex = 5;
1514 static int cz_dpm_get_num_of_pp_table_entries(struct pp_hwmgr *hwmgr)
1517 unsigned long ret = 0;
1519 result = pp_tables_get_num_of_entries(hwmgr, &ret);
1521 return result ? 0 : ret;
1524 static int cz_dpm_get_pp_table_entry(struct pp_hwmgr *hwmgr,
1525 unsigned long entry, struct pp_power_state *ps)
1528 struct cz_power_state *cz_ps;
1530 ps->hardware.magic = PhwCz_Magic;
1532 cz_ps = cast_PhwCzPowerState(&(ps->hardware));
1534 result = pp_tables_get_entry(hwmgr, entry, ps,
1535 cz_dpm_get_pp_table_entry_callback);
1537 cz_ps->uvd_clocks.vclk = ps->uvd_clocks.VCLK;
1538 cz_ps->uvd_clocks.dclk = ps->uvd_clocks.DCLK;
1543 static int cz_get_power_state_size(struct pp_hwmgr *hwmgr)
1545 return sizeof(struct cz_power_state);
1548 static void cz_hw_print_display_cfg(
1549 const struct cc6_settings *cc6_settings)
1551 PP_DBG_LOG("New Display Configuration:\n");
1553 PP_DBG_LOG(" cpu_cc6_disable: %d\n",
1554 cc6_settings->cpu_cc6_disable);
1555 PP_DBG_LOG(" cpu_pstate_disable: %d\n",
1556 cc6_settings->cpu_pstate_disable);
1557 PP_DBG_LOG(" nb_pstate_switch_disable: %d\n",
1558 cc6_settings->nb_pstate_switch_disable);
1559 PP_DBG_LOG(" cpu_pstate_separation_time: %d\n\n",
1560 cc6_settings->cpu_pstate_separation_time);
1563 static int cz_set_cpu_power_state(struct pp_hwmgr *hwmgr)
1565 struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
1568 if (hw_data->cc6_settings.cc6_setting_changed) {
1570 hw_data->cc6_settings.cc6_setting_changed = false;
1572 cz_hw_print_display_cfg(&hw_data->cc6_settings);
1574 data |= (hw_data->cc6_settings.cpu_pstate_separation_time
1575 & PWRMGT_SEPARATION_TIME_MASK)
1576 << PWRMGT_SEPARATION_TIME_SHIFT;
1578 data |= (hw_data->cc6_settings.cpu_cc6_disable ? 0x1 : 0x0)
1579 << PWRMGT_DISABLE_CPU_CSTATES_SHIFT;
1581 data |= (hw_data->cc6_settings.cpu_pstate_disable ? 0x1 : 0x0)
1582 << PWRMGT_DISABLE_CPU_PSTATES_SHIFT;
1584 PP_DBG_LOG("SetDisplaySizePowerParams data: 0x%X\n",
1587 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1588 PPSMC_MSG_SetDisplaySizePowerParams,
1596 static int cz_store_cc6_data(struct pp_hwmgr *hwmgr, uint32_t separation_time,
1597 bool cc6_disable, bool pstate_disable, bool pstate_switch_disable)
1599 struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
1601 if (separation_time !=
1602 hw_data->cc6_settings.cpu_pstate_separation_time ||
1603 cc6_disable != hw_data->cc6_settings.cpu_cc6_disable ||
1604 pstate_disable != hw_data->cc6_settings.cpu_pstate_disable ||
1605 pstate_switch_disable != hw_data->cc6_settings.nb_pstate_switch_disable) {
1607 hw_data->cc6_settings.cc6_setting_changed = true;
1609 hw_data->cc6_settings.cpu_pstate_separation_time =
1611 hw_data->cc6_settings.cpu_cc6_disable =
1613 hw_data->cc6_settings.cpu_pstate_disable =
1615 hw_data->cc6_settings.nb_pstate_switch_disable =
1616 pstate_switch_disable;
1623 static int cz_get_dal_power_level(struct pp_hwmgr *hwmgr,
1624 struct amd_pp_simple_clock_info *info)
1627 const struct phm_clock_voltage_dependency_table *table =
1628 hwmgr->dyn_state.vddc_dep_on_dal_pwrl;
1629 const struct phm_clock_and_voltage_limits *limits =
1630 &hwmgr->dyn_state.max_clock_voltage_on_ac;
1632 info->engine_max_clock = limits->sclk;
1633 info->memory_max_clock = limits->mclk;
1635 for (i = table->count - 1; i > 0; i--) {
1636 if (limits->vddc >= table->entries[i].v) {
1637 info->level = table->entries[i].clk;
1644 static int cz_force_clock_level(struct pp_hwmgr *hwmgr,
1645 enum pp_clock_type type, uint32_t mask)
1647 if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
1652 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1653 PPSMC_MSG_SetSclkSoftMin,
1655 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1656 PPSMC_MSG_SetSclkSoftMax,
1666 static int cz_print_clock_levels(struct pp_hwmgr *hwmgr,
1667 enum pp_clock_type type, char *buf)
1669 struct phm_clock_voltage_dependency_table *sclk_table =
1670 hwmgr->dyn_state.vddc_dependency_on_sclk;
1671 int i, now, size = 0;
1675 now = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device,
1677 ixTARGET_AND_CURRENT_PROFILE_INDEX),
1678 TARGET_AND_CURRENT_PROFILE_INDEX,
1681 for (i = 0; i < sclk_table->count; i++)
1682 size += sprintf(buf + size, "%d: %uMhz %s\n",
1683 i, sclk_table->entries[i].clk / 100,
1684 (i == now) ? "*" : "");
1692 static int cz_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
1693 PHM_PerformanceLevelDesignation designation, uint32_t index,
1694 PHM_PerformanceLevel *level)
1696 const struct cz_power_state *ps;
1697 struct cz_hwmgr *data;
1698 uint32_t level_index;
1701 if (level == NULL || hwmgr == NULL || state == NULL)
1704 data = (struct cz_hwmgr *)(hwmgr->backend);
1705 ps = cast_const_PhwCzPowerState(state);
1707 level_index = index > ps->level - 1 ? ps->level - 1 : index;
1708 level->coreClock = ps->levels[level_index].engineClock;
1710 if (designation == PHM_PerformanceLevelDesignation_PowerContainment) {
1711 for (i = 1; i < ps->level; i++) {
1712 if (ps->levels[i].engineClock > data->dce_slow_sclk_threshold) {
1713 level->coreClock = ps->levels[i].engineClock;
1719 if (level_index == 0)
1720 level->memory_clock = data->sys_info.nbp_memory_clock[CZ_NUM_NBPMEMORYCLOCK - 1];
1722 level->memory_clock = data->sys_info.nbp_memory_clock[0];
1724 level->vddc = (cz_convert_8Bit_index_to_voltage(hwmgr, ps->levels[level_index].vddcIndex) + 2) / 4;
1725 level->nonLocalMemoryFreq = 0;
1726 level->nonLocalMemoryWidth = 0;
1731 static int cz_get_current_shallow_sleep_clocks(struct pp_hwmgr *hwmgr,
1732 const struct pp_hw_power_state *state, struct pp_clock_info *clock_info)
1734 const struct cz_power_state *ps = cast_const_PhwCzPowerState(state);
1736 clock_info->min_eng_clk = ps->levels[0].engineClock / (1 << (ps->levels[0].ssDividerIndex));
1737 clock_info->max_eng_clk = ps->levels[ps->level - 1].engineClock / (1 << (ps->levels[ps->level - 1].ssDividerIndex));
1742 static int cz_get_clock_by_type(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type,
1743 struct amd_pp_clocks *clocks)
1745 struct cz_hwmgr *data = (struct cz_hwmgr *)(hwmgr->backend);
1747 struct phm_clock_voltage_dependency_table *table;
1749 clocks->count = cz_get_max_sclk_level(hwmgr);
1751 case amd_pp_disp_clock:
1752 for (i = 0; i < clocks->count; i++)
1753 clocks->clock[i] = data->sys_info.display_clock[i];
1755 case amd_pp_sys_clock:
1756 table = hwmgr->dyn_state.vddc_dependency_on_sclk;
1757 for (i = 0; i < clocks->count; i++)
1758 clocks->clock[i] = table->entries[i].clk;
1760 case amd_pp_mem_clock:
1761 clocks->count = CZ_NUM_NBPMEMORYCLOCK;
1762 for (i = 0; i < clocks->count; i++)
1763 clocks->clock[i] = data->sys_info.nbp_memory_clock[clocks->count - 1 - i];
1772 static int cz_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks)
1774 struct phm_clock_voltage_dependency_table *table =
1775 hwmgr->dyn_state.vddc_dependency_on_sclk;
1776 unsigned long level;
1777 const struct phm_clock_and_voltage_limits *limits =
1778 &hwmgr->dyn_state.max_clock_voltage_on_ac;
1780 if ((NULL == table) || (table->count <= 0) || (clocks == NULL))
1783 level = cz_get_max_sclk_level(hwmgr) - 1;
1785 if (level < table->count)
1786 clocks->engine_max_clock = table->entries[level].clk;
1788 clocks->engine_max_clock = table->entries[table->count - 1].clk;
1790 clocks->memory_max_clock = limits->mclk;
1795 static int cz_thermal_get_temperature(struct pp_hwmgr *hwmgr)
1797 int actual_temp = 0;
1798 uint32_t val = cgs_read_ind_register(hwmgr->device,
1799 CGS_IND_REG__SMC, ixTHM_TCON_CUR_TMP);
1800 uint32_t temp = PHM_GET_FIELD(val, THM_TCON_CUR_TMP, CUR_TEMP);
1802 if (PHM_GET_FIELD(val, THM_TCON_CUR_TMP, CUR_TEMP_RANGE_SEL))
1803 actual_temp = ((temp / 8) - 49) * PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1805 actual_temp = (temp / 8) * PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1810 static int cz_read_sensor(struct pp_hwmgr *hwmgr, int idx, int32_t *value)
1812 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1814 struct phm_clock_voltage_dependency_table *table =
1815 hwmgr->dyn_state.vddc_dependency_on_sclk;
1817 struct phm_vce_clock_voltage_dependency_table *vce_table =
1818 hwmgr->dyn_state.vce_clock_voltage_dependency_table;
1820 struct phm_uvd_clock_voltage_dependency_table *uvd_table =
1821 hwmgr->dyn_state.uvd_clock_voltage_dependency_table;
1823 uint32_t sclk_index = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixTARGET_AND_CURRENT_PROFILE_INDEX),
1824 TARGET_AND_CURRENT_PROFILE_INDEX, CURR_SCLK_INDEX);
1825 uint32_t uvd_index = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixTARGET_AND_CURRENT_PROFILE_INDEX_2),
1826 TARGET_AND_CURRENT_PROFILE_INDEX_2, CURR_UVD_INDEX);
1827 uint32_t vce_index = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixTARGET_AND_CURRENT_PROFILE_INDEX_2),
1828 TARGET_AND_CURRENT_PROFILE_INDEX_2, CURR_VCE_INDEX);
1830 uint32_t sclk, vclk, dclk, ecclk, tmp, activity_percent;
1831 uint16_t vddnb, vddgfx;
1835 case AMDGPU_PP_SENSOR_GFX_SCLK:
1836 if (sclk_index < NUM_SCLK_LEVELS) {
1837 sclk = table->entries[sclk_index].clk;
1842 case AMDGPU_PP_SENSOR_VDDNB:
1843 tmp = (cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMUSVI_NB_CURRENTVID) &
1844 CURRENT_NB_VID_MASK) >> CURRENT_NB_VID__SHIFT;
1845 vddnb = cz_convert_8Bit_index_to_voltage(hwmgr, tmp);
1848 case AMDGPU_PP_SENSOR_VDDGFX:
1849 tmp = (cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMUSVI_GFX_CURRENTVID) &
1850 CURRENT_GFX_VID_MASK) >> CURRENT_GFX_VID__SHIFT;
1851 vddgfx = cz_convert_8Bit_index_to_voltage(hwmgr, (u16)tmp);
1854 case AMDGPU_PP_SENSOR_UVD_VCLK:
1855 if (!cz_hwmgr->uvd_power_gated) {
1856 if (uvd_index >= CZ_MAX_HARDWARE_POWERLEVELS) {
1859 vclk = uvd_table->entries[uvd_index].vclk;
1866 case AMDGPU_PP_SENSOR_UVD_DCLK:
1867 if (!cz_hwmgr->uvd_power_gated) {
1868 if (uvd_index >= CZ_MAX_HARDWARE_POWERLEVELS) {
1871 dclk = uvd_table->entries[uvd_index].dclk;
1878 case AMDGPU_PP_SENSOR_VCE_ECCLK:
1879 if (!cz_hwmgr->vce_power_gated) {
1880 if (vce_index >= CZ_MAX_HARDWARE_POWERLEVELS) {
1883 ecclk = vce_table->entries[vce_index].ecclk;
1890 case AMDGPU_PP_SENSOR_GPU_LOAD:
1891 result = smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetAverageGraphicsActivity);
1893 activity_percent = cgs_read_register(hwmgr->device, mmSMU_MP1_SRBM2P_ARG_0);
1894 activity_percent = activity_percent > 100 ? 100 : activity_percent;
1896 activity_percent = 50;
1898 *value = activity_percent;
1900 case AMDGPU_PP_SENSOR_UVD_POWER:
1901 *value = cz_hwmgr->uvd_power_gated ? 0 : 1;
1903 case AMDGPU_PP_SENSOR_VCE_POWER:
1904 *value = cz_hwmgr->vce_power_gated ? 0 : 1;
1906 case AMDGPU_PP_SENSOR_GPU_TEMP:
1907 *value = cz_thermal_get_temperature(hwmgr);
1914 static const struct pp_hwmgr_func cz_hwmgr_funcs = {
1915 .backend_init = cz_hwmgr_backend_init,
1916 .backend_fini = cz_hwmgr_backend_fini,
1918 .apply_state_adjust_rules = cz_apply_state_adjust_rules,
1919 .force_dpm_level = cz_dpm_force_dpm_level,
1920 .get_power_state_size = cz_get_power_state_size,
1921 .powerdown_uvd = cz_dpm_powerdown_uvd,
1922 .powergate_uvd = cz_dpm_powergate_uvd,
1923 .powergate_vce = cz_dpm_powergate_vce,
1924 .get_mclk = cz_dpm_get_mclk,
1925 .get_sclk = cz_dpm_get_sclk,
1926 .patch_boot_state = cz_dpm_patch_boot_state,
1927 .get_pp_table_entry = cz_dpm_get_pp_table_entry,
1928 .get_num_of_pp_table_entries = cz_dpm_get_num_of_pp_table_entries,
1929 .set_cpu_power_state = cz_set_cpu_power_state,
1930 .store_cc6_data = cz_store_cc6_data,
1931 .force_clock_level = cz_force_clock_level,
1932 .print_clock_levels = cz_print_clock_levels,
1933 .get_dal_power_level = cz_get_dal_power_level,
1934 .get_performance_level = cz_get_performance_level,
1935 .get_current_shallow_sleep_clocks = cz_get_current_shallow_sleep_clocks,
1936 .get_clock_by_type = cz_get_clock_by_type,
1937 .get_max_high_clocks = cz_get_max_high_clocks,
1938 .read_sensor = cz_read_sensor,
1941 int cz_hwmgr_init(struct pp_hwmgr *hwmgr)
1943 hwmgr->hwmgr_func = &cz_hwmgr_funcs;
1944 hwmgr->pptable_func = &pptable_funcs;