drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/module.h>
  24 #include <linux/slab.h>
  25 #include <linux/fb.h>
  26 #include <asm/div64.h>
  27 #include "linux/delay.h"
  28 #include "pp_acpi.h"
  29 #include "hwmgr.h"
  30 #include "polaris10_hwmgr.h"
  31 #include "polaris10_powertune.h"
  32 #include "polaris10_dyn_defaults.h"
  33 #include "polaris10_smumgr.h"
  34 #include "pp_debug.h"
  35 #include "ppatomctrl.h"
  36 #include "atombios.h"
  37 #include "tonga_pptable.h"
  38 #include "pppcielanes.h"
  39 #include "amd_pcie_helpers.h"
  40 #include "hardwaremanager.h"
  41 #include "tonga_processpptables.h"
  42 #include "cgs_common.h"
  43 #include "smu74.h"
  44 #include "smu_ucode_xfer_vi.h"
  45 #include "smu74_discrete.h"
  46 #include "smu/smu_7_1_3_d.h"
  47 #include "smu/smu_7_1_3_sh_mask.h"
  48 #include "gmc/gmc_8_1_d.h"
  49 #include "gmc/gmc_8_1_sh_mask.h"
  50 #include "oss/oss_3_0_d.h"
  51 #include "gca/gfx_8_0_d.h"
  52 #include "bif/bif_5_0_d.h"
  53 #include "bif/bif_5_0_sh_mask.h"
  54 #include "gmc/gmc_8_1_d.h"
  55 #include "gmc/gmc_8_1_sh_mask.h"
  56 #include "bif/bif_5_0_d.h"
  57 #include "bif/bif_5_0_sh_mask.h"
  58 #include "dce/dce_10_0_d.h"
  59 #include "dce/dce_10_0_sh_mask.h"
  60
  61 #include "polaris10_thermal.h"
  62 #include "polaris10_clockpowergating.h"
  63
  64 #define MC_CG_ARB_FREQ_F0           0x0a
  65 #define MC_CG_ARB_FREQ_F1           0x0b
  66 #define MC_CG_ARB_FREQ_F2           0x0c
  67 #define MC_CG_ARB_FREQ_F3           0x0d
  68
  69 #define MC_CG_SEQ_DRAMCONF_S0       0x05
  70 #define MC_CG_SEQ_DRAMCONF_S1       0x06
  71 #define MC_CG_SEQ_YCLK_SUSPEND      0x04
  72 #define MC_CG_SEQ_YCLK_RESUME       0x0a
  73
  74
  75 #define SMC_RAM_END 0x40000
  76
  77 #define SMC_CG_IND_START            0xc0030000
  78 #define SMC_CG_IND_END              0xc0040000
  79
  80 #define VOLTAGE_SCALE               4
  81 #define VOLTAGE_VID_OFFSET_SCALE1   625
  82 #define VOLTAGE_VID_OFFSET_SCALE2   100
  83
  84 #define VDDC_VDDCI_DELTA            200
  85
  86 #define MEM_FREQ_LOW_LATENCY        25000
  87 #define MEM_FREQ_HIGH_LATENCY       80000
  88
  89 #define MEM_LATENCY_HIGH            45
  90 #define MEM_LATENCY_LOW             35
  91 #define MEM_LATENCY_ERR             0xFFFF
  92
  93 #define MC_SEQ_MISC0_GDDR5_SHIFT 28
  94 #define MC_SEQ_MISC0_GDDR5_MASK  0xf0000000
  95 #define MC_SEQ_MISC0_GDDR5_VALUE 5
  96
  97
  98 #define PCIE_BUS_CLK                10000
  99 #define TCLK                        (PCIE_BUS_CLK / 10)
 100
 101
 102 static const uint16_t polaris10_clock_stretcher_lookup_table[2][4] =
 103 { {600, 1050, 3, 0}, {600, 1050, 6, 1} };
 104
 105 /*  [FF, SS] type, [] 4 voltage ranges, and [Floor Freq, Boundary Freq, VID min , VID max] */
 106 static const uint32_t polaris10_clock_stretcher_ddt_table[2][4][4] =
 107 { { {265, 529, 120, 128}, {325, 650, 96, 119}, {430, 860, 32, 95}, {0, 0, 0, 31} },
 108   { {275, 550, 104, 112}, {319, 638, 96, 103}, {360, 720, 64, 95}, {384, 768, 32, 63} } };
 109
 110 /*  [Use_For_Low_freq] value, [0%, 5%, 10%, 7.14%, 14.28%, 20%] (coming from PWR_CKS_CNTL.stretch_amount reg spec) */
 111 static const uint8_t polaris10_clock_stretch_amount_conversion[2][6] =
 112 { {0, 1, 3, 2, 4, 5}, {0, 2, 4, 5, 6, 5} };
 113
 114 /** Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */
 115 enum DPM_EVENT_SRC {
 116         DPM_EVENT_SRC_ANALOG = 0,
 117         DPM_EVENT_SRC_EXTERNAL = 1,
 118         DPM_EVENT_SRC_DIGITAL = 2,
 119         DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
 120         DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL = 4
 121 };
 122
 123 static const unsigned long PhwPolaris10_Magic = (unsigned long)(PHM_VIslands_Magic);
 124
 125 struct polaris10_power_state *cast_phw_polaris10_power_state(
 126                                   struct pp_hw_power_state *hw_ps)
 127 {
 128         PP_ASSERT_WITH_CODE((PhwPolaris10_Magic == hw_ps->magic),
 129                                 "Invalid Powerstate Type!",
 130                                  return NULL);
 131
 132         return (struct polaris10_power_state *)hw_ps;
 133 }
 134
 135 const struct polaris10_power_state *cast_const_phw_polaris10_power_state(
 136                                  const struct pp_hw_power_state *hw_ps)
 137 {
 138         PP_ASSERT_WITH_CODE((PhwPolaris10_Magic == hw_ps->magic),
 139                                 "Invalid Powerstate Type!",
 140                                  return NULL);
 141
 142         return (const struct polaris10_power_state *)hw_ps;
 143 }
 144
 145 static bool polaris10_is_dpm_running(struct pp_hwmgr *hwmgr)
 146 {
 147         return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device,
 148                         CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON))
 149                         ? true : false;
 150 }
 151
 152 /**
 153  * Find the MC microcode version and store it in the HwMgr struct
 154  *
 155  * @param    hwmgr  the address of the powerplay hardware manager.
 156  * @return   always 0
 157  */
 158 int phm_get_mc_microcode_version (struct pp_hwmgr *hwmgr)
 159 {
 160         cgs_write_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_INDEX, 0x9F);
 161
 162         hwmgr->microcode_version_info.MC = cgs_read_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_DATA);
 163
 164         return 0;
 165 }
 166
 167 uint16_t phm_get_current_pcie_speed(struct pp_hwmgr *hwmgr)
 168 {
 169         uint32_t speedCntl = 0;
 170
 171         /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
 172         speedCntl = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__PCIE,
 173                         ixPCIE_LC_SPEED_CNTL);
 174         return((uint16_t)PHM_GET_FIELD(speedCntl,
 175                         PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE));
 176 }
 177
 178 int phm_get_current_pcie_lane_number(struct pp_hwmgr *hwmgr)
 179 {
 180         uint32_t link_width;
 181
 182         /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
 183         link_width = PHM_READ_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
 184                         PCIE_LC_LINK_WIDTH_CNTL, LC_LINK_WIDTH_RD);
 185
 186         PP_ASSERT_WITH_CODE((7 >= link_width),
 187                         "Invalid PCIe lane width!", return 0);
 188
 189         return decode_pcie_lane_width(link_width);
 190 }
 191
 192 /**
 193 * Enable voltage control
 194 *
 195 * @param    pHwMgr  the address of the powerplay hardware manager.
 196 * @return   always PP_Result_OK
 197 */
 198 int polaris10_enable_smc_voltage_controller(struct pp_hwmgr *hwmgr)
 199 {
 200         PP_ASSERT_WITH_CODE(
 201                 (hwmgr->smumgr->smumgr_funcs->send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_Voltage_Cntl_Enable) == 0),
 202                 "Failed to enable voltage DPM during DPM Start Function!",
 203                 return 1;
 204         );
 205
 206         return 0;
 207 }
 208
 209 /**
 210 * Checks if we want to support voltage control
 211 *
 212 * @param    hwmgr  the address of the powerplay hardware manager.
 213 */
 214 static bool polaris10_voltage_control(const struct pp_hwmgr *hwmgr)
 215 {
 216         const struct polaris10_hwmgr *data =
 217                         (const struct polaris10_hwmgr *)(hwmgr->backend);
 218
 219         return (POLARIS10_VOLTAGE_CONTROL_NONE != data->voltage_control);
 220 }
 221
 222 /**
 223 * Enable voltage control
 224 *
 225 * @param    hwmgr  the address of the powerplay hardware manager.
 226 * @return   always 0
 227 */
 228 static int polaris10_enable_voltage_control(struct pp_hwmgr *hwmgr)
 229 {
 230         /* enable voltage control */
 231         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 232                         GENERAL_PWRMGT, VOLT_PWRMGT_EN, 1);
 233
 234         return 0;
 235 }
 236
 237 /**
 238 * Create Voltage Tables.
 239 *
 240 * @param    hwmgr  the address of the powerplay hardware manager.
 241 * @return   always 0
 242 */
 243 static int polaris10_construct_voltage_tables(struct pp_hwmgr *hwmgr)
 244 {
 245         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 246         struct phm_ppt_v1_information *table_info =
 247                         (struct phm_ppt_v1_information *)hwmgr->pptable;
 248         int result;
 249
 250         if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
 251                 result = atomctrl_get_voltage_table_v3(hwmgr,
 252                                 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT,
 253                                 &(data->mvdd_voltage_table));
 254                 PP_ASSERT_WITH_CODE((0 == result),
 255                                 "Failed to retrieve MVDD table.",
 256                                 return result);
 257         } else if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
 258                 result = phm_get_svi2_mvdd_voltage_table(&(data->mvdd_voltage_table),
 259                                 table_info->vdd_dep_on_mclk);
 260                 PP_ASSERT_WITH_CODE((0 == result),
 261                                 "Failed to retrieve SVI2 MVDD table from dependancy table.",
 262                                 return result;);
 263         }
 264
 265         if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
 266                 result = atomctrl_get_voltage_table_v3(hwmgr,
 267                                 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT,
 268                                 &(data->vddci_voltage_table));
 269                 PP_ASSERT_WITH_CODE((0 == result),
 270                                 "Failed to retrieve VDDCI table.",
 271                                 return result);
 272         } else if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
 273                 result = phm_get_svi2_vddci_voltage_table(&(data->vddci_voltage_table),
 274                                 table_info->vdd_dep_on_mclk);
 275                 PP_ASSERT_WITH_CODE((0 == result),
 276                                 "Failed to retrieve SVI2 VDDCI table from dependancy table.",
 277                                 return result);
 278         }
 279
 280         if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
 281                 result = phm_get_svi2_vdd_voltage_table(&(data->vddc_voltage_table),
 282                                 table_info->vddc_lookup_table);
 283                 PP_ASSERT_WITH_CODE((0 == result),
 284                                 "Failed to retrieve SVI2 VDDC table from lookup table.",
 285                                 return result);
 286         }
 287
 288         PP_ASSERT_WITH_CODE(
 289                         (data->vddc_voltage_table.count <= (SMU74_MAX_LEVELS_VDDC)),
 290                         "Too many voltage values for VDDC. Trimming to fit state table.",
 291                         phm_trim_voltage_table_to_fit_state_table(SMU74_MAX_LEVELS_VDDC,
 292                                                                 &(data->vddc_voltage_table)));
 293
 294         PP_ASSERT_WITH_CODE(
 295                         (data->vddci_voltage_table.count <= (SMU74_MAX_LEVELS_VDDCI)),
 296                         "Too many voltage values for VDDCI. Trimming to fit state table.",
 297                         phm_trim_voltage_table_to_fit_state_table(SMU74_MAX_LEVELS_VDDCI,
 298                                         &(data->vddci_voltage_table)));
 299
 300         PP_ASSERT_WITH_CODE(
 301                         (data->mvdd_voltage_table.count <= (SMU74_MAX_LEVELS_MVDD)),
 302                         "Too many voltage values for MVDD. Trimming to fit state table.",
 303                         phm_trim_voltage_table_to_fit_state_table(SMU74_MAX_LEVELS_MVDD,
 304                                                            &(data->mvdd_voltage_table)));
 305
 306         return 0;
 307 }
 308
 309 /**
 310 * Programs static screed detection parameters
 311 *
 312 * @param    hwmgr  the address of the powerplay hardware manager.
 313 * @return   always 0
 314 */
 315 static int polaris10_program_static_screen_threshold_parameters(
 316                                                         struct pp_hwmgr *hwmgr)
 317 {
 318         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 319
 320         /* Set static screen threshold unit */
 321         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 322                         CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD_UNIT,
 323                         data->static_screen_threshold_unit);
 324         /* Set static screen threshold */
 325         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 326                         CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD,
 327                         data->static_screen_threshold);
 328
 329         return 0;
 330 }
 331
 332 /**
 333 * Setup display gap for glitch free memory clock switching.
 334 *
 335 * @param    hwmgr  the address of the powerplay hardware manager.
 336 * @return   always  0
 337 */
 338 static int polaris10_enable_display_gap(struct pp_hwmgr *hwmgr)
 339 {
 340         uint32_t display_gap =
 341                         cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 342                                         ixCG_DISPLAY_GAP_CNTL);
 343
 344         display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL,
 345                         DISP_GAP, DISPLAY_GAP_IGNORE);
 346
 347         display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL,
 348                         DISP_GAP_MCHG, DISPLAY_GAP_VBLANK);
 349
 350         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 351                         ixCG_DISPLAY_GAP_CNTL, display_gap);
 352
 353         return 0;
 354 }
 355
 356 /**
 357 * Programs activity state transition voting clients
 358 *
 359 * @param    hwmgr  the address of the powerplay hardware manager.
 360 * @return   always  0
 361 */
 362 static int polaris10_program_voting_clients(struct pp_hwmgr *hwmgr)
 363 {
 364         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 365
 366         /* Clear reset for voting clients before enabling DPM */
 367         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 368                         SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 0);
 369         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 370                         SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 0);
 371
 372         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 373                         ixCG_FREQ_TRAN_VOTING_0, data->voting_rights_clients0);
 374         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 375                         ixCG_FREQ_TRAN_VOTING_1, data->voting_rights_clients1);
 376         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 377                         ixCG_FREQ_TRAN_VOTING_2, data->voting_rights_clients2);
 378         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 379                         ixCG_FREQ_TRAN_VOTING_3, data->voting_rights_clients3);
 380         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 381                         ixCG_FREQ_TRAN_VOTING_4, data->voting_rights_clients4);
 382         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 383                         ixCG_FREQ_TRAN_VOTING_5, data->voting_rights_clients5);
 384         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 385                         ixCG_FREQ_TRAN_VOTING_6, data->voting_rights_clients6);
 386         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 387                         ixCG_FREQ_TRAN_VOTING_7, data->voting_rights_clients7);
 388
 389         return 0;
 390 }
 391
 392 /**
 393 * Get the location of various tables inside the FW image.
 394 *
 395 * @param    hwmgr  the address of the powerplay hardware manager.
 396 * @return   always  0
 397 */
 398 static int polaris10_process_firmware_header(struct pp_hwmgr *hwmgr)
 399 {
 400         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 401         struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend);
 402         uint32_t tmp;
 403         int result;
 404         bool error = false;
 405
 406         result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
 407                         SMU7_FIRMWARE_HEADER_LOCATION +
 408                         offsetof(SMU74_Firmware_Header, DpmTable),
 409                         &tmp, data->sram_end);
 410
 411         if (0 == result)
 412                 data->dpm_table_start = tmp;
 413
 414         error |= (0 != result);
 415
 416         result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
 417                         SMU7_FIRMWARE_HEADER_LOCATION +
 418                         offsetof(SMU74_Firmware_Header, SoftRegisters),
 419                         &tmp, data->sram_end);
 420
 421         if (!result) {
 422                 data->soft_regs_start = tmp;
 423                 smu_data->soft_regs_start = tmp;
 424         }
 425
 426         error |= (0 != result);
 427
 428         result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
 429                         SMU7_FIRMWARE_HEADER_LOCATION +
 430                         offsetof(SMU74_Firmware_Header, mcRegisterTable),
 431                         &tmp, data->sram_end);
 432
 433         if (!result)
 434                 data->mc_reg_table_start = tmp;
 435
 436         result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
 437                         SMU7_FIRMWARE_HEADER_LOCATION +
 438                         offsetof(SMU74_Firmware_Header, FanTable),
 439                         &tmp, data->sram_end);
 440
 441         if (!result)
 442                 data->fan_table_start = tmp;
 443
 444         error |= (0 != result);
 445
 446         result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
 447                         SMU7_FIRMWARE_HEADER_LOCATION +
 448                         offsetof(SMU74_Firmware_Header, mcArbDramTimingTable),
 449                         &tmp, data->sram_end);
 450
 451         if (!result)
 452                 data->arb_table_start = tmp;
 453
 454         error |= (0 != result);
 455
 456         result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
 457                         SMU7_FIRMWARE_HEADER_LOCATION +
 458                         offsetof(SMU74_Firmware_Header, Version),
 459                         &tmp, data->sram_end);
 460
 461         if (!result)
 462                 hwmgr->microcode_version_info.SMC = tmp;
 463
 464         error |= (0 != result);
 465
 466         return error ? -1 : 0;
 467 }
 468
 469 /* Copy one arb setting to another and then switch the active set.
 470  * arb_src and arb_dest is one of the MC_CG_ARB_FREQ_Fx constants.
 471  */
 472 static int polaris10_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr,
 473                 uint32_t arb_src, uint32_t arb_dest)
 474 {
 475         uint32_t mc_arb_dram_timing;
 476         uint32_t mc_arb_dram_timing2;
 477         uint32_t burst_time;
 478         uint32_t mc_cg_config;
 479
 480         switch (arb_src) {
 481         case MC_CG_ARB_FREQ_F0:
 482                 mc_arb_dram_timing  = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
 483                 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
 484                 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
 485                 break;
 486         case MC_CG_ARB_FREQ_F1:
 487                 mc_arb_dram_timing  = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1);
 488                 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1);
 489                 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1);
 490                 break;
 491         default:
 492                 return -EINVAL;
 493         }
 494
 495         switch (arb_dest) {
 496         case MC_CG_ARB_FREQ_F0:
 497                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING, mc_arb_dram_timing);
 498                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
 499                 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0, burst_time);
 500                 break;
 501         case MC_CG_ARB_FREQ_F1:
 502                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
 503                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
 504                 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1, burst_time);
 505                 break;
 506         default:
 507                 return -EINVAL;
 508         }
 509
 510         mc_cg_config = cgs_read_register(hwmgr->device, mmMC_CG_CONFIG);
 511         mc_cg_config |= 0x0000000F;
 512         cgs_write_register(hwmgr->device, mmMC_CG_CONFIG, mc_cg_config);
 513         PHM_WRITE_FIELD(hwmgr->device, MC_ARB_CG, CG_ARB_REQ, arb_dest);
 514
 515         return 0;
 516 }
 517
 518 /**
 519 * Initial switch from ARB F0->F1
 520 *
 521 * @param    hwmgr  the address of the powerplay hardware manager.
 522 * @return   always 0
 523 * This function is to be called from the SetPowerState table.
 524 */
 525 static int polaris10_initial_switch_from_arbf0_to_f1(struct pp_hwmgr *hwmgr)
 526 {
 527         return polaris10_copy_and_switch_arb_sets(hwmgr,
 528                         MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
 529 }
 530
 531 static int polaris10_setup_default_pcie_table(struct pp_hwmgr *hwmgr)
 532 {
 533         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 534         struct phm_ppt_v1_information *table_info =
 535                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 536         struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
 537         uint32_t i, max_entry;
 538
 539         PP_ASSERT_WITH_CODE((data->use_pcie_performance_levels ||
 540                         data->use_pcie_power_saving_levels), "No pcie performance levels!",
 541                         return -EINVAL);
 542
 543         if (data->use_pcie_performance_levels &&
 544                         !data->use_pcie_power_saving_levels) {
 545                 data->pcie_gen_power_saving = data->pcie_gen_performance;
 546                 data->pcie_lane_power_saving = data->pcie_lane_performance;
 547         } else if (!data->use_pcie_performance_levels &&
 548                         data->use_pcie_power_saving_levels) {
 549                 data->pcie_gen_performance = data->pcie_gen_power_saving;
 550                 data->pcie_lane_performance = data->pcie_lane_power_saving;
 551         }
 552
 553         phm_reset_single_dpm_table(&data->dpm_table.pcie_speed_table,
 554                                         SMU74_MAX_LEVELS_LINK,
 555                                         MAX_REGULAR_DPM_NUMBER);
 556
 557         if (pcie_table != NULL) {
 558                 /* max_entry is used to make sure we reserve one PCIE level
 559                  * for boot level (fix for A+A PSPP issue).
 560                  * If PCIE table from PPTable have ULV entry + 8 entries,
 561                  * then ignore the last entry.*/
 562                 max_entry = (SMU74_MAX_LEVELS_LINK < pcie_table->count) ?
 563                                 SMU74_MAX_LEVELS_LINK : pcie_table->count;
 564                 for (i = 1; i < max_entry; i++) {
 565                         phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i - 1,
 566                                         get_pcie_gen_support(data->pcie_gen_cap,
 567                                                         pcie_table->entries[i].gen_speed),
 568                                         get_pcie_lane_support(data->pcie_lane_cap,
 569                                                         pcie_table->entries[i].lane_width));
 570                 }
 571                 data->dpm_table.pcie_speed_table.count = max_entry - 1;
 572
 573                 /* Setup BIF_SCLK levels */
 574                 for (i = 0; i < max_entry; i++)
 575                         data->bif_sclk_table[i] = pcie_table->entries[i].pcie_sclk;
 576         } else {
 577                 /* Hardcode Pcie Table */
 578                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 0,
 579                                 get_pcie_gen_support(data->pcie_gen_cap,
 580                                                 PP_Min_PCIEGen),
 581                                 get_pcie_lane_support(data->pcie_lane_cap,
 582                                                 PP_Max_PCIELane));
 583                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 1,
 584                                 get_pcie_gen_support(data->pcie_gen_cap,
 585                                                 PP_Min_PCIEGen),
 586                                 get_pcie_lane_support(data->pcie_lane_cap,
 587                                                 PP_Max_PCIELane));
 588                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 2,
 589                                 get_pcie_gen_support(data->pcie_gen_cap,
 590                                                 PP_Max_PCIEGen),
 591                                 get_pcie_lane_support(data->pcie_lane_cap,
 592                                                 PP_Max_PCIELane));
 593                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 3,
 594                                 get_pcie_gen_support(data->pcie_gen_cap,
 595                                                 PP_Max_PCIEGen),
 596                                 get_pcie_lane_support(data->pcie_lane_cap,
 597                                                 PP_Max_PCIELane));
 598                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 4,
 599                                 get_pcie_gen_support(data->pcie_gen_cap,
 600                                                 PP_Max_PCIEGen),
 601                                 get_pcie_lane_support(data->pcie_lane_cap,
 602                                                 PP_Max_PCIELane));
 603                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 5,
 604                                 get_pcie_gen_support(data->pcie_gen_cap,
 605                                                 PP_Max_PCIEGen),
 606                                 get_pcie_lane_support(data->pcie_lane_cap,
 607                                                 PP_Max_PCIELane));
 608
 609                 data->dpm_table.pcie_speed_table.count = 6;
 610         }
 611         /* Populate last level for boot PCIE level, but do not increment count. */
 612         phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table,
 613                         data->dpm_table.pcie_speed_table.count,
 614                         get_pcie_gen_support(data->pcie_gen_cap,
 615                                         PP_Min_PCIEGen),
 616                         get_pcie_lane_support(data->pcie_lane_cap,
 617                                         PP_Max_PCIELane));
 618
 619         return 0;
 620 }
 621
 622 /*
 623  * This function is to initalize all DPM state tables
 624  * for SMU7 based on the dependency table.
 625  * Dynamic state patching function will then trim these
 626  * state tables to the allowed range based
 627  * on the power policy or external client requests,
 628  * such as UVD request, etc.
 629  */
 630 int polaris10_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
 631 {
 632         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 633         struct phm_ppt_v1_information *table_info =
 634                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 635         uint32_t i;
 636
 637         struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table =
 638                         table_info->vdd_dep_on_sclk;
 639         struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
 640                         table_info->vdd_dep_on_mclk;
 641
 642         PP_ASSERT_WITH_CODE(dep_sclk_table != NULL,
 643                         "SCLK dependency table is missing. This table is mandatory",
 644                         return -EINVAL);
 645         PP_ASSERT_WITH_CODE(dep_sclk_table->count >= 1,
 646                         "SCLK dependency table has to have is missing."
 647                         "This table is mandatory",
 648                         return -EINVAL);
 649
 650         PP_ASSERT_WITH_CODE(dep_mclk_table != NULL,
 651                         "MCLK dependency table is missing. This table is mandatory",
 652                         return -EINVAL);
 653         PP_ASSERT_WITH_CODE(dep_mclk_table->count >= 1,
 654                         "MCLK dependency table has to have is missing."
 655                         "This table is mandatory",
 656                         return -EINVAL);
 657
 658         /* clear the state table to reset everything to default */
 659         phm_reset_single_dpm_table(
 660                         &data->dpm_table.sclk_table, SMU74_MAX_LEVELS_GRAPHICS, MAX_REGULAR_DPM_NUMBER);
 661         phm_reset_single_dpm_table(
 662                         &data->dpm_table.mclk_table, SMU74_MAX_LEVELS_MEMORY, MAX_REGULAR_DPM_NUMBER);
 663
 664
 665         /* Initialize Sclk DPM table based on allow Sclk values */
 666         data->dpm_table.sclk_table.count = 0;
 667         for (i = 0; i < dep_sclk_table->count; i++) {
 668                 if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count - 1].value !=
 669                                                 dep_sclk_table->entries[i].clk) {
 670
 671                         data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value =
 672                                         dep_sclk_table->entries[i].clk;
 673
 674                         data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled =
 675                                         (i == 0) ? true : false;
 676                         data->dpm_table.sclk_table.count++;
 677                 }
 678         }
 679
 680         /* Initialize Mclk DPM table based on allow Mclk values */
 681         data->dpm_table.mclk_table.count = 0;
 682         for (i = 0; i < dep_mclk_table->count; i++) {
 683                 if (i == 0 || data->dpm_table.mclk_table.dpm_levels
 684                                 [data->dpm_table.mclk_table.count - 1].value !=
 685                                                 dep_mclk_table->entries[i].clk) {
 686                         data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value =
 687                                                         dep_mclk_table->entries[i].clk;
 688                         data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled =
 689                                                         (i == 0) ? true : false;
 690                         data->dpm_table.mclk_table.count++;
 691                 }
 692         }
 693
 694         /* setup PCIE gen speed levels */
 695         polaris10_setup_default_pcie_table(hwmgr);
 696
 697         /* save a copy of the default DPM table */
 698         memcpy(&(data->golden_dpm_table), &(data->dpm_table),
 699                         sizeof(struct polaris10_dpm_table));
 700
 701         return 0;
 702 }
 703
 704 uint8_t convert_to_vid(uint16_t vddc)
 705 {
 706         return (uint8_t) ((6200 - (vddc * VOLTAGE_SCALE)) / 25);
 707 }
 708
 709 /**
 710  * Mvdd table preparation for SMC.
 711  *
 712  * @param    *hwmgr The address of the hardware manager.
 713  * @param    *table The SMC DPM table structure to be populated.
 714  * @return   0
 715  */
 716 static int polaris10_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr,
 717                         SMU74_Discrete_DpmTable *table)
 718 {
 719         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 720         uint32_t count, level;
 721
 722         if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
 723                 count = data->mvdd_voltage_table.count;
 724                 if (count > SMU_MAX_SMIO_LEVELS)
 725                         count = SMU_MAX_SMIO_LEVELS;
 726                 for (level = 0; level < count; level++) {
 727                         table->SmioTable2.Pattern[level].Voltage =
 728                                 PP_HOST_TO_SMC_US(data->mvdd_voltage_table.entries[count].value * VOLTAGE_SCALE);
 729                         /* Index into DpmTable.Smio. Drive bits from Smio entry to get this voltage level.*/
 730                         table->SmioTable2.Pattern[level].Smio =
 731                                 (uint8_t) level;
 732                         table->Smio[level] |=
 733                                 data->mvdd_voltage_table.entries[level].smio_low;
 734                 }
 735                 table->SmioMask2 = data->vddci_voltage_table.mask_low;
 736
 737                 table->MvddLevelCount = (uint32_t) PP_HOST_TO_SMC_UL(count);
 738         }
 739
 740         return 0;
 741 }
 742
 743 static int polaris10_populate_smc_vddci_table(struct pp_hwmgr *hwmgr,
 744                                         struct SMU74_Discrete_DpmTable *table)
 745 {
 746         uint32_t count, level;
 747         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 748
 749         count = data->vddci_voltage_table.count;
 750
 751         if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
 752                 if (count > SMU_MAX_SMIO_LEVELS)
 753                         count = SMU_MAX_SMIO_LEVELS;
 754                 for (level = 0; level < count; ++level) {
 755                         table->SmioTable1.Pattern[level].Voltage =
 756                                 PP_HOST_TO_SMC_US(data->vddci_voltage_table.entries[level].value * VOLTAGE_SCALE);
 757                         table->SmioTable1.Pattern[level].Smio = (uint8_t) level;
 758
 759                         table->Smio[level] |= data->vddci_voltage_table.entries[level].smio_low;
 760                 }
 761         }
 762
 763         table->SmioMask1 = data->vddci_voltage_table.mask_low;
 764
 765         return 0;
 766 }
 767
 768 /**
 769 * Preparation of vddc and vddgfx CAC tables for SMC.
 770 *
 771 * @param    hwmgr  the address of the hardware manager
 772 * @param    table  the SMC DPM table structure to be populated
 773 * @return   always 0
 774 */
 775 static int polaris10_populate_cac_table(struct pp_hwmgr *hwmgr,
 776                 struct SMU74_Discrete_DpmTable *table)
 777 {
 778         uint32_t count;
 779         uint8_t index;
 780         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 781         struct phm_ppt_v1_information *table_info =
 782                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 783         struct phm_ppt_v1_voltage_lookup_table *lookup_table =
 784                         table_info->vddc_lookup_table;
 785         /* tables is already swapped, so in order to use the value from it,
 786          * we need to swap it back.
 787          * We are populating vddc CAC data to BapmVddc table
 788          * in split and merged mode
 789          */
 790         for (count = 0; count < lookup_table->count; count++) {
 791                 index = phm_get_voltage_index(lookup_table,
 792                                 data->vddc_voltage_table.entries[count].value);
 793                 table->BapmVddcVidLoSidd[count] = convert_to_vid(lookup_table->entries[index].us_cac_low);
 794                 table->BapmVddcVidHiSidd[count] = convert_to_vid(lookup_table->entries[index].us_cac_mid);
 795                 table->BapmVddcVidHiSidd2[count] = convert_to_vid(lookup_table->entries[index].us_cac_high);
 796         }
 797
 798         return 0;
 799 }
 800
 801 /**
 802 * Preparation of voltage tables for SMC.
 803 *
 804 * @param    hwmgr   the address of the hardware manager
 805 * @param    table   the SMC DPM table structure to be populated
 806 * @return   always  0
 807 */
 808
 809 int polaris10_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
 810                 struct SMU74_Discrete_DpmTable *table)
 811 {
 812         polaris10_populate_smc_vddci_table(hwmgr, table);
 813         polaris10_populate_smc_mvdd_table(hwmgr, table);
 814         polaris10_populate_cac_table(hwmgr, table);
 815
 816         return 0;
 817 }
 818
 819 static int polaris10_populate_ulv_level(struct pp_hwmgr *hwmgr,
 820                 struct SMU74_Discrete_Ulv *state)
 821 {
 822         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 823         struct phm_ppt_v1_information *table_info =
 824                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 825
 826         state->CcPwrDynRm = 0;
 827         state->CcPwrDynRm1 = 0;
 828
 829         state->VddcOffset = (uint16_t) table_info->us_ulv_voltage_offset;
 830         state->VddcOffsetVid = (uint8_t)(table_info->us_ulv_voltage_offset *
 831                         VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
 832
 833         state->VddcPhase = (data->vddc_phase_shed_control) ? 0 : 1;
 834
 835         CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm);
 836         CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm1);
 837         CONVERT_FROM_HOST_TO_SMC_US(state->VddcOffset);
 838
 839         return 0;
 840 }
 841
 842 static int polaris10_populate_ulv_state(struct pp_hwmgr *hwmgr,
 843                 struct SMU74_Discrete_DpmTable *table)
 844 {
 845         return polaris10_populate_ulv_level(hwmgr, &table->Ulv);
 846 }
 847
 848 static int polaris10_populate_smc_link_level(struct pp_hwmgr *hwmgr,
 849                 struct SMU74_Discrete_DpmTable *table)
 850 {
 851         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 852         struct polaris10_dpm_table *dpm_table = &data->dpm_table;
 853         int i;
 854
 855         /* Index (dpm_table->pcie_speed_table.count)
 856          * is reserved for PCIE boot level. */
 857         for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
 858                 table->LinkLevel[i].PcieGenSpeed  =
 859                                 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
 860                 table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width(
 861                                 dpm_table->pcie_speed_table.dpm_levels[i].param1);
 862                 table->LinkLevel[i].EnabledForActivity = 1;
 863                 table->LinkLevel[i].SPC = (uint8_t)(data->pcie_spc_cap & 0xff);
 864                 table->LinkLevel[i].DownThreshold = PP_HOST_TO_SMC_UL(5);
 865                 table->LinkLevel[i].UpThreshold = PP_HOST_TO_SMC_UL(30);
 866         }
 867
 868         data->smc_state_table.LinkLevelCount =
 869                         (uint8_t)dpm_table->pcie_speed_table.count;
 870         data->dpm_level_enable_mask.pcie_dpm_enable_mask =
 871                         phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
 872
 873         return 0;
 874 }
 875
 876 static uint32_t polaris10_get_xclk(struct pp_hwmgr *hwmgr)
 877 {
 878         uint32_t reference_clock, tmp;
 879         struct cgs_display_info info = {0};
 880         struct cgs_mode_info mode_info;
 881
 882         info.mode_info = &mode_info;
 883
 884         tmp = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_CLKPIN_CNTL_2, MUX_TCLK_TO_XCLK);
 885
 886         if (tmp)
 887                 return TCLK;
 888
 889         cgs_get_active_displays_info(hwmgr->device, &info);
 890         reference_clock = mode_info.ref_clock;
 891
 892         tmp = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_CLKPIN_CNTL, XTALIN_DIVIDE);
 893
 894         if (0 != tmp)
 895                 return reference_clock / 4;
 896
 897         return reference_clock;
 898 }
 899
 900 /**
 901 * Calculates the SCLK dividers using the provided engine clock
 902 *
 903 * @param    hwmgr  the address of the hardware manager
 904 * @param    clock  the engine clock to use to populate the structure
 905 * @param    sclk   the SMC SCLK structure to be populated
 906 */
 907 static int polaris10_calculate_sclk_params(struct pp_hwmgr *hwmgr,
 908                 uint32_t clock, SMU_SclkSetting *sclk_setting)
 909 {
 910         const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 911         const SMU74_Discrete_DpmTable *table = &(data->smc_state_table);
 912         struct pp_atomctrl_clock_dividers_ai dividers;
 913
 914         uint32_t ref_clock;
 915         uint32_t pcc_target_percent, pcc_target_freq, ss_target_percent, ss_target_freq;
 916         uint8_t i;
 917         int result;
 918         uint64_t temp;
 919
 920         sclk_setting->SclkFrequency = clock;
 921         /* get the engine clock dividers for this clock value */
 922         result = atomctrl_get_engine_pll_dividers_ai(hwmgr, clock,  &dividers);
 923         if (result == 0) {
 924                 sclk_setting->Fcw_int = dividers.usSclk_fcw_int;
 925                 sclk_setting->Fcw_frac = dividers.usSclk_fcw_frac;
 926                 sclk_setting->Pcc_fcw_int = dividers.usPcc_fcw_int;
 927                 sclk_setting->PllRange = dividers.ucSclkPllRange;
 928                 sclk_setting->Sclk_slew_rate = 0x400;
 929                 sclk_setting->Pcc_up_slew_rate = dividers.usPcc_fcw_slew_frac;
 930                 sclk_setting->Pcc_down_slew_rate = 0xffff;
 931                 sclk_setting->SSc_En = dividers.ucSscEnable;
 932                 sclk_setting->Fcw1_int = dividers.usSsc_fcw1_int;
 933                 sclk_setting->Fcw1_frac = dividers.usSsc_fcw1_frac;
 934                 sclk_setting->Sclk_ss_slew_rate = dividers.usSsc_fcw_slew_frac;
 935                 return result;
 936         }
 937
 938         ref_clock = polaris10_get_xclk(hwmgr);
 939
 940         for (i = 0; i < NUM_SCLK_RANGE; i++) {
 941                 if (clock > data->range_table[i].trans_lower_frequency
 942                 && clock <= data->range_table[i].trans_upper_frequency) {
 943                         sclk_setting->PllRange = i;
 944                         break;
 945                 }
 946         }
 947
 948         sclk_setting->Fcw_int = (uint16_t)((clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
 949         temp = clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
 950         temp <<= 0x10;
 951         do_div(temp, ref_clock);
 952         sclk_setting->Fcw_frac = temp & 0xffff;
 953
 954         pcc_target_percent = 10; /*  Hardcode 10% for now. */
 955         pcc_target_freq = clock - (clock * pcc_target_percent / 100);
 956         sclk_setting->Pcc_fcw_int = (uint16_t)((pcc_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
 957
 958         ss_target_percent = 2; /*  Hardcode 2% for now. */
 959         sclk_setting->SSc_En = 0;
 960         if (ss_target_percent) {
 961                 sclk_setting->SSc_En = 1;
 962                 ss_target_freq = clock - (clock * ss_target_percent / 100);
 963                 sclk_setting->Fcw1_int = (uint16_t)((ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
 964                 temp = ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
 965                 temp <<= 0x10;
 966                 do_div(temp, ref_clock);
 967                 sclk_setting->Fcw1_frac = temp & 0xffff;
 968         }
 969
 970         return 0;
 971 }
 972
 973 static int polaris10_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr,
 974                 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table,
 975                 uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd)
 976 {
 977         uint32_t i;
 978         uint16_t vddci;
 979         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 980
 981         *voltage = *mvdd = 0;
 982
 983         /* clock - voltage dependency table is empty table */
 984         if (dep_table->count == 0)
 985                 return -EINVAL;
 986
 987         for (i = 0; i < dep_table->count; i++) {
 988                 /* find first sclk bigger than request */
 989                 if (dep_table->entries[i].clk >= clock) {
 990                         *voltage |= (dep_table->entries[i].vddc *
 991                                         VOLTAGE_SCALE) << VDDC_SHIFT;
 992                         if (POLARIS10_VOLTAGE_CONTROL_NONE == data->vddci_control)
 993                                 *voltage |= (data->vbios_boot_state.vddci_bootup_value *
 994                                                 VOLTAGE_SCALE) << VDDCI_SHIFT;
 995                         else if (dep_table->entries[i].vddci)
 996                                 *voltage |= (dep_table->entries[i].vddci *
 997                                                 VOLTAGE_SCALE) << VDDCI_SHIFT;
 998                         else {
 999                                 vddci = phm_find_closest_vddci(&(data->vddci_voltage_table),
1000                                                 (dep_table->entries[i].vddc -
1001                                                                 (uint16_t)data->vddc_vddci_delta));
1002                                 *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1003                         }
1004
1005                         if (POLARIS10_VOLTAGE_CONTROL_NONE == data->mvdd_control)
1006                                 *mvdd = data->vbios_boot_state.mvdd_bootup_value *
1007                                         VOLTAGE_SCALE;
1008                         else if (dep_table->entries[i].mvdd)
1009                                 *mvdd = (uint32_t) dep_table->entries[i].mvdd *
1010                                         VOLTAGE_SCALE;
1011
1012                         *voltage |= 1 << PHASES_SHIFT;
1013                         return 0;
1014                 }
1015         }
1016
1017         /* sclk is bigger than max sclk in the dependence table */
1018         *voltage |= (dep_table->entries[i - 1].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
1019
1020         if (POLARIS10_VOLTAGE_CONTROL_NONE == data->vddci_control)
1021                 *voltage |= (data->vbios_boot_state.vddci_bootup_value *
1022                                 VOLTAGE_SCALE) << VDDCI_SHIFT;
1023         else if (dep_table->entries[i-1].vddci) {
1024                 vddci = phm_find_closest_vddci(&(data->vddci_voltage_table),
1025                                 (dep_table->entries[i].vddc -
1026                                                 (uint16_t)data->vddc_vddci_delta));
1027                 *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1028         }
1029
1030         if (POLARIS10_VOLTAGE_CONTROL_NONE == data->mvdd_control)
1031                 *mvdd = data->vbios_boot_state.mvdd_bootup_value * VOLTAGE_SCALE;
1032         else if (dep_table->entries[i].mvdd)
1033                 *mvdd = (uint32_t) dep_table->entries[i - 1].mvdd * VOLTAGE_SCALE;
1034
1035         return 0;
1036 }
1037
1038 static const sclkFcwRange_t Range_Table[NUM_SCLK_RANGE] =
1039 { {VCO_2_4, POSTDIV_DIV_BY_16,  75, 160, 112},
1040   {VCO_3_6, POSTDIV_DIV_BY_16, 112, 224, 160},
1041   {VCO_2_4, POSTDIV_DIV_BY_8,   75, 160, 112},
1042   {VCO_3_6, POSTDIV_DIV_BY_8,  112, 224, 160},
1043   {VCO_2_4, POSTDIV_DIV_BY_4,   75, 160, 112},
1044   {VCO_3_6, POSTDIV_DIV_BY_4,  112, 216, 160},
1045   {VCO_2_4, POSTDIV_DIV_BY_2,   75, 160, 108},
1046   {VCO_3_6, POSTDIV_DIV_BY_2,  112, 216, 160} };
1047
1048 static void polaris10_get_sclk_range_table(struct pp_hwmgr *hwmgr)
1049 {
1050         uint32_t i, ref_clk;
1051         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1052         SMU74_Discrete_DpmTable  *table = &(data->smc_state_table);
1053         struct pp_atom_ctrl_sclk_range_table range_table_from_vbios = { { {0} } };
1054
1055         ref_clk = polaris10_get_xclk(hwmgr);
1056
1057         if (0 == atomctrl_get_smc_sclk_range_table(hwmgr, &range_table_from_vbios)) {
1058                 for (i = 0; i < NUM_SCLK_RANGE; i++) {
1059                         table->SclkFcwRangeTable[i].vco_setting = range_table_from_vbios.entry[i].ucVco_setting;
1060                         table->SclkFcwRangeTable[i].postdiv = range_table_from_vbios.entry[i].ucPostdiv;
1061                         table->SclkFcwRangeTable[i].fcw_pcc = range_table_from_vbios.entry[i].usFcw_pcc;
1062
1063                         table->SclkFcwRangeTable[i].fcw_trans_upper = range_table_from_vbios.entry[i].usFcw_trans_upper;
1064                         table->SclkFcwRangeTable[i].fcw_trans_lower = range_table_from_vbios.entry[i].usRcw_trans_lower;
1065
1066                         CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc);
1067                         CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper);
1068                         CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower);
1069                 }
1070                 return;
1071         }
1072
1073         for (i = 0; i < NUM_SCLK_RANGE; i++) {
1074
1075                 data->range_table[i].trans_lower_frequency = (ref_clk * Range_Table[i].fcw_trans_lower) >> Range_Table[i].postdiv;
1076                 data->range_table[i].trans_upper_frequency = (ref_clk * Range_Table[i].fcw_trans_upper) >> Range_Table[i].postdiv;
1077
1078                 table->SclkFcwRangeTable[i].vco_setting = Range_Table[i].vco_setting;
1079                 table->SclkFcwRangeTable[i].postdiv = Range_Table[i].postdiv;
1080                 table->SclkFcwRangeTable[i].fcw_pcc = Range_Table[i].fcw_pcc;
1081
1082                 table->SclkFcwRangeTable[i].fcw_trans_upper = Range_Table[i].fcw_trans_upper;
1083                 table->SclkFcwRangeTable[i].fcw_trans_lower = Range_Table[i].fcw_trans_lower;
1084
1085                 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc);
1086                 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper);
1087                 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower);
1088         }
1089 }
1090
1091 /**
1092 * Populates single SMC SCLK structure using the provided engine clock
1093 *
1094 * @param    hwmgr      the address of the hardware manager
1095 * @param    clock the engine clock to use to populate the structure
1096 * @param    sclk        the SMC SCLK structure to be populated
1097 */
1098
1099 static int polaris10_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
1100                 uint32_t clock, uint16_t sclk_al_threshold,
1101                 struct SMU74_Discrete_GraphicsLevel *level)
1102 {
1103         int result, i, temp;
1104         /* PP_Clocks minClocks; */
1105         uint32_t mvdd;
1106         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1107         struct phm_ppt_v1_information *table_info =
1108                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1109         SMU_SclkSetting curr_sclk_setting = { 0 };
1110
1111         result = polaris10_calculate_sclk_params(hwmgr, clock, &curr_sclk_setting);
1112
1113         /* populate graphics levels */
1114         result = polaris10_get_dependency_volt_by_clk(hwmgr,
1115                         table_info->vdd_dep_on_sclk, clock,
1116                         &level->MinVoltage, &mvdd);
1117
1118         PP_ASSERT_WITH_CODE((0 == result),
1119                         "can not find VDDC voltage value for "
1120                         "VDDC engine clock dependency table",
1121                         return result);
1122         level->ActivityLevel = sclk_al_threshold;
1123
1124         level->CcPwrDynRm = 0;
1125         level->CcPwrDynRm1 = 0;
1126         level->EnabledForActivity = 0;
1127         level->EnabledForThrottle = 1;
1128         level->UpHyst = 10;
1129         level->DownHyst = 0;
1130         level->VoltageDownHyst = 0;
1131         level->PowerThrottle = 0;
1132
1133         /*
1134         * TODO: get minimum clocks from dal configaration
1135         * PECI_GetMinClockSettings(hwmgr->pPECI, &minClocks);
1136         */
1137         /* data->DisplayTiming.minClockInSR = minClocks.engineClockInSR; */
1138
1139         /* get level->DeepSleepDivId
1140         if (phm_cap_enabled(hwmgr->platformDescriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep))
1141                 level->DeepSleepDivId = PhwFiji_GetSleepDividerIdFromClock(hwmgr, clock, minClocks.engineClockInSR);
1142         */
1143         PP_ASSERT_WITH_CODE((clock >= POLARIS10_MINIMUM_ENGINE_CLOCK), "Engine clock can't satisfy stutter requirement!", return 0);
1144         for (i = POLARIS10_MAX_DEEPSLEEP_DIVIDER_ID;  ; i--) {
1145                 temp = clock >> i;
1146
1147                 if (temp >= POLARIS10_MINIMUM_ENGINE_CLOCK || i == 0)
1148                         break;
1149         }
1150
1151         level->DeepSleepDivId = i;
1152
1153         /* Default to slow, highest DPM level will be
1154          * set to PPSMC_DISPLAY_WATERMARK_LOW later.
1155          */
1156         if (data->update_up_hyst)
1157                 level->UpHyst = (uint8_t)data->up_hyst;
1158         if (data->update_down_hyst)
1159                 level->DownHyst = (uint8_t)data->down_hyst;
1160
1161         level->SclkSetting = curr_sclk_setting;
1162
1163         CONVERT_FROM_HOST_TO_SMC_UL(level->MinVoltage);
1164         CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm);
1165         CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm1);
1166         CONVERT_FROM_HOST_TO_SMC_US(level->ActivityLevel);
1167         CONVERT_FROM_HOST_TO_SMC_UL(level->SclkSetting.SclkFrequency);
1168         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_int);
1169         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_frac);
1170         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_fcw_int);
1171         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Sclk_slew_rate);
1172         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_up_slew_rate);
1173         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_down_slew_rate);
1174         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_int);
1175         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_frac);
1176         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Sclk_ss_slew_rate);
1177         return 0;
1178 }
1179
1180 /**
1181 * Populates all SMC SCLK levels' structure based on the trimmed allowed dpm engine clock states
1182 *
1183 * @param    hwmgr      the address of the hardware manager
1184 */
1185 static int polaris10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
1186 {
1187         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1188         struct polaris10_dpm_table *dpm_table = &data->dpm_table;
1189         struct phm_ppt_v1_information *table_info =
1190                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1191         struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
1192         uint8_t pcie_entry_cnt = (uint8_t) data->dpm_table.pcie_speed_table.count;
1193         int result = 0;
1194         uint32_t array = data->dpm_table_start +
1195                         offsetof(SMU74_Discrete_DpmTable, GraphicsLevel);
1196         uint32_t array_size = sizeof(struct SMU74_Discrete_GraphicsLevel) *
1197                         SMU74_MAX_LEVELS_GRAPHICS;
1198         struct SMU74_Discrete_GraphicsLevel *levels =
1199                         data->smc_state_table.GraphicsLevel;
1200         uint32_t i, max_entry;
1201         uint8_t hightest_pcie_level_enabled = 0,
1202                 lowest_pcie_level_enabled = 0,
1203                 mid_pcie_level_enabled = 0,
1204                 count = 0;
1205
1206         polaris10_get_sclk_range_table(hwmgr);
1207
1208         for (i = 0; i < dpm_table->sclk_table.count; i++) {
1209
1210                 result = polaris10_populate_single_graphic_level(hwmgr,
1211                                 dpm_table->sclk_table.dpm_levels[i].value,
1212                                 (uint16_t)data->activity_target[i],
1213                                 &(data->smc_state_table.GraphicsLevel[i]));
1214                 if (result)
1215                         return result;
1216
1217                 /* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */
1218                 if (i > 1)
1219                         levels[i].DeepSleepDivId = 0;
1220         }
1221         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1222                                         PHM_PlatformCaps_SPLLShutdownSupport))
1223                 data->smc_state_table.GraphicsLevel[0].SclkSetting.SSc_En = 0;
1224
1225         data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
1226         data->smc_state_table.GraphicsDpmLevelCount =
1227                         (uint8_t)dpm_table->sclk_table.count;
1228         data->dpm_level_enable_mask.sclk_dpm_enable_mask =
1229                         phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
1230
1231
1232         if (pcie_table != NULL) {
1233                 PP_ASSERT_WITH_CODE((1 <= pcie_entry_cnt),
1234                                 "There must be 1 or more PCIE levels defined in PPTable.",
1235                                 return -EINVAL);
1236                 max_entry = pcie_entry_cnt - 1;
1237                 for (i = 0; i < dpm_table->sclk_table.count; i++)
1238                         levels[i].pcieDpmLevel =
1239                                         (uint8_t) ((i < max_entry) ? i : max_entry);
1240         } else {
1241                 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
1242                                 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1243                                                 (1 << (hightest_pcie_level_enabled + 1))) != 0))
1244                         hightest_pcie_level_enabled++;
1245
1246                 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
1247                                 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1248                                                 (1 << lowest_pcie_level_enabled)) == 0))
1249                         lowest_pcie_level_enabled++;
1250
1251                 while ((count < hightest_pcie_level_enabled) &&
1252                                 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1253                                                 (1 << (lowest_pcie_level_enabled + 1 + count))) == 0))
1254                         count++;
1255
1256                 mid_pcie_level_enabled = (lowest_pcie_level_enabled + 1 + count) <
1257                                 hightest_pcie_level_enabled ?
1258                                                 (lowest_pcie_level_enabled + 1 + count) :
1259                                                 hightest_pcie_level_enabled;
1260
1261                 /* set pcieDpmLevel to hightest_pcie_level_enabled */
1262                 for (i = 2; i < dpm_table->sclk_table.count; i++)
1263                         levels[i].pcieDpmLevel = hightest_pcie_level_enabled;
1264
1265                 /* set pcieDpmLevel to lowest_pcie_level_enabled */
1266                 levels[0].pcieDpmLevel = lowest_pcie_level_enabled;
1267
1268                 /* set pcieDpmLevel to mid_pcie_level_enabled */
1269                 levels[1].pcieDpmLevel = mid_pcie_level_enabled;
1270         }
1271         /* level count will send to smc once at init smc table and never change */
1272         result = polaris10_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels,
1273                         (uint32_t)array_size, data->sram_end);
1274
1275         return result;
1276 }
1277
1278 static int polaris10_populate_single_memory_level(struct pp_hwmgr *hwmgr,
1279                 uint32_t clock, struct SMU74_Discrete_MemoryLevel *mem_level)
1280 {
1281         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1282         struct phm_ppt_v1_information *table_info =
1283                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1284         int result = 0;
1285         struct cgs_display_info info = {0, 0, NULL};
1286
1287         cgs_get_active_displays_info(hwmgr->device, &info);
1288
1289         if (table_info->vdd_dep_on_mclk) {
1290                 result = polaris10_get_dependency_volt_by_clk(hwmgr,
1291                                 table_info->vdd_dep_on_mclk, clock,
1292                                 &mem_level->MinVoltage, &mem_level->MinMvdd);
1293                 PP_ASSERT_WITH_CODE((0 == result),
1294                                 "can not find MinVddc voltage value from memory "
1295                                 "VDDC voltage dependency table", return result);
1296         }
1297
1298         mem_level->MclkFrequency = clock;
1299         mem_level->EnabledForThrottle = 1;
1300         mem_level->EnabledForActivity = 0;
1301         mem_level->UpHyst = 0;
1302         mem_level->DownHyst = 100;
1303         mem_level->VoltageDownHyst = 0;
1304         mem_level->ActivityLevel = (uint16_t)data->mclk_activity_target;
1305         mem_level->StutterEnable = false;
1306         mem_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
1307
1308         data->display_timing.num_existing_displays = info.display_count;
1309
1310         if ((data->mclk_stutter_mode_threshold) &&
1311                 (clock <= data->mclk_stutter_mode_threshold) &&
1312                 (PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL,
1313                                 STUTTER_ENABLE) & 0x1))
1314                 mem_level->StutterEnable = true;
1315
1316         if (!result) {
1317                 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinMvdd);
1318                 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MclkFrequency);
1319                 CONVERT_FROM_HOST_TO_SMC_US(mem_level->ActivityLevel);
1320                 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinVoltage);
1321         }
1322         return result;
1323 }
1324
1325 /**
1326 * Populates all SMC MCLK levels' structure based on the trimmed allowed dpm memory clock states
1327 *
1328 * @param    hwmgr      the address of the hardware manager
1329 */
1330 static int polaris10_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
1331 {
1332         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1333         struct polaris10_dpm_table *dpm_table = &data->dpm_table;
1334         int result;
1335         /* populate MCLK dpm table to SMU7 */
1336         uint32_t array = data->dpm_table_start +
1337                         offsetof(SMU74_Discrete_DpmTable, MemoryLevel);
1338         uint32_t array_size = sizeof(SMU74_Discrete_MemoryLevel) *
1339                         SMU74_MAX_LEVELS_MEMORY;
1340         struct SMU74_Discrete_MemoryLevel *levels =
1341                         data->smc_state_table.MemoryLevel;
1342         uint32_t i;
1343
1344         for (i = 0; i < dpm_table->mclk_table.count; i++) {
1345                 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),
1346                                 "can not populate memory level as memory clock is zero",
1347                                 return -EINVAL);
1348                 result = polaris10_populate_single_memory_level(hwmgr,
1349                                 dpm_table->mclk_table.dpm_levels[i].value,
1350                                 &levels[i]);
1351                 if (i == dpm_table->mclk_table.count - 1) {
1352                         levels[i].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH;
1353                         levels[i].EnabledForActivity = 1;
1354                 }
1355                 if (result)
1356                         return result;
1357         }
1358
1359         /* in order to prevent MC activity from stutter mode to push DPM up.
1360          * the UVD change complements this by putting the MCLK in
1361          * a higher state by default such that we are not effected by
1362          * up threshold or and MCLK DPM latency.
1363          */
1364         levels[0].ActivityLevel = 0x1f;
1365         CONVERT_FROM_HOST_TO_SMC_US(levels[0].ActivityLevel);
1366
1367         data->smc_state_table.MemoryDpmLevelCount =
1368                         (uint8_t)dpm_table->mclk_table.count;
1369         data->dpm_level_enable_mask.mclk_dpm_enable_mask =
1370                         phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
1371
1372         /* level count will send to smc once at init smc table and never change */
1373         result = polaris10_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels,
1374                         (uint32_t)array_size, data->sram_end);
1375
1376         return result;
1377 }
1378
1379 /**
1380 * Populates the SMC MVDD structure using the provided memory clock.
1381 *
1382 * @param    hwmgr      the address of the hardware manager
1383 * @param    mclk        the MCLK value to be used in the decision if MVDD should be high or low.
1384 * @param    voltage     the SMC VOLTAGE structure to be populated
1385 */
1386 int polaris10_populate_mvdd_value(struct pp_hwmgr *hwmgr,
1387                 uint32_t mclk, SMIO_Pattern *smio_pat)
1388 {
1389         const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1390         struct phm_ppt_v1_information *table_info =
1391                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1392         uint32_t i = 0;
1393
1394         if (POLARIS10_VOLTAGE_CONTROL_NONE != data->mvdd_control) {
1395                 /* find mvdd value which clock is more than request */
1396                 for (i = 0; i < table_info->vdd_dep_on_mclk->count; i++) {
1397                         if (mclk <= table_info->vdd_dep_on_mclk->entries[i].clk) {
1398                                 smio_pat->Voltage = data->mvdd_voltage_table.entries[i].value;
1399                                 break;
1400                         }
1401                 }
1402                 PP_ASSERT_WITH_CODE(i < table_info->vdd_dep_on_mclk->count,
1403                                 "MVDD Voltage is outside the supported range.",
1404                                 return -EINVAL);
1405         } else
1406                 return -EINVAL;
1407
1408         return 0;
1409 }
1410
1411 static int polaris10_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
1412                 SMU74_Discrete_DpmTable *table)
1413 {
1414         int result = 0;
1415         uint32_t sclk_frequency;
1416         const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1417         struct phm_ppt_v1_information *table_info =
1418                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1419         SMIO_Pattern vol_level;
1420         uint32_t mvdd;
1421         uint16_t us_mvdd;
1422
1423         table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
1424
1425         if (!data->sclk_dpm_key_disabled) {
1426                 /* Get MinVoltage and Frequency from DPM0,
1427                  * already converted to SMC_UL */
1428                 sclk_frequency = data->dpm_table.sclk_table.dpm_levels[0].value;
1429                 result = polaris10_get_dependency_volt_by_clk(hwmgr,
1430                                 table_info->vdd_dep_on_sclk,
1431                                 table->ACPILevel.SclkFrequency,
1432                                 &table->ACPILevel.MinVoltage, &mvdd);
1433                 PP_ASSERT_WITH_CODE((0 == result),
1434                                 "Cannot find ACPI VDDC voltage value "
1435                                 "in Clock Dependency Table", );
1436         } else {
1437                 sclk_frequency = data->vbios_boot_state.sclk_bootup_value;
1438                 table->ACPILevel.MinVoltage =
1439                                 data->vbios_boot_state.vddc_bootup_value * VOLTAGE_SCALE;
1440         }
1441
1442         result = polaris10_calculate_sclk_params(hwmgr, sclk_frequency,  &(table->ACPILevel.SclkSetting));
1443         PP_ASSERT_WITH_CODE(result == 0, "Error retrieving Engine Clock dividers from VBIOS.", return result);
1444
1445         table->ACPILevel.DeepSleepDivId = 0;
1446         table->ACPILevel.CcPwrDynRm = 0;
1447         table->ACPILevel.CcPwrDynRm1 = 0;
1448
1449         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);
1450         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.MinVoltage);
1451         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);
1452         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);
1453
1454         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkSetting.SclkFrequency);
1455         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_int);
1456         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_frac);
1457         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_fcw_int);
1458         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_slew_rate);
1459         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_up_slew_rate);
1460         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_down_slew_rate);
1461         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_int);
1462         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_frac);
1463         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_ss_slew_rate);
1464
1465         if (!data->mclk_dpm_key_disabled) {
1466                 /* Get MinVoltage and Frequency from DPM0, already converted to SMC_UL */
1467                 table->MemoryACPILevel.MclkFrequency =
1468                                 data->dpm_table.mclk_table.dpm_levels[0].value;
1469                 result = polaris10_get_dependency_volt_by_clk(hwmgr,
1470                                 table_info->vdd_dep_on_mclk,
1471                                 table->MemoryACPILevel.MclkFrequency,
1472                                 &table->MemoryACPILevel.MinVoltage, &mvdd);
1473                 PP_ASSERT_WITH_CODE((0 == result),
1474                                 "Cannot find ACPI VDDCI voltage value "
1475                                 "in Clock Dependency Table",
1476                                 );
1477         } else {
1478                 table->MemoryACPILevel.MclkFrequency =
1479                                 data->vbios_boot_state.mclk_bootup_value;
1480                 table->MemoryACPILevel.MinVoltage =
1481                                 data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE;
1482         }
1483
1484         us_mvdd = 0;
1485         if ((POLARIS10_VOLTAGE_CONTROL_NONE == data->mvdd_control) ||
1486                         (data->mclk_dpm_key_disabled))
1487                 us_mvdd = data->vbios_boot_state.mvdd_bootup_value;
1488         else {
1489                 if (!polaris10_populate_mvdd_value(hwmgr,
1490                                 data->dpm_table.mclk_table.dpm_levels[0].value,
1491                                 &vol_level))
1492                         us_mvdd = vol_level.Voltage;
1493         }
1494
1495         if (0 == polaris10_populate_mvdd_value(hwmgr, 0, &vol_level))
1496                 table->MemoryACPILevel.MinMvdd = PP_HOST_TO_SMC_UL(vol_level.Voltage);
1497         else
1498                 table->MemoryACPILevel.MinMvdd = 0;
1499
1500         table->MemoryACPILevel.StutterEnable = false;
1501
1502         table->MemoryACPILevel.EnabledForThrottle = 0;
1503         table->MemoryACPILevel.EnabledForActivity = 0;
1504         table->MemoryACPILevel.UpHyst = 0;
1505         table->MemoryACPILevel.DownHyst = 100;
1506         table->MemoryACPILevel.VoltageDownHyst = 0;
1507         table->MemoryACPILevel.ActivityLevel =
1508                         PP_HOST_TO_SMC_US((uint16_t)data->mclk_activity_target);
1509
1510         CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MclkFrequency);
1511         CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MinVoltage);
1512
1513         return result;
1514 }
1515
1516 static int polaris10_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
1517                 SMU74_Discrete_DpmTable *table)
1518 {
1519         int result = -EINVAL;
1520         uint8_t count;
1521         struct pp_atomctrl_clock_dividers_vi dividers;
1522         struct phm_ppt_v1_information *table_info =
1523                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1524         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1525                         table_info->mm_dep_table;
1526         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1527
1528         table->VceLevelCount = (uint8_t)(mm_table->count);
1529         table->VceBootLevel = 0;
1530
1531         for (count = 0; count < table->VceLevelCount; count++) {
1532                 table->VceLevel[count].Frequency = mm_table->entries[count].eclk;
1533                 table->VceLevel[count].MinVoltage = 0;
1534                 table->VceLevel[count].MinVoltage |=
1535                                 (mm_table->entries[count].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
1536                 table->VceLevel[count].MinVoltage |=
1537                                 ((mm_table->entries[count].vddc - data->vddc_vddci_delta) *
1538                                                 VOLTAGE_SCALE) << VDDCI_SHIFT;
1539                 table->VceLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1540
1541                 /*retrieve divider value for VBIOS */
1542                 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1543                                 table->VceLevel[count].Frequency, &dividers);
1544                 PP_ASSERT_WITH_CODE((0 == result),
1545                                 "can not find divide id for VCE engine clock",
1546                                 return result);
1547
1548                 table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1549
1550                 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency);
1551                 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].MinVoltage);
1552         }
1553         return result;
1554 }
1555
1556 static int polaris10_populate_smc_samu_level(struct pp_hwmgr *hwmgr,
1557                 SMU74_Discrete_DpmTable *table)
1558 {
1559         int result = -EINVAL;
1560         uint8_t count;
1561         struct pp_atomctrl_clock_dividers_vi dividers;
1562         struct phm_ppt_v1_information *table_info =
1563                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1564         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1565                         table_info->mm_dep_table;
1566         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1567
1568         table->SamuBootLevel = 0;
1569         table->SamuLevelCount = (uint8_t)(mm_table->count);
1570
1571         for (count = 0; count < table->SamuLevelCount; count++) {
1572                 /* not sure whether we need evclk or not */
1573                 table->SamuLevel[count].MinVoltage = 0;
1574                 table->SamuLevel[count].Frequency = mm_table->entries[count].samclock;
1575                 table->SamuLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
1576                                 VOLTAGE_SCALE) << VDDC_SHIFT;
1577                 table->SamuLevel[count].MinVoltage |= ((mm_table->entries[count].vddc -
1578                                 data->vddc_vddci_delta) * VOLTAGE_SCALE) << VDDCI_SHIFT;
1579                 table->SamuLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1580
1581                 /* retrieve divider value for VBIOS */
1582                 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1583                                 table->SamuLevel[count].Frequency, &dividers);
1584                 PP_ASSERT_WITH_CODE((0 == result),
1585                                 "can not find divide id for samu clock", return result);
1586
1587                 table->SamuLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1588
1589                 CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].Frequency);
1590                 CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].MinVoltage);
1591         }
1592         return result;
1593 }
1594
1595 static int polaris10_populate_memory_timing_parameters(struct pp_hwmgr *hwmgr,
1596                 int32_t eng_clock, int32_t mem_clock,
1597                 SMU74_Discrete_MCArbDramTimingTableEntry *arb_regs)
1598 {
1599         uint32_t dram_timing;
1600         uint32_t dram_timing2;
1601         uint32_t burst_time;
1602         int result;
1603
1604         result = atomctrl_set_engine_dram_timings_rv770(hwmgr,
1605                         eng_clock, mem_clock);
1606         PP_ASSERT_WITH_CODE(result == 0,
1607                         "Error calling VBIOS to set DRAM_TIMING.", return result);
1608
1609         dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
1610         dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
1611         burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
1612
1613
1614         arb_regs->McArbDramTiming  = PP_HOST_TO_SMC_UL(dram_timing);
1615         arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dram_timing2);
1616         arb_regs->McArbBurstTime   = (uint8_t)burst_time;
1617
1618         return 0;
1619 }
1620
1621 static int polaris10_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
1622 {
1623         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1624         struct SMU74_Discrete_MCArbDramTimingTable arb_regs;
1625         uint32_t i, j;
1626         int result = 0;
1627
1628         for (i = 0; i < data->dpm_table.sclk_table.count; i++) {
1629                 for (j = 0; j < data->dpm_table.mclk_table.count; j++) {
1630                         result = polaris10_populate_memory_timing_parameters(hwmgr,
1631                                         data->dpm_table.sclk_table.dpm_levels[i].value,
1632                                         data->dpm_table.mclk_table.dpm_levels[j].value,
1633                                         &arb_regs.entries[i][j]);
1634                         if (result == 0)
1635                                 result = atomctrl_set_ac_timing_ai(hwmgr, data->dpm_table.mclk_table.dpm_levels[j].value, j);
1636                         if (result != 0)
1637                                 return result;
1638                 }
1639         }
1640
1641         result = polaris10_copy_bytes_to_smc(
1642                         hwmgr->smumgr,
1643                         data->arb_table_start,
1644                         (uint8_t *)&arb_regs,
1645                         sizeof(SMU74_Discrete_MCArbDramTimingTable),
1646                         data->sram_end);
1647         return result;
1648 }
1649
1650 static int polaris10_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
1651                 struct SMU74_Discrete_DpmTable *table)
1652 {
1653         int result = -EINVAL;
1654         uint8_t count;
1655         struct pp_atomctrl_clock_dividers_vi dividers;
1656         struct phm_ppt_v1_information *table_info =
1657                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1658         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1659                         table_info->mm_dep_table;
1660         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1661
1662         table->UvdLevelCount = (uint8_t)(mm_table->count);
1663         table->UvdBootLevel = 0;
1664
1665         for (count = 0; count < table->UvdLevelCount; count++) {
1666                 table->UvdLevel[count].MinVoltage = 0;
1667                 table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk;
1668                 table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk;
1669                 table->UvdLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
1670                                 VOLTAGE_SCALE) << VDDC_SHIFT;
1671                 table->UvdLevel[count].MinVoltage |= ((mm_table->entries[count].vddc -
1672                                 data->vddc_vddci_delta) * VOLTAGE_SCALE) << VDDCI_SHIFT;
1673                 table->UvdLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1674
1675                 /* retrieve divider value for VBIOS */
1676                 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1677                                 table->UvdLevel[count].VclkFrequency, &dividers);
1678                 PP_ASSERT_WITH_CODE((0 == result),
1679                                 "can not find divide id for Vclk clock", return result);
1680
1681                 table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
1682
1683                 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1684                                 table->UvdLevel[count].DclkFrequency, &dividers);
1685                 PP_ASSERT_WITH_CODE((0 == result),
1686                                 "can not find divide id for Dclk clock", return result);
1687
1688                 table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;
1689
1690                 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency);
1691                 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency);
1692                 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].MinVoltage);
1693
1694         }
1695         return result;
1696 }
1697
1698 static int polaris10_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
1699                 struct SMU74_Discrete_DpmTable *table)
1700 {
1701         int result = 0;
1702         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1703
1704         table->GraphicsBootLevel = 0;
1705         table->MemoryBootLevel = 0;
1706
1707         /* find boot level from dpm table */
1708         result = phm_find_boot_level(&(data->dpm_table.sclk_table),
1709                         data->vbios_boot_state.sclk_bootup_value,
1710                         (uint32_t *)&(table->GraphicsBootLevel));
1711
1712         result = phm_find_boot_level(&(data->dpm_table.mclk_table),
1713                         data->vbios_boot_state.mclk_bootup_value,
1714                         (uint32_t *)&(table->MemoryBootLevel));
1715
1716         table->BootVddc  = data->vbios_boot_state.vddc_bootup_value *
1717                         VOLTAGE_SCALE;
1718         table->BootVddci = data->vbios_boot_state.vddci_bootup_value *
1719                         VOLTAGE_SCALE;
1720         table->BootMVdd  = data->vbios_boot_state.mvdd_bootup_value *
1721                         VOLTAGE_SCALE;
1722
1723         CONVERT_FROM_HOST_TO_SMC_US(table->BootVddc);
1724         CONVERT_FROM_HOST_TO_SMC_US(table->BootVddci);
1725         CONVERT_FROM_HOST_TO_SMC_US(table->BootMVdd);
1726
1727         return 0;
1728 }
1729
1730
1731 static int polaris10_populate_smc_initailial_state(struct pp_hwmgr *hwmgr)
1732 {
1733         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1734         struct phm_ppt_v1_information *table_info =
1735                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1736         uint8_t count, level;
1737
1738         count = (uint8_t)(table_info->vdd_dep_on_sclk->count);
1739
1740         for (level = 0; level < count; level++) {
1741                 if (table_info->vdd_dep_on_sclk->entries[level].clk >=
1742                                 data->vbios_boot_state.sclk_bootup_value) {
1743                         data->smc_state_table.GraphicsBootLevel = level;
1744                         break;
1745                 }
1746         }
1747
1748         count = (uint8_t)(table_info->vdd_dep_on_mclk->count);
1749         for (level = 0; level < count; level++) {
1750                 if (table_info->vdd_dep_on_mclk->entries[level].clk >=
1751                                 data->vbios_boot_state.mclk_bootup_value) {
1752                         data->smc_state_table.MemoryBootLevel = level;
1753                         break;
1754                 }
1755         }
1756
1757         return 0;
1758 }
1759
1760 static int polaris10_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
1761 {
1762         uint32_t ro, efuse, volt_without_cks, volt_with_cks, value, max, min;
1763         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1764         uint8_t i, stretch_amount, stretch_amount2, volt_offset = 0;
1765         struct phm_ppt_v1_information *table_info =
1766                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1767         struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
1768                         table_info->vdd_dep_on_sclk;
1769
1770         stretch_amount = (uint8_t)table_info->cac_dtp_table->usClockStretchAmount;
1771
1772         /* Read SMU_Eefuse to read and calculate RO and determine
1773          * if the part is SS or FF. if RO >= 1660MHz, part is FF.
1774          */
1775         efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1776                         ixSMU_EFUSE_0 + (67 * 4));
1777         efuse &= 0xFF000000;
1778         efuse = efuse >> 24;
1779
1780         if (hwmgr->chip_id == CHIP_POLARIS10) {
1781                 min = 1000;
1782                 max = 2300;
1783         } else {
1784                 min = 1100;
1785                 max = 2100;
1786         }
1787
1788         ro = efuse * (max -min)/255 + min;
1789
1790         /* Populate Sclk_CKS_masterEn0_7 and Sclk_voltageOffset */
1791         for (i = 0; i < sclk_table->count; i++) {
1792                 data->smc_state_table.Sclk_CKS_masterEn0_7 |=
1793                                 sclk_table->entries[i].cks_enable << i;
1794
1795                 volt_without_cks =  (uint32_t)(((ro - 40) * 1000 - 2753594 - sclk_table->entries[i].clk/100 * 136418 /1000) / \
1796                                         (sclk_table->entries[i].clk/100 * 1132925 /10000 - 242418)/100);
1797
1798                 volt_with_cks = (uint32_t)((ro * 1000 -2396351 - sclk_table->entries[i].clk/100 * 329021/1000) / \
1799                                 (sclk_table->entries[i].clk/10000 * 649434 /1000  - 18005)/10);
1800
1801                 if (volt_without_cks >= volt_with_cks)
1802                         volt_offset = (uint8_t)(((volt_without_cks - volt_with_cks +
1803                                         sclk_table->entries[i].cks_voffset) * 100 / 625) + 1);
1804
1805                 data->smc_state_table.Sclk_voltageOffset[i] = volt_offset;
1806         }
1807
1808         /* Populate CKS Lookup Table */
1809         if (stretch_amount == 1 || stretch_amount == 2 || stretch_amount == 5)
1810                 stretch_amount2 = 0;
1811         else if (stretch_amount == 3 || stretch_amount == 4)
1812                 stretch_amount2 = 1;
1813         else {
1814                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
1815                                 PHM_PlatformCaps_ClockStretcher);
1816                 PP_ASSERT_WITH_CODE(false,
1817                                 "Stretch Amount in PPTable not supported\n",
1818                                 return -EINVAL);
1819         }
1820
1821         value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL);
1822         value &= 0xFFFFFFFE;
1823         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL, value);
1824
1825         return 0;
1826 }
1827
1828 /**
1829 * Populates the SMC VRConfig field in DPM table.
1830 *
1831 * @param    hwmgr   the address of the hardware manager
1832 * @param    table   the SMC DPM table structure to be populated
1833 * @return   always 0
1834 */
1835 static int polaris10_populate_vr_config(struct pp_hwmgr *hwmgr,
1836                 struct SMU74_Discrete_DpmTable *table)
1837 {
1838         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1839         uint16_t config;
1840
1841         config = VR_MERGED_WITH_VDDC;
1842         table->VRConfig |= (config << VRCONF_VDDGFX_SHIFT);
1843
1844         /* Set Vddc Voltage Controller */
1845         if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
1846                 config = VR_SVI2_PLANE_1;
1847                 table->VRConfig |= config;
1848         } else {
1849                 PP_ASSERT_WITH_CODE(false,
1850                                 "VDDC should be on SVI2 control in merged mode!",
1851                                 );
1852         }
1853         /* Set Vddci Voltage Controller */
1854         if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
1855                 config = VR_SVI2_PLANE_2;  /* only in merged mode */
1856                 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1857         } else if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
1858                 config = VR_SMIO_PATTERN_1;
1859                 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1860         } else {
1861                 config = VR_STATIC_VOLTAGE;
1862                 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1863         }
1864         /* Set Mvdd Voltage Controller */
1865         if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
1866                 config = VR_SVI2_PLANE_2;
1867                 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
1868         } else if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
1869                 config = VR_SMIO_PATTERN_2;
1870                 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
1871         } else {
1872                 config = VR_STATIC_VOLTAGE;
1873                 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
1874         }
1875
1876         return 0;
1877 }
1878
1879
1880 int polaris10_populate_avfs_parameters(struct pp_hwmgr *hwmgr)
1881 {
1882         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1883         SMU74_Discrete_DpmTable  *table = &(data->smc_state_table);
1884         int result = 0;
1885         struct pp_atom_ctrl__avfs_parameters avfs_params = {0};
1886         AVFS_meanNsigma_t AVFS_meanNsigma = { {0} };
1887         AVFS_Sclk_Offset_t AVFS_SclkOffset = { {0} };
1888         uint32_t tmp, i;
1889         struct pp_smumgr *smumgr = hwmgr->smumgr;
1890         struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
1891
1892         struct phm_ppt_v1_information *table_info =
1893                         (struct phm_ppt_v1_information *)hwmgr->pptable;
1894         struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
1895                         table_info->vdd_dep_on_sclk;
1896
1897
1898         if (smu_data->avfs.avfs_btc_status == AVFS_BTC_NOTSUPPORTED)
1899                 return result;
1900
1901         result = atomctrl_get_avfs_information(hwmgr, &avfs_params);
1902
1903         if (0 == result) {
1904                 table->BTCGB_VDROOP_TABLE[0].a0  = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a0);
1905                 table->BTCGB_VDROOP_TABLE[0].a1  = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a1);
1906                 table->BTCGB_VDROOP_TABLE[0].a2  = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a2);
1907                 table->BTCGB_VDROOP_TABLE[1].a0  = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a0);
1908                 table->BTCGB_VDROOP_TABLE[1].a1  = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a1);
1909                 table->BTCGB_VDROOP_TABLE[1].a2  = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a2);
1910                 table->AVFSGB_VDROOP_TABLE[0].m1 = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_m1);
1911                 table->AVFSGB_VDROOP_TABLE[0].m2 = PP_HOST_TO_SMC_US(avfs_params.usAVFSGB_FUSE_TABLE_CKSON_m2);
1912                 table->AVFSGB_VDROOP_TABLE[0].b  = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_b);
1913                 table->AVFSGB_VDROOP_TABLE[0].m1_shift = 24;
1914                 table->AVFSGB_VDROOP_TABLE[0].m2_shift  = 12;
1915                 table->AVFSGB_VDROOP_TABLE[1].m1 = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_m1);
1916                 table->AVFSGB_VDROOP_TABLE[1].m2 = PP_HOST_TO_SMC_US(avfs_params.usAVFSGB_FUSE_TABLE_CKSOFF_m2);
1917                 table->AVFSGB_VDROOP_TABLE[1].b  = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_b);
1918                 table->AVFSGB_VDROOP_TABLE[1].m1_shift = 24;
1919                 table->AVFSGB_VDROOP_TABLE[1].m2_shift  = 12;
1920                 table->MaxVoltage                = PP_HOST_TO_SMC_US(avfs_params.usMaxVoltage_0_25mv);
1921                 AVFS_meanNsigma.Aconstant[0]      = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant0);
1922                 AVFS_meanNsigma.Aconstant[1]      = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant1);
1923                 AVFS_meanNsigma.Aconstant[2]      = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant2);
1924                 AVFS_meanNsigma.DC_tol_sigma      = PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_DC_tol_sigma);
1925                 AVFS_meanNsigma.Platform_mean     = PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_Platform_mean);
1926                 AVFS_meanNsigma.PSM_Age_CompFactor = PP_HOST_TO_SMC_US(avfs_params.usPSM_Age_ComFactor);
1927                 AVFS_meanNsigma.Platform_sigma     = PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_Platform_sigma);
1928
1929                 for (i = 0; i < NUM_VFT_COLUMNS; i++) {
1930                         AVFS_meanNsigma.Static_Voltage_Offset[i] = (uint8_t)(sclk_table->entries[i].cks_voffset * 100 / 625);
1931                         AVFS_SclkOffset.Sclk_Offset[i] = PP_HOST_TO_SMC_US((uint16_t)(sclk_table->entries[i].sclk_offset) / 100);
1932                 }
1933
1934                 result = polaris10_read_smc_sram_dword(smumgr,
1935                                 SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, AvfsMeanNSigma),
1936                                 &tmp, data->sram_end);
1937
1938                 polaris10_copy_bytes_to_smc(smumgr,
1939                                         tmp,
1940                                         (uint8_t *)&AVFS_meanNsigma,
1941                                         sizeof(AVFS_meanNsigma_t),
1942                                         data->sram_end);
1943
1944                 result = polaris10_read_smc_sram_dword(smumgr,
1945                                 SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, AvfsSclkOffsetTable),
1946                                 &tmp, data->sram_end);
1947                 polaris10_copy_bytes_to_smc(smumgr,
1948                                         tmp,
1949                                         (uint8_t *)&AVFS_SclkOffset,
1950                                         sizeof(AVFS_Sclk_Offset_t),
1951                                         data->sram_end);
1952
1953                 data->avfs_vdroop_override_setting = (avfs_params.ucEnableGB_VDROOP_TABLE_CKSON << BTCGB0_Vdroop_Enable_SHIFT) |
1954                                                 (avfs_params.ucEnableGB_VDROOP_TABLE_CKSOFF << BTCGB1_Vdroop_Enable_SHIFT) |
1955                                                 (avfs_params.ucEnableGB_FUSE_TABLE_CKSON << AVFSGB0_Vdroop_Enable_SHIFT) |
1956                                                 (avfs_params.ucEnableGB_FUSE_TABLE_CKSOFF << AVFSGB1_Vdroop_Enable_SHIFT);
1957                 data->apply_avfs_cks_off_voltage = (avfs_params.ucEnableApplyAVFS_CKS_OFF_Voltage == 1) ? true : false;
1958         }
1959         return result;
1960 }
1961
1962
1963 /**
1964 * Initializes the SMC table and uploads it
1965 *
1966 * @param    hwmgr  the address of the powerplay hardware manager.
1967 * @return   always 0
1968 */
1969 static int polaris10_init_smc_table(struct pp_hwmgr *hwmgr)
1970 {
1971         int result;
1972         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1973         struct phm_ppt_v1_information *table_info =
1974                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1975         struct SMU74_Discrete_DpmTable *table = &(data->smc_state_table);
1976         const struct polaris10_ulv_parm *ulv = &(data->ulv);
1977         uint8_t i;
1978         struct pp_atomctrl_gpio_pin_assignment gpio_pin;
1979         pp_atomctrl_clock_dividers_vi dividers;
1980
1981         result = polaris10_setup_default_dpm_tables(hwmgr);
1982         PP_ASSERT_WITH_CODE(0 == result,
1983                         "Failed to setup default DPM tables!", return result);
1984
1985         if (POLARIS10_VOLTAGE_CONTROL_NONE != data->voltage_control)
1986                 polaris10_populate_smc_voltage_tables(hwmgr, table);
1987
1988         table->SystemFlags = 0;
1989         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1990                         PHM_PlatformCaps_AutomaticDCTransition))
1991                 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
1992
1993         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1994                         PHM_PlatformCaps_StepVddc))
1995                 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
1996
1997         if (data->is_memory_gddr5)
1998                 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
1999
2000         if (ulv->ulv_supported && table_info->us_ulv_voltage_offset) {
2001                 result = polaris10_populate_ulv_state(hwmgr, table);
2002                 PP_ASSERT_WITH_CODE(0 == result,
2003                                 "Failed to initialize ULV state!", return result);
2004                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2005                                 ixCG_ULV_PARAMETER, PPPOLARIS10_CGULVPARAMETER_DFLT);
2006         }
2007
2008         result = polaris10_populate_smc_link_level(hwmgr, table);
2009         PP_ASSERT_WITH_CODE(0 == result,
2010                         "Failed to initialize Link Level!", return result);
2011
2012         result = polaris10_populate_all_graphic_levels(hwmgr);
2013         PP_ASSERT_WITH_CODE(0 == result,
2014                         "Failed to initialize Graphics Level!", return result);
2015
2016         result = polaris10_populate_all_memory_levels(hwmgr);
2017         PP_ASSERT_WITH_CODE(0 == result,
2018                         "Failed to initialize Memory Level!", return result);
2019
2020         result = polaris10_populate_smc_acpi_level(hwmgr, table);
2021         PP_ASSERT_WITH_CODE(0 == result,
2022                         "Failed to initialize ACPI Level!", return result);
2023
2024         result = polaris10_populate_smc_vce_level(hwmgr, table);
2025         PP_ASSERT_WITH_CODE(0 == result,
2026                         "Failed to initialize VCE Level!", return result);
2027
2028         result = polaris10_populate_smc_samu_level(hwmgr, table);
2029         PP_ASSERT_WITH_CODE(0 == result,
2030                         "Failed to initialize SAMU Level!", return result);
2031
2032         /* Since only the initial state is completely set up at this point
2033          * (the other states are just copies of the boot state) we only
2034          * need to populate the  ARB settings for the initial state.
2035          */
2036         result = polaris10_program_memory_timing_parameters(hwmgr);
2037         PP_ASSERT_WITH_CODE(0 == result,
2038                         "Failed to Write ARB settings for the initial state.", return result);
2039
2040         result = polaris10_populate_smc_uvd_level(hwmgr, table);
2041         PP_ASSERT_WITH_CODE(0 == result,
2042                         "Failed to initialize UVD Level!", return result);
2043
2044         result = polaris10_populate_smc_boot_level(hwmgr, table);
2045         PP_ASSERT_WITH_CODE(0 == result,
2046                         "Failed to initialize Boot Level!", return result);
2047
2048         result = polaris10_populate_smc_initailial_state(hwmgr);
2049         PP_ASSERT_WITH_CODE(0 == result,
2050                         "Failed to initialize Boot State!", return result);
2051
2052         result = polaris10_populate_bapm_parameters_in_dpm_table(hwmgr);
2053         PP_ASSERT_WITH_CODE(0 == result,
2054                         "Failed to populate BAPM Parameters!", return result);
2055
2056         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2057                         PHM_PlatformCaps_ClockStretcher)) {
2058                 result = polaris10_populate_clock_stretcher_data_table(hwmgr);
2059                 PP_ASSERT_WITH_CODE(0 == result,
2060                                 "Failed to populate Clock Stretcher Data Table!",
2061                                 return result);
2062         }
2063
2064         result = polaris10_populate_avfs_parameters(hwmgr);
2065         PP_ASSERT_WITH_CODE(0 == result, "Failed to populate AVFS Parameters!", return result;);
2066
2067         table->CurrSclkPllRange = 0xff;
2068         table->GraphicsVoltageChangeEnable  = 1;
2069         table->GraphicsThermThrottleEnable  = 1;
2070         table->GraphicsInterval = 1;
2071         table->VoltageInterval  = 1;
2072         table->ThermalInterval  = 1;
2073         table->TemperatureLimitHigh =
2074                         table_info->cac_dtp_table->usTargetOperatingTemp *
2075                         POLARIS10_Q88_FORMAT_CONVERSION_UNIT;
2076         table->TemperatureLimitLow  =
2077                         (table_info->cac_dtp_table->usTargetOperatingTemp - 1) *
2078                         POLARIS10_Q88_FORMAT_CONVERSION_UNIT;
2079         table->MemoryVoltageChangeEnable = 1;
2080         table->MemoryInterval = 1;
2081         table->VoltageResponseTime = 0;
2082         table->PhaseResponseTime = 0;
2083         table->MemoryThermThrottleEnable = 1;
2084         table->PCIeBootLinkLevel = 0;
2085         table->PCIeGenInterval = 1;
2086         table->VRConfig = 0;
2087
2088         result = polaris10_populate_vr_config(hwmgr, table);
2089         PP_ASSERT_WITH_CODE(0 == result,
2090                         "Failed to populate VRConfig setting!", return result);
2091
2092         table->ThermGpio = 17;
2093         table->SclkStepSize = 0x4000;
2094
2095         if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_VRHOT_GPIO_PINID, &gpio_pin)) {
2096                 table->VRHotGpio = gpio_pin.uc_gpio_pin_bit_shift;
2097         } else {
2098                 table->VRHotGpio = POLARIS10_UNUSED_GPIO_PIN;
2099                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2100                                 PHM_PlatformCaps_RegulatorHot);
2101         }
2102
2103         if (atomctrl_get_pp_assign_pin(hwmgr, PP_AC_DC_SWITCH_GPIO_PINID,
2104                         &gpio_pin)) {
2105                 table->AcDcGpio = gpio_pin.uc_gpio_pin_bit_shift;
2106                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2107                                 PHM_PlatformCaps_AutomaticDCTransition);
2108         } else {
2109                 table->AcDcGpio = POLARIS10_UNUSED_GPIO_PIN;
2110                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2111                                 PHM_PlatformCaps_AutomaticDCTransition);
2112         }
2113
2114         /* Thermal Output GPIO */
2115         if (atomctrl_get_pp_assign_pin(hwmgr, THERMAL_INT_OUTPUT_GPIO_PINID,
2116                         &gpio_pin)) {
2117                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2118                                 PHM_PlatformCaps_ThermalOutGPIO);
2119
2120                 table->ThermOutGpio = gpio_pin.uc_gpio_pin_bit_shift;
2121
2122                 /* For porlarity read GPIOPAD_A with assigned Gpio pin
2123                  * since VBIOS will program this register to set 'inactive state',
2124                  * driver can then determine 'active state' from this and
2125                  * program SMU with correct polarity
2126                  */
2127                 table->ThermOutPolarity = (0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A)
2128                                         & (1 << gpio_pin.uc_gpio_pin_bit_shift))) ? 1:0;
2129                 table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_ONLY;
2130
2131                 /* if required, combine VRHot/PCC with thermal out GPIO */
2132                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_RegulatorHot)
2133                 && phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_CombinePCCWithThermalSignal))
2134                         table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_VRHOT;
2135         } else {
2136                 table->ThermOutGpio = 17;
2137                 table->ThermOutPolarity = 1;
2138                 table->ThermOutMode = SMU7_THERM_OUT_MODE_DISABLE;
2139         }
2140
2141         /* Populate BIF_SCLK levels into SMC DPM table */
2142         for (i = 0; i <= data->dpm_table.pcie_speed_table.count; i++) {
2143                 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, data->bif_sclk_table[i], &dividers);
2144                 PP_ASSERT_WITH_CODE((result == 0), "Can not find DFS divide id for Sclk", return result);
2145
2146                 if (i == 0)
2147                         table->Ulv.BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider));
2148                 else
2149                         table->LinkLevel[i-1].BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider));
2150         }
2151
2152         for (i = 0; i < SMU74_MAX_ENTRIES_SMIO; i++)
2153                 table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]);
2154
2155         CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags);
2156         CONVERT_FROM_HOST_TO_SMC_UL(table->VRConfig);
2157         CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask1);
2158         CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask2);
2159         CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize);
2160         CONVERT_FROM_HOST_TO_SMC_UL(table->CurrSclkPllRange);
2161         CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh);
2162         CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow);
2163         CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime);
2164         CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);
2165
2166         /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
2167         result = polaris10_copy_bytes_to_smc(hwmgr->smumgr,
2168                         data->dpm_table_start +
2169                         offsetof(SMU74_Discrete_DpmTable, SystemFlags),
2170                         (uint8_t *)&(table->SystemFlags),
2171                         sizeof(SMU74_Discrete_DpmTable) - 3 * sizeof(SMU74_PIDController),
2172                         data->sram_end);
2173         PP_ASSERT_WITH_CODE(0 == result,
2174                         "Failed to upload dpm data to SMC memory!", return result);
2175
2176         return 0;
2177 }
2178
2179 /**
2180 * Initialize the ARB DRAM timing table's index field.
2181 *
2182 * @param    hwmgr  the address of the powerplay hardware manager.
2183 * @return   always 0
2184 */
2185 static int polaris10_init_arb_table_index(struct pp_hwmgr *hwmgr)
2186 {
2187         const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2188         uint32_t tmp;
2189         int result;
2190
2191         /* This is a read-modify-write on the first byte of the ARB table.
2192          * The first byte in the SMU73_Discrete_MCArbDramTimingTable structure
2193          * is the field 'current'.
2194          * This solution is ugly, but we never write the whole table only
2195          * individual fields in it.
2196          * In reality this field should not be in that structure
2197          * but in a soft register.
2198          */
2199         result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
2200                         data->arb_table_start, &tmp, data->sram_end);
2201
2202         if (result)
2203                 return result;
2204
2205         tmp &= 0x00FFFFFF;
2206         tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24;
2207
2208         return polaris10_write_smc_sram_dword(hwmgr->smumgr,
2209                         data->arb_table_start, tmp, data->sram_end);
2210 }
2211
2212 static int polaris10_enable_vrhot_gpio_interrupt(struct pp_hwmgr *hwmgr)
2213 {
2214         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2215                         PHM_PlatformCaps_RegulatorHot))
2216                 return smum_send_msg_to_smc(hwmgr->smumgr,
2217                                 PPSMC_MSG_EnableVRHotGPIOInterrupt);
2218
2219         return 0;
2220 }
2221
2222 static int polaris10_enable_sclk_control(struct pp_hwmgr *hwmgr)
2223 {
2224         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
2225                         SCLK_PWRMGT_OFF, 0);
2226         return 0;
2227 }
2228
2229 static int polaris10_enable_ulv(struct pp_hwmgr *hwmgr)
2230 {
2231         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2232         struct polaris10_ulv_parm *ulv = &(data->ulv);
2233
2234         if (ulv->ulv_supported)
2235                 return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_EnableULV);
2236
2237         return 0;
2238 }
2239
2240 static int polaris10_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
2241 {
2242         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2243                         PHM_PlatformCaps_SclkDeepSleep)) {
2244                 if (smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_MASTER_DeepSleep_ON))
2245                         PP_ASSERT_WITH_CODE(false,
2246                                         "Attempt to enable Master Deep Sleep switch failed!",
2247                                         return -1);
2248         } else {
2249                 if (smum_send_msg_to_smc(hwmgr->smumgr,
2250                                 PPSMC_MSG_MASTER_DeepSleep_OFF)) {
2251                         PP_ASSERT_WITH_CODE(false,
2252                                         "Attempt to disable Master Deep Sleep switch failed!",
2253                                         return -1);
2254                 }
2255         }
2256
2257         return 0;
2258 }
2259
2260 static int polaris10_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
2261 {
2262         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2263         uint32_t soft_register_value = 0;
2264         uint32_t handshake_disables_offset = data->soft_regs_start
2265                                 + offsetof(SMU74_SoftRegisters, HandshakeDisables);
2266
2267         /* enable SCLK dpm */
2268         if (!data->sclk_dpm_key_disabled)
2269                 PP_ASSERT_WITH_CODE(
2270                 (0 == smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_DPM_Enable)),
2271                 "Failed to enable SCLK DPM during DPM Start Function!",
2272                 return -1);
2273
2274         /* enable MCLK dpm */
2275         if (0 == data->mclk_dpm_key_disabled) {
2276 /* Disable UVD - SMU handshake for MCLK. */
2277                 soft_register_value = cgs_read_ind_register(hwmgr->device,
2278                                         CGS_IND_REG__SMC, handshake_disables_offset);
2279                 soft_register_value |= SMU7_UVD_MCLK_HANDSHAKE_DISABLE;
2280                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2281                                 handshake_disables_offset, soft_register_value);
2282
2283                 PP_ASSERT_WITH_CODE(
2284                                 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
2285                                                 PPSMC_MSG_MCLKDPM_Enable)),
2286                                 "Failed to enable MCLK DPM during DPM Start Function!",
2287                                 return -1);
2288
2289                 PHM_WRITE_FIELD(hwmgr->device, MC_SEQ_CNTL_3, CAC_EN, 0x1);
2290
2291                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x5);
2292                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x5);
2293                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x100005);
2294                 udelay(10);
2295                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x400005);
2296                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x400005);
2297                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x500005);
2298         }
2299
2300         return 0;
2301 }
2302
2303 static int polaris10_start_dpm(struct pp_hwmgr *hwmgr)
2304 {
2305         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2306
2307         /*enable general power management */
2308
2309         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
2310                         GLOBAL_PWRMGT_EN, 1);
2311
2312         /* enable sclk deep sleep */
2313
2314         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
2315                         DYNAMIC_PM_EN, 1);
2316
2317         /* prepare for PCIE DPM */
2318
2319         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2320                         data->soft_regs_start + offsetof(SMU74_SoftRegisters,
2321                                         VoltageChangeTimeout), 0x1000);
2322         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
2323                         SWRST_COMMAND_1, RESETLC, 0x0);
2324 /*
2325         PP_ASSERT_WITH_CODE(
2326                         (0 == smum_send_msg_to_smc(hwmgr->smumgr,
2327                                         PPSMC_MSG_Voltage_Cntl_Enable)),
2328                         "Failed to enable voltage DPM during DPM Start Function!",
2329                         return -1);
2330 */
2331
2332         if (polaris10_enable_sclk_mclk_dpm(hwmgr)) {
2333                 printk(KERN_ERR "Failed to enable Sclk DPM and Mclk DPM!");
2334                 return -1;
2335         }
2336
2337         /* enable PCIE dpm */
2338         if (0 == data->pcie_dpm_key_disabled) {
2339                 PP_ASSERT_WITH_CODE(
2340                                 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
2341                                                 PPSMC_MSG_PCIeDPM_Enable)),
2342                                 "Failed to enable pcie DPM during DPM Start Function!",
2343                                 return -1);
2344         }
2345
2346         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2347                                 PHM_PlatformCaps_Falcon_QuickTransition)) {
2348                 PP_ASSERT_WITH_CODE((0 == smum_send_msg_to_smc(hwmgr->smumgr,
2349                                 PPSMC_MSG_EnableACDCGPIOInterrupt)),
2350                                 "Failed to enable AC DC GPIO Interrupt!",
2351                                 );
2352         }
2353
2354         return 0;
2355 }
2356
2357 static void polaris10_set_dpm_event_sources(struct pp_hwmgr *hwmgr, uint32_t sources)
2358 {
2359         bool protection;
2360         enum DPM_EVENT_SRC src;
2361
2362         switch (sources) {
2363         default:
2364                 printk(KERN_ERR "Unknown throttling event sources.");
2365                 /* fall through */
2366         case 0:
2367                 protection = false;
2368                 /* src is unused */
2369                 break;
2370         case (1 << PHM_AutoThrottleSource_Thermal):
2371                 protection = true;
2372                 src = DPM_EVENT_SRC_DIGITAL;
2373                 break;
2374         case (1 << PHM_AutoThrottleSource_External):
2375                 protection = true;
2376                 src = DPM_EVENT_SRC_EXTERNAL;
2377                 break;
2378         case (1 << PHM_AutoThrottleSource_External) |
2379                         (1 << PHM_AutoThrottleSource_Thermal):
2380                 protection = true;
2381                 src = DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL;
2382                 break;
2383         }
2384         /* Order matters - don't enable thermal protection for the wrong source. */
2385         if (protection) {
2386                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_THERMAL_CTRL,
2387                                 DPM_EVENT_SRC, src);
2388                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
2389                                 THERMAL_PROTECTION_DIS,
2390                                 !phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2391                                                 PHM_PlatformCaps_ThermalController));
2392         } else
2393                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
2394                                 THERMAL_PROTECTION_DIS, 1);
2395 }
2396
2397 static int polaris10_enable_auto_throttle_source(struct pp_hwmgr *hwmgr,
2398                 PHM_AutoThrottleSource source)
2399 {
2400         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2401
2402         if (!(data->active_auto_throttle_sources & (1 << source))) {
2403                 data->active_auto_throttle_sources |= 1 << source;
2404                 polaris10_set_dpm_event_sources(hwmgr, data->active_auto_throttle_sources);
2405         }
2406         return 0;
2407 }
2408
2409 static int polaris10_enable_thermal_auto_throttle(struct pp_hwmgr *hwmgr)
2410 {
2411         return polaris10_enable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal);
2412 }
2413
2414 int polaris10_pcie_performance_request(struct pp_hwmgr *hwmgr)
2415 {
2416         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2417         data->pcie_performance_request = true;
2418
2419         return 0;
2420 }
2421
2422 int polaris10_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
2423 {
2424         int tmp_result, result = 0;
2425         tmp_result = (!polaris10_is_dpm_running(hwmgr)) ? 0 : -1;
2426         PP_ASSERT_WITH_CODE(result == 0,
2427                         "DPM is already running right now, no need to enable DPM!",
2428                         return 0);
2429
2430         if (polaris10_voltage_control(hwmgr)) {
2431                 tmp_result = polaris10_enable_voltage_control(hwmgr);
2432                 PP_ASSERT_WITH_CODE(tmp_result == 0,
2433                                 "Failed to enable voltage control!",
2434                                 result = tmp_result);
2435
2436                 tmp_result = polaris10_construct_voltage_tables(hwmgr);
2437                 PP_ASSERT_WITH_CODE((0 == tmp_result),
2438                                 "Failed to contruct voltage tables!",
2439                                 result = tmp_result);
2440         }
2441
2442         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2443                         PHM_PlatformCaps_EngineSpreadSpectrumSupport))
2444                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
2445                                 GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, 1);
2446
2447         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2448                         PHM_PlatformCaps_ThermalController))
2449                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
2450                                 GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, 0);
2451
2452         tmp_result = polaris10_program_static_screen_threshold_parameters(hwmgr);
2453         PP_ASSERT_WITH_CODE((0 == tmp_result),
2454                         "Failed to program static screen threshold parameters!",
2455                         result = tmp_result);
2456
2457         tmp_result = polaris10_enable_display_gap(hwmgr);
2458         PP_ASSERT_WITH_CODE((0 == tmp_result),
2459                         "Failed to enable display gap!", result = tmp_result);
2460
2461         tmp_result = polaris10_program_voting_clients(hwmgr);
2462         PP_ASSERT_WITH_CODE((0 == tmp_result),
2463                         "Failed to program voting clients!", result = tmp_result);
2464
2465         tmp_result = polaris10_process_firmware_header(hwmgr);
2466         PP_ASSERT_WITH_CODE((0 == tmp_result),
2467                         "Failed to process firmware header!", result = tmp_result);
2468
2469         tmp_result = polaris10_initial_switch_from_arbf0_to_f1(hwmgr);
2470         PP_ASSERT_WITH_CODE((0 == tmp_result),
2471                         "Failed to initialize switch from ArbF0 to F1!",
2472                         result = tmp_result);
2473
2474         tmp_result = polaris10_init_smc_table(hwmgr);
2475         PP_ASSERT_WITH_CODE((0 == tmp_result),
2476                         "Failed to initialize SMC table!", result = tmp_result);
2477
2478         tmp_result = polaris10_init_arb_table_index(hwmgr);
2479         PP_ASSERT_WITH_CODE((0 == tmp_result),
2480                         "Failed to initialize ARB table index!", result = tmp_result);
2481
2482         tmp_result = polaris10_populate_pm_fuses(hwmgr);
2483         PP_ASSERT_WITH_CODE((0 == tmp_result),
2484                         "Failed to populate PM fuses!", result = tmp_result);
2485
2486         tmp_result = polaris10_enable_vrhot_gpio_interrupt(hwmgr);
2487         PP_ASSERT_WITH_CODE((0 == tmp_result),
2488                         "Failed to enable VR hot GPIO interrupt!", result = tmp_result);
2489
2490         tmp_result = polaris10_enable_sclk_control(hwmgr);
2491         PP_ASSERT_WITH_CODE((0 == tmp_result),
2492                         "Failed to enable SCLK control!", result = tmp_result);
2493
2494         tmp_result = polaris10_enable_smc_voltage_controller(hwmgr);
2495         PP_ASSERT_WITH_CODE((0 == tmp_result),
2496                         "Failed to enable voltage control!", result = tmp_result);
2497
2498         tmp_result = polaris10_enable_ulv(hwmgr);
2499         PP_ASSERT_WITH_CODE((0 == tmp_result),
2500                         "Failed to enable ULV!", result = tmp_result);
2501
2502         tmp_result = polaris10_enable_deep_sleep_master_switch(hwmgr);
2503         PP_ASSERT_WITH_CODE((0 == tmp_result),
2504                         "Failed to enable deep sleep master switch!", result = tmp_result);
2505
2506         tmp_result = polaris10_start_dpm(hwmgr);
2507         PP_ASSERT_WITH_CODE((0 == tmp_result),
2508                         "Failed to start DPM!", result = tmp_result);
2509
2510         tmp_result = polaris10_enable_smc_cac(hwmgr);
2511         PP_ASSERT_WITH_CODE((0 == tmp_result),
2512                         "Failed to enable SMC CAC!", result = tmp_result);
2513
2514         tmp_result = polaris10_enable_power_containment(hwmgr);
2515         PP_ASSERT_WITH_CODE((0 == tmp_result),
2516                         "Failed to enable power containment!", result = tmp_result);
2517
2518         tmp_result = polaris10_power_control_set_level(hwmgr);
2519         PP_ASSERT_WITH_CODE((0 == tmp_result),
2520                         "Failed to power control set level!", result = tmp_result);
2521
2522         tmp_result = polaris10_enable_thermal_auto_throttle(hwmgr);
2523         PP_ASSERT_WITH_CODE((0 == tmp_result),
2524                         "Failed to enable thermal auto throttle!", result = tmp_result);
2525
2526         tmp_result = polaris10_pcie_performance_request(hwmgr);
2527         PP_ASSERT_WITH_CODE((0 == tmp_result),
2528                         "pcie performance request failed!", result = tmp_result);
2529
2530         return result;
2531 }
2532
2533 int polaris10_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
2534 {
2535
2536         return 0;
2537 }
2538
2539 int polaris10_reset_asic_tasks(struct pp_hwmgr *hwmgr)
2540 {
2541
2542         return 0;
2543 }
2544
2545 int polaris10_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
2546 {
2547         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2548
2549         if (data->soft_pp_table) {
2550                 kfree(data->soft_pp_table);
2551                 data->soft_pp_table = NULL;
2552         }
2553
2554         return phm_hwmgr_backend_fini(hwmgr);
2555 }
2556
2557 int polaris10_set_features_platform_caps(struct pp_hwmgr *hwmgr)
2558 {
2559         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2560
2561         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2562                         PHM_PlatformCaps_SclkDeepSleep);
2563
2564         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2565                 PHM_PlatformCaps_DynamicPatchPowerState);
2566
2567         if (data->mvdd_control == POLARIS10_VOLTAGE_CONTROL_NONE)
2568                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2569                                 PHM_PlatformCaps_EnableMVDDControl);
2570
2571         if (data->vddci_control == POLARIS10_VOLTAGE_CONTROL_NONE)
2572                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2573                                 PHM_PlatformCaps_ControlVDDCI);
2574
2575         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2576                          PHM_PlatformCaps_TablelessHardwareInterface);
2577
2578         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2579                         PHM_PlatformCaps_EnableSMU7ThermalManagement);
2580
2581         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2582                         PHM_PlatformCaps_DynamicPowerManagement);
2583
2584         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2585                         PHM_PlatformCaps_UnTabledHardwareInterface);
2586
2587         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2588                         PHM_PlatformCaps_TablelessHardwareInterface);
2589
2590         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2591                                         PHM_PlatformCaps_SMC);
2592
2593         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2594                                         PHM_PlatformCaps_NonABMSupportInPPLib);
2595
2596         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2597                                         PHM_PlatformCaps_DynamicUVDState);
2598
2599         /* power tune caps Assume disabled */
2600         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2601                                                 PHM_PlatformCaps_SQRamping);
2602         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2603                                                 PHM_PlatformCaps_DBRamping);
2604         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2605                                                 PHM_PlatformCaps_TDRamping);
2606         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2607                                                 PHM_PlatformCaps_TCPRamping);
2608
2609         if (hwmgr->powercontainment_enabled)
2610                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2611                             PHM_PlatformCaps_PowerContainment);
2612         else
2613                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2614                             PHM_PlatformCaps_PowerContainment);
2615
2616         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2617                                                         PHM_PlatformCaps_CAC);
2618
2619         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2620                                                 PHM_PlatformCaps_RegulatorHot);
2621
2622         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2623                                                 PHM_PlatformCaps_AutomaticDCTransition);
2624
2625         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2626                                                 PHM_PlatformCaps_ODFuzzyFanControlSupport);
2627
2628         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2629                                                 PHM_PlatformCaps_FanSpeedInTableIsRPM);
2630
2631         if (hwmgr->chip_id == CHIP_POLARIS11)
2632                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2633                                         PHM_PlatformCaps_SPLLShutdownSupport);
2634         return 0;
2635 }
2636
2637 static void polaris10_init_dpm_defaults(struct pp_hwmgr *hwmgr)
2638 {
2639         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2640
2641         polaris10_initialize_power_tune_defaults(hwmgr);
2642
2643         data->pcie_gen_performance.max = PP_PCIEGen1;
2644         data->pcie_gen_performance.min = PP_PCIEGen3;
2645         data->pcie_gen_power_saving.max = PP_PCIEGen1;
2646         data->pcie_gen_power_saving.min = PP_PCIEGen3;
2647         data->pcie_lane_performance.max = 0;
2648         data->pcie_lane_performance.min = 16;
2649         data->pcie_lane_power_saving.max = 0;
2650         data->pcie_lane_power_saving.min = 16;
2651 }
2652
2653 /**
2654 * Get Leakage VDDC based on leakage ID.
2655 *
2656 * @param    hwmgr  the address of the powerplay hardware manager.
2657 * @return   always 0
2658 */
2659 static int polaris10_get_evv_voltages(struct pp_hwmgr *hwmgr)
2660 {
2661         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2662         uint16_t vv_id;
2663         uint16_t vddc = 0;
2664         uint16_t i, j;
2665         uint32_t sclk = 0;
2666         struct phm_ppt_v1_information *table_info =
2667                         (struct phm_ppt_v1_information *)hwmgr->pptable;
2668         struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
2669                         table_info->vdd_dep_on_sclk;
2670         int result;
2671
2672         for (i = 0; i < POLARIS10_MAX_LEAKAGE_COUNT; i++) {
2673                 vv_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
2674                 if (!phm_get_sclk_for_voltage_evv(hwmgr,
2675                                 table_info->vddc_lookup_table, vv_id, &sclk)) {
2676                         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2677                                         PHM_PlatformCaps_ClockStretcher)) {
2678                                 for (j = 1; j < sclk_table->count; j++) {
2679                                         if (sclk_table->entries[j].clk == sclk &&
2680                                                         sclk_table->entries[j].cks_enable == 0) {
2681                                                 sclk += 5000;
2682                                                 break;
2683                                         }
2684                                 }
2685                         }
2686
2687
2688                         PP_ASSERT_WITH_CODE(0 == atomctrl_get_voltage_evv_on_sclk_ai(hwmgr,
2689                                                         VOLTAGE_TYPE_VDDC, sclk, vv_id, &vddc),
2690                                                 "Error retrieving EVV voltage value!",
2691                                                 continue);
2692
2693
2694                         /* need to make sure vddc is less than 2v or else, it could burn the ASIC. */
2695                         PP_ASSERT_WITH_CODE((vddc < 2000 && vddc != 0),
2696                                         "Invalid VDDC value", result = -EINVAL;);
2697
2698                         /* the voltage should not be zero nor equal to leakage ID */
2699                         if (vddc != 0 && vddc != vv_id) {
2700                                 data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = (uint16_t)(vddc/100);
2701                                 data->vddc_leakage.leakage_id[data->vddc_leakage.count] = vv_id;
2702                                 data->vddc_leakage.count++;
2703                         }
2704                 }
2705         }
2706
2707         return 0;
2708 }
2709
2710 /**
2711  * Change virtual leakage voltage to actual value.
2712  *
2713  * @param     hwmgr  the address of the powerplay hardware manager.
2714  * @param     pointer to changing voltage
2715  * @param     pointer to leakage table
2716  */
2717 static void polaris10_patch_with_vdd_leakage(struct pp_hwmgr *hwmgr,
2718                 uint16_t *voltage, struct polaris10_leakage_voltage *leakage_table)
2719 {
2720         uint32_t index;
2721
2722         /* search for leakage voltage ID 0xff01 ~ 0xff08 */
2723         for (index = 0; index < leakage_table->count; index++) {
2724                 /* if this voltage matches a leakage voltage ID */
2725                 /* patch with actual leakage voltage */
2726                 if (leakage_table->leakage_id[index] == *voltage) {
2727                         *voltage = leakage_table->actual_voltage[index];
2728                         break;
2729                 }
2730         }
2731
2732         if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0)
2733                 printk(KERN_ERR "Voltage value looks like a Leakage ID but it's not patched \n");
2734 }
2735
2736 /**
2737 * Patch voltage lookup table by EVV leakages.
2738 *
2739 * @param     hwmgr  the address of the powerplay hardware manager.
2740 * @param     pointer to voltage lookup table
2741 * @param     pointer to leakage table
2742 * @return     always 0
2743 */
2744 static int polaris10_patch_lookup_table_with_leakage(struct pp_hwmgr *hwmgr,
2745                 phm_ppt_v1_voltage_lookup_table *lookup_table,
2746                 struct polaris10_leakage_voltage *leakage_table)
2747 {
2748         uint32_t i;
2749
2750         for (i = 0; i < lookup_table->count; i++)
2751                 polaris10_patch_with_vdd_leakage(hwmgr,
2752                                 &lookup_table->entries[i].us_vdd, leakage_table);
2753
2754         return 0;
2755 }
2756
2757 static int polaris10_patch_clock_voltage_limits_with_vddc_leakage(
2758                 struct pp_hwmgr *hwmgr, struct polaris10_leakage_voltage *leakage_table,
2759                 uint16_t *vddc)
2760 {
2761         struct phm_ppt_v1_information *table_info =
2762                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2763         polaris10_patch_with_vdd_leakage(hwmgr, (uint16_t *)vddc, leakage_table);
2764         hwmgr->dyn_state.max_clock_voltage_on_dc.vddc =
2765                         table_info->max_clock_voltage_on_dc.vddc;
2766         return 0;
2767 }
2768
2769 static int polaris10_patch_voltage_dependency_tables_with_lookup_table(
2770                 struct pp_hwmgr *hwmgr)
2771 {
2772         uint8_t entryId;
2773         uint8_t voltageId;
2774         struct phm_ppt_v1_information *table_info =
2775                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2776
2777         struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
2778                         table_info->vdd_dep_on_sclk;
2779         struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table =
2780                         table_info->vdd_dep_on_mclk;
2781         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
2782                         table_info->mm_dep_table;
2783
2784         for (entryId = 0; entryId < sclk_table->count; ++entryId) {
2785                 voltageId = sclk_table->entries[entryId].vddInd;
2786                 sclk_table->entries[entryId].vddc =
2787                                 table_info->vddc_lookup_table->entries[voltageId].us_vdd;
2788         }
2789
2790         for (entryId = 0; entryId < mclk_table->count; ++entryId) {
2791                 voltageId = mclk_table->entries[entryId].vddInd;
2792                 mclk_table->entries[entryId].vddc =
2793                         table_info->vddc_lookup_table->entries[voltageId].us_vdd;
2794         }
2795
2796         for (entryId = 0; entryId < mm_table->count; ++entryId) {
2797                 voltageId = mm_table->entries[entryId].vddcInd;
2798                 mm_table->entries[entryId].vddc =
2799                         table_info->vddc_lookup_table->entries[voltageId].us_vdd;
2800         }
2801
2802         return 0;
2803
2804 }
2805
2806 static int polaris10_calc_voltage_dependency_tables(struct pp_hwmgr *hwmgr)
2807 {
2808         /* Need to determine if we need calculated voltage. */
2809         return 0;
2810 }
2811
2812 static int polaris10_calc_mm_voltage_dependency_table(struct pp_hwmgr *hwmgr)
2813 {
2814         /* Need to determine if we need calculated voltage from mm table. */
2815         return 0;
2816 }
2817
2818 static int polaris10_sort_lookup_table(struct pp_hwmgr *hwmgr,
2819                 struct phm_ppt_v1_voltage_lookup_table *lookup_table)
2820 {
2821         uint32_t table_size, i, j;
2822         struct phm_ppt_v1_voltage_lookup_record tmp_voltage_lookup_record;
2823         table_size = lookup_table->count;
2824
2825         PP_ASSERT_WITH_CODE(0 != lookup_table->count,
2826                 "Lookup table is empty", return -EINVAL);
2827
2828         /* Sorting voltages */
2829         for (i = 0; i < table_size - 1; i++) {
2830                 for (j = i + 1; j > 0; j--) {
2831                         if (lookup_table->entries[j].us_vdd <
2832                                         lookup_table->entries[j - 1].us_vdd) {
2833                                 tmp_voltage_lookup_record = lookup_table->entries[j - 1];
2834                                 lookup_table->entries[j - 1] = lookup_table->entries[j];
2835                                 lookup_table->entries[j] = tmp_voltage_lookup_record;
2836                         }
2837                 }
2838         }
2839
2840         return 0;
2841 }
2842
2843 static int polaris10_complete_dependency_tables(struct pp_hwmgr *hwmgr)
2844 {
2845         int result = 0;
2846         int tmp_result;
2847         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2848         struct phm_ppt_v1_information *table_info =
2849                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2850
2851         tmp_result = polaris10_patch_lookup_table_with_leakage(hwmgr,
2852                         table_info->vddc_lookup_table, &(data->vddc_leakage));
2853         if (tmp_result)
2854                 result = tmp_result;
2855
2856         tmp_result = polaris10_patch_clock_voltage_limits_with_vddc_leakage(hwmgr,
2857                         &(data->vddc_leakage), &table_info->max_clock_voltage_on_dc.vddc);
2858         if (tmp_result)
2859                 result = tmp_result;
2860
2861         tmp_result = polaris10_patch_voltage_dependency_tables_with_lookup_table(hwmgr);
2862         if (tmp_result)
2863                 result = tmp_result;
2864
2865         tmp_result = polaris10_calc_voltage_dependency_tables(hwmgr);
2866         if (tmp_result)
2867                 result = tmp_result;
2868
2869         tmp_result = polaris10_calc_mm_voltage_dependency_table(hwmgr);
2870         if (tmp_result)
2871                 result = tmp_result;
2872
2873         tmp_result = polaris10_sort_lookup_table(hwmgr, table_info->vddc_lookup_table);
2874         if (tmp_result)
2875                 result = tmp_result;
2876
2877         return result;
2878 }
2879
2880 static int polaris10_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr)
2881 {
2882         struct phm_ppt_v1_information *table_info =
2883                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2884
2885         struct phm_ppt_v1_clock_voltage_dependency_table *allowed_sclk_vdd_table =
2886                                                 table_info->vdd_dep_on_sclk;
2887         struct phm_ppt_v1_clock_voltage_dependency_table *allowed_mclk_vdd_table =
2888                                                 table_info->vdd_dep_on_mclk;
2889
2890         PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table != NULL,
2891                 "VDD dependency on SCLK table is missing.       \
2892                 This table is mandatory", return -EINVAL);
2893         PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1,
2894                 "VDD dependency on SCLK table has to have is missing.   \
2895                 This table is mandatory", return -EINVAL);
2896
2897         PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table != NULL,
2898                 "VDD dependency on MCLK table is missing.       \
2899                 This table is mandatory", return -EINVAL);
2900         PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1,
2901                 "VDD dependency on MCLK table has to have is missing.    \
2902                 This table is mandatory", return -EINVAL);
2903
2904         table_info->max_clock_voltage_on_ac.sclk =
2905                 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].clk;
2906         table_info->max_clock_voltage_on_ac.mclk =
2907                 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk;
2908         table_info->max_clock_voltage_on_ac.vddc =
2909                 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc;
2910         table_info->max_clock_voltage_on_ac.vddci =
2911                 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci;
2912
2913         hwmgr->dyn_state.max_clock_voltage_on_ac.sclk = table_info->max_clock_voltage_on_ac.sclk;
2914         hwmgr->dyn_state.max_clock_voltage_on_ac.mclk = table_info->max_clock_voltage_on_ac.mclk;
2915         hwmgr->dyn_state.max_clock_voltage_on_ac.vddc = table_info->max_clock_voltage_on_ac.vddc;
2916         hwmgr->dyn_state.max_clock_voltage_on_ac.vddci =table_info->max_clock_voltage_on_ac.vddci;
2917
2918         return 0;
2919 }
2920
2921 int polaris10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
2922 {
2923         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2924         struct pp_atomctrl_gpio_pin_assignment gpio_pin_assignment;
2925         uint32_t temp_reg;
2926         int result;
2927         struct phm_ppt_v1_information *table_info =
2928                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2929
2930         data->dll_default_on = false;
2931         data->sram_end = SMC_RAM_END;
2932         data->mclk_dpm0_activity_target = 0xa;
2933         data->disable_dpm_mask = 0xFF;
2934         data->static_screen_threshold = PPPOLARIS10_STATICSCREENTHRESHOLD_DFLT;
2935         data->static_screen_threshold_unit = PPPOLARIS10_STATICSCREENTHRESHOLD_DFLT;
2936         data->activity_target[0] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2937         data->activity_target[1] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2938         data->activity_target[2] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2939         data->activity_target[3] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2940         data->activity_target[4] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2941         data->activity_target[5] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2942         data->activity_target[6] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2943         data->activity_target[7] = PPPOLARIS10_TARGETACTIVITY_DFLT;
2944
2945         data->voting_rights_clients0 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT0;
2946         data->voting_rights_clients1 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT1;
2947         data->voting_rights_clients2 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT2;
2948         data->voting_rights_clients3 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT3;
2949         data->voting_rights_clients4 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT4;
2950         data->voting_rights_clients5 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT5;
2951         data->voting_rights_clients6 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT6;
2952         data->voting_rights_clients7 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT7;
2953
2954         data->vddc_vddci_delta = VDDC_VDDCI_DELTA;
2955
2956         data->mclk_activity_target = PPPOLARIS10_MCLK_TARGETACTIVITY_DFLT;
2957
2958         /* need to set voltage control types before EVV patching */
2959         data->voltage_control = POLARIS10_VOLTAGE_CONTROL_NONE;
2960         data->vddci_control = POLARIS10_VOLTAGE_CONTROL_NONE;
2961         data->mvdd_control = POLARIS10_VOLTAGE_CONTROL_NONE;
2962
2963         data->enable_tdc_limit_feature = true;
2964         data->enable_pkg_pwr_tracking_feature = true;
2965         data->force_pcie_gen = PP_PCIEGenInvalid;
2966         data->mclk_stutter_mode_threshold = 40000;
2967
2968         if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
2969                         VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2))
2970                 data->voltage_control = POLARIS10_VOLTAGE_CONTROL_BY_SVID2;
2971
2972         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2973                         PHM_PlatformCaps_EnableMVDDControl)) {
2974                 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
2975                                 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT))
2976                         data->mvdd_control = POLARIS10_VOLTAGE_CONTROL_BY_GPIO;
2977                 else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
2978                                 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2))
2979                         data->mvdd_control = POLARIS10_VOLTAGE_CONTROL_BY_SVID2;
2980         }
2981
2982         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2983                         PHM_PlatformCaps_ControlVDDCI)) {
2984                 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
2985                                 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
2986                         data->vddci_control = POLARIS10_VOLTAGE_CONTROL_BY_GPIO;
2987                 else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
2988                                 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2))
2989                         data->vddci_control = POLARIS10_VOLTAGE_CONTROL_BY_SVID2;
2990         }
2991
2992         if (table_info->cac_dtp_table->usClockStretchAmount != 0)
2993                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2994                                         PHM_PlatformCaps_ClockStretcher);
2995
2996         polaris10_set_features_platform_caps(hwmgr);
2997
2998         polaris10_init_dpm_defaults(hwmgr);
2999
3000         /* Get leakage voltage based on leakage ID. */
3001         result = polaris10_get_evv_voltages(hwmgr);
3002
3003         if (result) {
3004                 printk("Get EVV Voltage Failed.  Abort Driver loading!\n");
3005                 return -1;
3006         }
3007
3008         polaris10_complete_dependency_tables(hwmgr);
3009         polaris10_set_private_data_based_on_pptable(hwmgr);
3010
3011         /* Initalize Dynamic State Adjustment Rule Settings */
3012         result = phm_initializa_dynamic_state_adjustment_rule_settings(hwmgr);
3013
3014         if (0 == result) {
3015                 struct cgs_system_info sys_info = {0};
3016
3017                 data->is_tlu_enabled = 0;
3018
3019                 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
3020                                                         POLARIS10_MAX_HARDWARE_POWERLEVELS;
3021                 hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
3022                 hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
3023
3024
3025                 if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_PCC_GPIO_PINID, &gpio_pin_assignment)) {
3026                         temp_reg = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL);
3027                         switch (gpio_pin_assignment.uc_gpio_pin_bit_shift) {
3028                         case 0:
3029                                 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x1);
3030                                 break;
3031                         case 1:
3032                                 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x2);
3033                                 break;
3034                         case 2:
3035                                 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW, 0x1);
3036                                 break;
3037                         case 3:
3038                                 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, FORCE_NB_PS1, 0x1);
3039                                 break;
3040                         case 4:
3041                                 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, DPM_ENABLED, 0x1);
3042                                 break;
3043                         default:
3044                                 PP_ASSERT_WITH_CODE(0,
3045                                 "Failed to setup PCC HW register! Wrong GPIO assigned for VDDC_PCC_GPIO_PINID!",
3046                                 );
3047                                 break;
3048                         }
3049                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL, temp_reg);
3050                 }
3051
3052                 if (table_info->cac_dtp_table->usDefaultTargetOperatingTemp != 0 &&
3053                         hwmgr->thermal_controller.advanceFanControlParameters.ucFanControlMode) {
3054                         hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMinLimit =
3055                                 (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit;
3056
3057                         hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMaxLimit =
3058                                 (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM;
3059
3060                         hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMStep = 1;
3061
3062                         hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMaxLimit = 100;
3063
3064                         hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMinLimit =
3065                                 (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit;
3066
3067                         hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMStep = 1;
3068
3069                         table_info->cac_dtp_table->usDefaultTargetOperatingTemp = (table_info->cac_dtp_table->usDefaultTargetOperatingTemp >= 50) ?
3070                                                                         (table_info->cac_dtp_table->usDefaultTargetOperatingTemp -50) : 0;
3071
3072                         table_info->cac_dtp_table->usOperatingTempMaxLimit = table_info->cac_dtp_table->usDefaultTargetOperatingTemp;
3073                         table_info->cac_dtp_table->usOperatingTempStep = 1;
3074                         table_info->cac_dtp_table->usOperatingTempHyst = 1;
3075
3076                         hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanPWM =
3077                                        hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM;
3078
3079                         hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM =
3080                                        hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanRPM;
3081
3082                         hwmgr->dyn_state.cac_dtp_table->usOperatingTempMinLimit =
3083                                        table_info->cac_dtp_table->usOperatingTempMinLimit;
3084
3085                         hwmgr->dyn_state.cac_dtp_table->usOperatingTempMaxLimit =
3086                                        table_info->cac_dtp_table->usOperatingTempMaxLimit;
3087
3088                         hwmgr->dyn_state.cac_dtp_table->usDefaultTargetOperatingTemp =
3089                                        table_info->cac_dtp_table->usDefaultTargetOperatingTemp;
3090
3091                         hwmgr->dyn_state.cac_dtp_table->usOperatingTempStep =
3092                                        table_info->cac_dtp_table->usOperatingTempStep;
3093
3094                         hwmgr->dyn_state.cac_dtp_table->usTargetOperatingTemp =
3095                                        table_info->cac_dtp_table->usTargetOperatingTemp;
3096                 }
3097
3098                 sys_info.size = sizeof(struct cgs_system_info);
3099                 sys_info.info_id = CGS_SYSTEM_INFO_PCIE_GEN_INFO;
3100                 result = cgs_query_system_info(hwmgr->device, &sys_info);
3101                 if (result)
3102                         data->pcie_gen_cap = 0x30007;
3103                 else
3104                         data->pcie_gen_cap = (uint32_t)sys_info.value;
3105                 if (data->pcie_gen_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
3106                         data->pcie_spc_cap = 20;
3107                 sys_info.size = sizeof(struct cgs_system_info);
3108                 sys_info.info_id = CGS_SYSTEM_INFO_PCIE_MLW;
3109                 result = cgs_query_system_info(hwmgr->device, &sys_info);
3110                 if (result)
3111                         data->pcie_lane_cap = 0x2f0000;
3112                 else
3113                         data->pcie_lane_cap = (uint32_t)sys_info.value;
3114
3115                 hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */
3116 /* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */
3117                 hwmgr->platform_descriptor.clockStep.engineClock = 500;
3118                 hwmgr->platform_descriptor.clockStep.memoryClock = 500;
3119         } else {
3120                 /* Ignore return value in here, we are cleaning up a mess. */
3121                 polaris10_hwmgr_backend_fini(hwmgr);
3122         }
3123
3124         return 0;
3125 }
3126
3127 static int polaris10_force_dpm_highest(struct pp_hwmgr *hwmgr)
3128 {
3129         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3130         uint32_t level, tmp;
3131
3132         if (!data->pcie_dpm_key_disabled) {
3133                 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3134                         level = 0;
3135                         tmp = data->dpm_level_enable_mask.pcie_dpm_enable_mask;
3136                         while (tmp >>= 1)
3137                                 level++;
3138
3139                         if (level)
3140                                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3141                                                 PPSMC_MSG_PCIeDPM_ForceLevel, level);
3142                 }
3143         }
3144
3145         if (!data->sclk_dpm_key_disabled) {
3146                 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3147                         level = 0;
3148                         tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask;
3149                         while (tmp >>= 1)
3150                                 level++;
3151
3152                         if (level)
3153                                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3154                                                 PPSMC_MSG_SCLKDPM_SetEnabledMask,
3155                                                 (1 << level));
3156                 }
3157         }
3158
3159         if (!data->mclk_dpm_key_disabled) {
3160                 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3161                         level = 0;
3162                         tmp = data->dpm_level_enable_mask.mclk_dpm_enable_mask;
3163                         while (tmp >>= 1)
3164                                 level++;
3165
3166                         if (level)
3167                                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3168                                                 PPSMC_MSG_MCLKDPM_SetEnabledMask,
3169                                                 (1 << level));
3170                 }
3171         }
3172
3173         return 0;
3174 }
3175
3176 static int polaris10_upload_dpm_level_enable_mask(struct pp_hwmgr *hwmgr)
3177 {
3178         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3179
3180         phm_apply_dal_min_voltage_request(hwmgr);
3181
3182         if (!data->sclk_dpm_key_disabled) {
3183                 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask)
3184                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3185                                         PPSMC_MSG_SCLKDPM_SetEnabledMask,
3186                                         data->dpm_level_enable_mask.sclk_dpm_enable_mask);
3187         }
3188
3189         if (!data->mclk_dpm_key_disabled) {
3190                 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask)
3191                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3192                                         PPSMC_MSG_MCLKDPM_SetEnabledMask,
3193                                         data->dpm_level_enable_mask.mclk_dpm_enable_mask);
3194         }
3195
3196         return 0;
3197 }
3198
3199 static int polaris10_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
3200 {
3201         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3202
3203         if (!polaris10_is_dpm_running(hwmgr))
3204                 return -EINVAL;
3205
3206         if (!data->pcie_dpm_key_disabled) {
3207                 smum_send_msg_to_smc(hwmgr->smumgr,
3208                                 PPSMC_MSG_PCIeDPM_UnForceLevel);
3209         }
3210
3211         return polaris10_upload_dpm_level_enable_mask(hwmgr);
3212 }
3213
3214 static int polaris10_force_dpm_lowest(struct pp_hwmgr *hwmgr)
3215 {
3216         struct polaris10_hwmgr *data =
3217                         (struct polaris10_hwmgr *)(hwmgr->backend);
3218         uint32_t level;
3219
3220         if (!data->sclk_dpm_key_disabled)
3221                 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3222                         level = phm_get_lowest_enabled_level(hwmgr,
3223                                                               data->dpm_level_enable_mask.sclk_dpm_enable_mask);
3224                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3225                                                             PPSMC_MSG_SCLKDPM_SetEnabledMask,
3226                                                             (1 << level));
3227
3228         }
3229
3230         if (!data->mclk_dpm_key_disabled) {
3231                 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3232                         level = phm_get_lowest_enabled_level(hwmgr,
3233                                                               data->dpm_level_enable_mask.mclk_dpm_enable_mask);
3234                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3235                                                             PPSMC_MSG_MCLKDPM_SetEnabledMask,
3236                                                             (1 << level));
3237                 }
3238         }
3239
3240         if (!data->pcie_dpm_key_disabled) {
3241                 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3242                         level = phm_get_lowest_enabled_level(hwmgr,
3243                                                               data->dpm_level_enable_mask.pcie_dpm_enable_mask);
3244                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3245                                                             PPSMC_MSG_PCIeDPM_ForceLevel,
3246                                                             (level));
3247                 }
3248         }
3249
3250         return 0;
3251
3252 }
3253 static int polaris10_force_dpm_level(struct pp_hwmgr *hwmgr,
3254                                 enum amd_dpm_forced_level level)
3255 {
3256         int ret = 0;
3257
3258         switch (level) {
3259         case AMD_DPM_FORCED_LEVEL_HIGH:
3260                 ret = polaris10_force_dpm_highest(hwmgr);
3261                 if (ret)
3262                         return ret;
3263                 break;
3264         case AMD_DPM_FORCED_LEVEL_LOW:
3265                 ret = polaris10_force_dpm_lowest(hwmgr);
3266                 if (ret)
3267                         return ret;
3268                 break;
3269         case AMD_DPM_FORCED_LEVEL_AUTO:
3270                 ret = polaris10_unforce_dpm_levels(hwmgr);
3271                 if (ret)
3272                         return ret;
3273                 break;
3274         default:
3275                 break;
3276         }
3277
3278         hwmgr->dpm_level = level;
3279
3280         return ret;
3281 }
3282
3283 static int polaris10_get_power_state_size(struct pp_hwmgr *hwmgr)
3284 {
3285         return sizeof(struct polaris10_power_state);
3286 }
3287
3288
3289 static int polaris10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
3290                                 struct pp_power_state *request_ps,
3291                         const struct pp_power_state *current_ps)
3292 {
3293
3294         struct polaris10_power_state *polaris10_ps =
3295                                 cast_phw_polaris10_power_state(&request_ps->hardware);
3296         uint32_t sclk;
3297         uint32_t mclk;
3298         struct PP_Clocks minimum_clocks = {0};
3299         bool disable_mclk_switching;
3300         bool disable_mclk_switching_for_frame_lock;
3301         struct cgs_display_info info = {0};
3302         const struct phm_clock_and_voltage_limits *max_limits;
3303         uint32_t i;
3304         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3305         struct phm_ppt_v1_information *table_info =
3306                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
3307         int32_t count;
3308         int32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0;
3309
3310         data->battery_state = (PP_StateUILabel_Battery ==
3311                         request_ps->classification.ui_label);
3312
3313         PP_ASSERT_WITH_CODE(polaris10_ps->performance_level_count == 2,
3314                                  "VI should always have 2 performance levels",
3315                                 );
3316
3317         max_limits = (PP_PowerSource_AC == hwmgr->power_source) ?
3318                         &(hwmgr->dyn_state.max_clock_voltage_on_ac) :
3319                         &(hwmgr->dyn_state.max_clock_voltage_on_dc);
3320
3321         /* Cap clock DPM tables at DC MAX if it is in DC. */
3322         if (PP_PowerSource_DC == hwmgr->power_source) {
3323                 for (i = 0; i < polaris10_ps->performance_level_count; i++) {
3324                         if (polaris10_ps->performance_levels[i].memory_clock > max_limits->mclk)
3325                                 polaris10_ps->performance_levels[i].memory_clock = max_limits->mclk;
3326                         if (polaris10_ps->performance_levels[i].engine_clock > max_limits->sclk)
3327                                 polaris10_ps->performance_levels[i].engine_clock = max_limits->sclk;
3328                 }
3329         }
3330
3331         polaris10_ps->vce_clks.evclk = hwmgr->vce_arbiter.evclk;
3332         polaris10_ps->vce_clks.ecclk = hwmgr->vce_arbiter.ecclk;
3333
3334         cgs_get_active_displays_info(hwmgr->device, &info);
3335
3336         /*TO DO result = PHM_CheckVBlankTime(hwmgr, &vblankTooShort);*/
3337
3338         /* TO DO GetMinClockSettings(hwmgr->pPECI, &minimum_clocks); */
3339
3340         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3341                         PHM_PlatformCaps_StablePState)) {
3342                 max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac);
3343                 stable_pstate_sclk = (max_limits->sclk * 75) / 100;
3344
3345                 for (count = table_info->vdd_dep_on_sclk->count - 1;
3346                                 count >= 0; count--) {
3347                         if (stable_pstate_sclk >=
3348                                         table_info->vdd_dep_on_sclk->entries[count].clk) {
3349                                 stable_pstate_sclk =
3350                                                 table_info->vdd_dep_on_sclk->entries[count].clk;
3351                                 break;
3352                         }
3353                 }
3354
3355                 if (count < 0)
3356                         stable_pstate_sclk = table_info->vdd_dep_on_sclk->entries[0].clk;
3357
3358                 stable_pstate_mclk = max_limits->mclk;
3359
3360                 minimum_clocks.engineClock = stable_pstate_sclk;
3361                 minimum_clocks.memoryClock = stable_pstate_mclk;
3362         }
3363
3364         if (minimum_clocks.engineClock < hwmgr->gfx_arbiter.sclk)
3365                 minimum_clocks.engineClock = hwmgr->gfx_arbiter.sclk;
3366
3367         if (minimum_clocks.memoryClock < hwmgr->gfx_arbiter.mclk)
3368                 minimum_clocks.memoryClock = hwmgr->gfx_arbiter.mclk;
3369
3370         polaris10_ps->sclk_threshold = hwmgr->gfx_arbiter.sclk_threshold;
3371
3372         if (0 != hwmgr->gfx_arbiter.sclk_over_drive) {
3373                 PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.sclk_over_drive <=
3374                                 hwmgr->platform_descriptor.overdriveLimit.engineClock),
3375                                 "Overdrive sclk exceeds limit",
3376                                 hwmgr->gfx_arbiter.sclk_over_drive =
3377                                                 hwmgr->platform_descriptor.overdriveLimit.engineClock);
3378
3379                 if (hwmgr->gfx_arbiter.sclk_over_drive >= hwmgr->gfx_arbiter.sclk)
3380                         polaris10_ps->performance_levels[1].engine_clock =
3381                                         hwmgr->gfx_arbiter.sclk_over_drive;
3382         }
3383
3384         if (0 != hwmgr->gfx_arbiter.mclk_over_drive) {
3385                 PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.mclk_over_drive <=
3386                                 hwmgr->platform_descriptor.overdriveLimit.memoryClock),
3387                                 "Overdrive mclk exceeds limit",
3388                                 hwmgr->gfx_arbiter.mclk_over_drive =
3389                                                 hwmgr->platform_descriptor.overdriveLimit.memoryClock);
3390
3391                 if (hwmgr->gfx_arbiter.mclk_over_drive >= hwmgr->gfx_arbiter.mclk)
3392                         polaris10_ps->performance_levels[1].memory_clock =
3393                                         hwmgr->gfx_arbiter.mclk_over_drive;
3394         }
3395
3396         disable_mclk_switching_for_frame_lock = phm_cap_enabled(
3397                                     hwmgr->platform_descriptor.platformCaps,
3398                                     PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);
3399
3400         disable_mclk_switching = (1 < info.display_count) ||
3401                                     disable_mclk_switching_for_frame_lock;
3402
3403         sclk = polaris10_ps->performance_levels[0].engine_clock;
3404         mclk = polaris10_ps->performance_levels[0].memory_clock;
3405
3406         if (disable_mclk_switching)
3407                 mclk = polaris10_ps->performance_levels
3408                 [polaris10_ps->performance_level_count - 1].memory_clock;
3409
3410         if (sclk < minimum_clocks.engineClock)
3411                 sclk = (minimum_clocks.engineClock > max_limits->sclk) ?
3412                                 max_limits->sclk : minimum_clocks.engineClock;
3413
3414         if (mclk < minimum_clocks.memoryClock)
3415                 mclk = (minimum_clocks.memoryClock > max_limits->mclk) ?
3416                                 max_limits->mclk : minimum_clocks.memoryClock;
3417
3418         polaris10_ps->performance_levels[0].engine_clock = sclk;
3419         polaris10_ps->performance_levels[0].memory_clock = mclk;
3420
3421         polaris10_ps->performance_levels[1].engine_clock =
3422                 (polaris10_ps->performance_levels[1].engine_clock >=
3423                                 polaris10_ps->performance_levels[0].engine_clock) ?
3424                                                 polaris10_ps->performance_levels[1].engine_clock :
3425                                                 polaris10_ps->performance_levels[0].engine_clock;
3426
3427         if (disable_mclk_switching) {
3428                 if (mclk < polaris10_ps->performance_levels[1].memory_clock)
3429                         mclk = polaris10_ps->performance_levels[1].memory_clock;
3430
3431                 polaris10_ps->performance_levels[0].memory_clock = mclk;
3432                 polaris10_ps->performance_levels[1].memory_clock = mclk;
3433         } else {
3434                 if (polaris10_ps->performance_levels[1].memory_clock <
3435                                 polaris10_ps->performance_levels[0].memory_clock)
3436                         polaris10_ps->performance_levels[1].memory_clock =
3437                                         polaris10_ps->performance_levels[0].memory_clock;
3438         }
3439
3440         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3441                         PHM_PlatformCaps_StablePState)) {
3442                 for (i = 0; i < polaris10_ps->performance_level_count; i++) {
3443                         polaris10_ps->performance_levels[i].engine_clock = stable_pstate_sclk;
3444                         polaris10_ps->performance_levels[i].memory_clock = stable_pstate_mclk;
3445                         polaris10_ps->performance_levels[i].pcie_gen = data->pcie_gen_performance.max;
3446                         polaris10_ps->performance_levels[i].pcie_lane = data->pcie_gen_performance.max;
3447                 }
3448         }
3449         return 0;
3450 }
3451
3452
3453 static int polaris10_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
3454 {
3455         struct pp_power_state  *ps;
3456         struct polaris10_power_state  *polaris10_ps;
3457
3458         if (hwmgr == NULL)
3459                 return -EINVAL;
3460
3461         ps = hwmgr->request_ps;
3462
3463         if (ps == NULL)
3464                 return -EINVAL;
3465
3466         polaris10_ps = cast_phw_polaris10_power_state(&ps->hardware);
3467
3468         if (low)
3469                 return polaris10_ps->performance_levels[0].memory_clock;
3470         else
3471                 return polaris10_ps->performance_levels
3472                                 [polaris10_ps->performance_level_count-1].memory_clock;
3473 }
3474
3475 static int polaris10_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
3476 {
3477         struct pp_power_state  *ps;
3478         struct polaris10_power_state  *polaris10_ps;
3479
3480         if (hwmgr == NULL)
3481                 return -EINVAL;
3482
3483         ps = hwmgr->request_ps;
3484
3485         if (ps == NULL)
3486                 return -EINVAL;
3487
3488         polaris10_ps = cast_phw_polaris10_power_state(&ps->hardware);
3489
3490         if (low)
3491                 return polaris10_ps->performance_levels[0].engine_clock;
3492         else
3493                 return polaris10_ps->performance_levels
3494                                 [polaris10_ps->performance_level_count-1].engine_clock;
3495 }
3496
3497 static int polaris10_dpm_patch_boot_state(struct pp_hwmgr *hwmgr,
3498                                         struct pp_hw_power_state *hw_ps)
3499 {
3500         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3501         struct polaris10_power_state *ps = (struct polaris10_power_state *)hw_ps;
3502         ATOM_FIRMWARE_INFO_V2_2 *fw_info;
3503         uint16_t size;
3504         uint8_t frev, crev;
3505         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
3506
3507         /* First retrieve the Boot clocks and VDDC from the firmware info table.
3508          * We assume here that fw_info is unchanged if this call fails.
3509          */
3510         fw_info = (ATOM_FIRMWARE_INFO_V2_2 *)cgs_atom_get_data_table(
3511                         hwmgr->device, index,
3512                         &size, &frev, &crev);
3513         if (!fw_info)
3514                 /* During a test, there is no firmware info table. */
3515                 return 0;
3516
3517         /* Patch the state. */
3518         data->vbios_boot_state.sclk_bootup_value =
3519                         le32_to_cpu(fw_info->ulDefaultEngineClock);
3520         data->vbios_boot_state.mclk_bootup_value =
3521                         le32_to_cpu(fw_info->ulDefaultMemoryClock);
3522         data->vbios_boot_state.mvdd_bootup_value =
3523                         le16_to_cpu(fw_info->usBootUpMVDDCVoltage);
3524         data->vbios_boot_state.vddc_bootup_value =
3525                         le16_to_cpu(fw_info->usBootUpVDDCVoltage);
3526         data->vbios_boot_state.vddci_bootup_value =
3527                         le16_to_cpu(fw_info->usBootUpVDDCIVoltage);
3528         data->vbios_boot_state.pcie_gen_bootup_value =
3529                         phm_get_current_pcie_speed(hwmgr);
3530
3531         data->vbios_boot_state.pcie_lane_bootup_value =
3532                         (uint16_t)phm_get_current_pcie_lane_number(hwmgr);
3533
3534         /* set boot power state */
3535         ps->performance_levels[0].memory_clock = data->vbios_boot_state.mclk_bootup_value;
3536         ps->performance_levels[0].engine_clock = data->vbios_boot_state.sclk_bootup_value;
3537         ps->performance_levels[0].pcie_gen = data->vbios_boot_state.pcie_gen_bootup_value;
3538         ps->performance_levels[0].pcie_lane = data->vbios_boot_state.pcie_lane_bootup_value;
3539
3540         return 0;
3541 }
3542
3543 static int polaris10_get_pp_table_entry_callback_func(struct pp_hwmgr *hwmgr,
3544                 void *state, struct pp_power_state *power_state,
3545                 void *pp_table, uint32_t classification_flag)
3546 {
3547         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3548         struct polaris10_power_state  *polaris10_power_state =
3549                         (struct polaris10_power_state *)(&(power_state->hardware));
3550         struct polaris10_performance_level *performance_level;
3551         ATOM_Tonga_State *state_entry = (ATOM_Tonga_State *)state;
3552         ATOM_Tonga_POWERPLAYTABLE *powerplay_table =
3553                         (ATOM_Tonga_POWERPLAYTABLE *)pp_table;
3554         PPTable_Generic_SubTable_Header *sclk_dep_table =
3555                         (PPTable_Generic_SubTable_Header *)
3556                         (((unsigned long)powerplay_table) +
3557                                 le16_to_cpu(powerplay_table->usSclkDependencyTableOffset));
3558
3559         ATOM_Tonga_MCLK_Dependency_Table *mclk_dep_table =
3560                         (ATOM_Tonga_MCLK_Dependency_Table *)
3561                         (((unsigned long)powerplay_table) +
3562                                 le16_to_cpu(powerplay_table->usMclkDependencyTableOffset));
3563
3564         /* The following fields are not initialized here: id orderedList allStatesList */
3565         power_state->classification.ui_label =
3566                         (le16_to_cpu(state_entry->usClassification) &
3567                         ATOM_PPLIB_CLASSIFICATION_UI_MASK) >>
3568                         ATOM_PPLIB_CLASSIFICATION_UI_SHIFT;
3569         power_state->classification.flags = classification_flag;
3570         /* NOTE: There is a classification2 flag in BIOS that is not being used right now */
3571
3572         power_state->classification.temporary_state = false;
3573         power_state->classification.to_be_deleted = false;
3574
3575         power_state->validation.disallowOnDC =
3576                         (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) &
3577                                         ATOM_Tonga_DISALLOW_ON_DC));
3578
3579         power_state->pcie.lanes = 0;
3580
3581         power_state->display.disableFrameModulation = false;
3582         power_state->display.limitRefreshrate = false;
3583         power_state->display.enableVariBright =
3584                         (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) &
3585                                         ATOM_Tonga_ENABLE_VARIBRIGHT));
3586
3587         power_state->validation.supportedPowerLevels = 0;
3588         power_state->uvd_clocks.VCLK = 0;
3589         power_state->uvd_clocks.DCLK = 0;
3590         power_state->temperatures.min = 0;
3591         power_state->temperatures.max = 0;
3592
3593         performance_level = &(polaris10_power_state->performance_levels
3594                         [polaris10_power_state->performance_level_count++]);
3595
3596         PP_ASSERT_WITH_CODE(
3597                         (polaris10_power_state->performance_level_count < SMU74_MAX_LEVELS_GRAPHICS),
3598                         "Performance levels exceeds SMC limit!",
3599                         return -1);
3600
3601         PP_ASSERT_WITH_CODE(
3602                         (polaris10_power_state->performance_level_count <=
3603                                         hwmgr->platform_descriptor.hardwareActivityPerformanceLevels),
3604                         "Performance levels exceeds Driver limit!",
3605                         return -1);
3606
3607         /* Performance levels are arranged from low to high. */
3608         performance_level->memory_clock = mclk_dep_table->entries
3609                         [state_entry->ucMemoryClockIndexLow].ulMclk;
3610         if (sclk_dep_table->ucRevId == 0)
3611                 performance_level->engine_clock = ((ATOM_Tonga_SCLK_Dependency_Table *)sclk_dep_table)->entries
3612                         [state_entry->ucEngineClockIndexLow].ulSclk;
3613         else if (sclk_dep_table->ucRevId == 1)
3614                 performance_level->engine_clock = ((ATOM_Polaris_SCLK_Dependency_Table *)sclk_dep_table)->entries
3615                         [state_entry->ucEngineClockIndexLow].ulSclk;
3616         performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap,
3617                         state_entry->ucPCIEGenLow);
3618         performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap,
3619                         state_entry->ucPCIELaneHigh);
3620
3621         performance_level = &(polaris10_power_state->performance_levels
3622                         [polaris10_power_state->performance_level_count++]);
3623         performance_level->memory_clock = mclk_dep_table->entries
3624                         [state_entry->ucMemoryClockIndexHigh].ulMclk;
3625
3626         if (sclk_dep_table->ucRevId == 0)
3627                 performance_level->engine_clock = ((ATOM_Tonga_SCLK_Dependency_Table *)sclk_dep_table)->entries
3628                         [state_entry->ucEngineClockIndexHigh].ulSclk;
3629         else if (sclk_dep_table->ucRevId == 1)
3630                 performance_level->engine_clock = ((ATOM_Polaris_SCLK_Dependency_Table *)sclk_dep_table)->entries
3631                         [state_entry->ucEngineClockIndexHigh].ulSclk;
3632
3633         performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap,
3634                         state_entry->ucPCIEGenHigh);
3635         performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap,
3636                         state_entry->ucPCIELaneHigh);
3637
3638         return 0;
3639 }
3640
3641 static int polaris10_get_pp_table_entry(struct pp_hwmgr *hwmgr,
3642                 unsigned long entry_index, struct pp_power_state *state)
3643 {
3644         int result;
3645         struct polaris10_power_state *ps;
3646         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3647         struct phm_ppt_v1_information *table_info =
3648                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
3649         struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
3650                         table_info->vdd_dep_on_mclk;
3651
3652         state->hardware.magic = PHM_VIslands_Magic;
3653
3654         ps = (struct polaris10_power_state *)(&state->hardware);
3655
3656         result = tonga_get_powerplay_table_entry(hwmgr, entry_index, state,
3657                         polaris10_get_pp_table_entry_callback_func);
3658
3659         /* This is the earliest time we have all the dependency table and the VBIOS boot state
3660          * as PP_Tables_GetPowerPlayTableEntry retrieves the VBIOS boot state
3661          * if there is only one VDDCI/MCLK level, check if it's the same as VBIOS boot state
3662          */
3663         if (dep_mclk_table != NULL && dep_mclk_table->count == 1) {
3664                 if (dep_mclk_table->entries[0].clk !=
3665                                 data->vbios_boot_state.mclk_bootup_value)
3666                         printk(KERN_ERR "Single MCLK entry VDDCI/MCLK dependency table "
3667                                         "does not match VBIOS boot MCLK level");
3668                 if (dep_mclk_table->entries[0].vddci !=
3669                                 data->vbios_boot_state.vddci_bootup_value)
3670                         printk(KERN_ERR "Single VDDCI entry VDDCI/MCLK dependency table "
3671                                         "does not match VBIOS boot VDDCI level");
3672         }
3673
3674         /* set DC compatible flag if this state supports DC */
3675         if (!state->validation.disallowOnDC)
3676                 ps->dc_compatible = true;
3677
3678         if (state->classification.flags & PP_StateClassificationFlag_ACPI)
3679                 data->acpi_pcie_gen = ps->performance_levels[0].pcie_gen;
3680
3681         ps->uvd_clks.vclk = state->uvd_clocks.VCLK;
3682         ps->uvd_clks.dclk = state->uvd_clocks.DCLK;
3683
3684         if (!result) {
3685                 uint32_t i;
3686
3687                 switch (state->classification.ui_label) {
3688                 case PP_StateUILabel_Performance:
3689                         data->use_pcie_performance_levels = true;
3690                         for (i = 0; i < ps->performance_level_count; i++) {
3691                                 if (data->pcie_gen_performance.max <
3692                                                 ps->performance_levels[i].pcie_gen)
3693                                         data->pcie_gen_performance.max =
3694                                                         ps->performance_levels[i].pcie_gen;
3695
3696                                 if (data->pcie_gen_performance.min >
3697                                                 ps->performance_levels[i].pcie_gen)
3698                                         data->pcie_gen_performance.min =
3699                                                         ps->performance_levels[i].pcie_gen;
3700
3701                                 if (data->pcie_lane_performance.max <
3702                                                 ps->performance_levels[i].pcie_lane)
3703                                         data->pcie_lane_performance.max =
3704                                                         ps->performance_levels[i].pcie_lane;
3705                                 if (data->pcie_lane_performance.min >
3706                                                 ps->performance_levels[i].pcie_lane)
3707                                         data->pcie_lane_performance.min =
3708                                                         ps->performance_levels[i].pcie_lane;
3709                         }
3710                         break;
3711                 case PP_StateUILabel_Battery:
3712                         data->use_pcie_power_saving_levels = true;
3713
3714                         for (i = 0; i < ps->performance_level_count; i++) {
3715                                 if (data->pcie_gen_power_saving.max <
3716                                                 ps->performance_levels[i].pcie_gen)
3717                                         data->pcie_gen_power_saving.max =
3718                                                         ps->performance_levels[i].pcie_gen;
3719
3720                                 if (data->pcie_gen_power_saving.min >
3721                                                 ps->performance_levels[i].pcie_gen)
3722                                         data->pcie_gen_power_saving.min =
3723                                                         ps->performance_levels[i].pcie_gen;
3724
3725                                 if (data->pcie_lane_power_saving.max <
3726                                                 ps->performance_levels[i].pcie_lane)
3727                                         data->pcie_lane_power_saving.max =
3728                                                         ps->performance_levels[i].pcie_lane;
3729
3730                                 if (data->pcie_lane_power_saving.min >
3731                                                 ps->performance_levels[i].pcie_lane)
3732                                         data->pcie_lane_power_saving.min =
3733                                                         ps->performance_levels[i].pcie_lane;
3734                         }
3735                         break;
3736                 default:
3737                         break;
3738                 }
3739         }
3740         return 0;
3741 }
3742
3743 static void
3744 polaris10_print_current_perforce_level(struct pp_hwmgr *hwmgr, struct seq_file *m)
3745 {
3746         uint32_t sclk, mclk, activity_percent;
3747         uint32_t offset;
3748         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3749
3750         smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency);
3751
3752         sclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
3753
3754         smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency);
3755
3756         mclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
3757         seq_printf(m, "\n [  mclk  ]: %u MHz\n\n [  sclk  ]: %u MHz\n",
3758                         mclk / 100, sclk / 100);
3759
3760         offset = data->soft_regs_start + offsetof(SMU74_SoftRegisters, AverageGraphicsActivity);
3761         activity_percent = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset);
3762         activity_percent += 0x80;
3763         activity_percent >>= 8;
3764
3765         seq_printf(m, "\n [GPU load]: %u%%\n\n", activity_percent > 100 ? 100 : activity_percent);
3766
3767         seq_printf(m, "uvd    %sabled\n", data->uvd_power_gated ? "dis" : "en");
3768
3769         seq_printf(m, "vce    %sabled\n", data->vce_power_gated ? "dis" : "en");
3770 }
3771
3772 static int polaris10_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input)
3773 {
3774         const struct phm_set_power_state_input *states =
3775                         (const struct phm_set_power_state_input *)input;
3776         const struct polaris10_power_state *polaris10_ps =
3777                         cast_const_phw_polaris10_power_state(states->pnew_state);
3778         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3779         struct polaris10_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
3780         uint32_t sclk = polaris10_ps->performance_levels
3781                         [polaris10_ps->performance_level_count - 1].engine_clock;
3782         struct polaris10_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
3783         uint32_t mclk = polaris10_ps->performance_levels
3784                         [polaris10_ps->performance_level_count - 1].memory_clock;
3785         struct PP_Clocks min_clocks = {0};
3786         uint32_t i;
3787         struct cgs_display_info info = {0};
3788
3789         data->need_update_smu7_dpm_table = 0;
3790
3791         for (i = 0; i < sclk_table->count; i++) {
3792                 if (sclk == sclk_table->dpm_levels[i].value)
3793                         break;
3794         }
3795
3796         if (i >= sclk_table->count)
3797                 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
3798         else {
3799         /* TODO: Check SCLK in DAL's minimum clocks
3800          * in case DeepSleep divider update is required.
3801          */
3802                 if (data->display_timing.min_clock_in_sr != min_clocks.engineClockInSR &&
3803                         (min_clocks.engineClockInSR >= POLARIS10_MINIMUM_ENGINE_CLOCK ||
3804                                 data->display_timing.min_clock_in_sr >= POLARIS10_MINIMUM_ENGINE_CLOCK))
3805                         data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK;
3806         }
3807
3808         for (i = 0; i < mclk_table->count; i++) {
3809                 if (mclk == mclk_table->dpm_levels[i].value)
3810                         break;
3811         }
3812
3813         if (i >= mclk_table->count)
3814                 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
3815
3816         cgs_get_active_displays_info(hwmgr->device, &info);
3817
3818         if (data->display_timing.num_existing_displays != info.display_count)
3819                 data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK;
3820
3821         return 0;
3822 }
3823
3824 static uint16_t polaris10_get_maximum_link_speed(struct pp_hwmgr *hwmgr,
3825                 const struct polaris10_power_state *polaris10_ps)
3826 {
3827         uint32_t i;
3828         uint32_t sclk, max_sclk = 0;
3829         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3830         struct polaris10_dpm_table *dpm_table = &data->dpm_table;
3831
3832         for (i = 0; i < polaris10_ps->performance_level_count; i++) {
3833                 sclk = polaris10_ps->performance_levels[i].engine_clock;
3834                 if (max_sclk < sclk)
3835                         max_sclk = sclk;
3836         }
3837
3838         for (i = 0; i < dpm_table->sclk_table.count; i++) {
3839                 if (dpm_table->sclk_table.dpm_levels[i].value == max_sclk)
3840                         return (uint16_t) ((i >= dpm_table->pcie_speed_table.count) ?
3841                                         dpm_table->pcie_speed_table.dpm_levels
3842                                         [dpm_table->pcie_speed_table.count - 1].value :
3843                                         dpm_table->pcie_speed_table.dpm_levels[i].value);
3844         }
3845
3846         return 0;
3847 }
3848
3849 static int polaris10_request_link_speed_change_before_state_change(
3850                 struct pp_hwmgr *hwmgr, const void *input)
3851 {
3852         const struct phm_set_power_state_input *states =
3853                         (const struct phm_set_power_state_input *)input;
3854         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3855         const struct polaris10_power_state *polaris10_nps =
3856                         cast_const_phw_polaris10_power_state(states->pnew_state);
3857         const struct polaris10_power_state *polaris10_cps =
3858                         cast_const_phw_polaris10_power_state(states->pcurrent_state);
3859
3860         uint16_t target_link_speed = polaris10_get_maximum_link_speed(hwmgr, polaris10_nps);
3861         uint16_t current_link_speed;
3862
3863         if (data->force_pcie_gen == PP_PCIEGenInvalid)
3864                 current_link_speed = polaris10_get_maximum_link_speed(hwmgr, polaris10_cps);
3865         else
3866                 current_link_speed = data->force_pcie_gen;
3867
3868         data->force_pcie_gen = PP_PCIEGenInvalid;
3869         data->pspp_notify_required = false;
3870
3871         if (target_link_speed > current_link_speed) {
3872                 switch (target_link_speed) {
3873                 case PP_PCIEGen3:
3874                         if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN3, false))
3875                                 break;
3876                         data->force_pcie_gen = PP_PCIEGen2;
3877                         if (current_link_speed == PP_PCIEGen2)
3878                                 break;
3879                 case PP_PCIEGen2:
3880                         if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN2, false))
3881                                 break;
3882                 default:
3883                         data->force_pcie_gen = phm_get_current_pcie_speed(hwmgr);
3884                         break;
3885                 }
3886         } else {
3887                 if (target_link_speed < current_link_speed)
3888                         data->pspp_notify_required = true;
3889         }
3890
3891         return 0;
3892 }
3893
3894 static int polaris10_freeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
3895 {
3896         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3897
3898         if (0 == data->need_update_smu7_dpm_table)
3899                 return 0;
3900
3901         if ((0 == data->sclk_dpm_key_disabled) &&
3902                 (data->need_update_smu7_dpm_table &
3903                         (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
3904                 PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr),
3905                                 "Trying to freeze SCLK DPM when DPM is disabled",
3906                                 );
3907                 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
3908                                 PPSMC_MSG_SCLKDPM_FreezeLevel),
3909                                 "Failed to freeze SCLK DPM during FreezeSclkMclkDPM Function!",
3910                                 return -1);
3911         }
3912
3913         if ((0 == data->mclk_dpm_key_disabled) &&
3914                 (data->need_update_smu7_dpm_table &
3915                  DPMTABLE_OD_UPDATE_MCLK)) {
3916                 PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr),
3917                                 "Trying to freeze MCLK DPM when DPM is disabled",
3918                                 );
3919                 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
3920                                 PPSMC_MSG_MCLKDPM_FreezeLevel),
3921                                 "Failed to freeze MCLK DPM during FreezeSclkMclkDPM Function!",
3922                                 return -1);
3923         }
3924
3925         return 0;
3926 }
3927
3928 static int polaris10_populate_and_upload_sclk_mclk_dpm_levels(
3929                 struct pp_hwmgr *hwmgr, const void *input)
3930 {
3931         int result = 0;
3932         const struct phm_set_power_state_input *states =
3933                         (const struct phm_set_power_state_input *)input;
3934         const struct polaris10_power_state *polaris10_ps =
3935                         cast_const_phw_polaris10_power_state(states->pnew_state);
3936         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3937         uint32_t sclk = polaris10_ps->performance_levels
3938                         [polaris10_ps->performance_level_count - 1].engine_clock;
3939         uint32_t mclk = polaris10_ps->performance_levels
3940                         [polaris10_ps->performance_level_count - 1].memory_clock;
3941         struct polaris10_dpm_table *dpm_table = &data->dpm_table;
3942
3943         struct polaris10_dpm_table *golden_dpm_table = &data->golden_dpm_table;
3944         uint32_t dpm_count, clock_percent;
3945         uint32_t i;
3946
3947         if (0 == data->need_update_smu7_dpm_table)
3948                 return 0;
3949
3950         if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) {
3951                 dpm_table->sclk_table.dpm_levels
3952                 [dpm_table->sclk_table.count - 1].value = sclk;
3953
3954                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) ||
3955                     phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) {
3956                 /* Need to do calculation based on the golden DPM table
3957                  * as the Heatmap GPU Clock axis is also based on the default values
3958                  */
3959                         PP_ASSERT_WITH_CODE(
3960                                 (golden_dpm_table->sclk_table.dpm_levels
3961                                                 [golden_dpm_table->sclk_table.count - 1].value != 0),
3962                                 "Divide by 0!",
3963                                 return -1);
3964                         dpm_count = dpm_table->sclk_table.count < 2 ? 0 : dpm_table->sclk_table.count - 2;
3965
3966                         for (i = dpm_count; i > 1; i--) {
3967                                 if (sclk > golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value) {
3968                                         clock_percent =
3969                                               ((sclk
3970                                                 - golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value
3971                                                 ) * 100)
3972                                                 / golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value;
3973
3974                                         dpm_table->sclk_table.dpm_levels[i].value =
3975                                                         golden_dpm_table->sclk_table.dpm_levels[i].value +
3976                                                         (golden_dpm_table->sclk_table.dpm_levels[i].value *
3977                                                                 clock_percent)/100;
3978
3979                                 } else if (golden_dpm_table->sclk_table.dpm_levels[dpm_table->sclk_table.count-1].value > sclk) {
3980                                         clock_percent =
3981                                                 ((golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count - 1].value
3982                                                 - sclk) * 100)
3983                                                 / golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value;
3984
3985                                         dpm_table->sclk_table.dpm_levels[i].value =
3986                                                         golden_dpm_table->sclk_table.dpm_levels[i].value -
3987                                                         (golden_dpm_table->sclk_table.dpm_levels[i].value *
3988                                                                         clock_percent) / 100;
3989                                 } else
3990                                         dpm_table->sclk_table.dpm_levels[i].value =
3991                                                         golden_dpm_table->sclk_table.dpm_levels[i].value;
3992                         }
3993                 }
3994         }
3995
3996         if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) {
3997                 dpm_table->mclk_table.dpm_levels
3998                         [dpm_table->mclk_table.count - 1].value = mclk;
3999
4000                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) ||
4001                     phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) {
4002
4003                         PP_ASSERT_WITH_CODE(
4004                                         (golden_dpm_table->mclk_table.dpm_levels
4005                                                 [golden_dpm_table->mclk_table.count-1].value != 0),
4006                                         "Divide by 0!",
4007                                         return -1);
4008                         dpm_count = dpm_table->mclk_table.count < 2 ? 0 : dpm_table->mclk_table.count - 2;
4009                         for (i = dpm_count; i > 1; i--) {
4010                                 if (golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value < mclk) {
4011                                         clock_percent = ((mclk -
4012                                         golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value) * 100)
4013                                         / golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value;
4014
4015                                         dpm_table->mclk_table.dpm_levels[i].value =
4016                                                         golden_dpm_table->mclk_table.dpm_levels[i].value +
4017                                                         (golden_dpm_table->mclk_table.dpm_levels[i].value *
4018                                                         clock_percent) / 100;
4019
4020                                 } else if (golden_dpm_table->mclk_table.dpm_levels[dpm_table->mclk_table.count-1].value > mclk) {
4021                                         clock_percent = (
4022                                          (golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value - mclk)
4023                                         * 100)
4024                                         / golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value;
4025
4026                                         dpm_table->mclk_table.dpm_levels[i].value =
4027                                                         golden_dpm_table->mclk_table.dpm_levels[i].value -
4028                                                         (golden_dpm_table->mclk_table.dpm_levels[i].value *
4029                                                                         clock_percent) / 100;
4030                                 } else
4031                                         dpm_table->mclk_table.dpm_levels[i].value =
4032                                                         golden_dpm_table->mclk_table.dpm_levels[i].value;
4033                         }
4034                 }
4035         }
4036
4037         if (data->need_update_smu7_dpm_table &
4038                         (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK)) {
4039                 result = polaris10_populate_all_graphic_levels(hwmgr);
4040                 PP_ASSERT_WITH_CODE((0 == result),
4041                                 "Failed to populate SCLK during PopulateNewDPMClocksStates Function!",
4042                                 return result);
4043         }
4044
4045         if (data->need_update_smu7_dpm_table &
4046                         (DPMTABLE_OD_UPDATE_MCLK + DPMTABLE_UPDATE_MCLK)) {
4047                 /*populate MCLK dpm table to SMU7 */
4048                 result = polaris10_populate_all_memory_levels(hwmgr);
4049                 PP_ASSERT_WITH_CODE((0 == result),
4050                                 "Failed to populate MCLK during PopulateNewDPMClocksStates Function!",
4051                                 return result);
4052         }
4053
4054         return result;
4055 }
4056
4057 static int polaris10_trim_single_dpm_states(struct pp_hwmgr *hwmgr,
4058                           struct polaris10_single_dpm_table *dpm_table,
4059                         uint32_t low_limit, uint32_t high_limit)
4060 {
4061         uint32_t i;
4062
4063         for (i = 0; i < dpm_table->count; i++) {
4064                 if ((dpm_table->dpm_levels[i].value < low_limit)
4065                 || (dpm_table->dpm_levels[i].value > high_limit))
4066                         dpm_table->dpm_levels[i].enabled = false;
4067                 else
4068                         dpm_table->dpm_levels[i].enabled = true;
4069         }
4070
4071         return 0;
4072 }
4073
4074 static int polaris10_trim_dpm_states(struct pp_hwmgr *hwmgr,
4075                 const struct polaris10_power_state *polaris10_ps)
4076 {
4077         int result = 0;
4078         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4079         uint32_t high_limit_count;
4080
4081         PP_ASSERT_WITH_CODE((polaris10_ps->performance_level_count >= 1),
4082                         "power state did not have any performance level",
4083                         return -1);
4084
4085         high_limit_count = (1 == polaris10_ps->performance_level_count) ? 0 : 1;
4086
4087         polaris10_trim_single_dpm_states(hwmgr,
4088                         &(data->dpm_table.sclk_table),
4089                         polaris10_ps->performance_levels[0].engine_clock,
4090                         polaris10_ps->performance_levels[high_limit_count].engine_clock);
4091
4092         polaris10_trim_single_dpm_states(hwmgr,
4093                         &(data->dpm_table.mclk_table),
4094                         polaris10_ps->performance_levels[0].memory_clock,
4095                         polaris10_ps->performance_levels[high_limit_count].memory_clock);
4096
4097         return result;
4098 }
4099
4100 static int polaris10_generate_dpm_level_enable_mask(
4101                 struct pp_hwmgr *hwmgr, const void *input)
4102 {
4103         int result;
4104         const struct phm_set_power_state_input *states =
4105                         (const struct phm_set_power_state_input *)input;
4106         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4107         const struct polaris10_power_state *polaris10_ps =
4108                         cast_const_phw_polaris10_power_state(states->pnew_state);
4109
4110         result = polaris10_trim_dpm_states(hwmgr, polaris10_ps);
4111         if (result)
4112                 return result;
4113
4114         data->dpm_level_enable_mask.sclk_dpm_enable_mask =
4115                         phm_get_dpm_level_enable_mask_value(&data->dpm_table.sclk_table);
4116         data->dpm_level_enable_mask.mclk_dpm_enable_mask =
4117                         phm_get_dpm_level_enable_mask_value(&data->dpm_table.mclk_table);
4118         data->dpm_level_enable_mask.pcie_dpm_enable_mask =
4119                         phm_get_dpm_level_enable_mask_value(&data->dpm_table.pcie_speed_table);
4120
4121         return 0;
4122 }
4123
4124 int polaris10_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
4125 {
4126         return smum_send_msg_to_smc(hwmgr->smumgr, enable ?
4127                         PPSMC_MSG_UVDDPM_Enable :
4128                         PPSMC_MSG_UVDDPM_Disable);
4129 }
4130
4131 int polaris10_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
4132 {
4133         return smum_send_msg_to_smc(hwmgr->smumgr, enable?
4134                         PPSMC_MSG_VCEDPM_Enable :
4135                         PPSMC_MSG_VCEDPM_Disable);
4136 }
4137
4138 int polaris10_enable_disable_samu_dpm(struct pp_hwmgr *hwmgr, bool enable)
4139 {
4140         return smum_send_msg_to_smc(hwmgr->smumgr, enable?
4141                         PPSMC_MSG_SAMUDPM_Enable :
4142                         PPSMC_MSG_SAMUDPM_Disable);
4143 }
4144
4145 int polaris10_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate)
4146 {
4147         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4148         uint32_t mm_boot_level_offset, mm_boot_level_value;
4149         struct phm_ppt_v1_information *table_info =
4150                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
4151
4152         if (!bgate) {
4153                 data->smc_state_table.UvdBootLevel = 0;
4154                 if (table_info->mm_dep_table->count > 0)
4155                         data->smc_state_table.UvdBootLevel =
4156                                         (uint8_t) (table_info->mm_dep_table->count - 1);
4157                 mm_boot_level_offset = data->dpm_table_start +
4158                                 offsetof(SMU74_Discrete_DpmTable, UvdBootLevel);
4159                 mm_boot_level_offset /= 4;
4160                 mm_boot_level_offset *= 4;
4161                 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
4162                                 CGS_IND_REG__SMC, mm_boot_level_offset);
4163                 mm_boot_level_value &= 0x00FFFFFF;
4164                 mm_boot_level_value |= data->smc_state_table.UvdBootLevel << 24;
4165                 cgs_write_ind_register(hwmgr->device,
4166                                 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
4167
4168                 if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4169                                 PHM_PlatformCaps_UVDDPM) ||
4170                         phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4171                                 PHM_PlatformCaps_StablePState))
4172                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4173                                         PPSMC_MSG_UVDDPM_SetEnabledMask,
4174                                         (uint32_t)(1 << data->smc_state_table.UvdBootLevel));
4175         }
4176
4177         return polaris10_enable_disable_uvd_dpm(hwmgr, !bgate);
4178 }
4179
4180 static int polaris10_update_vce_dpm(struct pp_hwmgr *hwmgr, const void *input)
4181 {
4182         const struct phm_set_power_state_input *states =
4183                         (const struct phm_set_power_state_input *)input;
4184         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4185         const struct polaris10_power_state *polaris10_nps =
4186                         cast_const_phw_polaris10_power_state(states->pnew_state);
4187         const struct polaris10_power_state *polaris10_cps =
4188                         cast_const_phw_polaris10_power_state(states->pcurrent_state);
4189
4190         uint32_t mm_boot_level_offset, mm_boot_level_value;
4191         struct phm_ppt_v1_information *table_info =
4192                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
4193
4194         if (polaris10_nps->vce_clks.evclk > 0 &&
4195         (polaris10_cps == NULL || polaris10_cps->vce_clks.evclk == 0)) {
4196
4197                 data->smc_state_table.VceBootLevel =
4198                                 (uint8_t) (table_info->mm_dep_table->count - 1);
4199
4200                 mm_boot_level_offset = data->dpm_table_start +
4201                                 offsetof(SMU74_Discrete_DpmTable, VceBootLevel);
4202                 mm_boot_level_offset /= 4;
4203                 mm_boot_level_offset *= 4;
4204                 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
4205                                 CGS_IND_REG__SMC, mm_boot_level_offset);
4206                 mm_boot_level_value &= 0xFF00FFFF;
4207                 mm_boot_level_value |= data->smc_state_table.VceBootLevel << 16;
4208                 cgs_write_ind_register(hwmgr->device,
4209                                 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
4210
4211                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState)) {
4212                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4213                                         PPSMC_MSG_VCEDPM_SetEnabledMask,
4214                                         (uint32_t)1 << data->smc_state_table.VceBootLevel);
4215
4216                         polaris10_enable_disable_vce_dpm(hwmgr, true);
4217                 } else if (polaris10_nps->vce_clks.evclk == 0 &&
4218                                 polaris10_cps != NULL &&
4219                                 polaris10_cps->vce_clks.evclk > 0)
4220                         polaris10_enable_disable_vce_dpm(hwmgr, false);
4221         }
4222
4223         return 0;
4224 }
4225
4226 int polaris10_update_samu_dpm(struct pp_hwmgr *hwmgr, bool bgate)
4227 {
4228         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4229         uint32_t mm_boot_level_offset, mm_boot_level_value;
4230
4231         if (!bgate) {
4232                 data->smc_state_table.SamuBootLevel = 0;
4233                 mm_boot_level_offset = data->dpm_table_start +
4234                                 offsetof(SMU74_Discrete_DpmTable, SamuBootLevel);
4235                 mm_boot_level_offset /= 4;
4236                 mm_boot_level_offset *= 4;
4237                 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
4238                                 CGS_IND_REG__SMC, mm_boot_level_offset);
4239                 mm_boot_level_value &= 0xFFFFFF00;
4240                 mm_boot_level_value |= data->smc_state_table.SamuBootLevel << 0;
4241                 cgs_write_ind_register(hwmgr->device,
4242                                 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
4243
4244                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4245                                 PHM_PlatformCaps_StablePState))
4246                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4247                                         PPSMC_MSG_SAMUDPM_SetEnabledMask,
4248                                         (uint32_t)(1 << data->smc_state_table.SamuBootLevel));
4249         }
4250
4251         return polaris10_enable_disable_samu_dpm(hwmgr, !bgate);
4252 }
4253
4254 static int polaris10_update_sclk_threshold(struct pp_hwmgr *hwmgr)
4255 {
4256         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4257
4258         int result = 0;
4259         uint32_t low_sclk_interrupt_threshold = 0;
4260
4261         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4262                         PHM_PlatformCaps_SclkThrottleLowNotification)
4263                 && (hwmgr->gfx_arbiter.sclk_threshold !=
4264                                 data->low_sclk_interrupt_threshold)) {
4265                 data->low_sclk_interrupt_threshold =
4266                                 hwmgr->gfx_arbiter.sclk_threshold;
4267                 low_sclk_interrupt_threshold =
4268                                 data->low_sclk_interrupt_threshold;
4269
4270                 CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
4271
4272                 result = polaris10_copy_bytes_to_smc(
4273                                 hwmgr->smumgr,
4274                                 data->dpm_table_start +
4275                                 offsetof(SMU74_Discrete_DpmTable,
4276                                         LowSclkInterruptThreshold),
4277                                 (uint8_t *)&low_sclk_interrupt_threshold,
4278                                 sizeof(uint32_t),
4279                                 data->sram_end);
4280         }
4281
4282         return result;
4283 }
4284
4285 static int polaris10_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
4286 {
4287         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4288
4289         if (data->need_update_smu7_dpm_table &
4290                 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK))
4291                 return polaris10_program_memory_timing_parameters(hwmgr);
4292
4293         return 0;
4294 }
4295
4296 static int polaris10_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
4297 {
4298         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4299
4300         if (0 == data->need_update_smu7_dpm_table)
4301                 return 0;
4302
4303         if ((0 == data->sclk_dpm_key_disabled) &&
4304                 (data->need_update_smu7_dpm_table &
4305                 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
4306
4307                 PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr),
4308                                 "Trying to Unfreeze SCLK DPM when DPM is disabled",
4309                                 );
4310                 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4311                                 PPSMC_MSG_SCLKDPM_UnfreezeLevel),
4312                         "Failed to unfreeze SCLK DPM during UnFreezeSclkMclkDPM Function!",
4313                         return -1);
4314         }
4315
4316         if ((0 == data->mclk_dpm_key_disabled) &&
4317                 (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
4318
4319                 PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr),
4320                                 "Trying to Unfreeze MCLK DPM when DPM is disabled",
4321                                 );
4322                 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4323                                 PPSMC_MSG_SCLKDPM_UnfreezeLevel),
4324                     "Failed to unfreeze MCLK DPM during UnFreezeSclkMclkDPM Function!",
4325                     return -1);
4326         }
4327
4328         data->need_update_smu7_dpm_table = 0;
4329
4330         return 0;
4331 }
4332
4333 static int polaris10_notify_link_speed_change_after_state_change(
4334                 struct pp_hwmgr *hwmgr, const void *input)
4335 {
4336         const struct phm_set_power_state_input *states =
4337                         (const struct phm_set_power_state_input *)input;
4338         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4339         const struct polaris10_power_state *polaris10_ps =
4340                         cast_const_phw_polaris10_power_state(states->pnew_state);
4341         uint16_t target_link_speed = polaris10_get_maximum_link_speed(hwmgr, polaris10_ps);
4342         uint8_t  request;
4343
4344         if (data->pspp_notify_required) {
4345                 if (target_link_speed == PP_PCIEGen3)
4346                         request = PCIE_PERF_REQ_GEN3;
4347                 else if (target_link_speed == PP_PCIEGen2)
4348                         request = PCIE_PERF_REQ_GEN2;
4349                 else
4350                         request = PCIE_PERF_REQ_GEN1;
4351
4352                 if (request == PCIE_PERF_REQ_GEN1 &&
4353                                 phm_get_current_pcie_speed(hwmgr) > 0)
4354                         return 0;
4355
4356                 if (acpi_pcie_perf_request(hwmgr->device, request, false)) {
4357                         if (PP_PCIEGen2 == target_link_speed)
4358                                 printk("PSPP request to switch to Gen2 from Gen3 Failed!");
4359                         else
4360                                 printk("PSPP request to switch to Gen1 from Gen2 Failed!");
4361                 }
4362         }
4363
4364         return 0;
4365 }
4366
4367 static int polaris10_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input)
4368 {
4369         int tmp_result, result = 0;
4370         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4371
4372         tmp_result = polaris10_find_dpm_states_clocks_in_dpm_table(hwmgr, input);
4373         PP_ASSERT_WITH_CODE((0 == tmp_result),
4374                         "Failed to find DPM states clocks in DPM table!",
4375                         result = tmp_result);
4376
4377         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4378                         PHM_PlatformCaps_PCIEPerformanceRequest)) {
4379                 tmp_result =
4380                         polaris10_request_link_speed_change_before_state_change(hwmgr, input);
4381                 PP_ASSERT_WITH_CODE((0 == tmp_result),
4382                                 "Failed to request link speed change before state change!",
4383                                 result = tmp_result);
4384         }
4385
4386         tmp_result = polaris10_freeze_sclk_mclk_dpm(hwmgr);
4387         PP_ASSERT_WITH_CODE((0 == tmp_result),
4388                         "Failed to freeze SCLK MCLK DPM!", result = tmp_result);
4389
4390         tmp_result = polaris10_populate_and_upload_sclk_mclk_dpm_levels(hwmgr, input);
4391         PP_ASSERT_WITH_CODE((0 == tmp_result),
4392                         "Failed to populate and upload SCLK MCLK DPM levels!",
4393                         result = tmp_result);
4394
4395         tmp_result = polaris10_generate_dpm_level_enable_mask(hwmgr, input);
4396         PP_ASSERT_WITH_CODE((0 == tmp_result),
4397                         "Failed to generate DPM level enabled mask!",
4398                         result = tmp_result);
4399
4400         tmp_result = polaris10_update_vce_dpm(hwmgr, input);
4401         PP_ASSERT_WITH_CODE((0 == tmp_result),
4402                         "Failed to update VCE DPM!",
4403                         result = tmp_result);
4404
4405         tmp_result = polaris10_update_sclk_threshold(hwmgr);
4406         PP_ASSERT_WITH_CODE((0 == tmp_result),
4407                         "Failed to update SCLK threshold!",
4408                         result = tmp_result);
4409
4410         tmp_result = polaris10_program_mem_timing_parameters(hwmgr);
4411         PP_ASSERT_WITH_CODE((0 == tmp_result),
4412                         "Failed to program memory timing parameters!",
4413                         result = tmp_result);
4414
4415         tmp_result = polaris10_unfreeze_sclk_mclk_dpm(hwmgr);
4416         PP_ASSERT_WITH_CODE((0 == tmp_result),
4417                         "Failed to unfreeze SCLK MCLK DPM!",
4418                         result = tmp_result);
4419
4420         tmp_result = polaris10_upload_dpm_level_enable_mask(hwmgr);
4421         PP_ASSERT_WITH_CODE((0 == tmp_result),
4422                         "Failed to upload DPM level enabled mask!",
4423                         result = tmp_result);
4424
4425         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4426                         PHM_PlatformCaps_PCIEPerformanceRequest)) {
4427                 tmp_result =
4428                         polaris10_notify_link_speed_change_after_state_change(hwmgr, input);
4429                 PP_ASSERT_WITH_CODE((0 == tmp_result),
4430                                 "Failed to notify link speed change after state change!",
4431                                 result = tmp_result);
4432         }
4433         data->apply_optimized_settings = false;
4434         return result;
4435 }
4436
4437 static int polaris10_set_max_fan_pwm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm)
4438 {
4439         hwmgr->thermal_controller.
4440         advanceFanControlParameters.usMaxFanPWM = us_max_fan_pwm;
4441
4442         if (phm_is_hw_access_blocked(hwmgr))
4443                 return 0;
4444
4445         return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4446                         PPSMC_MSG_SetFanPwmMax, us_max_fan_pwm);
4447 }
4448
4449 int polaris10_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display)
4450 {
4451         PPSMC_Msg msg = has_display ? (PPSMC_Msg)PPSMC_HasDisplay : (PPSMC_Msg)PPSMC_NoDisplay;
4452
4453         return (smum_send_msg_to_smc(hwmgr->smumgr, msg) == 0) ?  0 : -1;
4454 }
4455
4456 int polaris10_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
4457 {
4458         uint32_t num_active_displays = 0;
4459         struct cgs_display_info info = {0};
4460         info.mode_info = NULL;
4461
4462         cgs_get_active_displays_info(hwmgr->device, &info);
4463
4464         num_active_displays = info.display_count;
4465
4466         if (num_active_displays > 1)  /* to do && (pHwMgr->pPECI->displayConfiguration.bMultiMonitorInSync != TRUE)) */
4467                 polaris10_notify_smc_display_change(hwmgr, false);
4468         else
4469                 polaris10_notify_smc_display_change(hwmgr, true);
4470
4471         return 0;
4472 }
4473
4474 /**
4475 * Programs the display gap
4476 *
4477 * @param    hwmgr  the address of the powerplay hardware manager.
4478 * @return   always OK
4479 */
4480 int polaris10_program_display_gap(struct pp_hwmgr *hwmgr)
4481 {
4482         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4483         uint32_t num_active_displays = 0;
4484         uint32_t display_gap = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL);
4485         uint32_t display_gap2;
4486         uint32_t pre_vbi_time_in_us;
4487         uint32_t frame_time_in_us;
4488         uint32_t ref_clock;
4489         uint32_t refresh_rate = 0;
4490         struct cgs_display_info info = {0};
4491         struct cgs_mode_info mode_info;
4492
4493         info.mode_info = &mode_info;
4494
4495         cgs_get_active_displays_info(hwmgr->device, &info);
4496         num_active_displays = info.display_count;
4497
4498         display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL, DISP_GAP, (num_active_displays > 0) ? DISPLAY_GAP_VBLANK_OR_WM : DISPLAY_GAP_IGNORE);
4499         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL, display_gap);
4500
4501         ref_clock = mode_info.ref_clock;
4502         refresh_rate = mode_info.refresh_rate;
4503
4504         if (0 == refresh_rate)
4505                 refresh_rate = 60;
4506
4507         frame_time_in_us = 1000000 / refresh_rate;
4508
4509         pre_vbi_time_in_us = frame_time_in_us - 200 - mode_info.vblank_time_us;
4510         display_gap2 = pre_vbi_time_in_us * (ref_clock / 100);
4511
4512         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL2, display_gap2);
4513
4514         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start + offsetof(SMU74_SoftRegisters, PreVBlankGap), 0x64);
4515
4516         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start + offsetof(SMU74_SoftRegisters, VBlankTimeout), (frame_time_in_us - pre_vbi_time_in_us));
4517
4518         polaris10_notify_smc_display_change(hwmgr, num_active_displays != 0);
4519
4520         return 0;
4521 }
4522
4523
4524 int polaris10_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
4525 {
4526         return polaris10_program_display_gap(hwmgr);
4527 }
4528
4529 /**
4530 *  Set maximum target operating fan output RPM
4531 *
4532 * @param    hwmgr:  the address of the powerplay hardware manager.
4533 * @param    usMaxFanRpm:  max operating fan RPM value.
4534 * @return   The response that came from the SMC.
4535 */
4536 static int polaris10_set_max_fan_rpm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_rpm)
4537 {
4538         hwmgr->thermal_controller.
4539         advanceFanControlParameters.usMaxFanRPM = us_max_fan_rpm;
4540
4541         if (phm_is_hw_access_blocked(hwmgr))
4542                 return 0;
4543
4544         return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4545                         PPSMC_MSG_SetFanRpmMax, us_max_fan_rpm);
4546 }
4547
4548 int polaris10_register_internal_thermal_interrupt(struct pp_hwmgr *hwmgr,
4549                                         const void *thermal_interrupt_info)
4550 {
4551         return 0;
4552 }
4553
4554 bool polaris10_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
4555 {
4556         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4557         bool is_update_required = false;
4558         struct cgs_display_info info = {0, 0, NULL};
4559
4560         cgs_get_active_displays_info(hwmgr->device, &info);
4561
4562         if (data->display_timing.num_existing_displays != info.display_count)
4563                 is_update_required = true;
4564 /* TO DO NEED TO GET DEEP SLEEP CLOCK FROM DAL
4565         if (phm_cap_enabled(hwmgr->hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
4566                 cgs_get_min_clock_settings(hwmgr->device, &min_clocks);
4567                 if (min_clocks.engineClockInSR != data->display_timing.minClockInSR &&
4568                         (min_clocks.engineClockInSR >= POLARIS10_MINIMUM_ENGINE_CLOCK ||
4569                                 data->display_timing.minClockInSR >= POLARIS10_MINIMUM_ENGINE_CLOCK))
4570                         is_update_required = true;
4571 */
4572         return is_update_required;
4573 }
4574
4575 static inline bool polaris10_are_power_levels_equal(const struct polaris10_performance_level *pl1,
4576                                                            const struct polaris10_performance_level *pl2)
4577 {
4578         return ((pl1->memory_clock == pl2->memory_clock) &&
4579                   (pl1->engine_clock == pl2->engine_clock) &&
4580                   (pl1->pcie_gen == pl2->pcie_gen) &&
4581                   (pl1->pcie_lane == pl2->pcie_lane));
4582 }
4583
4584 int polaris10_check_states_equal(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *pstate1, const struct pp_hw_power_state *pstate2, bool *equal)
4585 {
4586         const struct polaris10_power_state *psa = cast_const_phw_polaris10_power_state(pstate1);
4587         const struct polaris10_power_state *psb = cast_const_phw_polaris10_power_state(pstate2);
4588         int i;
4589
4590         if (pstate1 == NULL || pstate2 == NULL || equal == NULL)
4591                 return -EINVAL;
4592
4593         /* If the two states don't even have the same number of performance levels they cannot be the same state. */
4594         if (psa->performance_level_count != psb->performance_level_count) {
4595                 *equal = false;
4596                 return 0;
4597         }
4598
4599         for (i = 0; i < psa->performance_level_count; i++) {
4600                 if (!polaris10_are_power_levels_equal(&(psa->performance_levels[i]), &(psb->performance_levels[i]))) {
4601                         /* If we have found even one performance level pair that is different the states are different. */
4602                         *equal = false;
4603                         return 0;
4604                 }
4605         }
4606
4607         /* If all performance levels are the same try to use the UVD clocks to break the tie.*/
4608         *equal = ((psa->uvd_clks.vclk == psb->uvd_clks.vclk) && (psa->uvd_clks.dclk == psb->uvd_clks.dclk));
4609         *equal &= ((psa->vce_clks.evclk == psb->vce_clks.evclk) && (psa->vce_clks.ecclk == psb->vce_clks.ecclk));
4610         *equal &= (psa->sclk_threshold == psb->sclk_threshold);
4611
4612         return 0;
4613 }
4614
4615 int polaris10_upload_mc_firmware(struct pp_hwmgr *hwmgr)
4616 {
4617         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4618
4619         uint32_t vbios_version;
4620
4621         /*  Read MC indirect register offset 0x9F bits [3:0] to see if VBIOS has already loaded a full version of MC ucode or not.*/
4622
4623         phm_get_mc_microcode_version(hwmgr);
4624         vbios_version = hwmgr->microcode_version_info.MC & 0xf;
4625         /*  Full version of MC ucode has already been loaded. */
4626         if (vbios_version == 0) {
4627                 data->need_long_memory_training = false;
4628                 return 0;
4629         }
4630
4631         data->need_long_memory_training = true;
4632
4633 /*
4634  *      PPMCME_FirmwareDescriptorEntry *pfd = NULL;
4635         pfd = &tonga_mcmeFirmware;
4636         if (0 == PHM_READ_FIELD(hwmgr->device, MC_SEQ_SUP_CNTL, RUN))
4637                 polaris10_load_mc_microcode(hwmgr, pfd->dpmThreshold,
4638                                         pfd->cfgArray, pfd->cfgSize, pfd->ioDebugArray,
4639                                         pfd->ioDebugSize, pfd->ucodeArray, pfd->ucodeSize);
4640 */
4641         return 0;
4642 }
4643
4644 /**
4645  * Read clock related registers.
4646  *
4647  * @param    hwmgr  the address of the powerplay hardware manager.
4648  * @return   always 0
4649  */
4650 static int polaris10_read_clock_registers(struct pp_hwmgr *hwmgr)
4651 {
4652         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4653
4654         data->clock_registers.vCG_SPLL_FUNC_CNTL = cgs_read_ind_register(hwmgr->device,
4655                                                 CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL)
4656                                                 & CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK;
4657
4658         data->clock_registers.vCG_SPLL_FUNC_CNTL_2 = cgs_read_ind_register(hwmgr->device,
4659                                                 CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_2)
4660                                                 & CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL_MASK;
4661
4662         data->clock_registers.vCG_SPLL_FUNC_CNTL_4 = cgs_read_ind_register(hwmgr->device,
4663                                                 CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_4)
4664                                                 & CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_MASK;
4665
4666         return 0;
4667 }
4668
4669 /**
4670  * Find out if memory is GDDR5.
4671  *
4672  * @param    hwmgr  the address of the powerplay hardware manager.
4673  * @return   always 0
4674  */
4675 static int polaris10_get_memory_type(struct pp_hwmgr *hwmgr)
4676 {
4677         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4678         uint32_t temp;
4679
4680         temp = cgs_read_register(hwmgr->device, mmMC_SEQ_MISC0);
4681
4682         data->is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE ==
4683                         ((temp & MC_SEQ_MISC0_GDDR5_MASK) >>
4684                          MC_SEQ_MISC0_GDDR5_SHIFT));
4685
4686         return 0;
4687 }
4688
4689 /**
4690  * Enables Dynamic Power Management by SMC
4691  *
4692  * @param    hwmgr  the address of the powerplay hardware manager.
4693  * @return   always 0
4694  */
4695 static int polaris10_enable_acpi_power_management(struct pp_hwmgr *hwmgr)
4696 {
4697         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
4698                         GENERAL_PWRMGT, STATIC_PM_EN, 1);
4699
4700         return 0;
4701 }
4702
4703 /**
4704  * Initialize PowerGating States for different engines
4705  *
4706  * @param    hwmgr  the address of the powerplay hardware manager.
4707  * @return   always 0
4708  */
4709 static int polaris10_init_power_gate_state(struct pp_hwmgr *hwmgr)
4710 {
4711         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4712
4713         data->uvd_power_gated = false;
4714         data->vce_power_gated = false;
4715         data->samu_power_gated = false;
4716
4717         return 0;
4718 }
4719
4720 static int polaris10_init_sclk_threshold(struct pp_hwmgr *hwmgr)
4721 {
4722         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4723         data->low_sclk_interrupt_threshold = 0;
4724
4725         return 0;
4726 }
4727
4728 int polaris10_setup_asic_task(struct pp_hwmgr *hwmgr)
4729 {
4730         int tmp_result, result = 0;
4731
4732         polaris10_upload_mc_firmware(hwmgr);
4733
4734         tmp_result = polaris10_read_clock_registers(hwmgr);
4735         PP_ASSERT_WITH_CODE((0 == tmp_result),
4736                         "Failed to read clock registers!", result = tmp_result);
4737
4738         tmp_result = polaris10_get_memory_type(hwmgr);
4739         PP_ASSERT_WITH_CODE((0 == tmp_result),
4740                         "Failed to get memory type!", result = tmp_result);
4741
4742         tmp_result = polaris10_enable_acpi_power_management(hwmgr);
4743         PP_ASSERT_WITH_CODE((0 == tmp_result),
4744                         "Failed to enable ACPI power management!", result = tmp_result);
4745
4746         tmp_result = polaris10_init_power_gate_state(hwmgr);
4747         PP_ASSERT_WITH_CODE((0 == tmp_result),
4748                         "Failed to init power gate state!", result = tmp_result);
4749
4750         tmp_result = phm_get_mc_microcode_version(hwmgr);
4751         PP_ASSERT_WITH_CODE((0 == tmp_result),
4752                         "Failed to get MC microcode version!", result = tmp_result);
4753
4754         tmp_result = polaris10_init_sclk_threshold(hwmgr);
4755         PP_ASSERT_WITH_CODE((0 == tmp_result),
4756                         "Failed to init sclk threshold!", result = tmp_result);
4757
4758         return result;
4759 }
4760
4761 static int polaris10_get_pp_table(struct pp_hwmgr *hwmgr, char **table)
4762 {
4763         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4764
4765         if (!data->soft_pp_table) {
4766                 data->soft_pp_table = kmemdup(hwmgr->soft_pp_table,
4767                                               hwmgr->soft_pp_table_size,
4768                                               GFP_KERNEL);
4769                 if (!data->soft_pp_table)
4770                         return -ENOMEM;
4771         }
4772
4773         *table = (char *)&data->soft_pp_table;
4774
4775         return hwmgr->soft_pp_table_size;
4776 }
4777
4778 static int polaris10_set_pp_table(struct pp_hwmgr *hwmgr, const char *buf, size_t size)
4779 {
4780         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4781
4782         if (!data->soft_pp_table) {
4783                 data->soft_pp_table = kzalloc(hwmgr->soft_pp_table_size, GFP_KERNEL);
4784                 if (!data->soft_pp_table)
4785                         return -ENOMEM;
4786         }
4787
4788         memcpy(data->soft_pp_table, buf, size);
4789
4790         hwmgr->soft_pp_table = data->soft_pp_table;
4791
4792         /* TODO: re-init powerplay to implement modified pptable */
4793
4794         return 0;
4795 }
4796
4797 static int polaris10_force_clock_level(struct pp_hwmgr *hwmgr,
4798                 enum pp_clock_type type, uint32_t mask)
4799 {
4800         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4801
4802         if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
4803                 return -EINVAL;
4804
4805         switch (type) {
4806         case PP_SCLK:
4807                 if (!data->sclk_dpm_key_disabled)
4808                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4809                                         PPSMC_MSG_SCLKDPM_SetEnabledMask,
4810                                         data->dpm_level_enable_mask.sclk_dpm_enable_mask & mask);
4811                 break;
4812         case PP_MCLK:
4813                 if (!data->mclk_dpm_key_disabled)
4814                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4815                                         PPSMC_MSG_MCLKDPM_SetEnabledMask,
4816                                         data->dpm_level_enable_mask.mclk_dpm_enable_mask & mask);
4817                 break;
4818         case PP_PCIE:
4819         {
4820                 uint32_t tmp = mask & data->dpm_level_enable_mask.pcie_dpm_enable_mask;
4821                 uint32_t level = 0;
4822
4823                 while (tmp >>= 1)
4824                         level++;
4825
4826                 if (!data->pcie_dpm_key_disabled)
4827                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4828                                         PPSMC_MSG_PCIeDPM_ForceLevel,
4829                                         level);
4830                 break;
4831         }
4832         default:
4833                 break;
4834         }
4835
4836         return 0;
4837 }
4838
4839 static uint16_t polaris10_get_current_pcie_speed(struct pp_hwmgr *hwmgr)
4840 {
4841         uint32_t speedCntl = 0;
4842
4843         /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
4844         speedCntl = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__PCIE,
4845                         ixPCIE_LC_SPEED_CNTL);
4846         return((uint16_t)PHM_GET_FIELD(speedCntl,
4847                         PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE));
4848 }
4849
4850 static int polaris10_print_clock_levels(struct pp_hwmgr *hwmgr,
4851                 enum pp_clock_type type, char *buf)
4852 {
4853         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4854         struct polaris10_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
4855         struct polaris10_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
4856         struct polaris10_single_dpm_table *pcie_table = &(data->dpm_table.pcie_speed_table);
4857         int i, now, size = 0;
4858         uint32_t clock, pcie_speed;
4859
4860         switch (type) {
4861         case PP_SCLK:
4862                 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency);
4863                 clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
4864
4865                 for (i = 0; i < sclk_table->count; i++) {
4866                         if (clock > sclk_table->dpm_levels[i].value)
4867                                 continue;
4868                         break;
4869                 }
4870                 now = i;
4871
4872                 for (i = 0; i < sclk_table->count; i++)
4873                         size += sprintf(buf + size, "%d: %uMhz %s\n",
4874                                         i, sclk_table->dpm_levels[i].value / 100,
4875                                         (i == now) ? "*" : "");
4876                 break;
4877         case PP_MCLK:
4878                 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency);
4879                 clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
4880
4881                 for (i = 0; i < mclk_table->count; i++) {
4882                         if (clock > mclk_table->dpm_levels[i].value)
4883                                 continue;
4884                         break;
4885                 }
4886                 now = i;
4887
4888                 for (i = 0; i < mclk_table->count; i++)
4889                         size += sprintf(buf + size, "%d: %uMhz %s\n",
4890                                         i, mclk_table->dpm_levels[i].value / 100,
4891                                         (i == now) ? "*" : "");
4892                 break;
4893         case PP_PCIE:
4894                 pcie_speed = polaris10_get_current_pcie_speed(hwmgr);
4895                 for (i = 0; i < pcie_table->count; i++) {
4896                         if (pcie_speed != pcie_table->dpm_levels[i].value)
4897                                 continue;
4898                         break;
4899                 }
4900                 now = i;
4901
4902                 for (i = 0; i < pcie_table->count; i++)
4903                         size += sprintf(buf + size, "%d: %s %s\n", i,
4904                                         (pcie_table->dpm_levels[i].value == 0) ? "2.5GB, x8" :
4905                                         (pcie_table->dpm_levels[i].value == 1) ? "5.0GB, x16" :
4906                                         (pcie_table->dpm_levels[i].value == 2) ? "8.0GB, x16" : "",
4907                                         (i == now) ? "*" : "");
4908                 break;
4909         default:
4910                 break;
4911         }
4912         return size;
4913 }
4914
4915 static int polaris10_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
4916 {
4917         if (mode) {
4918                 /* stop auto-manage */
4919                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4920                                 PHM_PlatformCaps_MicrocodeFanControl))
4921                         polaris10_fan_ctrl_stop_smc_fan_control(hwmgr);
4922                 polaris10_fan_ctrl_set_static_mode(hwmgr, mode);
4923         } else
4924                 /* restart auto-manage */
4925                 polaris10_fan_ctrl_reset_fan_speed_to_default(hwmgr);
4926
4927         return 0;
4928 }
4929
4930 static int polaris10_get_fan_control_mode(struct pp_hwmgr *hwmgr)
4931 {
4932         if (hwmgr->fan_ctrl_is_in_default_mode)
4933                 return hwmgr->fan_ctrl_default_mode;
4934         else
4935                 return PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
4936                                 CG_FDO_CTRL2, FDO_PWM_MODE);
4937 }
4938
4939 static int polaris10_get_sclk_od(struct pp_hwmgr *hwmgr)
4940 {
4941         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4942         struct polaris10_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
4943         struct polaris10_single_dpm_table *golden_sclk_table =
4944                         &(data->golden_dpm_table.sclk_table);
4945         int value;
4946
4947         value = (sclk_table->dpm_levels[sclk_table->count - 1].value -
4948                         golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value) *
4949                         100 /
4950                         golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value;
4951
4952         return value;
4953 }
4954
4955 static int polaris10_set_sclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
4956 {
4957         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4958         struct polaris10_single_dpm_table *golden_sclk_table =
4959                         &(data->golden_dpm_table.sclk_table);
4960         struct pp_power_state  *ps;
4961         struct polaris10_power_state  *polaris10_ps;
4962
4963         if (value > 20)
4964                 value = 20;
4965
4966         ps = hwmgr->request_ps;
4967
4968         if (ps == NULL)
4969                 return -EINVAL;
4970
4971         polaris10_ps = cast_phw_polaris10_power_state(&ps->hardware);
4972
4973         polaris10_ps->performance_levels[polaris10_ps->performance_level_count - 1].engine_clock =
4974                         golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value *
4975                         value / 100 +
4976                         golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value;
4977
4978         return 0;
4979 }
4980
4981 static const struct pp_hwmgr_func polaris10_hwmgr_funcs = {
4982         .backend_init = &polaris10_hwmgr_backend_init,
4983         .backend_fini = &polaris10_hwmgr_backend_fini,
4984         .asic_setup = &polaris10_setup_asic_task,
4985         .dynamic_state_management_enable = &polaris10_enable_dpm_tasks,
4986         .apply_state_adjust_rules = polaris10_apply_state_adjust_rules,
4987         .force_dpm_level = &polaris10_force_dpm_level,
4988         .power_state_set = polaris10_set_power_state_tasks,
4989         .get_power_state_size = polaris10_get_power_state_size,
4990         .get_mclk = polaris10_dpm_get_mclk,
4991         .get_sclk = polaris10_dpm_get_sclk,
4992         .patch_boot_state = polaris10_dpm_patch_boot_state,
4993         .get_pp_table_entry = polaris10_get_pp_table_entry,
4994         .get_num_of_pp_table_entries = tonga_get_number_of_powerplay_table_entries,
4995         .print_current_perforce_level = polaris10_print_current_perforce_level,
4996         .powerdown_uvd = polaris10_phm_powerdown_uvd,
4997         .powergate_uvd = polaris10_phm_powergate_uvd,
4998         .powergate_vce = polaris10_phm_powergate_vce,
4999         .disable_clock_power_gating = polaris10_phm_disable_clock_power_gating,
5000         .update_clock_gatings = polaris10_phm_update_clock_gatings,
5001         .notify_smc_display_config_after_ps_adjustment = polaris10_notify_smc_display_config_after_ps_adjustment,
5002         .display_config_changed = polaris10_display_configuration_changed_task,
5003         .set_max_fan_pwm_output = polaris10_set_max_fan_pwm_output,
5004         .set_max_fan_rpm_output = polaris10_set_max_fan_rpm_output,
5005         .get_temperature = polaris10_thermal_get_temperature,
5006         .stop_thermal_controller = polaris10_thermal_stop_thermal_controller,
5007         .get_fan_speed_info = polaris10_fan_ctrl_get_fan_speed_info,
5008         .get_fan_speed_percent = polaris10_fan_ctrl_get_fan_speed_percent,
5009         .set_fan_speed_percent = polaris10_fan_ctrl_set_fan_speed_percent,
5010         .reset_fan_speed_to_default = polaris10_fan_ctrl_reset_fan_speed_to_default,
5011         .get_fan_speed_rpm = polaris10_fan_ctrl_get_fan_speed_rpm,
5012         .set_fan_speed_rpm = polaris10_fan_ctrl_set_fan_speed_rpm,
5013         .uninitialize_thermal_controller = polaris10_thermal_ctrl_uninitialize_thermal_controller,
5014         .register_internal_thermal_interrupt = polaris10_register_internal_thermal_interrupt,
5015         .check_smc_update_required_for_display_configuration = polaris10_check_smc_update_required_for_display_configuration,
5016         .check_states_equal = polaris10_check_states_equal,
5017         .set_fan_control_mode = polaris10_set_fan_control_mode,
5018         .get_fan_control_mode = polaris10_get_fan_control_mode,
5019         .get_pp_table = polaris10_get_pp_table,
5020         .set_pp_table = polaris10_set_pp_table,
5021         .force_clock_level = polaris10_force_clock_level,
5022         .print_clock_levels = polaris10_print_clock_levels,
5023         .enable_per_cu_power_gating = polaris10_phm_enable_per_cu_power_gating,
5024         .get_sclk_od = polaris10_get_sclk_od,
5025         .set_sclk_od = polaris10_set_sclk_od,
5026 };
5027
5028 int polaris10_hwmgr_init(struct pp_hwmgr *hwmgr)
5029 {
5030         struct polaris10_hwmgr  *data;
5031
5032         data = kzalloc (sizeof(struct polaris10_hwmgr), GFP_KERNEL);
5033         if (data == NULL)
5034                 return -ENOMEM;
5035
5036         hwmgr->backend = data;
5037         hwmgr->hwmgr_func = &polaris10_hwmgr_funcs;
5038         hwmgr->pptable_func = &tonga_pptable_funcs;
5039         pp_polaris10_thermal_initialize(hwmgr);
5040
5041         return 0;
5042 }