2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/module.h>
24 #include <linux/slab.h>
26 #include <asm/div64.h>
27 #include "linux/delay.h"
30 #include "polaris10_hwmgr.h"
31 #include "polaris10_powertune.h"
32 #include "polaris10_dyn_defaults.h"
33 #include "polaris10_smumgr.h"
35 #include "ppatomctrl.h"
37 #include "tonga_pptable.h"
38 #include "pppcielanes.h"
39 #include "amd_pcie_helpers.h"
40 #include "hardwaremanager.h"
41 #include "tonga_processpptables.h"
42 #include "cgs_common.h"
44 #include "smu_ucode_xfer_vi.h"
45 #include "smu74_discrete.h"
46 #include "smu/smu_7_1_3_d.h"
47 #include "smu/smu_7_1_3_sh_mask.h"
48 #include "gmc/gmc_8_1_d.h"
49 #include "gmc/gmc_8_1_sh_mask.h"
50 #include "oss/oss_3_0_d.h"
51 #include "gca/gfx_8_0_d.h"
52 #include "bif/bif_5_0_d.h"
53 #include "bif/bif_5_0_sh_mask.h"
54 #include "gmc/gmc_8_1_d.h"
55 #include "gmc/gmc_8_1_sh_mask.h"
56 #include "bif/bif_5_0_d.h"
57 #include "bif/bif_5_0_sh_mask.h"
58 #include "dce/dce_10_0_d.h"
59 #include "dce/dce_10_0_sh_mask.h"
61 #include "polaris10_thermal.h"
62 #include "polaris10_clockpowergating.h"
64 #define MC_CG_ARB_FREQ_F0 0x0a
65 #define MC_CG_ARB_FREQ_F1 0x0b
66 #define MC_CG_ARB_FREQ_F2 0x0c
67 #define MC_CG_ARB_FREQ_F3 0x0d
69 #define MC_CG_SEQ_DRAMCONF_S0 0x05
70 #define MC_CG_SEQ_DRAMCONF_S1 0x06
71 #define MC_CG_SEQ_YCLK_SUSPEND 0x04
72 #define MC_CG_SEQ_YCLK_RESUME 0x0a
75 #define SMC_RAM_END 0x40000
77 #define SMC_CG_IND_START 0xc0030000
78 #define SMC_CG_IND_END 0xc0040000
80 #define VOLTAGE_SCALE 4
81 #define VOLTAGE_VID_OFFSET_SCALE1 625
82 #define VOLTAGE_VID_OFFSET_SCALE2 100
84 #define VDDC_VDDCI_DELTA 200
86 #define MEM_FREQ_LOW_LATENCY 25000
87 #define MEM_FREQ_HIGH_LATENCY 80000
89 #define MEM_LATENCY_HIGH 45
90 #define MEM_LATENCY_LOW 35
91 #define MEM_LATENCY_ERR 0xFFFF
93 #define MC_SEQ_MISC0_GDDR5_SHIFT 28
94 #define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000
95 #define MC_SEQ_MISC0_GDDR5_VALUE 5
98 #define PCIE_BUS_CLK 10000
99 #define TCLK (PCIE_BUS_CLK / 10)
102 static const uint16_t polaris10_clock_stretcher_lookup_table[2][4] =
103 { {600, 1050, 3, 0}, {600, 1050, 6, 1} };
105 /* [FF, SS] type, [] 4 voltage ranges, and [Floor Freq, Boundary Freq, VID min , VID max] */
106 static const uint32_t polaris10_clock_stretcher_ddt_table[2][4][4] =
107 { { {265, 529, 120, 128}, {325, 650, 96, 119}, {430, 860, 32, 95}, {0, 0, 0, 31} },
108 { {275, 550, 104, 112}, {319, 638, 96, 103}, {360, 720, 64, 95}, {384, 768, 32, 63} } };
110 /* [Use_For_Low_freq] value, [0%, 5%, 10%, 7.14%, 14.28%, 20%] (coming from PWR_CKS_CNTL.stretch_amount reg spec) */
111 static const uint8_t polaris10_clock_stretch_amount_conversion[2][6] =
112 { {0, 1, 3, 2, 4, 5}, {0, 2, 4, 5, 6, 5} };
114 /** Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */
116 DPM_EVENT_SRC_ANALOG = 0,
117 DPM_EVENT_SRC_EXTERNAL = 1,
118 DPM_EVENT_SRC_DIGITAL = 2,
119 DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
120 DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL = 4
123 static const unsigned long PhwPolaris10_Magic = (unsigned long)(PHM_VIslands_Magic);
125 struct polaris10_power_state *cast_phw_polaris10_power_state(
126 struct pp_hw_power_state *hw_ps)
128 PP_ASSERT_WITH_CODE((PhwPolaris10_Magic == hw_ps->magic),
129 "Invalid Powerstate Type!",
132 return (struct polaris10_power_state *)hw_ps;
135 const struct polaris10_power_state *cast_const_phw_polaris10_power_state(
136 const struct pp_hw_power_state *hw_ps)
138 PP_ASSERT_WITH_CODE((PhwPolaris10_Magic == hw_ps->magic),
139 "Invalid Powerstate Type!",
142 return (const struct polaris10_power_state *)hw_ps;
145 static bool polaris10_is_dpm_running(struct pp_hwmgr *hwmgr)
147 return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device,
148 CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON))
153 * Find the MC microcode version and store it in the HwMgr struct
155 * @param hwmgr the address of the powerplay hardware manager.
158 int phm_get_mc_microcode_version (struct pp_hwmgr *hwmgr)
160 cgs_write_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_INDEX, 0x9F);
162 hwmgr->microcode_version_info.MC = cgs_read_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_DATA);
167 uint16_t phm_get_current_pcie_speed(struct pp_hwmgr *hwmgr)
169 uint32_t speedCntl = 0;
171 /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
172 speedCntl = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__PCIE,
173 ixPCIE_LC_SPEED_CNTL);
174 return((uint16_t)PHM_GET_FIELD(speedCntl,
175 PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE));
178 int phm_get_current_pcie_lane_number(struct pp_hwmgr *hwmgr)
182 /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
183 link_width = PHM_READ_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
184 PCIE_LC_LINK_WIDTH_CNTL, LC_LINK_WIDTH_RD);
186 PP_ASSERT_WITH_CODE((7 >= link_width),
187 "Invalid PCIe lane width!", return 0);
189 return decode_pcie_lane_width(link_width);
193 * Enable voltage control
195 * @param pHwMgr the address of the powerplay hardware manager.
196 * @return always PP_Result_OK
198 int polaris10_enable_smc_voltage_controller(struct pp_hwmgr *hwmgr)
201 (hwmgr->smumgr->smumgr_funcs->send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_Voltage_Cntl_Enable) == 0),
202 "Failed to enable voltage DPM during DPM Start Function!",
210 * Checks if we want to support voltage control
212 * @param hwmgr the address of the powerplay hardware manager.
214 static bool polaris10_voltage_control(const struct pp_hwmgr *hwmgr)
216 const struct polaris10_hwmgr *data =
217 (const struct polaris10_hwmgr *)(hwmgr->backend);
219 return (POLARIS10_VOLTAGE_CONTROL_NONE != data->voltage_control);
223 * Enable voltage control
225 * @param hwmgr the address of the powerplay hardware manager.
228 static int polaris10_enable_voltage_control(struct pp_hwmgr *hwmgr)
230 /* enable voltage control */
231 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
232 GENERAL_PWRMGT, VOLT_PWRMGT_EN, 1);
238 * Create Voltage Tables.
240 * @param hwmgr the address of the powerplay hardware manager.
243 static int polaris10_construct_voltage_tables(struct pp_hwmgr *hwmgr)
245 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
246 struct phm_ppt_v1_information *table_info =
247 (struct phm_ppt_v1_information *)hwmgr->pptable;
250 if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
251 result = atomctrl_get_voltage_table_v3(hwmgr,
252 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT,
253 &(data->mvdd_voltage_table));
254 PP_ASSERT_WITH_CODE((0 == result),
255 "Failed to retrieve MVDD table.",
257 } else if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
258 result = phm_get_svi2_mvdd_voltage_table(&(data->mvdd_voltage_table),
259 table_info->vdd_dep_on_mclk);
260 PP_ASSERT_WITH_CODE((0 == result),
261 "Failed to retrieve SVI2 MVDD table from dependancy table.",
265 if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
266 result = atomctrl_get_voltage_table_v3(hwmgr,
267 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT,
268 &(data->vddci_voltage_table));
269 PP_ASSERT_WITH_CODE((0 == result),
270 "Failed to retrieve VDDCI table.",
272 } else if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
273 result = phm_get_svi2_vddci_voltage_table(&(data->vddci_voltage_table),
274 table_info->vdd_dep_on_mclk);
275 PP_ASSERT_WITH_CODE((0 == result),
276 "Failed to retrieve SVI2 VDDCI table from dependancy table.",
280 if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
281 result = phm_get_svi2_vdd_voltage_table(&(data->vddc_voltage_table),
282 table_info->vddc_lookup_table);
283 PP_ASSERT_WITH_CODE((0 == result),
284 "Failed to retrieve SVI2 VDDC table from lookup table.",
289 (data->vddc_voltage_table.count <= (SMU74_MAX_LEVELS_VDDC)),
290 "Too many voltage values for VDDC. Trimming to fit state table.",
291 phm_trim_voltage_table_to_fit_state_table(SMU74_MAX_LEVELS_VDDC,
292 &(data->vddc_voltage_table)));
295 (data->vddci_voltage_table.count <= (SMU74_MAX_LEVELS_VDDCI)),
296 "Too many voltage values for VDDCI. Trimming to fit state table.",
297 phm_trim_voltage_table_to_fit_state_table(SMU74_MAX_LEVELS_VDDCI,
298 &(data->vddci_voltage_table)));
301 (data->mvdd_voltage_table.count <= (SMU74_MAX_LEVELS_MVDD)),
302 "Too many voltage values for MVDD. Trimming to fit state table.",
303 phm_trim_voltage_table_to_fit_state_table(SMU74_MAX_LEVELS_MVDD,
304 &(data->mvdd_voltage_table)));
310 * Programs static screed detection parameters
312 * @param hwmgr the address of the powerplay hardware manager.
315 static int polaris10_program_static_screen_threshold_parameters(
316 struct pp_hwmgr *hwmgr)
318 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
320 /* Set static screen threshold unit */
321 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
322 CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD_UNIT,
323 data->static_screen_threshold_unit);
324 /* Set static screen threshold */
325 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
326 CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD,
327 data->static_screen_threshold);
333 * Setup display gap for glitch free memory clock switching.
335 * @param hwmgr the address of the powerplay hardware manager.
338 static int polaris10_enable_display_gap(struct pp_hwmgr *hwmgr)
340 uint32_t display_gap =
341 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
342 ixCG_DISPLAY_GAP_CNTL);
344 display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL,
345 DISP_GAP, DISPLAY_GAP_IGNORE);
347 display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL,
348 DISP_GAP_MCHG, DISPLAY_GAP_VBLANK);
350 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
351 ixCG_DISPLAY_GAP_CNTL, display_gap);
357 * Programs activity state transition voting clients
359 * @param hwmgr the address of the powerplay hardware manager.
362 static int polaris10_program_voting_clients(struct pp_hwmgr *hwmgr)
364 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
366 /* Clear reset for voting clients before enabling DPM */
367 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
368 SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 0);
369 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
370 SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 0);
372 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
373 ixCG_FREQ_TRAN_VOTING_0, data->voting_rights_clients0);
374 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
375 ixCG_FREQ_TRAN_VOTING_1, data->voting_rights_clients1);
376 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
377 ixCG_FREQ_TRAN_VOTING_2, data->voting_rights_clients2);
378 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
379 ixCG_FREQ_TRAN_VOTING_3, data->voting_rights_clients3);
380 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
381 ixCG_FREQ_TRAN_VOTING_4, data->voting_rights_clients4);
382 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
383 ixCG_FREQ_TRAN_VOTING_5, data->voting_rights_clients5);
384 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
385 ixCG_FREQ_TRAN_VOTING_6, data->voting_rights_clients6);
386 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
387 ixCG_FREQ_TRAN_VOTING_7, data->voting_rights_clients7);
392 static int polaris10_clear_voting_clients(struct pp_hwmgr *hwmgr)
394 /* Reset voting clients before disabling DPM */
395 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
396 SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 1);
397 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
398 SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 1);
400 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
401 ixCG_FREQ_TRAN_VOTING_0, 0);
402 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
403 ixCG_FREQ_TRAN_VOTING_1, 0);
404 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
405 ixCG_FREQ_TRAN_VOTING_2, 0);
406 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
407 ixCG_FREQ_TRAN_VOTING_3, 0);
408 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
409 ixCG_FREQ_TRAN_VOTING_4, 0);
410 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
411 ixCG_FREQ_TRAN_VOTING_5, 0);
412 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
413 ixCG_FREQ_TRAN_VOTING_6, 0);
414 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
415 ixCG_FREQ_TRAN_VOTING_7, 0);
421 * Get the location of various tables inside the FW image.
423 * @param hwmgr the address of the powerplay hardware manager.
426 static int polaris10_process_firmware_header(struct pp_hwmgr *hwmgr)
428 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
429 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend);
434 result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
435 SMU7_FIRMWARE_HEADER_LOCATION +
436 offsetof(SMU74_Firmware_Header, DpmTable),
437 &tmp, data->sram_end);
440 data->dpm_table_start = tmp;
442 error |= (0 != result);
444 result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
445 SMU7_FIRMWARE_HEADER_LOCATION +
446 offsetof(SMU74_Firmware_Header, SoftRegisters),
447 &tmp, data->sram_end);
450 data->soft_regs_start = tmp;
451 smu_data->soft_regs_start = tmp;
454 error |= (0 != result);
456 result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
457 SMU7_FIRMWARE_HEADER_LOCATION +
458 offsetof(SMU74_Firmware_Header, mcRegisterTable),
459 &tmp, data->sram_end);
462 data->mc_reg_table_start = tmp;
464 result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
465 SMU7_FIRMWARE_HEADER_LOCATION +
466 offsetof(SMU74_Firmware_Header, FanTable),
467 &tmp, data->sram_end);
470 data->fan_table_start = tmp;
472 error |= (0 != result);
474 result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
475 SMU7_FIRMWARE_HEADER_LOCATION +
476 offsetof(SMU74_Firmware_Header, mcArbDramTimingTable),
477 &tmp, data->sram_end);
480 data->arb_table_start = tmp;
482 error |= (0 != result);
484 result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
485 SMU7_FIRMWARE_HEADER_LOCATION +
486 offsetof(SMU74_Firmware_Header, Version),
487 &tmp, data->sram_end);
490 hwmgr->microcode_version_info.SMC = tmp;
492 error |= (0 != result);
494 return error ? -1 : 0;
497 /* Copy one arb setting to another and then switch the active set.
498 * arb_src and arb_dest is one of the MC_CG_ARB_FREQ_Fx constants.
500 static int polaris10_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr,
501 uint32_t arb_src, uint32_t arb_dest)
503 uint32_t mc_arb_dram_timing;
504 uint32_t mc_arb_dram_timing2;
506 uint32_t mc_cg_config;
509 case MC_CG_ARB_FREQ_F0:
510 mc_arb_dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
511 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
512 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
514 case MC_CG_ARB_FREQ_F1:
515 mc_arb_dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1);
516 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1);
517 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1);
524 case MC_CG_ARB_FREQ_F0:
525 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING, mc_arb_dram_timing);
526 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
527 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0, burst_time);
529 case MC_CG_ARB_FREQ_F1:
530 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
531 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
532 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1, burst_time);
538 mc_cg_config = cgs_read_register(hwmgr->device, mmMC_CG_CONFIG);
539 mc_cg_config |= 0x0000000F;
540 cgs_write_register(hwmgr->device, mmMC_CG_CONFIG, mc_cg_config);
541 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_CG, CG_ARB_REQ, arb_dest);
546 static int polaris10_reset_to_default(struct pp_hwmgr *hwmgr)
548 return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_ResetToDefaults);
552 * Initial switch from ARB F0->F1
554 * @param hwmgr the address of the powerplay hardware manager.
556 * This function is to be called from the SetPowerState table.
558 static int polaris10_initial_switch_from_arbf0_to_f1(struct pp_hwmgr *hwmgr)
560 return polaris10_copy_and_switch_arb_sets(hwmgr,
561 MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
564 static int polaris10_force_switch_to_arbf0(struct pp_hwmgr *hwmgr)
568 tmp = (cgs_read_ind_register(hwmgr->device,
569 CGS_IND_REG__SMC, ixSMC_SCRATCH9) &
572 if (tmp == MC_CG_ARB_FREQ_F0)
575 return polaris10_copy_and_switch_arb_sets(hwmgr,
576 tmp, MC_CG_ARB_FREQ_F0);
579 static int polaris10_setup_default_pcie_table(struct pp_hwmgr *hwmgr)
581 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
582 struct phm_ppt_v1_information *table_info =
583 (struct phm_ppt_v1_information *)(hwmgr->pptable);
584 struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
585 uint32_t i, max_entry;
587 PP_ASSERT_WITH_CODE((data->use_pcie_performance_levels ||
588 data->use_pcie_power_saving_levels), "No pcie performance levels!",
591 if (data->use_pcie_performance_levels &&
592 !data->use_pcie_power_saving_levels) {
593 data->pcie_gen_power_saving = data->pcie_gen_performance;
594 data->pcie_lane_power_saving = data->pcie_lane_performance;
595 } else if (!data->use_pcie_performance_levels &&
596 data->use_pcie_power_saving_levels) {
597 data->pcie_gen_performance = data->pcie_gen_power_saving;
598 data->pcie_lane_performance = data->pcie_lane_power_saving;
601 phm_reset_single_dpm_table(&data->dpm_table.pcie_speed_table,
602 SMU74_MAX_LEVELS_LINK,
603 MAX_REGULAR_DPM_NUMBER);
605 if (pcie_table != NULL) {
606 /* max_entry is used to make sure we reserve one PCIE level
607 * for boot level (fix for A+A PSPP issue).
608 * If PCIE table from PPTable have ULV entry + 8 entries,
609 * then ignore the last entry.*/
610 max_entry = (SMU74_MAX_LEVELS_LINK < pcie_table->count) ?
611 SMU74_MAX_LEVELS_LINK : pcie_table->count;
612 for (i = 1; i < max_entry; i++) {
613 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i - 1,
614 get_pcie_gen_support(data->pcie_gen_cap,
615 pcie_table->entries[i].gen_speed),
616 get_pcie_lane_support(data->pcie_lane_cap,
617 pcie_table->entries[i].lane_width));
619 data->dpm_table.pcie_speed_table.count = max_entry - 1;
621 /* Setup BIF_SCLK levels */
622 for (i = 0; i < max_entry; i++)
623 data->bif_sclk_table[i] = pcie_table->entries[i].pcie_sclk;
625 /* Hardcode Pcie Table */
626 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 0,
627 get_pcie_gen_support(data->pcie_gen_cap,
629 get_pcie_lane_support(data->pcie_lane_cap,
631 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 1,
632 get_pcie_gen_support(data->pcie_gen_cap,
634 get_pcie_lane_support(data->pcie_lane_cap,
636 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 2,
637 get_pcie_gen_support(data->pcie_gen_cap,
639 get_pcie_lane_support(data->pcie_lane_cap,
641 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 3,
642 get_pcie_gen_support(data->pcie_gen_cap,
644 get_pcie_lane_support(data->pcie_lane_cap,
646 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 4,
647 get_pcie_gen_support(data->pcie_gen_cap,
649 get_pcie_lane_support(data->pcie_lane_cap,
651 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 5,
652 get_pcie_gen_support(data->pcie_gen_cap,
654 get_pcie_lane_support(data->pcie_lane_cap,
657 data->dpm_table.pcie_speed_table.count = 6;
659 /* Populate last level for boot PCIE level, but do not increment count. */
660 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table,
661 data->dpm_table.pcie_speed_table.count,
662 get_pcie_gen_support(data->pcie_gen_cap,
664 get_pcie_lane_support(data->pcie_lane_cap,
671 * This function is to initalize all DPM state tables
672 * for SMU7 based on the dependency table.
673 * Dynamic state patching function will then trim these
674 * state tables to the allowed range based
675 * on the power policy or external client requests,
676 * such as UVD request, etc.
678 int polaris10_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
680 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
681 struct phm_ppt_v1_information *table_info =
682 (struct phm_ppt_v1_information *)(hwmgr->pptable);
685 struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table =
686 table_info->vdd_dep_on_sclk;
687 struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
688 table_info->vdd_dep_on_mclk;
690 PP_ASSERT_WITH_CODE(dep_sclk_table != NULL,
691 "SCLK dependency table is missing. This table is mandatory",
693 PP_ASSERT_WITH_CODE(dep_sclk_table->count >= 1,
694 "SCLK dependency table has to have is missing."
695 "This table is mandatory",
698 PP_ASSERT_WITH_CODE(dep_mclk_table != NULL,
699 "MCLK dependency table is missing. This table is mandatory",
701 PP_ASSERT_WITH_CODE(dep_mclk_table->count >= 1,
702 "MCLK dependency table has to have is missing."
703 "This table is mandatory",
706 /* clear the state table to reset everything to default */
707 phm_reset_single_dpm_table(
708 &data->dpm_table.sclk_table, SMU74_MAX_LEVELS_GRAPHICS, MAX_REGULAR_DPM_NUMBER);
709 phm_reset_single_dpm_table(
710 &data->dpm_table.mclk_table, SMU74_MAX_LEVELS_MEMORY, MAX_REGULAR_DPM_NUMBER);
713 /* Initialize Sclk DPM table based on allow Sclk values */
714 data->dpm_table.sclk_table.count = 0;
715 for (i = 0; i < dep_sclk_table->count; i++) {
716 if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count - 1].value !=
717 dep_sclk_table->entries[i].clk) {
719 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value =
720 dep_sclk_table->entries[i].clk;
722 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled =
723 (i == 0) ? true : false;
724 data->dpm_table.sclk_table.count++;
728 /* Initialize Mclk DPM table based on allow Mclk values */
729 data->dpm_table.mclk_table.count = 0;
730 for (i = 0; i < dep_mclk_table->count; i++) {
731 if (i == 0 || data->dpm_table.mclk_table.dpm_levels
732 [data->dpm_table.mclk_table.count - 1].value !=
733 dep_mclk_table->entries[i].clk) {
734 data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value =
735 dep_mclk_table->entries[i].clk;
736 data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled =
737 (i == 0) ? true : false;
738 data->dpm_table.mclk_table.count++;
742 /* setup PCIE gen speed levels */
743 polaris10_setup_default_pcie_table(hwmgr);
745 /* save a copy of the default DPM table */
746 memcpy(&(data->golden_dpm_table), &(data->dpm_table),
747 sizeof(struct polaris10_dpm_table));
752 uint8_t convert_to_vid(uint16_t vddc)
754 return (uint8_t) ((6200 - (vddc * VOLTAGE_SCALE)) / 25);
758 * Mvdd table preparation for SMC.
760 * @param *hwmgr The address of the hardware manager.
761 * @param *table The SMC DPM table structure to be populated.
764 static int polaris10_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr,
765 SMU74_Discrete_DpmTable *table)
767 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
768 uint32_t count, level;
770 if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
771 count = data->mvdd_voltage_table.count;
772 if (count > SMU_MAX_SMIO_LEVELS)
773 count = SMU_MAX_SMIO_LEVELS;
774 for (level = 0; level < count; level++) {
775 table->SmioTable2.Pattern[level].Voltage =
776 PP_HOST_TO_SMC_US(data->mvdd_voltage_table.entries[count].value * VOLTAGE_SCALE);
777 /* Index into DpmTable.Smio. Drive bits from Smio entry to get this voltage level.*/
778 table->SmioTable2.Pattern[level].Smio =
780 table->Smio[level] |=
781 data->mvdd_voltage_table.entries[level].smio_low;
783 table->SmioMask2 = data->vddci_voltage_table.mask_low;
785 table->MvddLevelCount = (uint32_t) PP_HOST_TO_SMC_UL(count);
791 static int polaris10_populate_smc_vddci_table(struct pp_hwmgr *hwmgr,
792 struct SMU74_Discrete_DpmTable *table)
794 uint32_t count, level;
795 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
797 count = data->vddci_voltage_table.count;
799 if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
800 if (count > SMU_MAX_SMIO_LEVELS)
801 count = SMU_MAX_SMIO_LEVELS;
802 for (level = 0; level < count; ++level) {
803 table->SmioTable1.Pattern[level].Voltage =
804 PP_HOST_TO_SMC_US(data->vddci_voltage_table.entries[level].value * VOLTAGE_SCALE);
805 table->SmioTable1.Pattern[level].Smio = (uint8_t) level;
807 table->Smio[level] |= data->vddci_voltage_table.entries[level].smio_low;
811 table->SmioMask1 = data->vddci_voltage_table.mask_low;
817 * Preparation of vddc and vddgfx CAC tables for SMC.
819 * @param hwmgr the address of the hardware manager
820 * @param table the SMC DPM table structure to be populated
823 static int polaris10_populate_cac_table(struct pp_hwmgr *hwmgr,
824 struct SMU74_Discrete_DpmTable *table)
828 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
829 struct phm_ppt_v1_information *table_info =
830 (struct phm_ppt_v1_information *)(hwmgr->pptable);
831 struct phm_ppt_v1_voltage_lookup_table *lookup_table =
832 table_info->vddc_lookup_table;
833 /* tables is already swapped, so in order to use the value from it,
834 * we need to swap it back.
835 * We are populating vddc CAC data to BapmVddc table
836 * in split and merged mode
838 for (count = 0; count < lookup_table->count; count++) {
839 index = phm_get_voltage_index(lookup_table,
840 data->vddc_voltage_table.entries[count].value);
841 table->BapmVddcVidLoSidd[count] = convert_to_vid(lookup_table->entries[index].us_cac_low);
842 table->BapmVddcVidHiSidd[count] = convert_to_vid(lookup_table->entries[index].us_cac_mid);
843 table->BapmVddcVidHiSidd2[count] = convert_to_vid(lookup_table->entries[index].us_cac_high);
850 * Preparation of voltage tables for SMC.
852 * @param hwmgr the address of the hardware manager
853 * @param table the SMC DPM table structure to be populated
857 int polaris10_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
858 struct SMU74_Discrete_DpmTable *table)
860 polaris10_populate_smc_vddci_table(hwmgr, table);
861 polaris10_populate_smc_mvdd_table(hwmgr, table);
862 polaris10_populate_cac_table(hwmgr, table);
867 static int polaris10_populate_ulv_level(struct pp_hwmgr *hwmgr,
868 struct SMU74_Discrete_Ulv *state)
870 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
871 struct phm_ppt_v1_information *table_info =
872 (struct phm_ppt_v1_information *)(hwmgr->pptable);
874 state->CcPwrDynRm = 0;
875 state->CcPwrDynRm1 = 0;
877 state->VddcOffset = (uint16_t) table_info->us_ulv_voltage_offset;
878 state->VddcOffsetVid = (uint8_t)(table_info->us_ulv_voltage_offset *
879 VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
881 state->VddcPhase = (data->vddc_phase_shed_control) ? 0 : 1;
883 CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm);
884 CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm1);
885 CONVERT_FROM_HOST_TO_SMC_US(state->VddcOffset);
890 static int polaris10_populate_ulv_state(struct pp_hwmgr *hwmgr,
891 struct SMU74_Discrete_DpmTable *table)
893 return polaris10_populate_ulv_level(hwmgr, &table->Ulv);
896 static int polaris10_populate_smc_link_level(struct pp_hwmgr *hwmgr,
897 struct SMU74_Discrete_DpmTable *table)
899 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
900 struct polaris10_dpm_table *dpm_table = &data->dpm_table;
903 /* Index (dpm_table->pcie_speed_table.count)
904 * is reserved for PCIE boot level. */
905 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
906 table->LinkLevel[i].PcieGenSpeed =
907 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
908 table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width(
909 dpm_table->pcie_speed_table.dpm_levels[i].param1);
910 table->LinkLevel[i].EnabledForActivity = 1;
911 table->LinkLevel[i].SPC = (uint8_t)(data->pcie_spc_cap & 0xff);
912 table->LinkLevel[i].DownThreshold = PP_HOST_TO_SMC_UL(5);
913 table->LinkLevel[i].UpThreshold = PP_HOST_TO_SMC_UL(30);
916 data->smc_state_table.LinkLevelCount =
917 (uint8_t)dpm_table->pcie_speed_table.count;
918 data->dpm_level_enable_mask.pcie_dpm_enable_mask =
919 phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
924 static uint32_t polaris10_get_xclk(struct pp_hwmgr *hwmgr)
926 uint32_t reference_clock, tmp;
927 struct cgs_display_info info = {0};
928 struct cgs_mode_info mode_info;
930 info.mode_info = &mode_info;
932 tmp = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_CLKPIN_CNTL_2, MUX_TCLK_TO_XCLK);
937 cgs_get_active_displays_info(hwmgr->device, &info);
938 reference_clock = mode_info.ref_clock;
940 tmp = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_CLKPIN_CNTL, XTALIN_DIVIDE);
943 return reference_clock / 4;
945 return reference_clock;
949 * Calculates the SCLK dividers using the provided engine clock
951 * @param hwmgr the address of the hardware manager
952 * @param clock the engine clock to use to populate the structure
953 * @param sclk the SMC SCLK structure to be populated
955 static int polaris10_calculate_sclk_params(struct pp_hwmgr *hwmgr,
956 uint32_t clock, SMU_SclkSetting *sclk_setting)
958 const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
959 const SMU74_Discrete_DpmTable *table = &(data->smc_state_table);
960 struct pp_atomctrl_clock_dividers_ai dividers;
963 uint32_t pcc_target_percent, pcc_target_freq, ss_target_percent, ss_target_freq;
968 sclk_setting->SclkFrequency = clock;
969 /* get the engine clock dividers for this clock value */
970 result = atomctrl_get_engine_pll_dividers_ai(hwmgr, clock, ÷rs);
972 sclk_setting->Fcw_int = dividers.usSclk_fcw_int;
973 sclk_setting->Fcw_frac = dividers.usSclk_fcw_frac;
974 sclk_setting->Pcc_fcw_int = dividers.usPcc_fcw_int;
975 sclk_setting->PllRange = dividers.ucSclkPllRange;
976 sclk_setting->Sclk_slew_rate = 0x400;
977 sclk_setting->Pcc_up_slew_rate = dividers.usPcc_fcw_slew_frac;
978 sclk_setting->Pcc_down_slew_rate = 0xffff;
979 sclk_setting->SSc_En = dividers.ucSscEnable;
980 sclk_setting->Fcw1_int = dividers.usSsc_fcw1_int;
981 sclk_setting->Fcw1_frac = dividers.usSsc_fcw1_frac;
982 sclk_setting->Sclk_ss_slew_rate = dividers.usSsc_fcw_slew_frac;
986 ref_clock = polaris10_get_xclk(hwmgr);
988 for (i = 0; i < NUM_SCLK_RANGE; i++) {
989 if (clock > data->range_table[i].trans_lower_frequency
990 && clock <= data->range_table[i].trans_upper_frequency) {
991 sclk_setting->PllRange = i;
996 sclk_setting->Fcw_int = (uint16_t)((clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
997 temp = clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
999 do_div(temp, ref_clock);
1000 sclk_setting->Fcw_frac = temp & 0xffff;
1002 pcc_target_percent = 10; /* Hardcode 10% for now. */
1003 pcc_target_freq = clock - (clock * pcc_target_percent / 100);
1004 sclk_setting->Pcc_fcw_int = (uint16_t)((pcc_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
1006 ss_target_percent = 2; /* Hardcode 2% for now. */
1007 sclk_setting->SSc_En = 0;
1008 if (ss_target_percent) {
1009 sclk_setting->SSc_En = 1;
1010 ss_target_freq = clock - (clock * ss_target_percent / 100);
1011 sclk_setting->Fcw1_int = (uint16_t)((ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
1012 temp = ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
1014 do_div(temp, ref_clock);
1015 sclk_setting->Fcw1_frac = temp & 0xffff;
1021 static int polaris10_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr,
1022 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table,
1023 uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd)
1027 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1029 *voltage = *mvdd = 0;
1031 /* clock - voltage dependency table is empty table */
1032 if (dep_table->count == 0)
1035 for (i = 0; i < dep_table->count; i++) {
1036 /* find first sclk bigger than request */
1037 if (dep_table->entries[i].clk >= clock) {
1038 *voltage |= (dep_table->entries[i].vddc *
1039 VOLTAGE_SCALE) << VDDC_SHIFT;
1040 if (POLARIS10_VOLTAGE_CONTROL_NONE == data->vddci_control)
1041 *voltage |= (data->vbios_boot_state.vddci_bootup_value *
1042 VOLTAGE_SCALE) << VDDCI_SHIFT;
1043 else if (dep_table->entries[i].vddci)
1044 *voltage |= (dep_table->entries[i].vddci *
1045 VOLTAGE_SCALE) << VDDCI_SHIFT;
1047 vddci = phm_find_closest_vddci(&(data->vddci_voltage_table),
1048 (dep_table->entries[i].vddc -
1049 (uint16_t)data->vddc_vddci_delta));
1050 *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1053 if (POLARIS10_VOLTAGE_CONTROL_NONE == data->mvdd_control)
1054 *mvdd = data->vbios_boot_state.mvdd_bootup_value *
1056 else if (dep_table->entries[i].mvdd)
1057 *mvdd = (uint32_t) dep_table->entries[i].mvdd *
1060 *voltage |= 1 << PHASES_SHIFT;
1065 /* sclk is bigger than max sclk in the dependence table */
1066 *voltage |= (dep_table->entries[i - 1].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
1068 if (POLARIS10_VOLTAGE_CONTROL_NONE == data->vddci_control)
1069 *voltage |= (data->vbios_boot_state.vddci_bootup_value *
1070 VOLTAGE_SCALE) << VDDCI_SHIFT;
1071 else if (dep_table->entries[i-1].vddci) {
1072 vddci = phm_find_closest_vddci(&(data->vddci_voltage_table),
1073 (dep_table->entries[i].vddc -
1074 (uint16_t)data->vddc_vddci_delta));
1075 *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1078 if (POLARIS10_VOLTAGE_CONTROL_NONE == data->mvdd_control)
1079 *mvdd = data->vbios_boot_state.mvdd_bootup_value * VOLTAGE_SCALE;
1080 else if (dep_table->entries[i].mvdd)
1081 *mvdd = (uint32_t) dep_table->entries[i - 1].mvdd * VOLTAGE_SCALE;
1086 static const sclkFcwRange_t Range_Table[NUM_SCLK_RANGE] =
1087 { {VCO_2_4, POSTDIV_DIV_BY_16, 75, 160, 112},
1088 {VCO_3_6, POSTDIV_DIV_BY_16, 112, 224, 160},
1089 {VCO_2_4, POSTDIV_DIV_BY_8, 75, 160, 112},
1090 {VCO_3_6, POSTDIV_DIV_BY_8, 112, 224, 160},
1091 {VCO_2_4, POSTDIV_DIV_BY_4, 75, 160, 112},
1092 {VCO_3_6, POSTDIV_DIV_BY_4, 112, 216, 160},
1093 {VCO_2_4, POSTDIV_DIV_BY_2, 75, 160, 108},
1094 {VCO_3_6, POSTDIV_DIV_BY_2, 112, 216, 160} };
1096 static void polaris10_get_sclk_range_table(struct pp_hwmgr *hwmgr)
1098 uint32_t i, ref_clk;
1099 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1100 SMU74_Discrete_DpmTable *table = &(data->smc_state_table);
1101 struct pp_atom_ctrl_sclk_range_table range_table_from_vbios = { { {0} } };
1103 ref_clk = polaris10_get_xclk(hwmgr);
1105 if (0 == atomctrl_get_smc_sclk_range_table(hwmgr, &range_table_from_vbios)) {
1106 for (i = 0; i < NUM_SCLK_RANGE; i++) {
1107 table->SclkFcwRangeTable[i].vco_setting = range_table_from_vbios.entry[i].ucVco_setting;
1108 table->SclkFcwRangeTable[i].postdiv = range_table_from_vbios.entry[i].ucPostdiv;
1109 table->SclkFcwRangeTable[i].fcw_pcc = range_table_from_vbios.entry[i].usFcw_pcc;
1111 table->SclkFcwRangeTable[i].fcw_trans_upper = range_table_from_vbios.entry[i].usFcw_trans_upper;
1112 table->SclkFcwRangeTable[i].fcw_trans_lower = range_table_from_vbios.entry[i].usRcw_trans_lower;
1114 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc);
1115 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper);
1116 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower);
1121 for (i = 0; i < NUM_SCLK_RANGE; i++) {
1123 data->range_table[i].trans_lower_frequency = (ref_clk * Range_Table[i].fcw_trans_lower) >> Range_Table[i].postdiv;
1124 data->range_table[i].trans_upper_frequency = (ref_clk * Range_Table[i].fcw_trans_upper) >> Range_Table[i].postdiv;
1126 table->SclkFcwRangeTable[i].vco_setting = Range_Table[i].vco_setting;
1127 table->SclkFcwRangeTable[i].postdiv = Range_Table[i].postdiv;
1128 table->SclkFcwRangeTable[i].fcw_pcc = Range_Table[i].fcw_pcc;
1130 table->SclkFcwRangeTable[i].fcw_trans_upper = Range_Table[i].fcw_trans_upper;
1131 table->SclkFcwRangeTable[i].fcw_trans_lower = Range_Table[i].fcw_trans_lower;
1133 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc);
1134 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper);
1135 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower);
1140 * Populates single SMC SCLK structure using the provided engine clock
1142 * @param hwmgr the address of the hardware manager
1143 * @param clock the engine clock to use to populate the structure
1144 * @param sclk the SMC SCLK structure to be populated
1147 static int polaris10_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
1148 uint32_t clock, uint16_t sclk_al_threshold,
1149 struct SMU74_Discrete_GraphicsLevel *level)
1151 int result, i, temp;
1152 /* PP_Clocks minClocks; */
1154 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1155 struct phm_ppt_v1_information *table_info =
1156 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1157 SMU_SclkSetting curr_sclk_setting = { 0 };
1159 result = polaris10_calculate_sclk_params(hwmgr, clock, &curr_sclk_setting);
1161 /* populate graphics levels */
1162 result = polaris10_get_dependency_volt_by_clk(hwmgr,
1163 table_info->vdd_dep_on_sclk, clock,
1164 &level->MinVoltage, &mvdd);
1166 PP_ASSERT_WITH_CODE((0 == result),
1167 "can not find VDDC voltage value for "
1168 "VDDC engine clock dependency table",
1170 level->ActivityLevel = sclk_al_threshold;
1172 level->CcPwrDynRm = 0;
1173 level->CcPwrDynRm1 = 0;
1174 level->EnabledForActivity = 0;
1175 level->EnabledForThrottle = 1;
1177 level->DownHyst = 0;
1178 level->VoltageDownHyst = 0;
1179 level->PowerThrottle = 0;
1182 * TODO: get minimum clocks from dal configaration
1183 * PECI_GetMinClockSettings(hwmgr->pPECI, &minClocks);
1185 /* data->DisplayTiming.minClockInSR = minClocks.engineClockInSR; */
1187 /* get level->DeepSleepDivId
1188 if (phm_cap_enabled(hwmgr->platformDescriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep))
1189 level->DeepSleepDivId = PhwFiji_GetSleepDividerIdFromClock(hwmgr, clock, minClocks.engineClockInSR);
1191 PP_ASSERT_WITH_CODE((clock >= POLARIS10_MINIMUM_ENGINE_CLOCK), "Engine clock can't satisfy stutter requirement!", return 0);
1192 for (i = POLARIS10_MAX_DEEPSLEEP_DIVIDER_ID; ; i--) {
1195 if (temp >= POLARIS10_MINIMUM_ENGINE_CLOCK || i == 0)
1199 level->DeepSleepDivId = i;
1201 /* Default to slow, highest DPM level will be
1202 * set to PPSMC_DISPLAY_WATERMARK_LOW later.
1204 if (data->update_up_hyst)
1205 level->UpHyst = (uint8_t)data->up_hyst;
1206 if (data->update_down_hyst)
1207 level->DownHyst = (uint8_t)data->down_hyst;
1209 level->SclkSetting = curr_sclk_setting;
1211 CONVERT_FROM_HOST_TO_SMC_UL(level->MinVoltage);
1212 CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm);
1213 CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm1);
1214 CONVERT_FROM_HOST_TO_SMC_US(level->ActivityLevel);
1215 CONVERT_FROM_HOST_TO_SMC_UL(level->SclkSetting.SclkFrequency);
1216 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_int);
1217 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_frac);
1218 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_fcw_int);
1219 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Sclk_slew_rate);
1220 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_up_slew_rate);
1221 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_down_slew_rate);
1222 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_int);
1223 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_frac);
1224 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Sclk_ss_slew_rate);
1229 * Populates all SMC SCLK levels' structure based on the trimmed allowed dpm engine clock states
1231 * @param hwmgr the address of the hardware manager
1233 static int polaris10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
1235 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1236 struct polaris10_dpm_table *dpm_table = &data->dpm_table;
1237 struct phm_ppt_v1_information *table_info =
1238 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1239 struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
1240 uint8_t pcie_entry_cnt = (uint8_t) data->dpm_table.pcie_speed_table.count;
1242 uint32_t array = data->dpm_table_start +
1243 offsetof(SMU74_Discrete_DpmTable, GraphicsLevel);
1244 uint32_t array_size = sizeof(struct SMU74_Discrete_GraphicsLevel) *
1245 SMU74_MAX_LEVELS_GRAPHICS;
1246 struct SMU74_Discrete_GraphicsLevel *levels =
1247 data->smc_state_table.GraphicsLevel;
1248 uint32_t i, max_entry;
1249 uint8_t hightest_pcie_level_enabled = 0,
1250 lowest_pcie_level_enabled = 0,
1251 mid_pcie_level_enabled = 0,
1254 polaris10_get_sclk_range_table(hwmgr);
1256 for (i = 0; i < dpm_table->sclk_table.count; i++) {
1258 result = polaris10_populate_single_graphic_level(hwmgr,
1259 dpm_table->sclk_table.dpm_levels[i].value,
1260 (uint16_t)data->activity_target[i],
1261 &(data->smc_state_table.GraphicsLevel[i]));
1265 /* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */
1267 levels[i].DeepSleepDivId = 0;
1269 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1270 PHM_PlatformCaps_SPLLShutdownSupport))
1271 data->smc_state_table.GraphicsLevel[0].SclkSetting.SSc_En = 0;
1273 data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
1274 data->smc_state_table.GraphicsDpmLevelCount =
1275 (uint8_t)dpm_table->sclk_table.count;
1276 data->dpm_level_enable_mask.sclk_dpm_enable_mask =
1277 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
1280 if (pcie_table != NULL) {
1281 PP_ASSERT_WITH_CODE((1 <= pcie_entry_cnt),
1282 "There must be 1 or more PCIE levels defined in PPTable.",
1284 max_entry = pcie_entry_cnt - 1;
1285 for (i = 0; i < dpm_table->sclk_table.count; i++)
1286 levels[i].pcieDpmLevel =
1287 (uint8_t) ((i < max_entry) ? i : max_entry);
1289 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
1290 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1291 (1 << (hightest_pcie_level_enabled + 1))) != 0))
1292 hightest_pcie_level_enabled++;
1294 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
1295 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1296 (1 << lowest_pcie_level_enabled)) == 0))
1297 lowest_pcie_level_enabled++;
1299 while ((count < hightest_pcie_level_enabled) &&
1300 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1301 (1 << (lowest_pcie_level_enabled + 1 + count))) == 0))
1304 mid_pcie_level_enabled = (lowest_pcie_level_enabled + 1 + count) <
1305 hightest_pcie_level_enabled ?
1306 (lowest_pcie_level_enabled + 1 + count) :
1307 hightest_pcie_level_enabled;
1309 /* set pcieDpmLevel to hightest_pcie_level_enabled */
1310 for (i = 2; i < dpm_table->sclk_table.count; i++)
1311 levels[i].pcieDpmLevel = hightest_pcie_level_enabled;
1313 /* set pcieDpmLevel to lowest_pcie_level_enabled */
1314 levels[0].pcieDpmLevel = lowest_pcie_level_enabled;
1316 /* set pcieDpmLevel to mid_pcie_level_enabled */
1317 levels[1].pcieDpmLevel = mid_pcie_level_enabled;
1319 /* level count will send to smc once at init smc table and never change */
1320 result = polaris10_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels,
1321 (uint32_t)array_size, data->sram_end);
1326 static int polaris10_populate_single_memory_level(struct pp_hwmgr *hwmgr,
1327 uint32_t clock, struct SMU74_Discrete_MemoryLevel *mem_level)
1329 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1330 struct phm_ppt_v1_information *table_info =
1331 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1333 struct cgs_display_info info = {0, 0, NULL};
1335 cgs_get_active_displays_info(hwmgr->device, &info);
1337 if (table_info->vdd_dep_on_mclk) {
1338 result = polaris10_get_dependency_volt_by_clk(hwmgr,
1339 table_info->vdd_dep_on_mclk, clock,
1340 &mem_level->MinVoltage, &mem_level->MinMvdd);
1341 PP_ASSERT_WITH_CODE((0 == result),
1342 "can not find MinVddc voltage value from memory "
1343 "VDDC voltage dependency table", return result);
1346 mem_level->MclkFrequency = clock;
1347 mem_level->EnabledForThrottle = 1;
1348 mem_level->EnabledForActivity = 0;
1349 mem_level->UpHyst = 0;
1350 mem_level->DownHyst = 100;
1351 mem_level->VoltageDownHyst = 0;
1352 mem_level->ActivityLevel = (uint16_t)data->mclk_activity_target;
1353 mem_level->StutterEnable = false;
1354 mem_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
1356 data->display_timing.num_existing_displays = info.display_count;
1358 if ((data->mclk_stutter_mode_threshold) &&
1359 (clock <= data->mclk_stutter_mode_threshold) &&
1360 (PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL,
1361 STUTTER_ENABLE) & 0x1))
1362 mem_level->StutterEnable = true;
1365 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinMvdd);
1366 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MclkFrequency);
1367 CONVERT_FROM_HOST_TO_SMC_US(mem_level->ActivityLevel);
1368 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinVoltage);
1374 * Populates all SMC MCLK levels' structure based on the trimmed allowed dpm memory clock states
1376 * @param hwmgr the address of the hardware manager
1378 static int polaris10_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
1380 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1381 struct polaris10_dpm_table *dpm_table = &data->dpm_table;
1383 /* populate MCLK dpm table to SMU7 */
1384 uint32_t array = data->dpm_table_start +
1385 offsetof(SMU74_Discrete_DpmTable, MemoryLevel);
1386 uint32_t array_size = sizeof(SMU74_Discrete_MemoryLevel) *
1387 SMU74_MAX_LEVELS_MEMORY;
1388 struct SMU74_Discrete_MemoryLevel *levels =
1389 data->smc_state_table.MemoryLevel;
1392 for (i = 0; i < dpm_table->mclk_table.count; i++) {
1393 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),
1394 "can not populate memory level as memory clock is zero",
1396 result = polaris10_populate_single_memory_level(hwmgr,
1397 dpm_table->mclk_table.dpm_levels[i].value,
1399 if (i == dpm_table->mclk_table.count - 1) {
1400 levels[i].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH;
1401 levels[i].EnabledForActivity = 1;
1407 /* in order to prevent MC activity from stutter mode to push DPM up.
1408 * the UVD change complements this by putting the MCLK in
1409 * a higher state by default such that we are not effected by
1410 * up threshold or and MCLK DPM latency.
1412 levels[0].ActivityLevel = 0x1f;
1413 CONVERT_FROM_HOST_TO_SMC_US(levels[0].ActivityLevel);
1415 data->smc_state_table.MemoryDpmLevelCount =
1416 (uint8_t)dpm_table->mclk_table.count;
1417 data->dpm_level_enable_mask.mclk_dpm_enable_mask =
1418 phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
1420 /* level count will send to smc once at init smc table and never change */
1421 result = polaris10_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels,
1422 (uint32_t)array_size, data->sram_end);
1428 * Populates the SMC MVDD structure using the provided memory clock.
1430 * @param hwmgr the address of the hardware manager
1431 * @param mclk the MCLK value to be used in the decision if MVDD should be high or low.
1432 * @param voltage the SMC VOLTAGE structure to be populated
1434 int polaris10_populate_mvdd_value(struct pp_hwmgr *hwmgr,
1435 uint32_t mclk, SMIO_Pattern *smio_pat)
1437 const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1438 struct phm_ppt_v1_information *table_info =
1439 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1442 if (POLARIS10_VOLTAGE_CONTROL_NONE != data->mvdd_control) {
1443 /* find mvdd value which clock is more than request */
1444 for (i = 0; i < table_info->vdd_dep_on_mclk->count; i++) {
1445 if (mclk <= table_info->vdd_dep_on_mclk->entries[i].clk) {
1446 smio_pat->Voltage = data->mvdd_voltage_table.entries[i].value;
1450 PP_ASSERT_WITH_CODE(i < table_info->vdd_dep_on_mclk->count,
1451 "MVDD Voltage is outside the supported range.",
1459 static int polaris10_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
1460 SMU74_Discrete_DpmTable *table)
1463 uint32_t sclk_frequency;
1464 const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1465 struct phm_ppt_v1_information *table_info =
1466 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1467 SMIO_Pattern vol_level;
1471 table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
1473 if (!data->sclk_dpm_key_disabled) {
1474 /* Get MinVoltage and Frequency from DPM0,
1475 * already converted to SMC_UL */
1476 sclk_frequency = data->dpm_table.sclk_table.dpm_levels[0].value;
1477 result = polaris10_get_dependency_volt_by_clk(hwmgr,
1478 table_info->vdd_dep_on_sclk,
1479 table->ACPILevel.SclkFrequency,
1480 &table->ACPILevel.MinVoltage, &mvdd);
1481 PP_ASSERT_WITH_CODE((0 == result),
1482 "Cannot find ACPI VDDC voltage value "
1483 "in Clock Dependency Table", );
1485 sclk_frequency = data->vbios_boot_state.sclk_bootup_value;
1486 table->ACPILevel.MinVoltage =
1487 data->vbios_boot_state.vddc_bootup_value * VOLTAGE_SCALE;
1490 result = polaris10_calculate_sclk_params(hwmgr, sclk_frequency, &(table->ACPILevel.SclkSetting));
1491 PP_ASSERT_WITH_CODE(result == 0, "Error retrieving Engine Clock dividers from VBIOS.", return result);
1493 table->ACPILevel.DeepSleepDivId = 0;
1494 table->ACPILevel.CcPwrDynRm = 0;
1495 table->ACPILevel.CcPwrDynRm1 = 0;
1497 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);
1498 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.MinVoltage);
1499 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);
1500 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);
1502 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkSetting.SclkFrequency);
1503 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_int);
1504 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_frac);
1505 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_fcw_int);
1506 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_slew_rate);
1507 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_up_slew_rate);
1508 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_down_slew_rate);
1509 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_int);
1510 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_frac);
1511 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_ss_slew_rate);
1513 if (!data->mclk_dpm_key_disabled) {
1514 /* Get MinVoltage and Frequency from DPM0, already converted to SMC_UL */
1515 table->MemoryACPILevel.MclkFrequency =
1516 data->dpm_table.mclk_table.dpm_levels[0].value;
1517 result = polaris10_get_dependency_volt_by_clk(hwmgr,
1518 table_info->vdd_dep_on_mclk,
1519 table->MemoryACPILevel.MclkFrequency,
1520 &table->MemoryACPILevel.MinVoltage, &mvdd);
1521 PP_ASSERT_WITH_CODE((0 == result),
1522 "Cannot find ACPI VDDCI voltage value "
1523 "in Clock Dependency Table",
1526 table->MemoryACPILevel.MclkFrequency =
1527 data->vbios_boot_state.mclk_bootup_value;
1528 table->MemoryACPILevel.MinVoltage =
1529 data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE;
1533 if ((POLARIS10_VOLTAGE_CONTROL_NONE == data->mvdd_control) ||
1534 (data->mclk_dpm_key_disabled))
1535 us_mvdd = data->vbios_boot_state.mvdd_bootup_value;
1537 if (!polaris10_populate_mvdd_value(hwmgr,
1538 data->dpm_table.mclk_table.dpm_levels[0].value,
1540 us_mvdd = vol_level.Voltage;
1543 if (0 == polaris10_populate_mvdd_value(hwmgr, 0, &vol_level))
1544 table->MemoryACPILevel.MinMvdd = PP_HOST_TO_SMC_UL(vol_level.Voltage);
1546 table->MemoryACPILevel.MinMvdd = 0;
1548 table->MemoryACPILevel.StutterEnable = false;
1550 table->MemoryACPILevel.EnabledForThrottle = 0;
1551 table->MemoryACPILevel.EnabledForActivity = 0;
1552 table->MemoryACPILevel.UpHyst = 0;
1553 table->MemoryACPILevel.DownHyst = 100;
1554 table->MemoryACPILevel.VoltageDownHyst = 0;
1555 table->MemoryACPILevel.ActivityLevel =
1556 PP_HOST_TO_SMC_US((uint16_t)data->mclk_activity_target);
1558 CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MclkFrequency);
1559 CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MinVoltage);
1564 static int polaris10_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
1565 SMU74_Discrete_DpmTable *table)
1567 int result = -EINVAL;
1569 struct pp_atomctrl_clock_dividers_vi dividers;
1570 struct phm_ppt_v1_information *table_info =
1571 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1572 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1573 table_info->mm_dep_table;
1574 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1576 table->VceLevelCount = (uint8_t)(mm_table->count);
1577 table->VceBootLevel = 0;
1579 for (count = 0; count < table->VceLevelCount; count++) {
1580 table->VceLevel[count].Frequency = mm_table->entries[count].eclk;
1581 table->VceLevel[count].MinVoltage = 0;
1582 table->VceLevel[count].MinVoltage |=
1583 (mm_table->entries[count].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
1584 table->VceLevel[count].MinVoltage |=
1585 ((mm_table->entries[count].vddc - data->vddc_vddci_delta) *
1586 VOLTAGE_SCALE) << VDDCI_SHIFT;
1587 table->VceLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1589 /*retrieve divider value for VBIOS */
1590 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1591 table->VceLevel[count].Frequency, ÷rs);
1592 PP_ASSERT_WITH_CODE((0 == result),
1593 "can not find divide id for VCE engine clock",
1596 table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1598 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency);
1599 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].MinVoltage);
1604 static int polaris10_populate_smc_samu_level(struct pp_hwmgr *hwmgr,
1605 SMU74_Discrete_DpmTable *table)
1607 int result = -EINVAL;
1609 struct pp_atomctrl_clock_dividers_vi dividers;
1610 struct phm_ppt_v1_information *table_info =
1611 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1612 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1613 table_info->mm_dep_table;
1614 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1616 table->SamuBootLevel = 0;
1617 table->SamuLevelCount = (uint8_t)(mm_table->count);
1619 for (count = 0; count < table->SamuLevelCount; count++) {
1620 /* not sure whether we need evclk or not */
1621 table->SamuLevel[count].MinVoltage = 0;
1622 table->SamuLevel[count].Frequency = mm_table->entries[count].samclock;
1623 table->SamuLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
1624 VOLTAGE_SCALE) << VDDC_SHIFT;
1625 table->SamuLevel[count].MinVoltage |= ((mm_table->entries[count].vddc -
1626 data->vddc_vddci_delta) * VOLTAGE_SCALE) << VDDCI_SHIFT;
1627 table->SamuLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1629 /* retrieve divider value for VBIOS */
1630 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1631 table->SamuLevel[count].Frequency, ÷rs);
1632 PP_ASSERT_WITH_CODE((0 == result),
1633 "can not find divide id for samu clock", return result);
1635 table->SamuLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1637 CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].Frequency);
1638 CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].MinVoltage);
1643 static int polaris10_populate_memory_timing_parameters(struct pp_hwmgr *hwmgr,
1644 int32_t eng_clock, int32_t mem_clock,
1645 SMU74_Discrete_MCArbDramTimingTableEntry *arb_regs)
1647 uint32_t dram_timing;
1648 uint32_t dram_timing2;
1649 uint32_t burst_time;
1652 result = atomctrl_set_engine_dram_timings_rv770(hwmgr,
1653 eng_clock, mem_clock);
1654 PP_ASSERT_WITH_CODE(result == 0,
1655 "Error calling VBIOS to set DRAM_TIMING.", return result);
1657 dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
1658 dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
1659 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
1662 arb_regs->McArbDramTiming = PP_HOST_TO_SMC_UL(dram_timing);
1663 arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dram_timing2);
1664 arb_regs->McArbBurstTime = (uint8_t)burst_time;
1669 static int polaris10_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
1671 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1672 struct SMU74_Discrete_MCArbDramTimingTable arb_regs;
1676 for (i = 0; i < data->dpm_table.sclk_table.count; i++) {
1677 for (j = 0; j < data->dpm_table.mclk_table.count; j++) {
1678 result = polaris10_populate_memory_timing_parameters(hwmgr,
1679 data->dpm_table.sclk_table.dpm_levels[i].value,
1680 data->dpm_table.mclk_table.dpm_levels[j].value,
1681 &arb_regs.entries[i][j]);
1683 result = atomctrl_set_ac_timing_ai(hwmgr, data->dpm_table.mclk_table.dpm_levels[j].value, j);
1689 result = polaris10_copy_bytes_to_smc(
1691 data->arb_table_start,
1692 (uint8_t *)&arb_regs,
1693 sizeof(SMU74_Discrete_MCArbDramTimingTable),
1698 static int polaris10_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
1699 struct SMU74_Discrete_DpmTable *table)
1701 int result = -EINVAL;
1703 struct pp_atomctrl_clock_dividers_vi dividers;
1704 struct phm_ppt_v1_information *table_info =
1705 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1706 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1707 table_info->mm_dep_table;
1708 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1710 table->UvdLevelCount = (uint8_t)(mm_table->count);
1711 table->UvdBootLevel = 0;
1713 for (count = 0; count < table->UvdLevelCount; count++) {
1714 table->UvdLevel[count].MinVoltage = 0;
1715 table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk;
1716 table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk;
1717 table->UvdLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
1718 VOLTAGE_SCALE) << VDDC_SHIFT;
1719 table->UvdLevel[count].MinVoltage |= ((mm_table->entries[count].vddc -
1720 data->vddc_vddci_delta) * VOLTAGE_SCALE) << VDDCI_SHIFT;
1721 table->UvdLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1723 /* retrieve divider value for VBIOS */
1724 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1725 table->UvdLevel[count].VclkFrequency, ÷rs);
1726 PP_ASSERT_WITH_CODE((0 == result),
1727 "can not find divide id for Vclk clock", return result);
1729 table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
1731 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1732 table->UvdLevel[count].DclkFrequency, ÷rs);
1733 PP_ASSERT_WITH_CODE((0 == result),
1734 "can not find divide id for Dclk clock", return result);
1736 table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;
1738 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency);
1739 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency);
1740 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].MinVoltage);
1746 static int polaris10_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
1747 struct SMU74_Discrete_DpmTable *table)
1750 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1752 table->GraphicsBootLevel = 0;
1753 table->MemoryBootLevel = 0;
1755 /* find boot level from dpm table */
1756 result = phm_find_boot_level(&(data->dpm_table.sclk_table),
1757 data->vbios_boot_state.sclk_bootup_value,
1758 (uint32_t *)&(table->GraphicsBootLevel));
1760 result = phm_find_boot_level(&(data->dpm_table.mclk_table),
1761 data->vbios_boot_state.mclk_bootup_value,
1762 (uint32_t *)&(table->MemoryBootLevel));
1764 table->BootVddc = data->vbios_boot_state.vddc_bootup_value *
1766 table->BootVddci = data->vbios_boot_state.vddci_bootup_value *
1768 table->BootMVdd = data->vbios_boot_state.mvdd_bootup_value *
1771 CONVERT_FROM_HOST_TO_SMC_US(table->BootVddc);
1772 CONVERT_FROM_HOST_TO_SMC_US(table->BootVddci);
1773 CONVERT_FROM_HOST_TO_SMC_US(table->BootMVdd);
1779 static int polaris10_populate_smc_initailial_state(struct pp_hwmgr *hwmgr)
1781 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1782 struct phm_ppt_v1_information *table_info =
1783 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1784 uint8_t count, level;
1786 count = (uint8_t)(table_info->vdd_dep_on_sclk->count);
1788 for (level = 0; level < count; level++) {
1789 if (table_info->vdd_dep_on_sclk->entries[level].clk >=
1790 data->vbios_boot_state.sclk_bootup_value) {
1791 data->smc_state_table.GraphicsBootLevel = level;
1796 count = (uint8_t)(table_info->vdd_dep_on_mclk->count);
1797 for (level = 0; level < count; level++) {
1798 if (table_info->vdd_dep_on_mclk->entries[level].clk >=
1799 data->vbios_boot_state.mclk_bootup_value) {
1800 data->smc_state_table.MemoryBootLevel = level;
1808 static int polaris10_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
1810 uint32_t ro, efuse, volt_without_cks, volt_with_cks, value, max, min;
1811 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1812 uint8_t i, stretch_amount, stretch_amount2, volt_offset = 0;
1813 struct phm_ppt_v1_information *table_info =
1814 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1815 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
1816 table_info->vdd_dep_on_sclk;
1818 stretch_amount = (uint8_t)table_info->cac_dtp_table->usClockStretchAmount;
1820 /* Read SMU_Eefuse to read and calculate RO and determine
1821 * if the part is SS or FF. if RO >= 1660MHz, part is FF.
1823 efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1824 ixSMU_EFUSE_0 + (67 * 4));
1825 efuse &= 0xFF000000;
1826 efuse = efuse >> 24;
1828 if (hwmgr->chip_id == CHIP_POLARIS10) {
1836 ro = efuse * (max -min)/255 + min;
1838 /* Populate Sclk_CKS_masterEn0_7 and Sclk_voltageOffset */
1839 for (i = 0; i < sclk_table->count; i++) {
1840 data->smc_state_table.Sclk_CKS_masterEn0_7 |=
1841 sclk_table->entries[i].cks_enable << i;
1843 volt_without_cks = (uint32_t)(((ro - 40) * 1000 - 2753594 - sclk_table->entries[i].clk/100 * 136418 /1000) / \
1844 (sclk_table->entries[i].clk/100 * 1132925 /10000 - 242418)/100);
1846 volt_with_cks = (uint32_t)((ro * 1000 -2396351 - sclk_table->entries[i].clk/100 * 329021/1000) / \
1847 (sclk_table->entries[i].clk/10000 * 649434 /1000 - 18005)/10);
1849 if (volt_without_cks >= volt_with_cks)
1850 volt_offset = (uint8_t)(((volt_without_cks - volt_with_cks +
1851 sclk_table->entries[i].cks_voffset) * 100 / 625) + 1);
1853 data->smc_state_table.Sclk_voltageOffset[i] = volt_offset;
1856 /* Populate CKS Lookup Table */
1857 if (stretch_amount == 1 || stretch_amount == 2 || stretch_amount == 5)
1858 stretch_amount2 = 0;
1859 else if (stretch_amount == 3 || stretch_amount == 4)
1860 stretch_amount2 = 1;
1862 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
1863 PHM_PlatformCaps_ClockStretcher);
1864 PP_ASSERT_WITH_CODE(false,
1865 "Stretch Amount in PPTable not supported\n",
1869 value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL);
1870 value &= 0xFFFFFFFE;
1871 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL, value);
1877 * Populates the SMC VRConfig field in DPM table.
1879 * @param hwmgr the address of the hardware manager
1880 * @param table the SMC DPM table structure to be populated
1883 static int polaris10_populate_vr_config(struct pp_hwmgr *hwmgr,
1884 struct SMU74_Discrete_DpmTable *table)
1886 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1889 config = VR_MERGED_WITH_VDDC;
1890 table->VRConfig |= (config << VRCONF_VDDGFX_SHIFT);
1892 /* Set Vddc Voltage Controller */
1893 if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
1894 config = VR_SVI2_PLANE_1;
1895 table->VRConfig |= config;
1897 PP_ASSERT_WITH_CODE(false,
1898 "VDDC should be on SVI2 control in merged mode!",
1901 /* Set Vddci Voltage Controller */
1902 if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
1903 config = VR_SVI2_PLANE_2; /* only in merged mode */
1904 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1905 } else if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
1906 config = VR_SMIO_PATTERN_1;
1907 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1909 config = VR_STATIC_VOLTAGE;
1910 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1912 /* Set Mvdd Voltage Controller */
1913 if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
1914 config = VR_SVI2_PLANE_2;
1915 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
1916 } else if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
1917 config = VR_SMIO_PATTERN_2;
1918 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
1920 config = VR_STATIC_VOLTAGE;
1921 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
1928 int polaris10_populate_avfs_parameters(struct pp_hwmgr *hwmgr)
1930 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1931 SMU74_Discrete_DpmTable *table = &(data->smc_state_table);
1933 struct pp_atom_ctrl__avfs_parameters avfs_params = {0};
1934 AVFS_meanNsigma_t AVFS_meanNsigma = { {0} };
1935 AVFS_Sclk_Offset_t AVFS_SclkOffset = { {0} };
1937 struct pp_smumgr *smumgr = hwmgr->smumgr;
1938 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
1940 struct phm_ppt_v1_information *table_info =
1941 (struct phm_ppt_v1_information *)hwmgr->pptable;
1942 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
1943 table_info->vdd_dep_on_sclk;
1946 if (smu_data->avfs.avfs_btc_status == AVFS_BTC_NOTSUPPORTED)
1949 result = atomctrl_get_avfs_information(hwmgr, &avfs_params);
1952 table->BTCGB_VDROOP_TABLE[0].a0 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a0);
1953 table->BTCGB_VDROOP_TABLE[0].a1 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a1);
1954 table->BTCGB_VDROOP_TABLE[0].a2 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a2);
1955 table->BTCGB_VDROOP_TABLE[1].a0 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a0);
1956 table->BTCGB_VDROOP_TABLE[1].a1 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a1);
1957 table->BTCGB_VDROOP_TABLE[1].a2 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a2);
1958 table->AVFSGB_VDROOP_TABLE[0].m1 = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_m1);
1959 table->AVFSGB_VDROOP_TABLE[0].m2 = PP_HOST_TO_SMC_US(avfs_params.usAVFSGB_FUSE_TABLE_CKSON_m2);
1960 table->AVFSGB_VDROOP_TABLE[0].b = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_b);
1961 table->AVFSGB_VDROOP_TABLE[0].m1_shift = 24;
1962 table->AVFSGB_VDROOP_TABLE[0].m2_shift = 12;
1963 table->AVFSGB_VDROOP_TABLE[1].m1 = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_m1);
1964 table->AVFSGB_VDROOP_TABLE[1].m2 = PP_HOST_TO_SMC_US(avfs_params.usAVFSGB_FUSE_TABLE_CKSOFF_m2);
1965 table->AVFSGB_VDROOP_TABLE[1].b = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_b);
1966 table->AVFSGB_VDROOP_TABLE[1].m1_shift = 24;
1967 table->AVFSGB_VDROOP_TABLE[1].m2_shift = 12;
1968 table->MaxVoltage = PP_HOST_TO_SMC_US(avfs_params.usMaxVoltage_0_25mv);
1969 AVFS_meanNsigma.Aconstant[0] = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant0);
1970 AVFS_meanNsigma.Aconstant[1] = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant1);
1971 AVFS_meanNsigma.Aconstant[2] = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant2);
1972 AVFS_meanNsigma.DC_tol_sigma = PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_DC_tol_sigma);
1973 AVFS_meanNsigma.Platform_mean = PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_Platform_mean);
1974 AVFS_meanNsigma.PSM_Age_CompFactor = PP_HOST_TO_SMC_US(avfs_params.usPSM_Age_ComFactor);
1975 AVFS_meanNsigma.Platform_sigma = PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_Platform_sigma);
1977 for (i = 0; i < NUM_VFT_COLUMNS; i++) {
1978 AVFS_meanNsigma.Static_Voltage_Offset[i] = (uint8_t)(sclk_table->entries[i].cks_voffset * 100 / 625);
1979 AVFS_SclkOffset.Sclk_Offset[i] = PP_HOST_TO_SMC_US((uint16_t)(sclk_table->entries[i].sclk_offset) / 100);
1982 result = polaris10_read_smc_sram_dword(smumgr,
1983 SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, AvfsMeanNSigma),
1984 &tmp, data->sram_end);
1986 polaris10_copy_bytes_to_smc(smumgr,
1988 (uint8_t *)&AVFS_meanNsigma,
1989 sizeof(AVFS_meanNsigma_t),
1992 result = polaris10_read_smc_sram_dword(smumgr,
1993 SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, AvfsSclkOffsetTable),
1994 &tmp, data->sram_end);
1995 polaris10_copy_bytes_to_smc(smumgr,
1997 (uint8_t *)&AVFS_SclkOffset,
1998 sizeof(AVFS_Sclk_Offset_t),
2001 data->avfs_vdroop_override_setting = (avfs_params.ucEnableGB_VDROOP_TABLE_CKSON << BTCGB0_Vdroop_Enable_SHIFT) |
2002 (avfs_params.ucEnableGB_VDROOP_TABLE_CKSOFF << BTCGB1_Vdroop_Enable_SHIFT) |
2003 (avfs_params.ucEnableGB_FUSE_TABLE_CKSON << AVFSGB0_Vdroop_Enable_SHIFT) |
2004 (avfs_params.ucEnableGB_FUSE_TABLE_CKSOFF << AVFSGB1_Vdroop_Enable_SHIFT);
2005 data->apply_avfs_cks_off_voltage = (avfs_params.ucEnableApplyAVFS_CKS_OFF_Voltage == 1) ? true : false;
2012 * Initializes the SMC table and uploads it
2014 * @param hwmgr the address of the powerplay hardware manager.
2017 static int polaris10_init_smc_table(struct pp_hwmgr *hwmgr)
2020 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2021 struct phm_ppt_v1_information *table_info =
2022 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2023 struct SMU74_Discrete_DpmTable *table = &(data->smc_state_table);
2024 const struct polaris10_ulv_parm *ulv = &(data->ulv);
2026 struct pp_atomctrl_gpio_pin_assignment gpio_pin;
2027 pp_atomctrl_clock_dividers_vi dividers;
2029 result = polaris10_setup_default_dpm_tables(hwmgr);
2030 PP_ASSERT_WITH_CODE(0 == result,
2031 "Failed to setup default DPM tables!", return result);
2033 if (POLARIS10_VOLTAGE_CONTROL_NONE != data->voltage_control)
2034 polaris10_populate_smc_voltage_tables(hwmgr, table);
2036 table->SystemFlags = 0;
2037 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2038 PHM_PlatformCaps_AutomaticDCTransition))
2039 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
2041 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2042 PHM_PlatformCaps_StepVddc))
2043 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
2045 if (data->is_memory_gddr5)
2046 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
2048 if (ulv->ulv_supported && table_info->us_ulv_voltage_offset) {
2049 result = polaris10_populate_ulv_state(hwmgr, table);
2050 PP_ASSERT_WITH_CODE(0 == result,
2051 "Failed to initialize ULV state!", return result);
2052 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2053 ixCG_ULV_PARAMETER, PPPOLARIS10_CGULVPARAMETER_DFLT);
2056 result = polaris10_populate_smc_link_level(hwmgr, table);
2057 PP_ASSERT_WITH_CODE(0 == result,
2058 "Failed to initialize Link Level!", return result);
2060 result = polaris10_populate_all_graphic_levels(hwmgr);
2061 PP_ASSERT_WITH_CODE(0 == result,
2062 "Failed to initialize Graphics Level!", return result);
2064 result = polaris10_populate_all_memory_levels(hwmgr);
2065 PP_ASSERT_WITH_CODE(0 == result,
2066 "Failed to initialize Memory Level!", return result);
2068 result = polaris10_populate_smc_acpi_level(hwmgr, table);
2069 PP_ASSERT_WITH_CODE(0 == result,
2070 "Failed to initialize ACPI Level!", return result);
2072 result = polaris10_populate_smc_vce_level(hwmgr, table);
2073 PP_ASSERT_WITH_CODE(0 == result,
2074 "Failed to initialize VCE Level!", return result);
2076 result = polaris10_populate_smc_samu_level(hwmgr, table);
2077 PP_ASSERT_WITH_CODE(0 == result,
2078 "Failed to initialize SAMU Level!", return result);
2080 /* Since only the initial state is completely set up at this point
2081 * (the other states are just copies of the boot state) we only
2082 * need to populate the ARB settings for the initial state.
2084 result = polaris10_program_memory_timing_parameters(hwmgr);
2085 PP_ASSERT_WITH_CODE(0 == result,
2086 "Failed to Write ARB settings for the initial state.", return result);
2088 result = polaris10_populate_smc_uvd_level(hwmgr, table);
2089 PP_ASSERT_WITH_CODE(0 == result,
2090 "Failed to initialize UVD Level!", return result);
2092 result = polaris10_populate_smc_boot_level(hwmgr, table);
2093 PP_ASSERT_WITH_CODE(0 == result,
2094 "Failed to initialize Boot Level!", return result);
2096 result = polaris10_populate_smc_initailial_state(hwmgr);
2097 PP_ASSERT_WITH_CODE(0 == result,
2098 "Failed to initialize Boot State!", return result);
2100 result = polaris10_populate_bapm_parameters_in_dpm_table(hwmgr);
2101 PP_ASSERT_WITH_CODE(0 == result,
2102 "Failed to populate BAPM Parameters!", return result);
2104 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2105 PHM_PlatformCaps_ClockStretcher)) {
2106 result = polaris10_populate_clock_stretcher_data_table(hwmgr);
2107 PP_ASSERT_WITH_CODE(0 == result,
2108 "Failed to populate Clock Stretcher Data Table!",
2112 result = polaris10_populate_avfs_parameters(hwmgr);
2113 PP_ASSERT_WITH_CODE(0 == result, "Failed to populate AVFS Parameters!", return result;);
2115 table->CurrSclkPllRange = 0xff;
2116 table->GraphicsVoltageChangeEnable = 1;
2117 table->GraphicsThermThrottleEnable = 1;
2118 table->GraphicsInterval = 1;
2119 table->VoltageInterval = 1;
2120 table->ThermalInterval = 1;
2121 table->TemperatureLimitHigh =
2122 table_info->cac_dtp_table->usTargetOperatingTemp *
2123 POLARIS10_Q88_FORMAT_CONVERSION_UNIT;
2124 table->TemperatureLimitLow =
2125 (table_info->cac_dtp_table->usTargetOperatingTemp - 1) *
2126 POLARIS10_Q88_FORMAT_CONVERSION_UNIT;
2127 table->MemoryVoltageChangeEnable = 1;
2128 table->MemoryInterval = 1;
2129 table->VoltageResponseTime = 0;
2130 table->PhaseResponseTime = 0;
2131 table->MemoryThermThrottleEnable = 1;
2132 table->PCIeBootLinkLevel = 0;
2133 table->PCIeGenInterval = 1;
2134 table->VRConfig = 0;
2136 result = polaris10_populate_vr_config(hwmgr, table);
2137 PP_ASSERT_WITH_CODE(0 == result,
2138 "Failed to populate VRConfig setting!", return result);
2140 table->ThermGpio = 17;
2141 table->SclkStepSize = 0x4000;
2143 if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_VRHOT_GPIO_PINID, &gpio_pin)) {
2144 table->VRHotGpio = gpio_pin.uc_gpio_pin_bit_shift;
2146 table->VRHotGpio = POLARIS10_UNUSED_GPIO_PIN;
2147 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2148 PHM_PlatformCaps_RegulatorHot);
2151 if (atomctrl_get_pp_assign_pin(hwmgr, PP_AC_DC_SWITCH_GPIO_PINID,
2153 table->AcDcGpio = gpio_pin.uc_gpio_pin_bit_shift;
2154 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2155 PHM_PlatformCaps_AutomaticDCTransition);
2157 table->AcDcGpio = POLARIS10_UNUSED_GPIO_PIN;
2158 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2159 PHM_PlatformCaps_AutomaticDCTransition);
2162 /* Thermal Output GPIO */
2163 if (atomctrl_get_pp_assign_pin(hwmgr, THERMAL_INT_OUTPUT_GPIO_PINID,
2165 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2166 PHM_PlatformCaps_ThermalOutGPIO);
2168 table->ThermOutGpio = gpio_pin.uc_gpio_pin_bit_shift;
2170 /* For porlarity read GPIOPAD_A with assigned Gpio pin
2171 * since VBIOS will program this register to set 'inactive state',
2172 * driver can then determine 'active state' from this and
2173 * program SMU with correct polarity
2175 table->ThermOutPolarity = (0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A)
2176 & (1 << gpio_pin.uc_gpio_pin_bit_shift))) ? 1:0;
2177 table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_ONLY;
2179 /* if required, combine VRHot/PCC with thermal out GPIO */
2180 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_RegulatorHot)
2181 && phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_CombinePCCWithThermalSignal))
2182 table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_VRHOT;
2184 table->ThermOutGpio = 17;
2185 table->ThermOutPolarity = 1;
2186 table->ThermOutMode = SMU7_THERM_OUT_MODE_DISABLE;
2189 /* Populate BIF_SCLK levels into SMC DPM table */
2190 for (i = 0; i <= data->dpm_table.pcie_speed_table.count; i++) {
2191 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, data->bif_sclk_table[i], ÷rs);
2192 PP_ASSERT_WITH_CODE((result == 0), "Can not find DFS divide id for Sclk", return result);
2195 table->Ulv.BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider));
2197 table->LinkLevel[i-1].BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider));
2200 for (i = 0; i < SMU74_MAX_ENTRIES_SMIO; i++)
2201 table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]);
2203 CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags);
2204 CONVERT_FROM_HOST_TO_SMC_UL(table->VRConfig);
2205 CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask1);
2206 CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask2);
2207 CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize);
2208 CONVERT_FROM_HOST_TO_SMC_UL(table->CurrSclkPllRange);
2209 CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh);
2210 CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow);
2211 CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime);
2212 CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);
2214 /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
2215 result = polaris10_copy_bytes_to_smc(hwmgr->smumgr,
2216 data->dpm_table_start +
2217 offsetof(SMU74_Discrete_DpmTable, SystemFlags),
2218 (uint8_t *)&(table->SystemFlags),
2219 sizeof(SMU74_Discrete_DpmTable) - 3 * sizeof(SMU74_PIDController),
2221 PP_ASSERT_WITH_CODE(0 == result,
2222 "Failed to upload dpm data to SMC memory!", return result);
2228 * Initialize the ARB DRAM timing table's index field.
2230 * @param hwmgr the address of the powerplay hardware manager.
2233 static int polaris10_init_arb_table_index(struct pp_hwmgr *hwmgr)
2235 const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2239 /* This is a read-modify-write on the first byte of the ARB table.
2240 * The first byte in the SMU73_Discrete_MCArbDramTimingTable structure
2241 * is the field 'current'.
2242 * This solution is ugly, but we never write the whole table only
2243 * individual fields in it.
2244 * In reality this field should not be in that structure
2245 * but in a soft register.
2247 result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
2248 data->arb_table_start, &tmp, data->sram_end);
2254 tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24;
2256 return polaris10_write_smc_sram_dword(hwmgr->smumgr,
2257 data->arb_table_start, tmp, data->sram_end);
2260 static int polaris10_enable_vrhot_gpio_interrupt(struct pp_hwmgr *hwmgr)
2262 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2263 PHM_PlatformCaps_RegulatorHot))
2264 return smum_send_msg_to_smc(hwmgr->smumgr,
2265 PPSMC_MSG_EnableVRHotGPIOInterrupt);
2270 static int polaris10_enable_sclk_control(struct pp_hwmgr *hwmgr)
2272 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
2273 SCLK_PWRMGT_OFF, 0);
2277 static int polaris10_enable_ulv(struct pp_hwmgr *hwmgr)
2279 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2280 struct polaris10_ulv_parm *ulv = &(data->ulv);
2282 if (ulv->ulv_supported)
2283 return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_EnableULV);
2288 static int polaris10_disable_ulv(struct pp_hwmgr *hwmgr)
2290 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2291 struct polaris10_ulv_parm *ulv = &(data->ulv);
2293 if (ulv->ulv_supported)
2294 return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_DisableULV);
2299 static int polaris10_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
2301 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2302 PHM_PlatformCaps_SclkDeepSleep)) {
2303 if (smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_MASTER_DeepSleep_ON))
2304 PP_ASSERT_WITH_CODE(false,
2305 "Attempt to enable Master Deep Sleep switch failed!",
2308 if (smum_send_msg_to_smc(hwmgr->smumgr,
2309 PPSMC_MSG_MASTER_DeepSleep_OFF)) {
2310 PP_ASSERT_WITH_CODE(false,
2311 "Attempt to disable Master Deep Sleep switch failed!",
2319 static int polaris10_disable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
2321 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2322 PHM_PlatformCaps_SclkDeepSleep)) {
2323 if (smum_send_msg_to_smc(hwmgr->smumgr,
2324 PPSMC_MSG_MASTER_DeepSleep_OFF)) {
2325 PP_ASSERT_WITH_CODE(false,
2326 "Attempt to disable Master Deep Sleep switch failed!",
2334 static int polaris10_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
2336 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2337 uint32_t soft_register_value = 0;
2338 uint32_t handshake_disables_offset = data->soft_regs_start
2339 + offsetof(SMU74_SoftRegisters, HandshakeDisables);
2341 /* enable SCLK dpm */
2342 if (!data->sclk_dpm_key_disabled)
2343 PP_ASSERT_WITH_CODE(
2344 (0 == smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_DPM_Enable)),
2345 "Failed to enable SCLK DPM during DPM Start Function!",
2348 /* enable MCLK dpm */
2349 if (0 == data->mclk_dpm_key_disabled) {
2350 /* Disable UVD - SMU handshake for MCLK. */
2351 soft_register_value = cgs_read_ind_register(hwmgr->device,
2352 CGS_IND_REG__SMC, handshake_disables_offset);
2353 soft_register_value |= SMU7_UVD_MCLK_HANDSHAKE_DISABLE;
2354 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2355 handshake_disables_offset, soft_register_value);
2357 PP_ASSERT_WITH_CODE(
2358 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
2359 PPSMC_MSG_MCLKDPM_Enable)),
2360 "Failed to enable MCLK DPM during DPM Start Function!",
2363 PHM_WRITE_FIELD(hwmgr->device, MC_SEQ_CNTL_3, CAC_EN, 0x1);
2365 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x5);
2366 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x5);
2367 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x100005);
2369 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x400005);
2370 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x400005);
2371 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x500005);
2377 static int polaris10_start_dpm(struct pp_hwmgr *hwmgr)
2379 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2381 /*enable general power management */
2383 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
2384 GLOBAL_PWRMGT_EN, 1);
2386 /* enable sclk deep sleep */
2388 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
2391 /* prepare for PCIE DPM */
2393 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2394 data->soft_regs_start + offsetof(SMU74_SoftRegisters,
2395 VoltageChangeTimeout), 0x1000);
2396 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
2397 SWRST_COMMAND_1, RESETLC, 0x0);
2399 PP_ASSERT_WITH_CODE(
2400 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
2401 PPSMC_MSG_Voltage_Cntl_Enable)),
2402 "Failed to enable voltage DPM during DPM Start Function!",
2406 if (polaris10_enable_sclk_mclk_dpm(hwmgr)) {
2407 printk(KERN_ERR "Failed to enable Sclk DPM and Mclk DPM!");
2411 /* enable PCIE dpm */
2412 if (0 == data->pcie_dpm_key_disabled) {
2413 PP_ASSERT_WITH_CODE(
2414 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
2415 PPSMC_MSG_PCIeDPM_Enable)),
2416 "Failed to enable pcie DPM during DPM Start Function!",
2420 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2421 PHM_PlatformCaps_Falcon_QuickTransition)) {
2422 PP_ASSERT_WITH_CODE((0 == smum_send_msg_to_smc(hwmgr->smumgr,
2423 PPSMC_MSG_EnableACDCGPIOInterrupt)),
2424 "Failed to enable AC DC GPIO Interrupt!",
2431 static int polaris10_disable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
2433 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2435 /* disable SCLK dpm */
2436 if (!data->sclk_dpm_key_disabled)
2437 PP_ASSERT_WITH_CODE(
2438 (smum_send_msg_to_smc(hwmgr->smumgr,
2439 PPSMC_MSG_DPM_Disable) == 0),
2440 "Failed to disable SCLK DPM!",
2443 /* disable MCLK dpm */
2444 if (!data->mclk_dpm_key_disabled) {
2445 PP_ASSERT_WITH_CODE(
2446 (smum_send_msg_to_smc(hwmgr->smumgr,
2447 PPSMC_MSG_MCLKDPM_Disable) == 0),
2448 "Failed to disable MCLK DPM!",
2455 static int polaris10_stop_dpm(struct pp_hwmgr *hwmgr)
2457 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2459 /* disable general power management */
2460 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
2461 GLOBAL_PWRMGT_EN, 0);
2462 /* disable sclk deep sleep */
2463 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
2466 /* disable PCIE dpm */
2467 if (!data->pcie_dpm_key_disabled) {
2468 PP_ASSERT_WITH_CODE(
2469 (smum_send_msg_to_smc(hwmgr->smumgr,
2470 PPSMC_MSG_PCIeDPM_Disable) == 0),
2471 "Failed to disable pcie DPM during DPM Stop Function!",
2475 if (polaris10_disable_sclk_mclk_dpm(hwmgr)) {
2476 printk(KERN_ERR "Failed to disable Sclk DPM and Mclk DPM!");
2483 static void polaris10_set_dpm_event_sources(struct pp_hwmgr *hwmgr, uint32_t sources)
2486 enum DPM_EVENT_SRC src;
2490 printk(KERN_ERR "Unknown throttling event sources.");
2496 case (1 << PHM_AutoThrottleSource_Thermal):
2498 src = DPM_EVENT_SRC_DIGITAL;
2500 case (1 << PHM_AutoThrottleSource_External):
2502 src = DPM_EVENT_SRC_EXTERNAL;
2504 case (1 << PHM_AutoThrottleSource_External) |
2505 (1 << PHM_AutoThrottleSource_Thermal):
2507 src = DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL;
2510 /* Order matters - don't enable thermal protection for the wrong source. */
2512 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_THERMAL_CTRL,
2513 DPM_EVENT_SRC, src);
2514 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
2515 THERMAL_PROTECTION_DIS,
2516 !phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2517 PHM_PlatformCaps_ThermalController));
2519 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
2520 THERMAL_PROTECTION_DIS, 1);
2523 static int polaris10_enable_auto_throttle_source(struct pp_hwmgr *hwmgr,
2524 PHM_AutoThrottleSource source)
2526 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2528 if (!(data->active_auto_throttle_sources & (1 << source))) {
2529 data->active_auto_throttle_sources |= 1 << source;
2530 polaris10_set_dpm_event_sources(hwmgr, data->active_auto_throttle_sources);
2535 static int polaris10_enable_thermal_auto_throttle(struct pp_hwmgr *hwmgr)
2537 return polaris10_enable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal);
2540 static int polaris10_disable_auto_throttle_source(struct pp_hwmgr *hwmgr,
2541 PHM_AutoThrottleSource source)
2543 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2545 if (data->active_auto_throttle_sources & (1 << source)) {
2546 data->active_auto_throttle_sources &= ~(1 << source);
2547 polaris10_set_dpm_event_sources(hwmgr, data->active_auto_throttle_sources);
2552 static int polaris10_disable_thermal_auto_throttle(struct pp_hwmgr *hwmgr)
2554 return polaris10_disable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal);
2557 int polaris10_pcie_performance_request(struct pp_hwmgr *hwmgr)
2559 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2560 data->pcie_performance_request = true;
2565 int polaris10_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
2567 int tmp_result, result = 0;
2568 tmp_result = (!polaris10_is_dpm_running(hwmgr)) ? 0 : -1;
2569 PP_ASSERT_WITH_CODE(result == 0,
2570 "DPM is already running right now, no need to enable DPM!",
2573 if (polaris10_voltage_control(hwmgr)) {
2574 tmp_result = polaris10_enable_voltage_control(hwmgr);
2575 PP_ASSERT_WITH_CODE(tmp_result == 0,
2576 "Failed to enable voltage control!",
2577 result = tmp_result);
2579 tmp_result = polaris10_construct_voltage_tables(hwmgr);
2580 PP_ASSERT_WITH_CODE((0 == tmp_result),
2581 "Failed to contruct voltage tables!",
2582 result = tmp_result);
2585 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2586 PHM_PlatformCaps_EngineSpreadSpectrumSupport))
2587 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
2588 GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, 1);
2590 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2591 PHM_PlatformCaps_ThermalController))
2592 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
2593 GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, 0);
2595 tmp_result = polaris10_program_static_screen_threshold_parameters(hwmgr);
2596 PP_ASSERT_WITH_CODE((0 == tmp_result),
2597 "Failed to program static screen threshold parameters!",
2598 result = tmp_result);
2600 tmp_result = polaris10_enable_display_gap(hwmgr);
2601 PP_ASSERT_WITH_CODE((0 == tmp_result),
2602 "Failed to enable display gap!", result = tmp_result);
2604 tmp_result = polaris10_program_voting_clients(hwmgr);
2605 PP_ASSERT_WITH_CODE((0 == tmp_result),
2606 "Failed to program voting clients!", result = tmp_result);
2608 tmp_result = polaris10_process_firmware_header(hwmgr);
2609 PP_ASSERT_WITH_CODE((0 == tmp_result),
2610 "Failed to process firmware header!", result = tmp_result);
2612 tmp_result = polaris10_initial_switch_from_arbf0_to_f1(hwmgr);
2613 PP_ASSERT_WITH_CODE((0 == tmp_result),
2614 "Failed to initialize switch from ArbF0 to F1!",
2615 result = tmp_result);
2617 tmp_result = polaris10_init_smc_table(hwmgr);
2618 PP_ASSERT_WITH_CODE((0 == tmp_result),
2619 "Failed to initialize SMC table!", result = tmp_result);
2621 tmp_result = polaris10_init_arb_table_index(hwmgr);
2622 PP_ASSERT_WITH_CODE((0 == tmp_result),
2623 "Failed to initialize ARB table index!", result = tmp_result);
2625 tmp_result = polaris10_populate_pm_fuses(hwmgr);
2626 PP_ASSERT_WITH_CODE((0 == tmp_result),
2627 "Failed to populate PM fuses!", result = tmp_result);
2629 tmp_result = polaris10_enable_vrhot_gpio_interrupt(hwmgr);
2630 PP_ASSERT_WITH_CODE((0 == tmp_result),
2631 "Failed to enable VR hot GPIO interrupt!", result = tmp_result);
2633 tmp_result = polaris10_enable_sclk_control(hwmgr);
2634 PP_ASSERT_WITH_CODE((0 == tmp_result),
2635 "Failed to enable SCLK control!", result = tmp_result);
2637 tmp_result = polaris10_enable_smc_voltage_controller(hwmgr);
2638 PP_ASSERT_WITH_CODE((0 == tmp_result),
2639 "Failed to enable voltage control!", result = tmp_result);
2641 tmp_result = polaris10_enable_ulv(hwmgr);
2642 PP_ASSERT_WITH_CODE((0 == tmp_result),
2643 "Failed to enable ULV!", result = tmp_result);
2645 tmp_result = polaris10_enable_deep_sleep_master_switch(hwmgr);
2646 PP_ASSERT_WITH_CODE((0 == tmp_result),
2647 "Failed to enable deep sleep master switch!", result = tmp_result);
2649 tmp_result = polaris10_start_dpm(hwmgr);
2650 PP_ASSERT_WITH_CODE((0 == tmp_result),
2651 "Failed to start DPM!", result = tmp_result);
2653 tmp_result = polaris10_enable_smc_cac(hwmgr);
2654 PP_ASSERT_WITH_CODE((0 == tmp_result),
2655 "Failed to enable SMC CAC!", result = tmp_result);
2657 tmp_result = polaris10_enable_power_containment(hwmgr);
2658 PP_ASSERT_WITH_CODE((0 == tmp_result),
2659 "Failed to enable power containment!", result = tmp_result);
2661 tmp_result = polaris10_power_control_set_level(hwmgr);
2662 PP_ASSERT_WITH_CODE((0 == tmp_result),
2663 "Failed to power control set level!", result = tmp_result);
2665 tmp_result = polaris10_enable_thermal_auto_throttle(hwmgr);
2666 PP_ASSERT_WITH_CODE((0 == tmp_result),
2667 "Failed to enable thermal auto throttle!", result = tmp_result);
2669 tmp_result = polaris10_pcie_performance_request(hwmgr);
2670 PP_ASSERT_WITH_CODE((0 == tmp_result),
2671 "pcie performance request failed!", result = tmp_result);
2676 int polaris10_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
2678 int tmp_result, result = 0;
2680 tmp_result = (polaris10_is_dpm_running(hwmgr)) ? 0 : -1;
2681 PP_ASSERT_WITH_CODE(tmp_result == 0,
2682 "DPM is not running right now, no need to disable DPM!",
2685 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2686 PHM_PlatformCaps_ThermalController))
2687 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
2688 GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, 1);
2690 tmp_result = polaris10_disable_power_containment(hwmgr);
2691 PP_ASSERT_WITH_CODE((tmp_result == 0),
2692 "Failed to disable power containment!", result = tmp_result);
2694 tmp_result = polaris10_disable_smc_cac(hwmgr);
2695 PP_ASSERT_WITH_CODE((tmp_result == 0),
2696 "Failed to disable SMC CAC!", result = tmp_result);
2698 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
2699 CG_SPLL_SPREAD_SPECTRUM, SSEN, 0);
2700 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
2701 GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, 0);
2703 tmp_result = polaris10_disable_thermal_auto_throttle(hwmgr);
2704 PP_ASSERT_WITH_CODE((tmp_result == 0),
2705 "Failed to disable thermal auto throttle!", result = tmp_result);
2707 tmp_result = polaris10_stop_dpm(hwmgr);
2708 PP_ASSERT_WITH_CODE((tmp_result == 0),
2709 "Failed to stop DPM!", result = tmp_result);
2711 tmp_result = polaris10_disable_deep_sleep_master_switch(hwmgr);
2712 PP_ASSERT_WITH_CODE((tmp_result == 0),
2713 "Failed to disable deep sleep master switch!", result = tmp_result);
2715 tmp_result = polaris10_disable_ulv(hwmgr);
2716 PP_ASSERT_WITH_CODE((tmp_result == 0),
2717 "Failed to disable ULV!", result = tmp_result);
2719 tmp_result = polaris10_clear_voting_clients(hwmgr);
2720 PP_ASSERT_WITH_CODE((tmp_result == 0),
2721 "Failed to clear voting clients!", result = tmp_result);
2723 tmp_result = polaris10_reset_to_default(hwmgr);
2724 PP_ASSERT_WITH_CODE((tmp_result == 0),
2725 "Failed to reset to default!", result = tmp_result);
2727 tmp_result = polaris10_force_switch_to_arbf0(hwmgr);
2728 PP_ASSERT_WITH_CODE((tmp_result == 0),
2729 "Failed to force to switch arbf0!", result = tmp_result);
2734 int polaris10_reset_asic_tasks(struct pp_hwmgr *hwmgr)
2740 int polaris10_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
2742 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2744 if (data->soft_pp_table) {
2745 kfree(data->soft_pp_table);
2746 data->soft_pp_table = NULL;
2749 return phm_hwmgr_backend_fini(hwmgr);
2752 int polaris10_set_features_platform_caps(struct pp_hwmgr *hwmgr)
2754 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2756 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2757 PHM_PlatformCaps_SclkDeepSleep);
2759 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2760 PHM_PlatformCaps_DynamicPatchPowerState);
2762 if (data->mvdd_control == POLARIS10_VOLTAGE_CONTROL_NONE)
2763 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2764 PHM_PlatformCaps_EnableMVDDControl);
2766 if (data->vddci_control == POLARIS10_VOLTAGE_CONTROL_NONE)
2767 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2768 PHM_PlatformCaps_ControlVDDCI);
2770 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2771 PHM_PlatformCaps_TablelessHardwareInterface);
2773 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2774 PHM_PlatformCaps_EnableSMU7ThermalManagement);
2776 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2777 PHM_PlatformCaps_DynamicPowerManagement);
2779 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2780 PHM_PlatformCaps_UnTabledHardwareInterface);
2782 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2783 PHM_PlatformCaps_TablelessHardwareInterface);
2785 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2786 PHM_PlatformCaps_SMC);
2788 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2789 PHM_PlatformCaps_NonABMSupportInPPLib);
2791 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2792 PHM_PlatformCaps_DynamicUVDState);
2794 /* power tune caps Assume disabled */
2795 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2796 PHM_PlatformCaps_SQRamping);
2797 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2798 PHM_PlatformCaps_DBRamping);
2799 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2800 PHM_PlatformCaps_TDRamping);
2801 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2802 PHM_PlatformCaps_TCPRamping);
2804 if (hwmgr->powercontainment_enabled)
2805 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2806 PHM_PlatformCaps_PowerContainment);
2808 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2809 PHM_PlatformCaps_PowerContainment);
2811 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2812 PHM_PlatformCaps_CAC);
2814 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2815 PHM_PlatformCaps_RegulatorHot);
2817 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2818 PHM_PlatformCaps_AutomaticDCTransition);
2820 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2821 PHM_PlatformCaps_ODFuzzyFanControlSupport);
2823 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2824 PHM_PlatformCaps_FanSpeedInTableIsRPM);
2826 if (hwmgr->chip_id == CHIP_POLARIS11)
2827 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2828 PHM_PlatformCaps_SPLLShutdownSupport);
2832 static void polaris10_init_dpm_defaults(struct pp_hwmgr *hwmgr)
2834 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2836 polaris10_initialize_power_tune_defaults(hwmgr);
2838 data->pcie_gen_performance.max = PP_PCIEGen1;
2839 data->pcie_gen_performance.min = PP_PCIEGen3;
2840 data->pcie_gen_power_saving.max = PP_PCIEGen1;
2841 data->pcie_gen_power_saving.min = PP_PCIEGen3;
2842 data->pcie_lane_performance.max = 0;
2843 data->pcie_lane_performance.min = 16;
2844 data->pcie_lane_power_saving.max = 0;
2845 data->pcie_lane_power_saving.min = 16;
2849 * Get Leakage VDDC based on leakage ID.
2851 * @param hwmgr the address of the powerplay hardware manager.
2854 static int polaris10_get_evv_voltages(struct pp_hwmgr *hwmgr)
2856 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2861 struct phm_ppt_v1_information *table_info =
2862 (struct phm_ppt_v1_information *)hwmgr->pptable;
2863 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
2864 table_info->vdd_dep_on_sclk;
2867 for (i = 0; i < POLARIS10_MAX_LEAKAGE_COUNT; i++) {
2868 vv_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
2869 if (!phm_get_sclk_for_voltage_evv(hwmgr,
2870 table_info->vddc_lookup_table, vv_id, &sclk)) {
2871 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2872 PHM_PlatformCaps_ClockStretcher)) {
2873 for (j = 1; j < sclk_table->count; j++) {
2874 if (sclk_table->entries[j].clk == sclk &&
2875 sclk_table->entries[j].cks_enable == 0) {
2883 PP_ASSERT_WITH_CODE(0 == atomctrl_get_voltage_evv_on_sclk_ai(hwmgr,
2884 VOLTAGE_TYPE_VDDC, sclk, vv_id, &vddc),
2885 "Error retrieving EVV voltage value!",
2889 /* need to make sure vddc is less than 2v or else, it could burn the ASIC. */
2890 PP_ASSERT_WITH_CODE((vddc < 2000 && vddc != 0),
2891 "Invalid VDDC value", result = -EINVAL;);
2893 /* the voltage should not be zero nor equal to leakage ID */
2894 if (vddc != 0 && vddc != vv_id) {
2895 data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = (uint16_t)(vddc/100);
2896 data->vddc_leakage.leakage_id[data->vddc_leakage.count] = vv_id;
2897 data->vddc_leakage.count++;
2906 * Change virtual leakage voltage to actual value.
2908 * @param hwmgr the address of the powerplay hardware manager.
2909 * @param pointer to changing voltage
2910 * @param pointer to leakage table
2912 static void polaris10_patch_with_vdd_leakage(struct pp_hwmgr *hwmgr,
2913 uint16_t *voltage, struct polaris10_leakage_voltage *leakage_table)
2917 /* search for leakage voltage ID 0xff01 ~ 0xff08 */
2918 for (index = 0; index < leakage_table->count; index++) {
2919 /* if this voltage matches a leakage voltage ID */
2920 /* patch with actual leakage voltage */
2921 if (leakage_table->leakage_id[index] == *voltage) {
2922 *voltage = leakage_table->actual_voltage[index];
2927 if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0)
2928 printk(KERN_ERR "Voltage value looks like a Leakage ID but it's not patched \n");
2932 * Patch voltage lookup table by EVV leakages.
2934 * @param hwmgr the address of the powerplay hardware manager.
2935 * @param pointer to voltage lookup table
2936 * @param pointer to leakage table
2939 static int polaris10_patch_lookup_table_with_leakage(struct pp_hwmgr *hwmgr,
2940 phm_ppt_v1_voltage_lookup_table *lookup_table,
2941 struct polaris10_leakage_voltage *leakage_table)
2945 for (i = 0; i < lookup_table->count; i++)
2946 polaris10_patch_with_vdd_leakage(hwmgr,
2947 &lookup_table->entries[i].us_vdd, leakage_table);
2952 static int polaris10_patch_clock_voltage_limits_with_vddc_leakage(
2953 struct pp_hwmgr *hwmgr, struct polaris10_leakage_voltage *leakage_table,
2956 struct phm_ppt_v1_information *table_info =
2957 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2958 polaris10_patch_with_vdd_leakage(hwmgr, (uint16_t *)vddc, leakage_table);
2959 hwmgr->dyn_state.max_clock_voltage_on_dc.vddc =
2960 table_info->max_clock_voltage_on_dc.vddc;
2964 static int polaris10_patch_voltage_dependency_tables_with_lookup_table(
2965 struct pp_hwmgr *hwmgr)
2969 struct phm_ppt_v1_information *table_info =
2970 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2972 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
2973 table_info->vdd_dep_on_sclk;
2974 struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table =
2975 table_info->vdd_dep_on_mclk;
2976 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
2977 table_info->mm_dep_table;
2979 for (entryId = 0; entryId < sclk_table->count; ++entryId) {
2980 voltageId = sclk_table->entries[entryId].vddInd;
2981 sclk_table->entries[entryId].vddc =
2982 table_info->vddc_lookup_table->entries[voltageId].us_vdd;
2985 for (entryId = 0; entryId < mclk_table->count; ++entryId) {
2986 voltageId = mclk_table->entries[entryId].vddInd;
2987 mclk_table->entries[entryId].vddc =
2988 table_info->vddc_lookup_table->entries[voltageId].us_vdd;
2991 for (entryId = 0; entryId < mm_table->count; ++entryId) {
2992 voltageId = mm_table->entries[entryId].vddcInd;
2993 mm_table->entries[entryId].vddc =
2994 table_info->vddc_lookup_table->entries[voltageId].us_vdd;
3001 static int polaris10_calc_voltage_dependency_tables(struct pp_hwmgr *hwmgr)
3003 /* Need to determine if we need calculated voltage. */
3007 static int polaris10_calc_mm_voltage_dependency_table(struct pp_hwmgr *hwmgr)
3009 /* Need to determine if we need calculated voltage from mm table. */
3013 static int polaris10_sort_lookup_table(struct pp_hwmgr *hwmgr,
3014 struct phm_ppt_v1_voltage_lookup_table *lookup_table)
3016 uint32_t table_size, i, j;
3017 struct phm_ppt_v1_voltage_lookup_record tmp_voltage_lookup_record;
3018 table_size = lookup_table->count;
3020 PP_ASSERT_WITH_CODE(0 != lookup_table->count,
3021 "Lookup table is empty", return -EINVAL);
3023 /* Sorting voltages */
3024 for (i = 0; i < table_size - 1; i++) {
3025 for (j = i + 1; j > 0; j--) {
3026 if (lookup_table->entries[j].us_vdd <
3027 lookup_table->entries[j - 1].us_vdd) {
3028 tmp_voltage_lookup_record = lookup_table->entries[j - 1];
3029 lookup_table->entries[j - 1] = lookup_table->entries[j];
3030 lookup_table->entries[j] = tmp_voltage_lookup_record;
3038 static int polaris10_complete_dependency_tables(struct pp_hwmgr *hwmgr)
3042 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3043 struct phm_ppt_v1_information *table_info =
3044 (struct phm_ppt_v1_information *)(hwmgr->pptable);
3046 tmp_result = polaris10_patch_lookup_table_with_leakage(hwmgr,
3047 table_info->vddc_lookup_table, &(data->vddc_leakage));
3049 result = tmp_result;
3051 tmp_result = polaris10_patch_clock_voltage_limits_with_vddc_leakage(hwmgr,
3052 &(data->vddc_leakage), &table_info->max_clock_voltage_on_dc.vddc);
3054 result = tmp_result;
3056 tmp_result = polaris10_patch_voltage_dependency_tables_with_lookup_table(hwmgr);
3058 result = tmp_result;
3060 tmp_result = polaris10_calc_voltage_dependency_tables(hwmgr);
3062 result = tmp_result;
3064 tmp_result = polaris10_calc_mm_voltage_dependency_table(hwmgr);
3066 result = tmp_result;
3068 tmp_result = polaris10_sort_lookup_table(hwmgr, table_info->vddc_lookup_table);
3070 result = tmp_result;
3075 static int polaris10_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr)
3077 struct phm_ppt_v1_information *table_info =
3078 (struct phm_ppt_v1_information *)(hwmgr->pptable);
3080 struct phm_ppt_v1_clock_voltage_dependency_table *allowed_sclk_vdd_table =
3081 table_info->vdd_dep_on_sclk;
3082 struct phm_ppt_v1_clock_voltage_dependency_table *allowed_mclk_vdd_table =
3083 table_info->vdd_dep_on_mclk;
3085 PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table != NULL,
3086 "VDD dependency on SCLK table is missing. \
3087 This table is mandatory", return -EINVAL);
3088 PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1,
3089 "VDD dependency on SCLK table has to have is missing. \
3090 This table is mandatory", return -EINVAL);
3092 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table != NULL,
3093 "VDD dependency on MCLK table is missing. \
3094 This table is mandatory", return -EINVAL);
3095 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1,
3096 "VDD dependency on MCLK table has to have is missing. \
3097 This table is mandatory", return -EINVAL);
3099 table_info->max_clock_voltage_on_ac.sclk =
3100 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].clk;
3101 table_info->max_clock_voltage_on_ac.mclk =
3102 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk;
3103 table_info->max_clock_voltage_on_ac.vddc =
3104 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc;
3105 table_info->max_clock_voltage_on_ac.vddci =
3106 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci;
3108 hwmgr->dyn_state.max_clock_voltage_on_ac.sclk = table_info->max_clock_voltage_on_ac.sclk;
3109 hwmgr->dyn_state.max_clock_voltage_on_ac.mclk = table_info->max_clock_voltage_on_ac.mclk;
3110 hwmgr->dyn_state.max_clock_voltage_on_ac.vddc = table_info->max_clock_voltage_on_ac.vddc;
3111 hwmgr->dyn_state.max_clock_voltage_on_ac.vddci =table_info->max_clock_voltage_on_ac.vddci;
3116 int polaris10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
3118 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3119 struct pp_atomctrl_gpio_pin_assignment gpio_pin_assignment;
3122 struct phm_ppt_v1_information *table_info =
3123 (struct phm_ppt_v1_information *)(hwmgr->pptable);
3125 data->dll_default_on = false;
3126 data->sram_end = SMC_RAM_END;
3127 data->mclk_dpm0_activity_target = 0xa;
3128 data->disable_dpm_mask = 0xFF;
3129 data->static_screen_threshold = PPPOLARIS10_STATICSCREENTHRESHOLD_DFLT;
3130 data->static_screen_threshold_unit = PPPOLARIS10_STATICSCREENTHRESHOLD_DFLT;
3131 data->activity_target[0] = PPPOLARIS10_TARGETACTIVITY_DFLT;
3132 data->activity_target[1] = PPPOLARIS10_TARGETACTIVITY_DFLT;
3133 data->activity_target[2] = PPPOLARIS10_TARGETACTIVITY_DFLT;
3134 data->activity_target[3] = PPPOLARIS10_TARGETACTIVITY_DFLT;
3135 data->activity_target[4] = PPPOLARIS10_TARGETACTIVITY_DFLT;
3136 data->activity_target[5] = PPPOLARIS10_TARGETACTIVITY_DFLT;
3137 data->activity_target[6] = PPPOLARIS10_TARGETACTIVITY_DFLT;
3138 data->activity_target[7] = PPPOLARIS10_TARGETACTIVITY_DFLT;
3140 data->voting_rights_clients0 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT0;
3141 data->voting_rights_clients1 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT1;
3142 data->voting_rights_clients2 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT2;
3143 data->voting_rights_clients3 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT3;
3144 data->voting_rights_clients4 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT4;
3145 data->voting_rights_clients5 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT5;
3146 data->voting_rights_clients6 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT6;
3147 data->voting_rights_clients7 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT7;
3149 data->vddc_vddci_delta = VDDC_VDDCI_DELTA;
3151 data->mclk_activity_target = PPPOLARIS10_MCLK_TARGETACTIVITY_DFLT;
3153 /* need to set voltage control types before EVV patching */
3154 data->voltage_control = POLARIS10_VOLTAGE_CONTROL_NONE;
3155 data->vddci_control = POLARIS10_VOLTAGE_CONTROL_NONE;
3156 data->mvdd_control = POLARIS10_VOLTAGE_CONTROL_NONE;
3158 data->enable_tdc_limit_feature = true;
3159 data->enable_pkg_pwr_tracking_feature = true;
3160 data->force_pcie_gen = PP_PCIEGenInvalid;
3161 data->mclk_stutter_mode_threshold = 40000;
3163 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
3164 VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2))
3165 data->voltage_control = POLARIS10_VOLTAGE_CONTROL_BY_SVID2;
3167 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3168 PHM_PlatformCaps_EnableMVDDControl)) {
3169 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
3170 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT))
3171 data->mvdd_control = POLARIS10_VOLTAGE_CONTROL_BY_GPIO;
3172 else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
3173 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2))
3174 data->mvdd_control = POLARIS10_VOLTAGE_CONTROL_BY_SVID2;
3177 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3178 PHM_PlatformCaps_ControlVDDCI)) {
3179 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
3180 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
3181 data->vddci_control = POLARIS10_VOLTAGE_CONTROL_BY_GPIO;
3182 else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
3183 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2))
3184 data->vddci_control = POLARIS10_VOLTAGE_CONTROL_BY_SVID2;
3187 if (table_info->cac_dtp_table->usClockStretchAmount != 0)
3188 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
3189 PHM_PlatformCaps_ClockStretcher);
3191 polaris10_set_features_platform_caps(hwmgr);
3193 polaris10_init_dpm_defaults(hwmgr);
3195 /* Get leakage voltage based on leakage ID. */
3196 result = polaris10_get_evv_voltages(hwmgr);
3199 printk("Get EVV Voltage Failed. Abort Driver loading!\n");
3203 polaris10_complete_dependency_tables(hwmgr);
3204 polaris10_set_private_data_based_on_pptable(hwmgr);
3206 /* Initalize Dynamic State Adjustment Rule Settings */
3207 result = phm_initializa_dynamic_state_adjustment_rule_settings(hwmgr);
3210 struct cgs_system_info sys_info = {0};
3212 data->is_tlu_enabled = 0;
3214 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
3215 POLARIS10_MAX_HARDWARE_POWERLEVELS;
3216 hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
3217 hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
3220 if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_PCC_GPIO_PINID, &gpio_pin_assignment)) {
3221 temp_reg = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL);
3222 switch (gpio_pin_assignment.uc_gpio_pin_bit_shift) {
3224 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x1);
3227 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x2);
3230 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW, 0x1);
3233 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, FORCE_NB_PS1, 0x1);
3236 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, DPM_ENABLED, 0x1);
3239 PP_ASSERT_WITH_CODE(0,
3240 "Failed to setup PCC HW register! Wrong GPIO assigned for VDDC_PCC_GPIO_PINID!",
3244 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL, temp_reg);
3247 if (table_info->cac_dtp_table->usDefaultTargetOperatingTemp != 0 &&
3248 hwmgr->thermal_controller.advanceFanControlParameters.ucFanControlMode) {
3249 hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMinLimit =
3250 (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit;
3252 hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMaxLimit =
3253 (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM;
3255 hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMStep = 1;
3257 hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMaxLimit = 100;
3259 hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMinLimit =
3260 (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit;
3262 hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMStep = 1;
3264 table_info->cac_dtp_table->usDefaultTargetOperatingTemp = (table_info->cac_dtp_table->usDefaultTargetOperatingTemp >= 50) ?
3265 (table_info->cac_dtp_table->usDefaultTargetOperatingTemp -50) : 0;
3267 table_info->cac_dtp_table->usOperatingTempMaxLimit = table_info->cac_dtp_table->usDefaultTargetOperatingTemp;
3268 table_info->cac_dtp_table->usOperatingTempStep = 1;
3269 table_info->cac_dtp_table->usOperatingTempHyst = 1;
3271 hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanPWM =
3272 hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM;
3274 hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM =
3275 hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanRPM;
3277 hwmgr->dyn_state.cac_dtp_table->usOperatingTempMinLimit =
3278 table_info->cac_dtp_table->usOperatingTempMinLimit;
3280 hwmgr->dyn_state.cac_dtp_table->usOperatingTempMaxLimit =
3281 table_info->cac_dtp_table->usOperatingTempMaxLimit;
3283 hwmgr->dyn_state.cac_dtp_table->usDefaultTargetOperatingTemp =
3284 table_info->cac_dtp_table->usDefaultTargetOperatingTemp;
3286 hwmgr->dyn_state.cac_dtp_table->usOperatingTempStep =
3287 table_info->cac_dtp_table->usOperatingTempStep;
3289 hwmgr->dyn_state.cac_dtp_table->usTargetOperatingTemp =
3290 table_info->cac_dtp_table->usTargetOperatingTemp;
3293 sys_info.size = sizeof(struct cgs_system_info);
3294 sys_info.info_id = CGS_SYSTEM_INFO_PCIE_GEN_INFO;
3295 result = cgs_query_system_info(hwmgr->device, &sys_info);
3297 data->pcie_gen_cap = 0x30007;
3299 data->pcie_gen_cap = (uint32_t)sys_info.value;
3300 if (data->pcie_gen_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
3301 data->pcie_spc_cap = 20;
3302 sys_info.size = sizeof(struct cgs_system_info);
3303 sys_info.info_id = CGS_SYSTEM_INFO_PCIE_MLW;
3304 result = cgs_query_system_info(hwmgr->device, &sys_info);
3306 data->pcie_lane_cap = 0x2f0000;
3308 data->pcie_lane_cap = (uint32_t)sys_info.value;
3310 hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */
3311 /* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */
3312 hwmgr->platform_descriptor.clockStep.engineClock = 500;
3313 hwmgr->platform_descriptor.clockStep.memoryClock = 500;
3315 /* Ignore return value in here, we are cleaning up a mess. */
3316 polaris10_hwmgr_backend_fini(hwmgr);
3322 static int polaris10_force_dpm_highest(struct pp_hwmgr *hwmgr)
3324 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3325 uint32_t level, tmp;
3327 if (!data->pcie_dpm_key_disabled) {
3328 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3330 tmp = data->dpm_level_enable_mask.pcie_dpm_enable_mask;
3335 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3336 PPSMC_MSG_PCIeDPM_ForceLevel, level);
3340 if (!data->sclk_dpm_key_disabled) {
3341 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3343 tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask;
3348 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3349 PPSMC_MSG_SCLKDPM_SetEnabledMask,
3354 if (!data->mclk_dpm_key_disabled) {
3355 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3357 tmp = data->dpm_level_enable_mask.mclk_dpm_enable_mask;
3362 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3363 PPSMC_MSG_MCLKDPM_SetEnabledMask,
3371 static int polaris10_upload_dpm_level_enable_mask(struct pp_hwmgr *hwmgr)
3373 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3375 phm_apply_dal_min_voltage_request(hwmgr);
3377 if (!data->sclk_dpm_key_disabled) {
3378 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask)
3379 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3380 PPSMC_MSG_SCLKDPM_SetEnabledMask,
3381 data->dpm_level_enable_mask.sclk_dpm_enable_mask);
3384 if (!data->mclk_dpm_key_disabled) {
3385 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask)
3386 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3387 PPSMC_MSG_MCLKDPM_SetEnabledMask,
3388 data->dpm_level_enable_mask.mclk_dpm_enable_mask);
3394 static int polaris10_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
3396 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3398 if (!polaris10_is_dpm_running(hwmgr))
3401 if (!data->pcie_dpm_key_disabled) {
3402 smum_send_msg_to_smc(hwmgr->smumgr,
3403 PPSMC_MSG_PCIeDPM_UnForceLevel);
3406 return polaris10_upload_dpm_level_enable_mask(hwmgr);
3409 static int polaris10_force_dpm_lowest(struct pp_hwmgr *hwmgr)
3411 struct polaris10_hwmgr *data =
3412 (struct polaris10_hwmgr *)(hwmgr->backend);
3415 if (!data->sclk_dpm_key_disabled)
3416 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3417 level = phm_get_lowest_enabled_level(hwmgr,
3418 data->dpm_level_enable_mask.sclk_dpm_enable_mask);
3419 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3420 PPSMC_MSG_SCLKDPM_SetEnabledMask,
3425 if (!data->mclk_dpm_key_disabled) {
3426 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3427 level = phm_get_lowest_enabled_level(hwmgr,
3428 data->dpm_level_enable_mask.mclk_dpm_enable_mask);
3429 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3430 PPSMC_MSG_MCLKDPM_SetEnabledMask,
3435 if (!data->pcie_dpm_key_disabled) {
3436 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3437 level = phm_get_lowest_enabled_level(hwmgr,
3438 data->dpm_level_enable_mask.pcie_dpm_enable_mask);
3439 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3440 PPSMC_MSG_PCIeDPM_ForceLevel,
3448 static int polaris10_force_dpm_level(struct pp_hwmgr *hwmgr,
3449 enum amd_dpm_forced_level level)
3454 case AMD_DPM_FORCED_LEVEL_HIGH:
3455 ret = polaris10_force_dpm_highest(hwmgr);
3459 case AMD_DPM_FORCED_LEVEL_LOW:
3460 ret = polaris10_force_dpm_lowest(hwmgr);
3464 case AMD_DPM_FORCED_LEVEL_AUTO:
3465 ret = polaris10_unforce_dpm_levels(hwmgr);
3473 hwmgr->dpm_level = level;
3478 static int polaris10_get_power_state_size(struct pp_hwmgr *hwmgr)
3480 return sizeof(struct polaris10_power_state);
3484 static int polaris10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
3485 struct pp_power_state *request_ps,
3486 const struct pp_power_state *current_ps)
3489 struct polaris10_power_state *polaris10_ps =
3490 cast_phw_polaris10_power_state(&request_ps->hardware);
3493 struct PP_Clocks minimum_clocks = {0};
3494 bool disable_mclk_switching;
3495 bool disable_mclk_switching_for_frame_lock;
3496 struct cgs_display_info info = {0};
3497 const struct phm_clock_and_voltage_limits *max_limits;
3499 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3500 struct phm_ppt_v1_information *table_info =
3501 (struct phm_ppt_v1_information *)(hwmgr->pptable);
3503 int32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0;
3505 data->battery_state = (PP_StateUILabel_Battery ==
3506 request_ps->classification.ui_label);
3508 PP_ASSERT_WITH_CODE(polaris10_ps->performance_level_count == 2,
3509 "VI should always have 2 performance levels",
3512 max_limits = (PP_PowerSource_AC == hwmgr->power_source) ?
3513 &(hwmgr->dyn_state.max_clock_voltage_on_ac) :
3514 &(hwmgr->dyn_state.max_clock_voltage_on_dc);
3516 /* Cap clock DPM tables at DC MAX if it is in DC. */
3517 if (PP_PowerSource_DC == hwmgr->power_source) {
3518 for (i = 0; i < polaris10_ps->performance_level_count; i++) {
3519 if (polaris10_ps->performance_levels[i].memory_clock > max_limits->mclk)
3520 polaris10_ps->performance_levels[i].memory_clock = max_limits->mclk;
3521 if (polaris10_ps->performance_levels[i].engine_clock > max_limits->sclk)
3522 polaris10_ps->performance_levels[i].engine_clock = max_limits->sclk;
3526 polaris10_ps->vce_clks.evclk = hwmgr->vce_arbiter.evclk;
3527 polaris10_ps->vce_clks.ecclk = hwmgr->vce_arbiter.ecclk;
3529 cgs_get_active_displays_info(hwmgr->device, &info);
3531 /*TO DO result = PHM_CheckVBlankTime(hwmgr, &vblankTooShort);*/
3533 /* TO DO GetMinClockSettings(hwmgr->pPECI, &minimum_clocks); */
3535 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3536 PHM_PlatformCaps_StablePState)) {
3537 max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac);
3538 stable_pstate_sclk = (max_limits->sclk * 75) / 100;
3540 for (count = table_info->vdd_dep_on_sclk->count - 1;
3541 count >= 0; count--) {
3542 if (stable_pstate_sclk >=
3543 table_info->vdd_dep_on_sclk->entries[count].clk) {
3544 stable_pstate_sclk =
3545 table_info->vdd_dep_on_sclk->entries[count].clk;
3551 stable_pstate_sclk = table_info->vdd_dep_on_sclk->entries[0].clk;
3553 stable_pstate_mclk = max_limits->mclk;
3555 minimum_clocks.engineClock = stable_pstate_sclk;
3556 minimum_clocks.memoryClock = stable_pstate_mclk;
3559 if (minimum_clocks.engineClock < hwmgr->gfx_arbiter.sclk)
3560 minimum_clocks.engineClock = hwmgr->gfx_arbiter.sclk;
3562 if (minimum_clocks.memoryClock < hwmgr->gfx_arbiter.mclk)
3563 minimum_clocks.memoryClock = hwmgr->gfx_arbiter.mclk;
3565 polaris10_ps->sclk_threshold = hwmgr->gfx_arbiter.sclk_threshold;
3567 if (0 != hwmgr->gfx_arbiter.sclk_over_drive) {
3568 PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.sclk_over_drive <=
3569 hwmgr->platform_descriptor.overdriveLimit.engineClock),
3570 "Overdrive sclk exceeds limit",
3571 hwmgr->gfx_arbiter.sclk_over_drive =
3572 hwmgr->platform_descriptor.overdriveLimit.engineClock);
3574 if (hwmgr->gfx_arbiter.sclk_over_drive >= hwmgr->gfx_arbiter.sclk)
3575 polaris10_ps->performance_levels[1].engine_clock =
3576 hwmgr->gfx_arbiter.sclk_over_drive;
3579 if (0 != hwmgr->gfx_arbiter.mclk_over_drive) {
3580 PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.mclk_over_drive <=
3581 hwmgr->platform_descriptor.overdriveLimit.memoryClock),
3582 "Overdrive mclk exceeds limit",
3583 hwmgr->gfx_arbiter.mclk_over_drive =
3584 hwmgr->platform_descriptor.overdriveLimit.memoryClock);
3586 if (hwmgr->gfx_arbiter.mclk_over_drive >= hwmgr->gfx_arbiter.mclk)
3587 polaris10_ps->performance_levels[1].memory_clock =
3588 hwmgr->gfx_arbiter.mclk_over_drive;
3591 disable_mclk_switching_for_frame_lock = phm_cap_enabled(
3592 hwmgr->platform_descriptor.platformCaps,
3593 PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);
3595 disable_mclk_switching = (1 < info.display_count) ||
3596 disable_mclk_switching_for_frame_lock;
3598 sclk = polaris10_ps->performance_levels[0].engine_clock;
3599 mclk = polaris10_ps->performance_levels[0].memory_clock;
3601 if (disable_mclk_switching)
3602 mclk = polaris10_ps->performance_levels
3603 [polaris10_ps->performance_level_count - 1].memory_clock;
3605 if (sclk < minimum_clocks.engineClock)
3606 sclk = (minimum_clocks.engineClock > max_limits->sclk) ?
3607 max_limits->sclk : minimum_clocks.engineClock;
3609 if (mclk < minimum_clocks.memoryClock)
3610 mclk = (minimum_clocks.memoryClock > max_limits->mclk) ?
3611 max_limits->mclk : minimum_clocks.memoryClock;
3613 polaris10_ps->performance_levels[0].engine_clock = sclk;
3614 polaris10_ps->performance_levels[0].memory_clock = mclk;
3616 polaris10_ps->performance_levels[1].engine_clock =
3617 (polaris10_ps->performance_levels[1].engine_clock >=
3618 polaris10_ps->performance_levels[0].engine_clock) ?
3619 polaris10_ps->performance_levels[1].engine_clock :
3620 polaris10_ps->performance_levels[0].engine_clock;
3622 if (disable_mclk_switching) {
3623 if (mclk < polaris10_ps->performance_levels[1].memory_clock)
3624 mclk = polaris10_ps->performance_levels[1].memory_clock;
3626 polaris10_ps->performance_levels[0].memory_clock = mclk;
3627 polaris10_ps->performance_levels[1].memory_clock = mclk;
3629 if (polaris10_ps->performance_levels[1].memory_clock <
3630 polaris10_ps->performance_levels[0].memory_clock)
3631 polaris10_ps->performance_levels[1].memory_clock =
3632 polaris10_ps->performance_levels[0].memory_clock;
3635 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3636 PHM_PlatformCaps_StablePState)) {
3637 for (i = 0; i < polaris10_ps->performance_level_count; i++) {
3638 polaris10_ps->performance_levels[i].engine_clock = stable_pstate_sclk;
3639 polaris10_ps->performance_levels[i].memory_clock = stable_pstate_mclk;
3640 polaris10_ps->performance_levels[i].pcie_gen = data->pcie_gen_performance.max;
3641 polaris10_ps->performance_levels[i].pcie_lane = data->pcie_gen_performance.max;
3648 static int polaris10_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
3650 struct pp_power_state *ps;
3651 struct polaris10_power_state *polaris10_ps;
3656 ps = hwmgr->request_ps;
3661 polaris10_ps = cast_phw_polaris10_power_state(&ps->hardware);
3664 return polaris10_ps->performance_levels[0].memory_clock;
3666 return polaris10_ps->performance_levels
3667 [polaris10_ps->performance_level_count-1].memory_clock;
3670 static int polaris10_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
3672 struct pp_power_state *ps;
3673 struct polaris10_power_state *polaris10_ps;
3678 ps = hwmgr->request_ps;
3683 polaris10_ps = cast_phw_polaris10_power_state(&ps->hardware);
3686 return polaris10_ps->performance_levels[0].engine_clock;
3688 return polaris10_ps->performance_levels
3689 [polaris10_ps->performance_level_count-1].engine_clock;
3692 static int polaris10_dpm_patch_boot_state(struct pp_hwmgr *hwmgr,
3693 struct pp_hw_power_state *hw_ps)
3695 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3696 struct polaris10_power_state *ps = (struct polaris10_power_state *)hw_ps;
3697 ATOM_FIRMWARE_INFO_V2_2 *fw_info;
3700 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
3702 /* First retrieve the Boot clocks and VDDC from the firmware info table.
3703 * We assume here that fw_info is unchanged if this call fails.
3705 fw_info = (ATOM_FIRMWARE_INFO_V2_2 *)cgs_atom_get_data_table(
3706 hwmgr->device, index,
3707 &size, &frev, &crev);
3709 /* During a test, there is no firmware info table. */
3712 /* Patch the state. */
3713 data->vbios_boot_state.sclk_bootup_value =
3714 le32_to_cpu(fw_info->ulDefaultEngineClock);
3715 data->vbios_boot_state.mclk_bootup_value =
3716 le32_to_cpu(fw_info->ulDefaultMemoryClock);
3717 data->vbios_boot_state.mvdd_bootup_value =
3718 le16_to_cpu(fw_info->usBootUpMVDDCVoltage);
3719 data->vbios_boot_state.vddc_bootup_value =
3720 le16_to_cpu(fw_info->usBootUpVDDCVoltage);
3721 data->vbios_boot_state.vddci_bootup_value =
3722 le16_to_cpu(fw_info->usBootUpVDDCIVoltage);
3723 data->vbios_boot_state.pcie_gen_bootup_value =
3724 phm_get_current_pcie_speed(hwmgr);
3726 data->vbios_boot_state.pcie_lane_bootup_value =
3727 (uint16_t)phm_get_current_pcie_lane_number(hwmgr);
3729 /* set boot power state */
3730 ps->performance_levels[0].memory_clock = data->vbios_boot_state.mclk_bootup_value;
3731 ps->performance_levels[0].engine_clock = data->vbios_boot_state.sclk_bootup_value;
3732 ps->performance_levels[0].pcie_gen = data->vbios_boot_state.pcie_gen_bootup_value;
3733 ps->performance_levels[0].pcie_lane = data->vbios_boot_state.pcie_lane_bootup_value;
3738 static int polaris10_get_pp_table_entry_callback_func(struct pp_hwmgr *hwmgr,
3739 void *state, struct pp_power_state *power_state,
3740 void *pp_table, uint32_t classification_flag)
3742 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3743 struct polaris10_power_state *polaris10_power_state =
3744 (struct polaris10_power_state *)(&(power_state->hardware));
3745 struct polaris10_performance_level *performance_level;
3746 ATOM_Tonga_State *state_entry = (ATOM_Tonga_State *)state;
3747 ATOM_Tonga_POWERPLAYTABLE *powerplay_table =
3748 (ATOM_Tonga_POWERPLAYTABLE *)pp_table;
3749 PPTable_Generic_SubTable_Header *sclk_dep_table =
3750 (PPTable_Generic_SubTable_Header *)
3751 (((unsigned long)powerplay_table) +
3752 le16_to_cpu(powerplay_table->usSclkDependencyTableOffset));
3754 ATOM_Tonga_MCLK_Dependency_Table *mclk_dep_table =
3755 (ATOM_Tonga_MCLK_Dependency_Table *)
3756 (((unsigned long)powerplay_table) +
3757 le16_to_cpu(powerplay_table->usMclkDependencyTableOffset));
3759 /* The following fields are not initialized here: id orderedList allStatesList */
3760 power_state->classification.ui_label =
3761 (le16_to_cpu(state_entry->usClassification) &
3762 ATOM_PPLIB_CLASSIFICATION_UI_MASK) >>
3763 ATOM_PPLIB_CLASSIFICATION_UI_SHIFT;
3764 power_state->classification.flags = classification_flag;
3765 /* NOTE: There is a classification2 flag in BIOS that is not being used right now */
3767 power_state->classification.temporary_state = false;
3768 power_state->classification.to_be_deleted = false;
3770 power_state->validation.disallowOnDC =
3771 (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) &
3772 ATOM_Tonga_DISALLOW_ON_DC));
3774 power_state->pcie.lanes = 0;
3776 power_state->display.disableFrameModulation = false;
3777 power_state->display.limitRefreshrate = false;
3778 power_state->display.enableVariBright =
3779 (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) &
3780 ATOM_Tonga_ENABLE_VARIBRIGHT));
3782 power_state->validation.supportedPowerLevels = 0;
3783 power_state->uvd_clocks.VCLK = 0;
3784 power_state->uvd_clocks.DCLK = 0;
3785 power_state->temperatures.min = 0;
3786 power_state->temperatures.max = 0;
3788 performance_level = &(polaris10_power_state->performance_levels
3789 [polaris10_power_state->performance_level_count++]);
3791 PP_ASSERT_WITH_CODE(
3792 (polaris10_power_state->performance_level_count < SMU74_MAX_LEVELS_GRAPHICS),
3793 "Performance levels exceeds SMC limit!",
3796 PP_ASSERT_WITH_CODE(
3797 (polaris10_power_state->performance_level_count <=
3798 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels),
3799 "Performance levels exceeds Driver limit!",
3802 /* Performance levels are arranged from low to high. */
3803 performance_level->memory_clock = mclk_dep_table->entries
3804 [state_entry->ucMemoryClockIndexLow].ulMclk;
3805 if (sclk_dep_table->ucRevId == 0)
3806 performance_level->engine_clock = ((ATOM_Tonga_SCLK_Dependency_Table *)sclk_dep_table)->entries
3807 [state_entry->ucEngineClockIndexLow].ulSclk;
3808 else if (sclk_dep_table->ucRevId == 1)
3809 performance_level->engine_clock = ((ATOM_Polaris_SCLK_Dependency_Table *)sclk_dep_table)->entries
3810 [state_entry->ucEngineClockIndexLow].ulSclk;
3811 performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap,
3812 state_entry->ucPCIEGenLow);
3813 performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap,
3814 state_entry->ucPCIELaneHigh);
3816 performance_level = &(polaris10_power_state->performance_levels
3817 [polaris10_power_state->performance_level_count++]);
3818 performance_level->memory_clock = mclk_dep_table->entries
3819 [state_entry->ucMemoryClockIndexHigh].ulMclk;
3821 if (sclk_dep_table->ucRevId == 0)
3822 performance_level->engine_clock = ((ATOM_Tonga_SCLK_Dependency_Table *)sclk_dep_table)->entries
3823 [state_entry->ucEngineClockIndexHigh].ulSclk;
3824 else if (sclk_dep_table->ucRevId == 1)
3825 performance_level->engine_clock = ((ATOM_Polaris_SCLK_Dependency_Table *)sclk_dep_table)->entries
3826 [state_entry->ucEngineClockIndexHigh].ulSclk;
3828 performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap,
3829 state_entry->ucPCIEGenHigh);
3830 performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap,
3831 state_entry->ucPCIELaneHigh);
3836 static int polaris10_get_pp_table_entry(struct pp_hwmgr *hwmgr,
3837 unsigned long entry_index, struct pp_power_state *state)
3840 struct polaris10_power_state *ps;
3841 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3842 struct phm_ppt_v1_information *table_info =
3843 (struct phm_ppt_v1_information *)(hwmgr->pptable);
3844 struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
3845 table_info->vdd_dep_on_mclk;
3847 state->hardware.magic = PHM_VIslands_Magic;
3849 ps = (struct polaris10_power_state *)(&state->hardware);
3851 result = tonga_get_powerplay_table_entry(hwmgr, entry_index, state,
3852 polaris10_get_pp_table_entry_callback_func);
3854 /* This is the earliest time we have all the dependency table and the VBIOS boot state
3855 * as PP_Tables_GetPowerPlayTableEntry retrieves the VBIOS boot state
3856 * if there is only one VDDCI/MCLK level, check if it's the same as VBIOS boot state
3858 if (dep_mclk_table != NULL && dep_mclk_table->count == 1) {
3859 if (dep_mclk_table->entries[0].clk !=
3860 data->vbios_boot_state.mclk_bootup_value)
3861 printk(KERN_ERR "Single MCLK entry VDDCI/MCLK dependency table "
3862 "does not match VBIOS boot MCLK level");
3863 if (dep_mclk_table->entries[0].vddci !=
3864 data->vbios_boot_state.vddci_bootup_value)
3865 printk(KERN_ERR "Single VDDCI entry VDDCI/MCLK dependency table "
3866 "does not match VBIOS boot VDDCI level");
3869 /* set DC compatible flag if this state supports DC */
3870 if (!state->validation.disallowOnDC)
3871 ps->dc_compatible = true;
3873 if (state->classification.flags & PP_StateClassificationFlag_ACPI)
3874 data->acpi_pcie_gen = ps->performance_levels[0].pcie_gen;
3876 ps->uvd_clks.vclk = state->uvd_clocks.VCLK;
3877 ps->uvd_clks.dclk = state->uvd_clocks.DCLK;
3882 switch (state->classification.ui_label) {
3883 case PP_StateUILabel_Performance:
3884 data->use_pcie_performance_levels = true;
3885 for (i = 0; i < ps->performance_level_count; i++) {
3886 if (data->pcie_gen_performance.max <
3887 ps->performance_levels[i].pcie_gen)
3888 data->pcie_gen_performance.max =
3889 ps->performance_levels[i].pcie_gen;
3891 if (data->pcie_gen_performance.min >
3892 ps->performance_levels[i].pcie_gen)
3893 data->pcie_gen_performance.min =
3894 ps->performance_levels[i].pcie_gen;
3896 if (data->pcie_lane_performance.max <
3897 ps->performance_levels[i].pcie_lane)
3898 data->pcie_lane_performance.max =
3899 ps->performance_levels[i].pcie_lane;
3900 if (data->pcie_lane_performance.min >
3901 ps->performance_levels[i].pcie_lane)
3902 data->pcie_lane_performance.min =
3903 ps->performance_levels[i].pcie_lane;
3906 case PP_StateUILabel_Battery:
3907 data->use_pcie_power_saving_levels = true;
3909 for (i = 0; i < ps->performance_level_count; i++) {
3910 if (data->pcie_gen_power_saving.max <
3911 ps->performance_levels[i].pcie_gen)
3912 data->pcie_gen_power_saving.max =
3913 ps->performance_levels[i].pcie_gen;
3915 if (data->pcie_gen_power_saving.min >
3916 ps->performance_levels[i].pcie_gen)
3917 data->pcie_gen_power_saving.min =
3918 ps->performance_levels[i].pcie_gen;
3920 if (data->pcie_lane_power_saving.max <
3921 ps->performance_levels[i].pcie_lane)
3922 data->pcie_lane_power_saving.max =
3923 ps->performance_levels[i].pcie_lane;
3925 if (data->pcie_lane_power_saving.min >
3926 ps->performance_levels[i].pcie_lane)
3927 data->pcie_lane_power_saving.min =
3928 ps->performance_levels[i].pcie_lane;
3939 polaris10_print_current_perforce_level(struct pp_hwmgr *hwmgr, struct seq_file *m)
3941 uint32_t sclk, mclk, activity_percent;
3943 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3945 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency);
3947 sclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
3949 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency);
3951 mclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
3952 seq_printf(m, "\n [ mclk ]: %u MHz\n\n [ sclk ]: %u MHz\n",
3953 mclk / 100, sclk / 100);
3955 offset = data->soft_regs_start + offsetof(SMU74_SoftRegisters, AverageGraphicsActivity);
3956 activity_percent = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset);
3957 activity_percent += 0x80;
3958 activity_percent >>= 8;
3960 seq_printf(m, "\n [GPU load]: %u%%\n\n", activity_percent > 100 ? 100 : activity_percent);
3962 seq_printf(m, "uvd %sabled\n", data->uvd_power_gated ? "dis" : "en");
3964 seq_printf(m, "vce %sabled\n", data->vce_power_gated ? "dis" : "en");
3967 static int polaris10_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input)
3969 const struct phm_set_power_state_input *states =
3970 (const struct phm_set_power_state_input *)input;
3971 const struct polaris10_power_state *polaris10_ps =
3972 cast_const_phw_polaris10_power_state(states->pnew_state);
3973 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3974 struct polaris10_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
3975 uint32_t sclk = polaris10_ps->performance_levels
3976 [polaris10_ps->performance_level_count - 1].engine_clock;
3977 struct polaris10_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
3978 uint32_t mclk = polaris10_ps->performance_levels
3979 [polaris10_ps->performance_level_count - 1].memory_clock;
3980 struct PP_Clocks min_clocks = {0};
3982 struct cgs_display_info info = {0};
3984 data->need_update_smu7_dpm_table = 0;
3986 for (i = 0; i < sclk_table->count; i++) {
3987 if (sclk == sclk_table->dpm_levels[i].value)
3991 if (i >= sclk_table->count)
3992 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
3994 /* TODO: Check SCLK in DAL's minimum clocks
3995 * in case DeepSleep divider update is required.
3997 if (data->display_timing.min_clock_in_sr != min_clocks.engineClockInSR &&
3998 (min_clocks.engineClockInSR >= POLARIS10_MINIMUM_ENGINE_CLOCK ||
3999 data->display_timing.min_clock_in_sr >= POLARIS10_MINIMUM_ENGINE_CLOCK))
4000 data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK;
4003 for (i = 0; i < mclk_table->count; i++) {
4004 if (mclk == mclk_table->dpm_levels[i].value)
4008 if (i >= mclk_table->count)
4009 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
4011 cgs_get_active_displays_info(hwmgr->device, &info);
4013 if (data->display_timing.num_existing_displays != info.display_count)
4014 data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK;
4019 static uint16_t polaris10_get_maximum_link_speed(struct pp_hwmgr *hwmgr,
4020 const struct polaris10_power_state *polaris10_ps)
4023 uint32_t sclk, max_sclk = 0;
4024 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4025 struct polaris10_dpm_table *dpm_table = &data->dpm_table;
4027 for (i = 0; i < polaris10_ps->performance_level_count; i++) {
4028 sclk = polaris10_ps->performance_levels[i].engine_clock;
4029 if (max_sclk < sclk)
4033 for (i = 0; i < dpm_table->sclk_table.count; i++) {
4034 if (dpm_table->sclk_table.dpm_levels[i].value == max_sclk)
4035 return (uint16_t) ((i >= dpm_table->pcie_speed_table.count) ?
4036 dpm_table->pcie_speed_table.dpm_levels
4037 [dpm_table->pcie_speed_table.count - 1].value :
4038 dpm_table->pcie_speed_table.dpm_levels[i].value);
4044 static int polaris10_request_link_speed_change_before_state_change(
4045 struct pp_hwmgr *hwmgr, const void *input)
4047 const struct phm_set_power_state_input *states =
4048 (const struct phm_set_power_state_input *)input;
4049 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4050 const struct polaris10_power_state *polaris10_nps =
4051 cast_const_phw_polaris10_power_state(states->pnew_state);
4052 const struct polaris10_power_state *polaris10_cps =
4053 cast_const_phw_polaris10_power_state(states->pcurrent_state);
4055 uint16_t target_link_speed = polaris10_get_maximum_link_speed(hwmgr, polaris10_nps);
4056 uint16_t current_link_speed;
4058 if (data->force_pcie_gen == PP_PCIEGenInvalid)
4059 current_link_speed = polaris10_get_maximum_link_speed(hwmgr, polaris10_cps);
4061 current_link_speed = data->force_pcie_gen;
4063 data->force_pcie_gen = PP_PCIEGenInvalid;
4064 data->pspp_notify_required = false;
4066 if (target_link_speed > current_link_speed) {
4067 switch (target_link_speed) {
4069 if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN3, false))
4071 data->force_pcie_gen = PP_PCIEGen2;
4072 if (current_link_speed == PP_PCIEGen2)
4075 if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN2, false))
4078 data->force_pcie_gen = phm_get_current_pcie_speed(hwmgr);
4082 if (target_link_speed < current_link_speed)
4083 data->pspp_notify_required = true;
4089 static int polaris10_freeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
4091 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4093 if (0 == data->need_update_smu7_dpm_table)
4096 if ((0 == data->sclk_dpm_key_disabled) &&
4097 (data->need_update_smu7_dpm_table &
4098 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
4099 PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr),
4100 "Trying to freeze SCLK DPM when DPM is disabled",
4102 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4103 PPSMC_MSG_SCLKDPM_FreezeLevel),
4104 "Failed to freeze SCLK DPM during FreezeSclkMclkDPM Function!",
4108 if ((0 == data->mclk_dpm_key_disabled) &&
4109 (data->need_update_smu7_dpm_table &
4110 DPMTABLE_OD_UPDATE_MCLK)) {
4111 PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr),
4112 "Trying to freeze MCLK DPM when DPM is disabled",
4114 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4115 PPSMC_MSG_MCLKDPM_FreezeLevel),
4116 "Failed to freeze MCLK DPM during FreezeSclkMclkDPM Function!",
4123 static int polaris10_populate_and_upload_sclk_mclk_dpm_levels(
4124 struct pp_hwmgr *hwmgr, const void *input)
4127 const struct phm_set_power_state_input *states =
4128 (const struct phm_set_power_state_input *)input;
4129 const struct polaris10_power_state *polaris10_ps =
4130 cast_const_phw_polaris10_power_state(states->pnew_state);
4131 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4132 uint32_t sclk = polaris10_ps->performance_levels
4133 [polaris10_ps->performance_level_count - 1].engine_clock;
4134 uint32_t mclk = polaris10_ps->performance_levels
4135 [polaris10_ps->performance_level_count - 1].memory_clock;
4136 struct polaris10_dpm_table *dpm_table = &data->dpm_table;
4138 struct polaris10_dpm_table *golden_dpm_table = &data->golden_dpm_table;
4139 uint32_t dpm_count, clock_percent;
4142 if (0 == data->need_update_smu7_dpm_table)
4145 if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) {
4146 dpm_table->sclk_table.dpm_levels
4147 [dpm_table->sclk_table.count - 1].value = sclk;
4149 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) ||
4150 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) {
4151 /* Need to do calculation based on the golden DPM table
4152 * as the Heatmap GPU Clock axis is also based on the default values
4154 PP_ASSERT_WITH_CODE(
4155 (golden_dpm_table->sclk_table.dpm_levels
4156 [golden_dpm_table->sclk_table.count - 1].value != 0),
4159 dpm_count = dpm_table->sclk_table.count < 2 ? 0 : dpm_table->sclk_table.count - 2;
4161 for (i = dpm_count; i > 1; i--) {
4162 if (sclk > golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value) {
4165 - golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value
4167 / golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value;
4169 dpm_table->sclk_table.dpm_levels[i].value =
4170 golden_dpm_table->sclk_table.dpm_levels[i].value +
4171 (golden_dpm_table->sclk_table.dpm_levels[i].value *
4174 } else if (golden_dpm_table->sclk_table.dpm_levels[dpm_table->sclk_table.count-1].value > sclk) {
4176 ((golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count - 1].value
4178 / golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value;
4180 dpm_table->sclk_table.dpm_levels[i].value =
4181 golden_dpm_table->sclk_table.dpm_levels[i].value -
4182 (golden_dpm_table->sclk_table.dpm_levels[i].value *
4183 clock_percent) / 100;
4185 dpm_table->sclk_table.dpm_levels[i].value =
4186 golden_dpm_table->sclk_table.dpm_levels[i].value;
4191 if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) {
4192 dpm_table->mclk_table.dpm_levels
4193 [dpm_table->mclk_table.count - 1].value = mclk;
4195 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) ||
4196 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) {
4198 PP_ASSERT_WITH_CODE(
4199 (golden_dpm_table->mclk_table.dpm_levels
4200 [golden_dpm_table->mclk_table.count-1].value != 0),
4203 dpm_count = dpm_table->mclk_table.count < 2 ? 0 : dpm_table->mclk_table.count - 2;
4204 for (i = dpm_count; i > 1; i--) {
4205 if (golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value < mclk) {
4206 clock_percent = ((mclk -
4207 golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value) * 100)
4208 / golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value;
4210 dpm_table->mclk_table.dpm_levels[i].value =
4211 golden_dpm_table->mclk_table.dpm_levels[i].value +
4212 (golden_dpm_table->mclk_table.dpm_levels[i].value *
4213 clock_percent) / 100;
4215 } else if (golden_dpm_table->mclk_table.dpm_levels[dpm_table->mclk_table.count-1].value > mclk) {
4217 (golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value - mclk)
4219 / golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value;
4221 dpm_table->mclk_table.dpm_levels[i].value =
4222 golden_dpm_table->mclk_table.dpm_levels[i].value -
4223 (golden_dpm_table->mclk_table.dpm_levels[i].value *
4224 clock_percent) / 100;
4226 dpm_table->mclk_table.dpm_levels[i].value =
4227 golden_dpm_table->mclk_table.dpm_levels[i].value;
4232 if (data->need_update_smu7_dpm_table &
4233 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK)) {
4234 result = polaris10_populate_all_graphic_levels(hwmgr);
4235 PP_ASSERT_WITH_CODE((0 == result),
4236 "Failed to populate SCLK during PopulateNewDPMClocksStates Function!",
4240 if (data->need_update_smu7_dpm_table &
4241 (DPMTABLE_OD_UPDATE_MCLK + DPMTABLE_UPDATE_MCLK)) {
4242 /*populate MCLK dpm table to SMU7 */
4243 result = polaris10_populate_all_memory_levels(hwmgr);
4244 PP_ASSERT_WITH_CODE((0 == result),
4245 "Failed to populate MCLK during PopulateNewDPMClocksStates Function!",
4252 static int polaris10_trim_single_dpm_states(struct pp_hwmgr *hwmgr,
4253 struct polaris10_single_dpm_table *dpm_table,
4254 uint32_t low_limit, uint32_t high_limit)
4258 for (i = 0; i < dpm_table->count; i++) {
4259 if ((dpm_table->dpm_levels[i].value < low_limit)
4260 || (dpm_table->dpm_levels[i].value > high_limit))
4261 dpm_table->dpm_levels[i].enabled = false;
4263 dpm_table->dpm_levels[i].enabled = true;
4269 static int polaris10_trim_dpm_states(struct pp_hwmgr *hwmgr,
4270 const struct polaris10_power_state *polaris10_ps)
4273 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4274 uint32_t high_limit_count;
4276 PP_ASSERT_WITH_CODE((polaris10_ps->performance_level_count >= 1),
4277 "power state did not have any performance level",
4280 high_limit_count = (1 == polaris10_ps->performance_level_count) ? 0 : 1;
4282 polaris10_trim_single_dpm_states(hwmgr,
4283 &(data->dpm_table.sclk_table),
4284 polaris10_ps->performance_levels[0].engine_clock,
4285 polaris10_ps->performance_levels[high_limit_count].engine_clock);
4287 polaris10_trim_single_dpm_states(hwmgr,
4288 &(data->dpm_table.mclk_table),
4289 polaris10_ps->performance_levels[0].memory_clock,
4290 polaris10_ps->performance_levels[high_limit_count].memory_clock);
4295 static int polaris10_generate_dpm_level_enable_mask(
4296 struct pp_hwmgr *hwmgr, const void *input)
4299 const struct phm_set_power_state_input *states =
4300 (const struct phm_set_power_state_input *)input;
4301 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4302 const struct polaris10_power_state *polaris10_ps =
4303 cast_const_phw_polaris10_power_state(states->pnew_state);
4305 result = polaris10_trim_dpm_states(hwmgr, polaris10_ps);
4309 data->dpm_level_enable_mask.sclk_dpm_enable_mask =
4310 phm_get_dpm_level_enable_mask_value(&data->dpm_table.sclk_table);
4311 data->dpm_level_enable_mask.mclk_dpm_enable_mask =
4312 phm_get_dpm_level_enable_mask_value(&data->dpm_table.mclk_table);
4313 data->dpm_level_enable_mask.pcie_dpm_enable_mask =
4314 phm_get_dpm_level_enable_mask_value(&data->dpm_table.pcie_speed_table);
4319 int polaris10_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
4321 return smum_send_msg_to_smc(hwmgr->smumgr, enable ?
4322 PPSMC_MSG_UVDDPM_Enable :
4323 PPSMC_MSG_UVDDPM_Disable);
4326 int polaris10_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
4328 return smum_send_msg_to_smc(hwmgr->smumgr, enable?
4329 PPSMC_MSG_VCEDPM_Enable :
4330 PPSMC_MSG_VCEDPM_Disable);
4333 int polaris10_enable_disable_samu_dpm(struct pp_hwmgr *hwmgr, bool enable)
4335 return smum_send_msg_to_smc(hwmgr->smumgr, enable?
4336 PPSMC_MSG_SAMUDPM_Enable :
4337 PPSMC_MSG_SAMUDPM_Disable);
4340 int polaris10_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate)
4342 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4343 uint32_t mm_boot_level_offset, mm_boot_level_value;
4344 struct phm_ppt_v1_information *table_info =
4345 (struct phm_ppt_v1_information *)(hwmgr->pptable);
4348 data->smc_state_table.UvdBootLevel = 0;
4349 if (table_info->mm_dep_table->count > 0)
4350 data->smc_state_table.UvdBootLevel =
4351 (uint8_t) (table_info->mm_dep_table->count - 1);
4352 mm_boot_level_offset = data->dpm_table_start +
4353 offsetof(SMU74_Discrete_DpmTable, UvdBootLevel);
4354 mm_boot_level_offset /= 4;
4355 mm_boot_level_offset *= 4;
4356 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
4357 CGS_IND_REG__SMC, mm_boot_level_offset);
4358 mm_boot_level_value &= 0x00FFFFFF;
4359 mm_boot_level_value |= data->smc_state_table.UvdBootLevel << 24;
4360 cgs_write_ind_register(hwmgr->device,
4361 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
4363 if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4364 PHM_PlatformCaps_UVDDPM) ||
4365 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4366 PHM_PlatformCaps_StablePState))
4367 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4368 PPSMC_MSG_UVDDPM_SetEnabledMask,
4369 (uint32_t)(1 << data->smc_state_table.UvdBootLevel));
4372 return polaris10_enable_disable_uvd_dpm(hwmgr, !bgate);
4375 static int polaris10_update_vce_dpm(struct pp_hwmgr *hwmgr, const void *input)
4377 const struct phm_set_power_state_input *states =
4378 (const struct phm_set_power_state_input *)input;
4379 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4380 const struct polaris10_power_state *polaris10_nps =
4381 cast_const_phw_polaris10_power_state(states->pnew_state);
4382 const struct polaris10_power_state *polaris10_cps =
4383 cast_const_phw_polaris10_power_state(states->pcurrent_state);
4385 uint32_t mm_boot_level_offset, mm_boot_level_value;
4386 struct phm_ppt_v1_information *table_info =
4387 (struct phm_ppt_v1_information *)(hwmgr->pptable);
4389 if (polaris10_nps->vce_clks.evclk > 0 &&
4390 (polaris10_cps == NULL || polaris10_cps->vce_clks.evclk == 0)) {
4392 data->smc_state_table.VceBootLevel =
4393 (uint8_t) (table_info->mm_dep_table->count - 1);
4395 mm_boot_level_offset = data->dpm_table_start +
4396 offsetof(SMU74_Discrete_DpmTable, VceBootLevel);
4397 mm_boot_level_offset /= 4;
4398 mm_boot_level_offset *= 4;
4399 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
4400 CGS_IND_REG__SMC, mm_boot_level_offset);
4401 mm_boot_level_value &= 0xFF00FFFF;
4402 mm_boot_level_value |= data->smc_state_table.VceBootLevel << 16;
4403 cgs_write_ind_register(hwmgr->device,
4404 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
4406 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState)) {
4407 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4408 PPSMC_MSG_VCEDPM_SetEnabledMask,
4409 (uint32_t)1 << data->smc_state_table.VceBootLevel);
4411 polaris10_enable_disable_vce_dpm(hwmgr, true);
4412 } else if (polaris10_nps->vce_clks.evclk == 0 &&
4413 polaris10_cps != NULL &&
4414 polaris10_cps->vce_clks.evclk > 0)
4415 polaris10_enable_disable_vce_dpm(hwmgr, false);
4421 int polaris10_update_samu_dpm(struct pp_hwmgr *hwmgr, bool bgate)
4423 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4424 uint32_t mm_boot_level_offset, mm_boot_level_value;
4427 data->smc_state_table.SamuBootLevel = 0;
4428 mm_boot_level_offset = data->dpm_table_start +
4429 offsetof(SMU74_Discrete_DpmTable, SamuBootLevel);
4430 mm_boot_level_offset /= 4;
4431 mm_boot_level_offset *= 4;
4432 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
4433 CGS_IND_REG__SMC, mm_boot_level_offset);
4434 mm_boot_level_value &= 0xFFFFFF00;
4435 mm_boot_level_value |= data->smc_state_table.SamuBootLevel << 0;
4436 cgs_write_ind_register(hwmgr->device,
4437 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
4439 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4440 PHM_PlatformCaps_StablePState))
4441 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4442 PPSMC_MSG_SAMUDPM_SetEnabledMask,
4443 (uint32_t)(1 << data->smc_state_table.SamuBootLevel));
4446 return polaris10_enable_disable_samu_dpm(hwmgr, !bgate);
4449 static int polaris10_update_sclk_threshold(struct pp_hwmgr *hwmgr)
4451 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4454 uint32_t low_sclk_interrupt_threshold = 0;
4456 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4457 PHM_PlatformCaps_SclkThrottleLowNotification)
4458 && (hwmgr->gfx_arbiter.sclk_threshold !=
4459 data->low_sclk_interrupt_threshold)) {
4460 data->low_sclk_interrupt_threshold =
4461 hwmgr->gfx_arbiter.sclk_threshold;
4462 low_sclk_interrupt_threshold =
4463 data->low_sclk_interrupt_threshold;
4465 CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
4467 result = polaris10_copy_bytes_to_smc(
4469 data->dpm_table_start +
4470 offsetof(SMU74_Discrete_DpmTable,
4471 LowSclkInterruptThreshold),
4472 (uint8_t *)&low_sclk_interrupt_threshold,
4480 static int polaris10_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
4482 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4484 if (data->need_update_smu7_dpm_table &
4485 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK))
4486 return polaris10_program_memory_timing_parameters(hwmgr);
4491 static int polaris10_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
4493 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4495 if (0 == data->need_update_smu7_dpm_table)
4498 if ((0 == data->sclk_dpm_key_disabled) &&
4499 (data->need_update_smu7_dpm_table &
4500 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
4502 PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr),
4503 "Trying to Unfreeze SCLK DPM when DPM is disabled",
4505 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4506 PPSMC_MSG_SCLKDPM_UnfreezeLevel),
4507 "Failed to unfreeze SCLK DPM during UnFreezeSclkMclkDPM Function!",
4511 if ((0 == data->mclk_dpm_key_disabled) &&
4512 (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
4514 PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr),
4515 "Trying to Unfreeze MCLK DPM when DPM is disabled",
4517 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4518 PPSMC_MSG_SCLKDPM_UnfreezeLevel),
4519 "Failed to unfreeze MCLK DPM during UnFreezeSclkMclkDPM Function!",
4523 data->need_update_smu7_dpm_table = 0;
4528 static int polaris10_notify_link_speed_change_after_state_change(
4529 struct pp_hwmgr *hwmgr, const void *input)
4531 const struct phm_set_power_state_input *states =
4532 (const struct phm_set_power_state_input *)input;
4533 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4534 const struct polaris10_power_state *polaris10_ps =
4535 cast_const_phw_polaris10_power_state(states->pnew_state);
4536 uint16_t target_link_speed = polaris10_get_maximum_link_speed(hwmgr, polaris10_ps);
4539 if (data->pspp_notify_required) {
4540 if (target_link_speed == PP_PCIEGen3)
4541 request = PCIE_PERF_REQ_GEN3;
4542 else if (target_link_speed == PP_PCIEGen2)
4543 request = PCIE_PERF_REQ_GEN2;
4545 request = PCIE_PERF_REQ_GEN1;
4547 if (request == PCIE_PERF_REQ_GEN1 &&
4548 phm_get_current_pcie_speed(hwmgr) > 0)
4551 if (acpi_pcie_perf_request(hwmgr->device, request, false)) {
4552 if (PP_PCIEGen2 == target_link_speed)
4553 printk("PSPP request to switch to Gen2 from Gen3 Failed!");
4555 printk("PSPP request to switch to Gen1 from Gen2 Failed!");
4562 static int polaris10_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input)
4564 int tmp_result, result = 0;
4565 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4567 tmp_result = polaris10_find_dpm_states_clocks_in_dpm_table(hwmgr, input);
4568 PP_ASSERT_WITH_CODE((0 == tmp_result),
4569 "Failed to find DPM states clocks in DPM table!",
4570 result = tmp_result);
4572 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4573 PHM_PlatformCaps_PCIEPerformanceRequest)) {
4575 polaris10_request_link_speed_change_before_state_change(hwmgr, input);
4576 PP_ASSERT_WITH_CODE((0 == tmp_result),
4577 "Failed to request link speed change before state change!",
4578 result = tmp_result);
4581 tmp_result = polaris10_freeze_sclk_mclk_dpm(hwmgr);
4582 PP_ASSERT_WITH_CODE((0 == tmp_result),
4583 "Failed to freeze SCLK MCLK DPM!", result = tmp_result);
4585 tmp_result = polaris10_populate_and_upload_sclk_mclk_dpm_levels(hwmgr, input);
4586 PP_ASSERT_WITH_CODE((0 == tmp_result),
4587 "Failed to populate and upload SCLK MCLK DPM levels!",
4588 result = tmp_result);
4590 tmp_result = polaris10_generate_dpm_level_enable_mask(hwmgr, input);
4591 PP_ASSERT_WITH_CODE((0 == tmp_result),
4592 "Failed to generate DPM level enabled mask!",
4593 result = tmp_result);
4595 tmp_result = polaris10_update_vce_dpm(hwmgr, input);
4596 PP_ASSERT_WITH_CODE((0 == tmp_result),
4597 "Failed to update VCE DPM!",
4598 result = tmp_result);
4600 tmp_result = polaris10_update_sclk_threshold(hwmgr);
4601 PP_ASSERT_WITH_CODE((0 == tmp_result),
4602 "Failed to update SCLK threshold!",
4603 result = tmp_result);
4605 tmp_result = polaris10_program_mem_timing_parameters(hwmgr);
4606 PP_ASSERT_WITH_CODE((0 == tmp_result),
4607 "Failed to program memory timing parameters!",
4608 result = tmp_result);
4610 tmp_result = polaris10_unfreeze_sclk_mclk_dpm(hwmgr);
4611 PP_ASSERT_WITH_CODE((0 == tmp_result),
4612 "Failed to unfreeze SCLK MCLK DPM!",
4613 result = tmp_result);
4615 tmp_result = polaris10_upload_dpm_level_enable_mask(hwmgr);
4616 PP_ASSERT_WITH_CODE((0 == tmp_result),
4617 "Failed to upload DPM level enabled mask!",
4618 result = tmp_result);
4620 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4621 PHM_PlatformCaps_PCIEPerformanceRequest)) {
4623 polaris10_notify_link_speed_change_after_state_change(hwmgr, input);
4624 PP_ASSERT_WITH_CODE((0 == tmp_result),
4625 "Failed to notify link speed change after state change!",
4626 result = tmp_result);
4628 data->apply_optimized_settings = false;
4632 static int polaris10_set_max_fan_pwm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm)
4634 hwmgr->thermal_controller.
4635 advanceFanControlParameters.usMaxFanPWM = us_max_fan_pwm;
4637 if (phm_is_hw_access_blocked(hwmgr))
4640 return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4641 PPSMC_MSG_SetFanPwmMax, us_max_fan_pwm);
4644 int polaris10_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display)
4646 PPSMC_Msg msg = has_display ? (PPSMC_Msg)PPSMC_HasDisplay : (PPSMC_Msg)PPSMC_NoDisplay;
4648 return (smum_send_msg_to_smc(hwmgr->smumgr, msg) == 0) ? 0 : -1;
4651 int polaris10_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
4653 uint32_t num_active_displays = 0;
4654 struct cgs_display_info info = {0};
4655 info.mode_info = NULL;
4657 cgs_get_active_displays_info(hwmgr->device, &info);
4659 num_active_displays = info.display_count;
4661 if (num_active_displays > 1) /* to do && (pHwMgr->pPECI->displayConfiguration.bMultiMonitorInSync != TRUE)) */
4662 polaris10_notify_smc_display_change(hwmgr, false);
4664 polaris10_notify_smc_display_change(hwmgr, true);
4670 * Programs the display gap
4672 * @param hwmgr the address of the powerplay hardware manager.
4675 int polaris10_program_display_gap(struct pp_hwmgr *hwmgr)
4677 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4678 uint32_t num_active_displays = 0;
4679 uint32_t display_gap = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL);
4680 uint32_t display_gap2;
4681 uint32_t pre_vbi_time_in_us;
4682 uint32_t frame_time_in_us;
4684 uint32_t refresh_rate = 0;
4685 struct cgs_display_info info = {0};
4686 struct cgs_mode_info mode_info;
4688 info.mode_info = &mode_info;
4690 cgs_get_active_displays_info(hwmgr->device, &info);
4691 num_active_displays = info.display_count;
4693 display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL, DISP_GAP, (num_active_displays > 0) ? DISPLAY_GAP_VBLANK_OR_WM : DISPLAY_GAP_IGNORE);
4694 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL, display_gap);
4696 ref_clock = mode_info.ref_clock;
4697 refresh_rate = mode_info.refresh_rate;
4699 if (0 == refresh_rate)
4702 frame_time_in_us = 1000000 / refresh_rate;
4704 pre_vbi_time_in_us = frame_time_in_us - 200 - mode_info.vblank_time_us;
4705 display_gap2 = pre_vbi_time_in_us * (ref_clock / 100);
4707 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL2, display_gap2);
4709 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start + offsetof(SMU74_SoftRegisters, PreVBlankGap), 0x64);
4711 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start + offsetof(SMU74_SoftRegisters, VBlankTimeout), (frame_time_in_us - pre_vbi_time_in_us));
4713 polaris10_notify_smc_display_change(hwmgr, num_active_displays != 0);
4719 int polaris10_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
4721 return polaris10_program_display_gap(hwmgr);
4725 * Set maximum target operating fan output RPM
4727 * @param hwmgr: the address of the powerplay hardware manager.
4728 * @param usMaxFanRpm: max operating fan RPM value.
4729 * @return The response that came from the SMC.
4731 static int polaris10_set_max_fan_rpm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_rpm)
4733 hwmgr->thermal_controller.
4734 advanceFanControlParameters.usMaxFanRPM = us_max_fan_rpm;
4736 if (phm_is_hw_access_blocked(hwmgr))
4739 return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4740 PPSMC_MSG_SetFanRpmMax, us_max_fan_rpm);
4743 int polaris10_register_internal_thermal_interrupt(struct pp_hwmgr *hwmgr,
4744 const void *thermal_interrupt_info)
4749 bool polaris10_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
4751 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4752 bool is_update_required = false;
4753 struct cgs_display_info info = {0, 0, NULL};
4755 cgs_get_active_displays_info(hwmgr->device, &info);
4757 if (data->display_timing.num_existing_displays != info.display_count)
4758 is_update_required = true;
4759 /* TO DO NEED TO GET DEEP SLEEP CLOCK FROM DAL
4760 if (phm_cap_enabled(hwmgr->hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
4761 cgs_get_min_clock_settings(hwmgr->device, &min_clocks);
4762 if (min_clocks.engineClockInSR != data->display_timing.minClockInSR &&
4763 (min_clocks.engineClockInSR >= POLARIS10_MINIMUM_ENGINE_CLOCK ||
4764 data->display_timing.minClockInSR >= POLARIS10_MINIMUM_ENGINE_CLOCK))
4765 is_update_required = true;
4767 return is_update_required;
4770 static inline bool polaris10_are_power_levels_equal(const struct polaris10_performance_level *pl1,
4771 const struct polaris10_performance_level *pl2)
4773 return ((pl1->memory_clock == pl2->memory_clock) &&
4774 (pl1->engine_clock == pl2->engine_clock) &&
4775 (pl1->pcie_gen == pl2->pcie_gen) &&
4776 (pl1->pcie_lane == pl2->pcie_lane));
4779 int polaris10_check_states_equal(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *pstate1, const struct pp_hw_power_state *pstate2, bool *equal)
4781 const struct polaris10_power_state *psa = cast_const_phw_polaris10_power_state(pstate1);
4782 const struct polaris10_power_state *psb = cast_const_phw_polaris10_power_state(pstate2);
4785 if (pstate1 == NULL || pstate2 == NULL || equal == NULL)
4788 /* If the two states don't even have the same number of performance levels they cannot be the same state. */
4789 if (psa->performance_level_count != psb->performance_level_count) {
4794 for (i = 0; i < psa->performance_level_count; i++) {
4795 if (!polaris10_are_power_levels_equal(&(psa->performance_levels[i]), &(psb->performance_levels[i]))) {
4796 /* If we have found even one performance level pair that is different the states are different. */
4802 /* If all performance levels are the same try to use the UVD clocks to break the tie.*/
4803 *equal = ((psa->uvd_clks.vclk == psb->uvd_clks.vclk) && (psa->uvd_clks.dclk == psb->uvd_clks.dclk));
4804 *equal &= ((psa->vce_clks.evclk == psb->vce_clks.evclk) && (psa->vce_clks.ecclk == psb->vce_clks.ecclk));
4805 *equal &= (psa->sclk_threshold == psb->sclk_threshold);
4810 int polaris10_upload_mc_firmware(struct pp_hwmgr *hwmgr)
4812 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4814 uint32_t vbios_version;
4816 /* Read MC indirect register offset 0x9F bits [3:0] to see if VBIOS has already loaded a full version of MC ucode or not.*/
4818 phm_get_mc_microcode_version(hwmgr);
4819 vbios_version = hwmgr->microcode_version_info.MC & 0xf;
4820 /* Full version of MC ucode has already been loaded. */
4821 if (vbios_version == 0) {
4822 data->need_long_memory_training = false;
4826 data->need_long_memory_training = true;
4829 * PPMCME_FirmwareDescriptorEntry *pfd = NULL;
4830 pfd = &tonga_mcmeFirmware;
4831 if (0 == PHM_READ_FIELD(hwmgr->device, MC_SEQ_SUP_CNTL, RUN))
4832 polaris10_load_mc_microcode(hwmgr, pfd->dpmThreshold,
4833 pfd->cfgArray, pfd->cfgSize, pfd->ioDebugArray,
4834 pfd->ioDebugSize, pfd->ucodeArray, pfd->ucodeSize);
4840 * Read clock related registers.
4842 * @param hwmgr the address of the powerplay hardware manager.
4845 static int polaris10_read_clock_registers(struct pp_hwmgr *hwmgr)
4847 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4849 data->clock_registers.vCG_SPLL_FUNC_CNTL = cgs_read_ind_register(hwmgr->device,
4850 CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL)
4851 & CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK;
4853 data->clock_registers.vCG_SPLL_FUNC_CNTL_2 = cgs_read_ind_register(hwmgr->device,
4854 CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_2)
4855 & CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL_MASK;
4857 data->clock_registers.vCG_SPLL_FUNC_CNTL_4 = cgs_read_ind_register(hwmgr->device,
4858 CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_4)
4859 & CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_MASK;
4865 * Find out if memory is GDDR5.
4867 * @param hwmgr the address of the powerplay hardware manager.
4870 static int polaris10_get_memory_type(struct pp_hwmgr *hwmgr)
4872 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4875 temp = cgs_read_register(hwmgr->device, mmMC_SEQ_MISC0);
4877 data->is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE ==
4878 ((temp & MC_SEQ_MISC0_GDDR5_MASK) >>
4879 MC_SEQ_MISC0_GDDR5_SHIFT));
4885 * Enables Dynamic Power Management by SMC
4887 * @param hwmgr the address of the powerplay hardware manager.
4890 static int polaris10_enable_acpi_power_management(struct pp_hwmgr *hwmgr)
4892 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
4893 GENERAL_PWRMGT, STATIC_PM_EN, 1);
4899 * Initialize PowerGating States for different engines
4901 * @param hwmgr the address of the powerplay hardware manager.
4904 static int polaris10_init_power_gate_state(struct pp_hwmgr *hwmgr)
4906 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4908 data->uvd_power_gated = false;
4909 data->vce_power_gated = false;
4910 data->samu_power_gated = false;
4915 static int polaris10_init_sclk_threshold(struct pp_hwmgr *hwmgr)
4917 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4918 data->low_sclk_interrupt_threshold = 0;
4923 int polaris10_setup_asic_task(struct pp_hwmgr *hwmgr)
4925 int tmp_result, result = 0;
4927 polaris10_upload_mc_firmware(hwmgr);
4929 tmp_result = polaris10_read_clock_registers(hwmgr);
4930 PP_ASSERT_WITH_CODE((0 == tmp_result),
4931 "Failed to read clock registers!", result = tmp_result);
4933 tmp_result = polaris10_get_memory_type(hwmgr);
4934 PP_ASSERT_WITH_CODE((0 == tmp_result),
4935 "Failed to get memory type!", result = tmp_result);
4937 tmp_result = polaris10_enable_acpi_power_management(hwmgr);
4938 PP_ASSERT_WITH_CODE((0 == tmp_result),
4939 "Failed to enable ACPI power management!", result = tmp_result);
4941 tmp_result = polaris10_init_power_gate_state(hwmgr);
4942 PP_ASSERT_WITH_CODE((0 == tmp_result),
4943 "Failed to init power gate state!", result = tmp_result);
4945 tmp_result = phm_get_mc_microcode_version(hwmgr);
4946 PP_ASSERT_WITH_CODE((0 == tmp_result),
4947 "Failed to get MC microcode version!", result = tmp_result);
4949 tmp_result = polaris10_init_sclk_threshold(hwmgr);
4950 PP_ASSERT_WITH_CODE((0 == tmp_result),
4951 "Failed to init sclk threshold!", result = tmp_result);
4956 static int polaris10_get_pp_table(struct pp_hwmgr *hwmgr, char **table)
4958 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4960 if (!data->soft_pp_table) {
4961 data->soft_pp_table = kmemdup(hwmgr->soft_pp_table,
4962 hwmgr->soft_pp_table_size,
4964 if (!data->soft_pp_table)
4968 *table = (char *)&data->soft_pp_table;
4970 return hwmgr->soft_pp_table_size;
4973 static int polaris10_set_pp_table(struct pp_hwmgr *hwmgr, const char *buf, size_t size)
4975 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4977 if (!data->soft_pp_table) {
4978 data->soft_pp_table = kzalloc(hwmgr->soft_pp_table_size, GFP_KERNEL);
4979 if (!data->soft_pp_table)
4983 memcpy(data->soft_pp_table, buf, size);
4985 hwmgr->soft_pp_table = data->soft_pp_table;
4987 /* TODO: re-init powerplay to implement modified pptable */
4992 static int polaris10_force_clock_level(struct pp_hwmgr *hwmgr,
4993 enum pp_clock_type type, uint32_t mask)
4995 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4997 if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
5002 if (!data->sclk_dpm_key_disabled)
5003 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
5004 PPSMC_MSG_SCLKDPM_SetEnabledMask,
5005 data->dpm_level_enable_mask.sclk_dpm_enable_mask & mask);
5008 if (!data->mclk_dpm_key_disabled)
5009 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
5010 PPSMC_MSG_MCLKDPM_SetEnabledMask,
5011 data->dpm_level_enable_mask.mclk_dpm_enable_mask & mask);
5015 uint32_t tmp = mask & data->dpm_level_enable_mask.pcie_dpm_enable_mask;
5021 if (!data->pcie_dpm_key_disabled)
5022 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
5023 PPSMC_MSG_PCIeDPM_ForceLevel,
5034 static uint16_t polaris10_get_current_pcie_speed(struct pp_hwmgr *hwmgr)
5036 uint32_t speedCntl = 0;
5038 /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
5039 speedCntl = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__PCIE,
5040 ixPCIE_LC_SPEED_CNTL);
5041 return((uint16_t)PHM_GET_FIELD(speedCntl,
5042 PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE));
5045 static int polaris10_print_clock_levels(struct pp_hwmgr *hwmgr,
5046 enum pp_clock_type type, char *buf)
5048 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
5049 struct polaris10_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
5050 struct polaris10_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
5051 struct polaris10_single_dpm_table *pcie_table = &(data->dpm_table.pcie_speed_table);
5052 int i, now, size = 0;
5053 uint32_t clock, pcie_speed;
5057 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency);
5058 clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
5060 for (i = 0; i < sclk_table->count; i++) {
5061 if (clock > sclk_table->dpm_levels[i].value)
5067 for (i = 0; i < sclk_table->count; i++)
5068 size += sprintf(buf + size, "%d: %uMhz %s\n",
5069 i, sclk_table->dpm_levels[i].value / 100,
5070 (i == now) ? "*" : "");
5073 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency);
5074 clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
5076 for (i = 0; i < mclk_table->count; i++) {
5077 if (clock > mclk_table->dpm_levels[i].value)
5083 for (i = 0; i < mclk_table->count; i++)
5084 size += sprintf(buf + size, "%d: %uMhz %s\n",
5085 i, mclk_table->dpm_levels[i].value / 100,
5086 (i == now) ? "*" : "");
5089 pcie_speed = polaris10_get_current_pcie_speed(hwmgr);
5090 for (i = 0; i < pcie_table->count; i++) {
5091 if (pcie_speed != pcie_table->dpm_levels[i].value)
5097 for (i = 0; i < pcie_table->count; i++)
5098 size += sprintf(buf + size, "%d: %s %s\n", i,
5099 (pcie_table->dpm_levels[i].value == 0) ? "2.5GB, x8" :
5100 (pcie_table->dpm_levels[i].value == 1) ? "5.0GB, x16" :
5101 (pcie_table->dpm_levels[i].value == 2) ? "8.0GB, x16" : "",
5102 (i == now) ? "*" : "");
5110 static int polaris10_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
5113 /* stop auto-manage */
5114 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
5115 PHM_PlatformCaps_MicrocodeFanControl))
5116 polaris10_fan_ctrl_stop_smc_fan_control(hwmgr);
5117 polaris10_fan_ctrl_set_static_mode(hwmgr, mode);
5119 /* restart auto-manage */
5120 polaris10_fan_ctrl_reset_fan_speed_to_default(hwmgr);
5125 static int polaris10_get_fan_control_mode(struct pp_hwmgr *hwmgr)
5127 if (hwmgr->fan_ctrl_is_in_default_mode)
5128 return hwmgr->fan_ctrl_default_mode;
5130 return PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
5131 CG_FDO_CTRL2, FDO_PWM_MODE);
5134 static int polaris10_get_sclk_od(struct pp_hwmgr *hwmgr)
5136 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
5137 struct polaris10_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
5138 struct polaris10_single_dpm_table *golden_sclk_table =
5139 &(data->golden_dpm_table.sclk_table);
5142 value = (sclk_table->dpm_levels[sclk_table->count - 1].value -
5143 golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value) *
5145 golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value;
5150 static int polaris10_set_sclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
5152 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
5153 struct polaris10_single_dpm_table *golden_sclk_table =
5154 &(data->golden_dpm_table.sclk_table);
5155 struct pp_power_state *ps;
5156 struct polaris10_power_state *polaris10_ps;
5161 ps = hwmgr->request_ps;
5166 polaris10_ps = cast_phw_polaris10_power_state(&ps->hardware);
5168 polaris10_ps->performance_levels[polaris10_ps->performance_level_count - 1].engine_clock =
5169 golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value *
5171 golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value;
5176 static int polaris10_get_mclk_od(struct pp_hwmgr *hwmgr)
5178 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
5179 struct polaris10_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
5180 struct polaris10_single_dpm_table *golden_mclk_table =
5181 &(data->golden_dpm_table.mclk_table);
5184 value = (mclk_table->dpm_levels[mclk_table->count - 1].value -
5185 golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value) *
5187 golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value;
5192 static int polaris10_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
5194 struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
5195 struct polaris10_single_dpm_table *golden_mclk_table =
5196 &(data->golden_dpm_table.mclk_table);
5197 struct pp_power_state *ps;
5198 struct polaris10_power_state *polaris10_ps;
5203 ps = hwmgr->request_ps;
5208 polaris10_ps = cast_phw_polaris10_power_state(&ps->hardware);
5210 polaris10_ps->performance_levels[polaris10_ps->performance_level_count - 1].memory_clock =
5211 golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value *
5213 golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value;
5217 static const struct pp_hwmgr_func polaris10_hwmgr_funcs = {
5218 .backend_init = &polaris10_hwmgr_backend_init,
5219 .backend_fini = &polaris10_hwmgr_backend_fini,
5220 .asic_setup = &polaris10_setup_asic_task,
5221 .dynamic_state_management_enable = &polaris10_enable_dpm_tasks,
5222 .apply_state_adjust_rules = polaris10_apply_state_adjust_rules,
5223 .force_dpm_level = &polaris10_force_dpm_level,
5224 .power_state_set = polaris10_set_power_state_tasks,
5225 .get_power_state_size = polaris10_get_power_state_size,
5226 .get_mclk = polaris10_dpm_get_mclk,
5227 .get_sclk = polaris10_dpm_get_sclk,
5228 .patch_boot_state = polaris10_dpm_patch_boot_state,
5229 .get_pp_table_entry = polaris10_get_pp_table_entry,
5230 .get_num_of_pp_table_entries = tonga_get_number_of_powerplay_table_entries,
5231 .print_current_perforce_level = polaris10_print_current_perforce_level,
5232 .powerdown_uvd = polaris10_phm_powerdown_uvd,
5233 .powergate_uvd = polaris10_phm_powergate_uvd,
5234 .powergate_vce = polaris10_phm_powergate_vce,
5235 .disable_clock_power_gating = polaris10_phm_disable_clock_power_gating,
5236 .update_clock_gatings = polaris10_phm_update_clock_gatings,
5237 .notify_smc_display_config_after_ps_adjustment = polaris10_notify_smc_display_config_after_ps_adjustment,
5238 .display_config_changed = polaris10_display_configuration_changed_task,
5239 .set_max_fan_pwm_output = polaris10_set_max_fan_pwm_output,
5240 .set_max_fan_rpm_output = polaris10_set_max_fan_rpm_output,
5241 .get_temperature = polaris10_thermal_get_temperature,
5242 .stop_thermal_controller = polaris10_thermal_stop_thermal_controller,
5243 .get_fan_speed_info = polaris10_fan_ctrl_get_fan_speed_info,
5244 .get_fan_speed_percent = polaris10_fan_ctrl_get_fan_speed_percent,
5245 .set_fan_speed_percent = polaris10_fan_ctrl_set_fan_speed_percent,
5246 .reset_fan_speed_to_default = polaris10_fan_ctrl_reset_fan_speed_to_default,
5247 .get_fan_speed_rpm = polaris10_fan_ctrl_get_fan_speed_rpm,
5248 .set_fan_speed_rpm = polaris10_fan_ctrl_set_fan_speed_rpm,
5249 .uninitialize_thermal_controller = polaris10_thermal_ctrl_uninitialize_thermal_controller,
5250 .register_internal_thermal_interrupt = polaris10_register_internal_thermal_interrupt,
5251 .check_smc_update_required_for_display_configuration = polaris10_check_smc_update_required_for_display_configuration,
5252 .check_states_equal = polaris10_check_states_equal,
5253 .set_fan_control_mode = polaris10_set_fan_control_mode,
5254 .get_fan_control_mode = polaris10_get_fan_control_mode,
5255 .get_pp_table = polaris10_get_pp_table,
5256 .set_pp_table = polaris10_set_pp_table,
5257 .force_clock_level = polaris10_force_clock_level,
5258 .print_clock_levels = polaris10_print_clock_levels,
5259 .enable_per_cu_power_gating = polaris10_phm_enable_per_cu_power_gating,
5260 .get_sclk_od = polaris10_get_sclk_od,
5261 .set_sclk_od = polaris10_set_sclk_od,
5262 .get_mclk_od = polaris10_get_mclk_od,
5263 .set_mclk_od = polaris10_set_mclk_od,
5266 int polaris10_hwmgr_init(struct pp_hwmgr *hwmgr)
5268 struct polaris10_hwmgr *data;
5270 data = kzalloc (sizeof(struct polaris10_hwmgr), GFP_KERNEL);
5274 hwmgr->backend = data;
5275 hwmgr->hwmgr_func = &polaris10_hwmgr_funcs;
5276 hwmgr->pptable_func = &tonga_pptable_funcs;
5277 pp_polaris10_thermal_initialize(hwmgr);