drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/module.h>
  24 #include <linux/slab.h>
  25 #include <linux/fb.h>
  26 #include <asm/div64.h>
  27 #include "linux/delay.h"
  28 #include "pp_acpi.h"
  29 #include "hwmgr.h"
  30 #include "polaris10_hwmgr.h"
  31 #include "polaris10_powertune.h"
  32 #include "polaris10_dyn_defaults.h"
  33 #include "polaris10_smumgr.h"
  34 #include "pp_debug.h"
  35 #include "ppatomctrl.h"
  36 #include "atombios.h"
  37 #include "tonga_pptable.h"
  38 #include "pppcielanes.h"
  39 #include "amd_pcie_helpers.h"
  40 #include "hardwaremanager.h"
  41 #include "tonga_processpptables.h"
  42 #include "cgs_common.h"
  43 #include "smu74.h"
  44 #include "smu_ucode_xfer_vi.h"
  45 #include "smu74_discrete.h"
  46 #include "smu/smu_7_1_3_d.h"
  47 #include "smu/smu_7_1_3_sh_mask.h"
  48 #include "gmc/gmc_8_1_d.h"
  49 #include "gmc/gmc_8_1_sh_mask.h"
  50 #include "oss/oss_3_0_d.h"
  51 #include "gca/gfx_8_0_d.h"
  52 #include "bif/bif_5_0_d.h"
  53 #include "bif/bif_5_0_sh_mask.h"
  54 #include "gmc/gmc_8_1_d.h"
  55 #include "gmc/gmc_8_1_sh_mask.h"
  56 #include "bif/bif_5_0_d.h"
  57 #include "bif/bif_5_0_sh_mask.h"
  58 #include "dce/dce_10_0_d.h"
  59 #include "dce/dce_10_0_sh_mask.h"
  60
  61 #include "polaris10_thermal.h"
  62 #include "polaris10_clockpowergating.h"
  63
  64 #define MC_CG_ARB_FREQ_F0           0x0a
  65 #define MC_CG_ARB_FREQ_F1           0x0b
  66 #define MC_CG_ARB_FREQ_F2           0x0c
  67 #define MC_CG_ARB_FREQ_F3           0x0d
  68
  69 #define MC_CG_SEQ_DRAMCONF_S0       0x05
  70 #define MC_CG_SEQ_DRAMCONF_S1       0x06
  71 #define MC_CG_SEQ_YCLK_SUSPEND      0x04
  72 #define MC_CG_SEQ_YCLK_RESUME       0x0a
  73
  74
  75 #define SMC_RAM_END 0x40000
  76
  77 #define SMC_CG_IND_START            0xc0030000
  78 #define SMC_CG_IND_END              0xc0040000
  79
  80 #define VOLTAGE_SCALE               4
  81 #define VOLTAGE_VID_OFFSET_SCALE1   625
  82 #define VOLTAGE_VID_OFFSET_SCALE2   100
  83
  84 #define VDDC_VDDCI_DELTA            200
  85
  86 #define MEM_FREQ_LOW_LATENCY        25000
  87 #define MEM_FREQ_HIGH_LATENCY       80000
  88
  89 #define MEM_LATENCY_HIGH            45
  90 #define MEM_LATENCY_LOW             35
  91 #define MEM_LATENCY_ERR             0xFFFF
  92
  93 #define MC_SEQ_MISC0_GDDR5_SHIFT 28
  94 #define MC_SEQ_MISC0_GDDR5_MASK  0xf0000000
  95 #define MC_SEQ_MISC0_GDDR5_VALUE 5
  96
  97
  98 #define PCIE_BUS_CLK                10000
  99 #define TCLK                        (PCIE_BUS_CLK / 10)
 100
 101
 102 static const uint16_t polaris10_clock_stretcher_lookup_table[2][4] =
 103 { {600, 1050, 3, 0}, {600, 1050, 6, 1} };
 104
 105 /*  [FF, SS] type, [] 4 voltage ranges, and [Floor Freq, Boundary Freq, VID min , VID max] */
 106 static const uint32_t polaris10_clock_stretcher_ddt_table[2][4][4] =
 107 { { {265, 529, 120, 128}, {325, 650, 96, 119}, {430, 860, 32, 95}, {0, 0, 0, 31} },
 108   { {275, 550, 104, 112}, {319, 638, 96, 103}, {360, 720, 64, 95}, {384, 768, 32, 63} } };
 109
 110 /*  [Use_For_Low_freq] value, [0%, 5%, 10%, 7.14%, 14.28%, 20%] (coming from PWR_CKS_CNTL.stretch_amount reg spec) */
 111 static const uint8_t polaris10_clock_stretch_amount_conversion[2][6] =
 112 { {0, 1, 3, 2, 4, 5}, {0, 2, 4, 5, 6, 5} };
 113
 114 /** Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */
 115 enum DPM_EVENT_SRC {
 116         DPM_EVENT_SRC_ANALOG = 0,
 117         DPM_EVENT_SRC_EXTERNAL = 1,
 118         DPM_EVENT_SRC_DIGITAL = 2,
 119         DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
 120         DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL = 4
 121 };
 122
 123 static const unsigned long PhwPolaris10_Magic = (unsigned long)(PHM_VIslands_Magic);
 124
 125 struct polaris10_power_state *cast_phw_polaris10_power_state(
 126                                   struct pp_hw_power_state *hw_ps)
 127 {
 128         PP_ASSERT_WITH_CODE((PhwPolaris10_Magic == hw_ps->magic),
 129                                 "Invalid Powerstate Type!",
 130                                  return NULL);
 131
 132         return (struct polaris10_power_state *)hw_ps;
 133 }
 134
 135 const struct polaris10_power_state *cast_const_phw_polaris10_power_state(
 136                                  const struct pp_hw_power_state *hw_ps)
 137 {
 138         PP_ASSERT_WITH_CODE((PhwPolaris10_Magic == hw_ps->magic),
 139                                 "Invalid Powerstate Type!",
 140                                  return NULL);
 141
 142         return (const struct polaris10_power_state *)hw_ps;
 143 }
 144
 145 static bool polaris10_is_dpm_running(struct pp_hwmgr *hwmgr)
 146 {
 147         return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device,
 148                         CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON))
 149                         ? true : false;
 150 }
 151
 152 /**
 153  * Find the MC microcode version and store it in the HwMgr struct
 154  *
 155  * @param    hwmgr  the address of the powerplay hardware manager.
 156  * @return   always 0
 157  */
 158 int phm_get_mc_microcode_version (struct pp_hwmgr *hwmgr)
 159 {
 160         cgs_write_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_INDEX, 0x9F);
 161
 162         hwmgr->microcode_version_info.MC = cgs_read_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_DATA);
 163
 164         return 0;
 165 }
 166
 167 uint16_t phm_get_current_pcie_speed(struct pp_hwmgr *hwmgr)
 168 {
 169         uint32_t speedCntl = 0;
 170
 171         /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
 172         speedCntl = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__PCIE,
 173                         ixPCIE_LC_SPEED_CNTL);
 174         return((uint16_t)PHM_GET_FIELD(speedCntl,
 175                         PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE));
 176 }
 177
 178 int phm_get_current_pcie_lane_number(struct pp_hwmgr *hwmgr)
 179 {
 180         uint32_t link_width;
 181
 182         /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
 183         link_width = PHM_READ_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
 184                         PCIE_LC_LINK_WIDTH_CNTL, LC_LINK_WIDTH_RD);
 185
 186         PP_ASSERT_WITH_CODE((7 >= link_width),
 187                         "Invalid PCIe lane width!", return 0);
 188
 189         return decode_pcie_lane_width(link_width);
 190 }
 191
 192 /**
 193 * Enable voltage control
 194 *
 195 * @param    pHwMgr  the address of the powerplay hardware manager.
 196 * @return   always PP_Result_OK
 197 */
 198 int polaris10_enable_smc_voltage_controller(struct pp_hwmgr *hwmgr)
 199 {
 200         PP_ASSERT_WITH_CODE(
 201                 (hwmgr->smumgr->smumgr_funcs->send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_Voltage_Cntl_Enable) == 0),
 202                 "Failed to enable voltage DPM during DPM Start Function!",
 203                 return 1;
 204         );
 205
 206         return 0;
 207 }
 208
 209 /**
 210 * Checks if we want to support voltage control
 211 *
 212 * @param    hwmgr  the address of the powerplay hardware manager.
 213 */
 214 static bool polaris10_voltage_control(const struct pp_hwmgr *hwmgr)
 215 {
 216         const struct polaris10_hwmgr *data =
 217                         (const struct polaris10_hwmgr *)(hwmgr->backend);
 218
 219         return (POLARIS10_VOLTAGE_CONTROL_NONE != data->voltage_control);
 220 }
 221
 222 /**
 223 * Enable voltage control
 224 *
 225 * @param    hwmgr  the address of the powerplay hardware manager.
 226 * @return   always 0
 227 */
 228 static int polaris10_enable_voltage_control(struct pp_hwmgr *hwmgr)
 229 {
 230         /* enable voltage control */
 231         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 232                         GENERAL_PWRMGT, VOLT_PWRMGT_EN, 1);
 233
 234         return 0;
 235 }
 236
 237 /**
 238 * Create Voltage Tables.
 239 *
 240 * @param    hwmgr  the address of the powerplay hardware manager.
 241 * @return   always 0
 242 */
 243 static int polaris10_construct_voltage_tables(struct pp_hwmgr *hwmgr)
 244 {
 245         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 246         struct phm_ppt_v1_information *table_info =
 247                         (struct phm_ppt_v1_information *)hwmgr->pptable;
 248         int result;
 249
 250         if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
 251                 result = atomctrl_get_voltage_table_v3(hwmgr,
 252                                 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT,
 253                                 &(data->mvdd_voltage_table));
 254                 PP_ASSERT_WITH_CODE((0 == result),
 255                                 "Failed to retrieve MVDD table.",
 256                                 return result);
 257         } else if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
 258                 result = phm_get_svi2_mvdd_voltage_table(&(data->mvdd_voltage_table),
 259                                 table_info->vdd_dep_on_mclk);
 260                 PP_ASSERT_WITH_CODE((0 == result),
 261                                 "Failed to retrieve SVI2 MVDD table from dependancy table.",
 262                                 return result;);
 263         }
 264
 265         if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
 266                 result = atomctrl_get_voltage_table_v3(hwmgr,
 267                                 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT,
 268                                 &(data->vddci_voltage_table));
 269                 PP_ASSERT_WITH_CODE((0 == result),
 270                                 "Failed to retrieve VDDCI table.",
 271                                 return result);
 272         } else if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
 273                 result = phm_get_svi2_vddci_voltage_table(&(data->vddci_voltage_table),
 274                                 table_info->vdd_dep_on_mclk);
 275                 PP_ASSERT_WITH_CODE((0 == result),
 276                                 "Failed to retrieve SVI2 VDDCI table from dependancy table.",
 277                                 return result);
 278         }
 279
 280         if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
 281                 result = phm_get_svi2_vdd_voltage_table(&(data->vddc_voltage_table),
 282                                 table_info->vddc_lookup_table);
 283                 PP_ASSERT_WITH_CODE((0 == result),
 284                                 "Failed to retrieve SVI2 VDDC table from lookup table.",
 285                                 return result);
 286         }
 287
 288         PP_ASSERT_WITH_CODE(
 289                         (data->vddc_voltage_table.count <= (SMU74_MAX_LEVELS_VDDC)),
 290                         "Too many voltage values for VDDC. Trimming to fit state table.",
 291                         phm_trim_voltage_table_to_fit_state_table(SMU74_MAX_LEVELS_VDDC,
 292                                                                 &(data->vddc_voltage_table)));
 293
 294         PP_ASSERT_WITH_CODE(
 295                         (data->vddci_voltage_table.count <= (SMU74_MAX_LEVELS_VDDCI)),
 296                         "Too many voltage values for VDDCI. Trimming to fit state table.",
 297                         phm_trim_voltage_table_to_fit_state_table(SMU74_MAX_LEVELS_VDDCI,
 298                                         &(data->vddci_voltage_table)));
 299
 300         PP_ASSERT_WITH_CODE(
 301                         (data->mvdd_voltage_table.count <= (SMU74_MAX_LEVELS_MVDD)),
 302                         "Too many voltage values for MVDD. Trimming to fit state table.",
 303                         phm_trim_voltage_table_to_fit_state_table(SMU74_MAX_LEVELS_MVDD,
 304                                                            &(data->mvdd_voltage_table)));
 305
 306         return 0;
 307 }
 308
 309 /**
 310 * Programs static screed detection parameters
 311 *
 312 * @param    hwmgr  the address of the powerplay hardware manager.
 313 * @return   always 0
 314 */
 315 static int polaris10_program_static_screen_threshold_parameters(
 316                                                         struct pp_hwmgr *hwmgr)
 317 {
 318         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 319
 320         /* Set static screen threshold unit */
 321         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 322                         CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD_UNIT,
 323                         data->static_screen_threshold_unit);
 324         /* Set static screen threshold */
 325         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 326                         CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD,
 327                         data->static_screen_threshold);
 328
 329         return 0;
 330 }
 331
 332 /**
 333 * Setup display gap for glitch free memory clock switching.
 334 *
 335 * @param    hwmgr  the address of the powerplay hardware manager.
 336 * @return   always  0
 337 */
 338 static int polaris10_enable_display_gap(struct pp_hwmgr *hwmgr)
 339 {
 340         uint32_t display_gap =
 341                         cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 342                                         ixCG_DISPLAY_GAP_CNTL);
 343
 344         display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL,
 345                         DISP_GAP, DISPLAY_GAP_IGNORE);
 346
 347         display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL,
 348                         DISP_GAP_MCHG, DISPLAY_GAP_VBLANK);
 349
 350         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 351                         ixCG_DISPLAY_GAP_CNTL, display_gap);
 352
 353         return 0;
 354 }
 355
 356 /**
 357 * Programs activity state transition voting clients
 358 *
 359 * @param    hwmgr  the address of the powerplay hardware manager.
 360 * @return   always  0
 361 */
 362 static int polaris10_program_voting_clients(struct pp_hwmgr *hwmgr)
 363 {
 364         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 365
 366         /* Clear reset for voting clients before enabling DPM */
 367         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 368                         SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 0);
 369         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 370                         SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 0);
 371
 372         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 373                         ixCG_FREQ_TRAN_VOTING_0, data->voting_rights_clients0);
 374         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 375                         ixCG_FREQ_TRAN_VOTING_1, data->voting_rights_clients1);
 376         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 377                         ixCG_FREQ_TRAN_VOTING_2, data->voting_rights_clients2);
 378         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 379                         ixCG_FREQ_TRAN_VOTING_3, data->voting_rights_clients3);
 380         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 381                         ixCG_FREQ_TRAN_VOTING_4, data->voting_rights_clients4);
 382         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 383                         ixCG_FREQ_TRAN_VOTING_5, data->voting_rights_clients5);
 384         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 385                         ixCG_FREQ_TRAN_VOTING_6, data->voting_rights_clients6);
 386         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 387                         ixCG_FREQ_TRAN_VOTING_7, data->voting_rights_clients7);
 388
 389         return 0;
 390 }
 391
 392 static int polaris10_clear_voting_clients(struct pp_hwmgr *hwmgr)
 393 {
 394         /* Reset voting clients before disabling DPM */
 395         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 396                         SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 1);
 397         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 398                         SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 1);
 399
 400         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 401                         ixCG_FREQ_TRAN_VOTING_0, 0);
 402         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 403                         ixCG_FREQ_TRAN_VOTING_1, 0);
 404         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 405                         ixCG_FREQ_TRAN_VOTING_2, 0);
 406         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 407                         ixCG_FREQ_TRAN_VOTING_3, 0);
 408         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 409                         ixCG_FREQ_TRAN_VOTING_4, 0);
 410         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 411                         ixCG_FREQ_TRAN_VOTING_5, 0);
 412         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 413                         ixCG_FREQ_TRAN_VOTING_6, 0);
 414         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 415                         ixCG_FREQ_TRAN_VOTING_7, 0);
 416
 417         return 0;
 418 }
 419
 420 /**
 421 * Get the location of various tables inside the FW image.
 422 *
 423 * @param    hwmgr  the address of the powerplay hardware manager.
 424 * @return   always  0
 425 */
 426 static int polaris10_process_firmware_header(struct pp_hwmgr *hwmgr)
 427 {
 428         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 429         struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend);
 430         uint32_t tmp;
 431         int result;
 432         bool error = false;
 433
 434         result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
 435                         SMU7_FIRMWARE_HEADER_LOCATION +
 436                         offsetof(SMU74_Firmware_Header, DpmTable),
 437                         &tmp, data->sram_end);
 438
 439         if (0 == result)
 440                 data->dpm_table_start = tmp;
 441
 442         error |= (0 != result);
 443
 444         result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
 445                         SMU7_FIRMWARE_HEADER_LOCATION +
 446                         offsetof(SMU74_Firmware_Header, SoftRegisters),
 447                         &tmp, data->sram_end);
 448
 449         if (!result) {
 450                 data->soft_regs_start = tmp;
 451                 smu_data->soft_regs_start = tmp;
 452         }
 453
 454         error |= (0 != result);
 455
 456         result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
 457                         SMU7_FIRMWARE_HEADER_LOCATION +
 458                         offsetof(SMU74_Firmware_Header, mcRegisterTable),
 459                         &tmp, data->sram_end);
 460
 461         if (!result)
 462                 data->mc_reg_table_start = tmp;
 463
 464         result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
 465                         SMU7_FIRMWARE_HEADER_LOCATION +
 466                         offsetof(SMU74_Firmware_Header, FanTable),
 467                         &tmp, data->sram_end);
 468
 469         if (!result)
 470                 data->fan_table_start = tmp;
 471
 472         error |= (0 != result);
 473
 474         result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
 475                         SMU7_FIRMWARE_HEADER_LOCATION +
 476                         offsetof(SMU74_Firmware_Header, mcArbDramTimingTable),
 477                         &tmp, data->sram_end);
 478
 479         if (!result)
 480                 data->arb_table_start = tmp;
 481
 482         error |= (0 != result);
 483
 484         result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
 485                         SMU7_FIRMWARE_HEADER_LOCATION +
 486                         offsetof(SMU74_Firmware_Header, Version),
 487                         &tmp, data->sram_end);
 488
 489         if (!result)
 490                 hwmgr->microcode_version_info.SMC = tmp;
 491
 492         error |= (0 != result);
 493
 494         return error ? -1 : 0;
 495 }
 496
 497 /* Copy one arb setting to another and then switch the active set.
 498  * arb_src and arb_dest is one of the MC_CG_ARB_FREQ_Fx constants.
 499  */
 500 static int polaris10_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr,
 501                 uint32_t arb_src, uint32_t arb_dest)
 502 {
 503         uint32_t mc_arb_dram_timing;
 504         uint32_t mc_arb_dram_timing2;
 505         uint32_t burst_time;
 506         uint32_t mc_cg_config;
 507
 508         switch (arb_src) {
 509         case MC_CG_ARB_FREQ_F0:
 510                 mc_arb_dram_timing  = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
 511                 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
 512                 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
 513                 break;
 514         case MC_CG_ARB_FREQ_F1:
 515                 mc_arb_dram_timing  = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1);
 516                 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1);
 517                 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1);
 518                 break;
 519         default:
 520                 return -EINVAL;
 521         }
 522
 523         switch (arb_dest) {
 524         case MC_CG_ARB_FREQ_F0:
 525                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING, mc_arb_dram_timing);
 526                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
 527                 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0, burst_time);
 528                 break;
 529         case MC_CG_ARB_FREQ_F1:
 530                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
 531                 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
 532                 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1, burst_time);
 533                 break;
 534         default:
 535                 return -EINVAL;
 536         }
 537
 538         mc_cg_config = cgs_read_register(hwmgr->device, mmMC_CG_CONFIG);
 539         mc_cg_config |= 0x0000000F;
 540         cgs_write_register(hwmgr->device, mmMC_CG_CONFIG, mc_cg_config);
 541         PHM_WRITE_FIELD(hwmgr->device, MC_ARB_CG, CG_ARB_REQ, arb_dest);
 542
 543         return 0;
 544 }
 545
 546 static int polaris10_reset_to_default(struct pp_hwmgr *hwmgr)
 547 {
 548         return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_ResetToDefaults);
 549 }
 550
 551 /**
 552 * Initial switch from ARB F0->F1
 553 *
 554 * @param    hwmgr  the address of the powerplay hardware manager.
 555 * @return   always 0
 556 * This function is to be called from the SetPowerState table.
 557 */
 558 static int polaris10_initial_switch_from_arbf0_to_f1(struct pp_hwmgr *hwmgr)
 559 {
 560         return polaris10_copy_and_switch_arb_sets(hwmgr,
 561                         MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
 562 }
 563
 564 static int polaris10_force_switch_to_arbf0(struct pp_hwmgr *hwmgr)
 565 {
 566         uint32_t tmp;
 567
 568         tmp = (cgs_read_ind_register(hwmgr->device,
 569                         CGS_IND_REG__SMC, ixSMC_SCRATCH9) &
 570                         0x0000ff00) >> 8;
 571
 572         if (tmp == MC_CG_ARB_FREQ_F0)
 573                 return 0;
 574
 575         return polaris10_copy_and_switch_arb_sets(hwmgr,
 576                         tmp, MC_CG_ARB_FREQ_F0);
 577 }
 578
 579 static int polaris10_setup_default_pcie_table(struct pp_hwmgr *hwmgr)
 580 {
 581         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 582         struct phm_ppt_v1_information *table_info =
 583                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 584         struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
 585         uint32_t i, max_entry;
 586
 587         PP_ASSERT_WITH_CODE((data->use_pcie_performance_levels ||
 588                         data->use_pcie_power_saving_levels), "No pcie performance levels!",
 589                         return -EINVAL);
 590
 591         if (data->use_pcie_performance_levels &&
 592                         !data->use_pcie_power_saving_levels) {
 593                 data->pcie_gen_power_saving = data->pcie_gen_performance;
 594                 data->pcie_lane_power_saving = data->pcie_lane_performance;
 595         } else if (!data->use_pcie_performance_levels &&
 596                         data->use_pcie_power_saving_levels) {
 597                 data->pcie_gen_performance = data->pcie_gen_power_saving;
 598                 data->pcie_lane_performance = data->pcie_lane_power_saving;
 599         }
 600
 601         phm_reset_single_dpm_table(&data->dpm_table.pcie_speed_table,
 602                                         SMU74_MAX_LEVELS_LINK,
 603                                         MAX_REGULAR_DPM_NUMBER);
 604
 605         if (pcie_table != NULL) {
 606                 /* max_entry is used to make sure we reserve one PCIE level
 607                  * for boot level (fix for A+A PSPP issue).
 608                  * If PCIE table from PPTable have ULV entry + 8 entries,
 609                  * then ignore the last entry.*/
 610                 max_entry = (SMU74_MAX_LEVELS_LINK < pcie_table->count) ?
 611                                 SMU74_MAX_LEVELS_LINK : pcie_table->count;
 612                 for (i = 1; i < max_entry; i++) {
 613                         phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i - 1,
 614                                         get_pcie_gen_support(data->pcie_gen_cap,
 615                                                         pcie_table->entries[i].gen_speed),
 616                                         get_pcie_lane_support(data->pcie_lane_cap,
 617                                                         pcie_table->entries[i].lane_width));
 618                 }
 619                 data->dpm_table.pcie_speed_table.count = max_entry - 1;
 620
 621                 /* Setup BIF_SCLK levels */
 622                 for (i = 0; i < max_entry; i++)
 623                         data->bif_sclk_table[i] = pcie_table->entries[i].pcie_sclk;
 624         } else {
 625                 /* Hardcode Pcie Table */
 626                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 0,
 627                                 get_pcie_gen_support(data->pcie_gen_cap,
 628                                                 PP_Min_PCIEGen),
 629                                 get_pcie_lane_support(data->pcie_lane_cap,
 630                                                 PP_Max_PCIELane));
 631                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 1,
 632                                 get_pcie_gen_support(data->pcie_gen_cap,
 633                                                 PP_Min_PCIEGen),
 634                                 get_pcie_lane_support(data->pcie_lane_cap,
 635                                                 PP_Max_PCIELane));
 636                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 2,
 637                                 get_pcie_gen_support(data->pcie_gen_cap,
 638                                                 PP_Max_PCIEGen),
 639                                 get_pcie_lane_support(data->pcie_lane_cap,
 640                                                 PP_Max_PCIELane));
 641                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 3,
 642                                 get_pcie_gen_support(data->pcie_gen_cap,
 643                                                 PP_Max_PCIEGen),
 644                                 get_pcie_lane_support(data->pcie_lane_cap,
 645                                                 PP_Max_PCIELane));
 646                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 4,
 647                                 get_pcie_gen_support(data->pcie_gen_cap,
 648                                                 PP_Max_PCIEGen),
 649                                 get_pcie_lane_support(data->pcie_lane_cap,
 650                                                 PP_Max_PCIELane));
 651                 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 5,
 652                                 get_pcie_gen_support(data->pcie_gen_cap,
 653                                                 PP_Max_PCIEGen),
 654                                 get_pcie_lane_support(data->pcie_lane_cap,
 655                                                 PP_Max_PCIELane));
 656
 657                 data->dpm_table.pcie_speed_table.count = 6;
 658         }
 659         /* Populate last level for boot PCIE level, but do not increment count. */
 660         phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table,
 661                         data->dpm_table.pcie_speed_table.count,
 662                         get_pcie_gen_support(data->pcie_gen_cap,
 663                                         PP_Min_PCIEGen),
 664                         get_pcie_lane_support(data->pcie_lane_cap,
 665                                         PP_Max_PCIELane));
 666
 667         return 0;
 668 }
 669
 670 /*
 671  * This function is to initalize all DPM state tables
 672  * for SMU7 based on the dependency table.
 673  * Dynamic state patching function will then trim these
 674  * state tables to the allowed range based
 675  * on the power policy or external client requests,
 676  * such as UVD request, etc.
 677  */
 678 int polaris10_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
 679 {
 680         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 681         struct phm_ppt_v1_information *table_info =
 682                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 683         uint32_t i;
 684
 685         struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table =
 686                         table_info->vdd_dep_on_sclk;
 687         struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
 688                         table_info->vdd_dep_on_mclk;
 689
 690         PP_ASSERT_WITH_CODE(dep_sclk_table != NULL,
 691                         "SCLK dependency table is missing. This table is mandatory",
 692                         return -EINVAL);
 693         PP_ASSERT_WITH_CODE(dep_sclk_table->count >= 1,
 694                         "SCLK dependency table has to have is missing."
 695                         "This table is mandatory",
 696                         return -EINVAL);
 697
 698         PP_ASSERT_WITH_CODE(dep_mclk_table != NULL,
 699                         "MCLK dependency table is missing. This table is mandatory",
 700                         return -EINVAL);
 701         PP_ASSERT_WITH_CODE(dep_mclk_table->count >= 1,
 702                         "MCLK dependency table has to have is missing."
 703                         "This table is mandatory",
 704                         return -EINVAL);
 705
 706         /* clear the state table to reset everything to default */
 707         phm_reset_single_dpm_table(
 708                         &data->dpm_table.sclk_table, SMU74_MAX_LEVELS_GRAPHICS, MAX_REGULAR_DPM_NUMBER);
 709         phm_reset_single_dpm_table(
 710                         &data->dpm_table.mclk_table, SMU74_MAX_LEVELS_MEMORY, MAX_REGULAR_DPM_NUMBER);
 711
 712
 713         /* Initialize Sclk DPM table based on allow Sclk values */
 714         data->dpm_table.sclk_table.count = 0;
 715         for (i = 0; i < dep_sclk_table->count; i++) {
 716                 if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count - 1].value !=
 717                                                 dep_sclk_table->entries[i].clk) {
 718
 719                         data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value =
 720                                         dep_sclk_table->entries[i].clk;
 721
 722                         data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled =
 723                                         (i == 0) ? true : false;
 724                         data->dpm_table.sclk_table.count++;
 725                 }
 726         }
 727
 728         /* Initialize Mclk DPM table based on allow Mclk values */
 729         data->dpm_table.mclk_table.count = 0;
 730         for (i = 0; i < dep_mclk_table->count; i++) {
 731                 if (i == 0 || data->dpm_table.mclk_table.dpm_levels
 732                                 [data->dpm_table.mclk_table.count - 1].value !=
 733                                                 dep_mclk_table->entries[i].clk) {
 734                         data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value =
 735                                                         dep_mclk_table->entries[i].clk;
 736                         data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled =
 737                                                         (i == 0) ? true : false;
 738                         data->dpm_table.mclk_table.count++;
 739                 }
 740         }
 741
 742         /* setup PCIE gen speed levels */
 743         polaris10_setup_default_pcie_table(hwmgr);
 744
 745         /* save a copy of the default DPM table */
 746         memcpy(&(data->golden_dpm_table), &(data->dpm_table),
 747                         sizeof(struct polaris10_dpm_table));
 748
 749         return 0;
 750 }
 751
 752 uint8_t convert_to_vid(uint16_t vddc)
 753 {
 754         return (uint8_t) ((6200 - (vddc * VOLTAGE_SCALE)) / 25);
 755 }
 756
 757 /**
 758  * Mvdd table preparation for SMC.
 759  *
 760  * @param    *hwmgr The address of the hardware manager.
 761  * @param    *table The SMC DPM table structure to be populated.
 762  * @return   0
 763  */
 764 static int polaris10_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr,
 765                         SMU74_Discrete_DpmTable *table)
 766 {
 767         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 768         uint32_t count, level;
 769
 770         if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
 771                 count = data->mvdd_voltage_table.count;
 772                 if (count > SMU_MAX_SMIO_LEVELS)
 773                         count = SMU_MAX_SMIO_LEVELS;
 774                 for (level = 0; level < count; level++) {
 775                         table->SmioTable2.Pattern[level].Voltage =
 776                                 PP_HOST_TO_SMC_US(data->mvdd_voltage_table.entries[count].value * VOLTAGE_SCALE);
 777                         /* Index into DpmTable.Smio. Drive bits from Smio entry to get this voltage level.*/
 778                         table->SmioTable2.Pattern[level].Smio =
 779                                 (uint8_t) level;
 780                         table->Smio[level] |=
 781                                 data->mvdd_voltage_table.entries[level].smio_low;
 782                 }
 783                 table->SmioMask2 = data->vddci_voltage_table.mask_low;
 784
 785                 table->MvddLevelCount = (uint32_t) PP_HOST_TO_SMC_UL(count);
 786         }
 787
 788         return 0;
 789 }
 790
 791 static int polaris10_populate_smc_vddci_table(struct pp_hwmgr *hwmgr,
 792                                         struct SMU74_Discrete_DpmTable *table)
 793 {
 794         uint32_t count, level;
 795         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 796
 797         count = data->vddci_voltage_table.count;
 798
 799         if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
 800                 if (count > SMU_MAX_SMIO_LEVELS)
 801                         count = SMU_MAX_SMIO_LEVELS;
 802                 for (level = 0; level < count; ++level) {
 803                         table->SmioTable1.Pattern[level].Voltage =
 804                                 PP_HOST_TO_SMC_US(data->vddci_voltage_table.entries[level].value * VOLTAGE_SCALE);
 805                         table->SmioTable1.Pattern[level].Smio = (uint8_t) level;
 806
 807                         table->Smio[level] |= data->vddci_voltage_table.entries[level].smio_low;
 808                 }
 809         }
 810
 811         table->SmioMask1 = data->vddci_voltage_table.mask_low;
 812
 813         return 0;
 814 }
 815
 816 /**
 817 * Preparation of vddc and vddgfx CAC tables for SMC.
 818 *
 819 * @param    hwmgr  the address of the hardware manager
 820 * @param    table  the SMC DPM table structure to be populated
 821 * @return   always 0
 822 */
 823 static int polaris10_populate_cac_table(struct pp_hwmgr *hwmgr,
 824                 struct SMU74_Discrete_DpmTable *table)
 825 {
 826         uint32_t count;
 827         uint8_t index;
 828         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 829         struct phm_ppt_v1_information *table_info =
 830                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 831         struct phm_ppt_v1_voltage_lookup_table *lookup_table =
 832                         table_info->vddc_lookup_table;
 833         /* tables is already swapped, so in order to use the value from it,
 834          * we need to swap it back.
 835          * We are populating vddc CAC data to BapmVddc table
 836          * in split and merged mode
 837          */
 838         for (count = 0; count < lookup_table->count; count++) {
 839                 index = phm_get_voltage_index(lookup_table,
 840                                 data->vddc_voltage_table.entries[count].value);
 841                 table->BapmVddcVidLoSidd[count] = convert_to_vid(lookup_table->entries[index].us_cac_low);
 842                 table->BapmVddcVidHiSidd[count] = convert_to_vid(lookup_table->entries[index].us_cac_mid);
 843                 table->BapmVddcVidHiSidd2[count] = convert_to_vid(lookup_table->entries[index].us_cac_high);
 844         }
 845
 846         return 0;
 847 }
 848
 849 /**
 850 * Preparation of voltage tables for SMC.
 851 *
 852 * @param    hwmgr   the address of the hardware manager
 853 * @param    table   the SMC DPM table structure to be populated
 854 * @return   always  0
 855 */
 856
 857 int polaris10_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
 858                 struct SMU74_Discrete_DpmTable *table)
 859 {
 860         polaris10_populate_smc_vddci_table(hwmgr, table);
 861         polaris10_populate_smc_mvdd_table(hwmgr, table);
 862         polaris10_populate_cac_table(hwmgr, table);
 863
 864         return 0;
 865 }
 866
 867 static int polaris10_populate_ulv_level(struct pp_hwmgr *hwmgr,
 868                 struct SMU74_Discrete_Ulv *state)
 869 {
 870         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 871         struct phm_ppt_v1_information *table_info =
 872                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 873
 874         state->CcPwrDynRm = 0;
 875         state->CcPwrDynRm1 = 0;
 876
 877         state->VddcOffset = (uint16_t) table_info->us_ulv_voltage_offset;
 878         state->VddcOffsetVid = (uint8_t)(table_info->us_ulv_voltage_offset *
 879                         VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
 880
 881         state->VddcPhase = (data->vddc_phase_shed_control) ? 0 : 1;
 882
 883         CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm);
 884         CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm1);
 885         CONVERT_FROM_HOST_TO_SMC_US(state->VddcOffset);
 886
 887         return 0;
 888 }
 889
 890 static int polaris10_populate_ulv_state(struct pp_hwmgr *hwmgr,
 891                 struct SMU74_Discrete_DpmTable *table)
 892 {
 893         return polaris10_populate_ulv_level(hwmgr, &table->Ulv);
 894 }
 895
 896 static int polaris10_populate_smc_link_level(struct pp_hwmgr *hwmgr,
 897                 struct SMU74_Discrete_DpmTable *table)
 898 {
 899         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 900         struct polaris10_dpm_table *dpm_table = &data->dpm_table;
 901         int i;
 902
 903         /* Index (dpm_table->pcie_speed_table.count)
 904          * is reserved for PCIE boot level. */
 905         for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
 906                 table->LinkLevel[i].PcieGenSpeed  =
 907                                 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
 908                 table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width(
 909                                 dpm_table->pcie_speed_table.dpm_levels[i].param1);
 910                 table->LinkLevel[i].EnabledForActivity = 1;
 911                 table->LinkLevel[i].SPC = (uint8_t)(data->pcie_spc_cap & 0xff);
 912                 table->LinkLevel[i].DownThreshold = PP_HOST_TO_SMC_UL(5);
 913                 table->LinkLevel[i].UpThreshold = PP_HOST_TO_SMC_UL(30);
 914         }
 915
 916         data->smc_state_table.LinkLevelCount =
 917                         (uint8_t)dpm_table->pcie_speed_table.count;
 918         data->dpm_level_enable_mask.pcie_dpm_enable_mask =
 919                         phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
 920
 921         return 0;
 922 }
 923
 924 static uint32_t polaris10_get_xclk(struct pp_hwmgr *hwmgr)
 925 {
 926         uint32_t reference_clock, tmp;
 927         struct cgs_display_info info = {0};
 928         struct cgs_mode_info mode_info;
 929
 930         info.mode_info = &mode_info;
 931
 932         tmp = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_CLKPIN_CNTL_2, MUX_TCLK_TO_XCLK);
 933
 934         if (tmp)
 935                 return TCLK;
 936
 937         cgs_get_active_displays_info(hwmgr->device, &info);
 938         reference_clock = mode_info.ref_clock;
 939
 940         tmp = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_CLKPIN_CNTL, XTALIN_DIVIDE);
 941
 942         if (0 != tmp)
 943                 return reference_clock / 4;
 944
 945         return reference_clock;
 946 }
 947
 948 /**
 949 * Calculates the SCLK dividers using the provided engine clock
 950 *
 951 * @param    hwmgr  the address of the hardware manager
 952 * @param    clock  the engine clock to use to populate the structure
 953 * @param    sclk   the SMC SCLK structure to be populated
 954 */
 955 static int polaris10_calculate_sclk_params(struct pp_hwmgr *hwmgr,
 956                 uint32_t clock, SMU_SclkSetting *sclk_setting)
 957 {
 958         const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 959         const SMU74_Discrete_DpmTable *table = &(data->smc_state_table);
 960         struct pp_atomctrl_clock_dividers_ai dividers;
 961
 962         uint32_t ref_clock;
 963         uint32_t pcc_target_percent, pcc_target_freq, ss_target_percent, ss_target_freq;
 964         uint8_t i;
 965         int result;
 966         uint64_t temp;
 967
 968         sclk_setting->SclkFrequency = clock;
 969         /* get the engine clock dividers for this clock value */
 970         result = atomctrl_get_engine_pll_dividers_ai(hwmgr, clock,  &dividers);
 971         if (result == 0) {
 972                 sclk_setting->Fcw_int = dividers.usSclk_fcw_int;
 973                 sclk_setting->Fcw_frac = dividers.usSclk_fcw_frac;
 974                 sclk_setting->Pcc_fcw_int = dividers.usPcc_fcw_int;
 975                 sclk_setting->PllRange = dividers.ucSclkPllRange;
 976                 sclk_setting->Sclk_slew_rate = 0x400;
 977                 sclk_setting->Pcc_up_slew_rate = dividers.usPcc_fcw_slew_frac;
 978                 sclk_setting->Pcc_down_slew_rate = 0xffff;
 979                 sclk_setting->SSc_En = dividers.ucSscEnable;
 980                 sclk_setting->Fcw1_int = dividers.usSsc_fcw1_int;
 981                 sclk_setting->Fcw1_frac = dividers.usSsc_fcw1_frac;
 982                 sclk_setting->Sclk_ss_slew_rate = dividers.usSsc_fcw_slew_frac;
 983                 return result;
 984         }
 985
 986         ref_clock = polaris10_get_xclk(hwmgr);
 987
 988         for (i = 0; i < NUM_SCLK_RANGE; i++) {
 989                 if (clock > data->range_table[i].trans_lower_frequency
 990                 && clock <= data->range_table[i].trans_upper_frequency) {
 991                         sclk_setting->PllRange = i;
 992                         break;
 993                 }
 994         }
 995
 996         sclk_setting->Fcw_int = (uint16_t)((clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
 997         temp = clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
 998         temp <<= 0x10;
 999         do_div(temp, ref_clock);
1000         sclk_setting->Fcw_frac = temp & 0xffff;
1001
1002         pcc_target_percent = 10; /*  Hardcode 10% for now. */
1003         pcc_target_freq = clock - (clock * pcc_target_percent / 100);
1004         sclk_setting->Pcc_fcw_int = (uint16_t)((pcc_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
1005
1006         ss_target_percent = 2; /*  Hardcode 2% for now. */
1007         sclk_setting->SSc_En = 0;
1008         if (ss_target_percent) {
1009                 sclk_setting->SSc_En = 1;
1010                 ss_target_freq = clock - (clock * ss_target_percent / 100);
1011                 sclk_setting->Fcw1_int = (uint16_t)((ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
1012                 temp = ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
1013                 temp <<= 0x10;
1014                 do_div(temp, ref_clock);
1015                 sclk_setting->Fcw1_frac = temp & 0xffff;
1016         }
1017
1018         return 0;
1019 }
1020
1021 static int polaris10_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr,
1022                 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table,
1023                 uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd)
1024 {
1025         uint32_t i;
1026         uint16_t vddci;
1027         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1028
1029         *voltage = *mvdd = 0;
1030
1031         /* clock - voltage dependency table is empty table */
1032         if (dep_table->count == 0)
1033                 return -EINVAL;
1034
1035         for (i = 0; i < dep_table->count; i++) {
1036                 /* find first sclk bigger than request */
1037                 if (dep_table->entries[i].clk >= clock) {
1038                         *voltage |= (dep_table->entries[i].vddc *
1039                                         VOLTAGE_SCALE) << VDDC_SHIFT;
1040                         if (POLARIS10_VOLTAGE_CONTROL_NONE == data->vddci_control)
1041                                 *voltage |= (data->vbios_boot_state.vddci_bootup_value *
1042                                                 VOLTAGE_SCALE) << VDDCI_SHIFT;
1043                         else if (dep_table->entries[i].vddci)
1044                                 *voltage |= (dep_table->entries[i].vddci *
1045                                                 VOLTAGE_SCALE) << VDDCI_SHIFT;
1046                         else {
1047                                 vddci = phm_find_closest_vddci(&(data->vddci_voltage_table),
1048                                                 (dep_table->entries[i].vddc -
1049                                                                 (uint16_t)data->vddc_vddci_delta));
1050                                 *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1051                         }
1052
1053                         if (POLARIS10_VOLTAGE_CONTROL_NONE == data->mvdd_control)
1054                                 *mvdd = data->vbios_boot_state.mvdd_bootup_value *
1055                                         VOLTAGE_SCALE;
1056                         else if (dep_table->entries[i].mvdd)
1057                                 *mvdd = (uint32_t) dep_table->entries[i].mvdd *
1058                                         VOLTAGE_SCALE;
1059
1060                         *voltage |= 1 << PHASES_SHIFT;
1061                         return 0;
1062                 }
1063         }
1064
1065         /* sclk is bigger than max sclk in the dependence table */
1066         *voltage |= (dep_table->entries[i - 1].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
1067
1068         if (POLARIS10_VOLTAGE_CONTROL_NONE == data->vddci_control)
1069                 *voltage |= (data->vbios_boot_state.vddci_bootup_value *
1070                                 VOLTAGE_SCALE) << VDDCI_SHIFT;
1071         else if (dep_table->entries[i-1].vddci) {
1072                 vddci = phm_find_closest_vddci(&(data->vddci_voltage_table),
1073                                 (dep_table->entries[i].vddc -
1074                                                 (uint16_t)data->vddc_vddci_delta));
1075                 *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1076         }
1077
1078         if (POLARIS10_VOLTAGE_CONTROL_NONE == data->mvdd_control)
1079                 *mvdd = data->vbios_boot_state.mvdd_bootup_value * VOLTAGE_SCALE;
1080         else if (dep_table->entries[i].mvdd)
1081                 *mvdd = (uint32_t) dep_table->entries[i - 1].mvdd * VOLTAGE_SCALE;
1082
1083         return 0;
1084 }
1085
1086 static const sclkFcwRange_t Range_Table[NUM_SCLK_RANGE] =
1087 { {VCO_2_4, POSTDIV_DIV_BY_16,  75, 160, 112},
1088   {VCO_3_6, POSTDIV_DIV_BY_16, 112, 224, 160},
1089   {VCO_2_4, POSTDIV_DIV_BY_8,   75, 160, 112},
1090   {VCO_3_6, POSTDIV_DIV_BY_8,  112, 224, 160},
1091   {VCO_2_4, POSTDIV_DIV_BY_4,   75, 160, 112},
1092   {VCO_3_6, POSTDIV_DIV_BY_4,  112, 216, 160},
1093   {VCO_2_4, POSTDIV_DIV_BY_2,   75, 160, 108},
1094   {VCO_3_6, POSTDIV_DIV_BY_2,  112, 216, 160} };
1095
1096 static void polaris10_get_sclk_range_table(struct pp_hwmgr *hwmgr)
1097 {
1098         uint32_t i, ref_clk;
1099         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1100         SMU74_Discrete_DpmTable  *table = &(data->smc_state_table);
1101         struct pp_atom_ctrl_sclk_range_table range_table_from_vbios = { { {0} } };
1102
1103         ref_clk = polaris10_get_xclk(hwmgr);
1104
1105         if (0 == atomctrl_get_smc_sclk_range_table(hwmgr, &range_table_from_vbios)) {
1106                 for (i = 0; i < NUM_SCLK_RANGE; i++) {
1107                         table->SclkFcwRangeTable[i].vco_setting = range_table_from_vbios.entry[i].ucVco_setting;
1108                         table->SclkFcwRangeTable[i].postdiv = range_table_from_vbios.entry[i].ucPostdiv;
1109                         table->SclkFcwRangeTable[i].fcw_pcc = range_table_from_vbios.entry[i].usFcw_pcc;
1110
1111                         table->SclkFcwRangeTable[i].fcw_trans_upper = range_table_from_vbios.entry[i].usFcw_trans_upper;
1112                         table->SclkFcwRangeTable[i].fcw_trans_lower = range_table_from_vbios.entry[i].usRcw_trans_lower;
1113
1114                         CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc);
1115                         CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper);
1116                         CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower);
1117                 }
1118                 return;
1119         }
1120
1121         for (i = 0; i < NUM_SCLK_RANGE; i++) {
1122
1123                 data->range_table[i].trans_lower_frequency = (ref_clk * Range_Table[i].fcw_trans_lower) >> Range_Table[i].postdiv;
1124                 data->range_table[i].trans_upper_frequency = (ref_clk * Range_Table[i].fcw_trans_upper) >> Range_Table[i].postdiv;
1125
1126                 table->SclkFcwRangeTable[i].vco_setting = Range_Table[i].vco_setting;
1127                 table->SclkFcwRangeTable[i].postdiv = Range_Table[i].postdiv;
1128                 table->SclkFcwRangeTable[i].fcw_pcc = Range_Table[i].fcw_pcc;
1129
1130                 table->SclkFcwRangeTable[i].fcw_trans_upper = Range_Table[i].fcw_trans_upper;
1131                 table->SclkFcwRangeTable[i].fcw_trans_lower = Range_Table[i].fcw_trans_lower;
1132
1133                 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc);
1134                 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper);
1135                 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower);
1136         }
1137 }
1138
1139 /**
1140 * Populates single SMC SCLK structure using the provided engine clock
1141 *
1142 * @param    hwmgr      the address of the hardware manager
1143 * @param    clock the engine clock to use to populate the structure
1144 * @param    sclk        the SMC SCLK structure to be populated
1145 */
1146
1147 static int polaris10_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
1148                 uint32_t clock, uint16_t sclk_al_threshold,
1149                 struct SMU74_Discrete_GraphicsLevel *level)
1150 {
1151         int result, i, temp;
1152         /* PP_Clocks minClocks; */
1153         uint32_t mvdd;
1154         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1155         struct phm_ppt_v1_information *table_info =
1156                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1157         SMU_SclkSetting curr_sclk_setting = { 0 };
1158
1159         result = polaris10_calculate_sclk_params(hwmgr, clock, &curr_sclk_setting);
1160
1161         /* populate graphics levels */
1162         result = polaris10_get_dependency_volt_by_clk(hwmgr,
1163                         table_info->vdd_dep_on_sclk, clock,
1164                         &level->MinVoltage, &mvdd);
1165
1166         PP_ASSERT_WITH_CODE((0 == result),
1167                         "can not find VDDC voltage value for "
1168                         "VDDC engine clock dependency table",
1169                         return result);
1170         level->ActivityLevel = sclk_al_threshold;
1171
1172         level->CcPwrDynRm = 0;
1173         level->CcPwrDynRm1 = 0;
1174         level->EnabledForActivity = 0;
1175         level->EnabledForThrottle = 1;
1176         level->UpHyst = 10;
1177         level->DownHyst = 0;
1178         level->VoltageDownHyst = 0;
1179         level->PowerThrottle = 0;
1180
1181         /*
1182         * TODO: get minimum clocks from dal configaration
1183         * PECI_GetMinClockSettings(hwmgr->pPECI, &minClocks);
1184         */
1185         /* data->DisplayTiming.minClockInSR = minClocks.engineClockInSR; */
1186
1187         /* get level->DeepSleepDivId
1188         if (phm_cap_enabled(hwmgr->platformDescriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep))
1189                 level->DeepSleepDivId = PhwFiji_GetSleepDividerIdFromClock(hwmgr, clock, minClocks.engineClockInSR);
1190         */
1191         PP_ASSERT_WITH_CODE((clock >= POLARIS10_MINIMUM_ENGINE_CLOCK), "Engine clock can't satisfy stutter requirement!", return 0);
1192         for (i = POLARIS10_MAX_DEEPSLEEP_DIVIDER_ID;  ; i--) {
1193                 temp = clock >> i;
1194
1195                 if (temp >= POLARIS10_MINIMUM_ENGINE_CLOCK || i == 0)
1196                         break;
1197         }
1198
1199         level->DeepSleepDivId = i;
1200
1201         /* Default to slow, highest DPM level will be
1202          * set to PPSMC_DISPLAY_WATERMARK_LOW later.
1203          */
1204         if (data->update_up_hyst)
1205                 level->UpHyst = (uint8_t)data->up_hyst;
1206         if (data->update_down_hyst)
1207                 level->DownHyst = (uint8_t)data->down_hyst;
1208
1209         level->SclkSetting = curr_sclk_setting;
1210
1211         CONVERT_FROM_HOST_TO_SMC_UL(level->MinVoltage);
1212         CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm);
1213         CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm1);
1214         CONVERT_FROM_HOST_TO_SMC_US(level->ActivityLevel);
1215         CONVERT_FROM_HOST_TO_SMC_UL(level->SclkSetting.SclkFrequency);
1216         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_int);
1217         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_frac);
1218         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_fcw_int);
1219         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Sclk_slew_rate);
1220         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_up_slew_rate);
1221         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_down_slew_rate);
1222         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_int);
1223         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_frac);
1224         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Sclk_ss_slew_rate);
1225         return 0;
1226 }
1227
1228 /**
1229 * Populates all SMC SCLK levels' structure based on the trimmed allowed dpm engine clock states
1230 *
1231 * @param    hwmgr      the address of the hardware manager
1232 */
1233 static int polaris10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
1234 {
1235         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1236         struct polaris10_dpm_table *dpm_table = &data->dpm_table;
1237         struct phm_ppt_v1_information *table_info =
1238                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1239         struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
1240         uint8_t pcie_entry_cnt = (uint8_t) data->dpm_table.pcie_speed_table.count;
1241         int result = 0;
1242         uint32_t array = data->dpm_table_start +
1243                         offsetof(SMU74_Discrete_DpmTable, GraphicsLevel);
1244         uint32_t array_size = sizeof(struct SMU74_Discrete_GraphicsLevel) *
1245                         SMU74_MAX_LEVELS_GRAPHICS;
1246         struct SMU74_Discrete_GraphicsLevel *levels =
1247                         data->smc_state_table.GraphicsLevel;
1248         uint32_t i, max_entry;
1249         uint8_t hightest_pcie_level_enabled = 0,
1250                 lowest_pcie_level_enabled = 0,
1251                 mid_pcie_level_enabled = 0,
1252                 count = 0;
1253
1254         polaris10_get_sclk_range_table(hwmgr);
1255
1256         for (i = 0; i < dpm_table->sclk_table.count; i++) {
1257
1258                 result = polaris10_populate_single_graphic_level(hwmgr,
1259                                 dpm_table->sclk_table.dpm_levels[i].value,
1260                                 (uint16_t)data->activity_target[i],
1261                                 &(data->smc_state_table.GraphicsLevel[i]));
1262                 if (result)
1263                         return result;
1264
1265                 /* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */
1266                 if (i > 1)
1267                         levels[i].DeepSleepDivId = 0;
1268         }
1269         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1270                                         PHM_PlatformCaps_SPLLShutdownSupport))
1271                 data->smc_state_table.GraphicsLevel[0].SclkSetting.SSc_En = 0;
1272
1273         data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
1274         data->smc_state_table.GraphicsDpmLevelCount =
1275                         (uint8_t)dpm_table->sclk_table.count;
1276         data->dpm_level_enable_mask.sclk_dpm_enable_mask =
1277                         phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
1278
1279
1280         if (pcie_table != NULL) {
1281                 PP_ASSERT_WITH_CODE((1 <= pcie_entry_cnt),
1282                                 "There must be 1 or more PCIE levels defined in PPTable.",
1283                                 return -EINVAL);
1284                 max_entry = pcie_entry_cnt - 1;
1285                 for (i = 0; i < dpm_table->sclk_table.count; i++)
1286                         levels[i].pcieDpmLevel =
1287                                         (uint8_t) ((i < max_entry) ? i : max_entry);
1288         } else {
1289                 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
1290                                 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1291                                                 (1 << (hightest_pcie_level_enabled + 1))) != 0))
1292                         hightest_pcie_level_enabled++;
1293
1294                 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
1295                                 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1296                                                 (1 << lowest_pcie_level_enabled)) == 0))
1297                         lowest_pcie_level_enabled++;
1298
1299                 while ((count < hightest_pcie_level_enabled) &&
1300                                 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1301                                                 (1 << (lowest_pcie_level_enabled + 1 + count))) == 0))
1302                         count++;
1303
1304                 mid_pcie_level_enabled = (lowest_pcie_level_enabled + 1 + count) <
1305                                 hightest_pcie_level_enabled ?
1306                                                 (lowest_pcie_level_enabled + 1 + count) :
1307                                                 hightest_pcie_level_enabled;
1308
1309                 /* set pcieDpmLevel to hightest_pcie_level_enabled */
1310                 for (i = 2; i < dpm_table->sclk_table.count; i++)
1311                         levels[i].pcieDpmLevel = hightest_pcie_level_enabled;
1312
1313                 /* set pcieDpmLevel to lowest_pcie_level_enabled */
1314                 levels[0].pcieDpmLevel = lowest_pcie_level_enabled;
1315
1316                 /* set pcieDpmLevel to mid_pcie_level_enabled */
1317                 levels[1].pcieDpmLevel = mid_pcie_level_enabled;
1318         }
1319         /* level count will send to smc once at init smc table and never change */
1320         result = polaris10_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels,
1321                         (uint32_t)array_size, data->sram_end);
1322
1323         return result;
1324 }
1325
1326 static int polaris10_populate_single_memory_level(struct pp_hwmgr *hwmgr,
1327                 uint32_t clock, struct SMU74_Discrete_MemoryLevel *mem_level)
1328 {
1329         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1330         struct phm_ppt_v1_information *table_info =
1331                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1332         int result = 0;
1333         struct cgs_display_info info = {0, 0, NULL};
1334
1335         cgs_get_active_displays_info(hwmgr->device, &info);
1336
1337         if (table_info->vdd_dep_on_mclk) {
1338                 result = polaris10_get_dependency_volt_by_clk(hwmgr,
1339                                 table_info->vdd_dep_on_mclk, clock,
1340                                 &mem_level->MinVoltage, &mem_level->MinMvdd);
1341                 PP_ASSERT_WITH_CODE((0 == result),
1342                                 "can not find MinVddc voltage value from memory "
1343                                 "VDDC voltage dependency table", return result);
1344         }
1345
1346         mem_level->MclkFrequency = clock;
1347         mem_level->EnabledForThrottle = 1;
1348         mem_level->EnabledForActivity = 0;
1349         mem_level->UpHyst = 0;
1350         mem_level->DownHyst = 100;
1351         mem_level->VoltageDownHyst = 0;
1352         mem_level->ActivityLevel = (uint16_t)data->mclk_activity_target;
1353         mem_level->StutterEnable = false;
1354         mem_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
1355
1356         data->display_timing.num_existing_displays = info.display_count;
1357
1358         if ((data->mclk_stutter_mode_threshold) &&
1359                 (clock <= data->mclk_stutter_mode_threshold) &&
1360                 (PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL,
1361                                 STUTTER_ENABLE) & 0x1))
1362                 mem_level->StutterEnable = true;
1363
1364         if (!result) {
1365                 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinMvdd);
1366                 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MclkFrequency);
1367                 CONVERT_FROM_HOST_TO_SMC_US(mem_level->ActivityLevel);
1368                 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinVoltage);
1369         }
1370         return result;
1371 }
1372
1373 /**
1374 * Populates all SMC MCLK levels' structure based on the trimmed allowed dpm memory clock states
1375 *
1376 * @param    hwmgr      the address of the hardware manager
1377 */
1378 static int polaris10_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
1379 {
1380         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1381         struct polaris10_dpm_table *dpm_table = &data->dpm_table;
1382         int result;
1383         /* populate MCLK dpm table to SMU7 */
1384         uint32_t array = data->dpm_table_start +
1385                         offsetof(SMU74_Discrete_DpmTable, MemoryLevel);
1386         uint32_t array_size = sizeof(SMU74_Discrete_MemoryLevel) *
1387                         SMU74_MAX_LEVELS_MEMORY;
1388         struct SMU74_Discrete_MemoryLevel *levels =
1389                         data->smc_state_table.MemoryLevel;
1390         uint32_t i;
1391
1392         for (i = 0; i < dpm_table->mclk_table.count; i++) {
1393                 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),
1394                                 "can not populate memory level as memory clock is zero",
1395                                 return -EINVAL);
1396                 result = polaris10_populate_single_memory_level(hwmgr,
1397                                 dpm_table->mclk_table.dpm_levels[i].value,
1398                                 &levels[i]);
1399                 if (i == dpm_table->mclk_table.count - 1) {
1400                         levels[i].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH;
1401                         levels[i].EnabledForActivity = 1;
1402                 }
1403                 if (result)
1404                         return result;
1405         }
1406
1407         /* In order to prevent MC activity from stutter mode to push DPM up,
1408          * the UVD change complements this by putting the MCLK in
1409          * a higher state by default such that we are not affected by
1410          * up threshold or and MCLK DPM latency.
1411          */
1412         levels[0].ActivityLevel = 0x1f;
1413         CONVERT_FROM_HOST_TO_SMC_US(levels[0].ActivityLevel);
1414
1415         data->smc_state_table.MemoryDpmLevelCount =
1416                         (uint8_t)dpm_table->mclk_table.count;
1417         data->dpm_level_enable_mask.mclk_dpm_enable_mask =
1418                         phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
1419
1420         /* level count will send to smc once at init smc table and never change */
1421         result = polaris10_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels,
1422                         (uint32_t)array_size, data->sram_end);
1423
1424         return result;
1425 }
1426
1427 /**
1428 * Populates the SMC MVDD structure using the provided memory clock.
1429 *
1430 * @param    hwmgr      the address of the hardware manager
1431 * @param    mclk        the MCLK value to be used in the decision if MVDD should be high or low.
1432 * @param    voltage     the SMC VOLTAGE structure to be populated
1433 */
1434 int polaris10_populate_mvdd_value(struct pp_hwmgr *hwmgr,
1435                 uint32_t mclk, SMIO_Pattern *smio_pat)
1436 {
1437         const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1438         struct phm_ppt_v1_information *table_info =
1439                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1440         uint32_t i = 0;
1441
1442         if (POLARIS10_VOLTAGE_CONTROL_NONE != data->mvdd_control) {
1443                 /* find mvdd value which clock is more than request */
1444                 for (i = 0; i < table_info->vdd_dep_on_mclk->count; i++) {
1445                         if (mclk <= table_info->vdd_dep_on_mclk->entries[i].clk) {
1446                                 smio_pat->Voltage = data->mvdd_voltage_table.entries[i].value;
1447                                 break;
1448                         }
1449                 }
1450                 PP_ASSERT_WITH_CODE(i < table_info->vdd_dep_on_mclk->count,
1451                                 "MVDD Voltage is outside the supported range.",
1452                                 return -EINVAL);
1453         } else
1454                 return -EINVAL;
1455
1456         return 0;
1457 }
1458
1459 static int polaris10_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
1460                 SMU74_Discrete_DpmTable *table)
1461 {
1462         int result = 0;
1463         uint32_t sclk_frequency;
1464         const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1465         struct phm_ppt_v1_information *table_info =
1466                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1467         SMIO_Pattern vol_level;
1468         uint32_t mvdd;
1469         uint16_t us_mvdd;
1470
1471         table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
1472
1473         if (!data->sclk_dpm_key_disabled) {
1474                 /* Get MinVoltage and Frequency from DPM0,
1475                  * already converted to SMC_UL */
1476                 sclk_frequency = data->dpm_table.sclk_table.dpm_levels[0].value;
1477                 result = polaris10_get_dependency_volt_by_clk(hwmgr,
1478                                 table_info->vdd_dep_on_sclk,
1479                                 table->ACPILevel.SclkFrequency,
1480                                 &table->ACPILevel.MinVoltage, &mvdd);
1481                 PP_ASSERT_WITH_CODE((0 == result),
1482                                 "Cannot find ACPI VDDC voltage value "
1483                                 "in Clock Dependency Table", );
1484         } else {
1485                 sclk_frequency = data->vbios_boot_state.sclk_bootup_value;
1486                 table->ACPILevel.MinVoltage =
1487                                 data->vbios_boot_state.vddc_bootup_value * VOLTAGE_SCALE;
1488         }
1489
1490         result = polaris10_calculate_sclk_params(hwmgr, sclk_frequency,  &(table->ACPILevel.SclkSetting));
1491         PP_ASSERT_WITH_CODE(result == 0, "Error retrieving Engine Clock dividers from VBIOS.", return result);
1492
1493         table->ACPILevel.DeepSleepDivId = 0;
1494         table->ACPILevel.CcPwrDynRm = 0;
1495         table->ACPILevel.CcPwrDynRm1 = 0;
1496
1497         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);
1498         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.MinVoltage);
1499         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);
1500         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);
1501
1502         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkSetting.SclkFrequency);
1503         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_int);
1504         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_frac);
1505         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_fcw_int);
1506         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_slew_rate);
1507         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_up_slew_rate);
1508         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_down_slew_rate);
1509         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_int);
1510         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_frac);
1511         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_ss_slew_rate);
1512
1513         if (!data->mclk_dpm_key_disabled) {
1514                 /* Get MinVoltage and Frequency from DPM0, already converted to SMC_UL */
1515                 table->MemoryACPILevel.MclkFrequency =
1516                                 data->dpm_table.mclk_table.dpm_levels[0].value;
1517                 result = polaris10_get_dependency_volt_by_clk(hwmgr,
1518                                 table_info->vdd_dep_on_mclk,
1519                                 table->MemoryACPILevel.MclkFrequency,
1520                                 &table->MemoryACPILevel.MinVoltage, &mvdd);
1521                 PP_ASSERT_WITH_CODE((0 == result),
1522                                 "Cannot find ACPI VDDCI voltage value "
1523                                 "in Clock Dependency Table",
1524                                 );
1525         } else {
1526                 table->MemoryACPILevel.MclkFrequency =
1527                                 data->vbios_boot_state.mclk_bootup_value;
1528                 table->MemoryACPILevel.MinVoltage =
1529                                 data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE;
1530         }
1531
1532         us_mvdd = 0;
1533         if ((POLARIS10_VOLTAGE_CONTROL_NONE == data->mvdd_control) ||
1534                         (data->mclk_dpm_key_disabled))
1535                 us_mvdd = data->vbios_boot_state.mvdd_bootup_value;
1536         else {
1537                 if (!polaris10_populate_mvdd_value(hwmgr,
1538                                 data->dpm_table.mclk_table.dpm_levels[0].value,
1539                                 &vol_level))
1540                         us_mvdd = vol_level.Voltage;
1541         }
1542
1543         if (0 == polaris10_populate_mvdd_value(hwmgr, 0, &vol_level))
1544                 table->MemoryACPILevel.MinMvdd = PP_HOST_TO_SMC_UL(vol_level.Voltage);
1545         else
1546                 table->MemoryACPILevel.MinMvdd = 0;
1547
1548         table->MemoryACPILevel.StutterEnable = false;
1549
1550         table->MemoryACPILevel.EnabledForThrottle = 0;
1551         table->MemoryACPILevel.EnabledForActivity = 0;
1552         table->MemoryACPILevel.UpHyst = 0;
1553         table->MemoryACPILevel.DownHyst = 100;
1554         table->MemoryACPILevel.VoltageDownHyst = 0;
1555         table->MemoryACPILevel.ActivityLevel =
1556                         PP_HOST_TO_SMC_US((uint16_t)data->mclk_activity_target);
1557
1558         CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MclkFrequency);
1559         CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MinVoltage);
1560
1561         return result;
1562 }
1563
1564 static int polaris10_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
1565                 SMU74_Discrete_DpmTable *table)
1566 {
1567         int result = -EINVAL;
1568         uint8_t count;
1569         struct pp_atomctrl_clock_dividers_vi dividers;
1570         struct phm_ppt_v1_information *table_info =
1571                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1572         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1573                         table_info->mm_dep_table;
1574         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1575
1576         table->VceLevelCount = (uint8_t)(mm_table->count);
1577         table->VceBootLevel = 0;
1578
1579         for (count = 0; count < table->VceLevelCount; count++) {
1580                 table->VceLevel[count].Frequency = mm_table->entries[count].eclk;
1581                 table->VceLevel[count].MinVoltage = 0;
1582                 table->VceLevel[count].MinVoltage |=
1583                                 (mm_table->entries[count].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
1584                 table->VceLevel[count].MinVoltage |=
1585                                 ((mm_table->entries[count].vddc - data->vddc_vddci_delta) *
1586                                                 VOLTAGE_SCALE) << VDDCI_SHIFT;
1587                 table->VceLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1588
1589                 /*retrieve divider value for VBIOS */
1590                 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1591                                 table->VceLevel[count].Frequency, &dividers);
1592                 PP_ASSERT_WITH_CODE((0 == result),
1593                                 "can not find divide id for VCE engine clock",
1594                                 return result);
1595
1596                 table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1597
1598                 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency);
1599                 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].MinVoltage);
1600         }
1601         return result;
1602 }
1603
1604 static int polaris10_populate_smc_samu_level(struct pp_hwmgr *hwmgr,
1605                 SMU74_Discrete_DpmTable *table)
1606 {
1607         int result = -EINVAL;
1608         uint8_t count;
1609         struct pp_atomctrl_clock_dividers_vi dividers;
1610         struct phm_ppt_v1_information *table_info =
1611                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1612         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1613                         table_info->mm_dep_table;
1614         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1615
1616         table->SamuBootLevel = 0;
1617         table->SamuLevelCount = (uint8_t)(mm_table->count);
1618
1619         for (count = 0; count < table->SamuLevelCount; count++) {
1620                 /* not sure whether we need evclk or not */
1621                 table->SamuLevel[count].MinVoltage = 0;
1622                 table->SamuLevel[count].Frequency = mm_table->entries[count].samclock;
1623                 table->SamuLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
1624                                 VOLTAGE_SCALE) << VDDC_SHIFT;
1625                 table->SamuLevel[count].MinVoltage |= ((mm_table->entries[count].vddc -
1626                                 data->vddc_vddci_delta) * VOLTAGE_SCALE) << VDDCI_SHIFT;
1627                 table->SamuLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1628
1629                 /* retrieve divider value for VBIOS */
1630                 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1631                                 table->SamuLevel[count].Frequency, &dividers);
1632                 PP_ASSERT_WITH_CODE((0 == result),
1633                                 "can not find divide id for samu clock", return result);
1634
1635                 table->SamuLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1636
1637                 CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].Frequency);
1638                 CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].MinVoltage);
1639         }
1640         return result;
1641 }
1642
1643 static int polaris10_populate_memory_timing_parameters(struct pp_hwmgr *hwmgr,
1644                 int32_t eng_clock, int32_t mem_clock,
1645                 SMU74_Discrete_MCArbDramTimingTableEntry *arb_regs)
1646 {
1647         uint32_t dram_timing;
1648         uint32_t dram_timing2;
1649         uint32_t burst_time;
1650         int result;
1651
1652         result = atomctrl_set_engine_dram_timings_rv770(hwmgr,
1653                         eng_clock, mem_clock);
1654         PP_ASSERT_WITH_CODE(result == 0,
1655                         "Error calling VBIOS to set DRAM_TIMING.", return result);
1656
1657         dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
1658         dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
1659         burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
1660
1661
1662         arb_regs->McArbDramTiming  = PP_HOST_TO_SMC_UL(dram_timing);
1663         arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dram_timing2);
1664         arb_regs->McArbBurstTime   = (uint8_t)burst_time;
1665
1666         return 0;
1667 }
1668
1669 static int polaris10_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
1670 {
1671         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1672         struct SMU74_Discrete_MCArbDramTimingTable arb_regs;
1673         uint32_t i, j;
1674         int result = 0;
1675
1676         for (i = 0; i < data->dpm_table.sclk_table.count; i++) {
1677                 for (j = 0; j < data->dpm_table.mclk_table.count; j++) {
1678                         result = polaris10_populate_memory_timing_parameters(hwmgr,
1679                                         data->dpm_table.sclk_table.dpm_levels[i].value,
1680                                         data->dpm_table.mclk_table.dpm_levels[j].value,
1681                                         &arb_regs.entries[i][j]);
1682                         if (result == 0)
1683                                 result = atomctrl_set_ac_timing_ai(hwmgr, data->dpm_table.mclk_table.dpm_levels[j].value, j);
1684                         if (result != 0)
1685                                 return result;
1686                 }
1687         }
1688
1689         result = polaris10_copy_bytes_to_smc(
1690                         hwmgr->smumgr,
1691                         data->arb_table_start,
1692                         (uint8_t *)&arb_regs,
1693                         sizeof(SMU74_Discrete_MCArbDramTimingTable),
1694                         data->sram_end);
1695         return result;
1696 }
1697
1698 static int polaris10_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
1699                 struct SMU74_Discrete_DpmTable *table)
1700 {
1701         int result = -EINVAL;
1702         uint8_t count;
1703         struct pp_atomctrl_clock_dividers_vi dividers;
1704         struct phm_ppt_v1_information *table_info =
1705                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1706         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1707                         table_info->mm_dep_table;
1708         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1709
1710         table->UvdLevelCount = (uint8_t)(mm_table->count);
1711         table->UvdBootLevel = 0;
1712
1713         for (count = 0; count < table->UvdLevelCount; count++) {
1714                 table->UvdLevel[count].MinVoltage = 0;
1715                 table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk;
1716                 table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk;
1717                 table->UvdLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
1718                                 VOLTAGE_SCALE) << VDDC_SHIFT;
1719                 table->UvdLevel[count].MinVoltage |= ((mm_table->entries[count].vddc -
1720                                 data->vddc_vddci_delta) * VOLTAGE_SCALE) << VDDCI_SHIFT;
1721                 table->UvdLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1722
1723                 /* retrieve divider value for VBIOS */
1724                 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1725                                 table->UvdLevel[count].VclkFrequency, &dividers);
1726                 PP_ASSERT_WITH_CODE((0 == result),
1727                                 "can not find divide id for Vclk clock", return result);
1728
1729                 table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
1730
1731                 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1732                                 table->UvdLevel[count].DclkFrequency, &dividers);
1733                 PP_ASSERT_WITH_CODE((0 == result),
1734                                 "can not find divide id for Dclk clock", return result);
1735
1736                 table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;
1737
1738                 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency);
1739                 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency);
1740                 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].MinVoltage);
1741
1742         }
1743         return result;
1744 }
1745
1746 static int polaris10_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
1747                 struct SMU74_Discrete_DpmTable *table)
1748 {
1749         int result = 0;
1750         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1751
1752         table->GraphicsBootLevel = 0;
1753         table->MemoryBootLevel = 0;
1754
1755         /* find boot level from dpm table */
1756         result = phm_find_boot_level(&(data->dpm_table.sclk_table),
1757                         data->vbios_boot_state.sclk_bootup_value,
1758                         (uint32_t *)&(table->GraphicsBootLevel));
1759
1760         result = phm_find_boot_level(&(data->dpm_table.mclk_table),
1761                         data->vbios_boot_state.mclk_bootup_value,
1762                         (uint32_t *)&(table->MemoryBootLevel));
1763
1764         table->BootVddc  = data->vbios_boot_state.vddc_bootup_value *
1765                         VOLTAGE_SCALE;
1766         table->BootVddci = data->vbios_boot_state.vddci_bootup_value *
1767                         VOLTAGE_SCALE;
1768         table->BootMVdd  = data->vbios_boot_state.mvdd_bootup_value *
1769                         VOLTAGE_SCALE;
1770
1771         CONVERT_FROM_HOST_TO_SMC_US(table->BootVddc);
1772         CONVERT_FROM_HOST_TO_SMC_US(table->BootVddci);
1773         CONVERT_FROM_HOST_TO_SMC_US(table->BootMVdd);
1774
1775         return 0;
1776 }
1777
1778
1779 static int polaris10_populate_smc_initailial_state(struct pp_hwmgr *hwmgr)
1780 {
1781         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1782         struct phm_ppt_v1_information *table_info =
1783                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1784         uint8_t count, level;
1785
1786         count = (uint8_t)(table_info->vdd_dep_on_sclk->count);
1787
1788         for (level = 0; level < count; level++) {
1789                 if (table_info->vdd_dep_on_sclk->entries[level].clk >=
1790                                 data->vbios_boot_state.sclk_bootup_value) {
1791                         data->smc_state_table.GraphicsBootLevel = level;
1792                         break;
1793                 }
1794         }
1795
1796         count = (uint8_t)(table_info->vdd_dep_on_mclk->count);
1797         for (level = 0; level < count; level++) {
1798                 if (table_info->vdd_dep_on_mclk->entries[level].clk >=
1799                                 data->vbios_boot_state.mclk_bootup_value) {
1800                         data->smc_state_table.MemoryBootLevel = level;
1801                         break;
1802                 }
1803         }
1804
1805         return 0;
1806 }
1807
1808 static int polaris10_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
1809 {
1810         uint32_t ro, efuse, volt_without_cks, volt_with_cks, value, max, min;
1811         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1812         uint8_t i, stretch_amount, stretch_amount2, volt_offset = 0;
1813         struct phm_ppt_v1_information *table_info =
1814                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1815         struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
1816                         table_info->vdd_dep_on_sclk;
1817
1818         stretch_amount = (uint8_t)table_info->cac_dtp_table->usClockStretchAmount;
1819
1820         /* Read SMU_Eefuse to read and calculate RO and determine
1821          * if the part is SS or FF. if RO >= 1660MHz, part is FF.
1822          */
1823         efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1824                         ixSMU_EFUSE_0 + (67 * 4));
1825         efuse &= 0xFF000000;
1826         efuse = efuse >> 24;
1827
1828         if (hwmgr->chip_id == CHIP_POLARIS10) {
1829                 min = 1000;
1830                 max = 2300;
1831         } else {
1832                 min = 1100;
1833                 max = 2100;
1834         }
1835
1836         ro = efuse * (max -min)/255 + min;
1837
1838         /* Populate Sclk_CKS_masterEn0_7 and Sclk_voltageOffset */
1839         for (i = 0; i < sclk_table->count; i++) {
1840                 data->smc_state_table.Sclk_CKS_masterEn0_7 |=
1841                                 sclk_table->entries[i].cks_enable << i;
1842
1843                 volt_without_cks =  (uint32_t)(((ro - 40) * 1000 - 2753594 - sclk_table->entries[i].clk/100 * 136418 /1000) / \
1844                                         (sclk_table->entries[i].clk/100 * 1132925 /10000 - 242418)/100);
1845
1846                 volt_with_cks = (uint32_t)((ro * 1000 -2396351 - sclk_table->entries[i].clk/100 * 329021/1000) / \
1847                                 (sclk_table->entries[i].clk/10000 * 649434 /1000  - 18005)/10);
1848
1849                 if (volt_without_cks >= volt_with_cks)
1850                         volt_offset = (uint8_t)(((volt_without_cks - volt_with_cks +
1851                                         sclk_table->entries[i].cks_voffset) * 100 / 625) + 1);
1852
1853                 data->smc_state_table.Sclk_voltageOffset[i] = volt_offset;
1854         }
1855
1856         /* Populate CKS Lookup Table */
1857         if (stretch_amount == 1 || stretch_amount == 2 || stretch_amount == 5)
1858                 stretch_amount2 = 0;
1859         else if (stretch_amount == 3 || stretch_amount == 4)
1860                 stretch_amount2 = 1;
1861         else {
1862                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
1863                                 PHM_PlatformCaps_ClockStretcher);
1864                 PP_ASSERT_WITH_CODE(false,
1865                                 "Stretch Amount in PPTable not supported\n",
1866                                 return -EINVAL);
1867         }
1868
1869         value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL);
1870         value &= 0xFFFFFFFE;
1871         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL, value);
1872
1873         return 0;
1874 }
1875
1876 /**
1877 * Populates the SMC VRConfig field in DPM table.
1878 *
1879 * @param    hwmgr   the address of the hardware manager
1880 * @param    table   the SMC DPM table structure to be populated
1881 * @return   always 0
1882 */
1883 static int polaris10_populate_vr_config(struct pp_hwmgr *hwmgr,
1884                 struct SMU74_Discrete_DpmTable *table)
1885 {
1886         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1887         uint16_t config;
1888
1889         config = VR_MERGED_WITH_VDDC;
1890         table->VRConfig |= (config << VRCONF_VDDGFX_SHIFT);
1891
1892         /* Set Vddc Voltage Controller */
1893         if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
1894                 config = VR_SVI2_PLANE_1;
1895                 table->VRConfig |= config;
1896         } else {
1897                 PP_ASSERT_WITH_CODE(false,
1898                                 "VDDC should be on SVI2 control in merged mode!",
1899                                 );
1900         }
1901         /* Set Vddci Voltage Controller */
1902         if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
1903                 config = VR_SVI2_PLANE_2;  /* only in merged mode */
1904                 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1905         } else if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
1906                 config = VR_SMIO_PATTERN_1;
1907                 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1908         } else {
1909                 config = VR_STATIC_VOLTAGE;
1910                 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1911         }
1912         /* Set Mvdd Voltage Controller */
1913         if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
1914                 config = VR_SVI2_PLANE_2;
1915                 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
1916                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start +
1917                         offsetof(SMU74_SoftRegisters, AllowMvddSwitch), 0x1);
1918         } else {
1919                 config = VR_STATIC_VOLTAGE;
1920                 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
1921         }
1922
1923         return 0;
1924 }
1925
1926
1927 int polaris10_populate_avfs_parameters(struct pp_hwmgr *hwmgr)
1928 {
1929         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
1930         SMU74_Discrete_DpmTable  *table = &(data->smc_state_table);
1931         int result = 0;
1932         struct pp_atom_ctrl__avfs_parameters avfs_params = {0};
1933         AVFS_meanNsigma_t AVFS_meanNsigma = { {0} };
1934         AVFS_Sclk_Offset_t AVFS_SclkOffset = { {0} };
1935         uint32_t tmp, i;
1936         struct pp_smumgr *smumgr = hwmgr->smumgr;
1937         struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend);
1938
1939         struct phm_ppt_v1_information *table_info =
1940                         (struct phm_ppt_v1_information *)hwmgr->pptable;
1941         struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
1942                         table_info->vdd_dep_on_sclk;
1943
1944
1945         if (smu_data->avfs.avfs_btc_status == AVFS_BTC_NOTSUPPORTED)
1946                 return result;
1947
1948         result = atomctrl_get_avfs_information(hwmgr, &avfs_params);
1949
1950         if (0 == result) {
1951                 table->BTCGB_VDROOP_TABLE[0].a0  = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a0);
1952                 table->BTCGB_VDROOP_TABLE[0].a1  = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a1);
1953                 table->BTCGB_VDROOP_TABLE[0].a2  = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a2);
1954                 table->BTCGB_VDROOP_TABLE[1].a0  = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a0);
1955                 table->BTCGB_VDROOP_TABLE[1].a1  = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a1);
1956                 table->BTCGB_VDROOP_TABLE[1].a2  = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a2);
1957                 table->AVFSGB_VDROOP_TABLE[0].m1 = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_m1);
1958                 table->AVFSGB_VDROOP_TABLE[0].m2 = PP_HOST_TO_SMC_US(avfs_params.usAVFSGB_FUSE_TABLE_CKSON_m2);
1959                 table->AVFSGB_VDROOP_TABLE[0].b  = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_b);
1960                 table->AVFSGB_VDROOP_TABLE[0].m1_shift = 24;
1961                 table->AVFSGB_VDROOP_TABLE[0].m2_shift  = 12;
1962                 table->AVFSGB_VDROOP_TABLE[1].m1 = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_m1);
1963                 table->AVFSGB_VDROOP_TABLE[1].m2 = PP_HOST_TO_SMC_US(avfs_params.usAVFSGB_FUSE_TABLE_CKSOFF_m2);
1964                 table->AVFSGB_VDROOP_TABLE[1].b  = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_b);
1965                 table->AVFSGB_VDROOP_TABLE[1].m1_shift = 24;
1966                 table->AVFSGB_VDROOP_TABLE[1].m2_shift  = 12;
1967                 table->MaxVoltage                = PP_HOST_TO_SMC_US(avfs_params.usMaxVoltage_0_25mv);
1968                 AVFS_meanNsigma.Aconstant[0]      = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant0);
1969                 AVFS_meanNsigma.Aconstant[1]      = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant1);
1970                 AVFS_meanNsigma.Aconstant[2]      = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant2);
1971                 AVFS_meanNsigma.DC_tol_sigma      = PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_DC_tol_sigma);
1972                 AVFS_meanNsigma.Platform_mean     = PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_Platform_mean);
1973                 AVFS_meanNsigma.PSM_Age_CompFactor = PP_HOST_TO_SMC_US(avfs_params.usPSM_Age_ComFactor);
1974                 AVFS_meanNsigma.Platform_sigma     = PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_Platform_sigma);
1975
1976                 for (i = 0; i < NUM_VFT_COLUMNS; i++) {
1977                         AVFS_meanNsigma.Static_Voltage_Offset[i] = (uint8_t)(sclk_table->entries[i].cks_voffset * 100 / 625);
1978                         AVFS_SclkOffset.Sclk_Offset[i] = PP_HOST_TO_SMC_US((uint16_t)(sclk_table->entries[i].sclk_offset) / 100);
1979                 }
1980
1981                 result = polaris10_read_smc_sram_dword(smumgr,
1982                                 SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, AvfsMeanNSigma),
1983                                 &tmp, data->sram_end);
1984
1985                 polaris10_copy_bytes_to_smc(smumgr,
1986                                         tmp,
1987                                         (uint8_t *)&AVFS_meanNsigma,
1988                                         sizeof(AVFS_meanNsigma_t),
1989                                         data->sram_end);
1990
1991                 result = polaris10_read_smc_sram_dword(smumgr,
1992                                 SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, AvfsSclkOffsetTable),
1993                                 &tmp, data->sram_end);
1994                 polaris10_copy_bytes_to_smc(smumgr,
1995                                         tmp,
1996                                         (uint8_t *)&AVFS_SclkOffset,
1997                                         sizeof(AVFS_Sclk_Offset_t),
1998                                         data->sram_end);
1999
2000                 data->avfs_vdroop_override_setting = (avfs_params.ucEnableGB_VDROOP_TABLE_CKSON << BTCGB0_Vdroop_Enable_SHIFT) |
2001                                                 (avfs_params.ucEnableGB_VDROOP_TABLE_CKSOFF << BTCGB1_Vdroop_Enable_SHIFT) |
2002                                                 (avfs_params.ucEnableGB_FUSE_TABLE_CKSON << AVFSGB0_Vdroop_Enable_SHIFT) |
2003                                                 (avfs_params.ucEnableGB_FUSE_TABLE_CKSOFF << AVFSGB1_Vdroop_Enable_SHIFT);
2004                 data->apply_avfs_cks_off_voltage = (avfs_params.ucEnableApplyAVFS_CKS_OFF_Voltage == 1) ? true : false;
2005         }
2006         return result;
2007 }
2008
2009
2010 /**
2011 * Initializes the SMC table and uploads it
2012 *
2013 * @param    hwmgr  the address of the powerplay hardware manager.
2014 * @return   always 0
2015 */
2016 static int polaris10_init_smc_table(struct pp_hwmgr *hwmgr)
2017 {
2018         int result;
2019         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2020         struct phm_ppt_v1_information *table_info =
2021                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2022         struct SMU74_Discrete_DpmTable *table = &(data->smc_state_table);
2023         const struct polaris10_ulv_parm *ulv = &(data->ulv);
2024         uint8_t i;
2025         struct pp_atomctrl_gpio_pin_assignment gpio_pin;
2026         pp_atomctrl_clock_dividers_vi dividers;
2027
2028         result = polaris10_setup_default_dpm_tables(hwmgr);
2029         PP_ASSERT_WITH_CODE(0 == result,
2030                         "Failed to setup default DPM tables!", return result);
2031
2032         if (POLARIS10_VOLTAGE_CONTROL_NONE != data->voltage_control)
2033                 polaris10_populate_smc_voltage_tables(hwmgr, table);
2034
2035         table->SystemFlags = 0;
2036         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2037                         PHM_PlatformCaps_AutomaticDCTransition))
2038                 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
2039
2040         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2041                         PHM_PlatformCaps_StepVddc))
2042                 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
2043
2044         if (data->is_memory_gddr5)
2045                 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
2046
2047         if (ulv->ulv_supported && table_info->us_ulv_voltage_offset) {
2048                 result = polaris10_populate_ulv_state(hwmgr, table);
2049                 PP_ASSERT_WITH_CODE(0 == result,
2050                                 "Failed to initialize ULV state!", return result);
2051                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2052                                 ixCG_ULV_PARAMETER, PPPOLARIS10_CGULVPARAMETER_DFLT);
2053         }
2054
2055         result = polaris10_populate_smc_link_level(hwmgr, table);
2056         PP_ASSERT_WITH_CODE(0 == result,
2057                         "Failed to initialize Link Level!", return result);
2058
2059         result = polaris10_populate_all_graphic_levels(hwmgr);
2060         PP_ASSERT_WITH_CODE(0 == result,
2061                         "Failed to initialize Graphics Level!", return result);
2062
2063         result = polaris10_populate_all_memory_levels(hwmgr);
2064         PP_ASSERT_WITH_CODE(0 == result,
2065                         "Failed to initialize Memory Level!", return result);
2066
2067         result = polaris10_populate_smc_acpi_level(hwmgr, table);
2068         PP_ASSERT_WITH_CODE(0 == result,
2069                         "Failed to initialize ACPI Level!", return result);
2070
2071         result = polaris10_populate_smc_vce_level(hwmgr, table);
2072         PP_ASSERT_WITH_CODE(0 == result,
2073                         "Failed to initialize VCE Level!", return result);
2074
2075         result = polaris10_populate_smc_samu_level(hwmgr, table);
2076         PP_ASSERT_WITH_CODE(0 == result,
2077                         "Failed to initialize SAMU Level!", return result);
2078
2079         /* Since only the initial state is completely set up at this point
2080          * (the other states are just copies of the boot state) we only
2081          * need to populate the  ARB settings for the initial state.
2082          */
2083         result = polaris10_program_memory_timing_parameters(hwmgr);
2084         PP_ASSERT_WITH_CODE(0 == result,
2085                         "Failed to Write ARB settings for the initial state.", return result);
2086
2087         result = polaris10_populate_smc_uvd_level(hwmgr, table);
2088         PP_ASSERT_WITH_CODE(0 == result,
2089                         "Failed to initialize UVD Level!", return result);
2090
2091         result = polaris10_populate_smc_boot_level(hwmgr, table);
2092         PP_ASSERT_WITH_CODE(0 == result,
2093                         "Failed to initialize Boot Level!", return result);
2094
2095         result = polaris10_populate_smc_initailial_state(hwmgr);
2096         PP_ASSERT_WITH_CODE(0 == result,
2097                         "Failed to initialize Boot State!", return result);
2098
2099         result = polaris10_populate_bapm_parameters_in_dpm_table(hwmgr);
2100         PP_ASSERT_WITH_CODE(0 == result,
2101                         "Failed to populate BAPM Parameters!", return result);
2102
2103         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2104                         PHM_PlatformCaps_ClockStretcher)) {
2105                 result = polaris10_populate_clock_stretcher_data_table(hwmgr);
2106                 PP_ASSERT_WITH_CODE(0 == result,
2107                                 "Failed to populate Clock Stretcher Data Table!",
2108                                 return result);
2109         }
2110
2111         result = polaris10_populate_avfs_parameters(hwmgr);
2112         PP_ASSERT_WITH_CODE(0 == result, "Failed to populate AVFS Parameters!", return result;);
2113
2114         table->CurrSclkPllRange = 0xff;
2115         table->GraphicsVoltageChangeEnable  = 1;
2116         table->GraphicsThermThrottleEnable  = 1;
2117         table->GraphicsInterval = 1;
2118         table->VoltageInterval  = 1;
2119         table->ThermalInterval  = 1;
2120         table->TemperatureLimitHigh =
2121                         table_info->cac_dtp_table->usTargetOperatingTemp *
2122                         POLARIS10_Q88_FORMAT_CONVERSION_UNIT;
2123         table->TemperatureLimitLow  =
2124                         (table_info->cac_dtp_table->usTargetOperatingTemp - 1) *
2125                         POLARIS10_Q88_FORMAT_CONVERSION_UNIT;
2126         table->MemoryVoltageChangeEnable = 1;
2127         table->MemoryInterval = 1;
2128         table->VoltageResponseTime = 0;
2129         table->PhaseResponseTime = 0;
2130         table->MemoryThermThrottleEnable = 1;
2131         table->PCIeBootLinkLevel = 0;
2132         table->PCIeGenInterval = 1;
2133         table->VRConfig = 0;
2134
2135         result = polaris10_populate_vr_config(hwmgr, table);
2136         PP_ASSERT_WITH_CODE(0 == result,
2137                         "Failed to populate VRConfig setting!", return result);
2138
2139         table->ThermGpio = 17;
2140         table->SclkStepSize = 0x4000;
2141
2142         if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_VRHOT_GPIO_PINID, &gpio_pin)) {
2143                 table->VRHotGpio = gpio_pin.uc_gpio_pin_bit_shift;
2144         } else {
2145                 table->VRHotGpio = POLARIS10_UNUSED_GPIO_PIN;
2146                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2147                                 PHM_PlatformCaps_RegulatorHot);
2148         }
2149
2150         if (atomctrl_get_pp_assign_pin(hwmgr, PP_AC_DC_SWITCH_GPIO_PINID,
2151                         &gpio_pin)) {
2152                 table->AcDcGpio = gpio_pin.uc_gpio_pin_bit_shift;
2153                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2154                                 PHM_PlatformCaps_AutomaticDCTransition);
2155         } else {
2156                 table->AcDcGpio = POLARIS10_UNUSED_GPIO_PIN;
2157                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2158                                 PHM_PlatformCaps_AutomaticDCTransition);
2159         }
2160
2161         /* Thermal Output GPIO */
2162         if (atomctrl_get_pp_assign_pin(hwmgr, THERMAL_INT_OUTPUT_GPIO_PINID,
2163                         &gpio_pin)) {
2164                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2165                                 PHM_PlatformCaps_ThermalOutGPIO);
2166
2167                 table->ThermOutGpio = gpio_pin.uc_gpio_pin_bit_shift;
2168
2169                 /* For porlarity read GPIOPAD_A with assigned Gpio pin
2170                  * since VBIOS will program this register to set 'inactive state',
2171                  * driver can then determine 'active state' from this and
2172                  * program SMU with correct polarity
2173                  */
2174                 table->ThermOutPolarity = (0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A)
2175                                         & (1 << gpio_pin.uc_gpio_pin_bit_shift))) ? 1:0;
2176                 table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_ONLY;
2177
2178                 /* if required, combine VRHot/PCC with thermal out GPIO */
2179                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_RegulatorHot)
2180                 && phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_CombinePCCWithThermalSignal))
2181                         table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_VRHOT;
2182         } else {
2183                 table->ThermOutGpio = 17;
2184                 table->ThermOutPolarity = 1;
2185                 table->ThermOutMode = SMU7_THERM_OUT_MODE_DISABLE;
2186         }
2187
2188         /* Populate BIF_SCLK levels into SMC DPM table */
2189         for (i = 0; i <= data->dpm_table.pcie_speed_table.count; i++) {
2190                 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, data->bif_sclk_table[i], &dividers);
2191                 PP_ASSERT_WITH_CODE((result == 0), "Can not find DFS divide id for Sclk", return result);
2192
2193                 if (i == 0)
2194                         table->Ulv.BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider));
2195                 else
2196                         table->LinkLevel[i-1].BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider));
2197         }
2198
2199         for (i = 0; i < SMU74_MAX_ENTRIES_SMIO; i++)
2200                 table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]);
2201
2202         CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags);
2203         CONVERT_FROM_HOST_TO_SMC_UL(table->VRConfig);
2204         CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask1);
2205         CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask2);
2206         CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize);
2207         CONVERT_FROM_HOST_TO_SMC_UL(table->CurrSclkPllRange);
2208         CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh);
2209         CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow);
2210         CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime);
2211         CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);
2212
2213         /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
2214         result = polaris10_copy_bytes_to_smc(hwmgr->smumgr,
2215                         data->dpm_table_start +
2216                         offsetof(SMU74_Discrete_DpmTable, SystemFlags),
2217                         (uint8_t *)&(table->SystemFlags),
2218                         sizeof(SMU74_Discrete_DpmTable) - 3 * sizeof(SMU74_PIDController),
2219                         data->sram_end);
2220         PP_ASSERT_WITH_CODE(0 == result,
2221                         "Failed to upload dpm data to SMC memory!", return result);
2222
2223         return 0;
2224 }
2225
2226 /**
2227 * Initialize the ARB DRAM timing table's index field.
2228 *
2229 * @param    hwmgr  the address of the powerplay hardware manager.
2230 * @return   always 0
2231 */
2232 static int polaris10_init_arb_table_index(struct pp_hwmgr *hwmgr)
2233 {
2234         const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2235         uint32_t tmp;
2236         int result;
2237
2238         /* This is a read-modify-write on the first byte of the ARB table.
2239          * The first byte in the SMU73_Discrete_MCArbDramTimingTable structure
2240          * is the field 'current'.
2241          * This solution is ugly, but we never write the whole table only
2242          * individual fields in it.
2243          * In reality this field should not be in that structure
2244          * but in a soft register.
2245          */
2246         result = polaris10_read_smc_sram_dword(hwmgr->smumgr,
2247                         data->arb_table_start, &tmp, data->sram_end);
2248
2249         if (result)
2250                 return result;
2251
2252         tmp &= 0x00FFFFFF;
2253         tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24;
2254
2255         return polaris10_write_smc_sram_dword(hwmgr->smumgr,
2256                         data->arb_table_start, tmp, data->sram_end);
2257 }
2258
2259 static int polaris10_enable_vrhot_gpio_interrupt(struct pp_hwmgr *hwmgr)
2260 {
2261         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2262                         PHM_PlatformCaps_RegulatorHot))
2263                 return smum_send_msg_to_smc(hwmgr->smumgr,
2264                                 PPSMC_MSG_EnableVRHotGPIOInterrupt);
2265
2266         return 0;
2267 }
2268
2269 static int polaris10_enable_sclk_control(struct pp_hwmgr *hwmgr)
2270 {
2271         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
2272                         SCLK_PWRMGT_OFF, 0);
2273         return 0;
2274 }
2275
2276 static int polaris10_enable_ulv(struct pp_hwmgr *hwmgr)
2277 {
2278         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2279         struct polaris10_ulv_parm *ulv = &(data->ulv);
2280
2281         if (ulv->ulv_supported)
2282                 return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_EnableULV);
2283
2284         return 0;
2285 }
2286
2287 static int polaris10_disable_ulv(struct pp_hwmgr *hwmgr)
2288 {
2289         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2290         struct polaris10_ulv_parm *ulv = &(data->ulv);
2291
2292         if (ulv->ulv_supported)
2293                 return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_DisableULV);
2294
2295         return 0;
2296 }
2297
2298 static int polaris10_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
2299 {
2300         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2301                         PHM_PlatformCaps_SclkDeepSleep)) {
2302                 if (smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_MASTER_DeepSleep_ON))
2303                         PP_ASSERT_WITH_CODE(false,
2304                                         "Attempt to enable Master Deep Sleep switch failed!",
2305                                         return -1);
2306         } else {
2307                 if (smum_send_msg_to_smc(hwmgr->smumgr,
2308                                 PPSMC_MSG_MASTER_DeepSleep_OFF)) {
2309                         PP_ASSERT_WITH_CODE(false,
2310                                         "Attempt to disable Master Deep Sleep switch failed!",
2311                                         return -1);
2312                 }
2313         }
2314
2315         return 0;
2316 }
2317
2318 static int polaris10_disable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
2319 {
2320         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2321                         PHM_PlatformCaps_SclkDeepSleep)) {
2322                 if (smum_send_msg_to_smc(hwmgr->smumgr,
2323                                 PPSMC_MSG_MASTER_DeepSleep_OFF)) {
2324                         PP_ASSERT_WITH_CODE(false,
2325                                         "Attempt to disable Master Deep Sleep switch failed!",
2326                                         return -1);
2327                 }
2328         }
2329
2330         return 0;
2331 }
2332
2333 static int polaris10_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
2334 {
2335         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2336         uint32_t soft_register_value = 0;
2337         uint32_t handshake_disables_offset = data->soft_regs_start
2338                                 + offsetof(SMU74_SoftRegisters, HandshakeDisables);
2339
2340         /* enable SCLK dpm */
2341         if (!data->sclk_dpm_key_disabled)
2342                 PP_ASSERT_WITH_CODE(
2343                 (0 == smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_DPM_Enable)),
2344                 "Failed to enable SCLK DPM during DPM Start Function!",
2345                 return -1);
2346
2347         /* enable MCLK dpm */
2348         if (0 == data->mclk_dpm_key_disabled) {
2349 /* Disable UVD - SMU handshake for MCLK. */
2350                 soft_register_value = cgs_read_ind_register(hwmgr->device,
2351                                         CGS_IND_REG__SMC, handshake_disables_offset);
2352                 soft_register_value |= SMU7_UVD_MCLK_HANDSHAKE_DISABLE;
2353                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2354                                 handshake_disables_offset, soft_register_value);
2355
2356                 PP_ASSERT_WITH_CODE(
2357                                 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
2358                                                 PPSMC_MSG_MCLKDPM_Enable)),
2359                                 "Failed to enable MCLK DPM during DPM Start Function!",
2360                                 return -1);
2361
2362                 PHM_WRITE_FIELD(hwmgr->device, MC_SEQ_CNTL_3, CAC_EN, 0x1);
2363
2364                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x5);
2365                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x5);
2366                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x100005);
2367                 udelay(10);
2368                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x400005);
2369                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x400005);
2370                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x500005);
2371         }
2372
2373         return 0;
2374 }
2375
2376 static int polaris10_start_dpm(struct pp_hwmgr *hwmgr)
2377 {
2378         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2379
2380         /*enable general power management */
2381
2382         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
2383                         GLOBAL_PWRMGT_EN, 1);
2384
2385         /* enable sclk deep sleep */
2386
2387         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
2388                         DYNAMIC_PM_EN, 1);
2389
2390         /* prepare for PCIE DPM */
2391
2392         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2393                         data->soft_regs_start + offsetof(SMU74_SoftRegisters,
2394                                         VoltageChangeTimeout), 0x1000);
2395         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
2396                         SWRST_COMMAND_1, RESETLC, 0x0);
2397 /*
2398         PP_ASSERT_WITH_CODE(
2399                         (0 == smum_send_msg_to_smc(hwmgr->smumgr,
2400                                         PPSMC_MSG_Voltage_Cntl_Enable)),
2401                         "Failed to enable voltage DPM during DPM Start Function!",
2402                         return -1);
2403 */
2404
2405         if (polaris10_enable_sclk_mclk_dpm(hwmgr)) {
2406                 printk(KERN_ERR "Failed to enable Sclk DPM and Mclk DPM!");
2407                 return -1;
2408         }
2409
2410         /* enable PCIE dpm */
2411         if (0 == data->pcie_dpm_key_disabled) {
2412                 PP_ASSERT_WITH_CODE(
2413                                 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
2414                                                 PPSMC_MSG_PCIeDPM_Enable)),
2415                                 "Failed to enable pcie DPM during DPM Start Function!",
2416                                 return -1);
2417         }
2418
2419         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2420                                 PHM_PlatformCaps_Falcon_QuickTransition)) {
2421                 PP_ASSERT_WITH_CODE((0 == smum_send_msg_to_smc(hwmgr->smumgr,
2422                                 PPSMC_MSG_EnableACDCGPIOInterrupt)),
2423                                 "Failed to enable AC DC GPIO Interrupt!",
2424                                 );
2425         }
2426
2427         return 0;
2428 }
2429
2430 static int polaris10_disable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
2431 {
2432         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2433
2434         /* disable SCLK dpm */
2435         if (!data->sclk_dpm_key_disabled)
2436                 PP_ASSERT_WITH_CODE(
2437                                 (smum_send_msg_to_smc(hwmgr->smumgr,
2438                                                 PPSMC_MSG_DPM_Disable) == 0),
2439                                 "Failed to disable SCLK DPM!",
2440                                 return -1);
2441
2442         /* disable MCLK dpm */
2443         if (!data->mclk_dpm_key_disabled) {
2444                 PP_ASSERT_WITH_CODE(
2445                                 (smum_send_msg_to_smc(hwmgr->smumgr,
2446                                                 PPSMC_MSG_MCLKDPM_Disable) == 0),
2447                                 "Failed to disable MCLK DPM!",
2448                                 return -1);
2449         }
2450
2451         return 0;
2452 }
2453
2454 static int polaris10_stop_dpm(struct pp_hwmgr *hwmgr)
2455 {
2456         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2457
2458         /* disable general power management */
2459         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
2460                         GLOBAL_PWRMGT_EN, 0);
2461         /* disable sclk deep sleep */
2462         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
2463                         DYNAMIC_PM_EN, 0);
2464
2465         /* disable PCIE dpm */
2466         if (!data->pcie_dpm_key_disabled) {
2467                 PP_ASSERT_WITH_CODE(
2468                                 (smum_send_msg_to_smc(hwmgr->smumgr,
2469                                                 PPSMC_MSG_PCIeDPM_Disable) == 0),
2470                                 "Failed to disable pcie DPM during DPM Stop Function!",
2471                                 return -1);
2472         }
2473
2474         if (polaris10_disable_sclk_mclk_dpm(hwmgr)) {
2475                 printk(KERN_ERR "Failed to disable Sclk DPM and Mclk DPM!");
2476                 return -1;
2477         }
2478
2479         return 0;
2480 }
2481
2482 static void polaris10_set_dpm_event_sources(struct pp_hwmgr *hwmgr, uint32_t sources)
2483 {
2484         bool protection;
2485         enum DPM_EVENT_SRC src;
2486
2487         switch (sources) {
2488         default:
2489                 printk(KERN_ERR "Unknown throttling event sources.");
2490                 /* fall through */
2491         case 0:
2492                 protection = false;
2493                 /* src is unused */
2494                 break;
2495         case (1 << PHM_AutoThrottleSource_Thermal):
2496                 protection = true;
2497                 src = DPM_EVENT_SRC_DIGITAL;
2498                 break;
2499         case (1 << PHM_AutoThrottleSource_External):
2500                 protection = true;
2501                 src = DPM_EVENT_SRC_EXTERNAL;
2502                 break;
2503         case (1 << PHM_AutoThrottleSource_External) |
2504                         (1 << PHM_AutoThrottleSource_Thermal):
2505                 protection = true;
2506                 src = DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL;
2507                 break;
2508         }
2509         /* Order matters - don't enable thermal protection for the wrong source. */
2510         if (protection) {
2511                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_THERMAL_CTRL,
2512                                 DPM_EVENT_SRC, src);
2513                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
2514                                 THERMAL_PROTECTION_DIS,
2515                                 !phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2516                                                 PHM_PlatformCaps_ThermalController));
2517         } else
2518                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
2519                                 THERMAL_PROTECTION_DIS, 1);
2520 }
2521
2522 static int polaris10_enable_auto_throttle_source(struct pp_hwmgr *hwmgr,
2523                 PHM_AutoThrottleSource source)
2524 {
2525         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2526
2527         if (!(data->active_auto_throttle_sources & (1 << source))) {
2528                 data->active_auto_throttle_sources |= 1 << source;
2529                 polaris10_set_dpm_event_sources(hwmgr, data->active_auto_throttle_sources);
2530         }
2531         return 0;
2532 }
2533
2534 static int polaris10_enable_thermal_auto_throttle(struct pp_hwmgr *hwmgr)
2535 {
2536         return polaris10_enable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal);
2537 }
2538
2539 static int polaris10_disable_auto_throttle_source(struct pp_hwmgr *hwmgr,
2540                 PHM_AutoThrottleSource source)
2541 {
2542         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2543
2544         if (data->active_auto_throttle_sources & (1 << source)) {
2545                 data->active_auto_throttle_sources &= ~(1 << source);
2546                 polaris10_set_dpm_event_sources(hwmgr, data->active_auto_throttle_sources);
2547         }
2548         return 0;
2549 }
2550
2551 static int polaris10_disable_thermal_auto_throttle(struct pp_hwmgr *hwmgr)
2552 {
2553         return polaris10_disable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal);
2554 }
2555
2556 int polaris10_pcie_performance_request(struct pp_hwmgr *hwmgr)
2557 {
2558         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2559         data->pcie_performance_request = true;
2560
2561         return 0;
2562 }
2563
2564 int polaris10_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
2565 {
2566         int tmp_result, result = 0;
2567         tmp_result = (!polaris10_is_dpm_running(hwmgr)) ? 0 : -1;
2568         PP_ASSERT_WITH_CODE(result == 0,
2569                         "DPM is already running right now, no need to enable DPM!",
2570                         return 0);
2571
2572         if (polaris10_voltage_control(hwmgr)) {
2573                 tmp_result = polaris10_enable_voltage_control(hwmgr);
2574                 PP_ASSERT_WITH_CODE(tmp_result == 0,
2575                                 "Failed to enable voltage control!",
2576                                 result = tmp_result);
2577
2578                 tmp_result = polaris10_construct_voltage_tables(hwmgr);
2579                 PP_ASSERT_WITH_CODE((0 == tmp_result),
2580                                 "Failed to contruct voltage tables!",
2581                                 result = tmp_result);
2582         }
2583
2584         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2585                         PHM_PlatformCaps_EngineSpreadSpectrumSupport))
2586                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
2587                                 GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, 1);
2588
2589         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2590                         PHM_PlatformCaps_ThermalController))
2591                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
2592                                 GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, 0);
2593
2594         tmp_result = polaris10_program_static_screen_threshold_parameters(hwmgr);
2595         PP_ASSERT_WITH_CODE((0 == tmp_result),
2596                         "Failed to program static screen threshold parameters!",
2597                         result = tmp_result);
2598
2599         tmp_result = polaris10_enable_display_gap(hwmgr);
2600         PP_ASSERT_WITH_CODE((0 == tmp_result),
2601                         "Failed to enable display gap!", result = tmp_result);
2602
2603         tmp_result = polaris10_program_voting_clients(hwmgr);
2604         PP_ASSERT_WITH_CODE((0 == tmp_result),
2605                         "Failed to program voting clients!", result = tmp_result);
2606
2607         tmp_result = polaris10_process_firmware_header(hwmgr);
2608         PP_ASSERT_WITH_CODE((0 == tmp_result),
2609                         "Failed to process firmware header!", result = tmp_result);
2610
2611         tmp_result = polaris10_initial_switch_from_arbf0_to_f1(hwmgr);
2612         PP_ASSERT_WITH_CODE((0 == tmp_result),
2613                         "Failed to initialize switch from ArbF0 to F1!",
2614                         result = tmp_result);
2615
2616         tmp_result = polaris10_init_smc_table(hwmgr);
2617         PP_ASSERT_WITH_CODE((0 == tmp_result),
2618                         "Failed to initialize SMC table!", result = tmp_result);
2619
2620         tmp_result = polaris10_init_arb_table_index(hwmgr);
2621         PP_ASSERT_WITH_CODE((0 == tmp_result),
2622                         "Failed to initialize ARB table index!", result = tmp_result);
2623
2624         tmp_result = polaris10_populate_pm_fuses(hwmgr);
2625         PP_ASSERT_WITH_CODE((0 == tmp_result),
2626                         "Failed to populate PM fuses!", result = tmp_result);
2627
2628         tmp_result = polaris10_enable_vrhot_gpio_interrupt(hwmgr);
2629         PP_ASSERT_WITH_CODE((0 == tmp_result),
2630                         "Failed to enable VR hot GPIO interrupt!", result = tmp_result);
2631
2632         tmp_result = polaris10_enable_sclk_control(hwmgr);
2633         PP_ASSERT_WITH_CODE((0 == tmp_result),
2634                         "Failed to enable SCLK control!", result = tmp_result);
2635
2636         tmp_result = polaris10_enable_smc_voltage_controller(hwmgr);
2637         PP_ASSERT_WITH_CODE((0 == tmp_result),
2638                         "Failed to enable voltage control!", result = tmp_result);
2639
2640         tmp_result = polaris10_enable_ulv(hwmgr);
2641         PP_ASSERT_WITH_CODE((0 == tmp_result),
2642                         "Failed to enable ULV!", result = tmp_result);
2643
2644         tmp_result = polaris10_enable_deep_sleep_master_switch(hwmgr);
2645         PP_ASSERT_WITH_CODE((0 == tmp_result),
2646                         "Failed to enable deep sleep master switch!", result = tmp_result);
2647
2648         tmp_result = polaris10_start_dpm(hwmgr);
2649         PP_ASSERT_WITH_CODE((0 == tmp_result),
2650                         "Failed to start DPM!", result = tmp_result);
2651
2652         tmp_result = polaris10_enable_smc_cac(hwmgr);
2653         PP_ASSERT_WITH_CODE((0 == tmp_result),
2654                         "Failed to enable SMC CAC!", result = tmp_result);
2655
2656         tmp_result = polaris10_enable_power_containment(hwmgr);
2657         PP_ASSERT_WITH_CODE((0 == tmp_result),
2658                         "Failed to enable power containment!", result = tmp_result);
2659
2660         tmp_result = polaris10_power_control_set_level(hwmgr);
2661         PP_ASSERT_WITH_CODE((0 == tmp_result),
2662                         "Failed to power control set level!", result = tmp_result);
2663
2664         tmp_result = polaris10_enable_thermal_auto_throttle(hwmgr);
2665         PP_ASSERT_WITH_CODE((0 == tmp_result),
2666                         "Failed to enable thermal auto throttle!", result = tmp_result);
2667
2668         tmp_result = polaris10_pcie_performance_request(hwmgr);
2669         PP_ASSERT_WITH_CODE((0 == tmp_result),
2670                         "pcie performance request failed!", result = tmp_result);
2671
2672         return result;
2673 }
2674
2675 int polaris10_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
2676 {
2677         int tmp_result, result = 0;
2678
2679         tmp_result = (polaris10_is_dpm_running(hwmgr)) ? 0 : -1;
2680         PP_ASSERT_WITH_CODE(tmp_result == 0,
2681                         "DPM is not running right now, no need to disable DPM!",
2682                         return 0);
2683
2684         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2685                         PHM_PlatformCaps_ThermalController))
2686                 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
2687                                 GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, 1);
2688
2689         tmp_result = polaris10_disable_power_containment(hwmgr);
2690         PP_ASSERT_WITH_CODE((tmp_result == 0),
2691                         "Failed to disable power containment!", result = tmp_result);
2692
2693         tmp_result = polaris10_disable_smc_cac(hwmgr);
2694         PP_ASSERT_WITH_CODE((tmp_result == 0),
2695                         "Failed to disable SMC CAC!", result = tmp_result);
2696
2697         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
2698                         CG_SPLL_SPREAD_SPECTRUM, SSEN, 0);
2699         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
2700                         GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, 0);
2701
2702         tmp_result = polaris10_disable_thermal_auto_throttle(hwmgr);
2703         PP_ASSERT_WITH_CODE((tmp_result == 0),
2704                         "Failed to disable thermal auto throttle!", result = tmp_result);
2705
2706         tmp_result = polaris10_stop_dpm(hwmgr);
2707         PP_ASSERT_WITH_CODE((tmp_result == 0),
2708                         "Failed to stop DPM!", result = tmp_result);
2709
2710         tmp_result = polaris10_disable_deep_sleep_master_switch(hwmgr);
2711         PP_ASSERT_WITH_CODE((tmp_result == 0),
2712                         "Failed to disable deep sleep master switch!", result = tmp_result);
2713
2714         tmp_result = polaris10_disable_ulv(hwmgr);
2715         PP_ASSERT_WITH_CODE((tmp_result == 0),
2716                         "Failed to disable ULV!", result = tmp_result);
2717
2718         tmp_result = polaris10_clear_voting_clients(hwmgr);
2719         PP_ASSERT_WITH_CODE((tmp_result == 0),
2720                         "Failed to clear voting clients!", result = tmp_result);
2721
2722         tmp_result = polaris10_reset_to_default(hwmgr);
2723         PP_ASSERT_WITH_CODE((tmp_result == 0),
2724                         "Failed to reset to default!", result = tmp_result);
2725
2726         tmp_result = polaris10_force_switch_to_arbf0(hwmgr);
2727         PP_ASSERT_WITH_CODE((tmp_result == 0),
2728                         "Failed to force to switch arbf0!", result = tmp_result);
2729
2730         return result;
2731 }
2732
2733 int polaris10_reset_asic_tasks(struct pp_hwmgr *hwmgr)
2734 {
2735
2736         return 0;
2737 }
2738
2739 int polaris10_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
2740 {
2741         return phm_hwmgr_backend_fini(hwmgr);
2742 }
2743
2744 int polaris10_set_features_platform_caps(struct pp_hwmgr *hwmgr)
2745 {
2746         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2747
2748         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2749                         PHM_PlatformCaps_SclkDeepSleep);
2750
2751         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2752                 PHM_PlatformCaps_DynamicPatchPowerState);
2753
2754         if (data->mvdd_control == POLARIS10_VOLTAGE_CONTROL_NONE)
2755                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2756                                 PHM_PlatformCaps_EnableMVDDControl);
2757
2758         if (data->vddci_control == POLARIS10_VOLTAGE_CONTROL_NONE)
2759                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2760                                 PHM_PlatformCaps_ControlVDDCI);
2761
2762         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2763                          PHM_PlatformCaps_TablelessHardwareInterface);
2764
2765         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2766                         PHM_PlatformCaps_EnableSMU7ThermalManagement);
2767
2768         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2769                         PHM_PlatformCaps_DynamicPowerManagement);
2770
2771         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2772                         PHM_PlatformCaps_UnTabledHardwareInterface);
2773
2774         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2775                         PHM_PlatformCaps_TablelessHardwareInterface);
2776
2777         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2778                                         PHM_PlatformCaps_SMC);
2779
2780         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2781                                         PHM_PlatformCaps_NonABMSupportInPPLib);
2782
2783         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2784                                         PHM_PlatformCaps_DynamicUVDState);
2785
2786         /* power tune caps Assume disabled */
2787         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2788                                                 PHM_PlatformCaps_SQRamping);
2789         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2790                                                 PHM_PlatformCaps_DBRamping);
2791         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2792                                                 PHM_PlatformCaps_TDRamping);
2793         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2794                                                 PHM_PlatformCaps_TCPRamping);
2795
2796         if (hwmgr->powercontainment_enabled)
2797                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2798                             PHM_PlatformCaps_PowerContainment);
2799         else
2800                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2801                             PHM_PlatformCaps_PowerContainment);
2802
2803         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2804                                                         PHM_PlatformCaps_CAC);
2805
2806         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2807                                                 PHM_PlatformCaps_RegulatorHot);
2808
2809         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2810                                                 PHM_PlatformCaps_AutomaticDCTransition);
2811
2812         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2813                                                 PHM_PlatformCaps_ODFuzzyFanControlSupport);
2814
2815         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2816                                                 PHM_PlatformCaps_FanSpeedInTableIsRPM);
2817
2818         if (hwmgr->chip_id == CHIP_POLARIS11)
2819                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2820                                         PHM_PlatformCaps_SPLLShutdownSupport);
2821         return 0;
2822 }
2823
2824 static void polaris10_init_dpm_defaults(struct pp_hwmgr *hwmgr)
2825 {
2826         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2827
2828         polaris10_initialize_power_tune_defaults(hwmgr);
2829
2830         data->pcie_gen_performance.max = PP_PCIEGen1;
2831         data->pcie_gen_performance.min = PP_PCIEGen3;
2832         data->pcie_gen_power_saving.max = PP_PCIEGen1;
2833         data->pcie_gen_power_saving.min = PP_PCIEGen3;
2834         data->pcie_lane_performance.max = 0;
2835         data->pcie_lane_performance.min = 16;
2836         data->pcie_lane_power_saving.max = 0;
2837         data->pcie_lane_power_saving.min = 16;
2838 }
2839
2840 /**
2841 * Get Leakage VDDC based on leakage ID.
2842 *
2843 * @param    hwmgr  the address of the powerplay hardware manager.
2844 * @return   always 0
2845 */
2846 static int polaris10_get_evv_voltages(struct pp_hwmgr *hwmgr)
2847 {
2848         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
2849         uint16_t vv_id;
2850         uint16_t vddc = 0;
2851         uint16_t i, j;
2852         uint32_t sclk = 0;
2853         struct phm_ppt_v1_information *table_info =
2854                         (struct phm_ppt_v1_information *)hwmgr->pptable;
2855         struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
2856                         table_info->vdd_dep_on_sclk;
2857         int result;
2858
2859         for (i = 0; i < POLARIS10_MAX_LEAKAGE_COUNT; i++) {
2860                 vv_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
2861                 if (!phm_get_sclk_for_voltage_evv(hwmgr,
2862                                 table_info->vddc_lookup_table, vv_id, &sclk)) {
2863                         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2864                                         PHM_PlatformCaps_ClockStretcher)) {
2865                                 for (j = 1; j < sclk_table->count; j++) {
2866                                         if (sclk_table->entries[j].clk == sclk &&
2867                                                         sclk_table->entries[j].cks_enable == 0) {
2868                                                 sclk += 5000;
2869                                                 break;
2870                                         }
2871                                 }
2872                         }
2873
2874                         if (atomctrl_get_voltage_evv_on_sclk_ai(hwmgr,
2875                                                 VOLTAGE_TYPE_VDDC,
2876                                                 sclk, vv_id, &vddc) != 0) {
2877                                 printk(KERN_WARNING "failed to retrieving EVV voltage!\n");
2878                                 continue;
2879                         }
2880
2881                         /* need to make sure vddc is less than 2v or else, it could burn the ASIC. */
2882                         PP_ASSERT_WITH_CODE((vddc < 2000 && vddc != 0),
2883                                         "Invalid VDDC value", result = -EINVAL;);
2884
2885                         /* the voltage should not be zero nor equal to leakage ID */
2886                         if (vddc != 0 && vddc != vv_id) {
2887                                 data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = (uint16_t)(vddc/100);
2888                                 data->vddc_leakage.leakage_id[data->vddc_leakage.count] = vv_id;
2889                                 data->vddc_leakage.count++;
2890                         }
2891                 }
2892         }
2893
2894         return 0;
2895 }
2896
2897 /**
2898  * Change virtual leakage voltage to actual value.
2899  *
2900  * @param     hwmgr  the address of the powerplay hardware manager.
2901  * @param     pointer to changing voltage
2902  * @param     pointer to leakage table
2903  */
2904 static void polaris10_patch_with_vdd_leakage(struct pp_hwmgr *hwmgr,
2905                 uint16_t *voltage, struct polaris10_leakage_voltage *leakage_table)
2906 {
2907         uint32_t index;
2908
2909         /* search for leakage voltage ID 0xff01 ~ 0xff08 */
2910         for (index = 0; index < leakage_table->count; index++) {
2911                 /* if this voltage matches a leakage voltage ID */
2912                 /* patch with actual leakage voltage */
2913                 if (leakage_table->leakage_id[index] == *voltage) {
2914                         *voltage = leakage_table->actual_voltage[index];
2915                         break;
2916                 }
2917         }
2918
2919         if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0)
2920                 printk(KERN_ERR "Voltage value looks like a Leakage ID but it's not patched \n");
2921 }
2922
2923 /**
2924 * Patch voltage lookup table by EVV leakages.
2925 *
2926 * @param     hwmgr  the address of the powerplay hardware manager.
2927 * @param     pointer to voltage lookup table
2928 * @param     pointer to leakage table
2929 * @return     always 0
2930 */
2931 static int polaris10_patch_lookup_table_with_leakage(struct pp_hwmgr *hwmgr,
2932                 phm_ppt_v1_voltage_lookup_table *lookup_table,
2933                 struct polaris10_leakage_voltage *leakage_table)
2934 {
2935         uint32_t i;
2936
2937         for (i = 0; i < lookup_table->count; i++)
2938                 polaris10_patch_with_vdd_leakage(hwmgr,
2939                                 &lookup_table->entries[i].us_vdd, leakage_table);
2940
2941         return 0;
2942 }
2943
2944 static int polaris10_patch_clock_voltage_limits_with_vddc_leakage(
2945                 struct pp_hwmgr *hwmgr, struct polaris10_leakage_voltage *leakage_table,
2946                 uint16_t *vddc)
2947 {
2948         struct phm_ppt_v1_information *table_info =
2949                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2950         polaris10_patch_with_vdd_leakage(hwmgr, (uint16_t *)vddc, leakage_table);
2951         hwmgr->dyn_state.max_clock_voltage_on_dc.vddc =
2952                         table_info->max_clock_voltage_on_dc.vddc;
2953         return 0;
2954 }
2955
2956 static int polaris10_patch_voltage_dependency_tables_with_lookup_table(
2957                 struct pp_hwmgr *hwmgr)
2958 {
2959         uint8_t entryId;
2960         uint8_t voltageId;
2961         struct phm_ppt_v1_information *table_info =
2962                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2963
2964         struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
2965                         table_info->vdd_dep_on_sclk;
2966         struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table =
2967                         table_info->vdd_dep_on_mclk;
2968         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
2969                         table_info->mm_dep_table;
2970
2971         for (entryId = 0; entryId < sclk_table->count; ++entryId) {
2972                 voltageId = sclk_table->entries[entryId].vddInd;
2973                 sclk_table->entries[entryId].vddc =
2974                                 table_info->vddc_lookup_table->entries[voltageId].us_vdd;
2975         }
2976
2977         for (entryId = 0; entryId < mclk_table->count; ++entryId) {
2978                 voltageId = mclk_table->entries[entryId].vddInd;
2979                 mclk_table->entries[entryId].vddc =
2980                         table_info->vddc_lookup_table->entries[voltageId].us_vdd;
2981         }
2982
2983         for (entryId = 0; entryId < mm_table->count; ++entryId) {
2984                 voltageId = mm_table->entries[entryId].vddcInd;
2985                 mm_table->entries[entryId].vddc =
2986                         table_info->vddc_lookup_table->entries[voltageId].us_vdd;
2987         }
2988
2989         return 0;
2990
2991 }
2992
2993 static int polaris10_calc_voltage_dependency_tables(struct pp_hwmgr *hwmgr)
2994 {
2995         /* Need to determine if we need calculated voltage. */
2996         return 0;
2997 }
2998
2999 static int polaris10_calc_mm_voltage_dependency_table(struct pp_hwmgr *hwmgr)
3000 {
3001         /* Need to determine if we need calculated voltage from mm table. */
3002         return 0;
3003 }
3004
3005 static int polaris10_sort_lookup_table(struct pp_hwmgr *hwmgr,
3006                 struct phm_ppt_v1_voltage_lookup_table *lookup_table)
3007 {
3008         uint32_t table_size, i, j;
3009         struct phm_ppt_v1_voltage_lookup_record tmp_voltage_lookup_record;
3010         table_size = lookup_table->count;
3011
3012         PP_ASSERT_WITH_CODE(0 != lookup_table->count,
3013                 "Lookup table is empty", return -EINVAL);
3014
3015         /* Sorting voltages */
3016         for (i = 0; i < table_size - 1; i++) {
3017                 for (j = i + 1; j > 0; j--) {
3018                         if (lookup_table->entries[j].us_vdd <
3019                                         lookup_table->entries[j - 1].us_vdd) {
3020                                 tmp_voltage_lookup_record = lookup_table->entries[j - 1];
3021                                 lookup_table->entries[j - 1] = lookup_table->entries[j];
3022                                 lookup_table->entries[j] = tmp_voltage_lookup_record;
3023                         }
3024                 }
3025         }
3026
3027         return 0;
3028 }
3029
3030 static int polaris10_complete_dependency_tables(struct pp_hwmgr *hwmgr)
3031 {
3032         int result = 0;
3033         int tmp_result;
3034         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3035         struct phm_ppt_v1_information *table_info =
3036                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
3037
3038         tmp_result = polaris10_patch_lookup_table_with_leakage(hwmgr,
3039                         table_info->vddc_lookup_table, &(data->vddc_leakage));
3040         if (tmp_result)
3041                 result = tmp_result;
3042
3043         tmp_result = polaris10_patch_clock_voltage_limits_with_vddc_leakage(hwmgr,
3044                         &(data->vddc_leakage), &table_info->max_clock_voltage_on_dc.vddc);
3045         if (tmp_result)
3046                 result = tmp_result;
3047
3048         tmp_result = polaris10_patch_voltage_dependency_tables_with_lookup_table(hwmgr);
3049         if (tmp_result)
3050                 result = tmp_result;
3051
3052         tmp_result = polaris10_calc_voltage_dependency_tables(hwmgr);
3053         if (tmp_result)
3054                 result = tmp_result;
3055
3056         tmp_result = polaris10_calc_mm_voltage_dependency_table(hwmgr);
3057         if (tmp_result)
3058                 result = tmp_result;
3059
3060         tmp_result = polaris10_sort_lookup_table(hwmgr, table_info->vddc_lookup_table);
3061         if (tmp_result)
3062                 result = tmp_result;
3063
3064         return result;
3065 }
3066
3067 static int polaris10_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr)
3068 {
3069         struct phm_ppt_v1_information *table_info =
3070                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
3071
3072         struct phm_ppt_v1_clock_voltage_dependency_table *allowed_sclk_vdd_table =
3073                                                 table_info->vdd_dep_on_sclk;
3074         struct phm_ppt_v1_clock_voltage_dependency_table *allowed_mclk_vdd_table =
3075                                                 table_info->vdd_dep_on_mclk;
3076
3077         PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table != NULL,
3078                 "VDD dependency on SCLK table is missing.       \
3079                 This table is mandatory", return -EINVAL);
3080         PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1,
3081                 "VDD dependency on SCLK table has to have is missing.   \
3082                 This table is mandatory", return -EINVAL);
3083
3084         PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table != NULL,
3085                 "VDD dependency on MCLK table is missing.       \
3086                 This table is mandatory", return -EINVAL);
3087         PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1,
3088                 "VDD dependency on MCLK table has to have is missing.    \
3089                 This table is mandatory", return -EINVAL);
3090
3091         table_info->max_clock_voltage_on_ac.sclk =
3092                 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].clk;
3093         table_info->max_clock_voltage_on_ac.mclk =
3094                 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk;
3095         table_info->max_clock_voltage_on_ac.vddc =
3096                 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc;
3097         table_info->max_clock_voltage_on_ac.vddci =
3098                 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci;
3099
3100         hwmgr->dyn_state.max_clock_voltage_on_ac.sclk = table_info->max_clock_voltage_on_ac.sclk;
3101         hwmgr->dyn_state.max_clock_voltage_on_ac.mclk = table_info->max_clock_voltage_on_ac.mclk;
3102         hwmgr->dyn_state.max_clock_voltage_on_ac.vddc = table_info->max_clock_voltage_on_ac.vddc;
3103         hwmgr->dyn_state.max_clock_voltage_on_ac.vddci =table_info->max_clock_voltage_on_ac.vddci;
3104
3105         return 0;
3106 }
3107
3108 int polaris10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
3109 {
3110         struct polaris10_hwmgr *data;
3111         struct pp_atomctrl_gpio_pin_assignment gpio_pin_assignment;
3112         uint32_t temp_reg;
3113         int result;
3114         struct phm_ppt_v1_information *table_info =
3115                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
3116
3117         data = kzalloc(sizeof(struct polaris10_hwmgr), GFP_KERNEL);
3118         if (data == NULL)
3119                 return -ENOMEM;
3120
3121         hwmgr->backend = data;
3122
3123         data->dll_default_on = false;
3124         data->sram_end = SMC_RAM_END;
3125         data->mclk_dpm0_activity_target = 0xa;
3126         data->disable_dpm_mask = 0xFF;
3127         data->static_screen_threshold = PPPOLARIS10_STATICSCREENTHRESHOLD_DFLT;
3128         data->static_screen_threshold_unit = PPPOLARIS10_STATICSCREENTHRESHOLD_DFLT;
3129         data->activity_target[0] = PPPOLARIS10_TARGETACTIVITY_DFLT;
3130         data->activity_target[1] = PPPOLARIS10_TARGETACTIVITY_DFLT;
3131         data->activity_target[2] = PPPOLARIS10_TARGETACTIVITY_DFLT;
3132         data->activity_target[3] = PPPOLARIS10_TARGETACTIVITY_DFLT;
3133         data->activity_target[4] = PPPOLARIS10_TARGETACTIVITY_DFLT;
3134         data->activity_target[5] = PPPOLARIS10_TARGETACTIVITY_DFLT;
3135         data->activity_target[6] = PPPOLARIS10_TARGETACTIVITY_DFLT;
3136         data->activity_target[7] = PPPOLARIS10_TARGETACTIVITY_DFLT;
3137
3138         data->voting_rights_clients0 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT0;
3139         data->voting_rights_clients1 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT1;
3140         data->voting_rights_clients2 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT2;
3141         data->voting_rights_clients3 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT3;
3142         data->voting_rights_clients4 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT4;
3143         data->voting_rights_clients5 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT5;
3144         data->voting_rights_clients6 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT6;
3145         data->voting_rights_clients7 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT7;
3146
3147         data->vddc_vddci_delta = VDDC_VDDCI_DELTA;
3148
3149         data->mclk_activity_target = PPPOLARIS10_MCLK_TARGETACTIVITY_DFLT;
3150
3151         /* need to set voltage control types before EVV patching */
3152         data->voltage_control = POLARIS10_VOLTAGE_CONTROL_NONE;
3153         data->vddci_control = POLARIS10_VOLTAGE_CONTROL_NONE;
3154         data->mvdd_control = POLARIS10_VOLTAGE_CONTROL_NONE;
3155
3156         data->enable_tdc_limit_feature = true;
3157         data->enable_pkg_pwr_tracking_feature = true;
3158         data->force_pcie_gen = PP_PCIEGenInvalid;
3159         data->mclk_stutter_mode_threshold = 40000;
3160
3161         if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
3162                         VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2))
3163                 data->voltage_control = POLARIS10_VOLTAGE_CONTROL_BY_SVID2;
3164
3165         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3166                         PHM_PlatformCaps_EnableMVDDControl)) {
3167                 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
3168                                 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT))
3169                         data->mvdd_control = POLARIS10_VOLTAGE_CONTROL_BY_GPIO;
3170                 else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
3171                                 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2))
3172                         data->mvdd_control = POLARIS10_VOLTAGE_CONTROL_BY_SVID2;
3173         }
3174
3175         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3176                         PHM_PlatformCaps_ControlVDDCI)) {
3177                 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
3178                                 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
3179                         data->vddci_control = POLARIS10_VOLTAGE_CONTROL_BY_GPIO;
3180                 else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
3181                                 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2))
3182                         data->vddci_control = POLARIS10_VOLTAGE_CONTROL_BY_SVID2;
3183         }
3184
3185         if (table_info->cac_dtp_table->usClockStretchAmount != 0)
3186                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
3187                                         PHM_PlatformCaps_ClockStretcher);
3188
3189         polaris10_set_features_platform_caps(hwmgr);
3190
3191         polaris10_init_dpm_defaults(hwmgr);
3192
3193         /* Get leakage voltage based on leakage ID. */
3194         result = polaris10_get_evv_voltages(hwmgr);
3195
3196         if (result) {
3197                 printk("Get EVV Voltage Failed.  Abort Driver loading!\n");
3198                 return -1;
3199         }
3200
3201         polaris10_complete_dependency_tables(hwmgr);
3202         polaris10_set_private_data_based_on_pptable(hwmgr);
3203
3204         /* Initalize Dynamic State Adjustment Rule Settings */
3205         result = phm_initializa_dynamic_state_adjustment_rule_settings(hwmgr);
3206
3207         if (0 == result) {
3208                 struct cgs_system_info sys_info = {0};
3209
3210                 data->is_tlu_enabled = 0;
3211
3212                 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
3213                                                         POLARIS10_MAX_HARDWARE_POWERLEVELS;
3214                 hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
3215                 hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
3216
3217
3218                 if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_PCC_GPIO_PINID, &gpio_pin_assignment)) {
3219                         temp_reg = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL);
3220                         switch (gpio_pin_assignment.uc_gpio_pin_bit_shift) {
3221                         case 0:
3222                                 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x1);
3223                                 break;
3224                         case 1:
3225                                 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x2);
3226                                 break;
3227                         case 2:
3228                                 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW, 0x1);
3229                                 break;
3230                         case 3:
3231                                 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, FORCE_NB_PS1, 0x1);
3232                                 break;
3233                         case 4:
3234                                 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, DPM_ENABLED, 0x1);
3235                                 break;
3236                         default:
3237                                 PP_ASSERT_WITH_CODE(0,
3238                                 "Failed to setup PCC HW register! Wrong GPIO assigned for VDDC_PCC_GPIO_PINID!",
3239                                 );
3240                                 break;
3241                         }
3242                         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL, temp_reg);
3243                 }
3244
3245                 if (table_info->cac_dtp_table->usDefaultTargetOperatingTemp != 0 &&
3246                         hwmgr->thermal_controller.advanceFanControlParameters.ucFanControlMode) {
3247                         hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMinLimit =
3248                                 (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit;
3249
3250                         hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMaxLimit =
3251                                 (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM;
3252
3253                         hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMStep = 1;
3254
3255                         hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMaxLimit = 100;
3256
3257                         hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMinLimit =
3258                                 (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit;
3259
3260                         hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMStep = 1;
3261
3262                         table_info->cac_dtp_table->usDefaultTargetOperatingTemp = (table_info->cac_dtp_table->usDefaultTargetOperatingTemp >= 50) ?
3263                                                                         (table_info->cac_dtp_table->usDefaultTargetOperatingTemp -50) : 0;
3264
3265                         table_info->cac_dtp_table->usOperatingTempMaxLimit = table_info->cac_dtp_table->usDefaultTargetOperatingTemp;
3266                         table_info->cac_dtp_table->usOperatingTempStep = 1;
3267                         table_info->cac_dtp_table->usOperatingTempHyst = 1;
3268
3269                         hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanPWM =
3270                                        hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM;
3271
3272                         hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM =
3273                                        hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanRPM;
3274
3275                         hwmgr->dyn_state.cac_dtp_table->usOperatingTempMinLimit =
3276                                        table_info->cac_dtp_table->usOperatingTempMinLimit;
3277
3278                         hwmgr->dyn_state.cac_dtp_table->usOperatingTempMaxLimit =
3279                                        table_info->cac_dtp_table->usOperatingTempMaxLimit;
3280
3281                         hwmgr->dyn_state.cac_dtp_table->usDefaultTargetOperatingTemp =
3282                                        table_info->cac_dtp_table->usDefaultTargetOperatingTemp;
3283
3284                         hwmgr->dyn_state.cac_dtp_table->usOperatingTempStep =
3285                                        table_info->cac_dtp_table->usOperatingTempStep;
3286
3287                         hwmgr->dyn_state.cac_dtp_table->usTargetOperatingTemp =
3288                                        table_info->cac_dtp_table->usTargetOperatingTemp;
3289                 }
3290
3291                 sys_info.size = sizeof(struct cgs_system_info);
3292                 sys_info.info_id = CGS_SYSTEM_INFO_PCIE_GEN_INFO;
3293                 result = cgs_query_system_info(hwmgr->device, &sys_info);
3294                 if (result)
3295                         data->pcie_gen_cap = AMDGPU_DEFAULT_PCIE_GEN_MASK;
3296                 else
3297                         data->pcie_gen_cap = (uint32_t)sys_info.value;
3298                 if (data->pcie_gen_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
3299                         data->pcie_spc_cap = 20;
3300                 sys_info.size = sizeof(struct cgs_system_info);
3301                 sys_info.info_id = CGS_SYSTEM_INFO_PCIE_MLW;
3302                 result = cgs_query_system_info(hwmgr->device, &sys_info);
3303                 if (result)
3304                         data->pcie_lane_cap = AMDGPU_DEFAULT_PCIE_MLW_MASK;
3305                 else
3306                         data->pcie_lane_cap = (uint32_t)sys_info.value;
3307
3308                 hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */
3309 /* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */
3310                 hwmgr->platform_descriptor.clockStep.engineClock = 500;
3311                 hwmgr->platform_descriptor.clockStep.memoryClock = 500;
3312         } else {
3313                 /* Ignore return value in here, we are cleaning up a mess. */
3314                 polaris10_hwmgr_backend_fini(hwmgr);
3315         }
3316
3317         return 0;
3318 }
3319
3320 static int polaris10_force_dpm_highest(struct pp_hwmgr *hwmgr)
3321 {
3322         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3323         uint32_t level, tmp;
3324
3325         if (!data->pcie_dpm_key_disabled) {
3326                 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3327                         level = 0;
3328                         tmp = data->dpm_level_enable_mask.pcie_dpm_enable_mask;
3329                         while (tmp >>= 1)
3330                                 level++;
3331
3332                         if (level)
3333                                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3334                                                 PPSMC_MSG_PCIeDPM_ForceLevel, level);
3335                 }
3336         }
3337
3338         if (!data->sclk_dpm_key_disabled) {
3339                 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3340                         level = 0;
3341                         tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask;
3342                         while (tmp >>= 1)
3343                                 level++;
3344
3345                         if (level)
3346                                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3347                                                 PPSMC_MSG_SCLKDPM_SetEnabledMask,
3348                                                 (1 << level));
3349                 }
3350         }
3351
3352         if (!data->mclk_dpm_key_disabled) {
3353                 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3354                         level = 0;
3355                         tmp = data->dpm_level_enable_mask.mclk_dpm_enable_mask;
3356                         while (tmp >>= 1)
3357                                 level++;
3358
3359                         if (level)
3360                                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3361                                                 PPSMC_MSG_MCLKDPM_SetEnabledMask,
3362                                                 (1 << level));
3363                 }
3364         }
3365
3366         return 0;
3367 }
3368
3369 static int polaris10_upload_dpm_level_enable_mask(struct pp_hwmgr *hwmgr)
3370 {
3371         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3372
3373         phm_apply_dal_min_voltage_request(hwmgr);
3374
3375         if (!data->sclk_dpm_key_disabled) {
3376                 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask)
3377                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3378                                         PPSMC_MSG_SCLKDPM_SetEnabledMask,
3379                                         data->dpm_level_enable_mask.sclk_dpm_enable_mask);
3380         }
3381
3382         if (!data->mclk_dpm_key_disabled) {
3383                 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask)
3384                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3385                                         PPSMC_MSG_MCLKDPM_SetEnabledMask,
3386                                         data->dpm_level_enable_mask.mclk_dpm_enable_mask);
3387         }
3388
3389         return 0;
3390 }
3391
3392 static int polaris10_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
3393 {
3394         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3395
3396         if (!polaris10_is_dpm_running(hwmgr))
3397                 return -EINVAL;
3398
3399         if (!data->pcie_dpm_key_disabled) {
3400                 smum_send_msg_to_smc(hwmgr->smumgr,
3401                                 PPSMC_MSG_PCIeDPM_UnForceLevel);
3402         }
3403
3404         return polaris10_upload_dpm_level_enable_mask(hwmgr);
3405 }
3406
3407 static int polaris10_force_dpm_lowest(struct pp_hwmgr *hwmgr)
3408 {
3409         struct polaris10_hwmgr *data =
3410                         (struct polaris10_hwmgr *)(hwmgr->backend);
3411         uint32_t level;
3412
3413         if (!data->sclk_dpm_key_disabled)
3414                 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3415                         level = phm_get_lowest_enabled_level(hwmgr,
3416                                                               data->dpm_level_enable_mask.sclk_dpm_enable_mask);
3417                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3418                                                             PPSMC_MSG_SCLKDPM_SetEnabledMask,
3419                                                             (1 << level));
3420
3421         }
3422
3423         if (!data->mclk_dpm_key_disabled) {
3424                 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3425                         level = phm_get_lowest_enabled_level(hwmgr,
3426                                                               data->dpm_level_enable_mask.mclk_dpm_enable_mask);
3427                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3428                                                             PPSMC_MSG_MCLKDPM_SetEnabledMask,
3429                                                             (1 << level));
3430                 }
3431         }
3432
3433         if (!data->pcie_dpm_key_disabled) {
3434                 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3435                         level = phm_get_lowest_enabled_level(hwmgr,
3436                                                               data->dpm_level_enable_mask.pcie_dpm_enable_mask);
3437                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3438                                                             PPSMC_MSG_PCIeDPM_ForceLevel,
3439                                                             (level));
3440                 }
3441         }
3442
3443         return 0;
3444
3445 }
3446 static int polaris10_force_dpm_level(struct pp_hwmgr *hwmgr,
3447                                 enum amd_dpm_forced_level level)
3448 {
3449         int ret = 0;
3450
3451         switch (level) {
3452         case AMD_DPM_FORCED_LEVEL_HIGH:
3453                 ret = polaris10_force_dpm_highest(hwmgr);
3454                 if (ret)
3455                         return ret;
3456                 break;
3457         case AMD_DPM_FORCED_LEVEL_LOW:
3458                 ret = polaris10_force_dpm_lowest(hwmgr);
3459                 if (ret)
3460                         return ret;
3461                 break;
3462         case AMD_DPM_FORCED_LEVEL_AUTO:
3463                 ret = polaris10_unforce_dpm_levels(hwmgr);
3464                 if (ret)
3465                         return ret;
3466                 break;
3467         default:
3468                 break;
3469         }
3470
3471         hwmgr->dpm_level = level;
3472
3473         return ret;
3474 }
3475
3476 static int polaris10_get_power_state_size(struct pp_hwmgr *hwmgr)
3477 {
3478         return sizeof(struct polaris10_power_state);
3479 }
3480
3481
3482 static int polaris10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
3483                                 struct pp_power_state *request_ps,
3484                         const struct pp_power_state *current_ps)
3485 {
3486
3487         struct polaris10_power_state *polaris10_ps =
3488                                 cast_phw_polaris10_power_state(&request_ps->hardware);
3489         uint32_t sclk;
3490         uint32_t mclk;
3491         struct PP_Clocks minimum_clocks = {0};
3492         bool disable_mclk_switching;
3493         bool disable_mclk_switching_for_frame_lock;
3494         struct cgs_display_info info = {0};
3495         const struct phm_clock_and_voltage_limits *max_limits;
3496         uint32_t i;
3497         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3498         struct phm_ppt_v1_information *table_info =
3499                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
3500         int32_t count;
3501         int32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0;
3502
3503         data->battery_state = (PP_StateUILabel_Battery ==
3504                         request_ps->classification.ui_label);
3505
3506         PP_ASSERT_WITH_CODE(polaris10_ps->performance_level_count == 2,
3507                                  "VI should always have 2 performance levels",
3508                                 );
3509
3510         max_limits = (PP_PowerSource_AC == hwmgr->power_source) ?
3511                         &(hwmgr->dyn_state.max_clock_voltage_on_ac) :
3512                         &(hwmgr->dyn_state.max_clock_voltage_on_dc);
3513
3514         /* Cap clock DPM tables at DC MAX if it is in DC. */
3515         if (PP_PowerSource_DC == hwmgr->power_source) {
3516                 for (i = 0; i < polaris10_ps->performance_level_count; i++) {
3517                         if (polaris10_ps->performance_levels[i].memory_clock > max_limits->mclk)
3518                                 polaris10_ps->performance_levels[i].memory_clock = max_limits->mclk;
3519                         if (polaris10_ps->performance_levels[i].engine_clock > max_limits->sclk)
3520                                 polaris10_ps->performance_levels[i].engine_clock = max_limits->sclk;
3521                 }
3522         }
3523
3524         polaris10_ps->vce_clks.evclk = hwmgr->vce_arbiter.evclk;
3525         polaris10_ps->vce_clks.ecclk = hwmgr->vce_arbiter.ecclk;
3526
3527         cgs_get_active_displays_info(hwmgr->device, &info);
3528
3529         /*TO DO result = PHM_CheckVBlankTime(hwmgr, &vblankTooShort);*/
3530
3531         /* TO DO GetMinClockSettings(hwmgr->pPECI, &minimum_clocks); */
3532
3533         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3534                         PHM_PlatformCaps_StablePState)) {
3535                 max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac);
3536                 stable_pstate_sclk = (max_limits->sclk * 75) / 100;
3537
3538                 for (count = table_info->vdd_dep_on_sclk->count - 1;
3539                                 count >= 0; count--) {
3540                         if (stable_pstate_sclk >=
3541                                         table_info->vdd_dep_on_sclk->entries[count].clk) {
3542                                 stable_pstate_sclk =
3543                                                 table_info->vdd_dep_on_sclk->entries[count].clk;
3544                                 break;
3545                         }
3546                 }
3547
3548                 if (count < 0)
3549                         stable_pstate_sclk = table_info->vdd_dep_on_sclk->entries[0].clk;
3550
3551                 stable_pstate_mclk = max_limits->mclk;
3552
3553                 minimum_clocks.engineClock = stable_pstate_sclk;
3554                 minimum_clocks.memoryClock = stable_pstate_mclk;
3555         }
3556
3557         if (minimum_clocks.engineClock < hwmgr->gfx_arbiter.sclk)
3558                 minimum_clocks.engineClock = hwmgr->gfx_arbiter.sclk;
3559
3560         if (minimum_clocks.memoryClock < hwmgr->gfx_arbiter.mclk)
3561                 minimum_clocks.memoryClock = hwmgr->gfx_arbiter.mclk;
3562
3563         polaris10_ps->sclk_threshold = hwmgr->gfx_arbiter.sclk_threshold;
3564
3565         if (0 != hwmgr->gfx_arbiter.sclk_over_drive) {
3566                 PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.sclk_over_drive <=
3567                                 hwmgr->platform_descriptor.overdriveLimit.engineClock),
3568                                 "Overdrive sclk exceeds limit",
3569                                 hwmgr->gfx_arbiter.sclk_over_drive =
3570                                                 hwmgr->platform_descriptor.overdriveLimit.engineClock);
3571
3572                 if (hwmgr->gfx_arbiter.sclk_over_drive >= hwmgr->gfx_arbiter.sclk)
3573                         polaris10_ps->performance_levels[1].engine_clock =
3574                                         hwmgr->gfx_arbiter.sclk_over_drive;
3575         }
3576
3577         if (0 != hwmgr->gfx_arbiter.mclk_over_drive) {
3578                 PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.mclk_over_drive <=
3579                                 hwmgr->platform_descriptor.overdriveLimit.memoryClock),
3580                                 "Overdrive mclk exceeds limit",
3581                                 hwmgr->gfx_arbiter.mclk_over_drive =
3582                                                 hwmgr->platform_descriptor.overdriveLimit.memoryClock);
3583
3584                 if (hwmgr->gfx_arbiter.mclk_over_drive >= hwmgr->gfx_arbiter.mclk)
3585                         polaris10_ps->performance_levels[1].memory_clock =
3586                                         hwmgr->gfx_arbiter.mclk_over_drive;
3587         }
3588
3589         disable_mclk_switching_for_frame_lock = phm_cap_enabled(
3590                                     hwmgr->platform_descriptor.platformCaps,
3591                                     PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);
3592
3593         disable_mclk_switching = (1 < info.display_count) ||
3594                                     disable_mclk_switching_for_frame_lock;
3595
3596         sclk = polaris10_ps->performance_levels[0].engine_clock;
3597         mclk = polaris10_ps->performance_levels[0].memory_clock;
3598
3599         if (disable_mclk_switching)
3600                 mclk = polaris10_ps->performance_levels
3601                 [polaris10_ps->performance_level_count - 1].memory_clock;
3602
3603         if (sclk < minimum_clocks.engineClock)
3604                 sclk = (minimum_clocks.engineClock > max_limits->sclk) ?
3605                                 max_limits->sclk : minimum_clocks.engineClock;
3606
3607         if (mclk < minimum_clocks.memoryClock)
3608                 mclk = (minimum_clocks.memoryClock > max_limits->mclk) ?
3609                                 max_limits->mclk : minimum_clocks.memoryClock;
3610
3611         polaris10_ps->performance_levels[0].engine_clock = sclk;
3612         polaris10_ps->performance_levels[0].memory_clock = mclk;
3613
3614         polaris10_ps->performance_levels[1].engine_clock =
3615                 (polaris10_ps->performance_levels[1].engine_clock >=
3616                                 polaris10_ps->performance_levels[0].engine_clock) ?
3617                                                 polaris10_ps->performance_levels[1].engine_clock :
3618                                                 polaris10_ps->performance_levels[0].engine_clock;
3619
3620         if (disable_mclk_switching) {
3621                 if (mclk < polaris10_ps->performance_levels[1].memory_clock)
3622                         mclk = polaris10_ps->performance_levels[1].memory_clock;
3623
3624                 polaris10_ps->performance_levels[0].memory_clock = mclk;
3625                 polaris10_ps->performance_levels[1].memory_clock = mclk;
3626         } else {
3627                 if (polaris10_ps->performance_levels[1].memory_clock <
3628                                 polaris10_ps->performance_levels[0].memory_clock)
3629                         polaris10_ps->performance_levels[1].memory_clock =
3630                                         polaris10_ps->performance_levels[0].memory_clock;
3631         }
3632
3633         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3634                         PHM_PlatformCaps_StablePState)) {
3635                 for (i = 0; i < polaris10_ps->performance_level_count; i++) {
3636                         polaris10_ps->performance_levels[i].engine_clock = stable_pstate_sclk;
3637                         polaris10_ps->performance_levels[i].memory_clock = stable_pstate_mclk;
3638                         polaris10_ps->performance_levels[i].pcie_gen = data->pcie_gen_performance.max;
3639                         polaris10_ps->performance_levels[i].pcie_lane = data->pcie_gen_performance.max;
3640                 }
3641         }
3642         return 0;
3643 }
3644
3645
3646 static int polaris10_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
3647 {
3648         struct pp_power_state  *ps;
3649         struct polaris10_power_state  *polaris10_ps;
3650
3651         if (hwmgr == NULL)
3652                 return -EINVAL;
3653
3654         ps = hwmgr->request_ps;
3655
3656         if (ps == NULL)
3657                 return -EINVAL;
3658
3659         polaris10_ps = cast_phw_polaris10_power_state(&ps->hardware);
3660
3661         if (low)
3662                 return polaris10_ps->performance_levels[0].memory_clock;
3663         else
3664                 return polaris10_ps->performance_levels
3665                                 [polaris10_ps->performance_level_count-1].memory_clock;
3666 }
3667
3668 static int polaris10_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
3669 {
3670         struct pp_power_state  *ps;
3671         struct polaris10_power_state  *polaris10_ps;
3672
3673         if (hwmgr == NULL)
3674                 return -EINVAL;
3675
3676         ps = hwmgr->request_ps;
3677
3678         if (ps == NULL)
3679                 return -EINVAL;
3680
3681         polaris10_ps = cast_phw_polaris10_power_state(&ps->hardware);
3682
3683         if (low)
3684                 return polaris10_ps->performance_levels[0].engine_clock;
3685         else
3686                 return polaris10_ps->performance_levels
3687                                 [polaris10_ps->performance_level_count-1].engine_clock;
3688 }
3689
3690 static int polaris10_dpm_patch_boot_state(struct pp_hwmgr *hwmgr,
3691                                         struct pp_hw_power_state *hw_ps)
3692 {
3693         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3694         struct polaris10_power_state *ps = (struct polaris10_power_state *)hw_ps;
3695         ATOM_FIRMWARE_INFO_V2_2 *fw_info;
3696         uint16_t size;
3697         uint8_t frev, crev;
3698         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
3699
3700         /* First retrieve the Boot clocks and VDDC from the firmware info table.
3701          * We assume here that fw_info is unchanged if this call fails.
3702          */
3703         fw_info = (ATOM_FIRMWARE_INFO_V2_2 *)cgs_atom_get_data_table(
3704                         hwmgr->device, index,
3705                         &size, &frev, &crev);
3706         if (!fw_info)
3707                 /* During a test, there is no firmware info table. */
3708                 return 0;
3709
3710         /* Patch the state. */
3711         data->vbios_boot_state.sclk_bootup_value =
3712                         le32_to_cpu(fw_info->ulDefaultEngineClock);
3713         data->vbios_boot_state.mclk_bootup_value =
3714                         le32_to_cpu(fw_info->ulDefaultMemoryClock);
3715         data->vbios_boot_state.mvdd_bootup_value =
3716                         le16_to_cpu(fw_info->usBootUpMVDDCVoltage);
3717         data->vbios_boot_state.vddc_bootup_value =
3718                         le16_to_cpu(fw_info->usBootUpVDDCVoltage);
3719         data->vbios_boot_state.vddci_bootup_value =
3720                         le16_to_cpu(fw_info->usBootUpVDDCIVoltage);
3721         data->vbios_boot_state.pcie_gen_bootup_value =
3722                         phm_get_current_pcie_speed(hwmgr);
3723
3724         data->vbios_boot_state.pcie_lane_bootup_value =
3725                         (uint16_t)phm_get_current_pcie_lane_number(hwmgr);
3726
3727         /* set boot power state */
3728         ps->performance_levels[0].memory_clock = data->vbios_boot_state.mclk_bootup_value;
3729         ps->performance_levels[0].engine_clock = data->vbios_boot_state.sclk_bootup_value;
3730         ps->performance_levels[0].pcie_gen = data->vbios_boot_state.pcie_gen_bootup_value;
3731         ps->performance_levels[0].pcie_lane = data->vbios_boot_state.pcie_lane_bootup_value;
3732
3733         return 0;
3734 }
3735
3736 static int polaris10_get_pp_table_entry_callback_func(struct pp_hwmgr *hwmgr,
3737                 void *state, struct pp_power_state *power_state,
3738                 void *pp_table, uint32_t classification_flag)
3739 {
3740         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3741         struct polaris10_power_state  *polaris10_power_state =
3742                         (struct polaris10_power_state *)(&(power_state->hardware));
3743         struct polaris10_performance_level *performance_level;
3744         ATOM_Tonga_State *state_entry = (ATOM_Tonga_State *)state;
3745         ATOM_Tonga_POWERPLAYTABLE *powerplay_table =
3746                         (ATOM_Tonga_POWERPLAYTABLE *)pp_table;
3747         PPTable_Generic_SubTable_Header *sclk_dep_table =
3748                         (PPTable_Generic_SubTable_Header *)
3749                         (((unsigned long)powerplay_table) +
3750                                 le16_to_cpu(powerplay_table->usSclkDependencyTableOffset));
3751
3752         ATOM_Tonga_MCLK_Dependency_Table *mclk_dep_table =
3753                         (ATOM_Tonga_MCLK_Dependency_Table *)
3754                         (((unsigned long)powerplay_table) +
3755                                 le16_to_cpu(powerplay_table->usMclkDependencyTableOffset));
3756
3757         /* The following fields are not initialized here: id orderedList allStatesList */
3758         power_state->classification.ui_label =
3759                         (le16_to_cpu(state_entry->usClassification) &
3760                         ATOM_PPLIB_CLASSIFICATION_UI_MASK) >>
3761                         ATOM_PPLIB_CLASSIFICATION_UI_SHIFT;
3762         power_state->classification.flags = classification_flag;
3763         /* NOTE: There is a classification2 flag in BIOS that is not being used right now */
3764
3765         power_state->classification.temporary_state = false;
3766         power_state->classification.to_be_deleted = false;
3767
3768         power_state->validation.disallowOnDC =
3769                         (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) &
3770                                         ATOM_Tonga_DISALLOW_ON_DC));
3771
3772         power_state->pcie.lanes = 0;
3773
3774         power_state->display.disableFrameModulation = false;
3775         power_state->display.limitRefreshrate = false;
3776         power_state->display.enableVariBright =
3777                         (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) &
3778                                         ATOM_Tonga_ENABLE_VARIBRIGHT));
3779
3780         power_state->validation.supportedPowerLevels = 0;
3781         power_state->uvd_clocks.VCLK = 0;
3782         power_state->uvd_clocks.DCLK = 0;
3783         power_state->temperatures.min = 0;
3784         power_state->temperatures.max = 0;
3785
3786         performance_level = &(polaris10_power_state->performance_levels
3787                         [polaris10_power_state->performance_level_count++]);
3788
3789         PP_ASSERT_WITH_CODE(
3790                         (polaris10_power_state->performance_level_count < SMU74_MAX_LEVELS_GRAPHICS),
3791                         "Performance levels exceeds SMC limit!",
3792                         return -1);
3793
3794         PP_ASSERT_WITH_CODE(
3795                         (polaris10_power_state->performance_level_count <=
3796                                         hwmgr->platform_descriptor.hardwareActivityPerformanceLevels),
3797                         "Performance levels exceeds Driver limit!",
3798                         return -1);
3799
3800         /* Performance levels are arranged from low to high. */
3801         performance_level->memory_clock = mclk_dep_table->entries
3802                         [state_entry->ucMemoryClockIndexLow].ulMclk;
3803         if (sclk_dep_table->ucRevId == 0)
3804                 performance_level->engine_clock = ((ATOM_Tonga_SCLK_Dependency_Table *)sclk_dep_table)->entries
3805                         [state_entry->ucEngineClockIndexLow].ulSclk;
3806         else if (sclk_dep_table->ucRevId == 1)
3807                 performance_level->engine_clock = ((ATOM_Polaris_SCLK_Dependency_Table *)sclk_dep_table)->entries
3808                         [state_entry->ucEngineClockIndexLow].ulSclk;
3809         performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap,
3810                         state_entry->ucPCIEGenLow);
3811         performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap,
3812                         state_entry->ucPCIELaneHigh);
3813
3814         performance_level = &(polaris10_power_state->performance_levels
3815                         [polaris10_power_state->performance_level_count++]);
3816         performance_level->memory_clock = mclk_dep_table->entries
3817                         [state_entry->ucMemoryClockIndexHigh].ulMclk;
3818
3819         if (sclk_dep_table->ucRevId == 0)
3820                 performance_level->engine_clock = ((ATOM_Tonga_SCLK_Dependency_Table *)sclk_dep_table)->entries
3821                         [state_entry->ucEngineClockIndexHigh].ulSclk;
3822         else if (sclk_dep_table->ucRevId == 1)
3823                 performance_level->engine_clock = ((ATOM_Polaris_SCLK_Dependency_Table *)sclk_dep_table)->entries
3824                         [state_entry->ucEngineClockIndexHigh].ulSclk;
3825
3826         performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap,
3827                         state_entry->ucPCIEGenHigh);
3828         performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap,
3829                         state_entry->ucPCIELaneHigh);
3830
3831         return 0;
3832 }
3833
3834 static int polaris10_get_pp_table_entry(struct pp_hwmgr *hwmgr,
3835                 unsigned long entry_index, struct pp_power_state *state)
3836 {
3837         int result;
3838         struct polaris10_power_state *ps;
3839         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3840         struct phm_ppt_v1_information *table_info =
3841                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
3842         struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
3843                         table_info->vdd_dep_on_mclk;
3844
3845         state->hardware.magic = PHM_VIslands_Magic;
3846
3847         ps = (struct polaris10_power_state *)(&state->hardware);
3848
3849         result = tonga_get_powerplay_table_entry(hwmgr, entry_index, state,
3850                         polaris10_get_pp_table_entry_callback_func);
3851
3852         /* This is the earliest time we have all the dependency table and the VBIOS boot state
3853          * as PP_Tables_GetPowerPlayTableEntry retrieves the VBIOS boot state
3854          * if there is only one VDDCI/MCLK level, check if it's the same as VBIOS boot state
3855          */
3856         if (dep_mclk_table != NULL && dep_mclk_table->count == 1) {
3857                 if (dep_mclk_table->entries[0].clk !=
3858                                 data->vbios_boot_state.mclk_bootup_value)
3859                         printk(KERN_ERR "Single MCLK entry VDDCI/MCLK dependency table "
3860                                         "does not match VBIOS boot MCLK level");
3861                 if (dep_mclk_table->entries[0].vddci !=
3862                                 data->vbios_boot_state.vddci_bootup_value)
3863                         printk(KERN_ERR "Single VDDCI entry VDDCI/MCLK dependency table "
3864                                         "does not match VBIOS boot VDDCI level");
3865         }
3866
3867         /* set DC compatible flag if this state supports DC */
3868         if (!state->validation.disallowOnDC)
3869                 ps->dc_compatible = true;
3870
3871         if (state->classification.flags & PP_StateClassificationFlag_ACPI)
3872                 data->acpi_pcie_gen = ps->performance_levels[0].pcie_gen;
3873
3874         ps->uvd_clks.vclk = state->uvd_clocks.VCLK;
3875         ps->uvd_clks.dclk = state->uvd_clocks.DCLK;
3876
3877         if (!result) {
3878                 uint32_t i;
3879
3880                 switch (state->classification.ui_label) {
3881                 case PP_StateUILabel_Performance:
3882                         data->use_pcie_performance_levels = true;
3883                         for (i = 0; i < ps->performance_level_count; i++) {
3884                                 if (data->pcie_gen_performance.max <
3885                                                 ps->performance_levels[i].pcie_gen)
3886                                         data->pcie_gen_performance.max =
3887                                                         ps->performance_levels[i].pcie_gen;
3888
3889                                 if (data->pcie_gen_performance.min >
3890                                                 ps->performance_levels[i].pcie_gen)
3891                                         data->pcie_gen_performance.min =
3892                                                         ps->performance_levels[i].pcie_gen;
3893
3894                                 if (data->pcie_lane_performance.max <
3895                                                 ps->performance_levels[i].pcie_lane)
3896                                         data->pcie_lane_performance.max =
3897                                                         ps->performance_levels[i].pcie_lane;
3898                                 if (data->pcie_lane_performance.min >
3899                                                 ps->performance_levels[i].pcie_lane)
3900                                         data->pcie_lane_performance.min =
3901                                                         ps->performance_levels[i].pcie_lane;
3902                         }
3903                         break;
3904                 case PP_StateUILabel_Battery:
3905                         data->use_pcie_power_saving_levels = true;
3906
3907                         for (i = 0; i < ps->performance_level_count; i++) {
3908                                 if (data->pcie_gen_power_saving.max <
3909                                                 ps->performance_levels[i].pcie_gen)
3910                                         data->pcie_gen_power_saving.max =
3911                                                         ps->performance_levels[i].pcie_gen;
3912
3913                                 if (data->pcie_gen_power_saving.min >
3914                                                 ps->performance_levels[i].pcie_gen)
3915                                         data->pcie_gen_power_saving.min =
3916                                                         ps->performance_levels[i].pcie_gen;
3917
3918                                 if (data->pcie_lane_power_saving.max <
3919                                                 ps->performance_levels[i].pcie_lane)
3920                                         data->pcie_lane_power_saving.max =
3921                                                         ps->performance_levels[i].pcie_lane;
3922
3923                                 if (data->pcie_lane_power_saving.min >
3924                                                 ps->performance_levels[i].pcie_lane)
3925                                         data->pcie_lane_power_saving.min =
3926                                                         ps->performance_levels[i].pcie_lane;
3927                         }
3928                         break;
3929                 default:
3930                         break;
3931                 }
3932         }
3933         return 0;
3934 }
3935
3936 static void
3937 polaris10_print_current_perforce_level(struct pp_hwmgr *hwmgr, struct seq_file *m)
3938 {
3939         uint32_t sclk, mclk, activity_percent;
3940         uint32_t offset;
3941         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3942
3943         smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency);
3944
3945         sclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
3946
3947         smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency);
3948
3949         mclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
3950         seq_printf(m, "\n [  mclk  ]: %u MHz\n\n [  sclk  ]: %u MHz\n",
3951                         mclk / 100, sclk / 100);
3952
3953         offset = data->soft_regs_start + offsetof(SMU74_SoftRegisters, AverageGraphicsActivity);
3954         activity_percent = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset);
3955         activity_percent += 0x80;
3956         activity_percent >>= 8;
3957
3958         seq_printf(m, "\n [GPU load]: %u%%\n\n", activity_percent > 100 ? 100 : activity_percent);
3959
3960         seq_printf(m, "uvd    %sabled\n", data->uvd_power_gated ? "dis" : "en");
3961
3962         seq_printf(m, "vce    %sabled\n", data->vce_power_gated ? "dis" : "en");
3963 }
3964
3965 static int polaris10_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input)
3966 {
3967         const struct phm_set_power_state_input *states =
3968                         (const struct phm_set_power_state_input *)input;
3969         const struct polaris10_power_state *polaris10_ps =
3970                         cast_const_phw_polaris10_power_state(states->pnew_state);
3971         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
3972         struct polaris10_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
3973         uint32_t sclk = polaris10_ps->performance_levels
3974                         [polaris10_ps->performance_level_count - 1].engine_clock;
3975         struct polaris10_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
3976         uint32_t mclk = polaris10_ps->performance_levels
3977                         [polaris10_ps->performance_level_count - 1].memory_clock;
3978         struct PP_Clocks min_clocks = {0};
3979         uint32_t i;
3980         struct cgs_display_info info = {0};
3981
3982         data->need_update_smu7_dpm_table = 0;
3983
3984         for (i = 0; i < sclk_table->count; i++) {
3985                 if (sclk == sclk_table->dpm_levels[i].value)
3986                         break;
3987         }
3988
3989         if (i >= sclk_table->count)
3990                 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
3991         else {
3992         /* TODO: Check SCLK in DAL's minimum clocks
3993          * in case DeepSleep divider update is required.
3994          */
3995                 if (data->display_timing.min_clock_in_sr != min_clocks.engineClockInSR &&
3996                         (min_clocks.engineClockInSR >= POLARIS10_MINIMUM_ENGINE_CLOCK ||
3997                                 data->display_timing.min_clock_in_sr >= POLARIS10_MINIMUM_ENGINE_CLOCK))
3998                         data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK;
3999         }
4000
4001         for (i = 0; i < mclk_table->count; i++) {
4002                 if (mclk == mclk_table->dpm_levels[i].value)
4003                         break;
4004         }
4005
4006         if (i >= mclk_table->count)
4007                 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
4008
4009         cgs_get_active_displays_info(hwmgr->device, &info);
4010
4011         if (data->display_timing.num_existing_displays != info.display_count)
4012                 data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK;
4013
4014         return 0;
4015 }
4016
4017 static uint16_t polaris10_get_maximum_link_speed(struct pp_hwmgr *hwmgr,
4018                 const struct polaris10_power_state *polaris10_ps)
4019 {
4020         uint32_t i;
4021         uint32_t sclk, max_sclk = 0;
4022         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4023         struct polaris10_dpm_table *dpm_table = &data->dpm_table;
4024
4025         for (i = 0; i < polaris10_ps->performance_level_count; i++) {
4026                 sclk = polaris10_ps->performance_levels[i].engine_clock;
4027                 if (max_sclk < sclk)
4028                         max_sclk = sclk;
4029         }
4030
4031         for (i = 0; i < dpm_table->sclk_table.count; i++) {
4032                 if (dpm_table->sclk_table.dpm_levels[i].value == max_sclk)
4033                         return (uint16_t) ((i >= dpm_table->pcie_speed_table.count) ?
4034                                         dpm_table->pcie_speed_table.dpm_levels
4035                                         [dpm_table->pcie_speed_table.count - 1].value :
4036                                         dpm_table->pcie_speed_table.dpm_levels[i].value);
4037         }
4038
4039         return 0;
4040 }
4041
4042 static int polaris10_request_link_speed_change_before_state_change(
4043                 struct pp_hwmgr *hwmgr, const void *input)
4044 {
4045         const struct phm_set_power_state_input *states =
4046                         (const struct phm_set_power_state_input *)input;
4047         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4048         const struct polaris10_power_state *polaris10_nps =
4049                         cast_const_phw_polaris10_power_state(states->pnew_state);
4050         const struct polaris10_power_state *polaris10_cps =
4051                         cast_const_phw_polaris10_power_state(states->pcurrent_state);
4052
4053         uint16_t target_link_speed = polaris10_get_maximum_link_speed(hwmgr, polaris10_nps);
4054         uint16_t current_link_speed;
4055
4056         if (data->force_pcie_gen == PP_PCIEGenInvalid)
4057                 current_link_speed = polaris10_get_maximum_link_speed(hwmgr, polaris10_cps);
4058         else
4059                 current_link_speed = data->force_pcie_gen;
4060
4061         data->force_pcie_gen = PP_PCIEGenInvalid;
4062         data->pspp_notify_required = false;
4063
4064         if (target_link_speed > current_link_speed) {
4065                 switch (target_link_speed) {
4066                 case PP_PCIEGen3:
4067                         if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN3, false))
4068                                 break;
4069                         data->force_pcie_gen = PP_PCIEGen2;
4070                         if (current_link_speed == PP_PCIEGen2)
4071                                 break;
4072                 case PP_PCIEGen2:
4073                         if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN2, false))
4074                                 break;
4075                 default:
4076                         data->force_pcie_gen = phm_get_current_pcie_speed(hwmgr);
4077                         break;
4078                 }
4079         } else {
4080                 if (target_link_speed < current_link_speed)
4081                         data->pspp_notify_required = true;
4082         }
4083
4084         return 0;
4085 }
4086
4087 static int polaris10_freeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
4088 {
4089         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4090
4091         if (0 == data->need_update_smu7_dpm_table)
4092                 return 0;
4093
4094         if ((0 == data->sclk_dpm_key_disabled) &&
4095                 (data->need_update_smu7_dpm_table &
4096                         (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
4097                 PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr),
4098                                 "Trying to freeze SCLK DPM when DPM is disabled",
4099                                 );
4100                 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4101                                 PPSMC_MSG_SCLKDPM_FreezeLevel),
4102                                 "Failed to freeze SCLK DPM during FreezeSclkMclkDPM Function!",
4103                                 return -1);
4104         }
4105
4106         if ((0 == data->mclk_dpm_key_disabled) &&
4107                 (data->need_update_smu7_dpm_table &
4108                  DPMTABLE_OD_UPDATE_MCLK)) {
4109                 PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr),
4110                                 "Trying to freeze MCLK DPM when DPM is disabled",
4111                                 );
4112                 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4113                                 PPSMC_MSG_MCLKDPM_FreezeLevel),
4114                                 "Failed to freeze MCLK DPM during FreezeSclkMclkDPM Function!",
4115                                 return -1);
4116         }
4117
4118         return 0;
4119 }
4120
4121 static int polaris10_populate_and_upload_sclk_mclk_dpm_levels(
4122                 struct pp_hwmgr *hwmgr, const void *input)
4123 {
4124         int result = 0;
4125         const struct phm_set_power_state_input *states =
4126                         (const struct phm_set_power_state_input *)input;
4127         const struct polaris10_power_state *polaris10_ps =
4128                         cast_const_phw_polaris10_power_state(states->pnew_state);
4129         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4130         uint32_t sclk = polaris10_ps->performance_levels
4131                         [polaris10_ps->performance_level_count - 1].engine_clock;
4132         uint32_t mclk = polaris10_ps->performance_levels
4133                         [polaris10_ps->performance_level_count - 1].memory_clock;
4134         struct polaris10_dpm_table *dpm_table = &data->dpm_table;
4135
4136         struct polaris10_dpm_table *golden_dpm_table = &data->golden_dpm_table;
4137         uint32_t dpm_count, clock_percent;
4138         uint32_t i;
4139
4140         if (0 == data->need_update_smu7_dpm_table)
4141                 return 0;
4142
4143         if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) {
4144                 dpm_table->sclk_table.dpm_levels
4145                 [dpm_table->sclk_table.count - 1].value = sclk;
4146
4147                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) ||
4148                     phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) {
4149                 /* Need to do calculation based on the golden DPM table
4150                  * as the Heatmap GPU Clock axis is also based on the default values
4151                  */
4152                         PP_ASSERT_WITH_CODE(
4153                                 (golden_dpm_table->sclk_table.dpm_levels
4154                                                 [golden_dpm_table->sclk_table.count - 1].value != 0),
4155                                 "Divide by 0!",
4156                                 return -1);
4157                         dpm_count = dpm_table->sclk_table.count < 2 ? 0 : dpm_table->sclk_table.count - 2;
4158
4159                         for (i = dpm_count; i > 1; i--) {
4160                                 if (sclk > golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value) {
4161                                         clock_percent =
4162                                               ((sclk
4163                                                 - golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value
4164                                                 ) * 100)
4165                                                 / golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value;
4166
4167                                         dpm_table->sclk_table.dpm_levels[i].value =
4168                                                         golden_dpm_table->sclk_table.dpm_levels[i].value +
4169                                                         (golden_dpm_table->sclk_table.dpm_levels[i].value *
4170                                                                 clock_percent)/100;
4171
4172                                 } else if (golden_dpm_table->sclk_table.dpm_levels[dpm_table->sclk_table.count-1].value > sclk) {
4173                                         clock_percent =
4174                                                 ((golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count - 1].value
4175                                                 - sclk) * 100)
4176                                                 / golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value;
4177
4178                                         dpm_table->sclk_table.dpm_levels[i].value =
4179                                                         golden_dpm_table->sclk_table.dpm_levels[i].value -
4180                                                         (golden_dpm_table->sclk_table.dpm_levels[i].value *
4181                                                                         clock_percent) / 100;
4182                                 } else
4183                                         dpm_table->sclk_table.dpm_levels[i].value =
4184                                                         golden_dpm_table->sclk_table.dpm_levels[i].value;
4185                         }
4186                 }
4187         }
4188
4189         if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) {
4190                 dpm_table->mclk_table.dpm_levels
4191                         [dpm_table->mclk_table.count - 1].value = mclk;
4192
4193                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) ||
4194                     phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) {
4195
4196                         PP_ASSERT_WITH_CODE(
4197                                         (golden_dpm_table->mclk_table.dpm_levels
4198                                                 [golden_dpm_table->mclk_table.count-1].value != 0),
4199                                         "Divide by 0!",
4200                                         return -1);
4201                         dpm_count = dpm_table->mclk_table.count < 2 ? 0 : dpm_table->mclk_table.count - 2;
4202                         for (i = dpm_count; i > 1; i--) {
4203                                 if (golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value < mclk) {
4204                                         clock_percent = ((mclk -
4205                                         golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value) * 100)
4206                                         / golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value;
4207
4208                                         dpm_table->mclk_table.dpm_levels[i].value =
4209                                                         golden_dpm_table->mclk_table.dpm_levels[i].value +
4210                                                         (golden_dpm_table->mclk_table.dpm_levels[i].value *
4211                                                         clock_percent) / 100;
4212
4213                                 } else if (golden_dpm_table->mclk_table.dpm_levels[dpm_table->mclk_table.count-1].value > mclk) {
4214                                         clock_percent = (
4215                                          (golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value - mclk)
4216                                         * 100)
4217                                         / golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value;
4218
4219                                         dpm_table->mclk_table.dpm_levels[i].value =
4220                                                         golden_dpm_table->mclk_table.dpm_levels[i].value -
4221                                                         (golden_dpm_table->mclk_table.dpm_levels[i].value *
4222                                                                         clock_percent) / 100;
4223                                 } else
4224                                         dpm_table->mclk_table.dpm_levels[i].value =
4225                                                         golden_dpm_table->mclk_table.dpm_levels[i].value;
4226                         }
4227                 }
4228         }
4229
4230         if (data->need_update_smu7_dpm_table &
4231                         (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK)) {
4232                 result = polaris10_populate_all_graphic_levels(hwmgr);
4233                 PP_ASSERT_WITH_CODE((0 == result),
4234                                 "Failed to populate SCLK during PopulateNewDPMClocksStates Function!",
4235                                 return result);
4236         }
4237
4238         if (data->need_update_smu7_dpm_table &
4239                         (DPMTABLE_OD_UPDATE_MCLK + DPMTABLE_UPDATE_MCLK)) {
4240                 /*populate MCLK dpm table to SMU7 */
4241                 result = polaris10_populate_all_memory_levels(hwmgr);
4242                 PP_ASSERT_WITH_CODE((0 == result),
4243                                 "Failed to populate MCLK during PopulateNewDPMClocksStates Function!",
4244                                 return result);
4245         }
4246
4247         return result;
4248 }
4249
4250 static int polaris10_trim_single_dpm_states(struct pp_hwmgr *hwmgr,
4251                           struct polaris10_single_dpm_table *dpm_table,
4252                         uint32_t low_limit, uint32_t high_limit)
4253 {
4254         uint32_t i;
4255
4256         for (i = 0; i < dpm_table->count; i++) {
4257                 if ((dpm_table->dpm_levels[i].value < low_limit)
4258                 || (dpm_table->dpm_levels[i].value > high_limit))
4259                         dpm_table->dpm_levels[i].enabled = false;
4260                 else
4261                         dpm_table->dpm_levels[i].enabled = true;
4262         }
4263
4264         return 0;
4265 }
4266
4267 static int polaris10_trim_dpm_states(struct pp_hwmgr *hwmgr,
4268                 const struct polaris10_power_state *polaris10_ps)
4269 {
4270         int result = 0;
4271         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4272         uint32_t high_limit_count;
4273
4274         PP_ASSERT_WITH_CODE((polaris10_ps->performance_level_count >= 1),
4275                         "power state did not have any performance level",
4276                         return -1);
4277
4278         high_limit_count = (1 == polaris10_ps->performance_level_count) ? 0 : 1;
4279
4280         polaris10_trim_single_dpm_states(hwmgr,
4281                         &(data->dpm_table.sclk_table),
4282                         polaris10_ps->performance_levels[0].engine_clock,
4283                         polaris10_ps->performance_levels[high_limit_count].engine_clock);
4284
4285         polaris10_trim_single_dpm_states(hwmgr,
4286                         &(data->dpm_table.mclk_table),
4287                         polaris10_ps->performance_levels[0].memory_clock,
4288                         polaris10_ps->performance_levels[high_limit_count].memory_clock);
4289
4290         return result;
4291 }
4292
4293 static int polaris10_generate_dpm_level_enable_mask(
4294                 struct pp_hwmgr *hwmgr, const void *input)
4295 {
4296         int result;
4297         const struct phm_set_power_state_input *states =
4298                         (const struct phm_set_power_state_input *)input;
4299         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4300         const struct polaris10_power_state *polaris10_ps =
4301                         cast_const_phw_polaris10_power_state(states->pnew_state);
4302
4303         result = polaris10_trim_dpm_states(hwmgr, polaris10_ps);
4304         if (result)
4305                 return result;
4306
4307         data->dpm_level_enable_mask.sclk_dpm_enable_mask =
4308                         phm_get_dpm_level_enable_mask_value(&data->dpm_table.sclk_table);
4309         data->dpm_level_enable_mask.mclk_dpm_enable_mask =
4310                         phm_get_dpm_level_enable_mask_value(&data->dpm_table.mclk_table);
4311         data->dpm_level_enable_mask.pcie_dpm_enable_mask =
4312                         phm_get_dpm_level_enable_mask_value(&data->dpm_table.pcie_speed_table);
4313
4314         return 0;
4315 }
4316
4317 int polaris10_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
4318 {
4319         return smum_send_msg_to_smc(hwmgr->smumgr, enable ?
4320                         PPSMC_MSG_UVDDPM_Enable :
4321                         PPSMC_MSG_UVDDPM_Disable);
4322 }
4323
4324 int polaris10_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
4325 {
4326         return smum_send_msg_to_smc(hwmgr->smumgr, enable?
4327                         PPSMC_MSG_VCEDPM_Enable :
4328                         PPSMC_MSG_VCEDPM_Disable);
4329 }
4330
4331 int polaris10_enable_disable_samu_dpm(struct pp_hwmgr *hwmgr, bool enable)
4332 {
4333         return smum_send_msg_to_smc(hwmgr->smumgr, enable?
4334                         PPSMC_MSG_SAMUDPM_Enable :
4335                         PPSMC_MSG_SAMUDPM_Disable);
4336 }
4337
4338 int polaris10_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate)
4339 {
4340         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4341         uint32_t mm_boot_level_offset, mm_boot_level_value;
4342         struct phm_ppt_v1_information *table_info =
4343                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
4344
4345         if (!bgate) {
4346                 data->smc_state_table.UvdBootLevel = 0;
4347                 if (table_info->mm_dep_table->count > 0)
4348                         data->smc_state_table.UvdBootLevel =
4349                                         (uint8_t) (table_info->mm_dep_table->count - 1);
4350                 mm_boot_level_offset = data->dpm_table_start +
4351                                 offsetof(SMU74_Discrete_DpmTable, UvdBootLevel);
4352                 mm_boot_level_offset /= 4;
4353                 mm_boot_level_offset *= 4;
4354                 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
4355                                 CGS_IND_REG__SMC, mm_boot_level_offset);
4356                 mm_boot_level_value &= 0x00FFFFFF;
4357                 mm_boot_level_value |= data->smc_state_table.UvdBootLevel << 24;
4358                 cgs_write_ind_register(hwmgr->device,
4359                                 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
4360
4361                 if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4362                                 PHM_PlatformCaps_UVDDPM) ||
4363                         phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4364                                 PHM_PlatformCaps_StablePState))
4365                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4366                                         PPSMC_MSG_UVDDPM_SetEnabledMask,
4367                                         (uint32_t)(1 << data->smc_state_table.UvdBootLevel));
4368         }
4369
4370         return polaris10_enable_disable_uvd_dpm(hwmgr, !bgate);
4371 }
4372
4373 static int polaris10_update_vce_dpm(struct pp_hwmgr *hwmgr, const void *input)
4374 {
4375         const struct phm_set_power_state_input *states =
4376                         (const struct phm_set_power_state_input *)input;
4377         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4378         const struct polaris10_power_state *polaris10_nps =
4379                         cast_const_phw_polaris10_power_state(states->pnew_state);
4380         const struct polaris10_power_state *polaris10_cps =
4381                         cast_const_phw_polaris10_power_state(states->pcurrent_state);
4382
4383         uint32_t mm_boot_level_offset, mm_boot_level_value;
4384         struct phm_ppt_v1_information *table_info =
4385                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
4386
4387         if (polaris10_nps->vce_clks.evclk > 0 &&
4388         (polaris10_cps == NULL || polaris10_cps->vce_clks.evclk == 0)) {
4389
4390                 data->smc_state_table.VceBootLevel =
4391                                 (uint8_t) (table_info->mm_dep_table->count - 1);
4392
4393                 mm_boot_level_offset = data->dpm_table_start +
4394                                 offsetof(SMU74_Discrete_DpmTable, VceBootLevel);
4395                 mm_boot_level_offset /= 4;
4396                 mm_boot_level_offset *= 4;
4397                 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
4398                                 CGS_IND_REG__SMC, mm_boot_level_offset);
4399                 mm_boot_level_value &= 0xFF00FFFF;
4400                 mm_boot_level_value |= data->smc_state_table.VceBootLevel << 16;
4401                 cgs_write_ind_register(hwmgr->device,
4402                                 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
4403
4404                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState)) {
4405                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4406                                         PPSMC_MSG_VCEDPM_SetEnabledMask,
4407                                         (uint32_t)1 << data->smc_state_table.VceBootLevel);
4408
4409                         polaris10_enable_disable_vce_dpm(hwmgr, true);
4410                 } else if (polaris10_nps->vce_clks.evclk == 0 &&
4411                                 polaris10_cps != NULL &&
4412                                 polaris10_cps->vce_clks.evclk > 0)
4413                         polaris10_enable_disable_vce_dpm(hwmgr, false);
4414         }
4415
4416         return 0;
4417 }
4418
4419 int polaris10_update_samu_dpm(struct pp_hwmgr *hwmgr, bool bgate)
4420 {
4421         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4422         uint32_t mm_boot_level_offset, mm_boot_level_value;
4423
4424         if (!bgate) {
4425                 data->smc_state_table.SamuBootLevel = 0;
4426                 mm_boot_level_offset = data->dpm_table_start +
4427                                 offsetof(SMU74_Discrete_DpmTable, SamuBootLevel);
4428                 mm_boot_level_offset /= 4;
4429                 mm_boot_level_offset *= 4;
4430                 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
4431                                 CGS_IND_REG__SMC, mm_boot_level_offset);
4432                 mm_boot_level_value &= 0xFFFFFF00;
4433                 mm_boot_level_value |= data->smc_state_table.SamuBootLevel << 0;
4434                 cgs_write_ind_register(hwmgr->device,
4435                                 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
4436
4437                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4438                                 PHM_PlatformCaps_StablePState))
4439                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4440                                         PPSMC_MSG_SAMUDPM_SetEnabledMask,
4441                                         (uint32_t)(1 << data->smc_state_table.SamuBootLevel));
4442         }
4443
4444         return polaris10_enable_disable_samu_dpm(hwmgr, !bgate);
4445 }
4446
4447 static int polaris10_update_sclk_threshold(struct pp_hwmgr *hwmgr)
4448 {
4449         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4450
4451         int result = 0;
4452         uint32_t low_sclk_interrupt_threshold = 0;
4453
4454         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4455                         PHM_PlatformCaps_SclkThrottleLowNotification)
4456                 && (hwmgr->gfx_arbiter.sclk_threshold !=
4457                                 data->low_sclk_interrupt_threshold)) {
4458                 data->low_sclk_interrupt_threshold =
4459                                 hwmgr->gfx_arbiter.sclk_threshold;
4460                 low_sclk_interrupt_threshold =
4461                                 data->low_sclk_interrupt_threshold;
4462
4463                 CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
4464
4465                 result = polaris10_copy_bytes_to_smc(
4466                                 hwmgr->smumgr,
4467                                 data->dpm_table_start +
4468                                 offsetof(SMU74_Discrete_DpmTable,
4469                                         LowSclkInterruptThreshold),
4470                                 (uint8_t *)&low_sclk_interrupt_threshold,
4471                                 sizeof(uint32_t),
4472                                 data->sram_end);
4473         }
4474
4475         return result;
4476 }
4477
4478 static int polaris10_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
4479 {
4480         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4481
4482         if (data->need_update_smu7_dpm_table &
4483                 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK))
4484                 return polaris10_program_memory_timing_parameters(hwmgr);
4485
4486         return 0;
4487 }
4488
4489 static int polaris10_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
4490 {
4491         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4492
4493         if (0 == data->need_update_smu7_dpm_table)
4494                 return 0;
4495
4496         if ((0 == data->sclk_dpm_key_disabled) &&
4497                 (data->need_update_smu7_dpm_table &
4498                 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
4499
4500                 PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr),
4501                                 "Trying to Unfreeze SCLK DPM when DPM is disabled",
4502                                 );
4503                 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4504                                 PPSMC_MSG_SCLKDPM_UnfreezeLevel),
4505                         "Failed to unfreeze SCLK DPM during UnFreezeSclkMclkDPM Function!",
4506                         return -1);
4507         }
4508
4509         if ((0 == data->mclk_dpm_key_disabled) &&
4510                 (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
4511
4512                 PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr),
4513                                 "Trying to Unfreeze MCLK DPM when DPM is disabled",
4514                                 );
4515                 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4516                                 PPSMC_MSG_SCLKDPM_UnfreezeLevel),
4517                     "Failed to unfreeze MCLK DPM during UnFreezeSclkMclkDPM Function!",
4518                     return -1);
4519         }
4520
4521         data->need_update_smu7_dpm_table = 0;
4522
4523         return 0;
4524 }
4525
4526 static int polaris10_notify_link_speed_change_after_state_change(
4527                 struct pp_hwmgr *hwmgr, const void *input)
4528 {
4529         const struct phm_set_power_state_input *states =
4530                         (const struct phm_set_power_state_input *)input;
4531         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4532         const struct polaris10_power_state *polaris10_ps =
4533                         cast_const_phw_polaris10_power_state(states->pnew_state);
4534         uint16_t target_link_speed = polaris10_get_maximum_link_speed(hwmgr, polaris10_ps);
4535         uint8_t  request;
4536
4537         if (data->pspp_notify_required) {
4538                 if (target_link_speed == PP_PCIEGen3)
4539                         request = PCIE_PERF_REQ_GEN3;
4540                 else if (target_link_speed == PP_PCIEGen2)
4541                         request = PCIE_PERF_REQ_GEN2;
4542                 else
4543                         request = PCIE_PERF_REQ_GEN1;
4544
4545                 if (request == PCIE_PERF_REQ_GEN1 &&
4546                                 phm_get_current_pcie_speed(hwmgr) > 0)
4547                         return 0;
4548
4549                 if (acpi_pcie_perf_request(hwmgr->device, request, false)) {
4550                         if (PP_PCIEGen2 == target_link_speed)
4551                                 printk("PSPP request to switch to Gen2 from Gen3 Failed!");
4552                         else
4553                                 printk("PSPP request to switch to Gen1 from Gen2 Failed!");
4554                 }
4555         }
4556
4557         return 0;
4558 }
4559
4560 static int polaris10_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input)
4561 {
4562         int tmp_result, result = 0;
4563         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4564
4565         tmp_result = polaris10_find_dpm_states_clocks_in_dpm_table(hwmgr, input);
4566         PP_ASSERT_WITH_CODE((0 == tmp_result),
4567                         "Failed to find DPM states clocks in DPM table!",
4568                         result = tmp_result);
4569
4570         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4571                         PHM_PlatformCaps_PCIEPerformanceRequest)) {
4572                 tmp_result =
4573                         polaris10_request_link_speed_change_before_state_change(hwmgr, input);
4574                 PP_ASSERT_WITH_CODE((0 == tmp_result),
4575                                 "Failed to request link speed change before state change!",
4576                                 result = tmp_result);
4577         }
4578
4579         tmp_result = polaris10_freeze_sclk_mclk_dpm(hwmgr);
4580         PP_ASSERT_WITH_CODE((0 == tmp_result),
4581                         "Failed to freeze SCLK MCLK DPM!", result = tmp_result);
4582
4583         tmp_result = polaris10_populate_and_upload_sclk_mclk_dpm_levels(hwmgr, input);
4584         PP_ASSERT_WITH_CODE((0 == tmp_result),
4585                         "Failed to populate and upload SCLK MCLK DPM levels!",
4586                         result = tmp_result);
4587
4588         tmp_result = polaris10_generate_dpm_level_enable_mask(hwmgr, input);
4589         PP_ASSERT_WITH_CODE((0 == tmp_result),
4590                         "Failed to generate DPM level enabled mask!",
4591                         result = tmp_result);
4592
4593         tmp_result = polaris10_update_vce_dpm(hwmgr, input);
4594         PP_ASSERT_WITH_CODE((0 == tmp_result),
4595                         "Failed to update VCE DPM!",
4596                         result = tmp_result);
4597
4598         tmp_result = polaris10_update_sclk_threshold(hwmgr);
4599         PP_ASSERT_WITH_CODE((0 == tmp_result),
4600                         "Failed to update SCLK threshold!",
4601                         result = tmp_result);
4602
4603         tmp_result = polaris10_program_mem_timing_parameters(hwmgr);
4604         PP_ASSERT_WITH_CODE((0 == tmp_result),
4605                         "Failed to program memory timing parameters!",
4606                         result = tmp_result);
4607
4608         tmp_result = polaris10_unfreeze_sclk_mclk_dpm(hwmgr);
4609         PP_ASSERT_WITH_CODE((0 == tmp_result),
4610                         "Failed to unfreeze SCLK MCLK DPM!",
4611                         result = tmp_result);
4612
4613         tmp_result = polaris10_upload_dpm_level_enable_mask(hwmgr);
4614         PP_ASSERT_WITH_CODE((0 == tmp_result),
4615                         "Failed to upload DPM level enabled mask!",
4616                         result = tmp_result);
4617
4618         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4619                         PHM_PlatformCaps_PCIEPerformanceRequest)) {
4620                 tmp_result =
4621                         polaris10_notify_link_speed_change_after_state_change(hwmgr, input);
4622                 PP_ASSERT_WITH_CODE((0 == tmp_result),
4623                                 "Failed to notify link speed change after state change!",
4624                                 result = tmp_result);
4625         }
4626         data->apply_optimized_settings = false;
4627         return result;
4628 }
4629
4630 static int polaris10_set_max_fan_pwm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm)
4631 {
4632         hwmgr->thermal_controller.
4633         advanceFanControlParameters.usMaxFanPWM = us_max_fan_pwm;
4634
4635         if (phm_is_hw_access_blocked(hwmgr))
4636                 return 0;
4637
4638         return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4639                         PPSMC_MSG_SetFanPwmMax, us_max_fan_pwm);
4640 }
4641
4642 int polaris10_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display)
4643 {
4644         PPSMC_Msg msg = has_display ? (PPSMC_Msg)PPSMC_HasDisplay : (PPSMC_Msg)PPSMC_NoDisplay;
4645
4646         return (smum_send_msg_to_smc(hwmgr->smumgr, msg) == 0) ?  0 : -1;
4647 }
4648
4649 int polaris10_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
4650 {
4651         uint32_t num_active_displays = 0;
4652         struct cgs_display_info info = {0};
4653         info.mode_info = NULL;
4654
4655         cgs_get_active_displays_info(hwmgr->device, &info);
4656
4657         num_active_displays = info.display_count;
4658
4659         if (num_active_displays > 1)  /* to do && (pHwMgr->pPECI->displayConfiguration.bMultiMonitorInSync != TRUE)) */
4660                 polaris10_notify_smc_display_change(hwmgr, false);
4661         else
4662                 polaris10_notify_smc_display_change(hwmgr, true);
4663
4664         return 0;
4665 }
4666
4667 /**
4668 * Programs the display gap
4669 *
4670 * @param    hwmgr  the address of the powerplay hardware manager.
4671 * @return   always OK
4672 */
4673 int polaris10_program_display_gap(struct pp_hwmgr *hwmgr)
4674 {
4675         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4676         uint32_t num_active_displays = 0;
4677         uint32_t display_gap = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL);
4678         uint32_t display_gap2;
4679         uint32_t pre_vbi_time_in_us;
4680         uint32_t frame_time_in_us;
4681         uint32_t ref_clock;
4682         uint32_t refresh_rate = 0;
4683         struct cgs_display_info info = {0};
4684         struct cgs_mode_info mode_info;
4685
4686         info.mode_info = &mode_info;
4687
4688         cgs_get_active_displays_info(hwmgr->device, &info);
4689         num_active_displays = info.display_count;
4690
4691         display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL, DISP_GAP, (num_active_displays > 0) ? DISPLAY_GAP_VBLANK_OR_WM : DISPLAY_GAP_IGNORE);
4692         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL, display_gap);
4693
4694         ref_clock = mode_info.ref_clock;
4695         refresh_rate = mode_info.refresh_rate;
4696
4697         if (0 == refresh_rate)
4698                 refresh_rate = 60;
4699
4700         frame_time_in_us = 1000000 / refresh_rate;
4701
4702         pre_vbi_time_in_us = frame_time_in_us - 200 - mode_info.vblank_time_us;
4703         display_gap2 = pre_vbi_time_in_us * (ref_clock / 100);
4704
4705         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL2, display_gap2);
4706
4707         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start + offsetof(SMU74_SoftRegisters, PreVBlankGap), 0x64);
4708
4709         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start + offsetof(SMU74_SoftRegisters, VBlankTimeout), (frame_time_in_us - pre_vbi_time_in_us));
4710
4711         polaris10_notify_smc_display_change(hwmgr, num_active_displays != 0);
4712
4713         return 0;
4714 }
4715
4716
4717 int polaris10_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
4718 {
4719         return polaris10_program_display_gap(hwmgr);
4720 }
4721
4722 /**
4723 *  Set maximum target operating fan output RPM
4724 *
4725 * @param    hwmgr:  the address of the powerplay hardware manager.
4726 * @param    usMaxFanRpm:  max operating fan RPM value.
4727 * @return   The response that came from the SMC.
4728 */
4729 static int polaris10_set_max_fan_rpm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_rpm)
4730 {
4731         hwmgr->thermal_controller.
4732         advanceFanControlParameters.usMaxFanRPM = us_max_fan_rpm;
4733
4734         if (phm_is_hw_access_blocked(hwmgr))
4735                 return 0;
4736
4737         return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4738                         PPSMC_MSG_SetFanRpmMax, us_max_fan_rpm);
4739 }
4740
4741 int polaris10_register_internal_thermal_interrupt(struct pp_hwmgr *hwmgr,
4742                                         const void *thermal_interrupt_info)
4743 {
4744         return 0;
4745 }
4746
4747 bool polaris10_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
4748 {
4749         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4750         bool is_update_required = false;
4751         struct cgs_display_info info = {0, 0, NULL};
4752
4753         cgs_get_active_displays_info(hwmgr->device, &info);
4754
4755         if (data->display_timing.num_existing_displays != info.display_count)
4756                 is_update_required = true;
4757 /* TO DO NEED TO GET DEEP SLEEP CLOCK FROM DAL
4758         if (phm_cap_enabled(hwmgr->hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
4759                 cgs_get_min_clock_settings(hwmgr->device, &min_clocks);
4760                 if (min_clocks.engineClockInSR != data->display_timing.minClockInSR &&
4761                         (min_clocks.engineClockInSR >= POLARIS10_MINIMUM_ENGINE_CLOCK ||
4762                                 data->display_timing.minClockInSR >= POLARIS10_MINIMUM_ENGINE_CLOCK))
4763                         is_update_required = true;
4764 */
4765         return is_update_required;
4766 }
4767
4768 static inline bool polaris10_are_power_levels_equal(const struct polaris10_performance_level *pl1,
4769                                                            const struct polaris10_performance_level *pl2)
4770 {
4771         return ((pl1->memory_clock == pl2->memory_clock) &&
4772                   (pl1->engine_clock == pl2->engine_clock) &&
4773                   (pl1->pcie_gen == pl2->pcie_gen) &&
4774                   (pl1->pcie_lane == pl2->pcie_lane));
4775 }
4776
4777 int polaris10_check_states_equal(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *pstate1, const struct pp_hw_power_state *pstate2, bool *equal)
4778 {
4779         const struct polaris10_power_state *psa = cast_const_phw_polaris10_power_state(pstate1);
4780         const struct polaris10_power_state *psb = cast_const_phw_polaris10_power_state(pstate2);
4781         int i;
4782
4783         if (pstate1 == NULL || pstate2 == NULL || equal == NULL)
4784                 return -EINVAL;
4785
4786         /* If the two states don't even have the same number of performance levels they cannot be the same state. */
4787         if (psa->performance_level_count != psb->performance_level_count) {
4788                 *equal = false;
4789                 return 0;
4790         }
4791
4792         for (i = 0; i < psa->performance_level_count; i++) {
4793                 if (!polaris10_are_power_levels_equal(&(psa->performance_levels[i]), &(psb->performance_levels[i]))) {
4794                         /* If we have found even one performance level pair that is different the states are different. */
4795                         *equal = false;
4796                         return 0;
4797                 }
4798         }
4799
4800         /* If all performance levels are the same try to use the UVD clocks to break the tie.*/
4801         *equal = ((psa->uvd_clks.vclk == psb->uvd_clks.vclk) && (psa->uvd_clks.dclk == psb->uvd_clks.dclk));
4802         *equal &= ((psa->vce_clks.evclk == psb->vce_clks.evclk) && (psa->vce_clks.ecclk == psb->vce_clks.ecclk));
4803         *equal &= (psa->sclk_threshold == psb->sclk_threshold);
4804
4805         return 0;
4806 }
4807
4808 int polaris10_upload_mc_firmware(struct pp_hwmgr *hwmgr)
4809 {
4810         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4811
4812         uint32_t vbios_version;
4813
4814         /*  Read MC indirect register offset 0x9F bits [3:0] to see if VBIOS has already loaded a full version of MC ucode or not.*/
4815
4816         phm_get_mc_microcode_version(hwmgr);
4817         vbios_version = hwmgr->microcode_version_info.MC & 0xf;
4818         /*  Full version of MC ucode has already been loaded. */
4819         if (vbios_version == 0) {
4820                 data->need_long_memory_training = false;
4821                 return 0;
4822         }
4823
4824         data->need_long_memory_training = true;
4825
4826 /*
4827  *      PPMCME_FirmwareDescriptorEntry *pfd = NULL;
4828         pfd = &tonga_mcmeFirmware;
4829         if (0 == PHM_READ_FIELD(hwmgr->device, MC_SEQ_SUP_CNTL, RUN))
4830                 polaris10_load_mc_microcode(hwmgr, pfd->dpmThreshold,
4831                                         pfd->cfgArray, pfd->cfgSize, pfd->ioDebugArray,
4832                                         pfd->ioDebugSize, pfd->ucodeArray, pfd->ucodeSize);
4833 */
4834         return 0;
4835 }
4836
4837 /**
4838  * Read clock related registers.
4839  *
4840  * @param    hwmgr  the address of the powerplay hardware manager.
4841  * @return   always 0
4842  */
4843 static int polaris10_read_clock_registers(struct pp_hwmgr *hwmgr)
4844 {
4845         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4846
4847         data->clock_registers.vCG_SPLL_FUNC_CNTL = cgs_read_ind_register(hwmgr->device,
4848                                                 CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL)
4849                                                 & CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK;
4850
4851         data->clock_registers.vCG_SPLL_FUNC_CNTL_2 = cgs_read_ind_register(hwmgr->device,
4852                                                 CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_2)
4853                                                 & CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL_MASK;
4854
4855         data->clock_registers.vCG_SPLL_FUNC_CNTL_4 = cgs_read_ind_register(hwmgr->device,
4856                                                 CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_4)
4857                                                 & CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_MASK;
4858
4859         return 0;
4860 }
4861
4862 /**
4863  * Find out if memory is GDDR5.
4864  *
4865  * @param    hwmgr  the address of the powerplay hardware manager.
4866  * @return   always 0
4867  */
4868 static int polaris10_get_memory_type(struct pp_hwmgr *hwmgr)
4869 {
4870         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4871         uint32_t temp;
4872
4873         temp = cgs_read_register(hwmgr->device, mmMC_SEQ_MISC0);
4874
4875         data->is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE ==
4876                         ((temp & MC_SEQ_MISC0_GDDR5_MASK) >>
4877                          MC_SEQ_MISC0_GDDR5_SHIFT));
4878
4879         return 0;
4880 }
4881
4882 /**
4883  * Enables Dynamic Power Management by SMC
4884  *
4885  * @param    hwmgr  the address of the powerplay hardware manager.
4886  * @return   always 0
4887  */
4888 static int polaris10_enable_acpi_power_management(struct pp_hwmgr *hwmgr)
4889 {
4890         PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
4891                         GENERAL_PWRMGT, STATIC_PM_EN, 1);
4892
4893         return 0;
4894 }
4895
4896 /**
4897  * Initialize PowerGating States for different engines
4898  *
4899  * @param    hwmgr  the address of the powerplay hardware manager.
4900  * @return   always 0
4901  */
4902 static int polaris10_init_power_gate_state(struct pp_hwmgr *hwmgr)
4903 {
4904         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4905
4906         data->uvd_power_gated = false;
4907         data->vce_power_gated = false;
4908         data->samu_power_gated = false;
4909
4910         return 0;
4911 }
4912
4913 static int polaris10_init_sclk_threshold(struct pp_hwmgr *hwmgr)
4914 {
4915         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4916         data->low_sclk_interrupt_threshold = 0;
4917
4918         return 0;
4919 }
4920
4921 int polaris10_setup_asic_task(struct pp_hwmgr *hwmgr)
4922 {
4923         int tmp_result, result = 0;
4924
4925         polaris10_upload_mc_firmware(hwmgr);
4926
4927         tmp_result = polaris10_read_clock_registers(hwmgr);
4928         PP_ASSERT_WITH_CODE((0 == tmp_result),
4929                         "Failed to read clock registers!", result = tmp_result);
4930
4931         tmp_result = polaris10_get_memory_type(hwmgr);
4932         PP_ASSERT_WITH_CODE((0 == tmp_result),
4933                         "Failed to get memory type!", result = tmp_result);
4934
4935         tmp_result = polaris10_enable_acpi_power_management(hwmgr);
4936         PP_ASSERT_WITH_CODE((0 == tmp_result),
4937                         "Failed to enable ACPI power management!", result = tmp_result);
4938
4939         tmp_result = polaris10_init_power_gate_state(hwmgr);
4940         PP_ASSERT_WITH_CODE((0 == tmp_result),
4941                         "Failed to init power gate state!", result = tmp_result);
4942
4943         tmp_result = phm_get_mc_microcode_version(hwmgr);
4944         PP_ASSERT_WITH_CODE((0 == tmp_result),
4945                         "Failed to get MC microcode version!", result = tmp_result);
4946
4947         tmp_result = polaris10_init_sclk_threshold(hwmgr);
4948         PP_ASSERT_WITH_CODE((0 == tmp_result),
4949                         "Failed to init sclk threshold!", result = tmp_result);
4950
4951         return result;
4952 }
4953
4954 static int polaris10_force_clock_level(struct pp_hwmgr *hwmgr,
4955                 enum pp_clock_type type, uint32_t mask)
4956 {
4957         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
4958
4959         if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
4960                 return -EINVAL;
4961
4962         switch (type) {
4963         case PP_SCLK:
4964                 if (!data->sclk_dpm_key_disabled)
4965                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4966                                         PPSMC_MSG_SCLKDPM_SetEnabledMask,
4967                                         data->dpm_level_enable_mask.sclk_dpm_enable_mask & mask);
4968                 break;
4969         case PP_MCLK:
4970                 if (!data->mclk_dpm_key_disabled)
4971                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4972                                         PPSMC_MSG_MCLKDPM_SetEnabledMask,
4973                                         data->dpm_level_enable_mask.mclk_dpm_enable_mask & mask);
4974                 break;
4975         case PP_PCIE:
4976         {
4977                 uint32_t tmp = mask & data->dpm_level_enable_mask.pcie_dpm_enable_mask;
4978                 uint32_t level = 0;
4979
4980                 while (tmp >>= 1)
4981                         level++;
4982
4983                 if (!data->pcie_dpm_key_disabled)
4984                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4985                                         PPSMC_MSG_PCIeDPM_ForceLevel,
4986                                         level);
4987                 break;
4988         }
4989         default:
4990                 break;
4991         }
4992
4993         return 0;
4994 }
4995
4996 static uint16_t polaris10_get_current_pcie_speed(struct pp_hwmgr *hwmgr)
4997 {
4998         uint32_t speedCntl = 0;
4999
5000         /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
5001         speedCntl = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__PCIE,
5002                         ixPCIE_LC_SPEED_CNTL);
5003         return((uint16_t)PHM_GET_FIELD(speedCntl,
5004                         PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE));
5005 }
5006
5007 static int polaris10_print_clock_levels(struct pp_hwmgr *hwmgr,
5008                 enum pp_clock_type type, char *buf)
5009 {
5010         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
5011         struct polaris10_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
5012         struct polaris10_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
5013         struct polaris10_single_dpm_table *pcie_table = &(data->dpm_table.pcie_speed_table);
5014         int i, now, size = 0;
5015         uint32_t clock, pcie_speed;
5016
5017         switch (type) {
5018         case PP_SCLK:
5019                 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency);
5020                 clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
5021
5022                 for (i = 0; i < sclk_table->count; i++) {
5023                         if (clock > sclk_table->dpm_levels[i].value)
5024                                 continue;
5025                         break;
5026                 }
5027                 now = i;
5028
5029                 for (i = 0; i < sclk_table->count; i++)
5030                         size += sprintf(buf + size, "%d: %uMhz %s\n",
5031                                         i, sclk_table->dpm_levels[i].value / 100,
5032                                         (i == now) ? "*" : "");
5033                 break;
5034         case PP_MCLK:
5035                 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency);
5036                 clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
5037
5038                 for (i = 0; i < mclk_table->count; i++) {
5039                         if (clock > mclk_table->dpm_levels[i].value)
5040                                 continue;
5041                         break;
5042                 }
5043                 now = i;
5044
5045                 for (i = 0; i < mclk_table->count; i++)
5046                         size += sprintf(buf + size, "%d: %uMhz %s\n",
5047                                         i, mclk_table->dpm_levels[i].value / 100,
5048                                         (i == now) ? "*" : "");
5049                 break;
5050         case PP_PCIE:
5051                 pcie_speed = polaris10_get_current_pcie_speed(hwmgr);
5052                 for (i = 0; i < pcie_table->count; i++) {
5053                         if (pcie_speed != pcie_table->dpm_levels[i].value)
5054                                 continue;
5055                         break;
5056                 }
5057                 now = i;
5058
5059                 for (i = 0; i < pcie_table->count; i++)
5060                         size += sprintf(buf + size, "%d: %s %s\n", i,
5061                                         (pcie_table->dpm_levels[i].value == 0) ? "2.5GB, x8" :
5062                                         (pcie_table->dpm_levels[i].value == 1) ? "5.0GB, x16" :
5063                                         (pcie_table->dpm_levels[i].value == 2) ? "8.0GB, x16" : "",
5064                                         (i == now) ? "*" : "");
5065                 break;
5066         default:
5067                 break;
5068         }
5069         return size;
5070 }
5071
5072 static int polaris10_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
5073 {
5074         if (mode) {
5075                 /* stop auto-manage */
5076                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
5077                                 PHM_PlatformCaps_MicrocodeFanControl))
5078                         polaris10_fan_ctrl_stop_smc_fan_control(hwmgr);
5079                 polaris10_fan_ctrl_set_static_mode(hwmgr, mode);
5080         } else
5081                 /* restart auto-manage */
5082                 polaris10_fan_ctrl_reset_fan_speed_to_default(hwmgr);
5083
5084         return 0;
5085 }
5086
5087 static int polaris10_get_fan_control_mode(struct pp_hwmgr *hwmgr)
5088 {
5089         if (hwmgr->fan_ctrl_is_in_default_mode)
5090                 return hwmgr->fan_ctrl_default_mode;
5091         else
5092                 return PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
5093                                 CG_FDO_CTRL2, FDO_PWM_MODE);
5094 }
5095
5096 static int polaris10_get_sclk_od(struct pp_hwmgr *hwmgr)
5097 {
5098         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
5099         struct polaris10_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
5100         struct polaris10_single_dpm_table *golden_sclk_table =
5101                         &(data->golden_dpm_table.sclk_table);
5102         int value;
5103
5104         value = (sclk_table->dpm_levels[sclk_table->count - 1].value -
5105                         golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value) *
5106                         100 /
5107                         golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value;
5108
5109         return value;
5110 }
5111
5112 static int polaris10_set_sclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
5113 {
5114         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
5115         struct polaris10_single_dpm_table *golden_sclk_table =
5116                         &(data->golden_dpm_table.sclk_table);
5117         struct pp_power_state  *ps;
5118         struct polaris10_power_state  *polaris10_ps;
5119
5120         if (value > 20)
5121                 value = 20;
5122
5123         ps = hwmgr->request_ps;
5124
5125         if (ps == NULL)
5126                 return -EINVAL;
5127
5128         polaris10_ps = cast_phw_polaris10_power_state(&ps->hardware);
5129
5130         polaris10_ps->performance_levels[polaris10_ps->performance_level_count - 1].engine_clock =
5131                         golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value *
5132                         value / 100 +
5133                         golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value;
5134
5135         return 0;
5136 }
5137
5138 static int polaris10_get_mclk_od(struct pp_hwmgr *hwmgr)
5139 {
5140         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
5141         struct polaris10_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
5142         struct polaris10_single_dpm_table *golden_mclk_table =
5143                         &(data->golden_dpm_table.mclk_table);
5144         int value;
5145
5146         value = (mclk_table->dpm_levels[mclk_table->count - 1].value -
5147                         golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value) *
5148                         100 /
5149                         golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value;
5150
5151         return value;
5152 }
5153
5154 static int polaris10_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
5155 {
5156         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
5157         struct polaris10_single_dpm_table *golden_mclk_table =
5158                         &(data->golden_dpm_table.mclk_table);
5159         struct pp_power_state  *ps;
5160         struct polaris10_power_state  *polaris10_ps;
5161
5162         if (value > 20)
5163                 value = 20;
5164
5165         ps = hwmgr->request_ps;
5166
5167         if (ps == NULL)
5168                 return -EINVAL;
5169
5170         polaris10_ps = cast_phw_polaris10_power_state(&ps->hardware);
5171
5172         polaris10_ps->performance_levels[polaris10_ps->performance_level_count - 1].memory_clock =
5173                         golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value *
5174                         value / 100 +
5175                         golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value;
5176
5177         return 0;
5178 }
5179 static const struct pp_hwmgr_func polaris10_hwmgr_funcs = {
5180         .backend_init = &polaris10_hwmgr_backend_init,
5181         .backend_fini = &polaris10_hwmgr_backend_fini,
5182         .asic_setup = &polaris10_setup_asic_task,
5183         .dynamic_state_management_enable = &polaris10_enable_dpm_tasks,
5184         .apply_state_adjust_rules = polaris10_apply_state_adjust_rules,
5185         .force_dpm_level = &polaris10_force_dpm_level,
5186         .power_state_set = polaris10_set_power_state_tasks,
5187         .get_power_state_size = polaris10_get_power_state_size,
5188         .get_mclk = polaris10_dpm_get_mclk,
5189         .get_sclk = polaris10_dpm_get_sclk,
5190         .patch_boot_state = polaris10_dpm_patch_boot_state,
5191         .get_pp_table_entry = polaris10_get_pp_table_entry,
5192         .get_num_of_pp_table_entries = tonga_get_number_of_powerplay_table_entries,
5193         .print_current_perforce_level = polaris10_print_current_perforce_level,
5194         .powerdown_uvd = polaris10_phm_powerdown_uvd,
5195         .powergate_uvd = polaris10_phm_powergate_uvd,
5196         .powergate_vce = polaris10_phm_powergate_vce,
5197         .disable_clock_power_gating = polaris10_phm_disable_clock_power_gating,
5198         .update_clock_gatings = polaris10_phm_update_clock_gatings,
5199         .notify_smc_display_config_after_ps_adjustment = polaris10_notify_smc_display_config_after_ps_adjustment,
5200         .display_config_changed = polaris10_display_configuration_changed_task,
5201         .set_max_fan_pwm_output = polaris10_set_max_fan_pwm_output,
5202         .set_max_fan_rpm_output = polaris10_set_max_fan_rpm_output,
5203         .get_temperature = polaris10_thermal_get_temperature,
5204         .stop_thermal_controller = polaris10_thermal_stop_thermal_controller,
5205         .get_fan_speed_info = polaris10_fan_ctrl_get_fan_speed_info,
5206         .get_fan_speed_percent = polaris10_fan_ctrl_get_fan_speed_percent,
5207         .set_fan_speed_percent = polaris10_fan_ctrl_set_fan_speed_percent,
5208         .reset_fan_speed_to_default = polaris10_fan_ctrl_reset_fan_speed_to_default,
5209         .get_fan_speed_rpm = polaris10_fan_ctrl_get_fan_speed_rpm,
5210         .set_fan_speed_rpm = polaris10_fan_ctrl_set_fan_speed_rpm,
5211         .uninitialize_thermal_controller = polaris10_thermal_ctrl_uninitialize_thermal_controller,
5212         .register_internal_thermal_interrupt = polaris10_register_internal_thermal_interrupt,
5213         .check_smc_update_required_for_display_configuration = polaris10_check_smc_update_required_for_display_configuration,
5214         .check_states_equal = polaris10_check_states_equal,
5215         .set_fan_control_mode = polaris10_set_fan_control_mode,
5216         .get_fan_control_mode = polaris10_get_fan_control_mode,
5217         .force_clock_level = polaris10_force_clock_level,
5218         .print_clock_levels = polaris10_print_clock_levels,
5219         .enable_per_cu_power_gating = polaris10_phm_enable_per_cu_power_gating,
5220         .get_sclk_od = polaris10_get_sclk_od,
5221         .set_sclk_od = polaris10_set_sclk_od,
5222         .get_mclk_od = polaris10_get_mclk_od,
5223         .set_mclk_od = polaris10_set_mclk_od,
5224 };
5225
5226 int polaris10_hwmgr_init(struct pp_hwmgr *hwmgr)
5227 {
5228         hwmgr->hwmgr_func = &polaris10_hwmgr_funcs;
5229         hwmgr->pptable_func = &tonga_pptable_funcs;
5230         pp_polaris10_thermal_initialize(hwmgr);
5231
5232         return 0;
5233 }