2 * Copyright 2018 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <linux/delay.h>
26 #include <linux/module.h>
27 #include <linux/slab.h>
30 #include "amd_powerplay.h"
31 #include "vega20_smumgr.h"
32 #include "hardwaremanager.h"
33 #include "ppatomfwctrl.h"
34 #include "atomfirmware.h"
35 #include "cgs_common.h"
36 #include "vega20_powertune.h"
37 #include "vega20_inc.h"
38 #include "pppcielanes.h"
39 #include "vega20_hwmgr.h"
40 #include "vega20_processpptables.h"
41 #include "vega20_pptable.h"
42 #include "vega20_thermal.h"
43 #include "vega20_ppsmc.h"
45 #include "amd_pcie_helpers.h"
46 #include "ppinterrupt.h"
47 #include "pp_overdriver.h"
48 #include "pp_thermal.h"
49 #include "soc15_common.h"
50 #include "smuio/smuio_9_0_offset.h"
51 #include "smuio/smuio_9_0_sh_mask.h"
53 static void vega20_set_default_registry_data(struct pp_hwmgr *hwmgr)
55 struct vega20_hwmgr *data =
56 (struct vega20_hwmgr *)(hwmgr->backend);
58 data->gfxclk_average_alpha = PPVEGA20_VEGA20GFXCLKAVERAGEALPHA_DFLT;
59 data->socclk_average_alpha = PPVEGA20_VEGA20SOCCLKAVERAGEALPHA_DFLT;
60 data->uclk_average_alpha = PPVEGA20_VEGA20UCLKCLKAVERAGEALPHA_DFLT;
61 data->gfx_activity_average_alpha = PPVEGA20_VEGA20GFXACTIVITYAVERAGEALPHA_DFLT;
62 data->lowest_uclk_reserved_for_ulv = PPVEGA20_VEGA20LOWESTUCLKRESERVEDFORULV_DFLT;
64 data->display_voltage_mode = PPVEGA20_VEGA20DISPLAYVOLTAGEMODE_DFLT;
65 data->dcef_clk_quad_eqn_a = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
66 data->dcef_clk_quad_eqn_b = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
67 data->dcef_clk_quad_eqn_c = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
68 data->disp_clk_quad_eqn_a = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
69 data->disp_clk_quad_eqn_b = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
70 data->disp_clk_quad_eqn_c = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
71 data->pixel_clk_quad_eqn_a = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
72 data->pixel_clk_quad_eqn_b = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
73 data->pixel_clk_quad_eqn_c = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
74 data->phy_clk_quad_eqn_a = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
75 data->phy_clk_quad_eqn_b = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
76 data->phy_clk_quad_eqn_c = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
79 * Disable the following features for now:
88 data->registry_data.disallowed_features = 0xE0041C00;
89 data->registry_data.od_state_in_dc_support = 0;
90 data->registry_data.thermal_support = 1;
91 data->registry_data.skip_baco_hardware = 0;
93 data->registry_data.log_avfs_param = 0;
94 data->registry_data.sclk_throttle_low_notification = 1;
95 data->registry_data.force_dpm_high = 0;
96 data->registry_data.stable_pstate_sclk_dpm_percentage = 75;
98 data->registry_data.didt_support = 0;
99 if (data->registry_data.didt_support) {
100 data->registry_data.didt_mode = 6;
101 data->registry_data.sq_ramping_support = 1;
102 data->registry_data.db_ramping_support = 0;
103 data->registry_data.td_ramping_support = 0;
104 data->registry_data.tcp_ramping_support = 0;
105 data->registry_data.dbr_ramping_support = 0;
106 data->registry_data.edc_didt_support = 1;
107 data->registry_data.gc_didt_support = 0;
108 data->registry_data.psm_didt_support = 0;
111 data->registry_data.pcie_lane_override = 0xff;
112 data->registry_data.pcie_speed_override = 0xff;
113 data->registry_data.pcie_clock_override = 0xffffffff;
114 data->registry_data.regulator_hot_gpio_support = 1;
115 data->registry_data.ac_dc_switch_gpio_support = 0;
116 data->registry_data.quick_transition_support = 0;
117 data->registry_data.zrpm_start_temp = 0xffff;
118 data->registry_data.zrpm_stop_temp = 0xffff;
119 data->registry_data.od8_feature_enable = 1;
120 data->registry_data.disable_water_mark = 0;
121 data->registry_data.disable_pp_tuning = 0;
122 data->registry_data.disable_xlpp_tuning = 0;
123 data->registry_data.disable_workload_policy = 0;
124 data->registry_data.perf_ui_tuning_profile_turbo = 0x19190F0F;
125 data->registry_data.perf_ui_tuning_profile_powerSave = 0x19191919;
126 data->registry_data.perf_ui_tuning_profile_xl = 0x00000F0A;
127 data->registry_data.force_workload_policy_mask = 0;
128 data->registry_data.disable_3d_fs_detection = 0;
129 data->registry_data.fps_support = 1;
130 data->registry_data.disable_auto_wattman = 1;
131 data->registry_data.auto_wattman_debug = 0;
132 data->registry_data.auto_wattman_sample_period = 100;
133 data->registry_data.fclk_gfxclk_ratio = 0x3F6CCCCD;
134 data->registry_data.auto_wattman_threshold = 50;
135 data->registry_data.gfxoff_controlled_by_driver = 1;
136 data->gfxoff_allowed = false;
137 data->counter_gfxoff = 0;
140 static int vega20_set_features_platform_caps(struct pp_hwmgr *hwmgr)
142 struct vega20_hwmgr *data =
143 (struct vega20_hwmgr *)(hwmgr->backend);
144 struct amdgpu_device *adev = hwmgr->adev;
146 if (data->vddci_control == VEGA20_VOLTAGE_CONTROL_NONE)
147 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
148 PHM_PlatformCaps_ControlVDDCI);
150 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
151 PHM_PlatformCaps_TablelessHardwareInterface);
153 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
154 PHM_PlatformCaps_EnableSMU7ThermalManagement);
156 if (adev->pg_flags & AMD_PG_SUPPORT_UVD)
157 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
158 PHM_PlatformCaps_UVDPowerGating);
160 if (adev->pg_flags & AMD_PG_SUPPORT_VCE)
161 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
162 PHM_PlatformCaps_VCEPowerGating);
164 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
165 PHM_PlatformCaps_UnTabledHardwareInterface);
167 if (data->registry_data.od8_feature_enable)
168 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
169 PHM_PlatformCaps_OD8inACSupport);
171 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
172 PHM_PlatformCaps_ActivityReporting);
173 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
174 PHM_PlatformCaps_FanSpeedInTableIsRPM);
176 if (data->registry_data.od_state_in_dc_support) {
177 if (data->registry_data.od8_feature_enable)
178 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
179 PHM_PlatformCaps_OD8inDCSupport);
182 if (data->registry_data.thermal_support &&
183 data->registry_data.fuzzy_fan_control_support &&
184 hwmgr->thermal_controller.advanceFanControlParameters.usTMax)
185 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
186 PHM_PlatformCaps_ODFuzzyFanControlSupport);
188 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
189 PHM_PlatformCaps_DynamicPowerManagement);
190 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
191 PHM_PlatformCaps_SMC);
192 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
193 PHM_PlatformCaps_ThermalPolicyDelay);
195 if (data->registry_data.force_dpm_high)
196 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
197 PHM_PlatformCaps_ExclusiveModeAlwaysHigh);
199 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
200 PHM_PlatformCaps_DynamicUVDState);
202 if (data->registry_data.sclk_throttle_low_notification)
203 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
204 PHM_PlatformCaps_SclkThrottleLowNotification);
206 /* power tune caps */
207 /* assume disabled */
208 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
209 PHM_PlatformCaps_PowerContainment);
210 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
211 PHM_PlatformCaps_DiDtSupport);
212 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
213 PHM_PlatformCaps_SQRamping);
214 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
215 PHM_PlatformCaps_DBRamping);
216 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
217 PHM_PlatformCaps_TDRamping);
218 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
219 PHM_PlatformCaps_TCPRamping);
220 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
221 PHM_PlatformCaps_DBRRamping);
222 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
223 PHM_PlatformCaps_DiDtEDCEnable);
224 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
225 PHM_PlatformCaps_GCEDC);
226 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
227 PHM_PlatformCaps_PSM);
229 if (data->registry_data.didt_support) {
230 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
231 PHM_PlatformCaps_DiDtSupport);
232 if (data->registry_data.sq_ramping_support)
233 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
234 PHM_PlatformCaps_SQRamping);
235 if (data->registry_data.db_ramping_support)
236 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
237 PHM_PlatformCaps_DBRamping);
238 if (data->registry_data.td_ramping_support)
239 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
240 PHM_PlatformCaps_TDRamping);
241 if (data->registry_data.tcp_ramping_support)
242 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
243 PHM_PlatformCaps_TCPRamping);
244 if (data->registry_data.dbr_ramping_support)
245 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
246 PHM_PlatformCaps_DBRRamping);
247 if (data->registry_data.edc_didt_support)
248 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
249 PHM_PlatformCaps_DiDtEDCEnable);
250 if (data->registry_data.gc_didt_support)
251 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
252 PHM_PlatformCaps_GCEDC);
253 if (data->registry_data.psm_didt_support)
254 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
255 PHM_PlatformCaps_PSM);
258 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
259 PHM_PlatformCaps_RegulatorHot);
261 if (data->registry_data.ac_dc_switch_gpio_support) {
262 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
263 PHM_PlatformCaps_AutomaticDCTransition);
264 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
265 PHM_PlatformCaps_SMCtoPPLIBAcdcGpioScheme);
268 if (data->registry_data.quick_transition_support) {
269 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
270 PHM_PlatformCaps_AutomaticDCTransition);
271 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
272 PHM_PlatformCaps_SMCtoPPLIBAcdcGpioScheme);
273 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
274 PHM_PlatformCaps_Falcon_QuickTransition);
277 if (data->lowest_uclk_reserved_for_ulv != PPVEGA20_VEGA20LOWESTUCLKRESERVEDFORULV_DFLT) {
278 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
279 PHM_PlatformCaps_LowestUclkReservedForUlv);
280 if (data->lowest_uclk_reserved_for_ulv == 1)
281 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
282 PHM_PlatformCaps_LowestUclkReservedForUlv);
285 if (data->registry_data.custom_fan_support)
286 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
287 PHM_PlatformCaps_CustomFanControlSupport);
292 static void vega20_init_dpm_defaults(struct pp_hwmgr *hwmgr)
294 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
297 data->smu_features[GNLD_DPM_PREFETCHER].smu_feature_id =
298 FEATURE_DPM_PREFETCHER_BIT;
299 data->smu_features[GNLD_DPM_GFXCLK].smu_feature_id =
300 FEATURE_DPM_GFXCLK_BIT;
301 data->smu_features[GNLD_DPM_UCLK].smu_feature_id =
302 FEATURE_DPM_UCLK_BIT;
303 data->smu_features[GNLD_DPM_SOCCLK].smu_feature_id =
304 FEATURE_DPM_SOCCLK_BIT;
305 data->smu_features[GNLD_DPM_UVD].smu_feature_id =
307 data->smu_features[GNLD_DPM_VCE].smu_feature_id =
309 data->smu_features[GNLD_ULV].smu_feature_id =
311 data->smu_features[GNLD_DPM_MP0CLK].smu_feature_id =
312 FEATURE_DPM_MP0CLK_BIT;
313 data->smu_features[GNLD_DPM_LINK].smu_feature_id =
314 FEATURE_DPM_LINK_BIT;
315 data->smu_features[GNLD_DPM_DCEFCLK].smu_feature_id =
316 FEATURE_DPM_DCEFCLK_BIT;
317 data->smu_features[GNLD_DS_GFXCLK].smu_feature_id =
318 FEATURE_DS_GFXCLK_BIT;
319 data->smu_features[GNLD_DS_SOCCLK].smu_feature_id =
320 FEATURE_DS_SOCCLK_BIT;
321 data->smu_features[GNLD_DS_LCLK].smu_feature_id =
323 data->smu_features[GNLD_PPT].smu_feature_id =
325 data->smu_features[GNLD_TDC].smu_feature_id =
327 data->smu_features[GNLD_THERMAL].smu_feature_id =
329 data->smu_features[GNLD_GFX_PER_CU_CG].smu_feature_id =
330 FEATURE_GFX_PER_CU_CG_BIT;
331 data->smu_features[GNLD_RM].smu_feature_id =
333 data->smu_features[GNLD_DS_DCEFCLK].smu_feature_id =
334 FEATURE_DS_DCEFCLK_BIT;
335 data->smu_features[GNLD_ACDC].smu_feature_id =
337 data->smu_features[GNLD_VR0HOT].smu_feature_id =
339 data->smu_features[GNLD_VR1HOT].smu_feature_id =
341 data->smu_features[GNLD_FW_CTF].smu_feature_id =
343 data->smu_features[GNLD_LED_DISPLAY].smu_feature_id =
344 FEATURE_LED_DISPLAY_BIT;
345 data->smu_features[GNLD_FAN_CONTROL].smu_feature_id =
346 FEATURE_FAN_CONTROL_BIT;
347 data->smu_features[GNLD_DIDT].smu_feature_id = FEATURE_GFX_EDC_BIT;
348 data->smu_features[GNLD_GFXOFF].smu_feature_id = FEATURE_GFXOFF_BIT;
349 data->smu_features[GNLD_CG].smu_feature_id = FEATURE_CG_BIT;
350 data->smu_features[GNLD_DPM_FCLK].smu_feature_id = FEATURE_DPM_FCLK_BIT;
351 data->smu_features[GNLD_DS_FCLK].smu_feature_id = FEATURE_DS_FCLK_BIT;
352 data->smu_features[GNLD_DS_MP1CLK].smu_feature_id = FEATURE_DS_MP1CLK_BIT;
353 data->smu_features[GNLD_DS_MP0CLK].smu_feature_id = FEATURE_DS_MP0CLK_BIT;
354 data->smu_features[GNLD_XGMI].smu_feature_id = FEATURE_XGMI_BIT;
356 for (i = 0; i < GNLD_FEATURES_MAX; i++) {
357 data->smu_features[i].smu_feature_bitmap =
358 (uint64_t)(1ULL << data->smu_features[i].smu_feature_id);
359 data->smu_features[i].allowed =
360 ((data->registry_data.disallowed_features >> i) & 1) ?
365 static int vega20_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr)
370 static int vega20_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
372 kfree(hwmgr->backend);
373 hwmgr->backend = NULL;
378 static int vega20_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
380 struct vega20_hwmgr *data;
381 struct amdgpu_device *adev = hwmgr->adev;
383 data = kzalloc(sizeof(struct vega20_hwmgr), GFP_KERNEL);
387 hwmgr->backend = data;
389 hwmgr->workload_mask = 1 << hwmgr->workload_prority[PP_SMC_POWER_PROFILE_VIDEO];
390 hwmgr->power_profile_mode = PP_SMC_POWER_PROFILE_VIDEO;
391 hwmgr->default_power_profile_mode = PP_SMC_POWER_PROFILE_VIDEO;
393 vega20_set_default_registry_data(hwmgr);
395 data->disable_dpm_mask = 0xff;
397 /* need to set voltage control types before EVV patching */
398 data->vddc_control = VEGA20_VOLTAGE_CONTROL_NONE;
399 data->mvdd_control = VEGA20_VOLTAGE_CONTROL_NONE;
400 data->vddci_control = VEGA20_VOLTAGE_CONTROL_NONE;
402 data->water_marks_bitmap = 0;
403 data->avfs_exist = false;
405 vega20_set_features_platform_caps(hwmgr);
407 vega20_init_dpm_defaults(hwmgr);
409 /* Parse pptable data read from VBIOS */
410 vega20_set_private_data_based_on_pptable(hwmgr);
412 data->is_tlu_enabled = false;
414 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
415 VEGA20_MAX_HARDWARE_POWERLEVELS;
416 hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
417 hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
419 hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */
420 /* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */
421 hwmgr->platform_descriptor.clockStep.engineClock = 500;
422 hwmgr->platform_descriptor.clockStep.memoryClock = 500;
424 data->total_active_cus = adev->gfx.cu_info.number;
429 static int vega20_init_sclk_threshold(struct pp_hwmgr *hwmgr)
431 struct vega20_hwmgr *data =
432 (struct vega20_hwmgr *)(hwmgr->backend);
434 data->low_sclk_interrupt_threshold = 0;
439 static int vega20_setup_asic_task(struct pp_hwmgr *hwmgr)
443 ret = vega20_init_sclk_threshold(hwmgr);
444 PP_ASSERT_WITH_CODE(!ret,
445 "Failed to init sclk threshold!",
452 * @fn vega20_init_dpm_state
453 * @brief Function to initialize all Soft Min/Max and Hard Min/Max to 0xff.
455 * @param dpm_state - the address of the DPM Table to initiailize.
458 static void vega20_init_dpm_state(struct vega20_dpm_state *dpm_state)
460 dpm_state->soft_min_level = 0x0;
461 dpm_state->soft_max_level = 0xffff;
462 dpm_state->hard_min_level = 0x0;
463 dpm_state->hard_max_level = 0xffff;
466 static int vega20_get_number_of_dpm_level(struct pp_hwmgr *hwmgr,
467 PPCLK_e clk_id, uint32_t *num_of_levels)
471 ret = smum_send_msg_to_smc_with_parameter(hwmgr,
472 PPSMC_MSG_GetDpmFreqByIndex,
473 (clk_id << 16 | 0xFF));
474 PP_ASSERT_WITH_CODE(!ret,
475 "[GetNumOfDpmLevel] failed to get dpm levels!",
478 *num_of_levels = smum_get_argument(hwmgr);
479 PP_ASSERT_WITH_CODE(*num_of_levels > 0,
480 "[GetNumOfDpmLevel] number of clk levels is invalid!",
486 static int vega20_get_dpm_frequency_by_index(struct pp_hwmgr *hwmgr,
487 PPCLK_e clk_id, uint32_t index, uint32_t *clk)
491 ret = smum_send_msg_to_smc_with_parameter(hwmgr,
492 PPSMC_MSG_GetDpmFreqByIndex,
493 (clk_id << 16 | index));
494 PP_ASSERT_WITH_CODE(!ret,
495 "[GetDpmFreqByIndex] failed to get dpm freq by index!",
498 *clk = smum_get_argument(hwmgr);
499 PP_ASSERT_WITH_CODE(*clk,
500 "[GetDpmFreqByIndex] clk value is invalid!",
506 static int vega20_setup_single_dpm_table(struct pp_hwmgr *hwmgr,
507 struct vega20_single_dpm_table *dpm_table, PPCLK_e clk_id)
510 uint32_t i, num_of_levels, clk;
512 ret = vega20_get_number_of_dpm_level(hwmgr, clk_id, &num_of_levels);
513 PP_ASSERT_WITH_CODE(!ret,
514 "[SetupSingleDpmTable] failed to get clk levels!",
517 dpm_table->count = num_of_levels;
519 for (i = 0; i < num_of_levels; i++) {
520 ret = vega20_get_dpm_frequency_by_index(hwmgr, clk_id, i, &clk);
521 PP_ASSERT_WITH_CODE(!ret,
522 "[SetupSingleDpmTable] failed to get clk of specific level!",
524 dpm_table->dpm_levels[i].value = clk;
525 dpm_table->dpm_levels[i].enabled = true;
531 static int vega20_setup_gfxclk_dpm_table(struct pp_hwmgr *hwmgr)
533 struct vega20_hwmgr *data =
534 (struct vega20_hwmgr *)(hwmgr->backend);
535 struct vega20_single_dpm_table *dpm_table;
538 dpm_table = &(data->dpm_table.gfx_table);
539 if (data->smu_features[GNLD_DPM_GFXCLK].enabled) {
540 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_GFXCLK);
541 PP_ASSERT_WITH_CODE(!ret,
542 "[SetupDefaultDpmTable] failed to get gfxclk dpm levels!",
545 dpm_table->count = 1;
546 dpm_table->dpm_levels[0].value = data->vbios_boot_state.gfx_clock / 100;
552 static int vega20_setup_memclk_dpm_table(struct pp_hwmgr *hwmgr)
554 struct vega20_hwmgr *data =
555 (struct vega20_hwmgr *)(hwmgr->backend);
556 struct vega20_single_dpm_table *dpm_table;
559 dpm_table = &(data->dpm_table.mem_table);
560 if (data->smu_features[GNLD_DPM_UCLK].enabled) {
561 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_UCLK);
562 PP_ASSERT_WITH_CODE(!ret,
563 "[SetupDefaultDpmTable] failed to get memclk dpm levels!",
566 dpm_table->count = 1;
567 dpm_table->dpm_levels[0].value = data->vbios_boot_state.mem_clock / 100;
574 * This function is to initialize all DPM state tables
575 * for SMU based on the dependency table.
576 * Dynamic state patching function will then trim these
577 * state tables to the allowed range based
578 * on the power policy or external client requests,
579 * such as UVD request, etc.
581 static int vega20_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
583 struct vega20_hwmgr *data =
584 (struct vega20_hwmgr *)(hwmgr->backend);
585 struct vega20_single_dpm_table *dpm_table;
588 memset(&data->dpm_table, 0, sizeof(data->dpm_table));
591 dpm_table = &(data->dpm_table.soc_table);
592 if (data->smu_features[GNLD_DPM_SOCCLK].enabled) {
593 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_SOCCLK);
594 PP_ASSERT_WITH_CODE(!ret,
595 "[SetupDefaultDpmTable] failed to get socclk dpm levels!",
598 dpm_table->count = 1;
599 dpm_table->dpm_levels[0].value = data->vbios_boot_state.soc_clock / 100;
601 vega20_init_dpm_state(&(dpm_table->dpm_state));
604 dpm_table = &(data->dpm_table.gfx_table);
605 ret = vega20_setup_gfxclk_dpm_table(hwmgr);
608 vega20_init_dpm_state(&(dpm_table->dpm_state));
611 dpm_table = &(data->dpm_table.mem_table);
612 ret = vega20_setup_memclk_dpm_table(hwmgr);
615 vega20_init_dpm_state(&(dpm_table->dpm_state));
618 dpm_table = &(data->dpm_table.eclk_table);
619 if (data->smu_features[GNLD_DPM_VCE].enabled) {
620 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_ECLK);
621 PP_ASSERT_WITH_CODE(!ret,
622 "[SetupDefaultDpmTable] failed to get eclk dpm levels!",
625 dpm_table->count = 1;
626 dpm_table->dpm_levels[0].value = data->vbios_boot_state.eclock / 100;
628 vega20_init_dpm_state(&(dpm_table->dpm_state));
631 dpm_table = &(data->dpm_table.vclk_table);
632 if (data->smu_features[GNLD_DPM_UVD].enabled) {
633 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_VCLK);
634 PP_ASSERT_WITH_CODE(!ret,
635 "[SetupDefaultDpmTable] failed to get vclk dpm levels!",
638 dpm_table->count = 1;
639 dpm_table->dpm_levels[0].value = data->vbios_boot_state.vclock / 100;
641 vega20_init_dpm_state(&(dpm_table->dpm_state));
644 dpm_table = &(data->dpm_table.dclk_table);
645 if (data->smu_features[GNLD_DPM_UVD].enabled) {
646 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DCLK);
647 PP_ASSERT_WITH_CODE(!ret,
648 "[SetupDefaultDpmTable] failed to get dclk dpm levels!",
651 dpm_table->count = 1;
652 dpm_table->dpm_levels[0].value = data->vbios_boot_state.dclock / 100;
654 vega20_init_dpm_state(&(dpm_table->dpm_state));
657 dpm_table = &(data->dpm_table.dcef_table);
658 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
659 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DCEFCLK);
660 PP_ASSERT_WITH_CODE(!ret,
661 "[SetupDefaultDpmTable] failed to get dcefclk dpm levels!",
664 dpm_table->count = 1;
665 dpm_table->dpm_levels[0].value = data->vbios_boot_state.dcef_clock / 100;
667 vega20_init_dpm_state(&(dpm_table->dpm_state));
670 dpm_table = &(data->dpm_table.pixel_table);
671 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
672 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_PIXCLK);
673 PP_ASSERT_WITH_CODE(!ret,
674 "[SetupDefaultDpmTable] failed to get pixclk dpm levels!",
677 dpm_table->count = 0;
678 vega20_init_dpm_state(&(dpm_table->dpm_state));
681 dpm_table = &(data->dpm_table.display_table);
682 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
683 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DISPCLK);
684 PP_ASSERT_WITH_CODE(!ret,
685 "[SetupDefaultDpmTable] failed to get dispclk dpm levels!",
688 dpm_table->count = 0;
689 vega20_init_dpm_state(&(dpm_table->dpm_state));
692 dpm_table = &(data->dpm_table.phy_table);
693 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
694 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_PHYCLK);
695 PP_ASSERT_WITH_CODE(!ret,
696 "[SetupDefaultDpmTable] failed to get phyclk dpm levels!",
699 dpm_table->count = 0;
700 vega20_init_dpm_state(&(dpm_table->dpm_state));
703 dpm_table = &(data->dpm_table.fclk_table);
704 if (data->smu_features[GNLD_DPM_FCLK].enabled) {
705 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_FCLK);
706 PP_ASSERT_WITH_CODE(!ret,
707 "[SetupDefaultDpmTable] failed to get fclk dpm levels!",
710 dpm_table->count = 0;
711 vega20_init_dpm_state(&(dpm_table->dpm_state));
713 /* save a copy of the default DPM table */
714 memcpy(&(data->golden_dpm_table), &(data->dpm_table),
715 sizeof(struct vega20_dpm_table));
721 * Initializes the SMC table and uploads it
723 * @param hwmgr the address of the powerplay hardware manager.
724 * @param pInput the pointer to input data (PowerState)
727 static int vega20_init_smc_table(struct pp_hwmgr *hwmgr)
730 struct vega20_hwmgr *data =
731 (struct vega20_hwmgr *)(hwmgr->backend);
732 PPTable_t *pp_table = &(data->smc_state_table.pp_table);
733 struct pp_atomfwctrl_bios_boot_up_values boot_up_values;
734 struct phm_ppt_v3_information *pptable_information =
735 (struct phm_ppt_v3_information *)hwmgr->pptable;
737 result = pp_atomfwctrl_get_vbios_bootup_values(hwmgr, &boot_up_values);
738 PP_ASSERT_WITH_CODE(!result,
739 "[InitSMCTable] Failed to get vbios bootup values!",
742 data->vbios_boot_state.vddc = boot_up_values.usVddc;
743 data->vbios_boot_state.vddci = boot_up_values.usVddci;
744 data->vbios_boot_state.mvddc = boot_up_values.usMvddc;
745 data->vbios_boot_state.gfx_clock = boot_up_values.ulGfxClk;
746 data->vbios_boot_state.mem_clock = boot_up_values.ulUClk;
747 data->vbios_boot_state.soc_clock = boot_up_values.ulSocClk;
748 data->vbios_boot_state.dcef_clock = boot_up_values.ulDCEFClk;
749 data->vbios_boot_state.eclock = boot_up_values.ulEClk;
750 data->vbios_boot_state.vclock = boot_up_values.ulVClk;
751 data->vbios_boot_state.dclock = boot_up_values.ulDClk;
752 data->vbios_boot_state.uc_cooling_id = boot_up_values.ucCoolingID;
754 smum_send_msg_to_smc_with_parameter(hwmgr,
755 PPSMC_MSG_SetMinDeepSleepDcefclk,
756 (uint32_t)(data->vbios_boot_state.dcef_clock / 100));
758 memcpy(pp_table, pptable_information->smc_pptable, sizeof(PPTable_t));
760 result = smum_smc_table_manager(hwmgr,
761 (uint8_t *)pp_table, TABLE_PPTABLE, false);
762 PP_ASSERT_WITH_CODE(!result,
763 "[InitSMCTable] Failed to upload PPtable!",
769 static int vega20_set_allowed_featuresmask(struct pp_hwmgr *hwmgr)
771 struct vega20_hwmgr *data =
772 (struct vega20_hwmgr *)(hwmgr->backend);
773 uint32_t allowed_features_low = 0, allowed_features_high = 0;
777 for (i = 0; i < GNLD_FEATURES_MAX; i++)
778 if (data->smu_features[i].allowed)
779 data->smu_features[i].smu_feature_id > 31 ?
780 (allowed_features_high |=
781 ((data->smu_features[i].smu_feature_bitmap >> SMU_FEATURES_HIGH_SHIFT)
783 (allowed_features_low |=
784 ((data->smu_features[i].smu_feature_bitmap >> SMU_FEATURES_LOW_SHIFT)
787 ret = smum_send_msg_to_smc_with_parameter(hwmgr,
788 PPSMC_MSG_SetAllowedFeaturesMaskHigh, allowed_features_high);
789 PP_ASSERT_WITH_CODE(!ret,
790 "[SetAllowedFeaturesMask] Attempt to set allowed features mask(high) failed!",
793 ret = smum_send_msg_to_smc_with_parameter(hwmgr,
794 PPSMC_MSG_SetAllowedFeaturesMaskLow, allowed_features_low);
795 PP_ASSERT_WITH_CODE(!ret,
796 "[SetAllowedFeaturesMask] Attempt to set allowed features mask (low) failed!",
802 static int vega20_run_btc_afll(struct pp_hwmgr *hwmgr)
804 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAfllBtc);
807 static int vega20_enable_all_smu_features(struct pp_hwmgr *hwmgr)
809 struct vega20_hwmgr *data =
810 (struct vega20_hwmgr *)(hwmgr->backend);
811 uint64_t features_enabled;
816 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr,
817 PPSMC_MSG_EnableAllSmuFeatures)) == 0,
818 "[EnableAllSMUFeatures] Failed to enable all smu features!",
821 ret = vega20_get_enabled_smc_features(hwmgr, &features_enabled);
822 PP_ASSERT_WITH_CODE(!ret,
823 "[EnableAllSmuFeatures] Failed to get enabled smc features!",
826 for (i = 0; i < GNLD_FEATURES_MAX; i++) {
827 enabled = (features_enabled & data->smu_features[i].smu_feature_bitmap) ?
829 data->smu_features[i].enabled = enabled;
830 data->smu_features[i].supported = enabled;
833 if (data->smu_features[i].allowed && !enabled)
834 pr_info("[EnableAllSMUFeatures] feature %d is expected enabled!", i);
835 else if (!data->smu_features[i].allowed && enabled)
836 pr_info("[EnableAllSMUFeatures] feature %d is expected disabled!", i);
843 static int vega20_notify_smc_display_change(struct pp_hwmgr *hwmgr)
845 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
847 if (data->smu_features[GNLD_DPM_UCLK].enabled)
848 return smum_send_msg_to_smc_with_parameter(hwmgr,
849 PPSMC_MSG_SetUclkFastSwitch,
855 static int vega20_send_clock_ratio(struct pp_hwmgr *hwmgr)
857 struct vega20_hwmgr *data =
858 (struct vega20_hwmgr *)(hwmgr->backend);
860 return smum_send_msg_to_smc_with_parameter(hwmgr,
861 PPSMC_MSG_SetFclkGfxClkRatio,
862 data->registry_data.fclk_gfxclk_ratio);
865 static int vega20_disable_all_smu_features(struct pp_hwmgr *hwmgr)
867 struct vega20_hwmgr *data =
868 (struct vega20_hwmgr *)(hwmgr->backend);
869 uint64_t features_enabled;
874 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr,
875 PPSMC_MSG_DisableAllSmuFeatures)) == 0,
876 "[DisableAllSMUFeatures] Failed to disable all smu features!",
879 ret = vega20_get_enabled_smc_features(hwmgr, &features_enabled);
880 PP_ASSERT_WITH_CODE(!ret,
881 "[DisableAllSMUFeatures] Failed to get enabled smc features!",
884 for (i = 0; i < GNLD_FEATURES_MAX; i++) {
885 enabled = (features_enabled & data->smu_features[i].smu_feature_bitmap) ?
887 data->smu_features[i].enabled = enabled;
888 data->smu_features[i].supported = enabled;
894 static int vega20_od8_set_feature_capabilities(
895 struct pp_hwmgr *hwmgr)
897 struct phm_ppt_v3_information *pptable_information =
898 (struct phm_ppt_v3_information *)hwmgr->pptable;
899 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
900 PPTable_t *pp_table = &(data->smc_state_table.pp_table);
901 struct vega20_od8_settings *od_settings = &(data->od8_settings);
903 od_settings->overdrive8_capabilities = 0;
905 if (data->smu_features[GNLD_DPM_GFXCLK].enabled) {
906 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_GFXCLK_LIMITS] &&
907 pptable_information->od_settings_max[OD8_SETTING_GFXCLK_FMAX] > 0 &&
908 pptable_information->od_settings_min[OD8_SETTING_GFXCLK_FMIN] > 0 &&
909 (pptable_information->od_settings_max[OD8_SETTING_GFXCLK_FMAX] >=
910 pptable_information->od_settings_min[OD8_SETTING_GFXCLK_FMIN]))
911 od_settings->overdrive8_capabilities |= OD8_GFXCLK_LIMITS;
913 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_GFXCLK_CURVE] &&
914 (pptable_information->od_settings_min[OD8_SETTING_GFXCLK_VOLTAGE1] >=
915 pp_table->MinVoltageGfx / VOLTAGE_SCALE) &&
916 (pptable_information->od_settings_max[OD8_SETTING_GFXCLK_VOLTAGE3] <=
917 pp_table->MaxVoltageGfx / VOLTAGE_SCALE) &&
918 (pptable_information->od_settings_max[OD8_SETTING_GFXCLK_VOLTAGE3] >=
919 pptable_information->od_settings_min[OD8_SETTING_GFXCLK_VOLTAGE1]))
920 od_settings->overdrive8_capabilities |= OD8_GFXCLK_CURVE;
923 if (data->smu_features[GNLD_DPM_UCLK].enabled) {
924 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_UCLK_MAX] &&
925 pptable_information->od_settings_min[OD8_SETTING_UCLK_FMAX] > 0 &&
926 pptable_information->od_settings_max[OD8_SETTING_UCLK_FMAX] > 0 &&
927 (pptable_information->od_settings_max[OD8_SETTING_UCLK_FMAX] >=
928 pptable_information->od_settings_min[OD8_SETTING_UCLK_FMAX]))
929 od_settings->overdrive8_capabilities |= OD8_UCLK_MAX;
932 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_POWER_LIMIT] &&
933 pptable_information->od_settings_max[OD8_SETTING_POWER_PERCENTAGE] > 0 &&
934 pptable_information->od_settings_max[OD8_SETTING_POWER_PERCENTAGE] <= 100 &&
935 pptable_information->od_settings_min[OD8_SETTING_POWER_PERCENTAGE] > 0 &&
936 pptable_information->od_settings_min[OD8_SETTING_POWER_PERCENTAGE] <= 100)
937 od_settings->overdrive8_capabilities |= OD8_POWER_LIMIT;
939 if (data->smu_features[GNLD_FAN_CONTROL].enabled) {
940 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_FAN_ACOUSTIC_LIMIT] &&
941 pptable_information->od_settings_min[OD8_SETTING_FAN_ACOUSTIC_LIMIT] > 0 &&
942 pptable_information->od_settings_max[OD8_SETTING_FAN_ACOUSTIC_LIMIT] > 0 &&
943 (pptable_information->od_settings_max[OD8_SETTING_FAN_ACOUSTIC_LIMIT] >=
944 pptable_information->od_settings_min[OD8_SETTING_FAN_ACOUSTIC_LIMIT]))
945 od_settings->overdrive8_capabilities |= OD8_ACOUSTIC_LIMIT_SCLK;
947 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_FAN_SPEED_MIN] &&
948 (pptable_information->od_settings_min[OD8_SETTING_FAN_MIN_SPEED] >=
949 (pp_table->FanPwmMin * pp_table->FanMaximumRpm / 100)) &&
950 pptable_information->od_settings_max[OD8_SETTING_FAN_MIN_SPEED] > 0 &&
951 (pptable_information->od_settings_max[OD8_SETTING_FAN_MIN_SPEED] >=
952 pptable_information->od_settings_min[OD8_SETTING_FAN_MIN_SPEED]))
953 od_settings->overdrive8_capabilities |= OD8_FAN_SPEED_MIN;
956 if (data->smu_features[GNLD_THERMAL].enabled) {
957 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_TEMPERATURE_FAN] &&
958 pptable_information->od_settings_max[OD8_SETTING_FAN_TARGET_TEMP] > 0 &&
959 pptable_information->od_settings_min[OD8_SETTING_FAN_TARGET_TEMP] > 0 &&
960 (pptable_information->od_settings_max[OD8_SETTING_FAN_TARGET_TEMP] >=
961 pptable_information->od_settings_min[OD8_SETTING_FAN_TARGET_TEMP]))
962 od_settings->overdrive8_capabilities |= OD8_TEMPERATURE_FAN;
964 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_TEMPERATURE_SYSTEM] &&
965 pptable_information->od_settings_max[OD8_SETTING_OPERATING_TEMP_MAX] > 0 &&
966 pptable_information->od_settings_min[OD8_SETTING_OPERATING_TEMP_MAX] > 0 &&
967 (pptable_information->od_settings_max[OD8_SETTING_OPERATING_TEMP_MAX] >=
968 pptable_information->od_settings_min[OD8_SETTING_OPERATING_TEMP_MAX]))
969 od_settings->overdrive8_capabilities |= OD8_TEMPERATURE_SYSTEM;
972 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_MEMORY_TIMING_TUNE])
973 od_settings->overdrive8_capabilities |= OD8_MEMORY_TIMING_TUNE;
975 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_FAN_ZERO_RPM_CONTROL] &&
976 pp_table->FanZeroRpmEnable)
977 od_settings->overdrive8_capabilities |= OD8_FAN_ZERO_RPM_CONTROL;
982 static int vega20_od8_set_feature_id(
983 struct pp_hwmgr *hwmgr)
985 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
986 struct vega20_od8_settings *od_settings = &(data->od8_settings);
988 if (od_settings->overdrive8_capabilities & OD8_GFXCLK_LIMITS) {
989 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].feature_id =
991 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].feature_id =
994 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].feature_id =
996 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].feature_id =
1000 if (od_settings->overdrive8_capabilities & OD8_GFXCLK_CURVE) {
1001 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].feature_id =
1003 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id =
1005 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].feature_id =
1007 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id =
1009 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].feature_id =
1011 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id =
1014 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].feature_id =
1016 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id =
1018 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].feature_id =
1020 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id =
1022 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].feature_id =
1024 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id =
1028 if (od_settings->overdrive8_capabilities & OD8_UCLK_MAX)
1029 od_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].feature_id = OD8_UCLK_MAX;
1031 od_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].feature_id = 0;
1033 if (od_settings->overdrive8_capabilities & OD8_POWER_LIMIT)
1034 od_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].feature_id = OD8_POWER_LIMIT;
1036 od_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].feature_id = 0;
1038 if (od_settings->overdrive8_capabilities & OD8_ACOUSTIC_LIMIT_SCLK)
1039 od_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].feature_id =
1040 OD8_ACOUSTIC_LIMIT_SCLK;
1042 od_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].feature_id =
1045 if (od_settings->overdrive8_capabilities & OD8_FAN_SPEED_MIN)
1046 od_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].feature_id =
1049 od_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].feature_id =
1052 if (od_settings->overdrive8_capabilities & OD8_TEMPERATURE_FAN)
1053 od_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].feature_id =
1054 OD8_TEMPERATURE_FAN;
1056 od_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].feature_id =
1059 if (od_settings->overdrive8_capabilities & OD8_TEMPERATURE_SYSTEM)
1060 od_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].feature_id =
1061 OD8_TEMPERATURE_SYSTEM;
1063 od_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].feature_id =
1069 static int vega20_od8_get_gfx_clock_base_voltage(
1070 struct pp_hwmgr *hwmgr,
1076 ret = smum_send_msg_to_smc_with_parameter(hwmgr,
1077 PPSMC_MSG_GetAVFSVoltageByDpm,
1078 ((AVFS_CURVE << 24) | (OD8_HOTCURVE_TEMPERATURE << 16) | freq));
1079 PP_ASSERT_WITH_CODE(!ret,
1080 "[GetBaseVoltage] failed to get GFXCLK AVFS voltage from SMU!",
1083 *voltage = smum_get_argument(hwmgr);
1084 *voltage = *voltage / VOLTAGE_SCALE;
1089 static int vega20_od8_initialize_default_settings(
1090 struct pp_hwmgr *hwmgr)
1092 struct phm_ppt_v3_information *pptable_information =
1093 (struct phm_ppt_v3_information *)hwmgr->pptable;
1094 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
1095 struct vega20_od8_settings *od8_settings = &(data->od8_settings);
1096 OverDriveTable_t *od_table = &(data->smc_state_table.overdrive_table);
1099 /* Set Feature Capabilities */
1100 vega20_od8_set_feature_capabilities(hwmgr);
1102 /* Map FeatureID to individual settings */
1103 vega20_od8_set_feature_id(hwmgr);
1105 /* Set default values */
1106 ret = smum_smc_table_manager(hwmgr, (uint8_t *)od_table, TABLE_OVERDRIVE, true);
1107 PP_ASSERT_WITH_CODE(!ret,
1108 "Failed to export over drive table!",
1111 if (od8_settings->overdrive8_capabilities & OD8_GFXCLK_LIMITS) {
1112 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].default_value =
1113 od_table->GfxclkFmin;
1114 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].default_value =
1115 od_table->GfxclkFmax;
1117 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].default_value =
1119 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].default_value =
1123 if (od8_settings->overdrive8_capabilities & OD8_GFXCLK_CURVE) {
1124 od_table->GfxclkFreq1 = od_table->GfxclkFmin;
1125 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].default_value =
1126 od_table->GfxclkFreq1;
1128 od_table->GfxclkFreq3 = od_table->GfxclkFmax;
1129 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].default_value =
1130 od_table->GfxclkFreq3;
1132 od_table->GfxclkFreq2 = (od_table->GfxclkFreq1 + od_table->GfxclkFreq3) / 2;
1133 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].default_value =
1134 od_table->GfxclkFreq2;
1136 PP_ASSERT_WITH_CODE(!vega20_od8_get_gfx_clock_base_voltage(hwmgr,
1137 &(od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value),
1138 od_table->GfxclkFreq1),
1139 "[PhwVega20_OD8_InitializeDefaultSettings] Failed to get Base clock voltage from SMU!",
1140 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value = 0);
1141 od_table->GfxclkVolt1 = od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value
1144 PP_ASSERT_WITH_CODE(!vega20_od8_get_gfx_clock_base_voltage(hwmgr,
1145 &(od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value),
1146 od_table->GfxclkFreq2),
1147 "[PhwVega20_OD8_InitializeDefaultSettings] Failed to get Base clock voltage from SMU!",
1148 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value = 0);
1149 od_table->GfxclkVolt2 = od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value
1152 PP_ASSERT_WITH_CODE(!vega20_od8_get_gfx_clock_base_voltage(hwmgr,
1153 &(od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value),
1154 od_table->GfxclkFreq3),
1155 "[PhwVega20_OD8_InitializeDefaultSettings] Failed to get Base clock voltage from SMU!",
1156 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value = 0);
1157 od_table->GfxclkVolt3 = od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value
1160 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].default_value =
1162 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value =
1164 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].default_value =
1166 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value =
1168 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].default_value =
1170 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value =
1174 if (od8_settings->overdrive8_capabilities & OD8_UCLK_MAX)
1175 od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].default_value =
1178 od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].default_value =
1181 if (od8_settings->overdrive8_capabilities & OD8_POWER_LIMIT)
1182 od8_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].default_value =
1183 od_table->OverDrivePct;
1185 od8_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].default_value =
1188 if (od8_settings->overdrive8_capabilities & OD8_ACOUSTIC_LIMIT_SCLK)
1189 od8_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].default_value =
1190 od_table->FanMaximumRpm;
1192 od8_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].default_value =
1195 if (od8_settings->overdrive8_capabilities & OD8_FAN_SPEED_MIN)
1196 od8_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].default_value =
1197 od_table->FanMinimumPwm * data->smc_state_table.pp_table.FanMaximumRpm / 100;
1199 od8_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].default_value =
1202 if (od8_settings->overdrive8_capabilities & OD8_TEMPERATURE_FAN)
1203 od8_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].default_value =
1204 od_table->FanTargetTemperature;
1206 od8_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].default_value =
1209 if (od8_settings->overdrive8_capabilities & OD8_TEMPERATURE_SYSTEM)
1210 od8_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].default_value =
1211 od_table->MaxOpTemp;
1213 od8_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].default_value =
1216 for (i = 0; i < OD8_SETTING_COUNT; i++) {
1217 if (od8_settings->od8_settings_array[i].feature_id) {
1218 od8_settings->od8_settings_array[i].min_value =
1219 pptable_information->od_settings_min[i];
1220 od8_settings->od8_settings_array[i].max_value =
1221 pptable_information->od_settings_max[i];
1222 od8_settings->od8_settings_array[i].current_value =
1223 od8_settings->od8_settings_array[i].default_value;
1225 od8_settings->od8_settings_array[i].min_value =
1227 od8_settings->od8_settings_array[i].max_value =
1229 od8_settings->od8_settings_array[i].current_value =
1234 ret = smum_smc_table_manager(hwmgr, (uint8_t *)od_table, TABLE_OVERDRIVE, false);
1235 PP_ASSERT_WITH_CODE(!ret,
1236 "Failed to import over drive table!",
1242 static int vega20_od8_set_settings(
1243 struct pp_hwmgr *hwmgr,
1247 OverDriveTable_t od_table;
1249 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
1250 struct vega20_od8_single_setting *od8_settings =
1251 data->od8_settings.od8_settings_array;
1253 ret = smum_smc_table_manager(hwmgr, (uint8_t *)(&od_table), TABLE_OVERDRIVE, true);
1254 PP_ASSERT_WITH_CODE(!ret,
1255 "Failed to export over drive table!",
1259 case OD8_SETTING_GFXCLK_FMIN:
1260 od_table.GfxclkFmin = (uint16_t)value;
1262 case OD8_SETTING_GFXCLK_FMAX:
1263 if (value < od8_settings[OD8_SETTING_GFXCLK_FMAX].min_value ||
1264 value > od8_settings[OD8_SETTING_GFXCLK_FMAX].max_value)
1267 od_table.GfxclkFmax = (uint16_t)value;
1269 case OD8_SETTING_GFXCLK_FREQ1:
1270 od_table.GfxclkFreq1 = (uint16_t)value;
1272 case OD8_SETTING_GFXCLK_VOLTAGE1:
1273 od_table.GfxclkVolt1 = (uint16_t)value;
1275 case OD8_SETTING_GFXCLK_FREQ2:
1276 od_table.GfxclkFreq2 = (uint16_t)value;
1278 case OD8_SETTING_GFXCLK_VOLTAGE2:
1279 od_table.GfxclkVolt2 = (uint16_t)value;
1281 case OD8_SETTING_GFXCLK_FREQ3:
1282 od_table.GfxclkFreq3 = (uint16_t)value;
1284 case OD8_SETTING_GFXCLK_VOLTAGE3:
1285 od_table.GfxclkVolt3 = (uint16_t)value;
1287 case OD8_SETTING_UCLK_FMAX:
1288 if (value < od8_settings[OD8_SETTING_UCLK_FMAX].min_value ||
1289 value > od8_settings[OD8_SETTING_UCLK_FMAX].max_value)
1291 od_table.UclkFmax = (uint16_t)value;
1293 case OD8_SETTING_POWER_PERCENTAGE:
1294 od_table.OverDrivePct = (int16_t)value;
1296 case OD8_SETTING_FAN_ACOUSTIC_LIMIT:
1297 od_table.FanMaximumRpm = (uint16_t)value;
1299 case OD8_SETTING_FAN_MIN_SPEED:
1300 od_table.FanMinimumPwm = (uint16_t)value;
1302 case OD8_SETTING_FAN_TARGET_TEMP:
1303 od_table.FanTargetTemperature = (uint16_t)value;
1305 case OD8_SETTING_OPERATING_TEMP_MAX:
1306 od_table.MaxOpTemp = (uint16_t)value;
1310 ret = smum_smc_table_manager(hwmgr, (uint8_t *)(&od_table), TABLE_OVERDRIVE, false);
1311 PP_ASSERT_WITH_CODE(!ret,
1312 "Failed to import over drive table!",
1318 static int vega20_get_sclk_od(
1319 struct pp_hwmgr *hwmgr)
1321 struct vega20_hwmgr *data = hwmgr->backend;
1322 struct vega20_single_dpm_table *sclk_table =
1323 &(data->dpm_table.gfx_table);
1324 struct vega20_single_dpm_table *golden_sclk_table =
1325 &(data->golden_dpm_table.gfx_table);
1326 int value = sclk_table->dpm_levels[sclk_table->count - 1].value;
1327 int golden_value = golden_sclk_table->dpm_levels
1328 [golden_sclk_table->count - 1].value;
1331 value -= golden_value;
1332 value = DIV_ROUND_UP(value * 100, golden_value);
1337 static int vega20_set_sclk_od(
1338 struct pp_hwmgr *hwmgr, uint32_t value)
1340 struct vega20_hwmgr *data = hwmgr->backend;
1341 struct vega20_single_dpm_table *golden_sclk_table =
1342 &(data->golden_dpm_table.gfx_table);
1346 od_sclk = golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value * value;
1348 od_sclk += golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value;
1350 ret = vega20_od8_set_settings(hwmgr, OD8_SETTING_GFXCLK_FMAX, od_sclk);
1351 PP_ASSERT_WITH_CODE(!ret,
1352 "[SetSclkOD] failed to set od gfxclk!",
1355 /* retrieve updated gfxclk table */
1356 ret = vega20_setup_gfxclk_dpm_table(hwmgr);
1357 PP_ASSERT_WITH_CODE(!ret,
1358 "[SetSclkOD] failed to refresh gfxclk table!",
1364 static int vega20_get_mclk_od(
1365 struct pp_hwmgr *hwmgr)
1367 struct vega20_hwmgr *data = hwmgr->backend;
1368 struct vega20_single_dpm_table *mclk_table =
1369 &(data->dpm_table.mem_table);
1370 struct vega20_single_dpm_table *golden_mclk_table =
1371 &(data->golden_dpm_table.mem_table);
1372 int value = mclk_table->dpm_levels[mclk_table->count - 1].value;
1373 int golden_value = golden_mclk_table->dpm_levels
1374 [golden_mclk_table->count - 1].value;
1377 value -= golden_value;
1378 value = DIV_ROUND_UP(value * 100, golden_value);
1383 static int vega20_set_mclk_od(
1384 struct pp_hwmgr *hwmgr, uint32_t value)
1386 struct vega20_hwmgr *data = hwmgr->backend;
1387 struct vega20_single_dpm_table *golden_mclk_table =
1388 &(data->golden_dpm_table.mem_table);
1392 od_mclk = golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value * value;
1394 od_mclk += golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value;
1396 ret = vega20_od8_set_settings(hwmgr, OD8_SETTING_UCLK_FMAX, od_mclk);
1397 PP_ASSERT_WITH_CODE(!ret,
1398 "[SetMclkOD] failed to set od memclk!",
1401 /* retrieve updated memclk table */
1402 ret = vega20_setup_memclk_dpm_table(hwmgr);
1403 PP_ASSERT_WITH_CODE(!ret,
1404 "[SetMclkOD] failed to refresh memclk table!",
1410 static int vega20_populate_umdpstate_clocks(
1411 struct pp_hwmgr *hwmgr)
1413 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
1414 struct vega20_single_dpm_table *gfx_table = &(data->dpm_table.gfx_table);
1415 struct vega20_single_dpm_table *mem_table = &(data->dpm_table.mem_table);
1417 hwmgr->pstate_sclk = gfx_table->dpm_levels[0].value;
1418 hwmgr->pstate_mclk = mem_table->dpm_levels[0].value;
1420 if (gfx_table->count > VEGA20_UMD_PSTATE_GFXCLK_LEVEL &&
1421 mem_table->count > VEGA20_UMD_PSTATE_MCLK_LEVEL) {
1422 hwmgr->pstate_sclk = gfx_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value;
1423 hwmgr->pstate_mclk = mem_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value;
1426 hwmgr->pstate_sclk = hwmgr->pstate_sclk * 100;
1427 hwmgr->pstate_mclk = hwmgr->pstate_mclk * 100;
1432 static int vega20_get_max_sustainable_clock(struct pp_hwmgr *hwmgr,
1433 PP_Clock *clock, PPCLK_e clock_select)
1437 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,
1438 PPSMC_MSG_GetDcModeMaxDpmFreq,
1439 (clock_select << 16))) == 0,
1440 "[GetMaxSustainableClock] Failed to get max DC clock from SMC!",
1442 *clock = smum_get_argument(hwmgr);
1444 /* if DC limit is zero, return AC limit */
1446 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,
1447 PPSMC_MSG_GetMaxDpmFreq,
1448 (clock_select << 16))) == 0,
1449 "[GetMaxSustainableClock] failed to get max AC clock from SMC!",
1451 *clock = smum_get_argument(hwmgr);
1457 static int vega20_init_max_sustainable_clocks(struct pp_hwmgr *hwmgr)
1459 struct vega20_hwmgr *data =
1460 (struct vega20_hwmgr *)(hwmgr->backend);
1461 struct vega20_max_sustainable_clocks *max_sustainable_clocks =
1462 &(data->max_sustainable_clocks);
1465 max_sustainable_clocks->uclock = data->vbios_boot_state.mem_clock / 100;
1466 max_sustainable_clocks->soc_clock = data->vbios_boot_state.soc_clock / 100;
1467 max_sustainable_clocks->dcef_clock = data->vbios_boot_state.dcef_clock / 100;
1468 max_sustainable_clocks->display_clock = 0xFFFFFFFF;
1469 max_sustainable_clocks->phy_clock = 0xFFFFFFFF;
1470 max_sustainable_clocks->pixel_clock = 0xFFFFFFFF;
1472 if (data->smu_features[GNLD_DPM_UCLK].enabled)
1473 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
1474 &(max_sustainable_clocks->uclock),
1476 "[InitMaxSustainableClocks] failed to get max UCLK from SMC!",
1479 if (data->smu_features[GNLD_DPM_SOCCLK].enabled)
1480 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
1481 &(max_sustainable_clocks->soc_clock),
1482 PPCLK_SOCCLK)) == 0,
1483 "[InitMaxSustainableClocks] failed to get max SOCCLK from SMC!",
1486 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
1487 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
1488 &(max_sustainable_clocks->dcef_clock),
1489 PPCLK_DCEFCLK)) == 0,
1490 "[InitMaxSustainableClocks] failed to get max DCEFCLK from SMC!",
1492 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
1493 &(max_sustainable_clocks->display_clock),
1494 PPCLK_DISPCLK)) == 0,
1495 "[InitMaxSustainableClocks] failed to get max DISPCLK from SMC!",
1497 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
1498 &(max_sustainable_clocks->phy_clock),
1499 PPCLK_PHYCLK)) == 0,
1500 "[InitMaxSustainableClocks] failed to get max PHYCLK from SMC!",
1502 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
1503 &(max_sustainable_clocks->pixel_clock),
1504 PPCLK_PIXCLK)) == 0,
1505 "[InitMaxSustainableClocks] failed to get max PIXCLK from SMC!",
1509 if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock)
1510 max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock;
1515 static int vega20_enable_mgpu_fan_boost(struct pp_hwmgr *hwmgr)
1519 result = smum_send_msg_to_smc(hwmgr,
1520 PPSMC_MSG_SetMGpuFanBoostLimitRpm);
1521 PP_ASSERT_WITH_CODE(!result,
1522 "[EnableMgpuFan] Failed to enable mgpu fan boost!",
1528 static void vega20_init_powergate_state(struct pp_hwmgr *hwmgr)
1530 struct vega20_hwmgr *data =
1531 (struct vega20_hwmgr *)(hwmgr->backend);
1533 data->uvd_power_gated = true;
1534 data->vce_power_gated = true;
1536 if (data->smu_features[GNLD_DPM_UVD].enabled)
1537 data->uvd_power_gated = false;
1539 if (data->smu_features[GNLD_DPM_VCE].enabled)
1540 data->vce_power_gated = false;
1543 static int vega20_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
1547 smum_send_msg_to_smc_with_parameter(hwmgr,
1548 PPSMC_MSG_NumOfDisplays, 0);
1550 result = vega20_set_allowed_featuresmask(hwmgr);
1551 PP_ASSERT_WITH_CODE(!result,
1552 "[EnableDPMTasks] Failed to set allowed featuresmask!\n",
1555 result = vega20_init_smc_table(hwmgr);
1556 PP_ASSERT_WITH_CODE(!result,
1557 "[EnableDPMTasks] Failed to initialize SMC table!",
1560 result = vega20_run_btc_afll(hwmgr);
1561 PP_ASSERT_WITH_CODE(!result,
1562 "[EnableDPMTasks] Failed to run btc afll!",
1565 result = vega20_enable_all_smu_features(hwmgr);
1566 PP_ASSERT_WITH_CODE(!result,
1567 "[EnableDPMTasks] Failed to enable all smu features!",
1570 result = vega20_notify_smc_display_change(hwmgr);
1571 PP_ASSERT_WITH_CODE(!result,
1572 "[EnableDPMTasks] Failed to notify smc display change!",
1575 result = vega20_send_clock_ratio(hwmgr);
1576 PP_ASSERT_WITH_CODE(!result,
1577 "[EnableDPMTasks] Failed to send clock ratio!",
1580 /* Initialize UVD/VCE powergating state */
1581 vega20_init_powergate_state(hwmgr);
1583 result = vega20_setup_default_dpm_tables(hwmgr);
1584 PP_ASSERT_WITH_CODE(!result,
1585 "[EnableDPMTasks] Failed to setup default DPM tables!",
1588 result = vega20_init_max_sustainable_clocks(hwmgr);
1589 PP_ASSERT_WITH_CODE(!result,
1590 "[EnableDPMTasks] Failed to get maximum sustainable clocks!",
1593 result = vega20_power_control_set_level(hwmgr);
1594 PP_ASSERT_WITH_CODE(!result,
1595 "[EnableDPMTasks] Failed to power control set level!",
1598 result = vega20_od8_initialize_default_settings(hwmgr);
1599 PP_ASSERT_WITH_CODE(!result,
1600 "[EnableDPMTasks] Failed to initialize odn settings!",
1603 result = vega20_populate_umdpstate_clocks(hwmgr);
1604 PP_ASSERT_WITH_CODE(!result,
1605 "[EnableDPMTasks] Failed to populate umdpstate clocks!",
1608 result = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetPptLimit,
1609 POWER_SOURCE_AC << 16);
1610 PP_ASSERT_WITH_CODE(!result,
1611 "[GetPptLimit] get default PPT limit failed!",
1613 hwmgr->power_limit =
1614 hwmgr->default_power_limit = smum_get_argument(hwmgr);
1619 static uint32_t vega20_find_lowest_dpm_level(
1620 struct vega20_single_dpm_table *table)
1624 for (i = 0; i < table->count; i++) {
1625 if (table->dpm_levels[i].enabled)
1628 if (i >= table->count) {
1630 table->dpm_levels[i].enabled = true;
1636 static uint32_t vega20_find_highest_dpm_level(
1637 struct vega20_single_dpm_table *table)
1641 PP_ASSERT_WITH_CODE(table != NULL,
1642 "[FindHighestDPMLevel] DPM Table does not exist!",
1644 PP_ASSERT_WITH_CODE(table->count > 0,
1645 "[FindHighestDPMLevel] DPM Table has no entry!",
1647 PP_ASSERT_WITH_CODE(table->count <= MAX_REGULAR_DPM_NUMBER,
1648 "[FindHighestDPMLevel] DPM Table has too many entries!",
1649 return MAX_REGULAR_DPM_NUMBER - 1);
1651 for (i = table->count - 1; i >= 0; i--) {
1652 if (table->dpm_levels[i].enabled)
1657 table->dpm_levels[i].enabled = true;
1663 static int vega20_upload_dpm_min_level(struct pp_hwmgr *hwmgr, uint32_t feature_mask)
1665 struct vega20_hwmgr *data =
1666 (struct vega20_hwmgr *)(hwmgr->backend);
1670 if (data->smu_features[GNLD_DPM_GFXCLK].enabled &&
1671 (feature_mask & FEATURE_DPM_GFXCLK_MASK)) {
1672 min_freq = data->dpm_table.gfx_table.dpm_state.soft_min_level;
1673 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1674 hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1675 (PPCLK_GFXCLK << 16) | (min_freq & 0xffff))),
1676 "Failed to set soft min gfxclk !",
1680 if (data->smu_features[GNLD_DPM_UCLK].enabled &&
1681 (feature_mask & FEATURE_DPM_UCLK_MASK)) {
1682 min_freq = data->dpm_table.mem_table.dpm_state.soft_min_level;
1683 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1684 hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1685 (PPCLK_UCLK << 16) | (min_freq & 0xffff))),
1686 "Failed to set soft min memclk !",
1689 min_freq = data->dpm_table.mem_table.dpm_state.hard_min_level;
1690 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1691 hwmgr, PPSMC_MSG_SetHardMinByFreq,
1692 (PPCLK_UCLK << 16) | (min_freq & 0xffff))),
1693 "Failed to set hard min memclk !",
1697 if (data->smu_features[GNLD_DPM_UVD].enabled &&
1698 (feature_mask & FEATURE_DPM_UVD_MASK)) {
1699 min_freq = data->dpm_table.vclk_table.dpm_state.soft_min_level;
1701 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1702 hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1703 (PPCLK_VCLK << 16) | (min_freq & 0xffff))),
1704 "Failed to set soft min vclk!",
1707 min_freq = data->dpm_table.dclk_table.dpm_state.soft_min_level;
1709 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1710 hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1711 (PPCLK_DCLK << 16) | (min_freq & 0xffff))),
1712 "Failed to set soft min dclk!",
1716 if (data->smu_features[GNLD_DPM_VCE].enabled &&
1717 (feature_mask & FEATURE_DPM_VCE_MASK)) {
1718 min_freq = data->dpm_table.eclk_table.dpm_state.soft_min_level;
1720 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1721 hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1722 (PPCLK_ECLK << 16) | (min_freq & 0xffff))),
1723 "Failed to set soft min eclk!",
1727 if (data->smu_features[GNLD_DPM_SOCCLK].enabled &&
1728 (feature_mask & FEATURE_DPM_SOCCLK_MASK)) {
1729 min_freq = data->dpm_table.soc_table.dpm_state.soft_min_level;
1731 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1732 hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1733 (PPCLK_SOCCLK << 16) | (min_freq & 0xffff))),
1734 "Failed to set soft min socclk!",
1741 static int vega20_upload_dpm_max_level(struct pp_hwmgr *hwmgr, uint32_t feature_mask)
1743 struct vega20_hwmgr *data =
1744 (struct vega20_hwmgr *)(hwmgr->backend);
1748 if (data->smu_features[GNLD_DPM_GFXCLK].enabled &&
1749 (feature_mask & FEATURE_DPM_GFXCLK_MASK)) {
1750 max_freq = data->dpm_table.gfx_table.dpm_state.soft_max_level;
1752 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1753 hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1754 (PPCLK_GFXCLK << 16) | (max_freq & 0xffff))),
1755 "Failed to set soft max gfxclk!",
1759 if (data->smu_features[GNLD_DPM_UCLK].enabled &&
1760 (feature_mask & FEATURE_DPM_UCLK_MASK)) {
1761 max_freq = data->dpm_table.mem_table.dpm_state.soft_max_level;
1763 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1764 hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1765 (PPCLK_UCLK << 16) | (max_freq & 0xffff))),
1766 "Failed to set soft max memclk!",
1770 if (data->smu_features[GNLD_DPM_UVD].enabled &&
1771 (feature_mask & FEATURE_DPM_UVD_MASK)) {
1772 max_freq = data->dpm_table.vclk_table.dpm_state.soft_max_level;
1774 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1775 hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1776 (PPCLK_VCLK << 16) | (max_freq & 0xffff))),
1777 "Failed to set soft max vclk!",
1780 max_freq = data->dpm_table.dclk_table.dpm_state.soft_max_level;
1781 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1782 hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1783 (PPCLK_DCLK << 16) | (max_freq & 0xffff))),
1784 "Failed to set soft max dclk!",
1788 if (data->smu_features[GNLD_DPM_VCE].enabled &&
1789 (feature_mask & FEATURE_DPM_VCE_MASK)) {
1790 max_freq = data->dpm_table.eclk_table.dpm_state.soft_max_level;
1792 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1793 hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1794 (PPCLK_ECLK << 16) | (max_freq & 0xffff))),
1795 "Failed to set soft max eclk!",
1799 if (data->smu_features[GNLD_DPM_SOCCLK].enabled &&
1800 (feature_mask & FEATURE_DPM_SOCCLK_MASK)) {
1801 max_freq = data->dpm_table.soc_table.dpm_state.soft_max_level;
1803 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1804 hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1805 (PPCLK_SOCCLK << 16) | (max_freq & 0xffff))),
1806 "Failed to set soft max socclk!",
1813 int vega20_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
1815 struct vega20_hwmgr *data =
1816 (struct vega20_hwmgr *)(hwmgr->backend);
1819 if (data->smu_features[GNLD_DPM_VCE].supported) {
1820 if (data->smu_features[GNLD_DPM_VCE].enabled == enable) {
1822 PP_DBG_LOG("[EnableDisableVCEDPM] feature VCE DPM already enabled!\n");
1824 PP_DBG_LOG("[EnableDisableVCEDPM] feature VCE DPM already disabled!\n");
1827 ret = vega20_enable_smc_features(hwmgr,
1829 data->smu_features[GNLD_DPM_VCE].smu_feature_bitmap);
1830 PP_ASSERT_WITH_CODE(!ret,
1831 "Attempt to Enable/Disable DPM VCE Failed!",
1833 data->smu_features[GNLD_DPM_VCE].enabled = enable;
1839 static int vega20_get_clock_ranges(struct pp_hwmgr *hwmgr,
1841 PPCLK_e clock_select,
1848 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,
1849 PPSMC_MSG_GetMaxDpmFreq, (clock_select << 16))) == 0,
1850 "[GetClockRanges] Failed to get max clock from SMC!",
1852 *clock = smum_get_argument(hwmgr);
1854 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,
1855 PPSMC_MSG_GetMinDpmFreq,
1856 (clock_select << 16))) == 0,
1857 "[GetClockRanges] Failed to get min clock from SMC!",
1859 *clock = smum_get_argument(hwmgr);
1865 static uint32_t vega20_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
1867 struct vega20_hwmgr *data =
1868 (struct vega20_hwmgr *)(hwmgr->backend);
1872 PP_ASSERT_WITH_CODE(data->smu_features[GNLD_DPM_GFXCLK].enabled,
1873 "[GetSclks]: gfxclk dpm not enabled!\n",
1877 ret = vega20_get_clock_ranges(hwmgr, &gfx_clk, PPCLK_GFXCLK, false);
1878 PP_ASSERT_WITH_CODE(!ret,
1879 "[GetSclks]: fail to get min PPCLK_GFXCLK\n",
1882 ret = vega20_get_clock_ranges(hwmgr, &gfx_clk, PPCLK_GFXCLK, true);
1883 PP_ASSERT_WITH_CODE(!ret,
1884 "[GetSclks]: fail to get max PPCLK_GFXCLK\n",
1888 return (gfx_clk * 100);
1891 static uint32_t vega20_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
1893 struct vega20_hwmgr *data =
1894 (struct vega20_hwmgr *)(hwmgr->backend);
1898 PP_ASSERT_WITH_CODE(data->smu_features[GNLD_DPM_UCLK].enabled,
1899 "[MemMclks]: memclk dpm not enabled!\n",
1903 ret = vega20_get_clock_ranges(hwmgr, &mem_clk, PPCLK_UCLK, false);
1904 PP_ASSERT_WITH_CODE(!ret,
1905 "[GetMclks]: fail to get min PPCLK_UCLK\n",
1908 ret = vega20_get_clock_ranges(hwmgr, &mem_clk, PPCLK_UCLK, true);
1909 PP_ASSERT_WITH_CODE(!ret,
1910 "[GetMclks]: fail to get max PPCLK_UCLK\n",
1914 return (mem_clk * 100);
1917 static int vega20_get_gpu_power(struct pp_hwmgr *hwmgr,
1921 SmuMetrics_t metrics_table;
1923 ret = smum_smc_table_manager(hwmgr, (uint8_t *)&metrics_table, TABLE_SMU_METRICS, true);
1924 PP_ASSERT_WITH_CODE(!ret,
1925 "Failed to export SMU METRICS table!",
1928 *query = metrics_table.CurrSocketPower << 8;
1933 static int vega20_get_current_clk_freq(struct pp_hwmgr *hwmgr,
1934 PPCLK_e clk_id, uint32_t *clk_freq)
1940 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,
1941 PPSMC_MSG_GetDpmClockFreq, (clk_id << 16))) == 0,
1942 "[GetCurrentClkFreq] Attempt to get Current Frequency Failed!",
1944 *clk_freq = smum_get_argument(hwmgr);
1946 *clk_freq = *clk_freq * 100;
1951 static int vega20_get_current_activity_percent(struct pp_hwmgr *hwmgr,
1952 uint32_t *activity_percent)
1955 SmuMetrics_t metrics_table;
1957 ret = smum_smc_table_manager(hwmgr, (uint8_t *)&metrics_table, TABLE_SMU_METRICS, true);
1958 PP_ASSERT_WITH_CODE(!ret,
1959 "Failed to export SMU METRICS table!",
1962 *activity_percent = metrics_table.AverageGfxActivity;
1967 static int vega20_read_sensor(struct pp_hwmgr *hwmgr, int idx,
1968 void *value, int *size)
1970 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
1971 struct amdgpu_device *adev = hwmgr->adev;
1976 case AMDGPU_PP_SENSOR_GFX_SCLK:
1977 ret = vega20_get_current_clk_freq(hwmgr,
1983 case AMDGPU_PP_SENSOR_GFX_MCLK:
1984 ret = vega20_get_current_clk_freq(hwmgr,
1990 case AMDGPU_PP_SENSOR_GPU_LOAD:
1991 ret = vega20_get_current_activity_percent(hwmgr, (uint32_t *)value);
1995 case AMDGPU_PP_SENSOR_GPU_TEMP:
1996 *((uint32_t *)value) = vega20_thermal_get_temperature(hwmgr);
1999 case AMDGPU_PP_SENSOR_UVD_POWER:
2000 *((uint32_t *)value) = data->uvd_power_gated ? 0 : 1;
2003 case AMDGPU_PP_SENSOR_VCE_POWER:
2004 *((uint32_t *)value) = data->vce_power_gated ? 0 : 1;
2007 case AMDGPU_PP_SENSOR_GPU_POWER:
2009 ret = vega20_get_gpu_power(hwmgr, (uint32_t *)value);
2011 case AMDGPU_PP_SENSOR_VDDGFX:
2012 val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_TEL_PLANE0) &
2013 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >>
2014 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT;
2015 *((uint32_t *)value) =
2016 (uint32_t)convert_to_vddc((uint8_t)val_vid);
2018 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:
2019 ret = vega20_get_enabled_smc_features(hwmgr, (uint64_t *)value);
2030 int vega20_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
2031 struct pp_display_clock_request *clock_req)
2034 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2035 enum amd_pp_clock_type clk_type = clock_req->clock_type;
2036 uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
2037 PPCLK_e clk_select = 0;
2038 uint32_t clk_request = 0;
2040 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
2042 case amd_pp_dcef_clock:
2043 clk_select = PPCLK_DCEFCLK;
2045 case amd_pp_disp_clock:
2046 clk_select = PPCLK_DISPCLK;
2048 case amd_pp_pixel_clock:
2049 clk_select = PPCLK_PIXCLK;
2051 case amd_pp_phy_clock:
2052 clk_select = PPCLK_PHYCLK;
2055 pr_info("[DisplayClockVoltageRequest]Invalid Clock Type!");
2061 clk_request = (clk_select << 16) | clk_freq;
2062 result = smum_send_msg_to_smc_with_parameter(hwmgr,
2063 PPSMC_MSG_SetHardMinByFreq,
2071 static int vega20_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
2072 PHM_PerformanceLevelDesignation designation, uint32_t index,
2073 PHM_PerformanceLevel *level)
2078 static int vega20_notify_smc_display_config_after_ps_adjustment(
2079 struct pp_hwmgr *hwmgr)
2081 struct vega20_hwmgr *data =
2082 (struct vega20_hwmgr *)(hwmgr->backend);
2083 struct vega20_single_dpm_table *dpm_table =
2084 &data->dpm_table.mem_table;
2085 struct PP_Clocks min_clocks = {0};
2086 struct pp_display_clock_request clock_req;
2089 min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk;
2090 min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk;
2091 min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock;
2093 if (data->smu_features[GNLD_DPM_DCEFCLK].supported) {
2094 clock_req.clock_type = amd_pp_dcef_clock;
2095 clock_req.clock_freq_in_khz = min_clocks.dcefClock * 10;
2096 if (!vega20_display_clock_voltage_request(hwmgr, &clock_req)) {
2097 if (data->smu_features[GNLD_DS_DCEFCLK].supported)
2098 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(
2099 hwmgr, PPSMC_MSG_SetMinDeepSleepDcefclk,
2100 min_clocks.dcefClockInSR / 100)) == 0,
2101 "Attempt to set divider for DCEFCLK Failed!",
2104 pr_info("Attempt to set Hard Min for DCEFCLK Failed!");
2108 if (data->smu_features[GNLD_DPM_UCLK].enabled) {
2109 dpm_table->dpm_state.hard_min_level = min_clocks.memoryClock / 100;
2110 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(hwmgr,
2111 PPSMC_MSG_SetHardMinByFreq,
2112 (PPCLK_UCLK << 16 ) | dpm_table->dpm_state.hard_min_level)),
2113 "[SetHardMinFreq] Set hard min uclk failed!",
2120 static int vega20_force_dpm_highest(struct pp_hwmgr *hwmgr)
2122 struct vega20_hwmgr *data =
2123 (struct vega20_hwmgr *)(hwmgr->backend);
2124 uint32_t soft_level;
2127 soft_level = vega20_find_highest_dpm_level(&(data->dpm_table.gfx_table));
2129 data->dpm_table.gfx_table.dpm_state.soft_min_level =
2130 data->dpm_table.gfx_table.dpm_state.soft_max_level =
2131 data->dpm_table.gfx_table.dpm_levels[soft_level].value;
2133 soft_level = vega20_find_highest_dpm_level(&(data->dpm_table.mem_table));
2135 data->dpm_table.mem_table.dpm_state.soft_min_level =
2136 data->dpm_table.mem_table.dpm_state.soft_max_level =
2137 data->dpm_table.mem_table.dpm_levels[soft_level].value;
2139 ret = vega20_upload_dpm_min_level(hwmgr, 0xFFFFFFFF);
2140 PP_ASSERT_WITH_CODE(!ret,
2141 "Failed to upload boot level to highest!",
2144 ret = vega20_upload_dpm_max_level(hwmgr, 0xFFFFFFFF);
2145 PP_ASSERT_WITH_CODE(!ret,
2146 "Failed to upload dpm max level to highest!",
2152 static int vega20_force_dpm_lowest(struct pp_hwmgr *hwmgr)
2154 struct vega20_hwmgr *data =
2155 (struct vega20_hwmgr *)(hwmgr->backend);
2156 uint32_t soft_level;
2159 soft_level = vega20_find_lowest_dpm_level(&(data->dpm_table.gfx_table));
2161 data->dpm_table.gfx_table.dpm_state.soft_min_level =
2162 data->dpm_table.gfx_table.dpm_state.soft_max_level =
2163 data->dpm_table.gfx_table.dpm_levels[soft_level].value;
2165 soft_level = vega20_find_lowest_dpm_level(&(data->dpm_table.mem_table));
2167 data->dpm_table.mem_table.dpm_state.soft_min_level =
2168 data->dpm_table.mem_table.dpm_state.soft_max_level =
2169 data->dpm_table.mem_table.dpm_levels[soft_level].value;
2171 ret = vega20_upload_dpm_min_level(hwmgr, 0xFFFFFFFF);
2172 PP_ASSERT_WITH_CODE(!ret,
2173 "Failed to upload boot level to highest!",
2176 ret = vega20_upload_dpm_max_level(hwmgr, 0xFFFFFFFF);
2177 PP_ASSERT_WITH_CODE(!ret,
2178 "Failed to upload dpm max level to highest!",
2185 static int vega20_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
2189 ret = vega20_upload_dpm_min_level(hwmgr, 0xFFFFFFFF);
2190 PP_ASSERT_WITH_CODE(!ret,
2191 "Failed to upload DPM Bootup Levels!",
2194 ret = vega20_upload_dpm_max_level(hwmgr, 0xFFFFFFFF);
2195 PP_ASSERT_WITH_CODE(!ret,
2196 "Failed to upload DPM Max Levels!",
2202 static int vega20_get_profiling_clk_mask(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level,
2203 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask)
2205 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2206 struct vega20_single_dpm_table *gfx_dpm_table = &(data->dpm_table.gfx_table);
2207 struct vega20_single_dpm_table *mem_dpm_table = &(data->dpm_table.mem_table);
2208 struct vega20_single_dpm_table *soc_dpm_table = &(data->dpm_table.soc_table);
2214 if (gfx_dpm_table->count > VEGA20_UMD_PSTATE_GFXCLK_LEVEL &&
2215 mem_dpm_table->count > VEGA20_UMD_PSTATE_MCLK_LEVEL &&
2216 soc_dpm_table->count > VEGA20_UMD_PSTATE_SOCCLK_LEVEL) {
2217 *sclk_mask = VEGA20_UMD_PSTATE_GFXCLK_LEVEL;
2218 *mclk_mask = VEGA20_UMD_PSTATE_MCLK_LEVEL;
2219 *soc_mask = VEGA20_UMD_PSTATE_SOCCLK_LEVEL;
2222 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
2224 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
2226 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2227 *sclk_mask = gfx_dpm_table->count - 1;
2228 *mclk_mask = mem_dpm_table->count - 1;
2229 *soc_mask = soc_dpm_table->count - 1;
2235 static int vega20_force_clock_level(struct pp_hwmgr *hwmgr,
2236 enum pp_clock_type type, uint32_t mask)
2238 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2239 uint32_t soft_min_level, soft_max_level;
2244 soft_min_level = mask ? (ffs(mask) - 1) : 0;
2245 soft_max_level = mask ? (fls(mask) - 1) : 0;
2247 data->dpm_table.gfx_table.dpm_state.soft_min_level =
2248 data->dpm_table.gfx_table.dpm_levels[soft_min_level].value;
2249 data->dpm_table.gfx_table.dpm_state.soft_max_level =
2250 data->dpm_table.gfx_table.dpm_levels[soft_max_level].value;
2252 ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_GFXCLK_MASK);
2253 PP_ASSERT_WITH_CODE(!ret,
2254 "Failed to upload boot level to lowest!",
2257 ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_GFXCLK_MASK);
2258 PP_ASSERT_WITH_CODE(!ret,
2259 "Failed to upload dpm max level to highest!",
2264 soft_min_level = mask ? (ffs(mask) - 1) : 0;
2265 soft_max_level = mask ? (fls(mask) - 1) : 0;
2267 data->dpm_table.mem_table.dpm_state.soft_min_level =
2268 data->dpm_table.mem_table.dpm_levels[soft_min_level].value;
2269 data->dpm_table.mem_table.dpm_state.soft_max_level =
2270 data->dpm_table.mem_table.dpm_levels[soft_max_level].value;
2272 ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_UCLK_MASK);
2273 PP_ASSERT_WITH_CODE(!ret,
2274 "Failed to upload boot level to lowest!",
2277 ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_UCLK_MASK);
2278 PP_ASSERT_WITH_CODE(!ret,
2279 "Failed to upload dpm max level to highest!",
2294 static int vega20_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
2295 enum amd_dpm_forced_level level)
2298 uint32_t sclk_mask, mclk_mask, soc_mask;
2301 case AMD_DPM_FORCED_LEVEL_HIGH:
2302 ret = vega20_force_dpm_highest(hwmgr);
2305 case AMD_DPM_FORCED_LEVEL_LOW:
2306 ret = vega20_force_dpm_lowest(hwmgr);
2309 case AMD_DPM_FORCED_LEVEL_AUTO:
2310 ret = vega20_unforce_dpm_levels(hwmgr);
2313 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
2314 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
2315 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
2316 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
2317 ret = vega20_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask);
2320 vega20_force_clock_level(hwmgr, PP_SCLK, 1 << sclk_mask);
2321 vega20_force_clock_level(hwmgr, PP_MCLK, 1 << mclk_mask);
2324 case AMD_DPM_FORCED_LEVEL_MANUAL:
2325 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
2333 static uint32_t vega20_get_fan_control_mode(struct pp_hwmgr *hwmgr)
2335 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2337 if (data->smu_features[GNLD_FAN_CONTROL].enabled == false)
2338 return AMD_FAN_CTRL_MANUAL;
2340 return AMD_FAN_CTRL_AUTO;
2343 static void vega20_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
2346 case AMD_FAN_CTRL_NONE:
2347 vega20_fan_ctrl_set_fan_speed_percent(hwmgr, 100);
2349 case AMD_FAN_CTRL_MANUAL:
2350 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
2351 vega20_fan_ctrl_stop_smc_fan_control(hwmgr);
2353 case AMD_FAN_CTRL_AUTO:
2354 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
2355 vega20_fan_ctrl_start_smc_fan_control(hwmgr);
2362 static int vega20_get_dal_power_level(struct pp_hwmgr *hwmgr,
2363 struct amd_pp_simple_clock_info *info)
2366 struct phm_ppt_v2_information *table_info =
2367 (struct phm_ppt_v2_information *)hwmgr->pptable;
2368 struct phm_clock_and_voltage_limits *max_limits =
2369 &table_info->max_clock_voltage_on_ac;
2371 info->engine_max_clock = max_limits->sclk;
2372 info->memory_max_clock = max_limits->mclk;
2378 static int vega20_get_sclks(struct pp_hwmgr *hwmgr,
2379 struct pp_clock_levels_with_latency *clocks)
2381 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2382 struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.gfx_table);
2385 PP_ASSERT_WITH_CODE(data->smu_features[GNLD_DPM_GFXCLK].enabled,
2386 "[GetSclks]: gfxclk dpm not enabled!\n",
2389 count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
2390 clocks->num_levels = count;
2392 for (i = 0; i < count; i++) {
2393 clocks->data[i].clocks_in_khz =
2394 dpm_table->dpm_levels[i].value * 1000;
2395 clocks->data[i].latency_in_us = 0;
2401 static uint32_t vega20_get_mem_latency(struct pp_hwmgr *hwmgr,
2407 static int vega20_get_memclocks(struct pp_hwmgr *hwmgr,
2408 struct pp_clock_levels_with_latency *clocks)
2410 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2411 struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.mem_table);
2414 PP_ASSERT_WITH_CODE(data->smu_features[GNLD_DPM_UCLK].enabled,
2415 "[GetMclks]: uclk dpm not enabled!\n",
2418 count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
2419 clocks->num_levels = data->mclk_latency_table.count = count;
2421 for (i = 0; i < count; i++) {
2422 clocks->data[i].clocks_in_khz =
2423 data->mclk_latency_table.entries[i].frequency =
2424 dpm_table->dpm_levels[i].value * 1000;
2425 clocks->data[i].latency_in_us =
2426 data->mclk_latency_table.entries[i].latency =
2427 vega20_get_mem_latency(hwmgr, dpm_table->dpm_levels[i].value);
2433 static int vega20_get_dcefclocks(struct pp_hwmgr *hwmgr,
2434 struct pp_clock_levels_with_latency *clocks)
2436 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2437 struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.dcef_table);
2440 PP_ASSERT_WITH_CODE(data->smu_features[GNLD_DPM_DCEFCLK].enabled,
2441 "[GetDcfclocks]: dcefclk dpm not enabled!\n",
2444 count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
2445 clocks->num_levels = count;
2447 for (i = 0; i < count; i++) {
2448 clocks->data[i].clocks_in_khz =
2449 dpm_table->dpm_levels[i].value * 1000;
2450 clocks->data[i].latency_in_us = 0;
2456 static int vega20_get_socclocks(struct pp_hwmgr *hwmgr,
2457 struct pp_clock_levels_with_latency *clocks)
2459 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2460 struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.soc_table);
2463 PP_ASSERT_WITH_CODE(data->smu_features[GNLD_DPM_SOCCLK].enabled,
2464 "[GetSocclks]: socclk dpm not enabled!\n",
2467 count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
2468 clocks->num_levels = count;
2470 for (i = 0; i < count; i++) {
2471 clocks->data[i].clocks_in_khz =
2472 dpm_table->dpm_levels[i].value * 1000;
2473 clocks->data[i].latency_in_us = 0;
2480 static int vega20_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr,
2481 enum amd_pp_clock_type type,
2482 struct pp_clock_levels_with_latency *clocks)
2487 case amd_pp_sys_clock:
2488 ret = vega20_get_sclks(hwmgr, clocks);
2490 case amd_pp_mem_clock:
2491 ret = vega20_get_memclocks(hwmgr, clocks);
2493 case amd_pp_dcef_clock:
2494 ret = vega20_get_dcefclocks(hwmgr, clocks);
2496 case amd_pp_soc_clock:
2497 ret = vega20_get_socclocks(hwmgr, clocks);
2506 static int vega20_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
2507 enum amd_pp_clock_type type,
2508 struct pp_clock_levels_with_voltage *clocks)
2510 clocks->num_levels = 0;
2515 static int vega20_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
2518 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2519 Watermarks_t *table = &(data->smc_state_table.water_marks_table);
2520 struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_ranges;
2522 if (!data->registry_data.disable_water_mark &&
2523 data->smu_features[GNLD_DPM_DCEFCLK].supported &&
2524 data->smu_features[GNLD_DPM_SOCCLK].supported) {
2525 smu_set_watermarks_for_clocks_ranges(table, wm_with_clock_ranges);
2526 data->water_marks_bitmap |= WaterMarksExist;
2527 data->water_marks_bitmap &= ~WaterMarksLoaded;
2533 static int vega20_odn_edit_dpm_table(struct pp_hwmgr *hwmgr,
2534 enum PP_OD_DPM_TABLE_COMMAND type,
2535 long *input, uint32_t size)
2537 struct vega20_hwmgr *data =
2538 (struct vega20_hwmgr *)(hwmgr->backend);
2539 struct vega20_od8_single_setting *od8_settings =
2540 data->od8_settings.od8_settings_array;
2541 OverDriveTable_t *od_table =
2542 &(data->smc_state_table.overdrive_table);
2543 struct pp_clock_levels_with_latency clocks;
2544 int32_t input_index, input_clk, input_vol, i;
2548 PP_ASSERT_WITH_CODE(input, "NULL user input for clock and voltage",
2552 case PP_OD_EDIT_SCLK_VDDC_TABLE:
2553 if (!(od8_settings[OD8_SETTING_GFXCLK_FMIN].feature_id &&
2554 od8_settings[OD8_SETTING_GFXCLK_FMAX].feature_id)) {
2555 pr_info("Sclk min/max frequency overdrive not supported\n");
2559 for (i = 0; i < size; i += 2) {
2561 pr_info("invalid number of input parameters %d\n",
2566 input_index = input[i];
2567 input_clk = input[i + 1];
2569 if (input_index != 0 && input_index != 1) {
2570 pr_info("Invalid index %d\n", input_index);
2571 pr_info("Support min/max sclk frequency setting only which index by 0/1\n");
2575 if (input_clk < od8_settings[OD8_SETTING_GFXCLK_FMIN].min_value ||
2576 input_clk > od8_settings[OD8_SETTING_GFXCLK_FMAX].max_value) {
2577 pr_info("clock freq %d is not within allowed range [%d - %d]\n",
2579 od8_settings[OD8_SETTING_GFXCLK_FMIN].min_value,
2580 od8_settings[OD8_SETTING_GFXCLK_FMAX].max_value);
2584 if ((input_index == 0 && od_table->GfxclkFmin != input_clk) ||
2585 (input_index == 1 && od_table->GfxclkFmax != input_clk))
2586 data->gfxclk_overdrive = true;
2588 if (input_index == 0)
2589 od_table->GfxclkFmin = input_clk;
2591 od_table->GfxclkFmax = input_clk;
2596 case PP_OD_EDIT_MCLK_VDDC_TABLE:
2597 if (!od8_settings[OD8_SETTING_UCLK_FMAX].feature_id) {
2598 pr_info("Mclk max frequency overdrive not supported\n");
2602 ret = vega20_get_memclocks(hwmgr, &clocks);
2603 PP_ASSERT_WITH_CODE(!ret,
2604 "Attempt to get memory clk levels failed!",
2607 for (i = 0; i < size; i += 2) {
2609 pr_info("invalid number of input parameters %d\n",
2614 input_index = input[i];
2615 input_clk = input[i + 1];
2617 if (input_index != 1) {
2618 pr_info("Invalid index %d\n", input_index);
2619 pr_info("Support max Mclk frequency setting only which index by 1\n");
2623 if (input_clk < clocks.data[0].clocks_in_khz / 1000 ||
2624 input_clk > od8_settings[OD8_SETTING_UCLK_FMAX].max_value) {
2625 pr_info("clock freq %d is not within allowed range [%d - %d]\n",
2627 clocks.data[0].clocks_in_khz / 1000,
2628 od8_settings[OD8_SETTING_UCLK_FMAX].max_value);
2632 if (input_index == 1 && od_table->UclkFmax != input_clk)
2633 data->memclk_overdrive = true;
2635 od_table->UclkFmax = input_clk;
2640 case PP_OD_EDIT_VDDC_CURVE:
2641 if (!(od8_settings[OD8_SETTING_GFXCLK_FREQ1].feature_id &&
2642 od8_settings[OD8_SETTING_GFXCLK_FREQ2].feature_id &&
2643 od8_settings[OD8_SETTING_GFXCLK_FREQ3].feature_id &&
2644 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
2645 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
2646 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id)) {
2647 pr_info("Voltage curve calibrate not supported\n");
2651 for (i = 0; i < size; i += 3) {
2653 pr_info("invalid number of input parameters %d\n",
2658 input_index = input[i];
2659 input_clk = input[i + 1];
2660 input_vol = input[i + 2];
2662 if (input_index > 2) {
2663 pr_info("Setting for point %d is not supported\n",
2665 pr_info("Three supported points index by 0, 1, 2\n");
2669 od8_id = OD8_SETTING_GFXCLK_FREQ1 + 2 * input_index;
2670 if (input_clk < od8_settings[od8_id].min_value ||
2671 input_clk > od8_settings[od8_id].max_value) {
2672 pr_info("clock freq %d is not within allowed range [%d - %d]\n",
2674 od8_settings[od8_id].min_value,
2675 od8_settings[od8_id].max_value);
2679 od8_id = OD8_SETTING_GFXCLK_VOLTAGE1 + 2 * input_index;
2680 if (input_vol < od8_settings[od8_id].min_value ||
2681 input_vol > od8_settings[od8_id].max_value) {
2682 pr_info("clock voltage %d is not within allowed range [%d - %d]\n",
2684 od8_settings[od8_id].min_value,
2685 od8_settings[od8_id].max_value);
2689 switch (input_index) {
2691 od_table->GfxclkFreq1 = input_clk;
2692 od_table->GfxclkVolt1 = input_vol * VOLTAGE_SCALE;
2695 od_table->GfxclkFreq2 = input_clk;
2696 od_table->GfxclkVolt2 = input_vol * VOLTAGE_SCALE;
2699 od_table->GfxclkFreq3 = input_clk;
2700 od_table->GfxclkVolt3 = input_vol * VOLTAGE_SCALE;
2706 case PP_OD_RESTORE_DEFAULT_TABLE:
2707 data->gfxclk_overdrive = false;
2708 data->memclk_overdrive = false;
2710 ret = smum_smc_table_manager(hwmgr,
2711 (uint8_t *)od_table,
2712 TABLE_OVERDRIVE, true);
2713 PP_ASSERT_WITH_CODE(!ret,
2714 "Failed to export overdrive table!",
2718 case PP_OD_COMMIT_DPM_TABLE:
2719 ret = smum_smc_table_manager(hwmgr,
2720 (uint8_t *)od_table,
2721 TABLE_OVERDRIVE, false);
2722 PP_ASSERT_WITH_CODE(!ret,
2723 "Failed to import overdrive table!",
2726 /* retrieve updated gfxclk table */
2727 if (data->gfxclk_overdrive) {
2728 data->gfxclk_overdrive = false;
2730 ret = vega20_setup_gfxclk_dpm_table(hwmgr);
2735 /* retrieve updated memclk table */
2736 if (data->memclk_overdrive) {
2737 data->memclk_overdrive = false;
2739 ret = vega20_setup_memclk_dpm_table(hwmgr);
2752 static int vega20_print_clock_levels(struct pp_hwmgr *hwmgr,
2753 enum pp_clock_type type, char *buf)
2755 struct vega20_hwmgr *data =
2756 (struct vega20_hwmgr *)(hwmgr->backend);
2757 struct vega20_od8_single_setting *od8_settings =
2758 data->od8_settings.od8_settings_array;
2759 OverDriveTable_t *od_table =
2760 &(data->smc_state_table.overdrive_table);
2761 struct pp_clock_levels_with_latency clocks;
2762 int i, now, size = 0;
2767 ret = vega20_get_current_clk_freq(hwmgr, PPCLK_GFXCLK, &now);
2768 PP_ASSERT_WITH_CODE(!ret,
2769 "Attempt to get current gfx clk Failed!",
2772 ret = vega20_get_sclks(hwmgr, &clocks);
2773 PP_ASSERT_WITH_CODE(!ret,
2774 "Attempt to get gfx clk levels Failed!",
2777 for (i = 0; i < clocks.num_levels; i++)
2778 size += sprintf(buf + size, "%d: %uMhz %s\n",
2779 i, clocks.data[i].clocks_in_khz / 1000,
2780 (clocks.data[i].clocks_in_khz == now) ? "*" : "");
2784 ret = vega20_get_current_clk_freq(hwmgr, PPCLK_UCLK, &now);
2785 PP_ASSERT_WITH_CODE(!ret,
2786 "Attempt to get current mclk freq Failed!",
2789 ret = vega20_get_memclocks(hwmgr, &clocks);
2790 PP_ASSERT_WITH_CODE(!ret,
2791 "Attempt to get memory clk levels Failed!",
2794 for (i = 0; i < clocks.num_levels; i++)
2795 size += sprintf(buf + size, "%d: %uMhz %s\n",
2796 i, clocks.data[i].clocks_in_khz / 1000,
2797 (clocks.data[i].clocks_in_khz == now) ? "*" : "");
2804 if (od8_settings[OD8_SETTING_GFXCLK_FMIN].feature_id &&
2805 od8_settings[OD8_SETTING_GFXCLK_FMAX].feature_id) {
2806 size = sprintf(buf, "%s:\n", "OD_SCLK");
2807 size += sprintf(buf + size, "0: %10uMhz\n",
2808 od_table->GfxclkFmin);
2809 size += sprintf(buf + size, "1: %10uMhz\n",
2810 od_table->GfxclkFmax);
2815 if (od8_settings[OD8_SETTING_UCLK_FMAX].feature_id) {
2816 size = sprintf(buf, "%s:\n", "OD_MCLK");
2817 size += sprintf(buf + size, "1: %10uMhz\n",
2818 od_table->UclkFmax);
2824 if (od8_settings[OD8_SETTING_GFXCLK_FREQ1].feature_id &&
2825 od8_settings[OD8_SETTING_GFXCLK_FREQ2].feature_id &&
2826 od8_settings[OD8_SETTING_GFXCLK_FREQ3].feature_id &&
2827 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
2828 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
2829 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id) {
2830 size = sprintf(buf, "%s:\n", "OD_VDDC_CURVE");
2831 size += sprintf(buf + size, "0: %10uMhz %10dmV\n",
2832 od_table->GfxclkFreq1,
2833 od_table->GfxclkVolt1 / VOLTAGE_SCALE);
2834 size += sprintf(buf + size, "1: %10uMhz %10dmV\n",
2835 od_table->GfxclkFreq2,
2836 od_table->GfxclkVolt2 / VOLTAGE_SCALE);
2837 size += sprintf(buf + size, "2: %10uMhz %10dmV\n",
2838 od_table->GfxclkFreq3,
2839 od_table->GfxclkVolt3 / VOLTAGE_SCALE);
2845 size = sprintf(buf, "%s:\n", "OD_RANGE");
2847 if (od8_settings[OD8_SETTING_GFXCLK_FMIN].feature_id &&
2848 od8_settings[OD8_SETTING_GFXCLK_FMAX].feature_id) {
2849 size += sprintf(buf + size, "SCLK: %7uMhz %10uMhz\n",
2850 od8_settings[OD8_SETTING_GFXCLK_FMIN].min_value,
2851 od8_settings[OD8_SETTING_GFXCLK_FMAX].max_value);
2854 if (od8_settings[OD8_SETTING_UCLK_FMAX].feature_id) {
2855 ret = vega20_get_memclocks(hwmgr, &clocks);
2856 PP_ASSERT_WITH_CODE(!ret,
2857 "Fail to get memory clk levels!",
2860 size += sprintf(buf + size, "MCLK: %7uMhz %10uMhz\n",
2861 clocks.data[0].clocks_in_khz / 1000,
2862 od8_settings[OD8_SETTING_UCLK_FMAX].max_value);
2865 if (od8_settings[OD8_SETTING_GFXCLK_FREQ1].feature_id &&
2866 od8_settings[OD8_SETTING_GFXCLK_FREQ2].feature_id &&
2867 od8_settings[OD8_SETTING_GFXCLK_FREQ3].feature_id &&
2868 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
2869 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
2870 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id) {
2871 size += sprintf(buf + size, "VDDC_CURVE_SCLK[0]: %7uMhz %10uMhz\n",
2872 od8_settings[OD8_SETTING_GFXCLK_FREQ1].min_value,
2873 od8_settings[OD8_SETTING_GFXCLK_FREQ1].max_value);
2874 size += sprintf(buf + size, "VDDC_CURVE_VOLT[0]: %7dmV %11dmV\n",
2875 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].min_value,
2876 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].max_value);
2877 size += sprintf(buf + size, "VDDC_CURVE_SCLK[1]: %7uMhz %10uMhz\n",
2878 od8_settings[OD8_SETTING_GFXCLK_FREQ2].min_value,
2879 od8_settings[OD8_SETTING_GFXCLK_FREQ2].max_value);
2880 size += sprintf(buf + size, "VDDC_CURVE_VOLT[1]: %7dmV %11dmV\n",
2881 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].min_value,
2882 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].max_value);
2883 size += sprintf(buf + size, "VDDC_CURVE_SCLK[2]: %7uMhz %10uMhz\n",
2884 od8_settings[OD8_SETTING_GFXCLK_FREQ3].min_value,
2885 od8_settings[OD8_SETTING_GFXCLK_FREQ3].max_value);
2886 size += sprintf(buf + size, "VDDC_CURVE_VOLT[2]: %7dmV %11dmV\n",
2887 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].min_value,
2888 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].max_value);
2898 static int vega20_set_uclk_to_highest_dpm_level(struct pp_hwmgr *hwmgr,
2899 struct vega20_single_dpm_table *dpm_table)
2901 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2904 if (data->smu_features[GNLD_DPM_UCLK].enabled) {
2905 PP_ASSERT_WITH_CODE(dpm_table->count > 0,
2906 "[SetUclkToHightestDpmLevel] Dpm table has no entry!",
2908 PP_ASSERT_WITH_CODE(dpm_table->count <= NUM_UCLK_DPM_LEVELS,
2909 "[SetUclkToHightestDpmLevel] Dpm table has too many entries!",
2912 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2913 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(hwmgr,
2914 PPSMC_MSG_SetHardMinByFreq,
2915 (PPCLK_UCLK << 16 ) | dpm_table->dpm_state.hard_min_level)),
2916 "[SetUclkToHightestDpmLevel] Set hard min uclk failed!",
2923 static int vega20_pre_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
2925 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2928 smum_send_msg_to_smc_with_parameter(hwmgr,
2929 PPSMC_MSG_NumOfDisplays, 0);
2931 ret = vega20_set_uclk_to_highest_dpm_level(hwmgr,
2932 &data->dpm_table.mem_table);
2937 static int vega20_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
2939 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2941 Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table);
2943 if ((data->water_marks_bitmap & WaterMarksExist) &&
2944 !(data->water_marks_bitmap & WaterMarksLoaded)) {
2945 result = smum_smc_table_manager(hwmgr,
2946 (uint8_t *)wm_table, TABLE_WATERMARKS, false);
2947 PP_ASSERT_WITH_CODE(!result,
2948 "Failed to update WMTABLE!",
2950 data->water_marks_bitmap |= WaterMarksLoaded;
2953 if ((data->water_marks_bitmap & WaterMarksExist) &&
2954 data->smu_features[GNLD_DPM_DCEFCLK].supported &&
2955 data->smu_features[GNLD_DPM_SOCCLK].supported) {
2956 result = smum_send_msg_to_smc_with_parameter(hwmgr,
2957 PPSMC_MSG_NumOfDisplays,
2958 hwmgr->display_config->num_display);
2964 int vega20_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
2966 struct vega20_hwmgr *data =
2967 (struct vega20_hwmgr *)(hwmgr->backend);
2970 if (data->smu_features[GNLD_DPM_UVD].supported) {
2971 if (data->smu_features[GNLD_DPM_UVD].enabled == enable) {
2973 PP_DBG_LOG("[EnableDisableUVDDPM] feature DPM UVD already enabled!\n");
2975 PP_DBG_LOG("[EnableDisableUVDDPM] feature DPM UVD already disabled!\n");
2978 ret = vega20_enable_smc_features(hwmgr,
2980 data->smu_features[GNLD_DPM_UVD].smu_feature_bitmap);
2981 PP_ASSERT_WITH_CODE(!ret,
2982 "[EnableDisableUVDDPM] Attempt to Enable/Disable DPM UVD Failed!",
2984 data->smu_features[GNLD_DPM_UVD].enabled = enable;
2990 static void vega20_power_gate_vce(struct pp_hwmgr *hwmgr, bool bgate)
2992 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
2994 if (data->vce_power_gated == bgate)
2997 data->vce_power_gated = bgate;
2998 vega20_enable_disable_vce_dpm(hwmgr, !bgate);
3001 static void vega20_power_gate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
3003 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
3005 if (data->uvd_power_gated == bgate)
3008 data->uvd_power_gated = bgate;
3009 vega20_enable_disable_uvd_dpm(hwmgr, !bgate);
3012 static int vega20_apply_clocks_adjust_rules(struct pp_hwmgr *hwmgr)
3014 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
3015 struct vega20_single_dpm_table *dpm_table;
3016 bool vblank_too_short = false;
3017 bool disable_mclk_switching;
3018 uint32_t i, latency;
3020 disable_mclk_switching = ((1 < hwmgr->display_config->num_display) &&
3021 !hwmgr->display_config->multi_monitor_in_sync) ||
3023 latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency;
3026 dpm_table = &(data->dpm_table.gfx_table);
3027 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3028 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3029 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3030 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3032 if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
3033 if (VEGA20_UMD_PSTATE_GFXCLK_LEVEL < dpm_table->count) {
3034 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value;
3035 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value;
3038 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
3039 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3040 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value;
3043 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
3044 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3045 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3050 dpm_table = &(data->dpm_table.mem_table);
3051 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3052 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3053 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3054 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3056 if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
3057 if (VEGA20_UMD_PSTATE_MCLK_LEVEL < dpm_table->count) {
3058 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value;
3059 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value;
3062 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
3063 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3064 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value;
3067 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
3068 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3069 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3073 /* honour DAL's UCLK Hardmin */
3074 if (dpm_table->dpm_state.hard_min_level < (hwmgr->display_config->min_mem_set_clock / 100))
3075 dpm_table->dpm_state.hard_min_level = hwmgr->display_config->min_mem_set_clock / 100;
3077 /* Hardmin is dependent on displayconfig */
3078 if (disable_mclk_switching) {
3079 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3080 for (i = 0; i < data->mclk_latency_table.count - 1; i++) {
3081 if (data->mclk_latency_table.entries[i].latency <= latency) {
3082 if (dpm_table->dpm_levels[i].value >= (hwmgr->display_config->min_mem_set_clock / 100)) {
3083 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[i].value;
3090 if (hwmgr->display_config->nb_pstate_switch_disable)
3091 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3094 dpm_table = &(data->dpm_table.vclk_table);
3095 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3096 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3097 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3098 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3100 if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
3101 if (VEGA20_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) {
3102 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
3103 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
3106 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
3107 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3108 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3113 dpm_table = &(data->dpm_table.dclk_table);
3114 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3115 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3116 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3117 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3119 if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
3120 if (VEGA20_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) {
3121 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
3122 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value;
3125 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
3126 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3127 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3132 dpm_table = &(data->dpm_table.soc_table);
3133 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3134 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3135 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3136 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3138 if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
3139 if (VEGA20_UMD_PSTATE_SOCCLK_LEVEL < dpm_table->count) {
3140 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_SOCCLK_LEVEL].value;
3141 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_SOCCLK_LEVEL].value;
3144 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
3145 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3146 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3151 dpm_table = &(data->dpm_table.eclk_table);
3152 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
3153 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3154 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
3155 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3157 if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
3158 if (VEGA20_UMD_PSTATE_VCEMCLK_LEVEL < dpm_table->count) {
3159 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_VCEMCLK_LEVEL].value;
3160 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_VCEMCLK_LEVEL].value;
3163 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
3164 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3165 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
3173 vega20_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
3175 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
3176 bool is_update_required = false;
3178 if (data->display_timing.num_existing_displays !=
3179 hwmgr->display_config->num_display)
3180 is_update_required = true;
3182 if (data->registry_data.gfx_clk_deep_sleep_support &&
3183 (data->display_timing.min_clock_in_sr !=
3184 hwmgr->display_config->min_core_set_clock_in_sr))
3185 is_update_required = true;
3187 return is_update_required;
3190 static int vega20_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
3194 ret = vega20_disable_all_smu_features(hwmgr);
3195 PP_ASSERT_WITH_CODE(!ret,
3196 "[DisableDpmTasks] Failed to disable all smu features!",
3202 static int vega20_power_off_asic(struct pp_hwmgr *hwmgr)
3204 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
3207 result = vega20_disable_dpm_tasks(hwmgr);
3208 PP_ASSERT_WITH_CODE((0 == result),
3209 "[PowerOffAsic] Failed to disable DPM!",
3211 data->water_marks_bitmap &= ~(WaterMarksLoaded);
3216 static int conv_power_profile_to_pplib_workload(int power_profile)
3218 int pplib_workload = 0;
3220 switch (power_profile) {
3221 case PP_SMC_POWER_PROFILE_FULLSCREEN3D:
3222 pplib_workload = WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT;
3224 case PP_SMC_POWER_PROFILE_POWERSAVING:
3225 pplib_workload = WORKLOAD_PPLIB_POWER_SAVING_BIT;
3227 case PP_SMC_POWER_PROFILE_VIDEO:
3228 pplib_workload = WORKLOAD_PPLIB_VIDEO_BIT;
3230 case PP_SMC_POWER_PROFILE_VR:
3231 pplib_workload = WORKLOAD_PPLIB_VR_BIT;
3233 case PP_SMC_POWER_PROFILE_COMPUTE:
3234 pplib_workload = WORKLOAD_PPLIB_COMPUTE_BIT;
3236 case PP_SMC_POWER_PROFILE_CUSTOM:
3237 pplib_workload = WORKLOAD_PPLIB_CUSTOM_BIT;
3241 return pplib_workload;
3244 static int vega20_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
3246 DpmActivityMonitorCoeffInt_t activity_monitor;
3247 uint32_t i, size = 0;
3248 uint16_t workload_type = 0;
3249 static const char *profile_name[] = {
3256 static const char *title[] = {
3257 "PROFILE_INDEX(NAME)",
3261 "MinActiveFreqType",
3266 "PD_Data_error_coeff",
3267 "PD_Data_error_rate_coeff"};
3273 size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
3274 title[0], title[1], title[2], title[3], title[4], title[5],
3275 title[6], title[7], title[8], title[9], title[10]);
3277 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
3278 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
3279 workload_type = conv_power_profile_to_pplib_workload(i);
3280 result = vega20_get_activity_monitor_coeff(hwmgr,
3281 (uint8_t *)(&activity_monitor), workload_type);
3282 PP_ASSERT_WITH_CODE(!result,
3283 "[GetPowerProfile] Failed to get activity monitor!",
3286 size += sprintf(buf + size, "%2d %14s%s:\n",
3287 i, profile_name[i], (i == hwmgr->power_profile_mode) ? "*" : " ");
3289 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
3293 activity_monitor.Gfx_FPS,
3294 activity_monitor.Gfx_UseRlcBusy,
3295 activity_monitor.Gfx_MinActiveFreqType,
3296 activity_monitor.Gfx_MinActiveFreq,
3297 activity_monitor.Gfx_BoosterFreqType,
3298 activity_monitor.Gfx_BoosterFreq,
3299 activity_monitor.Gfx_PD_Data_limit_c,
3300 activity_monitor.Gfx_PD_Data_error_coeff,
3301 activity_monitor.Gfx_PD_Data_error_rate_coeff);
3303 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
3307 activity_monitor.Soc_FPS,
3308 activity_monitor.Soc_UseRlcBusy,
3309 activity_monitor.Soc_MinActiveFreqType,
3310 activity_monitor.Soc_MinActiveFreq,
3311 activity_monitor.Soc_BoosterFreqType,
3312 activity_monitor.Soc_BoosterFreq,
3313 activity_monitor.Soc_PD_Data_limit_c,
3314 activity_monitor.Soc_PD_Data_error_coeff,
3315 activity_monitor.Soc_PD_Data_error_rate_coeff);
3317 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
3321 activity_monitor.Mem_FPS,
3322 activity_monitor.Mem_UseRlcBusy,
3323 activity_monitor.Mem_MinActiveFreqType,
3324 activity_monitor.Mem_MinActiveFreq,
3325 activity_monitor.Mem_BoosterFreqType,
3326 activity_monitor.Mem_BoosterFreq,
3327 activity_monitor.Mem_PD_Data_limit_c,
3328 activity_monitor.Mem_PD_Data_error_coeff,
3329 activity_monitor.Mem_PD_Data_error_rate_coeff);
3331 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
3335 activity_monitor.Fclk_FPS,
3336 activity_monitor.Fclk_UseRlcBusy,
3337 activity_monitor.Fclk_MinActiveFreqType,
3338 activity_monitor.Fclk_MinActiveFreq,
3339 activity_monitor.Fclk_BoosterFreqType,
3340 activity_monitor.Fclk_BoosterFreq,
3341 activity_monitor.Fclk_PD_Data_limit_c,
3342 activity_monitor.Fclk_PD_Data_error_coeff,
3343 activity_monitor.Fclk_PD_Data_error_rate_coeff);
3349 static int vega20_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size)
3351 DpmActivityMonitorCoeffInt_t activity_monitor;
3352 int workload_type, result = 0;
3354 hwmgr->power_profile_mode = input[size];
3356 if (hwmgr->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
3357 pr_err("Invalid power profile mode %d\n", hwmgr->power_profile_mode);
3361 if (hwmgr->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
3365 result = vega20_get_activity_monitor_coeff(hwmgr,
3366 (uint8_t *)(&activity_monitor),
3367 WORKLOAD_PPLIB_CUSTOM_BIT);
3368 PP_ASSERT_WITH_CODE(!result,
3369 "[SetPowerProfile] Failed to get activity monitor!",
3373 case 0: /* Gfxclk */
3374 activity_monitor.Gfx_FPS = input[1];
3375 activity_monitor.Gfx_UseRlcBusy = input[2];
3376 activity_monitor.Gfx_MinActiveFreqType = input[3];
3377 activity_monitor.Gfx_MinActiveFreq = input[4];
3378 activity_monitor.Gfx_BoosterFreqType = input[5];
3379 activity_monitor.Gfx_BoosterFreq = input[6];
3380 activity_monitor.Gfx_PD_Data_limit_c = input[7];
3381 activity_monitor.Gfx_PD_Data_error_coeff = input[8];
3382 activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9];
3384 case 1: /* Socclk */
3385 activity_monitor.Soc_FPS = input[1];
3386 activity_monitor.Soc_UseRlcBusy = input[2];
3387 activity_monitor.Soc_MinActiveFreqType = input[3];
3388 activity_monitor.Soc_MinActiveFreq = input[4];
3389 activity_monitor.Soc_BoosterFreqType = input[5];
3390 activity_monitor.Soc_BoosterFreq = input[6];
3391 activity_monitor.Soc_PD_Data_limit_c = input[7];
3392 activity_monitor.Soc_PD_Data_error_coeff = input[8];
3393 activity_monitor.Soc_PD_Data_error_rate_coeff = input[9];
3396 activity_monitor.Mem_FPS = input[1];
3397 activity_monitor.Mem_UseRlcBusy = input[2];
3398 activity_monitor.Mem_MinActiveFreqType = input[3];
3399 activity_monitor.Mem_MinActiveFreq = input[4];
3400 activity_monitor.Mem_BoosterFreqType = input[5];
3401 activity_monitor.Mem_BoosterFreq = input[6];
3402 activity_monitor.Mem_PD_Data_limit_c = input[7];
3403 activity_monitor.Mem_PD_Data_error_coeff = input[8];
3404 activity_monitor.Mem_PD_Data_error_rate_coeff = input[9];
3407 activity_monitor.Fclk_FPS = input[1];
3408 activity_monitor.Fclk_UseRlcBusy = input[2];
3409 activity_monitor.Fclk_MinActiveFreqType = input[3];
3410 activity_monitor.Fclk_MinActiveFreq = input[4];
3411 activity_monitor.Fclk_BoosterFreqType = input[5];
3412 activity_monitor.Fclk_BoosterFreq = input[6];
3413 activity_monitor.Fclk_PD_Data_limit_c = input[7];
3414 activity_monitor.Fclk_PD_Data_error_coeff = input[8];
3415 activity_monitor.Fclk_PD_Data_error_rate_coeff = input[9];
3419 result = vega20_set_activity_monitor_coeff(hwmgr,
3420 (uint8_t *)(&activity_monitor),
3421 WORKLOAD_PPLIB_CUSTOM_BIT);
3422 PP_ASSERT_WITH_CODE(!result,
3423 "[SetPowerProfile] Failed to set activity monitor!",
3427 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
3429 conv_power_profile_to_pplib_workload(hwmgr->power_profile_mode);
3430 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetWorkloadMask,
3431 1 << workload_type);
3436 static int vega20_notify_cac_buffer_info(struct pp_hwmgr *hwmgr,
3437 uint32_t virtual_addr_low,
3438 uint32_t virtual_addr_hi,
3439 uint32_t mc_addr_low,
3440 uint32_t mc_addr_hi,
3443 smum_send_msg_to_smc_with_parameter(hwmgr,
3444 PPSMC_MSG_SetSystemVirtualDramAddrHigh,
3446 smum_send_msg_to_smc_with_parameter(hwmgr,
3447 PPSMC_MSG_SetSystemVirtualDramAddrLow,
3449 smum_send_msg_to_smc_with_parameter(hwmgr,
3450 PPSMC_MSG_DramLogSetDramAddrHigh,
3453 smum_send_msg_to_smc_with_parameter(hwmgr,
3454 PPSMC_MSG_DramLogSetDramAddrLow,
3457 smum_send_msg_to_smc_with_parameter(hwmgr,
3458 PPSMC_MSG_DramLogSetDramSize,
3463 static int vega20_get_thermal_temperature_range(struct pp_hwmgr *hwmgr,
3464 struct PP_TemperatureRange *thermal_data)
3466 struct phm_ppt_v3_information *pptable_information =
3467 (struct phm_ppt_v3_information *)hwmgr->pptable;
3469 memcpy(thermal_data, &SMU7ThermalWithDelayPolicy[0], sizeof(struct PP_TemperatureRange));
3471 thermal_data->max = pptable_information->us_software_shutdown_temp *
3472 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
3477 static const struct pp_hwmgr_func vega20_hwmgr_funcs = {
3478 /* init/fini related */
3480 vega20_hwmgr_backend_init,
3482 vega20_hwmgr_backend_fini,
3484 vega20_setup_asic_task,
3486 vega20_power_off_asic,
3487 .dynamic_state_management_enable =
3488 vega20_enable_dpm_tasks,
3489 .dynamic_state_management_disable =
3490 vega20_disable_dpm_tasks,
3491 /* power state related */
3492 .apply_clocks_adjust_rules =
3493 vega20_apply_clocks_adjust_rules,
3494 .pre_display_config_changed =
3495 vega20_pre_display_configuration_changed_task,
3496 .display_config_changed =
3497 vega20_display_configuration_changed_task,
3498 .check_smc_update_required_for_display_configuration =
3499 vega20_check_smc_update_required_for_display_configuration,
3500 .notify_smc_display_config_after_ps_adjustment =
3501 vega20_notify_smc_display_config_after_ps_adjustment,
3504 vega20_dpm_get_sclk,
3506 vega20_dpm_get_mclk,
3507 .get_dal_power_level =
3508 vega20_get_dal_power_level,
3509 .get_clock_by_type_with_latency =
3510 vega20_get_clock_by_type_with_latency,
3511 .get_clock_by_type_with_voltage =
3512 vega20_get_clock_by_type_with_voltage,
3513 .set_watermarks_for_clocks_ranges =
3514 vega20_set_watermarks_for_clocks_ranges,
3515 .display_clock_voltage_request =
3516 vega20_display_clock_voltage_request,
3517 .get_performance_level =
3518 vega20_get_performance_level,
3519 /* UMD pstate, profile related */
3521 vega20_dpm_force_dpm_level,
3522 .get_power_profile_mode =
3523 vega20_get_power_profile_mode,
3524 .set_power_profile_mode =
3525 vega20_set_power_profile_mode,
3528 vega20_set_power_limit,
3537 .odn_edit_dpm_table =
3538 vega20_odn_edit_dpm_table,
3539 /* for sysfs to retrive/set gfxclk/memclk */
3540 .force_clock_level =
3541 vega20_force_clock_level,
3542 .print_clock_levels =
3543 vega20_print_clock_levels,
3546 /* powergate related */
3548 vega20_power_gate_uvd,
3550 vega20_power_gate_vce,
3551 /* thermal related */
3552 .start_thermal_controller =
3553 vega20_start_thermal_controller,
3554 .stop_thermal_controller =
3555 vega20_thermal_stop_thermal_controller,
3556 .get_thermal_temperature_range =
3557 vega20_get_thermal_temperature_range,
3558 .register_irq_handlers =
3559 smu9_register_irq_handlers,
3560 .disable_smc_firmware_ctf =
3561 vega20_thermal_disable_alert,
3562 /* fan control related */
3563 .get_fan_speed_percent =
3564 vega20_fan_ctrl_get_fan_speed_percent,
3565 .set_fan_speed_percent =
3566 vega20_fan_ctrl_set_fan_speed_percent,
3567 .get_fan_speed_info =
3568 vega20_fan_ctrl_get_fan_speed_info,
3569 .get_fan_speed_rpm =
3570 vega20_fan_ctrl_get_fan_speed_rpm,
3571 .set_fan_speed_rpm =
3572 vega20_fan_ctrl_set_fan_speed_rpm,
3573 .get_fan_control_mode =
3574 vega20_get_fan_control_mode,
3575 .set_fan_control_mode =
3576 vega20_set_fan_control_mode,
3577 /* smu memory related */
3578 .notify_cac_buffer_info =
3579 vega20_notify_cac_buffer_info,
3580 .enable_mgpu_fan_boost =
3581 vega20_enable_mgpu_fan_boost,
3584 int vega20_hwmgr_init(struct pp_hwmgr *hwmgr)
3586 hwmgr->hwmgr_func = &vega20_hwmgr_funcs;
3587 hwmgr->pptable_func = &vega20_pptable_funcs;