drivers/gpu/drm/amd/powerplay/navi10_ppt.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "pp_debug.h"
  25 #include <linux/firmware.h>
  26 #include <linux/pci.h>
  27 #include "amdgpu.h"
  28 #include "amdgpu_smu.h"
  29 #include "smu_internal.h"
  30 #include "atomfirmware.h"
  31 #include "amdgpu_atomfirmware.h"
  32 #include "smu_v11_0.h"
  33 #include "smu11_driver_if_navi10.h"
  34 #include "soc15_common.h"
  35 #include "atom.h"
  36 #include "navi10_ppt.h"
  37 #include "smu_v11_0_pptable.h"
  38 #include "smu_v11_0_ppsmc.h"
  39 #include "nbio/nbio_7_4_sh_mask.h"
  40
  41 #include "asic_reg/mp/mp_11_0_sh_mask.h"
  42
  43 #define FEATURE_MASK(feature) (1ULL << feature)
  44 #define SMC_DPM_FEATURE ( \
  45         FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \
  46         FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT)     | \
  47         FEATURE_MASK(FEATURE_DPM_GFX_PACE_BIT)   | \
  48         FEATURE_MASK(FEATURE_DPM_UCLK_BIT)       | \
  49         FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT)     | \
  50         FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)     | \
  51         FEATURE_MASK(FEATURE_DPM_LINK_BIT)       | \
  52         FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT))
  53
  54 #define MSG_MAP(msg, index) \
  55         [SMU_MSG_##msg] = {1, (index)}
  56
  57 static struct smu_11_0_cmn2aisc_mapping navi10_message_map[SMU_MSG_MAX_COUNT] = {
  58         MSG_MAP(TestMessage,                    PPSMC_MSG_TestMessage),
  59         MSG_MAP(GetSmuVersion,                  PPSMC_MSG_GetSmuVersion),
  60         MSG_MAP(GetDriverIfVersion,             PPSMC_MSG_GetDriverIfVersion),
  61         MSG_MAP(SetAllowedFeaturesMaskLow,      PPSMC_MSG_SetAllowedFeaturesMaskLow),
  62         MSG_MAP(SetAllowedFeaturesMaskHigh,     PPSMC_MSG_SetAllowedFeaturesMaskHigh),
  63         MSG_MAP(EnableAllSmuFeatures,           PPSMC_MSG_EnableAllSmuFeatures),
  64         MSG_MAP(DisableAllSmuFeatures,          PPSMC_MSG_DisableAllSmuFeatures),
  65         MSG_MAP(EnableSmuFeaturesLow,           PPSMC_MSG_EnableSmuFeaturesLow),
  66         MSG_MAP(EnableSmuFeaturesHigh,          PPSMC_MSG_EnableSmuFeaturesHigh),
  67         MSG_MAP(DisableSmuFeaturesLow,          PPSMC_MSG_DisableSmuFeaturesLow),
  68         MSG_MAP(DisableSmuFeaturesHigh,         PPSMC_MSG_DisableSmuFeaturesHigh),
  69         MSG_MAP(GetEnabledSmuFeaturesLow,       PPSMC_MSG_GetEnabledSmuFeaturesLow),
  70         MSG_MAP(GetEnabledSmuFeaturesHigh,      PPSMC_MSG_GetEnabledSmuFeaturesHigh),
  71         MSG_MAP(SetWorkloadMask,                PPSMC_MSG_SetWorkloadMask),
  72         MSG_MAP(SetPptLimit,                    PPSMC_MSG_SetPptLimit),
  73         MSG_MAP(SetDriverDramAddrHigh,          PPSMC_MSG_SetDriverDramAddrHigh),
  74         MSG_MAP(SetDriverDramAddrLow,           PPSMC_MSG_SetDriverDramAddrLow),
  75         MSG_MAP(SetToolsDramAddrHigh,           PPSMC_MSG_SetToolsDramAddrHigh),
  76         MSG_MAP(SetToolsDramAddrLow,            PPSMC_MSG_SetToolsDramAddrLow),
  77         MSG_MAP(TransferTableSmu2Dram,          PPSMC_MSG_TransferTableSmu2Dram),
  78         MSG_MAP(TransferTableDram2Smu,          PPSMC_MSG_TransferTableDram2Smu),
  79         MSG_MAP(UseDefaultPPTable,              PPSMC_MSG_UseDefaultPPTable),
  80         MSG_MAP(UseBackupPPTable,               PPSMC_MSG_UseBackupPPTable),
  81         MSG_MAP(RunBtc,                         PPSMC_MSG_RunBtc),
  82         MSG_MAP(EnterBaco,                      PPSMC_MSG_EnterBaco),
  83         MSG_MAP(SetSoftMinByFreq,               PPSMC_MSG_SetSoftMinByFreq),
  84         MSG_MAP(SetSoftMaxByFreq,               PPSMC_MSG_SetSoftMaxByFreq),
  85         MSG_MAP(SetHardMinByFreq,               PPSMC_MSG_SetHardMinByFreq),
  86         MSG_MAP(SetHardMaxByFreq,               PPSMC_MSG_SetHardMaxByFreq),
  87         MSG_MAP(GetMinDpmFreq,                  PPSMC_MSG_GetMinDpmFreq),
  88         MSG_MAP(GetMaxDpmFreq,                  PPSMC_MSG_GetMaxDpmFreq),
  89         MSG_MAP(GetDpmFreqByIndex,              PPSMC_MSG_GetDpmFreqByIndex),
  90         MSG_MAP(SetMemoryChannelConfig,         PPSMC_MSG_SetMemoryChannelConfig),
  91         MSG_MAP(SetGeminiMode,                  PPSMC_MSG_SetGeminiMode),
  92         MSG_MAP(SetGeminiApertureHigh,          PPSMC_MSG_SetGeminiApertureHigh),
  93         MSG_MAP(SetGeminiApertureLow,           PPSMC_MSG_SetGeminiApertureLow),
  94         MSG_MAP(OverridePcieParameters,         PPSMC_MSG_OverridePcieParameters),
  95         MSG_MAP(SetMinDeepSleepDcefclk,         PPSMC_MSG_SetMinDeepSleepDcefclk),
  96         MSG_MAP(ReenableAcDcInterrupt,          PPSMC_MSG_ReenableAcDcInterrupt),
  97         MSG_MAP(NotifyPowerSource,              PPSMC_MSG_NotifyPowerSource),
  98         MSG_MAP(SetUclkFastSwitch,              PPSMC_MSG_SetUclkFastSwitch),
  99         MSG_MAP(SetVideoFps,                    PPSMC_MSG_SetVideoFps),
 100         MSG_MAP(PrepareMp1ForUnload,            PPSMC_MSG_PrepareMp1ForUnload),
 101         MSG_MAP(DramLogSetDramAddrHigh,         PPSMC_MSG_DramLogSetDramAddrHigh),
 102         MSG_MAP(DramLogSetDramAddrLow,          PPSMC_MSG_DramLogSetDramAddrLow),
 103         MSG_MAP(DramLogSetDramSize,             PPSMC_MSG_DramLogSetDramSize),
 104         MSG_MAP(ConfigureGfxDidt,               PPSMC_MSG_ConfigureGfxDidt),
 105         MSG_MAP(NumOfDisplays,                  PPSMC_MSG_NumOfDisplays),
 106         MSG_MAP(SetSystemVirtualDramAddrHigh,   PPSMC_MSG_SetSystemVirtualDramAddrHigh),
 107         MSG_MAP(SetSystemVirtualDramAddrLow,    PPSMC_MSG_SetSystemVirtualDramAddrLow),
 108         MSG_MAP(AllowGfxOff,                    PPSMC_MSG_AllowGfxOff),
 109         MSG_MAP(DisallowGfxOff,                 PPSMC_MSG_DisallowGfxOff),
 110         MSG_MAP(GetPptLimit,                    PPSMC_MSG_GetPptLimit),
 111         MSG_MAP(GetDcModeMaxDpmFreq,            PPSMC_MSG_GetDcModeMaxDpmFreq),
 112         MSG_MAP(GetDebugData,                   PPSMC_MSG_GetDebugData),
 113         MSG_MAP(ExitBaco,                       PPSMC_MSG_ExitBaco),
 114         MSG_MAP(PrepareMp1ForReset,             PPSMC_MSG_PrepareMp1ForReset),
 115         MSG_MAP(PrepareMp1ForShutdown,          PPSMC_MSG_PrepareMp1ForShutdown),
 116         MSG_MAP(PowerUpVcn,             PPSMC_MSG_PowerUpVcn),
 117         MSG_MAP(PowerDownVcn,           PPSMC_MSG_PowerDownVcn),
 118         MSG_MAP(PowerUpJpeg,            PPSMC_MSG_PowerUpJpeg),
 119         MSG_MAP(PowerDownJpeg,          PPSMC_MSG_PowerDownJpeg),
 120         MSG_MAP(BacoAudioD3PME,         PPSMC_MSG_BacoAudioD3PME),
 121         MSG_MAP(ArmD3,                  PPSMC_MSG_ArmD3),
 122         MSG_MAP(DAL_DISABLE_DUMMY_PSTATE_CHANGE,PPSMC_MSG_DALDisableDummyPstateChange),
 123         MSG_MAP(DAL_ENABLE_DUMMY_PSTATE_CHANGE, PPSMC_MSG_DALEnableDummyPstateChange),
 124         MSG_MAP(GetVoltageByDpm,                     PPSMC_MSG_GetVoltageByDpm),
 125         MSG_MAP(GetVoltageByDpmOverdrive,            PPSMC_MSG_GetVoltageByDpmOverdrive),
 126 };
 127
 128 static struct smu_11_0_cmn2aisc_mapping navi10_clk_map[SMU_CLK_COUNT] = {
 129         CLK_MAP(GFXCLK, PPCLK_GFXCLK),
 130         CLK_MAP(SCLK,   PPCLK_GFXCLK),
 131         CLK_MAP(SOCCLK, PPCLK_SOCCLK),
 132         CLK_MAP(FCLK, PPCLK_SOCCLK),
 133         CLK_MAP(UCLK, PPCLK_UCLK),
 134         CLK_MAP(MCLK, PPCLK_UCLK),
 135         CLK_MAP(DCLK, PPCLK_DCLK),
 136         CLK_MAP(VCLK, PPCLK_VCLK),
 137         CLK_MAP(DCEFCLK, PPCLK_DCEFCLK),
 138         CLK_MAP(DISPCLK, PPCLK_DISPCLK),
 139         CLK_MAP(PIXCLK, PPCLK_PIXCLK),
 140         CLK_MAP(PHYCLK, PPCLK_PHYCLK),
 141 };
 142
 143 static struct smu_11_0_cmn2aisc_mapping navi10_feature_mask_map[SMU_FEATURE_COUNT] = {
 144         FEA_MAP(DPM_PREFETCHER),
 145         FEA_MAP(DPM_GFXCLK),
 146         FEA_MAP(DPM_GFX_PACE),
 147         FEA_MAP(DPM_UCLK),
 148         FEA_MAP(DPM_SOCCLK),
 149         FEA_MAP(DPM_MP0CLK),
 150         FEA_MAP(DPM_LINK),
 151         FEA_MAP(DPM_DCEFCLK),
 152         FEA_MAP(MEM_VDDCI_SCALING),
 153         FEA_MAP(MEM_MVDD_SCALING),
 154         FEA_MAP(DS_GFXCLK),
 155         FEA_MAP(DS_SOCCLK),
 156         FEA_MAP(DS_LCLK),
 157         FEA_MAP(DS_DCEFCLK),
 158         FEA_MAP(DS_UCLK),
 159         FEA_MAP(GFX_ULV),
 160         FEA_MAP(FW_DSTATE),
 161         FEA_MAP(GFXOFF),
 162         FEA_MAP(BACO),
 163         FEA_MAP(VCN_PG),
 164         FEA_MAP(JPEG_PG),
 165         FEA_MAP(USB_PG),
 166         FEA_MAP(RSMU_SMN_CG),
 167         FEA_MAP(PPT),
 168         FEA_MAP(TDC),
 169         FEA_MAP(GFX_EDC),
 170         FEA_MAP(APCC_PLUS),
 171         FEA_MAP(GTHR),
 172         FEA_MAP(ACDC),
 173         FEA_MAP(VR0HOT),
 174         FEA_MAP(VR1HOT),
 175         FEA_MAP(FW_CTF),
 176         FEA_MAP(FAN_CONTROL),
 177         FEA_MAP(THERMAL),
 178         FEA_MAP(GFX_DCS),
 179         FEA_MAP(RM),
 180         FEA_MAP(LED_DISPLAY),
 181         FEA_MAP(GFX_SS),
 182         FEA_MAP(OUT_OF_BAND_MONITOR),
 183         FEA_MAP(TEMP_DEPENDENT_VMIN),
 184         FEA_MAP(MMHUB_PG),
 185         FEA_MAP(ATHUB_PG),
 186         FEA_MAP(APCC_DFLL),
 187 };
 188
 189 static struct smu_11_0_cmn2aisc_mapping navi10_table_map[SMU_TABLE_COUNT] = {
 190         TAB_MAP(PPTABLE),
 191         TAB_MAP(WATERMARKS),
 192         TAB_MAP(AVFS),
 193         TAB_MAP(AVFS_PSM_DEBUG),
 194         TAB_MAP(AVFS_FUSE_OVERRIDE),
 195         TAB_MAP(PMSTATUSLOG),
 196         TAB_MAP(SMU_METRICS),
 197         TAB_MAP(DRIVER_SMU_CONFIG),
 198         TAB_MAP(ACTIVITY_MONITOR_COEFF),
 199         TAB_MAP(OVERDRIVE),
 200         TAB_MAP(I2C_COMMANDS),
 201         TAB_MAP(PACE),
 202 };
 203
 204 static struct smu_11_0_cmn2aisc_mapping navi10_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
 205         PWR_MAP(AC),
 206         PWR_MAP(DC),
 207 };
 208
 209 static struct smu_11_0_cmn2aisc_mapping navi10_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
 210         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT,       WORKLOAD_PPLIB_DEFAULT_BIT),
 211         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D,         WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
 212         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING,          WORKLOAD_PPLIB_POWER_SAVING_BIT),
 213         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO,                WORKLOAD_PPLIB_VIDEO_BIT),
 214         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR,                   WORKLOAD_PPLIB_VR_BIT),
 215         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE,              WORKLOAD_PPLIB_COMPUTE_BIT),
 216         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,               WORKLOAD_PPLIB_CUSTOM_BIT),
 217 };
 218
 219 static int navi10_get_smu_msg_index(struct smu_context *smc, uint32_t index)
 220 {
 221         struct smu_11_0_cmn2aisc_mapping mapping;
 222
 223         if (index >= SMU_MSG_MAX_COUNT)
 224                 return -EINVAL;
 225
 226         mapping = navi10_message_map[index];
 227         if (!(mapping.valid_mapping)) {
 228                 return -EINVAL;
 229         }
 230
 231         return mapping.map_to;
 232 }
 233
 234 static int navi10_get_smu_clk_index(struct smu_context *smc, uint32_t index)
 235 {
 236         struct smu_11_0_cmn2aisc_mapping mapping;
 237
 238         if (index >= SMU_CLK_COUNT)
 239                 return -EINVAL;
 240
 241         mapping = navi10_clk_map[index];
 242         if (!(mapping.valid_mapping)) {
 243                 return -EINVAL;
 244         }
 245
 246         return mapping.map_to;
 247 }
 248
 249 static int navi10_get_smu_feature_index(struct smu_context *smc, uint32_t index)
 250 {
 251         struct smu_11_0_cmn2aisc_mapping mapping;
 252
 253         if (index >= SMU_FEATURE_COUNT)
 254                 return -EINVAL;
 255
 256         mapping = navi10_feature_mask_map[index];
 257         if (!(mapping.valid_mapping)) {
 258                 return -EINVAL;
 259         }
 260
 261         return mapping.map_to;
 262 }
 263
 264 static int navi10_get_smu_table_index(struct smu_context *smc, uint32_t index)
 265 {
 266         struct smu_11_0_cmn2aisc_mapping mapping;
 267
 268         if (index >= SMU_TABLE_COUNT)
 269                 return -EINVAL;
 270
 271         mapping = navi10_table_map[index];
 272         if (!(mapping.valid_mapping)) {
 273                 return -EINVAL;
 274         }
 275
 276         return mapping.map_to;
 277 }
 278
 279 static int navi10_get_pwr_src_index(struct smu_context *smc, uint32_t index)
 280 {
 281         struct smu_11_0_cmn2aisc_mapping mapping;
 282
 283         if (index >= SMU_POWER_SOURCE_COUNT)
 284                 return -EINVAL;
 285
 286         mapping = navi10_pwr_src_map[index];
 287         if (!(mapping.valid_mapping)) {
 288                 return -EINVAL;
 289         }
 290
 291         return mapping.map_to;
 292 }
 293
 294
 295 static int navi10_get_workload_type(struct smu_context *smu, enum PP_SMC_POWER_PROFILE profile)
 296 {
 297         struct smu_11_0_cmn2aisc_mapping mapping;
 298
 299         if (profile > PP_SMC_POWER_PROFILE_CUSTOM)
 300                 return -EINVAL;
 301
 302         mapping = navi10_workload_map[profile];
 303         if (!(mapping.valid_mapping)) {
 304                 return -EINVAL;
 305         }
 306
 307         return mapping.map_to;
 308 }
 309
 310 static bool is_asic_secure(struct smu_context *smu)
 311 {
 312         struct amdgpu_device *adev = smu->adev;
 313         bool is_secure = true;
 314         uint32_t mp0_fw_intf;
 315
 316         mp0_fw_intf = RREG32_PCIE(MP0_Public |
 317                                    (smnMP0_FW_INTF & 0xffffffff));
 318
 319         if (!(mp0_fw_intf & (1 << 19)))
 320                 is_secure = false;
 321
 322         return is_secure;
 323 }
 324
 325 static int
 326 navi10_get_allowed_feature_mask(struct smu_context *smu,
 327                                   uint32_t *feature_mask, uint32_t num)
 328 {
 329         struct amdgpu_device *adev = smu->adev;
 330
 331         if (num > 2)
 332                 return -EINVAL;
 333
 334         memset(feature_mask, 0, sizeof(uint32_t) * num);
 335
 336         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
 337                                 | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)
 338                                 | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT)
 339                                 | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
 340                                 | FEATURE_MASK(FEATURE_PPT_BIT)
 341                                 | FEATURE_MASK(FEATURE_TDC_BIT)
 342                                 | FEATURE_MASK(FEATURE_GFX_EDC_BIT)
 343                                 | FEATURE_MASK(FEATURE_APCC_PLUS_BIT)
 344                                 | FEATURE_MASK(FEATURE_VR0HOT_BIT)
 345                                 | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
 346                                 | FEATURE_MASK(FEATURE_THERMAL_BIT)
 347                                 | FEATURE_MASK(FEATURE_LED_DISPLAY_BIT)
 348                                 | FEATURE_MASK(FEATURE_DS_LCLK_BIT)
 349                                 | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
 350                                 | FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
 351                                 | FEATURE_MASK(FEATURE_BACO_BIT)
 352                                 | FEATURE_MASK(FEATURE_ACDC_BIT)
 353                                 | FEATURE_MASK(FEATURE_GFX_SS_BIT)
 354                                 | FEATURE_MASK(FEATURE_APCC_DFLL_BIT)
 355                                 | FEATURE_MASK(FEATURE_FW_CTF_BIT)
 356                                 | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT);
 357
 358         if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
 359                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
 360
 361         if (adev->pm.pp_feature & PP_SCLK_DPM_MASK)
 362                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
 363
 364         if (adev->pm.pp_feature & PP_PCIE_DPM_MASK)
 365                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT);
 366
 367         if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)
 368                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT);
 369
 370         if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
 371                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
 372                                 | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
 373                                 | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
 374
 375         if (adev->pm.pp_feature & PP_ULV_MASK)
 376                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);
 377
 378         if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
 379                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
 380
 381         if (adev->pm.pp_feature & PP_GFXOFF_MASK)
 382                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
 383
 384         if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB)
 385                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT);
 386
 387         if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB)
 388                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT);
 389
 390         if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN)
 391                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VCN_PG_BIT);
 392
 393         if (smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG)
 394                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_JPEG_PG_BIT);
 395
 396         /* disable DPM UCLK and DS SOCCLK on navi10 A0 secure board */
 397         if (is_asic_secure(smu)) {
 398                 /* only for navi10 A0 */
 399                 if ((adev->asic_type == CHIP_NAVI10) &&
 400                         (adev->rev_id == 0)) {
 401                         *(uint64_t *)feature_mask &=
 402                                         ~(FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
 403                                           | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
 404                                           | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT));
 405                         *(uint64_t *)feature_mask &=
 406                                         ~FEATURE_MASK(FEATURE_DS_SOCCLK_BIT);
 407                 }
 408         }
 409
 410         return 0;
 411 }
 412
 413 static int navi10_check_powerplay_table(struct smu_context *smu)
 414 {
 415         return 0;
 416 }
 417
 418 static int navi10_append_powerplay_table(struct smu_context *smu)
 419 {
 420         struct amdgpu_device *adev = smu->adev;
 421         struct smu_table_context *table_context = &smu->smu_table;
 422         PPTable_t *smc_pptable = table_context->driver_pptable;
 423         struct atom_smc_dpm_info_v4_5 *smc_dpm_table;
 424         int index, ret;
 425
 426         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 427                                            smc_dpm_info);
 428
 429         ret = smu_get_atom_data_table(smu, index, NULL, NULL, NULL,
 430                                       (uint8_t **)&smc_dpm_table);
 431         if (ret)
 432                 return ret;
 433
 434         memcpy(smc_pptable->I2cControllers, smc_dpm_table->I2cControllers,
 435                sizeof(I2cControllerConfig_t) * NUM_I2C_CONTROLLERS);
 436
 437         /* SVI2 Board Parameters */
 438         smc_pptable->MaxVoltageStepGfx = smc_dpm_table->MaxVoltageStepGfx;
 439         smc_pptable->MaxVoltageStepSoc = smc_dpm_table->MaxVoltageStepSoc;
 440         smc_pptable->VddGfxVrMapping = smc_dpm_table->VddGfxVrMapping;
 441         smc_pptable->VddSocVrMapping = smc_dpm_table->VddSocVrMapping;
 442         smc_pptable->VddMem0VrMapping = smc_dpm_table->VddMem0VrMapping;
 443         smc_pptable->VddMem1VrMapping = smc_dpm_table->VddMem1VrMapping;
 444         smc_pptable->GfxUlvPhaseSheddingMask = smc_dpm_table->GfxUlvPhaseSheddingMask;
 445         smc_pptable->SocUlvPhaseSheddingMask = smc_dpm_table->SocUlvPhaseSheddingMask;
 446         smc_pptable->ExternalSensorPresent = smc_dpm_table->ExternalSensorPresent;
 447         smc_pptable->Padding8_V = smc_dpm_table->Padding8_V;
 448
 449         /* Telemetry Settings */
 450         smc_pptable->GfxMaxCurrent = smc_dpm_table->GfxMaxCurrent;
 451         smc_pptable->GfxOffset = smc_dpm_table->GfxOffset;
 452         smc_pptable->Padding_TelemetryGfx = smc_dpm_table->Padding_TelemetryGfx;
 453         smc_pptable->SocMaxCurrent = smc_dpm_table->SocMaxCurrent;
 454         smc_pptable->SocOffset = smc_dpm_table->SocOffset;
 455         smc_pptable->Padding_TelemetrySoc = smc_dpm_table->Padding_TelemetrySoc;
 456         smc_pptable->Mem0MaxCurrent = smc_dpm_table->Mem0MaxCurrent;
 457         smc_pptable->Mem0Offset = smc_dpm_table->Mem0Offset;
 458         smc_pptable->Padding_TelemetryMem0 = smc_dpm_table->Padding_TelemetryMem0;
 459         smc_pptable->Mem1MaxCurrent = smc_dpm_table->Mem1MaxCurrent;
 460         smc_pptable->Mem1Offset = smc_dpm_table->Mem1Offset;
 461         smc_pptable->Padding_TelemetryMem1 = smc_dpm_table->Padding_TelemetryMem1;
 462
 463         /* GPIO Settings */
 464         smc_pptable->AcDcGpio = smc_dpm_table->AcDcGpio;
 465         smc_pptable->AcDcPolarity = smc_dpm_table->AcDcPolarity;
 466         smc_pptable->VR0HotGpio = smc_dpm_table->VR0HotGpio;
 467         smc_pptable->VR0HotPolarity = smc_dpm_table->VR0HotPolarity;
 468         smc_pptable->VR1HotGpio = smc_dpm_table->VR1HotGpio;
 469         smc_pptable->VR1HotPolarity = smc_dpm_table->VR1HotPolarity;
 470         smc_pptable->GthrGpio = smc_dpm_table->GthrGpio;
 471         smc_pptable->GthrPolarity = smc_dpm_table->GthrPolarity;
 472
 473         /* LED Display Settings */
 474         smc_pptable->LedPin0 = smc_dpm_table->LedPin0;
 475         smc_pptable->LedPin1 = smc_dpm_table->LedPin1;
 476         smc_pptable->LedPin2 = smc_dpm_table->LedPin2;
 477         smc_pptable->padding8_4 = smc_dpm_table->padding8_4;
 478
 479         /* GFXCLK PLL Spread Spectrum */
 480         smc_pptable->PllGfxclkSpreadEnabled = smc_dpm_table->PllGfxclkSpreadEnabled;
 481         smc_pptable->PllGfxclkSpreadPercent = smc_dpm_table->PllGfxclkSpreadPercent;
 482         smc_pptable->PllGfxclkSpreadFreq = smc_dpm_table->PllGfxclkSpreadFreq;
 483
 484         /* GFXCLK DFLL Spread Spectrum */
 485         smc_pptable->DfllGfxclkSpreadEnabled = smc_dpm_table->DfllGfxclkSpreadEnabled;
 486         smc_pptable->DfllGfxclkSpreadPercent = smc_dpm_table->DfllGfxclkSpreadPercent;
 487         smc_pptable->DfllGfxclkSpreadFreq = smc_dpm_table->DfllGfxclkSpreadFreq;
 488
 489         /* UCLK Spread Spectrum */
 490         smc_pptable->UclkSpreadEnabled = smc_dpm_table->UclkSpreadEnabled;
 491         smc_pptable->UclkSpreadPercent = smc_dpm_table->UclkSpreadPercent;
 492         smc_pptable->UclkSpreadFreq = smc_dpm_table->UclkSpreadFreq;
 493
 494         /* SOCCLK Spread Spectrum */
 495         smc_pptable->SoclkSpreadEnabled = smc_dpm_table->SoclkSpreadEnabled;
 496         smc_pptable->SocclkSpreadPercent = smc_dpm_table->SocclkSpreadPercent;
 497         smc_pptable->SocclkSpreadFreq = smc_dpm_table->SocclkSpreadFreq;
 498
 499         /* Total board power */
 500         smc_pptable->TotalBoardPower = smc_dpm_table->TotalBoardPower;
 501         smc_pptable->BoardPadding = smc_dpm_table->BoardPadding;
 502
 503         /* Mvdd Svi2 Div Ratio Setting */
 504         smc_pptable->MvddRatio = smc_dpm_table->MvddRatio;
 505
 506         if (adev->pm.pp_feature & PP_GFXOFF_MASK) {
 507                 /* TODO: remove it once SMU fw fix it */
 508                 smc_pptable->DebugOverrides |= DPM_OVERRIDE_DISABLE_DFLL_PLL_SHUTDOWN;
 509         }
 510
 511         return 0;
 512 }
 513
 514 static int navi10_store_powerplay_table(struct smu_context *smu)
 515 {
 516         struct smu_11_0_powerplay_table *powerplay_table = NULL;
 517         struct smu_table_context *table_context = &smu->smu_table;
 518         struct smu_baco_context *smu_baco = &smu->smu_baco;
 519
 520         if (!table_context->power_play_table)
 521                 return -EINVAL;
 522
 523         powerplay_table = table_context->power_play_table;
 524
 525         memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
 526                sizeof(PPTable_t));
 527
 528         table_context->thermal_controller_type = powerplay_table->thermal_controller_type;
 529
 530         mutex_lock(&smu_baco->mutex);
 531         if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_BACO ||
 532             powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO)
 533                 smu_baco->platform_support = true;
 534         mutex_unlock(&smu_baco->mutex);
 535
 536         return 0;
 537 }
 538
 539 static int navi10_tables_init(struct smu_context *smu, struct smu_table *tables)
 540 {
 541         struct smu_table_context *smu_table = &smu->smu_table;
 542
 543         SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
 544                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 545         SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
 546                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 547         SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
 548                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 549         SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
 550                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 551         SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
 552                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 553         SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
 554                        sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE,
 555                        AMDGPU_GEM_DOMAIN_VRAM);
 556
 557         smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
 558         if (!smu_table->metrics_table)
 559                 return -ENOMEM;
 560         smu_table->metrics_time = 0;
 561
 562         smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
 563         if (!smu_table->watermarks_table)
 564                 return -ENOMEM;
 565
 566         return 0;
 567 }
 568
 569 static int navi10_get_metrics_table(struct smu_context *smu,
 570                                     SmuMetrics_t *metrics_table)
 571 {
 572         struct smu_table_context *smu_table= &smu->smu_table;
 573         int ret = 0;
 574
 575         mutex_lock(&smu->metrics_lock);
 576         if (!smu_table->metrics_time || time_after(jiffies, smu_table->metrics_time + msecs_to_jiffies(100))) {
 577                 ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
 578                                 (void *)smu_table->metrics_table, false);
 579                 if (ret) {
 580                         pr_info("Failed to export SMU metrics table!\n");
 581                         mutex_unlock(&smu->metrics_lock);
 582                         return ret;
 583                 }
 584                 smu_table->metrics_time = jiffies;
 585         }
 586
 587         memcpy(metrics_table, smu_table->metrics_table, sizeof(SmuMetrics_t));
 588         mutex_unlock(&smu->metrics_lock);
 589
 590         return ret;
 591 }
 592
 593 static int navi10_allocate_dpm_context(struct smu_context *smu)
 594 {
 595         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 596
 597         if (smu_dpm->dpm_context)
 598                 return -EINVAL;
 599
 600         smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
 601                                        GFP_KERNEL);
 602         if (!smu_dpm->dpm_context)
 603                 return -ENOMEM;
 604
 605         smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
 606
 607         return 0;
 608 }
 609
 610 static int navi10_set_default_dpm_table(struct smu_context *smu)
 611 {
 612         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 613         struct smu_table_context *table_context = &smu->smu_table;
 614         struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
 615         PPTable_t *driver_ppt = NULL;
 616         int i;
 617
 618         driver_ppt = table_context->driver_pptable;
 619
 620         dpm_context->dpm_tables.soc_table.min = driver_ppt->FreqTableSocclk[0];
 621         dpm_context->dpm_tables.soc_table.max = driver_ppt->FreqTableSocclk[NUM_SOCCLK_DPM_LEVELS - 1];
 622
 623         dpm_context->dpm_tables.gfx_table.min = driver_ppt->FreqTableGfx[0];
 624         dpm_context->dpm_tables.gfx_table.max = driver_ppt->FreqTableGfx[NUM_GFXCLK_DPM_LEVELS - 1];
 625
 626         dpm_context->dpm_tables.uclk_table.min = driver_ppt->FreqTableUclk[0];
 627         dpm_context->dpm_tables.uclk_table.max = driver_ppt->FreqTableUclk[NUM_UCLK_DPM_LEVELS - 1];
 628
 629         dpm_context->dpm_tables.vclk_table.min = driver_ppt->FreqTableVclk[0];
 630         dpm_context->dpm_tables.vclk_table.max = driver_ppt->FreqTableVclk[NUM_VCLK_DPM_LEVELS - 1];
 631
 632         dpm_context->dpm_tables.dclk_table.min = driver_ppt->FreqTableDclk[0];
 633         dpm_context->dpm_tables.dclk_table.max = driver_ppt->FreqTableDclk[NUM_DCLK_DPM_LEVELS - 1];
 634
 635         dpm_context->dpm_tables.dcef_table.min = driver_ppt->FreqTableDcefclk[0];
 636         dpm_context->dpm_tables.dcef_table.max = driver_ppt->FreqTableDcefclk[NUM_DCEFCLK_DPM_LEVELS - 1];
 637
 638         dpm_context->dpm_tables.pixel_table.min = driver_ppt->FreqTablePixclk[0];
 639         dpm_context->dpm_tables.pixel_table.max = driver_ppt->FreqTablePixclk[NUM_PIXCLK_DPM_LEVELS - 1];
 640
 641         dpm_context->dpm_tables.display_table.min = driver_ppt->FreqTableDispclk[0];
 642         dpm_context->dpm_tables.display_table.max = driver_ppt->FreqTableDispclk[NUM_DISPCLK_DPM_LEVELS - 1];
 643
 644         dpm_context->dpm_tables.phy_table.min = driver_ppt->FreqTablePhyclk[0];
 645         dpm_context->dpm_tables.phy_table.max = driver_ppt->FreqTablePhyclk[NUM_PHYCLK_DPM_LEVELS - 1];
 646
 647         for (i = 0; i < MAX_PCIE_CONF; i++) {
 648                 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = driver_ppt->PcieGenSpeed[i];
 649                 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = driver_ppt->PcieLaneCount[i];
 650         }
 651
 652         return 0;
 653 }
 654
 655 static int navi10_dpm_set_uvd_enable(struct smu_context *smu, bool enable)
 656 {
 657         struct smu_power_context *smu_power = &smu->smu_power;
 658         struct smu_power_gate *power_gate = &smu_power->power_gate;
 659         int ret = 0;
 660
 661         if (enable) {
 662                 /* vcn dpm on is a prerequisite for vcn power gate messages */
 663                 if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
 664                         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 1);
 665                         if (ret)
 666                                 return ret;
 667                 }
 668                 power_gate->vcn_gated = false;
 669         } else {
 670                 if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
 671                         ret = smu_send_smc_msg(smu, SMU_MSG_PowerDownVcn);
 672                         if (ret)
 673                                 return ret;
 674                 }
 675                 power_gate->vcn_gated = true;
 676         }
 677
 678         return ret;
 679 }
 680
 681 static int navi10_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
 682 {
 683         struct smu_power_context *smu_power = &smu->smu_power;
 684         struct smu_power_gate *power_gate = &smu_power->power_gate;
 685         int ret = 0;
 686
 687         if (enable) {
 688                 if (smu_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
 689                         ret = smu_send_smc_msg(smu, SMU_MSG_PowerUpJpeg);
 690                         if (ret)
 691                                 return ret;
 692                 }
 693                 power_gate->jpeg_gated = false;
 694         } else {
 695                 if (smu_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
 696                         ret = smu_send_smc_msg(smu, SMU_MSG_PowerDownJpeg);
 697                         if (ret)
 698                                 return ret;
 699                 }
 700                 power_gate->jpeg_gated = true;
 701         }
 702
 703         return ret;
 704 }
 705
 706 static int navi10_get_current_clk_freq_by_table(struct smu_context *smu,
 707                                        enum smu_clk_type clk_type,
 708                                        uint32_t *value)
 709 {
 710         int ret = 0, clk_id = 0;
 711         SmuMetrics_t metrics;
 712
 713         ret = navi10_get_metrics_table(smu, &metrics);
 714         if (ret)
 715                 return ret;
 716
 717         clk_id = smu_clk_get_index(smu, clk_type);
 718         if (clk_id < 0)
 719                 return clk_id;
 720
 721         *value = metrics.CurrClock[clk_id];
 722
 723         return ret;
 724 }
 725
 726 static bool navi10_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type)
 727 {
 728         PPTable_t *pptable = smu->smu_table.driver_pptable;
 729         DpmDescriptor_t *dpm_desc = NULL;
 730         uint32_t clk_index = 0;
 731
 732         clk_index = smu_clk_get_index(smu, clk_type);
 733         dpm_desc = &pptable->DpmDescriptor[clk_index];
 734
 735         /* 0 - Fine grained DPM, 1 - Discrete DPM */
 736         return dpm_desc->SnapToDiscrete == 0 ? true : false;
 737 }
 738
 739 static inline bool navi10_od_feature_is_supported(struct smu_11_0_overdrive_table *od_table, enum SMU_11_0_ODFEATURE_CAP cap)
 740 {
 741         return od_table->cap[cap];
 742 }
 743
 744 static void navi10_od_setting_get_range(struct smu_11_0_overdrive_table *od_table,
 745                                         enum SMU_11_0_ODSETTING_ID setting,
 746                                         uint32_t *min, uint32_t *max)
 747 {
 748         if (min)
 749                 *min = od_table->min[setting];
 750         if (max)
 751                 *max = od_table->max[setting];
 752 }
 753
 754 static int navi10_print_clk_levels(struct smu_context *smu,
 755                         enum smu_clk_type clk_type, char *buf)
 756 {
 757         uint16_t *curve_settings;
 758         int i, size = 0, ret = 0;
 759         uint32_t cur_value = 0, value = 0, count = 0;
 760         uint32_t freq_values[3] = {0};
 761         uint32_t mark_index = 0;
 762         struct smu_table_context *table_context = &smu->smu_table;
 763         uint32_t gen_speed, lane_width;
 764         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 765         struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
 766         struct amdgpu_device *adev = smu->adev;
 767         PPTable_t *pptable = (PPTable_t *)table_context->driver_pptable;
 768         OverDriveTable_t *od_table =
 769                 (OverDriveTable_t *)table_context->overdrive_table;
 770         struct smu_11_0_overdrive_table *od_settings = smu->od_settings;
 771         uint32_t min_value, max_value;
 772
 773         switch (clk_type) {
 774         case SMU_GFXCLK:
 775         case SMU_SCLK:
 776         case SMU_SOCCLK:
 777         case SMU_MCLK:
 778         case SMU_UCLK:
 779         case SMU_FCLK:
 780         case SMU_DCEFCLK:
 781                 ret = smu_get_current_clk_freq(smu, clk_type, &cur_value);
 782                 if (ret)
 783                         return size;
 784
 785                 /* 10KHz -> MHz */
 786                 cur_value = cur_value / 100;
 787
 788                 ret = smu_get_dpm_level_count(smu, clk_type, &count);
 789                 if (ret)
 790                         return size;
 791
 792                 if (!navi10_is_support_fine_grained_dpm(smu, clk_type)) {
 793                         for (i = 0; i < count; i++) {
 794                                 ret = smu_get_dpm_freq_by_index(smu, clk_type, i, &value);
 795                                 if (ret)
 796                                         return size;
 797
 798                                 size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
 799                                                 cur_value == value ? "*" : "");
 800                         }
 801                 } else {
 802                         ret = smu_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]);
 803                         if (ret)
 804                                 return size;
 805                         ret = smu_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]);
 806                         if (ret)
 807                                 return size;
 808
 809                         freq_values[1] = cur_value;
 810                         mark_index = cur_value == freq_values[0] ? 0 :
 811                                      cur_value == freq_values[2] ? 2 : 1;
 812                         if (mark_index != 1)
 813                                 freq_values[1] = (freq_values[0] + freq_values[2]) / 2;
 814
 815                         for (i = 0; i < 3; i++) {
 816                                 size += sprintf(buf + size, "%d: %uMhz %s\n", i, freq_values[i],
 817                                                 i == mark_index ? "*" : "");
 818                         }
 819
 820                 }
 821                 break;
 822         case SMU_PCIE:
 823                 gen_speed = (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
 824                              PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
 825                         >> PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
 826                 lane_width = (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
 827                               PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
 828                         >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
 829                 for (i = 0; i < NUM_LINK_LEVELS; i++)
 830                         size += sprintf(buf + size, "%d: %s %s %dMhz %s\n", i,
 831                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," :
 832                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," :
 833                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," :
 834                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "",
 835                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" :
 836                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" :
 837                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" :
 838                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" :
 839                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" :
 840                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "",
 841                                         pptable->LclkFreq[i],
 842                                         (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) &&
 843                                         (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ?
 844                                         "*" : "");
 845                 break;
 846         case SMU_OD_SCLK:
 847                 if (!smu->od_enabled || !od_table || !od_settings)
 848                         break;
 849                 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS))
 850                         break;
 851                 size += sprintf(buf + size, "OD_SCLK:\n");
 852                 size += sprintf(buf + size, "0: %uMhz\n1: %uMhz\n", od_table->GfxclkFmin, od_table->GfxclkFmax);
 853                 break;
 854         case SMU_OD_MCLK:
 855                 if (!smu->od_enabled || !od_table || !od_settings)
 856                         break;
 857                 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX))
 858                         break;
 859                 size += sprintf(buf + size, "OD_MCLK:\n");
 860                 size += sprintf(buf + size, "1: %uMHz\n", od_table->UclkFmax);
 861                 break;
 862         case SMU_OD_VDDC_CURVE:
 863                 if (!smu->od_enabled || !od_table || !od_settings)
 864                         break;
 865                 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE))
 866                         break;
 867                 size += sprintf(buf + size, "OD_VDDC_CURVE:\n");
 868                 for (i = 0; i < 3; i++) {
 869                         switch (i) {
 870                         case 0:
 871                                 curve_settings = &od_table->GfxclkFreq1;
 872                                 break;
 873                         case 1:
 874                                 curve_settings = &od_table->GfxclkFreq2;
 875                                 break;
 876                         case 2:
 877                                 curve_settings = &od_table->GfxclkFreq3;
 878                                 break;
 879                         default:
 880                                 break;
 881                         }
 882                         size += sprintf(buf + size, "%d: %uMHz @ %umV\n", i, curve_settings[0], curve_settings[1] / NAVI10_VOLTAGE_SCALE);
 883                 }
 884                 break;
 885         case SMU_OD_RANGE:
 886                 if (!smu->od_enabled || !od_table || !od_settings)
 887                         break;
 888                 size = sprintf(buf, "%s:\n", "OD_RANGE");
 889
 890                 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS)) {
 891                         navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_GFXCLKFMIN,
 892                                                     &min_value, NULL);
 893                         navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_GFXCLKFMAX,
 894                                                     NULL, &max_value);
 895                         size += sprintf(buf + size, "SCLK: %7uMhz %10uMhz\n",
 896                                         min_value, max_value);
 897                 }
 898
 899                 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX)) {
 900                         navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_UCLKFMAX,
 901                                                     &min_value, &max_value);
 902                         size += sprintf(buf + size, "MCLK: %7uMhz %10uMhz\n",
 903                                         min_value, max_value);
 904                 }
 905
 906                 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE)) {
 907                         navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P1,
 908                                                     &min_value, &max_value);
 909                         size += sprintf(buf + size, "VDDC_CURVE_SCLK[0]: %7uMhz %10uMhz\n",
 910                                         min_value, max_value);
 911                         navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P1,
 912                                                     &min_value, &max_value);
 913                         size += sprintf(buf + size, "VDDC_CURVE_VOLT[0]: %7dmV %11dmV\n",
 914                                         min_value, max_value);
 915                         navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P2,
 916                                                     &min_value, &max_value);
 917                         size += sprintf(buf + size, "VDDC_CURVE_SCLK[1]: %7uMhz %10uMhz\n",
 918                                         min_value, max_value);
 919                         navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P2,
 920                                                     &min_value, &max_value);
 921                         size += sprintf(buf + size, "VDDC_CURVE_VOLT[1]: %7dmV %11dmV\n",
 922                                         min_value, max_value);
 923                         navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P3,
 924                                                     &min_value, &max_value);
 925                         size += sprintf(buf + size, "VDDC_CURVE_SCLK[2]: %7uMhz %10uMhz\n",
 926                                         min_value, max_value);
 927                         navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P3,
 928                                                     &min_value, &max_value);
 929                         size += sprintf(buf + size, "VDDC_CURVE_VOLT[2]: %7dmV %11dmV\n",
 930                                         min_value, max_value);
 931                 }
 932
 933                 break;
 934         default:
 935                 break;
 936         }
 937
 938         return size;
 939 }
 940
 941 static int navi10_force_clk_levels(struct smu_context *smu,
 942                                    enum smu_clk_type clk_type, uint32_t mask)
 943 {
 944
 945         int ret = 0, size = 0;
 946         uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;
 947
 948         soft_min_level = mask ? (ffs(mask) - 1) : 0;
 949         soft_max_level = mask ? (fls(mask) - 1) : 0;
 950
 951         switch (clk_type) {
 952         case SMU_GFXCLK:
 953         case SMU_SCLK:
 954         case SMU_SOCCLK:
 955         case SMU_MCLK:
 956         case SMU_UCLK:
 957         case SMU_DCEFCLK:
 958         case SMU_FCLK:
 959                 /* There is only 2 levels for fine grained DPM */
 960                 if (navi10_is_support_fine_grained_dpm(smu, clk_type)) {
 961                         soft_max_level = (soft_max_level >= 1 ? 1 : 0);
 962                         soft_min_level = (soft_min_level >= 1 ? 1 : 0);
 963                 }
 964
 965                 ret = smu_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
 966                 if (ret)
 967                         return size;
 968
 969                 ret = smu_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
 970                 if (ret)
 971                         return size;
 972
 973                 ret = smu_set_soft_freq_range(smu, clk_type, min_freq, max_freq);
 974                 if (ret)
 975                         return size;
 976                 break;
 977         default:
 978                 break;
 979         }
 980
 981         return size;
 982 }
 983
 984 static int navi10_populate_umd_state_clk(struct smu_context *smu)
 985 {
 986         int ret = 0;
 987         uint32_t min_sclk_freq = 0, min_mclk_freq = 0;
 988
 989         ret = smu_get_dpm_freq_range(smu, SMU_SCLK, &min_sclk_freq, NULL, false);
 990         if (ret)
 991                 return ret;
 992
 993         smu->pstate_sclk = min_sclk_freq * 100;
 994
 995         ret = smu_get_dpm_freq_range(smu, SMU_MCLK, &min_mclk_freq, NULL, false);
 996         if (ret)
 997                 return ret;
 998
 999         smu->pstate_mclk = min_mclk_freq * 100;
1000
1001         return ret;
1002 }
1003
1004 static int navi10_get_clock_by_type_with_latency(struct smu_context *smu,
1005                                                  enum smu_clk_type clk_type,
1006                                                  struct pp_clock_levels_with_latency *clocks)
1007 {
1008         int ret = 0, i = 0;
1009         uint32_t level_count = 0, freq = 0;
1010
1011         switch (clk_type) {
1012         case SMU_GFXCLK:
1013         case SMU_DCEFCLK:
1014         case SMU_SOCCLK:
1015         case SMU_MCLK:
1016         case SMU_UCLK:
1017                 ret = smu_get_dpm_level_count(smu, clk_type, &level_count);
1018                 if (ret)
1019                         return ret;
1020
1021                 level_count = min(level_count, (uint32_t)MAX_NUM_CLOCKS);
1022                 clocks->num_levels = level_count;
1023
1024                 for (i = 0; i < level_count; i++) {
1025                         ret = smu_get_dpm_freq_by_index(smu, clk_type, i, &freq);
1026                         if (ret)
1027                                 return ret;
1028
1029                         clocks->data[i].clocks_in_khz = freq * 1000;
1030                         clocks->data[i].latency_in_us = 0;
1031                 }
1032                 break;
1033         default:
1034                 break;
1035         }
1036
1037         return ret;
1038 }
1039
1040 static int navi10_pre_display_config_changed(struct smu_context *smu)
1041 {
1042         int ret = 0;
1043         uint32_t max_freq = 0;
1044
1045         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0);
1046         if (ret)
1047                 return ret;
1048
1049         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1050                 ret = smu_get_dpm_freq_range(smu, SMU_UCLK, NULL, &max_freq, false);
1051                 if (ret)
1052                         return ret;
1053                 ret = smu_set_hard_freq_range(smu, SMU_UCLK, 0, max_freq);
1054                 if (ret)
1055                         return ret;
1056         }
1057
1058         return ret;
1059 }
1060
1061 static int navi10_display_config_changed(struct smu_context *smu)
1062 {
1063         int ret = 0;
1064
1065         if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1066             smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
1067             smu_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
1068                 ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays,
1069                                                   smu->display_config->num_display);
1070                 if (ret)
1071                         return ret;
1072         }
1073
1074         return ret;
1075 }
1076
1077 static int navi10_force_dpm_limit_value(struct smu_context *smu, bool highest)
1078 {
1079         int ret = 0, i = 0;
1080         uint32_t min_freq, max_freq, force_freq;
1081         enum smu_clk_type clk_type;
1082
1083         enum smu_clk_type clks[] = {
1084                 SMU_GFXCLK,
1085                 SMU_MCLK,
1086                 SMU_SOCCLK,
1087         };
1088
1089         for (i = 0; i < ARRAY_SIZE(clks); i++) {
1090                 clk_type = clks[i];
1091                 ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq, false);
1092                 if (ret)
1093                         return ret;
1094
1095                 force_freq = highest ? max_freq : min_freq;
1096                 ret = smu_set_soft_freq_range(smu, clk_type, force_freq, force_freq);
1097                 if (ret)
1098                         return ret;
1099         }
1100
1101         return ret;
1102 }
1103
1104 static int navi10_unforce_dpm_levels(struct smu_context *smu)
1105 {
1106         int ret = 0, i = 0;
1107         uint32_t min_freq, max_freq;
1108         enum smu_clk_type clk_type;
1109
1110         enum smu_clk_type clks[] = {
1111                 SMU_GFXCLK,
1112                 SMU_MCLK,
1113                 SMU_SOCCLK,
1114         };
1115
1116         for (i = 0; i < ARRAY_SIZE(clks); i++) {
1117                 clk_type = clks[i];
1118                 ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq, false);
1119                 if (ret)
1120                         return ret;
1121
1122                 ret = smu_set_soft_freq_range(smu, clk_type, min_freq, max_freq);
1123                 if (ret)
1124                         return ret;
1125         }
1126
1127         return ret;
1128 }
1129
1130 static int navi10_get_gpu_power(struct smu_context *smu, uint32_t *value)
1131 {
1132         int ret = 0;
1133         SmuMetrics_t metrics;
1134
1135         if (!value)
1136                 return -EINVAL;
1137
1138         ret = navi10_get_metrics_table(smu, &metrics);
1139         if (ret)
1140                 return ret;
1141
1142         *value = metrics.AverageSocketPower << 8;
1143
1144         return 0;
1145 }
1146
1147 static int navi10_get_current_activity_percent(struct smu_context *smu,
1148                                                enum amd_pp_sensors sensor,
1149                                                uint32_t *value)
1150 {
1151         int ret = 0;
1152         SmuMetrics_t metrics;
1153
1154         if (!value)
1155                 return -EINVAL;
1156
1157         ret = navi10_get_metrics_table(smu, &metrics);
1158         if (ret)
1159                 return ret;
1160
1161         switch (sensor) {
1162         case AMDGPU_PP_SENSOR_GPU_LOAD:
1163                 *value = metrics.AverageGfxActivity;
1164                 break;
1165         case AMDGPU_PP_SENSOR_MEM_LOAD:
1166                 *value = metrics.AverageUclkActivity;
1167                 break;
1168         default:
1169                 pr_err("Invalid sensor for retrieving clock activity\n");
1170                 return -EINVAL;
1171         }
1172
1173         return 0;
1174 }
1175
1176 static bool navi10_is_dpm_running(struct smu_context *smu)
1177 {
1178         int ret = 0;
1179         uint32_t feature_mask[2];
1180         unsigned long feature_enabled;
1181         ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
1182         feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
1183                            ((uint64_t)feature_mask[1] << 32));
1184         return !!(feature_enabled & SMC_DPM_FEATURE);
1185 }
1186
1187 static int navi10_get_fan_speed_rpm(struct smu_context *smu,
1188                                     uint32_t *speed)
1189 {
1190         SmuMetrics_t metrics;
1191         int ret = 0;
1192
1193         if (!speed)
1194                 return -EINVAL;
1195
1196         ret = navi10_get_metrics_table(smu, &metrics);
1197         if (ret)
1198                 return ret;
1199
1200         *speed = metrics.CurrFanSpeed;
1201
1202         return ret;
1203 }
1204
1205 static int navi10_get_fan_speed_percent(struct smu_context *smu,
1206                                         uint32_t *speed)
1207 {
1208         int ret = 0;
1209         uint32_t percent = 0;
1210         uint32_t current_rpm;
1211         PPTable_t *pptable = smu->smu_table.driver_pptable;
1212
1213         ret = navi10_get_fan_speed_rpm(smu, &current_rpm);
1214         if (ret)
1215                 return ret;
1216
1217         percent = current_rpm * 100 / pptable->FanMaximumRpm;
1218         *speed = percent > 100 ? 100 : percent;
1219
1220         return ret;
1221 }
1222
1223 static int navi10_get_power_profile_mode(struct smu_context *smu, char *buf)
1224 {
1225         DpmActivityMonitorCoeffInt_t activity_monitor;
1226         uint32_t i, size = 0;
1227         int16_t workload_type = 0;
1228         static const char *profile_name[] = {
1229                                         "BOOTUP_DEFAULT",
1230                                         "3D_FULL_SCREEN",
1231                                         "POWER_SAVING",
1232                                         "VIDEO",
1233                                         "VR",
1234                                         "COMPUTE",
1235                                         "CUSTOM"};
1236         static const char *title[] = {
1237                         "PROFILE_INDEX(NAME)",
1238                         "CLOCK_TYPE(NAME)",
1239                         "FPS",
1240                         "MinFreqType",
1241                         "MinActiveFreqType",
1242                         "MinActiveFreq",
1243                         "BoosterFreqType",
1244                         "BoosterFreq",
1245                         "PD_Data_limit_c",
1246                         "PD_Data_error_coeff",
1247                         "PD_Data_error_rate_coeff"};
1248         int result = 0;
1249
1250         if (!buf)
1251                 return -EINVAL;
1252
1253         size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
1254                         title[0], title[1], title[2], title[3], title[4], title[5],
1255                         title[6], title[7], title[8], title[9], title[10]);
1256
1257         for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1258                 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1259                 workload_type = smu_workload_get_type(smu, i);
1260                 if (workload_type < 0)
1261                         return -EINVAL;
1262
1263                 result = smu_update_table(smu,
1264                                           SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
1265                                           (void *)(&activity_monitor), false);
1266                 if (result) {
1267                         pr_err("[%s] Failed to get activity monitor!", __func__);
1268                         return result;
1269                 }
1270
1271                 size += sprintf(buf + size, "%2d %14s%s:\n",
1272                         i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1273
1274                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1275                         " ",
1276                         0,
1277                         "GFXCLK",
1278                         activity_monitor.Gfx_FPS,
1279                         activity_monitor.Gfx_MinFreqStep,
1280                         activity_monitor.Gfx_MinActiveFreqType,
1281                         activity_monitor.Gfx_MinActiveFreq,
1282                         activity_monitor.Gfx_BoosterFreqType,
1283                         activity_monitor.Gfx_BoosterFreq,
1284                         activity_monitor.Gfx_PD_Data_limit_c,
1285                         activity_monitor.Gfx_PD_Data_error_coeff,
1286                         activity_monitor.Gfx_PD_Data_error_rate_coeff);
1287
1288                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1289                         " ",
1290                         1,
1291                         "SOCCLK",
1292                         activity_monitor.Soc_FPS,
1293                         activity_monitor.Soc_MinFreqStep,
1294                         activity_monitor.Soc_MinActiveFreqType,
1295                         activity_monitor.Soc_MinActiveFreq,
1296                         activity_monitor.Soc_BoosterFreqType,
1297                         activity_monitor.Soc_BoosterFreq,
1298                         activity_monitor.Soc_PD_Data_limit_c,
1299                         activity_monitor.Soc_PD_Data_error_coeff,
1300                         activity_monitor.Soc_PD_Data_error_rate_coeff);
1301
1302                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1303                         " ",
1304                         2,
1305                         "MEMLK",
1306                         activity_monitor.Mem_FPS,
1307                         activity_monitor.Mem_MinFreqStep,
1308                         activity_monitor.Mem_MinActiveFreqType,
1309                         activity_monitor.Mem_MinActiveFreq,
1310                         activity_monitor.Mem_BoosterFreqType,
1311                         activity_monitor.Mem_BoosterFreq,
1312                         activity_monitor.Mem_PD_Data_limit_c,
1313                         activity_monitor.Mem_PD_Data_error_coeff,
1314                         activity_monitor.Mem_PD_Data_error_rate_coeff);
1315         }
1316
1317         return size;
1318 }
1319
1320 static int navi10_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
1321 {
1322         DpmActivityMonitorCoeffInt_t activity_monitor;
1323         int workload_type, ret = 0;
1324
1325         smu->power_profile_mode = input[size];
1326
1327         if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1328                 pr_err("Invalid power profile mode %d\n", smu->power_profile_mode);
1329                 return -EINVAL;
1330         }
1331
1332         if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1333                 if (size < 0)
1334                         return -EINVAL;
1335
1336                 ret = smu_update_table(smu,
1337                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1338                                        (void *)(&activity_monitor), false);
1339                 if (ret) {
1340                         pr_err("[%s] Failed to get activity monitor!", __func__);
1341                         return ret;
1342                 }
1343
1344                 switch (input[0]) {
1345                 case 0: /* Gfxclk */
1346                         activity_monitor.Gfx_FPS = input[1];
1347                         activity_monitor.Gfx_MinFreqStep = input[2];
1348                         activity_monitor.Gfx_MinActiveFreqType = input[3];
1349                         activity_monitor.Gfx_MinActiveFreq = input[4];
1350                         activity_monitor.Gfx_BoosterFreqType = input[5];
1351                         activity_monitor.Gfx_BoosterFreq = input[6];
1352                         activity_monitor.Gfx_PD_Data_limit_c = input[7];
1353                         activity_monitor.Gfx_PD_Data_error_coeff = input[8];
1354                         activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9];
1355                         break;
1356                 case 1: /* Socclk */
1357                         activity_monitor.Soc_FPS = input[1];
1358                         activity_monitor.Soc_MinFreqStep = input[2];
1359                         activity_monitor.Soc_MinActiveFreqType = input[3];
1360                         activity_monitor.Soc_MinActiveFreq = input[4];
1361                         activity_monitor.Soc_BoosterFreqType = input[5];
1362                         activity_monitor.Soc_BoosterFreq = input[6];
1363                         activity_monitor.Soc_PD_Data_limit_c = input[7];
1364                         activity_monitor.Soc_PD_Data_error_coeff = input[8];
1365                         activity_monitor.Soc_PD_Data_error_rate_coeff = input[9];
1366                         break;
1367                 case 2: /* Memlk */
1368                         activity_monitor.Mem_FPS = input[1];
1369                         activity_monitor.Mem_MinFreqStep = input[2];
1370                         activity_monitor.Mem_MinActiveFreqType = input[3];
1371                         activity_monitor.Mem_MinActiveFreq = input[4];
1372                         activity_monitor.Mem_BoosterFreqType = input[5];
1373                         activity_monitor.Mem_BoosterFreq = input[6];
1374                         activity_monitor.Mem_PD_Data_limit_c = input[7];
1375                         activity_monitor.Mem_PD_Data_error_coeff = input[8];
1376                         activity_monitor.Mem_PD_Data_error_rate_coeff = input[9];
1377                         break;
1378                 }
1379
1380                 ret = smu_update_table(smu,
1381                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1382                                        (void *)(&activity_monitor), true);
1383                 if (ret) {
1384                         pr_err("[%s] Failed to set activity monitor!", __func__);
1385                         return ret;
1386                 }
1387         }
1388
1389         /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1390         workload_type = smu_workload_get_type(smu, smu->power_profile_mode);
1391         if (workload_type < 0)
1392                 return -EINVAL;
1393         smu_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
1394                                     1 << workload_type);
1395
1396         return ret;
1397 }
1398
1399 static int navi10_get_profiling_clk_mask(struct smu_context *smu,
1400                                          enum amd_dpm_forced_level level,
1401                                          uint32_t *sclk_mask,
1402                                          uint32_t *mclk_mask,
1403                                          uint32_t *soc_mask)
1404 {
1405         int ret = 0;
1406         uint32_t level_count = 0;
1407
1408         if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
1409                 if (sclk_mask)
1410                         *sclk_mask = 0;
1411         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
1412                 if (mclk_mask)
1413                         *mclk_mask = 0;
1414         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
1415                 if(sclk_mask) {
1416                         ret = smu_get_dpm_level_count(smu, SMU_SCLK, &level_count);
1417                         if (ret)
1418                                 return ret;
1419                         *sclk_mask = level_count - 1;
1420                 }
1421
1422                 if(mclk_mask) {
1423                         ret = smu_get_dpm_level_count(smu, SMU_MCLK, &level_count);
1424                         if (ret)
1425                                 return ret;
1426                         *mclk_mask = level_count - 1;
1427                 }
1428
1429                 if(soc_mask) {
1430                         ret = smu_get_dpm_level_count(smu, SMU_SOCCLK, &level_count);
1431                         if (ret)
1432                                 return ret;
1433                         *soc_mask = level_count - 1;
1434                 }
1435         }
1436
1437         return ret;
1438 }
1439
1440 static int navi10_notify_smc_display_config(struct smu_context *smu)
1441 {
1442         struct smu_clocks min_clocks = {0};
1443         struct pp_display_clock_request clock_req;
1444         int ret = 0;
1445
1446         min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
1447         min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
1448         min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
1449
1450         if (smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1451                 clock_req.clock_type = amd_pp_dcef_clock;
1452                 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
1453
1454                 ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req);
1455                 if (!ret) {
1456                         if (smu_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
1457                                 ret = smu_send_smc_msg_with_param(smu,
1458                                                                   SMU_MSG_SetMinDeepSleepDcefclk,
1459                                                                   min_clocks.dcef_clock_in_sr/100);
1460                                 if (ret) {
1461                                         pr_err("Attempt to set divider for DCEFCLK Failed!");
1462                                         return ret;
1463                                 }
1464                         }
1465                 } else {
1466                         pr_info("Attempt to set Hard Min for DCEFCLK Failed!");
1467                 }
1468         }
1469
1470         if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1471                 ret = smu_set_hard_freq_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);
1472                 if (ret) {
1473                         pr_err("[%s] Set hard min uclk failed!", __func__);
1474                         return ret;
1475                 }
1476         }
1477
1478         return 0;
1479 }
1480
1481 static int navi10_set_watermarks_table(struct smu_context *smu,
1482                                        void *watermarks, struct
1483                                        dm_pp_wm_sets_with_clock_ranges_soc15
1484                                        *clock_ranges)
1485 {
1486         int i;
1487         int ret = 0;
1488         Watermarks_t *table = watermarks;
1489
1490         if (!table || !clock_ranges)
1491                 return -EINVAL;
1492
1493         if (clock_ranges->num_wm_dmif_sets > 4 ||
1494             clock_ranges->num_wm_mcif_sets > 4)
1495                 return -EINVAL;
1496
1497         for (i = 0; i < clock_ranges->num_wm_dmif_sets; i++) {
1498                 table->WatermarkRow[1][i].MinClock =
1499                         cpu_to_le16((uint16_t)
1500                         (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz /
1501                         1000));
1502                 table->WatermarkRow[1][i].MaxClock =
1503                         cpu_to_le16((uint16_t)
1504                         (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz /
1505                         1000));
1506                 table->WatermarkRow[1][i].MinUclk =
1507                         cpu_to_le16((uint16_t)
1508                         (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz /
1509                         1000));
1510                 table->WatermarkRow[1][i].MaxUclk =
1511                         cpu_to_le16((uint16_t)
1512                         (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz /
1513                         1000));
1514                 table->WatermarkRow[1][i].WmSetting = (uint8_t)
1515                                 clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id;
1516         }
1517
1518         for (i = 0; i < clock_ranges->num_wm_mcif_sets; i++) {
1519                 table->WatermarkRow[0][i].MinClock =
1520                         cpu_to_le16((uint16_t)
1521                         (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz /
1522                         1000));
1523                 table->WatermarkRow[0][i].MaxClock =
1524                         cpu_to_le16((uint16_t)
1525                         (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz /
1526                         1000));
1527                 table->WatermarkRow[0][i].MinUclk =
1528                         cpu_to_le16((uint16_t)
1529                         (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz /
1530                         1000));
1531                 table->WatermarkRow[0][i].MaxUclk =
1532                         cpu_to_le16((uint16_t)
1533                         (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz /
1534                         1000));
1535                 table->WatermarkRow[0][i].WmSetting = (uint8_t)
1536                                 clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id;
1537         }
1538
1539         smu->watermarks_bitmap |= WATERMARKS_EXIST;
1540
1541         /* pass data to smu controller */
1542         if (!(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
1543                 ret = smu_write_watermarks_table(smu);
1544                 if (ret) {
1545                         pr_err("Failed to update WMTABLE!");
1546                         return ret;
1547                 }
1548                 smu->watermarks_bitmap |= WATERMARKS_LOADED;
1549         }
1550
1551         return 0;
1552 }
1553
1554 static int navi10_thermal_get_temperature(struct smu_context *smu,
1555                                              enum amd_pp_sensors sensor,
1556                                              uint32_t *value)
1557 {
1558         SmuMetrics_t metrics;
1559         int ret = 0;
1560
1561         if (!value)
1562                 return -EINVAL;
1563
1564         ret = navi10_get_metrics_table(smu, &metrics);
1565         if (ret)
1566                 return ret;
1567
1568         switch (sensor) {
1569         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1570                 *value = metrics.TemperatureHotspot *
1571                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1572                 break;
1573         case AMDGPU_PP_SENSOR_EDGE_TEMP:
1574                 *value = metrics.TemperatureEdge *
1575                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1576                 break;
1577         case AMDGPU_PP_SENSOR_MEM_TEMP:
1578                 *value = metrics.TemperatureMem *
1579                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1580                 break;
1581         default:
1582                 pr_err("Invalid sensor for retrieving temp\n");
1583                 return -EINVAL;
1584         }
1585
1586         return 0;
1587 }
1588
1589 static int navi10_read_sensor(struct smu_context *smu,
1590                                  enum amd_pp_sensors sensor,
1591                                  void *data, uint32_t *size)
1592 {
1593         int ret = 0;
1594         struct smu_table_context *table_context = &smu->smu_table;
1595         PPTable_t *pptable = table_context->driver_pptable;
1596
1597         if(!data || !size)
1598                 return -EINVAL;
1599
1600         mutex_lock(&smu->sensor_lock);
1601         switch (sensor) {
1602         case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
1603                 *(uint32_t *)data = pptable->FanMaximumRpm;
1604                 *size = 4;
1605                 break;
1606         case AMDGPU_PP_SENSOR_MEM_LOAD:
1607         case AMDGPU_PP_SENSOR_GPU_LOAD:
1608                 ret = navi10_get_current_activity_percent(smu, sensor, (uint32_t *)data);
1609                 *size = 4;
1610                 break;
1611         case AMDGPU_PP_SENSOR_GPU_POWER:
1612                 ret = navi10_get_gpu_power(smu, (uint32_t *)data);
1613                 *size = 4;
1614                 break;
1615         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1616         case AMDGPU_PP_SENSOR_EDGE_TEMP:
1617         case AMDGPU_PP_SENSOR_MEM_TEMP:
1618                 ret = navi10_thermal_get_temperature(smu, sensor, (uint32_t *)data);
1619                 *size = 4;
1620                 break;
1621         default:
1622                 ret = smu_v11_0_read_sensor(smu, sensor, data, size);
1623         }
1624         mutex_unlock(&smu->sensor_lock);
1625
1626         return ret;
1627 }
1628
1629 static int navi10_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states)
1630 {
1631         uint32_t num_discrete_levels = 0;
1632         uint16_t *dpm_levels = NULL;
1633         uint16_t i = 0;
1634         struct smu_table_context *table_context = &smu->smu_table;
1635         PPTable_t *driver_ppt = NULL;
1636
1637         if (!clocks_in_khz || !num_states || !table_context->driver_pptable)
1638                 return -EINVAL;
1639
1640         driver_ppt = table_context->driver_pptable;
1641         num_discrete_levels = driver_ppt->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels;
1642         dpm_levels = driver_ppt->FreqTableUclk;
1643
1644         if (num_discrete_levels == 0 || dpm_levels == NULL)
1645                 return -EINVAL;
1646
1647         *num_states = num_discrete_levels;
1648         for (i = 0; i < num_discrete_levels; i++) {
1649                 /* convert to khz */
1650                 *clocks_in_khz = (*dpm_levels) * 1000;
1651                 clocks_in_khz++;
1652                 dpm_levels++;
1653         }
1654
1655         return 0;
1656 }
1657
1658 static int navi10_set_performance_level(struct smu_context *smu,
1659                                         enum amd_dpm_forced_level level);
1660
1661 static int navi10_set_standard_performance_level(struct smu_context *smu)
1662 {
1663         struct amdgpu_device *adev = smu->adev;
1664         int ret = 0;
1665         uint32_t sclk_freq = 0, uclk_freq = 0;
1666
1667         switch (adev->asic_type) {
1668         case CHIP_NAVI10:
1669                 sclk_freq = NAVI10_UMD_PSTATE_PROFILING_GFXCLK;
1670                 uclk_freq = NAVI10_UMD_PSTATE_PROFILING_MEMCLK;
1671                 break;
1672         case CHIP_NAVI14:
1673                 sclk_freq = NAVI14_UMD_PSTATE_PROFILING_GFXCLK;
1674                 uclk_freq = NAVI14_UMD_PSTATE_PROFILING_MEMCLK;
1675                 break;
1676         default:
1677                 /* by default, this is same as auto performance level */
1678                 return navi10_set_performance_level(smu, AMD_DPM_FORCED_LEVEL_AUTO);
1679         }
1680
1681         ret = smu_set_soft_freq_range(smu, SMU_SCLK, sclk_freq, sclk_freq);
1682         if (ret)
1683                 return ret;
1684         ret = smu_set_soft_freq_range(smu, SMU_UCLK, uclk_freq, uclk_freq);
1685         if (ret)
1686                 return ret;
1687
1688         return ret;
1689 }
1690
1691 static int navi10_set_peak_performance_level(struct smu_context *smu)
1692 {
1693         struct amdgpu_device *adev = smu->adev;
1694         int ret = 0;
1695         uint32_t sclk_freq = 0, uclk_freq = 0;
1696
1697         switch (adev->asic_type) {
1698         case CHIP_NAVI10:
1699                 switch (adev->pdev->revision) {
1700                 case 0xf0: /* XTX */
1701                 case 0xc0:
1702                         sclk_freq = NAVI10_PEAK_SCLK_XTX;
1703                         break;
1704                 case 0xf1: /* XT */
1705                 case 0xc1:
1706                         sclk_freq = NAVI10_PEAK_SCLK_XT;
1707                         break;
1708                 default: /* XL */
1709                         sclk_freq = NAVI10_PEAK_SCLK_XL;
1710                         break;
1711                 }
1712                 break;
1713         case CHIP_NAVI14:
1714                 switch (adev->pdev->revision) {
1715                 case 0xc7: /* XT */
1716                 case 0xf4:
1717                         sclk_freq = NAVI14_UMD_PSTATE_PEAK_XT_GFXCLK;
1718                         break;
1719                 case 0xc1: /* XTM */
1720                 case 0xf2:
1721                         sclk_freq = NAVI14_UMD_PSTATE_PEAK_XTM_GFXCLK;
1722                         break;
1723                 case 0xc3: /* XLM */
1724                 case 0xf3:
1725                         sclk_freq = NAVI14_UMD_PSTATE_PEAK_XLM_GFXCLK;
1726                         break;
1727                 case 0xc5: /* XTX */
1728                 case 0xf6:
1729                         sclk_freq = NAVI14_UMD_PSTATE_PEAK_XLM_GFXCLK;
1730                         break;
1731                 default: /* XL */
1732                         sclk_freq = NAVI14_UMD_PSTATE_PEAK_XL_GFXCLK;
1733                         break;
1734                 }
1735                 break;
1736         case CHIP_NAVI12:
1737                 sclk_freq = NAVI12_UMD_PSTATE_PEAK_GFXCLK;
1738                 break;
1739         default:
1740                 ret = smu_get_dpm_level_range(smu, SMU_SCLK, NULL, &sclk_freq);
1741                 if (ret)
1742                         return ret;
1743         }
1744
1745         ret = smu_get_dpm_level_range(smu, SMU_UCLK, NULL, &uclk_freq);
1746         if (ret)
1747                 return ret;
1748
1749         ret = smu_set_soft_freq_range(smu, SMU_SCLK, sclk_freq, sclk_freq);
1750         if (ret)
1751                 return ret;
1752         ret = smu_set_soft_freq_range(smu, SMU_UCLK, uclk_freq, uclk_freq);
1753         if (ret)
1754                 return ret;
1755
1756         return ret;
1757 }
1758
1759 static int navi10_set_performance_level(struct smu_context *smu,
1760                                         enum amd_dpm_forced_level level)
1761 {
1762         int ret = 0;
1763         uint32_t sclk_mask, mclk_mask, soc_mask;
1764
1765         switch (level) {
1766         case AMD_DPM_FORCED_LEVEL_HIGH:
1767                 ret = smu_force_dpm_limit_value(smu, true);
1768                 break;
1769         case AMD_DPM_FORCED_LEVEL_LOW:
1770                 ret = smu_force_dpm_limit_value(smu, false);
1771                 break;
1772         case AMD_DPM_FORCED_LEVEL_AUTO:
1773                 ret = smu_unforce_dpm_levels(smu);
1774                 break;
1775         case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1776                 ret = navi10_set_standard_performance_level(smu);
1777                 break;
1778         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1779         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1780                 ret = smu_get_profiling_clk_mask(smu, level,
1781                                                  &sclk_mask,
1782                                                  &mclk_mask,
1783                                                  &soc_mask);
1784                 if (ret)
1785                         return ret;
1786                 smu_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask, false);
1787                 smu_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask, false);
1788                 smu_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask, false);
1789                 break;
1790         case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1791                 ret = navi10_set_peak_performance_level(smu);
1792                 break;
1793         case AMD_DPM_FORCED_LEVEL_MANUAL:
1794         case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1795         default:
1796                 break;
1797         }
1798         return ret;
1799 }
1800
1801 static int navi10_get_thermal_temperature_range(struct smu_context *smu,
1802                                                 struct smu_temperature_range *range)
1803 {
1804         struct smu_table_context *table_context = &smu->smu_table;
1805         struct smu_11_0_powerplay_table *powerplay_table = table_context->power_play_table;
1806
1807         if (!range || !powerplay_table)
1808                 return -EINVAL;
1809
1810         range->max = powerplay_table->software_shutdown_temp *
1811                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1812
1813         return 0;
1814 }
1815
1816 static int navi10_display_disable_memory_clock_switch(struct smu_context *smu,
1817                                                 bool disable_memory_clock_switch)
1818 {
1819         int ret = 0;
1820         struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks =
1821                 (struct smu_11_0_max_sustainable_clocks *)
1822                         smu->smu_table.max_sustainable_clocks;
1823         uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal;
1824         uint32_t max_memory_clock = max_sustainable_clocks->uclock;
1825
1826         if(smu->disable_uclk_switch == disable_memory_clock_switch)
1827                 return 0;
1828
1829         if(disable_memory_clock_switch)
1830                 ret = smu_set_hard_freq_range(smu, SMU_UCLK, max_memory_clock, 0);
1831         else
1832                 ret = smu_set_hard_freq_range(smu, SMU_UCLK, min_memory_clock, 0);
1833
1834         if(!ret)
1835                 smu->disable_uclk_switch = disable_memory_clock_switch;
1836
1837         return ret;
1838 }
1839
1840 static uint32_t navi10_get_pptable_power_limit(struct smu_context *smu)
1841 {
1842         PPTable_t *pptable = smu->smu_table.driver_pptable;
1843         return pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
1844 }
1845
1846 static int navi10_get_power_limit(struct smu_context *smu,
1847                                      uint32_t *limit,
1848                                      bool cap)
1849 {
1850         PPTable_t *pptable = smu->smu_table.driver_pptable;
1851         uint32_t asic_default_power_limit = 0;
1852         int ret = 0;
1853         int power_src;
1854
1855         if (!smu->power_limit) {
1856                 if (smu_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
1857                         power_src = smu_power_get_index(smu, SMU_POWER_SOURCE_AC);
1858                         if (power_src < 0)
1859                                 return -EINVAL;
1860
1861                         ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetPptLimit,
1862                                 power_src << 16);
1863                         if (ret) {
1864                                 pr_err("[%s] get PPT limit failed!", __func__);
1865                                 return ret;
1866                         }
1867                         smu_read_smc_arg(smu, &asic_default_power_limit);
1868                 } else {
1869                         /* the last hope to figure out the ppt limit */
1870                         if (!pptable) {
1871                                 pr_err("Cannot get PPT limit due to pptable missing!");
1872                                 return -EINVAL;
1873                         }
1874                         asic_default_power_limit =
1875                                 pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
1876                 }
1877
1878                 smu->power_limit = asic_default_power_limit;
1879         }
1880
1881         if (cap)
1882                 *limit = smu_v11_0_get_max_power_limit(smu);
1883         else
1884                 *limit = smu->power_limit;
1885
1886         return 0;
1887 }
1888
1889 static int navi10_update_pcie_parameters(struct smu_context *smu,
1890                                      uint32_t pcie_gen_cap,
1891                                      uint32_t pcie_width_cap)
1892 {
1893         PPTable_t *pptable = smu->smu_table.driver_pptable;
1894         int ret, i;
1895         uint32_t smu_pcie_arg;
1896
1897         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1898         struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1899
1900         for (i = 0; i < NUM_LINK_LEVELS; i++) {
1901                 smu_pcie_arg = (i << 16) |
1902                         ((pptable->PcieGenSpeed[i] <= pcie_gen_cap) ? (pptable->PcieGenSpeed[i] << 8) :
1903                                 (pcie_gen_cap << 8)) | ((pptable->PcieLaneCount[i] <= pcie_width_cap) ?
1904                                         pptable->PcieLaneCount[i] : pcie_width_cap);
1905                 ret = smu_send_smc_msg_with_param(smu,
1906                                           SMU_MSG_OverridePcieParameters,
1907                                           smu_pcie_arg);
1908
1909                 if (ret)
1910                         return ret;
1911
1912                 if (pptable->PcieGenSpeed[i] > pcie_gen_cap)
1913                         dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pcie_gen_cap;
1914                 if (pptable->PcieLaneCount[i] > pcie_width_cap)
1915                         dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pcie_width_cap;
1916         }
1917
1918         return 0;
1919 }
1920
1921 static inline void navi10_dump_od_table(OverDriveTable_t *od_table) {
1922         pr_debug("OD: Gfxclk: (%d, %d)\n", od_table->GfxclkFmin, od_table->GfxclkFmax);
1923         pr_debug("OD: Gfx1: (%d, %d)\n", od_table->GfxclkFreq1, od_table->GfxclkVolt1);
1924         pr_debug("OD: Gfx2: (%d, %d)\n", od_table->GfxclkFreq2, od_table->GfxclkVolt2);
1925         pr_debug("OD: Gfx3: (%d, %d)\n", od_table->GfxclkFreq3, od_table->GfxclkVolt3);
1926         pr_debug("OD: UclkFmax: %d\n", od_table->UclkFmax);
1927         pr_debug("OD: OverDrivePct: %d\n", od_table->OverDrivePct);
1928 }
1929
1930 static int navi10_od_setting_check_range(struct smu_11_0_overdrive_table *od_table, enum SMU_11_0_ODSETTING_ID setting, uint32_t value)
1931 {
1932         if (value < od_table->min[setting]) {
1933                 pr_warn("OD setting (%d, %d) is less than the minimum allowed (%d)\n", setting, value, od_table->min[setting]);
1934                 return -EINVAL;
1935         }
1936         if (value > od_table->max[setting]) {
1937                 pr_warn("OD setting (%d, %d) is greater than the maximum allowed (%d)\n", setting, value, od_table->max[setting]);
1938                 return -EINVAL;
1939         }
1940         return 0;
1941 }
1942
1943 static int navi10_overdrive_get_gfx_clk_base_voltage(struct smu_context *smu,
1944                                                      uint16_t *voltage,
1945                                                      uint32_t freq)
1946 {
1947         uint32_t param = (freq & 0xFFFF) | (PPCLK_GFXCLK << 16);
1948         uint32_t value = 0;
1949         int ret;
1950
1951         ret = smu_send_smc_msg_with_param(smu,
1952                                           SMU_MSG_GetVoltageByDpm,
1953                                           param);
1954         if (ret) {
1955                 pr_err("[GetBaseVoltage] failed to get GFXCLK AVFS voltage from SMU!");
1956                 return ret;
1957         }
1958
1959         smu_read_smc_arg(smu, &value);
1960         *voltage = (uint16_t)value;
1961
1962         return 0;
1963 }
1964
1965 static int navi10_setup_od_limits(struct smu_context *smu) {
1966         struct smu_11_0_overdrive_table *overdrive_table = NULL;
1967         struct smu_11_0_powerplay_table *powerplay_table = NULL;
1968
1969         if (!smu->smu_table.power_play_table) {
1970                 pr_err("powerplay table uninitialized!\n");
1971                 return -ENOENT;
1972         }
1973         powerplay_table = (struct smu_11_0_powerplay_table *)smu->smu_table.power_play_table;
1974         overdrive_table = &powerplay_table->overdrive_table;
1975         if (!smu->od_settings) {
1976                 smu->od_settings = kmemdup(overdrive_table, sizeof(struct smu_11_0_overdrive_table), GFP_KERNEL);
1977         } else {
1978                 memcpy(smu->od_settings, overdrive_table, sizeof(struct smu_11_0_overdrive_table));
1979         }
1980         return 0;
1981 }
1982
1983 static int navi10_set_default_od_settings(struct smu_context *smu, bool initialize) {
1984         OverDriveTable_t *od_table, *boot_od_table;
1985         int ret = 0;
1986
1987         ret = smu_v11_0_set_default_od_settings(smu, initialize, sizeof(OverDriveTable_t));
1988         if (ret)
1989                 return ret;
1990
1991         od_table = (OverDriveTable_t *)smu->smu_table.overdrive_table;
1992         boot_od_table = (OverDriveTable_t *)smu->smu_table.boot_overdrive_table;
1993         if (initialize) {
1994                 ret = navi10_setup_od_limits(smu);
1995                 if (ret) {
1996                         pr_err("Failed to retrieve board OD limits\n");
1997                         return ret;
1998                 }
1999                 if (od_table) {
2000                         if (!od_table->GfxclkVolt1) {
2001                                 ret = navi10_overdrive_get_gfx_clk_base_voltage(smu,
2002                                                                                 &od_table->GfxclkVolt1,
2003                                                                                 od_table->GfxclkFreq1);
2004                                 if (ret)
2005                                         od_table->GfxclkVolt1 = 0;
2006                                 if (boot_od_table)
2007                                         boot_od_table->GfxclkVolt1 = od_table->GfxclkVolt1;
2008                         }
2009
2010                         if (!od_table->GfxclkVolt2) {
2011                                 ret = navi10_overdrive_get_gfx_clk_base_voltage(smu,
2012                                                                                 &od_table->GfxclkVolt2,
2013                                                                                 od_table->GfxclkFreq2);
2014                                 if (ret)
2015                                         od_table->GfxclkVolt2 = 0;
2016                                 if (boot_od_table)
2017                                         boot_od_table->GfxclkVolt2 = od_table->GfxclkVolt2;
2018                         }
2019
2020                         if (!od_table->GfxclkVolt3) {
2021                                 ret = navi10_overdrive_get_gfx_clk_base_voltage(smu,
2022                                                                                 &od_table->GfxclkVolt3,
2023                                                                                 od_table->GfxclkFreq3);
2024                                 if (ret)
2025                                         od_table->GfxclkVolt3 = 0;
2026                                 if (boot_od_table)
2027                                         boot_od_table->GfxclkVolt3 = od_table->GfxclkVolt3;
2028                         }
2029                 }
2030         }
2031
2032         if (od_table) {
2033                 navi10_dump_od_table(od_table);
2034         }
2035
2036         return ret;
2037 }
2038
2039 static int navi10_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type, long input[], uint32_t size) {
2040         int i;
2041         int ret = 0;
2042         struct smu_table_context *table_context = &smu->smu_table;
2043         OverDriveTable_t *od_table;
2044         struct smu_11_0_overdrive_table *od_settings;
2045         enum SMU_11_0_ODSETTING_ID freq_setting, voltage_setting;
2046         uint16_t *freq_ptr, *voltage_ptr;
2047         od_table = (OverDriveTable_t *)table_context->overdrive_table;
2048
2049         if (!smu->od_enabled) {
2050                 pr_warn("OverDrive is not enabled!\n");
2051                 return -EINVAL;
2052         }
2053
2054         if (!smu->od_settings) {
2055                 pr_err("OD board limits are not set!\n");
2056                 return -ENOENT;
2057         }
2058
2059         od_settings = smu->od_settings;
2060
2061         switch (type) {
2062         case PP_OD_EDIT_SCLK_VDDC_TABLE:
2063                 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS)) {
2064                         pr_warn("GFXCLK_LIMITS not supported!\n");
2065                         return -ENOTSUPP;
2066                 }
2067                 if (!table_context->overdrive_table) {
2068                         pr_err("Overdrive is not initialized\n");
2069                         return -EINVAL;
2070                 }
2071                 for (i = 0; i < size; i += 2) {
2072                         if (i + 2 > size) {
2073                                 pr_info("invalid number of input parameters %d\n", size);
2074                                 return -EINVAL;
2075                         }
2076                         switch (input[i]) {
2077                         case 0:
2078                                 freq_setting = SMU_11_0_ODSETTING_GFXCLKFMIN;
2079                                 freq_ptr = &od_table->GfxclkFmin;
2080                                 if (input[i + 1] > od_table->GfxclkFmax) {
2081                                         pr_info("GfxclkFmin (%ld) must be <= GfxclkFmax (%u)!\n",
2082                                                 input[i + 1],
2083                                                 od_table->GfxclkFmin);
2084                                         return -EINVAL;
2085                                 }
2086                                 break;
2087                         case 1:
2088                                 freq_setting = SMU_11_0_ODSETTING_GFXCLKFMAX;
2089                                 freq_ptr = &od_table->GfxclkFmax;
2090                                 if (input[i + 1] < od_table->GfxclkFmin) {
2091                                         pr_info("GfxclkFmax (%ld) must be >= GfxclkFmin (%u)!\n",
2092                                                 input[i + 1],
2093                                                 od_table->GfxclkFmax);
2094                                         return -EINVAL;
2095                                 }
2096                                 break;
2097                         default:
2098                                 pr_info("Invalid SCLK_VDDC_TABLE index: %ld\n", input[i]);
2099                                 pr_info("Supported indices: [0:min,1:max]\n");
2100                                 return -EINVAL;
2101                         }
2102                         ret = navi10_od_setting_check_range(od_settings, freq_setting, input[i + 1]);
2103                         if (ret)
2104                                 return ret;
2105                         *freq_ptr = input[i + 1];
2106                 }
2107                 break;
2108         case PP_OD_EDIT_MCLK_VDDC_TABLE:
2109                 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX)) {
2110                         pr_warn("UCLK_MAX not supported!\n");
2111                         return -ENOTSUPP;
2112                 }
2113                 if (size < 2) {
2114                         pr_info("invalid number of parameters: %d\n", size);
2115                         return -EINVAL;
2116                 }
2117                 if (input[0] != 1) {
2118                         pr_info("Invalid MCLK_VDDC_TABLE index: %ld\n", input[0]);
2119                         pr_info("Supported indices: [1:max]\n");
2120                         return -EINVAL;
2121                 }
2122                 ret = navi10_od_setting_check_range(od_settings, SMU_11_0_ODSETTING_UCLKFMAX, input[1]);
2123                 if (ret)
2124                         return ret;
2125                 od_table->UclkFmax = input[1];
2126                 break;
2127         case PP_OD_RESTORE_DEFAULT_TABLE:
2128                 if (!(table_context->overdrive_table && table_context->boot_overdrive_table)) {
2129                         pr_err("Overdrive table was not initialized!\n");
2130                         return -EINVAL;
2131                 }
2132                 memcpy(table_context->overdrive_table, table_context->boot_overdrive_table, sizeof(OverDriveTable_t));
2133                 break;
2134         case PP_OD_COMMIT_DPM_TABLE:
2135                 navi10_dump_od_table(od_table);
2136                 ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)od_table, true);
2137                 if (ret) {
2138                         pr_err("Failed to import overdrive table!\n");
2139                         return ret;
2140                 }
2141                 // no lock needed because smu_od_edit_dpm_table has it
2142                 ret = smu_handle_task(smu, smu->smu_dpm.dpm_level,
2143                         AMD_PP_TASK_READJUST_POWER_STATE,
2144                         false);
2145                 if (ret) {
2146                         return ret;
2147                 }
2148                 break;
2149         case PP_OD_EDIT_VDDC_CURVE:
2150                 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE)) {
2151                         pr_warn("GFXCLK_CURVE not supported!\n");
2152                         return -ENOTSUPP;
2153                 }
2154                 if (size < 3) {
2155                         pr_info("invalid number of parameters: %d\n", size);
2156                         return -EINVAL;
2157                 }
2158                 if (!od_table) {
2159                         pr_info("Overdrive is not initialized\n");
2160                         return -EINVAL;
2161                 }
2162
2163                 switch (input[0]) {
2164                 case 0:
2165                         freq_setting = SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P1;
2166                         voltage_setting = SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P1;
2167                         freq_ptr = &od_table->GfxclkFreq1;
2168                         voltage_ptr = &od_table->GfxclkVolt1;
2169                         break;
2170                 case 1:
2171                         freq_setting = SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P2;
2172                         voltage_setting = SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P2;
2173                         freq_ptr = &od_table->GfxclkFreq2;
2174                         voltage_ptr = &od_table->GfxclkVolt2;
2175                         break;
2176                 case 2:
2177                         freq_setting = SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P3;
2178                         voltage_setting = SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P3;
2179                         freq_ptr = &od_table->GfxclkFreq3;
2180                         voltage_ptr = &od_table->GfxclkVolt3;
2181                         break;
2182                 default:
2183                         pr_info("Invalid VDDC_CURVE index: %ld\n", input[0]);
2184                         pr_info("Supported indices: [0, 1, 2]\n");
2185                         return -EINVAL;
2186                 }
2187                 ret = navi10_od_setting_check_range(od_settings, freq_setting, input[1]);
2188                 if (ret)
2189                         return ret;
2190                 // Allow setting zero to disable the OverDrive VDDC curve
2191                 if (input[2] != 0) {
2192                         ret = navi10_od_setting_check_range(od_settings, voltage_setting, input[2]);
2193                         if (ret)
2194                                 return ret;
2195                         *freq_ptr = input[1];
2196                         *voltage_ptr = ((uint16_t)input[2]) * NAVI10_VOLTAGE_SCALE;
2197                         pr_debug("OD: set curve %ld: (%d, %d)\n", input[0], *freq_ptr, *voltage_ptr);
2198                 } else {
2199                         // If setting 0, disable all voltage curve settings
2200                         od_table->GfxclkVolt1 = 0;
2201                         od_table->GfxclkVolt2 = 0;
2202                         od_table->GfxclkVolt3 = 0;
2203                 }
2204                 navi10_dump_od_table(od_table);
2205                 break;
2206         default:
2207                 return -ENOSYS;
2208         }
2209         return ret;
2210 }
2211
2212 static int navi10_run_btc(struct smu_context *smu)
2213 {
2214         int ret = 0;
2215
2216         ret = smu_send_smc_msg(smu, SMU_MSG_RunBtc);
2217         if (ret)
2218                 pr_err("RunBtc failed!\n");
2219
2220         return ret;
2221 }
2222
2223 static int navi10_dummy_pstate_control(struct smu_context *smu, bool enable)
2224 {
2225         int result = 0;
2226
2227         if (!enable)
2228                 result = smu_send_smc_msg(smu, SMU_MSG_DAL_DISABLE_DUMMY_PSTATE_CHANGE);
2229         else
2230                 result = smu_send_smc_msg(smu, SMU_MSG_DAL_ENABLE_DUMMY_PSTATE_CHANGE);
2231
2232         return result;
2233 }
2234
2235 static int navi10_disable_umc_cdr_12gbps_workaround(struct smu_context *smu)
2236 {
2237         uint32_t uclk_count, uclk_min, uclk_max;
2238         uint32_t smu_version;
2239         int ret = 0;
2240
2241         ret = smu_get_smc_version(smu, NULL, &smu_version);
2242         if (ret)
2243                 return ret;
2244
2245         /* This workaround is available only for 42.50 or later SMC firmwares */
2246         if (smu_version < 0x2A3200)
2247                 return 0;
2248
2249         ret = smu_get_dpm_level_count(smu, SMU_UCLK, &uclk_count);
2250         if (ret)
2251                 return ret;
2252
2253         ret = smu_get_dpm_freq_by_index(smu, SMU_UCLK, (uint16_t)0, &uclk_min);
2254         if (ret)
2255                 return ret;
2256
2257         ret = smu_get_dpm_freq_by_index(smu, SMU_UCLK, (uint16_t)(uclk_count - 1), &uclk_max);
2258         if (ret)
2259                 return ret;
2260
2261         /* Force UCLK out of the highest DPM */
2262         ret = smu_set_hard_freq_range(smu, SMU_UCLK, 0, uclk_min);
2263         if (ret)
2264                 return ret;
2265
2266         /* Revert the UCLK Hardmax */
2267         ret = smu_set_hard_freq_range(smu, SMU_UCLK, 0, uclk_max);
2268         if (ret)
2269                 return ret;
2270
2271         /*
2272          * In this case, SMU already disabled dummy pstate during enablement
2273          * of UCLK DPM, we have to re-enabled it.
2274          * */
2275         return navi10_dummy_pstate_control(smu, true);
2276 }
2277
2278 static const struct pptable_funcs navi10_ppt_funcs = {
2279         .tables_init = navi10_tables_init,
2280         .alloc_dpm_context = navi10_allocate_dpm_context,
2281         .store_powerplay_table = navi10_store_powerplay_table,
2282         .check_powerplay_table = navi10_check_powerplay_table,
2283         .append_powerplay_table = navi10_append_powerplay_table,
2284         .get_smu_msg_index = navi10_get_smu_msg_index,
2285         .get_smu_clk_index = navi10_get_smu_clk_index,
2286         .get_smu_feature_index = navi10_get_smu_feature_index,
2287         .get_smu_table_index = navi10_get_smu_table_index,
2288         .get_smu_power_index = navi10_get_pwr_src_index,
2289         .get_workload_type = navi10_get_workload_type,
2290         .get_allowed_feature_mask = navi10_get_allowed_feature_mask,
2291         .set_default_dpm_table = navi10_set_default_dpm_table,
2292         .dpm_set_uvd_enable = navi10_dpm_set_uvd_enable,
2293         .dpm_set_jpeg_enable = navi10_dpm_set_jpeg_enable,
2294         .get_current_clk_freq_by_table = navi10_get_current_clk_freq_by_table,
2295         .print_clk_levels = navi10_print_clk_levels,
2296         .force_clk_levels = navi10_force_clk_levels,
2297         .populate_umd_state_clk = navi10_populate_umd_state_clk,
2298         .get_clock_by_type_with_latency = navi10_get_clock_by_type_with_latency,
2299         .pre_display_config_changed = navi10_pre_display_config_changed,
2300         .display_config_changed = navi10_display_config_changed,
2301         .notify_smc_display_config = navi10_notify_smc_display_config,
2302         .force_dpm_limit_value = navi10_force_dpm_limit_value,
2303         .unforce_dpm_levels = navi10_unforce_dpm_levels,
2304         .is_dpm_running = navi10_is_dpm_running,
2305         .get_fan_speed_percent = navi10_get_fan_speed_percent,
2306         .get_fan_speed_rpm = navi10_get_fan_speed_rpm,
2307         .get_power_profile_mode = navi10_get_power_profile_mode,
2308         .set_power_profile_mode = navi10_set_power_profile_mode,
2309         .get_profiling_clk_mask = navi10_get_profiling_clk_mask,
2310         .set_watermarks_table = navi10_set_watermarks_table,
2311         .read_sensor = navi10_read_sensor,
2312         .get_uclk_dpm_states = navi10_get_uclk_dpm_states,
2313         .set_performance_level = navi10_set_performance_level,
2314         .get_thermal_temperature_range = navi10_get_thermal_temperature_range,
2315         .display_disable_memory_clock_switch = navi10_display_disable_memory_clock_switch,
2316         .get_power_limit = navi10_get_power_limit,
2317         .update_pcie_parameters = navi10_update_pcie_parameters,
2318         .init_microcode = smu_v11_0_init_microcode,
2319         .load_microcode = smu_v11_0_load_microcode,
2320         .init_smc_tables = smu_v11_0_init_smc_tables,
2321         .fini_smc_tables = smu_v11_0_fini_smc_tables,
2322         .init_power = smu_v11_0_init_power,
2323         .fini_power = smu_v11_0_fini_power,
2324         .check_fw_status = smu_v11_0_check_fw_status,
2325         .setup_pptable = smu_v11_0_setup_pptable,
2326         .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
2327         .get_clk_info_from_vbios = smu_v11_0_get_clk_info_from_vbios,
2328         .check_pptable = smu_v11_0_check_pptable,
2329         .parse_pptable = smu_v11_0_parse_pptable,
2330         .populate_smc_tables = smu_v11_0_populate_smc_pptable,
2331         .check_fw_version = smu_v11_0_check_fw_version,
2332         .write_pptable = smu_v11_0_write_pptable,
2333         .set_min_dcef_deep_sleep = smu_v11_0_set_min_dcef_deep_sleep,
2334         .set_driver_table_location = smu_v11_0_set_driver_table_location,
2335         .set_tool_table_location = smu_v11_0_set_tool_table_location,
2336         .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
2337         .system_features_control = smu_v11_0_system_features_control,
2338         .send_smc_msg_with_param = smu_v11_0_send_msg_with_param,
2339         .read_smc_arg = smu_v11_0_read_arg,
2340         .init_display_count = smu_v11_0_init_display_count,
2341         .set_allowed_mask = smu_v11_0_set_allowed_mask,
2342         .get_enabled_mask = smu_v11_0_get_enabled_mask,
2343         .notify_display_change = smu_v11_0_notify_display_change,
2344         .set_power_limit = smu_v11_0_set_power_limit,
2345         .get_current_clk_freq = smu_v11_0_get_current_clk_freq,
2346         .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
2347         .start_thermal_control = smu_v11_0_start_thermal_control,
2348         .stop_thermal_control = smu_v11_0_stop_thermal_control,
2349         .set_deep_sleep_dcefclk = smu_v11_0_set_deep_sleep_dcefclk,
2350         .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
2351         .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
2352         .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
2353         .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
2354         .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
2355         .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
2356         .gfx_off_control = smu_v11_0_gfx_off_control,
2357         .register_irq_handler = smu_v11_0_register_irq_handler,
2358         .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
2359         .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
2360         .baco_is_support= smu_v11_0_baco_is_support,
2361         .baco_get_state = smu_v11_0_baco_get_state,
2362         .baco_set_state = smu_v11_0_baco_set_state,
2363         .baco_enter = smu_v11_0_baco_enter,
2364         .baco_exit = smu_v11_0_baco_exit,
2365         .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
2366         .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
2367         .override_pcie_parameters = smu_v11_0_override_pcie_parameters,
2368         .set_default_od_settings = navi10_set_default_od_settings,
2369         .od_edit_dpm_table = navi10_od_edit_dpm_table,
2370         .get_pptable_power_limit = navi10_get_pptable_power_limit,
2371         .run_btc = navi10_run_btc,
2372         .disable_umc_cdr_12gbps_workaround = navi10_disable_umc_cdr_12gbps_workaround,
2373 };
2374
2375 void navi10_set_ppt_funcs(struct smu_context *smu)
2376 {
2377         smu->ppt_funcs = &navi10_ppt_funcs;
2378 }