drivers/gpu/drm/armada/armada_crtc.c

   1 /*
   2  * Copyright (C) 2012 Russell King
   3  *  Rewritten from the dovefb driver, and Armada510 manuals.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  */
   9 #include <linux/clk.h>
  10 #include <linux/component.h>
  11 #include <linux/of_device.h>
  12 #include <linux/platform_device.h>
  13 #include <drm/drmP.h>
  14 #include <drm/drm_crtc_helper.h>
  15 #include <drm/drm_plane_helper.h>
  16 #include <drm/drm_atomic_helper.h>
  17 #include "armada_crtc.h"
  18 #include "armada_drm.h"
  19 #include "armada_fb.h"
  20 #include "armada_gem.h"
  21 #include "armada_hw.h"
  22 #include "armada_trace.h"
  23
  24 enum csc_mode {
  25         CSC_AUTO = 0,
  26         CSC_YUV_CCIR601 = 1,
  27         CSC_YUV_CCIR709 = 2,
  28         CSC_RGB_COMPUTER = 1,
  29         CSC_RGB_STUDIO = 2,
  30 };
  31
  32 static const uint32_t armada_primary_formats[] = {
  33         DRM_FORMAT_UYVY,
  34         DRM_FORMAT_YUYV,
  35         DRM_FORMAT_VYUY,
  36         DRM_FORMAT_YVYU,
  37         DRM_FORMAT_ARGB8888,
  38         DRM_FORMAT_ABGR8888,
  39         DRM_FORMAT_XRGB8888,
  40         DRM_FORMAT_XBGR8888,
  41         DRM_FORMAT_RGB888,
  42         DRM_FORMAT_BGR888,
  43         DRM_FORMAT_ARGB1555,
  44         DRM_FORMAT_ABGR1555,
  45         DRM_FORMAT_RGB565,
  46         DRM_FORMAT_BGR565,
  47 };
  48
  49 /*
  50  * A note about interlacing.  Let's consider HDMI 1920x1080i.
  51  * The timing parameters we have from X are:
  52  *  Hact HsyA HsyI Htot  Vact VsyA VsyI Vtot
  53  *  1920 2448 2492 2640  1080 1084 1094 1125
  54  * Which get translated to:
  55  *  Hact HsyA HsyI Htot  Vact VsyA VsyI Vtot
  56  *  1920 2448 2492 2640   540  542  547  562
  57  *
  58  * This is how it is defined by CEA-861-D - line and pixel numbers are
  59  * referenced to the rising edge of VSYNC and HSYNC.  Total clocks per
  60  * line: 2640.  The odd frame, the first active line is at line 21, and
  61  * the even frame, the first active line is 584.
  62  *
  63  * LN:    560     561     562     563             567     568    569
  64  * DE:    ~~~|____________________________//__________________________
  65  * HSYNC: ____|~|_____|~|_____|~|_____|~|_//__|~|_____|~|_____|~|_____
  66  * VSYNC: _________________________|~~~~~~//~~~~~~~~~~~~~~~|__________
  67  *  22 blanking lines.  VSYNC at 1320 (referenced to the HSYNC rising edge).
  68  *
  69  * LN:    1123   1124    1125      1               5       6      7
  70  * DE:    ~~~|____________________________//__________________________
  71  * HSYNC: ____|~|_____|~|_____|~|_____|~|_//__|~|_____|~|_____|~|_____
  72  * VSYNC: ____________________|~~~~~~~~~~~//~~~~~~~~~~|_______________
  73  *  23 blanking lines
  74  *
  75  * The Armada LCD Controller line and pixel numbers are, like X timings,
  76  * referenced to the top left of the active frame.
  77  *
  78  * So, translating these to our LCD controller:
  79  *  Odd frame, 563 total lines, VSYNC at line 543-548, pixel 1128.
  80  *  Even frame, 562 total lines, VSYNC at line 542-547, pixel 2448.
  81  * Note: Vsync front porch remains constant!
  82  *
  83  * if (odd_frame) {
  84  *   vtotal = mode->crtc_vtotal + 1;
  85  *   vbackporch = mode->crtc_vsync_start - mode->crtc_vdisplay + 1;
  86  *   vhorizpos = mode->crtc_hsync_start - mode->crtc_htotal / 2
  87  * } else {
  88  *   vtotal = mode->crtc_vtotal;
  89  *   vbackporch = mode->crtc_vsync_start - mode->crtc_vdisplay;
  90  *   vhorizpos = mode->crtc_hsync_start;
  91  * }
  92  * vfrontporch = mode->crtc_vtotal - mode->crtc_vsync_end;
  93  *
  94  * So, we need to reprogram these registers on each vsync event:
  95  *  LCD_SPU_V_PORCH, LCD_SPU_ADV_REG, LCD_SPUT_V_H_TOTAL
  96  *
  97  * Note: we do not use the frame done interrupts because these appear
  98  * to happen too early, and lead to jitter on the display (presumably
  99  * they occur at the end of the last active line, before the vsync back
 100  * porch, which we're reprogramming.)
 101  */
 102
 103 void
 104 armada_drm_crtc_update_regs(struct armada_crtc *dcrtc, struct armada_regs *regs)
 105 {
 106         while (regs->offset != ~0) {
 107                 void __iomem *reg = dcrtc->base + regs->offset;
 108                 uint32_t val;
 109
 110                 val = regs->mask;
 111                 if (val != 0)
 112                         val &= readl_relaxed(reg);
 113                 writel_relaxed(val | regs->val, reg);
 114                 ++regs;
 115         }
 116 }
 117
 118 #define dpms_blanked(dpms)      ((dpms) != DRM_MODE_DPMS_ON)
 119
 120 static void armada_drm_crtc_update(struct armada_crtc *dcrtc)
 121 {
 122         uint32_t dumb_ctrl;
 123
 124         dumb_ctrl = dcrtc->cfg_dumb_ctrl;
 125
 126         if (!dpms_blanked(dcrtc->dpms))
 127                 dumb_ctrl |= CFG_DUMB_ENA;
 128
 129         /*
 130          * When the dumb interface isn't in DUMB24_RGB888_0 mode, it might
 131          * be using SPI or GPIO.  If we set this to DUMB_BLANK, we will
 132          * force LCD_D[23:0] to output blank color, overriding the GPIO or
 133          * SPI usage.  So leave it as-is unless in DUMB24_RGB888_0 mode.
 134          */
 135         if (dpms_blanked(dcrtc->dpms) &&
 136             (dumb_ctrl & DUMB_MASK) == DUMB24_RGB888_0) {
 137                 dumb_ctrl &= ~DUMB_MASK;
 138                 dumb_ctrl |= DUMB_BLANK;
 139         }
 140
 141         /*
 142          * The documentation doesn't indicate what the normal state of
 143          * the sync signals are.  Sebastian Hesselbart kindly probed
 144          * these signals on his board to determine their state.
 145          *
 146          * The non-inverted state of the sync signals is active high.
 147          * Setting these bits makes the appropriate signal active low.
 148          */
 149         if (dcrtc->crtc.mode.flags & DRM_MODE_FLAG_NCSYNC)
 150                 dumb_ctrl |= CFG_INV_CSYNC;
 151         if (dcrtc->crtc.mode.flags & DRM_MODE_FLAG_NHSYNC)
 152                 dumb_ctrl |= CFG_INV_HSYNC;
 153         if (dcrtc->crtc.mode.flags & DRM_MODE_FLAG_NVSYNC)
 154                 dumb_ctrl |= CFG_INV_VSYNC;
 155
 156         if (dcrtc->dumb_ctrl != dumb_ctrl) {
 157                 dcrtc->dumb_ctrl = dumb_ctrl;
 158                 writel_relaxed(dumb_ctrl, dcrtc->base + LCD_SPU_DUMB_CTRL);
 159         }
 160 }
 161
 162 void armada_drm_plane_calc_addrs(u32 *addrs, struct drm_framebuffer *fb,
 163         int x, int y)
 164 {
 165         const struct drm_format_info *format = fb->format;
 166         unsigned int num_planes = format->num_planes;
 167         u32 addr = drm_fb_obj(fb)->dev_addr;
 168         int i;
 169
 170         if (num_planes > 3)
 171                 num_planes = 3;
 172
 173         addrs[0] = addr + fb->offsets[0] + y * fb->pitches[0] +
 174                    x * format->cpp[0];
 175
 176         y /= format->vsub;
 177         x /= format->hsub;
 178
 179         for (i = 1; i < num_planes; i++)
 180                 addrs[i] = addr + fb->offsets[i] + y * fb->pitches[i] +
 181                              x * format->cpp[i];
 182         for (; i < 3; i++)
 183                 addrs[i] = 0;
 184 }
 185
 186 static unsigned armada_drm_crtc_calc_fb(struct drm_framebuffer *fb,
 187         int x, int y, struct armada_regs *regs, bool interlaced)
 188 {
 189         unsigned pitch = fb->pitches[0];
 190         u32 addrs[3], addr_odd, addr_even;
 191         unsigned i = 0;
 192
 193         DRM_DEBUG_DRIVER("pitch %u x %d y %d bpp %d\n",
 194                 pitch, x, y, fb->format->cpp[0] * 8);
 195
 196         armada_drm_plane_calc_addrs(addrs, fb, x, y);
 197
 198         addr_odd = addr_even = addrs[0];
 199
 200         if (interlaced) {
 201                 addr_even += pitch;
 202                 pitch *= 2;
 203         }
 204
 205         /* write offset, base, and pitch */
 206         armada_reg_queue_set(regs, i, addr_odd, LCD_CFG_GRA_START_ADDR0);
 207         armada_reg_queue_set(regs, i, addr_even, LCD_CFG_GRA_START_ADDR1);
 208         armada_reg_queue_mod(regs, i, pitch, 0xffff, LCD_CFG_GRA_PITCH);
 209
 210         return i;
 211 }
 212
 213 static void armada_drm_plane_work_call(struct armada_crtc *dcrtc,
 214         struct armada_plane_work *work,
 215         void (*fn)(struct armada_crtc *, struct armada_plane_work *))
 216 {
 217         struct armada_plane *dplane = drm_to_armada_plane(work->plane);
 218         struct drm_pending_vblank_event *event;
 219         struct drm_framebuffer *fb;
 220
 221         if (fn)
 222                 fn(dcrtc, work);
 223         drm_crtc_vblank_put(&dcrtc->crtc);
 224
 225         event = work->event;
 226         fb = work->old_fb;
 227         if (event || fb) {
 228                 struct drm_device *dev = dcrtc->crtc.dev;
 229                 unsigned long flags;
 230
 231                 spin_lock_irqsave(&dev->event_lock, flags);
 232                 if (event)
 233                         drm_crtc_send_vblank_event(&dcrtc->crtc, event);
 234                 if (fb)
 235                         __armada_drm_queue_unref_work(dev, fb);
 236                 spin_unlock_irqrestore(&dev->event_lock, flags);
 237         }
 238
 239         if (work->need_kfree)
 240                 kfree(work);
 241
 242         wake_up(&dplane->frame_wait);
 243 }
 244
 245 static void armada_drm_plane_work_run(struct armada_crtc *dcrtc,
 246         struct drm_plane *plane)
 247 {
 248         struct armada_plane *dplane = drm_to_armada_plane(plane);
 249         struct armada_plane_work *work = xchg(&dplane->work, NULL);
 250
 251         /* Handle any pending frame work. */
 252         if (work)
 253                 armada_drm_plane_work_call(dcrtc, work, work->fn);
 254 }
 255
 256 int armada_drm_plane_work_queue(struct armada_crtc *dcrtc,
 257         struct armada_plane_work *work)
 258 {
 259         struct armada_plane *plane = drm_to_armada_plane(work->plane);
 260         int ret;
 261
 262         ret = drm_crtc_vblank_get(&dcrtc->crtc);
 263         if (ret)
 264                 return ret;
 265
 266         ret = cmpxchg(&plane->work, NULL, work) ? -EBUSY : 0;
 267         if (ret)
 268                 drm_crtc_vblank_put(&dcrtc->crtc);
 269
 270         return ret;
 271 }
 272
 273 int armada_drm_plane_work_wait(struct armada_plane *plane, long timeout)
 274 {
 275         return wait_event_timeout(plane->frame_wait, !plane->work, timeout);
 276 }
 277
 278 void armada_drm_plane_work_cancel(struct armada_crtc *dcrtc,
 279         struct armada_plane *dplane)
 280 {
 281         struct armada_plane_work *work = xchg(&dplane->work, NULL);
 282
 283         if (work)
 284                 armada_drm_plane_work_call(dcrtc, work, work->cancel);
 285 }
 286
 287 static void armada_drm_crtc_complete_frame_work(struct armada_crtc *dcrtc,
 288         struct armada_plane_work *work)
 289 {
 290         unsigned long flags;
 291
 292         spin_lock_irqsave(&dcrtc->irq_lock, flags);
 293         armada_drm_crtc_update_regs(dcrtc, work->regs);
 294         spin_unlock_irqrestore(&dcrtc->irq_lock, flags);
 295 }
 296
 297 static void armada_drm_crtc_complete_disable_work(struct armada_crtc *dcrtc,
 298         struct armada_plane_work *work)
 299 {
 300         unsigned long flags;
 301
 302         if (dcrtc->plane == work->plane)
 303                 dcrtc->plane = NULL;
 304
 305         spin_lock_irqsave(&dcrtc->irq_lock, flags);
 306         armada_drm_crtc_update_regs(dcrtc, work->regs);
 307         spin_unlock_irqrestore(&dcrtc->irq_lock, flags);
 308 }
 309
 310 static struct armada_plane_work *
 311 armada_drm_crtc_alloc_plane_work(struct drm_plane *plane)
 312 {
 313         struct armada_plane_work *work;
 314         int i = 0;
 315
 316         work = kzalloc(sizeof(*work), GFP_KERNEL);
 317         if (!work)
 318                 return NULL;
 319
 320         work->plane = plane;
 321         work->fn = armada_drm_crtc_complete_frame_work;
 322         work->need_kfree = true;
 323         armada_reg_queue_end(work->regs, i);
 324
 325         return work;
 326 }
 327
 328 static void armada_drm_crtc_finish_fb(struct armada_crtc *dcrtc,
 329         struct drm_framebuffer *fb, bool force)
 330 {
 331         struct armada_plane_work *work;
 332
 333         if (!fb)
 334                 return;
 335
 336         if (force) {
 337                 /* Display is disabled, so just drop the old fb */
 338                 drm_framebuffer_put(fb);
 339                 return;
 340         }
 341
 342         work = armada_drm_crtc_alloc_plane_work(dcrtc->crtc.primary);
 343         if (work) {
 344                 work->old_fb = fb;
 345
 346                 if (armada_drm_plane_work_queue(dcrtc, work) == 0)
 347                         return;
 348
 349                 kfree(work);
 350         }
 351
 352         /*
 353          * Oops - just drop the reference immediately and hope for
 354          * the best.  The worst that will happen is the buffer gets
 355          * reused before it has finished being displayed.
 356          */
 357         drm_framebuffer_put(fb);
 358 }
 359
 360 static void armada_drm_vblank_off(struct armada_crtc *dcrtc)
 361 {
 362         /*
 363          * Tell the DRM core that vblank IRQs aren't going to happen for
 364          * a while.  This cleans up any pending vblank events for us.
 365          */
 366         drm_crtc_vblank_off(&dcrtc->crtc);
 367         armada_drm_plane_work_run(dcrtc, dcrtc->crtc.primary);
 368 }
 369
 370 /* The mode_config.mutex will be held for this call */
 371 static void armada_drm_crtc_dpms(struct drm_crtc *crtc, int dpms)
 372 {
 373         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 374
 375         if (dpms_blanked(dcrtc->dpms) != dpms_blanked(dpms)) {
 376                 if (dpms_blanked(dpms))
 377                         armada_drm_vblank_off(dcrtc);
 378                 else if (!IS_ERR(dcrtc->clk))
 379                         WARN_ON(clk_prepare_enable(dcrtc->clk));
 380                 dcrtc->dpms = dpms;
 381                 armada_drm_crtc_update(dcrtc);
 382                 if (!dpms_blanked(dpms))
 383                         drm_crtc_vblank_on(&dcrtc->crtc);
 384                 else if (!IS_ERR(dcrtc->clk))
 385                         clk_disable_unprepare(dcrtc->clk);
 386         } else if (dcrtc->dpms != dpms) {
 387                 dcrtc->dpms = dpms;
 388         }
 389 }
 390
 391 /*
 392  * Prepare for a mode set.  Turn off overlay to ensure that we don't end
 393  * up with the overlay size being bigger than the active screen size.
 394  * We rely upon X refreshing this state after the mode set has completed.
 395  *
 396  * The mode_config.mutex will be held for this call
 397  */
 398 static void armada_drm_crtc_prepare(struct drm_crtc *crtc)
 399 {
 400         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 401         struct drm_plane *plane;
 402
 403         /*
 404          * If we have an overlay plane associated with this CRTC, disable
 405          * it before the modeset to avoid its coordinates being outside
 406          * the new mode parameters.
 407          */
 408         plane = dcrtc->plane;
 409         if (plane) {
 410                 drm_plane_force_disable(plane);
 411                 WARN_ON(!armada_drm_plane_work_wait(drm_to_armada_plane(plane),
 412                                                     HZ));
 413         }
 414 }
 415
 416 /* The mode_config.mutex will be held for this call */
 417 static void armada_drm_crtc_commit(struct drm_crtc *crtc)
 418 {
 419         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 420
 421         if (dcrtc->dpms != DRM_MODE_DPMS_ON) {
 422                 dcrtc->dpms = DRM_MODE_DPMS_ON;
 423                 armada_drm_crtc_update(dcrtc);
 424         }
 425 }
 426
 427 /* The mode_config.mutex will be held for this call */
 428 static bool armada_drm_crtc_mode_fixup(struct drm_crtc *crtc,
 429         const struct drm_display_mode *mode, struct drm_display_mode *adj)
 430 {
 431         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 432         int ret;
 433
 434         /* We can't do interlaced modes if we don't have the SPU_ADV_REG */
 435         if (!dcrtc->variant->has_spu_adv_reg &&
 436             adj->flags & DRM_MODE_FLAG_INTERLACE)
 437                 return false;
 438
 439         /* Check whether the display mode is possible */
 440         ret = dcrtc->variant->compute_clock(dcrtc, adj, NULL);
 441         if (ret)
 442                 return false;
 443
 444         return true;
 445 }
 446
 447 /* These are locked by dev->vbl_lock */
 448 static void armada_drm_crtc_disable_irq(struct armada_crtc *dcrtc, u32 mask)
 449 {
 450         if (dcrtc->irq_ena & mask) {
 451                 dcrtc->irq_ena &= ~mask;
 452                 writel(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA);
 453         }
 454 }
 455
 456 static void armada_drm_crtc_enable_irq(struct armada_crtc *dcrtc, u32 mask)
 457 {
 458         if ((dcrtc->irq_ena & mask) != mask) {
 459                 dcrtc->irq_ena |= mask;
 460                 writel(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA);
 461                 if (readl_relaxed(dcrtc->base + LCD_SPU_IRQ_ISR) & mask)
 462                         writel(0, dcrtc->base + LCD_SPU_IRQ_ISR);
 463         }
 464 }
 465
 466 static void armada_drm_crtc_irq(struct armada_crtc *dcrtc, u32 stat)
 467 {
 468         void __iomem *base = dcrtc->base;
 469         struct drm_plane *ovl_plane;
 470
 471         if (stat & DMA_FF_UNDERFLOW)
 472                 DRM_ERROR("video underflow on crtc %u\n", dcrtc->num);
 473         if (stat & GRA_FF_UNDERFLOW)
 474                 DRM_ERROR("graphics underflow on crtc %u\n", dcrtc->num);
 475
 476         if (stat & VSYNC_IRQ)
 477                 drm_crtc_handle_vblank(&dcrtc->crtc);
 478
 479         ovl_plane = dcrtc->plane;
 480         if (ovl_plane)
 481                 armada_drm_plane_work_run(dcrtc, ovl_plane);
 482
 483         spin_lock(&dcrtc->irq_lock);
 484         if (stat & GRA_FRAME_IRQ && dcrtc->interlaced) {
 485                 int i = stat & GRA_FRAME_IRQ0 ? 0 : 1;
 486                 uint32_t val;
 487
 488                 writel_relaxed(dcrtc->v[i].spu_v_porch, base + LCD_SPU_V_PORCH);
 489                 writel_relaxed(dcrtc->v[i].spu_v_h_total,
 490                                base + LCD_SPUT_V_H_TOTAL);
 491
 492                 val = readl_relaxed(base + LCD_SPU_ADV_REG);
 493                 val &= ~(ADV_VSYNC_L_OFF | ADV_VSYNC_H_OFF | ADV_VSYNCOFFEN);
 494                 val |= dcrtc->v[i].spu_adv_reg;
 495                 writel_relaxed(val, base + LCD_SPU_ADV_REG);
 496         }
 497
 498         if (stat & DUMB_FRAMEDONE && dcrtc->cursor_update) {
 499                 writel_relaxed(dcrtc->cursor_hw_pos,
 500                                base + LCD_SPU_HWC_OVSA_HPXL_VLN);
 501                 writel_relaxed(dcrtc->cursor_hw_sz,
 502                                base + LCD_SPU_HWC_HPXL_VLN);
 503                 armada_updatel(CFG_HWC_ENA,
 504                                CFG_HWC_ENA | CFG_HWC_1BITMOD | CFG_HWC_1BITENA,
 505                                base + LCD_SPU_DMA_CTRL0);
 506                 dcrtc->cursor_update = false;
 507                 armada_drm_crtc_disable_irq(dcrtc, DUMB_FRAMEDONE_ENA);
 508         }
 509
 510         spin_unlock(&dcrtc->irq_lock);
 511
 512         if (stat & GRA_FRAME_IRQ)
 513                 armada_drm_plane_work_run(dcrtc, dcrtc->crtc.primary);
 514 }
 515
 516 static irqreturn_t armada_drm_irq(int irq, void *arg)
 517 {
 518         struct armada_crtc *dcrtc = arg;
 519         u32 v, stat = readl_relaxed(dcrtc->base + LCD_SPU_IRQ_ISR);
 520
 521         /*
 522          * Reading the ISR appears to clear bits provided CLEAN_SPU_IRQ_ISR
 523          * is set.  Writing has some other effect to acknowledge the IRQ -
 524          * without this, we only get a single IRQ.
 525          */
 526         writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ISR);
 527
 528         trace_armada_drm_irq(&dcrtc->crtc, stat);
 529
 530         /* Mask out those interrupts we haven't enabled */
 531         v = stat & dcrtc->irq_ena;
 532
 533         if (v & (VSYNC_IRQ|GRA_FRAME_IRQ|DUMB_FRAMEDONE)) {
 534                 armada_drm_crtc_irq(dcrtc, stat);
 535                 return IRQ_HANDLED;
 536         }
 537         return IRQ_NONE;
 538 }
 539
 540 static uint32_t armada_drm_crtc_calculate_csc(struct armada_crtc *dcrtc)
 541 {
 542         struct drm_display_mode *adj = &dcrtc->crtc.mode;
 543         uint32_t val = 0;
 544
 545         if (dcrtc->csc_yuv_mode == CSC_YUV_CCIR709)
 546                 val |= CFG_CSC_YUV_CCIR709;
 547         if (dcrtc->csc_rgb_mode == CSC_RGB_STUDIO)
 548                 val |= CFG_CSC_RGB_STUDIO;
 549
 550         /*
 551          * In auto mode, set the colorimetry, based upon the HDMI spec.
 552          * 1280x720p, 1920x1080p and 1920x1080i use ITU709, others use
 553          * ITU601.  It may be more appropriate to set this depending on
 554          * the source - but what if the graphic frame is YUV and the
 555          * video frame is RGB?
 556          */
 557         if ((adj->hdisplay == 1280 && adj->vdisplay == 720 &&
 558              !(adj->flags & DRM_MODE_FLAG_INTERLACE)) ||
 559             (adj->hdisplay == 1920 && adj->vdisplay == 1080)) {
 560                 if (dcrtc->csc_yuv_mode == CSC_AUTO)
 561                         val |= CFG_CSC_YUV_CCIR709;
 562         }
 563
 564         /*
 565          * We assume we're connected to a TV-like device, so the YUV->RGB
 566          * conversion should produce a limited range.  We should set this
 567          * depending on the connectors attached to this CRTC, and what
 568          * kind of device they report being connected.
 569          */
 570         if (dcrtc->csc_rgb_mode == CSC_AUTO)
 571                 val |= CFG_CSC_RGB_STUDIO;
 572
 573         return val;
 574 }
 575
 576 static void armada_drm_gra_plane_regs(struct armada_regs *regs,
 577         struct drm_framebuffer *fb, struct armada_plane_state *state,
 578         int x, int y, bool interlaced)
 579 {
 580         unsigned int i;
 581         u32 ctrl0;
 582
 583         i = armada_drm_crtc_calc_fb(fb, x, y, regs, interlaced);
 584         armada_reg_queue_set(regs, i, state->dst_yx, LCD_SPU_GRA_OVSA_HPXL_VLN);
 585         armada_reg_queue_set(regs, i, state->src_hw, LCD_SPU_GRA_HPXL_VLN);
 586         armada_reg_queue_set(regs, i, state->dst_hw, LCD_SPU_GZM_HPXL_VLN);
 587
 588         ctrl0 = state->ctrl0;
 589         if (interlaced)
 590                 ctrl0 |= CFG_GRA_FTOGGLE;
 591
 592         armada_reg_queue_mod(regs, i, ctrl0, CFG_GRAFORMAT |
 593                              CFG_GRA_MOD(CFG_SWAPRB | CFG_SWAPUV |
 594                                          CFG_SWAPYU | CFG_YUV2RGB) |
 595                              CFG_PALETTE_ENA | CFG_GRA_FTOGGLE |
 596                              CFG_GRA_HSMOOTH | CFG_GRA_ENA,
 597                              LCD_SPU_DMA_CTRL0);
 598         armada_reg_queue_end(regs, i);
 599 }
 600
 601 static void armada_drm_primary_set(struct drm_crtc *crtc,
 602         struct drm_plane *plane, int x, int y)
 603 {
 604         struct armada_plane_state *state = &drm_to_armada_plane(plane)->state;
 605         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 606         struct armada_regs regs[8];
 607         bool interlaced = dcrtc->interlaced;
 608
 609         armada_drm_gra_plane_regs(regs, plane->fb, state, x, y, interlaced);
 610         armada_drm_crtc_update_regs(dcrtc, regs);
 611 }
 612
 613 /* The mode_config.mutex will be held for this call */
 614 static int armada_drm_crtc_mode_set(struct drm_crtc *crtc,
 615         struct drm_display_mode *mode, struct drm_display_mode *adj,
 616         int x, int y, struct drm_framebuffer *old_fb)
 617 {
 618         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 619         struct armada_regs regs[17];
 620         uint32_t lm, rm, tm, bm, val, sclk;
 621         unsigned long flags;
 622         unsigned i;
 623         bool interlaced;
 624
 625         drm_framebuffer_get(crtc->primary->fb);
 626
 627         interlaced = !!(adj->flags & DRM_MODE_FLAG_INTERLACE);
 628
 629         val = CFG_GRA_ENA;
 630         val |= CFG_GRA_FMT(drm_fb_to_armada_fb(dcrtc->crtc.primary->fb)->fmt);
 631         val |= CFG_GRA_MOD(drm_fb_to_armada_fb(dcrtc->crtc.primary->fb)->mod);
 632
 633         if (drm_fb_to_armada_fb(dcrtc->crtc.primary->fb)->fmt > CFG_420)
 634                 val |= CFG_PALETTE_ENA;
 635
 636         drm_to_armada_plane(crtc->primary)->state.ctrl0 = val;
 637         drm_to_armada_plane(crtc->primary)->state.src_hw =
 638         drm_to_armada_plane(crtc->primary)->state.dst_hw =
 639                 adj->crtc_vdisplay << 16 | adj->crtc_hdisplay;
 640         drm_to_armada_plane(crtc->primary)->state.dst_yx = 0;
 641
 642         i = 0;
 643         rm = adj->crtc_hsync_start - adj->crtc_hdisplay;
 644         lm = adj->crtc_htotal - adj->crtc_hsync_end;
 645         bm = adj->crtc_vsync_start - adj->crtc_vdisplay;
 646         tm = adj->crtc_vtotal - adj->crtc_vsync_end;
 647
 648         DRM_DEBUG_DRIVER("H: %d %d %d %d lm %d rm %d\n",
 649                 adj->crtc_hdisplay,
 650                 adj->crtc_hsync_start,
 651                 adj->crtc_hsync_end,
 652                 adj->crtc_htotal, lm, rm);
 653         DRM_DEBUG_DRIVER("V: %d %d %d %d tm %d bm %d\n",
 654                 adj->crtc_vdisplay,
 655                 adj->crtc_vsync_start,
 656                 adj->crtc_vsync_end,
 657                 adj->crtc_vtotal, tm, bm);
 658
 659         /* Wait for pending flips to complete */
 660         armada_drm_plane_work_wait(drm_to_armada_plane(dcrtc->crtc.primary),
 661                                    MAX_SCHEDULE_TIMEOUT);
 662
 663         drm_crtc_vblank_off(crtc);
 664
 665         val = dcrtc->dumb_ctrl & ~CFG_DUMB_ENA;
 666         if (val != dcrtc->dumb_ctrl) {
 667                 dcrtc->dumb_ctrl = val;
 668                 writel_relaxed(val, dcrtc->base + LCD_SPU_DUMB_CTRL);
 669         }
 670
 671         /*
 672          * If we are blanked, we would have disabled the clock.  Re-enable
 673          * it so that compute_clock() does the right thing.
 674          */
 675         if (!IS_ERR(dcrtc->clk) && dpms_blanked(dcrtc->dpms))
 676                 WARN_ON(clk_prepare_enable(dcrtc->clk));
 677
 678         /* Now compute the divider for real */
 679         dcrtc->variant->compute_clock(dcrtc, adj, &sclk);
 680
 681         armada_reg_queue_set(regs, i, sclk, LCD_CFG_SCLK_DIV);
 682
 683         if (interlaced ^ dcrtc->interlaced) {
 684                 if (adj->flags & DRM_MODE_FLAG_INTERLACE)
 685                         drm_crtc_vblank_get(&dcrtc->crtc);
 686                 else
 687                         drm_crtc_vblank_put(&dcrtc->crtc);
 688                 dcrtc->interlaced = interlaced;
 689         }
 690
 691         spin_lock_irqsave(&dcrtc->irq_lock, flags);
 692
 693         /* Ensure graphic fifo is enabled */
 694         armada_reg_queue_mod(regs, i, 0, CFG_PDWN64x66, LCD_SPU_SRAM_PARA1);
 695
 696         /* Even interlaced/progressive frame */
 697         dcrtc->v[1].spu_v_h_total = adj->crtc_vtotal << 16 |
 698                                     adj->crtc_htotal;
 699         dcrtc->v[1].spu_v_porch = tm << 16 | bm;
 700         val = adj->crtc_hsync_start;
 701         dcrtc->v[1].spu_adv_reg = val << 20 | val | ADV_VSYNCOFFEN |
 702                 dcrtc->variant->spu_adv_reg;
 703
 704         if (interlaced) {
 705                 /* Odd interlaced frame */
 706                 dcrtc->v[0].spu_v_h_total = dcrtc->v[1].spu_v_h_total +
 707                                                 (1 << 16);
 708                 dcrtc->v[0].spu_v_porch = dcrtc->v[1].spu_v_porch + 1;
 709                 val = adj->crtc_hsync_start - adj->crtc_htotal / 2;
 710                 dcrtc->v[0].spu_adv_reg = val << 20 | val | ADV_VSYNCOFFEN |
 711                         dcrtc->variant->spu_adv_reg;
 712         } else {
 713                 dcrtc->v[0] = dcrtc->v[1];
 714         }
 715
 716         val = adj->crtc_vdisplay << 16 | adj->crtc_hdisplay;
 717
 718         armada_reg_queue_set(regs, i, val, LCD_SPU_V_H_ACTIVE);
 719         armada_reg_queue_set(regs, i, (lm << 16) | rm, LCD_SPU_H_PORCH);
 720         armada_reg_queue_set(regs, i, dcrtc->v[0].spu_v_porch, LCD_SPU_V_PORCH);
 721         armada_reg_queue_set(regs, i, dcrtc->v[0].spu_v_h_total,
 722                            LCD_SPUT_V_H_TOTAL);
 723
 724         if (dcrtc->variant->has_spu_adv_reg) {
 725                 armada_reg_queue_mod(regs, i, dcrtc->v[0].spu_adv_reg,
 726                                      ADV_VSYNC_L_OFF | ADV_VSYNC_H_OFF |
 727                                      ADV_VSYNCOFFEN, LCD_SPU_ADV_REG);
 728         }
 729
 730         val = adj->flags & DRM_MODE_FLAG_NVSYNC ? CFG_VSYNC_INV : 0;
 731         armada_reg_queue_mod(regs, i, val, CFG_VSYNC_INV, LCD_SPU_DMA_CTRL1);
 732
 733         val = dcrtc->spu_iopad_ctrl | armada_drm_crtc_calculate_csc(dcrtc);
 734         armada_reg_queue_set(regs, i, val, LCD_SPU_IOPAD_CONTROL);
 735         armada_reg_queue_end(regs, i);
 736
 737         armada_drm_crtc_update_regs(dcrtc, regs);
 738
 739         armada_drm_primary_set(crtc, crtc->primary, x, y);
 740         spin_unlock_irqrestore(&dcrtc->irq_lock, flags);
 741
 742         armada_drm_crtc_update(dcrtc);
 743
 744         drm_crtc_vblank_on(crtc);
 745         armada_drm_crtc_finish_fb(dcrtc, old_fb, dpms_blanked(dcrtc->dpms));
 746
 747         return 0;
 748 }
 749
 750 /* The mode_config.mutex will be held for this call */
 751 static int armada_drm_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
 752         struct drm_framebuffer *old_fb)
 753 {
 754         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 755         struct armada_regs regs[4];
 756         unsigned i;
 757
 758         i = armada_drm_crtc_calc_fb(crtc->primary->fb, crtc->x, crtc->y, regs,
 759                                     dcrtc->interlaced);
 760         armada_reg_queue_end(regs, i);
 761
 762         /* Wait for pending flips to complete */
 763         armada_drm_plane_work_wait(drm_to_armada_plane(dcrtc->crtc.primary),
 764                                    MAX_SCHEDULE_TIMEOUT);
 765
 766         /* Take a reference to the new fb as we're using it */
 767         drm_framebuffer_get(crtc->primary->fb);
 768
 769         /* Update the base in the CRTC */
 770         armada_drm_crtc_update_regs(dcrtc, regs);
 771
 772         /* Drop our previously held reference */
 773         armada_drm_crtc_finish_fb(dcrtc, old_fb, dpms_blanked(dcrtc->dpms));
 774
 775         return 0;
 776 }
 777
 778 /* The mode_config.mutex will be held for this call */
 779 static void armada_drm_crtc_disable(struct drm_crtc *crtc)
 780 {
 781         armada_drm_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
 782
 783         /* Disable our primary plane when we disable the CRTC. */
 784         crtc->primary->funcs->disable_plane(crtc->primary, NULL);
 785 }
 786
 787 static const struct drm_crtc_helper_funcs armada_crtc_helper_funcs = {
 788         .dpms           = armada_drm_crtc_dpms,
 789         .prepare        = armada_drm_crtc_prepare,
 790         .commit         = armada_drm_crtc_commit,
 791         .mode_fixup     = armada_drm_crtc_mode_fixup,
 792         .mode_set       = armada_drm_crtc_mode_set,
 793         .mode_set_base  = armada_drm_crtc_mode_set_base,
 794         .disable        = armada_drm_crtc_disable,
 795 };
 796
 797 static void armada_load_cursor_argb(void __iomem *base, uint32_t *pix,
 798         unsigned stride, unsigned width, unsigned height)
 799 {
 800         uint32_t addr;
 801         unsigned y;
 802
 803         addr = SRAM_HWC32_RAM1;
 804         for (y = 0; y < height; y++) {
 805                 uint32_t *p = &pix[y * stride];
 806                 unsigned x;
 807
 808                 for (x = 0; x < width; x++, p++) {
 809                         uint32_t val = *p;
 810
 811                         val = (val & 0xff00ff00) |
 812                               (val & 0x000000ff) << 16 |
 813                               (val & 0x00ff0000) >> 16;
 814
 815                         writel_relaxed(val,
 816                                        base + LCD_SPU_SRAM_WRDAT);
 817                         writel_relaxed(addr | SRAM_WRITE,
 818                                        base + LCD_SPU_SRAM_CTRL);
 819                         readl_relaxed(base + LCD_SPU_HWC_OVSA_HPXL_VLN);
 820                         addr += 1;
 821                         if ((addr & 0x00ff) == 0)
 822                                 addr += 0xf00;
 823                         if ((addr & 0x30ff) == 0)
 824                                 addr = SRAM_HWC32_RAM2;
 825                 }
 826         }
 827 }
 828
 829 static void armada_drm_crtc_cursor_tran(void __iomem *base)
 830 {
 831         unsigned addr;
 832
 833         for (addr = 0; addr < 256; addr++) {
 834                 /* write the default value */
 835                 writel_relaxed(0x55555555, base + LCD_SPU_SRAM_WRDAT);
 836                 writel_relaxed(addr | SRAM_WRITE | SRAM_HWC32_TRAN,
 837                                base + LCD_SPU_SRAM_CTRL);
 838         }
 839 }
 840
 841 static int armada_drm_crtc_cursor_update(struct armada_crtc *dcrtc, bool reload)
 842 {
 843         uint32_t xoff, xscr, w = dcrtc->cursor_w, s;
 844         uint32_t yoff, yscr, h = dcrtc->cursor_h;
 845         uint32_t para1;
 846
 847         /*
 848          * Calculate the visible width and height of the cursor,
 849          * screen position, and the position in the cursor bitmap.
 850          */
 851         if (dcrtc->cursor_x < 0) {
 852                 xoff = -dcrtc->cursor_x;
 853                 xscr = 0;
 854                 w -= min(xoff, w);
 855         } else if (dcrtc->cursor_x + w > dcrtc->crtc.mode.hdisplay) {
 856                 xoff = 0;
 857                 xscr = dcrtc->cursor_x;
 858                 w = max_t(int, dcrtc->crtc.mode.hdisplay - dcrtc->cursor_x, 0);
 859         } else {
 860                 xoff = 0;
 861                 xscr = dcrtc->cursor_x;
 862         }
 863
 864         if (dcrtc->cursor_y < 0) {
 865                 yoff = -dcrtc->cursor_y;
 866                 yscr = 0;
 867                 h -= min(yoff, h);
 868         } else if (dcrtc->cursor_y + h > dcrtc->crtc.mode.vdisplay) {
 869                 yoff = 0;
 870                 yscr = dcrtc->cursor_y;
 871                 h = max_t(int, dcrtc->crtc.mode.vdisplay - dcrtc->cursor_y, 0);
 872         } else {
 873                 yoff = 0;
 874                 yscr = dcrtc->cursor_y;
 875         }
 876
 877         /* On interlaced modes, the vertical cursor size must be halved */
 878         s = dcrtc->cursor_w;
 879         if (dcrtc->interlaced) {
 880                 s *= 2;
 881                 yscr /= 2;
 882                 h /= 2;
 883         }
 884
 885         if (!dcrtc->cursor_obj || !h || !w) {
 886                 spin_lock_irq(&dcrtc->irq_lock);
 887                 armada_drm_crtc_disable_irq(dcrtc, DUMB_FRAMEDONE_ENA);
 888                 dcrtc->cursor_update = false;
 889                 armada_updatel(0, CFG_HWC_ENA, dcrtc->base + LCD_SPU_DMA_CTRL0);
 890                 spin_unlock_irq(&dcrtc->irq_lock);
 891                 return 0;
 892         }
 893
 894         spin_lock_irq(&dcrtc->irq_lock);
 895         para1 = readl_relaxed(dcrtc->base + LCD_SPU_SRAM_PARA1);
 896         armada_updatel(CFG_CSB_256x32, CFG_CSB_256x32 | CFG_PDWN256x32,
 897                        dcrtc->base + LCD_SPU_SRAM_PARA1);
 898         spin_unlock_irq(&dcrtc->irq_lock);
 899
 900         /*
 901          * Initialize the transparency if the SRAM was powered down.
 902          * We must also reload the cursor data as well.
 903          */
 904         if (!(para1 & CFG_CSB_256x32)) {
 905                 armada_drm_crtc_cursor_tran(dcrtc->base);
 906                 reload = true;
 907         }
 908
 909         if (dcrtc->cursor_hw_sz != (h << 16 | w)) {
 910                 spin_lock_irq(&dcrtc->irq_lock);
 911                 armada_drm_crtc_disable_irq(dcrtc, DUMB_FRAMEDONE_ENA);
 912                 dcrtc->cursor_update = false;
 913                 armada_updatel(0, CFG_HWC_ENA, dcrtc->base + LCD_SPU_DMA_CTRL0);
 914                 spin_unlock_irq(&dcrtc->irq_lock);
 915                 reload = true;
 916         }
 917         if (reload) {
 918                 struct armada_gem_object *obj = dcrtc->cursor_obj;
 919                 uint32_t *pix;
 920                 /* Set the top-left corner of the cursor image */
 921                 pix = obj->addr;
 922                 pix += yoff * s + xoff;
 923                 armada_load_cursor_argb(dcrtc->base, pix, s, w, h);
 924         }
 925
 926         /* Reload the cursor position, size and enable in the IRQ handler */
 927         spin_lock_irq(&dcrtc->irq_lock);
 928         dcrtc->cursor_hw_pos = yscr << 16 | xscr;
 929         dcrtc->cursor_hw_sz = h << 16 | w;
 930         dcrtc->cursor_update = true;
 931         armada_drm_crtc_enable_irq(dcrtc, DUMB_FRAMEDONE_ENA);
 932         spin_unlock_irq(&dcrtc->irq_lock);
 933
 934         return 0;
 935 }
 936
 937 static void cursor_update(void *data)
 938 {
 939         armada_drm_crtc_cursor_update(data, true);
 940 }
 941
 942 static int armada_drm_crtc_cursor_set(struct drm_crtc *crtc,
 943         struct drm_file *file, uint32_t handle, uint32_t w, uint32_t h)
 944 {
 945         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 946         struct armada_gem_object *obj = NULL;
 947         int ret;
 948
 949         /* If no cursor support, replicate drm's return value */
 950         if (!dcrtc->variant->has_spu_adv_reg)
 951                 return -ENXIO;
 952
 953         if (handle && w > 0 && h > 0) {
 954                 /* maximum size is 64x32 or 32x64 */
 955                 if (w > 64 || h > 64 || (w > 32 && h > 32))
 956                         return -ENOMEM;
 957
 958                 obj = armada_gem_object_lookup(file, handle);
 959                 if (!obj)
 960                         return -ENOENT;
 961
 962                 /* Must be a kernel-mapped object */
 963                 if (!obj->addr) {
 964                         drm_gem_object_put_unlocked(&obj->obj);
 965                         return -EINVAL;
 966                 }
 967
 968                 if (obj->obj.size < w * h * 4) {
 969                         DRM_ERROR("buffer is too small\n");
 970                         drm_gem_object_put_unlocked(&obj->obj);
 971                         return -ENOMEM;
 972                 }
 973         }
 974
 975         if (dcrtc->cursor_obj) {
 976                 dcrtc->cursor_obj->update = NULL;
 977                 dcrtc->cursor_obj->update_data = NULL;
 978                 drm_gem_object_put_unlocked(&dcrtc->cursor_obj->obj);
 979         }
 980         dcrtc->cursor_obj = obj;
 981         dcrtc->cursor_w = w;
 982         dcrtc->cursor_h = h;
 983         ret = armada_drm_crtc_cursor_update(dcrtc, true);
 984         if (obj) {
 985                 obj->update_data = dcrtc;
 986                 obj->update = cursor_update;
 987         }
 988
 989         return ret;
 990 }
 991
 992 static int armada_drm_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
 993 {
 994         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 995         int ret;
 996
 997         /* If no cursor support, replicate drm's return value */
 998         if (!dcrtc->variant->has_spu_adv_reg)
 999                 return -EFAULT;
1000
1001         dcrtc->cursor_x = x;
1002         dcrtc->cursor_y = y;
1003         ret = armada_drm_crtc_cursor_update(dcrtc, false);
1004
1005         return ret;
1006 }
1007
1008 static void armada_drm_crtc_destroy(struct drm_crtc *crtc)
1009 {
1010         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
1011         struct armada_private *priv = crtc->dev->dev_private;
1012
1013         if (dcrtc->cursor_obj)
1014                 drm_gem_object_put_unlocked(&dcrtc->cursor_obj->obj);
1015
1016         priv->dcrtc[dcrtc->num] = NULL;
1017         drm_crtc_cleanup(&dcrtc->crtc);
1018
1019         if (!IS_ERR(dcrtc->clk))
1020                 clk_disable_unprepare(dcrtc->clk);
1021
1022         writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ENA);
1023
1024         of_node_put(dcrtc->crtc.port);
1025
1026         kfree(dcrtc);
1027 }
1028
1029 /*
1030  * The mode_config lock is held here, to prevent races between this
1031  * and a mode_set.
1032  */
1033 static int armada_drm_crtc_page_flip(struct drm_crtc *crtc,
1034         struct drm_framebuffer *fb, struct drm_pending_vblank_event *event, uint32_t page_flip_flags,
1035         struct drm_modeset_acquire_ctx *ctx)
1036 {
1037         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
1038         struct armada_plane_work *work;
1039         unsigned i;
1040         int ret;
1041
1042         /* We don't support changing the pixel format */
1043         if (fb->format != crtc->primary->fb->format)
1044                 return -EINVAL;
1045
1046         work = armada_drm_crtc_alloc_plane_work(dcrtc->crtc.primary);
1047         if (!work)
1048                 return -ENOMEM;
1049
1050         work->event = event;
1051         work->old_fb = dcrtc->crtc.primary->fb;
1052
1053         i = armada_drm_crtc_calc_fb(fb, crtc->x, crtc->y, work->regs,
1054                                     dcrtc->interlaced);
1055         armada_reg_queue_end(work->regs, i);
1056
1057         /*
1058          * Ensure that we hold a reference on the new framebuffer.
1059          * This has to match the behaviour in mode_set.
1060          */
1061         drm_framebuffer_get(fb);
1062
1063         ret = armada_drm_plane_work_queue(dcrtc, work);
1064         if (ret) {
1065                 /* Undo our reference above */
1066                 drm_framebuffer_put(fb);
1067                 kfree(work);
1068                 return ret;
1069         }
1070
1071         /*
1072          * Don't take a reference on the new framebuffer;
1073          * drm_mode_page_flip_ioctl() has already grabbed a reference and
1074          * will _not_ drop that reference on successful return from this
1075          * function.  Simply mark this new framebuffer as the current one.
1076          */
1077         dcrtc->crtc.primary->fb = fb;
1078
1079         /*
1080          * Finally, if the display is blanked, we won't receive an
1081          * interrupt, so complete it now.
1082          */
1083         if (dpms_blanked(dcrtc->dpms))
1084                 armada_drm_plane_work_run(dcrtc, dcrtc->crtc.primary);
1085
1086         return 0;
1087 }
1088
1089 static int
1090 armada_drm_crtc_set_property(struct drm_crtc *crtc,
1091         struct drm_property *property, uint64_t val)
1092 {
1093         struct armada_private *priv = crtc->dev->dev_private;
1094         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
1095         bool update_csc = false;
1096
1097         if (property == priv->csc_yuv_prop) {
1098                 dcrtc->csc_yuv_mode = val;
1099                 update_csc = true;
1100         } else if (property == priv->csc_rgb_prop) {
1101                 dcrtc->csc_rgb_mode = val;
1102                 update_csc = true;
1103         }
1104
1105         if (update_csc) {
1106                 uint32_t val;
1107
1108                 val = dcrtc->spu_iopad_ctrl |
1109                       armada_drm_crtc_calculate_csc(dcrtc);
1110                 writel_relaxed(val, dcrtc->base + LCD_SPU_IOPAD_CONTROL);
1111         }
1112
1113         return 0;
1114 }
1115
1116 /* These are called under the vbl_lock. */
1117 static int armada_drm_crtc_enable_vblank(struct drm_crtc *crtc)
1118 {
1119         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
1120         unsigned long flags;
1121
1122         spin_lock_irqsave(&dcrtc->irq_lock, flags);
1123         armada_drm_crtc_enable_irq(dcrtc, VSYNC_IRQ_ENA);
1124         spin_unlock_irqrestore(&dcrtc->irq_lock, flags);
1125         return 0;
1126 }
1127
1128 static void armada_drm_crtc_disable_vblank(struct drm_crtc *crtc)
1129 {
1130         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
1131         unsigned long flags;
1132
1133         spin_lock_irqsave(&dcrtc->irq_lock, flags);
1134         armada_drm_crtc_disable_irq(dcrtc, VSYNC_IRQ_ENA);
1135         spin_unlock_irqrestore(&dcrtc->irq_lock, flags);
1136 }
1137
1138 static const struct drm_crtc_funcs armada_crtc_funcs = {
1139         .cursor_set     = armada_drm_crtc_cursor_set,
1140         .cursor_move    = armada_drm_crtc_cursor_move,
1141         .destroy        = armada_drm_crtc_destroy,
1142         .set_config     = drm_crtc_helper_set_config,
1143         .page_flip      = armada_drm_crtc_page_flip,
1144         .set_property   = armada_drm_crtc_set_property,
1145         .enable_vblank  = armada_drm_crtc_enable_vblank,
1146         .disable_vblank = armada_drm_crtc_disable_vblank,
1147 };
1148
1149 static void armada_drm_primary_update_state(struct drm_plane_state *state,
1150         struct armada_regs *regs)
1151 {
1152         struct armada_plane *dplane = drm_to_armada_plane(state->plane);
1153         struct armada_crtc *dcrtc = drm_to_armada_crtc(state->crtc);
1154         struct armada_framebuffer *dfb = drm_fb_to_armada_fb(state->fb);
1155         bool was_disabled;
1156         unsigned int idx = 0;
1157         u32 val;
1158
1159         val = CFG_GRA_FMT(dfb->fmt) | CFG_GRA_MOD(dfb->mod);
1160         if (dfb->fmt > CFG_420)
1161                 val |= CFG_PALETTE_ENA;
1162         if (state->visible)
1163                 val |= CFG_GRA_ENA;
1164         if (drm_rect_width(&state->src) >> 16 != drm_rect_width(&state->dst))
1165                 val |= CFG_GRA_HSMOOTH;
1166
1167         was_disabled = !(dplane->state.ctrl0 & CFG_GRA_ENA);
1168         if (was_disabled)
1169                 armada_reg_queue_mod(regs, idx,
1170                                      0, CFG_PDWN64x66, LCD_SPU_SRAM_PARA1);
1171
1172         dplane->state.ctrl0 = val;
1173         dplane->state.src_hw = (drm_rect_height(&state->src) & 0xffff0000) |
1174                                 drm_rect_width(&state->src) >> 16;
1175         dplane->state.dst_hw = drm_rect_height(&state->dst) << 16 |
1176                                drm_rect_width(&state->dst);
1177         dplane->state.dst_yx = state->dst.y1 << 16 | state->dst.x1;
1178
1179         armada_drm_gra_plane_regs(regs + idx, &dfb->fb, &dplane->state,
1180                                   state->src.x1 >> 16, state->src.y1 >> 16,
1181                                   dcrtc->interlaced);
1182
1183         dplane->state.vsync_update = !was_disabled;
1184         dplane->state.changed = true;
1185 }
1186
1187 static int armada_drm_primary_update(struct drm_plane *plane,
1188         struct drm_crtc *crtc, struct drm_framebuffer *fb,
1189         int crtc_x, int crtc_y, unsigned int crtc_w, unsigned int crtc_h,
1190         uint32_t src_x, uint32_t src_y, uint32_t src_w, uint32_t src_h,
1191         struct drm_modeset_acquire_ctx *ctx)
1192 {
1193         struct armada_plane *dplane = drm_to_armada_plane(plane);
1194         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
1195         struct armada_plane_work *work;
1196         struct drm_plane_state state = {
1197                 .plane = plane,
1198                 .crtc = crtc,
1199                 .fb = fb,
1200                 .src_x = src_x,
1201                 .src_y = src_y,
1202                 .src_w = src_w,
1203                 .src_h = src_h,
1204                 .crtc_x = crtc_x,
1205                 .crtc_y = crtc_y,
1206                 .crtc_w = crtc_w,
1207                 .crtc_h = crtc_h,
1208                 .rotation = DRM_MODE_ROTATE_0,
1209         };
1210         struct drm_crtc_state crtc_state = {
1211                 .crtc = crtc,
1212                 .enable = crtc->enabled,
1213                 .mode = crtc->mode,
1214         };
1215         int ret;
1216
1217         ret = drm_atomic_helper_check_plane_state(&state, &crtc_state, 0,
1218                                                   INT_MAX, true, false);
1219         if (ret)
1220                 return ret;
1221
1222         work = &dplane->works[dplane->next_work];
1223         work->fn = armada_drm_crtc_complete_frame_work;
1224
1225         if (plane->fb != fb) {
1226                 /*
1227                  * Take a reference on the new framebuffer - we want to
1228                  * hold on to it while the hardware is displaying it.
1229                  */
1230                 drm_framebuffer_reference(fb);
1231
1232                 work->old_fb = plane->fb;
1233         } else {
1234                 work->old_fb = NULL;
1235         }
1236
1237         armada_drm_primary_update_state(&state, work->regs);
1238
1239         if (!dplane->state.changed)
1240                 return 0;
1241
1242         /* Wait for pending work to complete */
1243         if (armada_drm_plane_work_wait(dplane, HZ / 10) == 0)
1244                 armada_drm_plane_work_cancel(dcrtc, dplane);
1245
1246         if (!dplane->state.vsync_update) {
1247                 work->fn(dcrtc, work);
1248                 if (work->old_fb)
1249                         drm_framebuffer_unreference(work->old_fb);
1250                 return 0;
1251         }
1252
1253         /* Queue it for update on the next interrupt if we are enabled */
1254         ret = armada_drm_plane_work_queue(dcrtc, work);
1255         if (ret) {
1256                 work->fn(dcrtc, work);
1257                 if (work->old_fb)
1258                         drm_framebuffer_unreference(work->old_fb);
1259         }
1260
1261         dplane->next_work = !dplane->next_work;
1262
1263         return 0;
1264 }
1265
1266 int armada_drm_plane_disable(struct drm_plane *plane,
1267                              struct drm_modeset_acquire_ctx *ctx)
1268 {
1269         struct armada_plane *dplane = drm_to_armada_plane(plane);
1270         struct armada_crtc *dcrtc;
1271         struct armada_plane_work *work;
1272         unsigned int idx = 0;
1273         u32 sram_para1, enable_mask;
1274
1275         if (!plane->crtc)
1276                 return 0;
1277
1278         /*
1279          * Arrange to power down most RAMs and FIFOs if this is the primary
1280          * plane, otherwise just the YUV FIFOs for the overlay plane.
1281          */
1282         if (plane->type == DRM_PLANE_TYPE_PRIMARY) {
1283                 sram_para1 = CFG_PDWN256x32 | CFG_PDWN256x24 | CFG_PDWN256x8 |
1284                              CFG_PDWN32x32 | CFG_PDWN64x66;
1285                 enable_mask = CFG_GRA_ENA;
1286         } else {
1287                 sram_para1 = CFG_PDWN16x66 | CFG_PDWN32x66;
1288                 enable_mask = CFG_DMA_ENA;
1289         }
1290
1291         dplane->state.ctrl0 &= ~enable_mask;
1292
1293         dcrtc = drm_to_armada_crtc(plane->crtc);
1294
1295         /*
1296          * Try to disable the plane and drop our ref on the framebuffer
1297          * at the next frame update. If we fail for any reason, disable
1298          * the plane immediately.
1299          */
1300         work = &dplane->works[dplane->next_work];
1301         work->fn = armada_drm_crtc_complete_disable_work;
1302         work->cancel = armada_drm_crtc_complete_disable_work;
1303         work->old_fb = plane->fb;
1304
1305         armada_reg_queue_mod(work->regs, idx,
1306                              0, enable_mask, LCD_SPU_DMA_CTRL0);
1307         armada_reg_queue_mod(work->regs, idx,
1308                              sram_para1, 0, LCD_SPU_SRAM_PARA1);
1309         armada_reg_queue_end(work->regs, idx);
1310
1311         /* Wait for any preceding work to complete, but don't wedge */
1312         if (WARN_ON(!armada_drm_plane_work_wait(dplane, HZ)))
1313                 armada_drm_plane_work_cancel(dcrtc, dplane);
1314
1315         if (armada_drm_plane_work_queue(dcrtc, work)) {
1316                 work->fn(dcrtc, work);
1317                 if (work->old_fb)
1318                         drm_framebuffer_unreference(work->old_fb);
1319         }
1320
1321         dplane->next_work = !dplane->next_work;
1322
1323         return 0;
1324 }
1325
1326 static const struct drm_plane_funcs armada_primary_plane_funcs = {
1327         .update_plane   = armada_drm_primary_update,
1328         .disable_plane  = armada_drm_plane_disable,
1329         .destroy        = drm_primary_helper_destroy,
1330 };
1331
1332 int armada_drm_plane_init(struct armada_plane *plane)
1333 {
1334         unsigned int i;
1335
1336         for (i = 0; i < ARRAY_SIZE(plane->works); i++)
1337                 plane->works[i].plane = &plane->base;
1338
1339         init_waitqueue_head(&plane->frame_wait);
1340
1341         return 0;
1342 }
1343
1344 static const struct drm_prop_enum_list armada_drm_csc_yuv_enum_list[] = {
1345         { CSC_AUTO,        "Auto" },
1346         { CSC_YUV_CCIR601, "CCIR601" },
1347         { CSC_YUV_CCIR709, "CCIR709" },
1348 };
1349
1350 static const struct drm_prop_enum_list armada_drm_csc_rgb_enum_list[] = {
1351         { CSC_AUTO,         "Auto" },
1352         { CSC_RGB_COMPUTER, "Computer system" },
1353         { CSC_RGB_STUDIO,   "Studio" },
1354 };
1355
1356 static int armada_drm_crtc_create_properties(struct drm_device *dev)
1357 {
1358         struct armada_private *priv = dev->dev_private;
1359
1360         if (priv->csc_yuv_prop)
1361                 return 0;
1362
1363         priv->csc_yuv_prop = drm_property_create_enum(dev, 0,
1364                                 "CSC_YUV", armada_drm_csc_yuv_enum_list,
1365                                 ARRAY_SIZE(armada_drm_csc_yuv_enum_list));
1366         priv->csc_rgb_prop = drm_property_create_enum(dev, 0,
1367                                 "CSC_RGB", armada_drm_csc_rgb_enum_list,
1368                                 ARRAY_SIZE(armada_drm_csc_rgb_enum_list));
1369
1370         if (!priv->csc_yuv_prop || !priv->csc_rgb_prop)
1371                 return -ENOMEM;
1372
1373         return 0;
1374 }
1375
1376 static int armada_drm_crtc_create(struct drm_device *drm, struct device *dev,
1377         struct resource *res, int irq, const struct armada_variant *variant,
1378         struct device_node *port)
1379 {
1380         struct armada_private *priv = drm->dev_private;
1381         struct armada_crtc *dcrtc;
1382         struct armada_plane *primary;
1383         void __iomem *base;
1384         int ret;
1385
1386         ret = armada_drm_crtc_create_properties(drm);
1387         if (ret)
1388                 return ret;
1389
1390         base = devm_ioremap_resource(dev, res);
1391         if (IS_ERR(base))
1392                 return PTR_ERR(base);
1393
1394         dcrtc = kzalloc(sizeof(*dcrtc), GFP_KERNEL);
1395         if (!dcrtc) {
1396                 DRM_ERROR("failed to allocate Armada crtc\n");
1397                 return -ENOMEM;
1398         }
1399
1400         if (dev != drm->dev)
1401                 dev_set_drvdata(dev, dcrtc);
1402
1403         dcrtc->variant = variant;
1404         dcrtc->base = base;
1405         dcrtc->num = drm->mode_config.num_crtc;
1406         dcrtc->clk = ERR_PTR(-EINVAL);
1407         dcrtc->csc_yuv_mode = CSC_AUTO;
1408         dcrtc->csc_rgb_mode = CSC_AUTO;
1409         dcrtc->cfg_dumb_ctrl = DUMB24_RGB888_0;
1410         dcrtc->spu_iopad_ctrl = CFG_VSCALE_LN_EN | CFG_IOPAD_DUMB24;
1411         spin_lock_init(&dcrtc->irq_lock);
1412         dcrtc->irq_ena = CLEAN_SPU_IRQ_ISR;
1413
1414         /* Initialize some registers which we don't otherwise set */
1415         writel_relaxed(0x00000001, dcrtc->base + LCD_CFG_SCLK_DIV);
1416         writel_relaxed(0x00000000, dcrtc->base + LCD_SPU_BLANKCOLOR);
1417         writel_relaxed(dcrtc->spu_iopad_ctrl,
1418                        dcrtc->base + LCD_SPU_IOPAD_CONTROL);
1419         writel_relaxed(0x00000000, dcrtc->base + LCD_SPU_SRAM_PARA0);
1420         writel_relaxed(CFG_PDWN256x32 | CFG_PDWN256x24 | CFG_PDWN256x8 |
1421                        CFG_PDWN32x32 | CFG_PDWN16x66 | CFG_PDWN32x66 |
1422                        CFG_PDWN64x66, dcrtc->base + LCD_SPU_SRAM_PARA1);
1423         writel_relaxed(0x2032ff81, dcrtc->base + LCD_SPU_DMA_CTRL1);
1424         writel_relaxed(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA);
1425         readl_relaxed(dcrtc->base + LCD_SPU_IRQ_ISR);
1426         writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ISR);
1427
1428         ret = devm_request_irq(dev, irq, armada_drm_irq, 0, "armada_drm_crtc",
1429                                dcrtc);
1430         if (ret < 0)
1431                 goto err_crtc;
1432
1433         if (dcrtc->variant->init) {
1434                 ret = dcrtc->variant->init(dcrtc, dev);
1435                 if (ret)
1436                         goto err_crtc;
1437         }
1438
1439         /* Ensure AXI pipeline is enabled */
1440         armada_updatel(CFG_ARBFAST_ENA, 0, dcrtc->base + LCD_SPU_DMA_CTRL0);
1441
1442         priv->dcrtc[dcrtc->num] = dcrtc;
1443
1444         dcrtc->crtc.port = port;
1445
1446         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
1447         if (!primary) {
1448                 ret = -ENOMEM;
1449                 goto err_crtc;
1450         }
1451
1452         ret = armada_drm_plane_init(primary);
1453         if (ret) {
1454                 kfree(primary);
1455                 goto err_crtc;
1456         }
1457
1458         ret = drm_universal_plane_init(drm, &primary->base, 0,
1459                                        &armada_primary_plane_funcs,
1460                                        armada_primary_formats,
1461                                        ARRAY_SIZE(armada_primary_formats),
1462                                        NULL,
1463                                        DRM_PLANE_TYPE_PRIMARY, NULL);
1464         if (ret) {
1465                 kfree(primary);
1466                 goto err_crtc;
1467         }
1468
1469         ret = drm_crtc_init_with_planes(drm, &dcrtc->crtc, &primary->base, NULL,
1470                                         &armada_crtc_funcs, NULL);
1471         if (ret)
1472                 goto err_crtc_init;
1473
1474         drm_crtc_helper_add(&dcrtc->crtc, &armada_crtc_helper_funcs);
1475
1476         drm_object_attach_property(&dcrtc->crtc.base, priv->csc_yuv_prop,
1477                                    dcrtc->csc_yuv_mode);
1478         drm_object_attach_property(&dcrtc->crtc.base, priv->csc_rgb_prop,
1479                                    dcrtc->csc_rgb_mode);
1480
1481         return armada_overlay_plane_create(drm, 1 << dcrtc->num);
1482
1483 err_crtc_init:
1484         primary->base.funcs->destroy(&primary->base);
1485 err_crtc:
1486         kfree(dcrtc);
1487
1488         return ret;
1489 }
1490
1491 static int
1492 armada_lcd_bind(struct device *dev, struct device *master, void *data)
1493 {
1494         struct platform_device *pdev = to_platform_device(dev);
1495         struct drm_device *drm = data;
1496         struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1497         int irq = platform_get_irq(pdev, 0);
1498         const struct armada_variant *variant;
1499         struct device_node *port = NULL;
1500
1501         if (irq < 0)
1502                 return irq;
1503
1504         if (!dev->of_node) {
1505                 const struct platform_device_id *id;
1506
1507                 id = platform_get_device_id(pdev);
1508                 if (!id)
1509                         return -ENXIO;
1510
1511                 variant = (const struct armada_variant *)id->driver_data;
1512         } else {
1513                 const struct of_device_id *match;
1514                 struct device_node *np, *parent = dev->of_node;
1515
1516                 match = of_match_device(dev->driver->of_match_table, dev);
1517                 if (!match)
1518                         return -ENXIO;
1519
1520                 np = of_get_child_by_name(parent, "ports");
1521                 if (np)
1522                         parent = np;
1523                 port = of_get_child_by_name(parent, "port");
1524                 of_node_put(np);
1525                 if (!port) {
1526                         dev_err(dev, "no port node found in %pOF\n", parent);
1527                         return -ENXIO;
1528                 }
1529
1530                 variant = match->data;
1531         }
1532
1533         return armada_drm_crtc_create(drm, dev, res, irq, variant, port);
1534 }
1535
1536 static void
1537 armada_lcd_unbind(struct device *dev, struct device *master, void *data)
1538 {
1539         struct armada_crtc *dcrtc = dev_get_drvdata(dev);
1540
1541         armada_drm_crtc_destroy(&dcrtc->crtc);
1542 }
1543
1544 static const struct component_ops armada_lcd_ops = {
1545         .bind = armada_lcd_bind,
1546         .unbind = armada_lcd_unbind,
1547 };
1548
1549 static int armada_lcd_probe(struct platform_device *pdev)
1550 {
1551         return component_add(&pdev->dev, &armada_lcd_ops);
1552 }
1553
1554 static int armada_lcd_remove(struct platform_device *pdev)
1555 {
1556         component_del(&pdev->dev, &armada_lcd_ops);
1557         return 0;
1558 }
1559
1560 static const struct of_device_id armada_lcd_of_match[] = {
1561         {
1562                 .compatible     = "marvell,dove-lcd",
1563                 .data           = &armada510_ops,
1564         },
1565         {}
1566 };
1567 MODULE_DEVICE_TABLE(of, armada_lcd_of_match);
1568
1569 static const struct platform_device_id armada_lcd_platform_ids[] = {
1570         {
1571                 .name           = "armada-lcd",
1572                 .driver_data    = (unsigned long)&armada510_ops,
1573         }, {
1574                 .name           = "armada-510-lcd",
1575                 .driver_data    = (unsigned long)&armada510_ops,
1576         },
1577         { },
1578 };
1579 MODULE_DEVICE_TABLE(platform, armada_lcd_platform_ids);
1580
1581 struct platform_driver armada_lcd_platform_driver = {
1582         .probe  = armada_lcd_probe,
1583         .remove = armada_lcd_remove,
1584         .driver = {
1585                 .name   = "armada-lcd",
1586                 .owner  =  THIS_MODULE,
1587                 .of_match_table = armada_lcd_of_match,
1588         },
1589         .id_table = armada_lcd_platform_ids,
1590 };