drivers/gpu/drm/armada/armada_crtc.c

   1 /*
   2  * Copyright (C) 2012 Russell King
   3  *  Rewritten from the dovefb driver, and Armada510 manuals.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  */
   9 #include <linux/clk.h>
  10 #include <linux/component.h>
  11 #include <linux/of_device.h>
  12 #include <linux/platform_device.h>
  13 #include <drm/drmP.h>
  14 #include <drm/drm_atomic.h>
  15 #include <drm/drm_crtc_helper.h>
  16 #include <drm/drm_plane_helper.h>
  17 #include <drm/drm_atomic_helper.h>
  18 #include "armada_crtc.h"
  19 #include "armada_drm.h"
  20 #include "armada_fb.h"
  21 #include "armada_gem.h"
  22 #include "armada_hw.h"
  23 #include "armada_trace.h"
  24
  25 enum csc_mode {
  26         CSC_AUTO = 0,
  27         CSC_YUV_CCIR601 = 1,
  28         CSC_YUV_CCIR709 = 2,
  29         CSC_RGB_COMPUTER = 1,
  30         CSC_RGB_STUDIO = 2,
  31 };
  32
  33 static const uint32_t armada_primary_formats[] = {
  34         DRM_FORMAT_UYVY,
  35         DRM_FORMAT_YUYV,
  36         DRM_FORMAT_VYUY,
  37         DRM_FORMAT_YVYU,
  38         DRM_FORMAT_ARGB8888,
  39         DRM_FORMAT_ABGR8888,
  40         DRM_FORMAT_XRGB8888,
  41         DRM_FORMAT_XBGR8888,
  42         DRM_FORMAT_RGB888,
  43         DRM_FORMAT_BGR888,
  44         DRM_FORMAT_ARGB1555,
  45         DRM_FORMAT_ABGR1555,
  46         DRM_FORMAT_RGB565,
  47         DRM_FORMAT_BGR565,
  48 };
  49
  50 /*
  51  * A note about interlacing.  Let's consider HDMI 1920x1080i.
  52  * The timing parameters we have from X are:
  53  *  Hact HsyA HsyI Htot  Vact VsyA VsyI Vtot
  54  *  1920 2448 2492 2640  1080 1084 1094 1125
  55  * Which get translated to:
  56  *  Hact HsyA HsyI Htot  Vact VsyA VsyI Vtot
  57  *  1920 2448 2492 2640   540  542  547  562
  58  *
  59  * This is how it is defined by CEA-861-D - line and pixel numbers are
  60  * referenced to the rising edge of VSYNC and HSYNC.  Total clocks per
  61  * line: 2640.  The odd frame, the first active line is at line 21, and
  62  * the even frame, the first active line is 584.
  63  *
  64  * LN:    560     561     562     563             567     568    569
  65  * DE:    ~~~|____________________________//__________________________
  66  * HSYNC: ____|~|_____|~|_____|~|_____|~|_//__|~|_____|~|_____|~|_____
  67  * VSYNC: _________________________|~~~~~~//~~~~~~~~~~~~~~~|__________
  68  *  22 blanking lines.  VSYNC at 1320 (referenced to the HSYNC rising edge).
  69  *
  70  * LN:    1123   1124    1125      1               5       6      7
  71  * DE:    ~~~|____________________________//__________________________
  72  * HSYNC: ____|~|_____|~|_____|~|_____|~|_//__|~|_____|~|_____|~|_____
  73  * VSYNC: ____________________|~~~~~~~~~~~//~~~~~~~~~~|_______________
  74  *  23 blanking lines
  75  *
  76  * The Armada LCD Controller line and pixel numbers are, like X timings,
  77  * referenced to the top left of the active frame.
  78  *
  79  * So, translating these to our LCD controller:
  80  *  Odd frame, 563 total lines, VSYNC at line 543-548, pixel 1128.
  81  *  Even frame, 562 total lines, VSYNC at line 542-547, pixel 2448.
  82  * Note: Vsync front porch remains constant!
  83  *
  84  * if (odd_frame) {
  85  *   vtotal = mode->crtc_vtotal + 1;
  86  *   vbackporch = mode->crtc_vsync_start - mode->crtc_vdisplay + 1;
  87  *   vhorizpos = mode->crtc_hsync_start - mode->crtc_htotal / 2
  88  * } else {
  89  *   vtotal = mode->crtc_vtotal;
  90  *   vbackporch = mode->crtc_vsync_start - mode->crtc_vdisplay;
  91  *   vhorizpos = mode->crtc_hsync_start;
  92  * }
  93  * vfrontporch = mode->crtc_vtotal - mode->crtc_vsync_end;
  94  *
  95  * So, we need to reprogram these registers on each vsync event:
  96  *  LCD_SPU_V_PORCH, LCD_SPU_ADV_REG, LCD_SPUT_V_H_TOTAL
  97  *
  98  * Note: we do not use the frame done interrupts because these appear
  99  * to happen too early, and lead to jitter on the display (presumably
 100  * they occur at the end of the last active line, before the vsync back
 101  * porch, which we're reprogramming.)
 102  */
 103
 104 void
 105 armada_drm_crtc_update_regs(struct armada_crtc *dcrtc, struct armada_regs *regs)
 106 {
 107         while (regs->offset != ~0) {
 108                 void __iomem *reg = dcrtc->base + regs->offset;
 109                 uint32_t val;
 110
 111                 val = regs->mask;
 112                 if (val != 0)
 113                         val &= readl_relaxed(reg);
 114                 writel_relaxed(val | regs->val, reg);
 115                 ++regs;
 116         }
 117 }
 118
 119 #define dpms_blanked(dpms)      ((dpms) != DRM_MODE_DPMS_ON)
 120
 121 static void armada_drm_crtc_update(struct armada_crtc *dcrtc)
 122 {
 123         uint32_t dumb_ctrl;
 124
 125         dumb_ctrl = dcrtc->cfg_dumb_ctrl;
 126
 127         if (!dpms_blanked(dcrtc->dpms))
 128                 dumb_ctrl |= CFG_DUMB_ENA;
 129
 130         /*
 131          * When the dumb interface isn't in DUMB24_RGB888_0 mode, it might
 132          * be using SPI or GPIO.  If we set this to DUMB_BLANK, we will
 133          * force LCD_D[23:0] to output blank color, overriding the GPIO or
 134          * SPI usage.  So leave it as-is unless in DUMB24_RGB888_0 mode.
 135          */
 136         if (dpms_blanked(dcrtc->dpms) &&
 137             (dumb_ctrl & DUMB_MASK) == DUMB24_RGB888_0) {
 138                 dumb_ctrl &= ~DUMB_MASK;
 139                 dumb_ctrl |= DUMB_BLANK;
 140         }
 141
 142         /*
 143          * The documentation doesn't indicate what the normal state of
 144          * the sync signals are.  Sebastian Hesselbart kindly probed
 145          * these signals on his board to determine their state.
 146          *
 147          * The non-inverted state of the sync signals is active high.
 148          * Setting these bits makes the appropriate signal active low.
 149          */
 150         if (dcrtc->crtc.mode.flags & DRM_MODE_FLAG_NCSYNC)
 151                 dumb_ctrl |= CFG_INV_CSYNC;
 152         if (dcrtc->crtc.mode.flags & DRM_MODE_FLAG_NHSYNC)
 153                 dumb_ctrl |= CFG_INV_HSYNC;
 154         if (dcrtc->crtc.mode.flags & DRM_MODE_FLAG_NVSYNC)
 155                 dumb_ctrl |= CFG_INV_VSYNC;
 156
 157         if (dcrtc->dumb_ctrl != dumb_ctrl) {
 158                 dcrtc->dumb_ctrl = dumb_ctrl;
 159                 writel_relaxed(dumb_ctrl, dcrtc->base + LCD_SPU_DUMB_CTRL);
 160         }
 161 }
 162
 163 void armada_drm_plane_calc_addrs(u32 *addrs, struct drm_framebuffer *fb,
 164         int x, int y)
 165 {
 166         const struct drm_format_info *format = fb->format;
 167         unsigned int num_planes = format->num_planes;
 168         u32 addr = drm_fb_obj(fb)->dev_addr;
 169         int i;
 170
 171         if (num_planes > 3)
 172                 num_planes = 3;
 173
 174         addrs[0] = addr + fb->offsets[0] + y * fb->pitches[0] +
 175                    x * format->cpp[0];
 176
 177         y /= format->vsub;
 178         x /= format->hsub;
 179
 180         for (i = 1; i < num_planes; i++)
 181                 addrs[i] = addr + fb->offsets[i] + y * fb->pitches[i] +
 182                              x * format->cpp[i];
 183         for (; i < 3; i++)
 184                 addrs[i] = 0;
 185 }
 186
 187 static unsigned armada_drm_crtc_calc_fb(struct drm_framebuffer *fb,
 188         int x, int y, struct armada_regs *regs, bool interlaced)
 189 {
 190         unsigned pitch = fb->pitches[0];
 191         u32 addrs[3], addr_odd, addr_even;
 192         unsigned i = 0;
 193
 194         DRM_DEBUG_DRIVER("pitch %u x %d y %d bpp %d\n",
 195                 pitch, x, y, fb->format->cpp[0] * 8);
 196
 197         armada_drm_plane_calc_addrs(addrs, fb, x, y);
 198
 199         addr_odd = addr_even = addrs[0];
 200
 201         if (interlaced) {
 202                 addr_even += pitch;
 203                 pitch *= 2;
 204         }
 205
 206         /* write offset, base, and pitch */
 207         armada_reg_queue_set(regs, i, addr_odd, LCD_CFG_GRA_START_ADDR0);
 208         armada_reg_queue_set(regs, i, addr_even, LCD_CFG_GRA_START_ADDR1);
 209         armada_reg_queue_mod(regs, i, pitch, 0xffff, LCD_CFG_GRA_PITCH);
 210
 211         return i;
 212 }
 213
 214 static void armada_drm_plane_work_call(struct armada_crtc *dcrtc,
 215         struct armada_plane_work *work,
 216         void (*fn)(struct armada_crtc *, struct armada_plane_work *))
 217 {
 218         struct armada_plane *dplane = drm_to_armada_plane(work->plane);
 219         struct drm_pending_vblank_event *event;
 220         struct drm_framebuffer *fb;
 221
 222         if (fn)
 223                 fn(dcrtc, work);
 224         drm_crtc_vblank_put(&dcrtc->crtc);
 225
 226         event = work->event;
 227         fb = work->old_fb;
 228         if (event || fb) {
 229                 struct drm_device *dev = dcrtc->crtc.dev;
 230                 unsigned long flags;
 231
 232                 spin_lock_irqsave(&dev->event_lock, flags);
 233                 if (event)
 234                         drm_crtc_send_vblank_event(&dcrtc->crtc, event);
 235                 if (fb)
 236                         __armada_drm_queue_unref_work(dev, fb);
 237                 spin_unlock_irqrestore(&dev->event_lock, flags);
 238         }
 239
 240         if (work->need_kfree)
 241                 kfree(work);
 242
 243         wake_up(&dplane->frame_wait);
 244 }
 245
 246 static void armada_drm_plane_work_run(struct armada_crtc *dcrtc,
 247         struct drm_plane *plane)
 248 {
 249         struct armada_plane *dplane = drm_to_armada_plane(plane);
 250         struct armada_plane_work *work = xchg(&dplane->work, NULL);
 251
 252         /* Handle any pending frame work. */
 253         if (work)
 254                 armada_drm_plane_work_call(dcrtc, work, work->fn);
 255 }
 256
 257 int armada_drm_plane_work_queue(struct armada_crtc *dcrtc,
 258         struct armada_plane_work *work)
 259 {
 260         struct armada_plane *plane = drm_to_armada_plane(work->plane);
 261         int ret;
 262
 263         ret = drm_crtc_vblank_get(&dcrtc->crtc);
 264         if (ret)
 265                 return ret;
 266
 267         ret = cmpxchg(&plane->work, NULL, work) ? -EBUSY : 0;
 268         if (ret)
 269                 drm_crtc_vblank_put(&dcrtc->crtc);
 270
 271         return ret;
 272 }
 273
 274 int armada_drm_plane_work_wait(struct armada_plane *plane, long timeout)
 275 {
 276         return wait_event_timeout(plane->frame_wait, !plane->work, timeout);
 277 }
 278
 279 void armada_drm_plane_work_cancel(struct armada_crtc *dcrtc,
 280         struct armada_plane *dplane)
 281 {
 282         struct armada_plane_work *work = xchg(&dplane->work, NULL);
 283
 284         if (work)
 285                 armada_drm_plane_work_call(dcrtc, work, work->cancel);
 286 }
 287
 288 static void armada_drm_crtc_complete_frame_work(struct armada_crtc *dcrtc,
 289         struct armada_plane_work *work)
 290 {
 291         unsigned long flags;
 292
 293         spin_lock_irqsave(&dcrtc->irq_lock, flags);
 294         armada_drm_crtc_update_regs(dcrtc, work->regs);
 295         spin_unlock_irqrestore(&dcrtc->irq_lock, flags);
 296 }
 297
 298 static struct armada_plane_work *
 299 armada_drm_crtc_alloc_plane_work(struct drm_plane *plane)
 300 {
 301         struct armada_plane_work *work;
 302         int i = 0;
 303
 304         work = kzalloc(sizeof(*work), GFP_KERNEL);
 305         if (!work)
 306                 return NULL;
 307
 308         work->plane = plane;
 309         work->fn = armada_drm_crtc_complete_frame_work;
 310         work->need_kfree = true;
 311         armada_reg_queue_end(work->regs, i);
 312
 313         return work;
 314 }
 315
 316 static void armada_drm_vblank_off(struct armada_crtc *dcrtc)
 317 {
 318         /*
 319          * Tell the DRM core that vblank IRQs aren't going to happen for
 320          * a while.  This cleans up any pending vblank events for us.
 321          */
 322         drm_crtc_vblank_off(&dcrtc->crtc);
 323         armada_drm_plane_work_run(dcrtc, dcrtc->crtc.primary);
 324 }
 325
 326 /* The mode_config.mutex will be held for this call */
 327 static void armada_drm_crtc_dpms(struct drm_crtc *crtc, int dpms)
 328 {
 329         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 330
 331         if (dpms_blanked(dcrtc->dpms) != dpms_blanked(dpms)) {
 332                 if (dpms_blanked(dpms))
 333                         armada_drm_vblank_off(dcrtc);
 334                 else if (!IS_ERR(dcrtc->clk))
 335                         WARN_ON(clk_prepare_enable(dcrtc->clk));
 336                 dcrtc->dpms = dpms;
 337                 armada_drm_crtc_update(dcrtc);
 338                 if (!dpms_blanked(dpms))
 339                         drm_crtc_vblank_on(&dcrtc->crtc);
 340                 else if (!IS_ERR(dcrtc->clk))
 341                         clk_disable_unprepare(dcrtc->clk);
 342         } else if (dcrtc->dpms != dpms) {
 343                 dcrtc->dpms = dpms;
 344         }
 345 }
 346
 347 /*
 348  * Prepare for a mode set.  Turn off overlay to ensure that we don't end
 349  * up with the overlay size being bigger than the active screen size.
 350  * We rely upon X refreshing this state after the mode set has completed.
 351  *
 352  * The mode_config.mutex will be held for this call
 353  */
 354 static void armada_drm_crtc_prepare(struct drm_crtc *crtc)
 355 {
 356         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 357         struct drm_plane *plane;
 358         u32 val;
 359
 360         /*
 361          * If we have an overlay plane associated with this CRTC, disable
 362          * it before the modeset to avoid its coordinates being outside
 363          * the new mode parameters.
 364          */
 365         plane = dcrtc->plane;
 366         if (plane) {
 367                 drm_plane_force_disable(plane);
 368                 WARN_ON(!armada_drm_plane_work_wait(drm_to_armada_plane(plane),
 369                                                     HZ));
 370         }
 371
 372         /* Wait for pending flips to complete */
 373         armada_drm_plane_work_wait(drm_to_armada_plane(dcrtc->crtc.primary),
 374                                    MAX_SCHEDULE_TIMEOUT);
 375
 376         drm_crtc_vblank_off(crtc);
 377
 378         val = dcrtc->dumb_ctrl & ~CFG_DUMB_ENA;
 379         if (val != dcrtc->dumb_ctrl) {
 380                 dcrtc->dumb_ctrl = val;
 381                 writel_relaxed(val, dcrtc->base + LCD_SPU_DUMB_CTRL);
 382         }
 383 }
 384
 385 /* The mode_config.mutex will be held for this call */
 386 static void armada_drm_crtc_commit(struct drm_crtc *crtc)
 387 {
 388         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 389
 390         dcrtc->dpms = DRM_MODE_DPMS_ON;
 391         armada_drm_crtc_update(dcrtc);
 392         drm_crtc_vblank_on(crtc);
 393 }
 394
 395 /* The mode_config.mutex will be held for this call */
 396 static bool armada_drm_crtc_mode_fixup(struct drm_crtc *crtc,
 397         const struct drm_display_mode *mode, struct drm_display_mode *adj)
 398 {
 399         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 400         int ret;
 401
 402         /* We can't do interlaced modes if we don't have the SPU_ADV_REG */
 403         if (!dcrtc->variant->has_spu_adv_reg &&
 404             adj->flags & DRM_MODE_FLAG_INTERLACE)
 405                 return false;
 406
 407         /* Check whether the display mode is possible */
 408         ret = dcrtc->variant->compute_clock(dcrtc, adj, NULL);
 409         if (ret)
 410                 return false;
 411
 412         return true;
 413 }
 414
 415 /* These are locked by dev->vbl_lock */
 416 static void armada_drm_crtc_disable_irq(struct armada_crtc *dcrtc, u32 mask)
 417 {
 418         if (dcrtc->irq_ena & mask) {
 419                 dcrtc->irq_ena &= ~mask;
 420                 writel(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA);
 421         }
 422 }
 423
 424 static void armada_drm_crtc_enable_irq(struct armada_crtc *dcrtc, u32 mask)
 425 {
 426         if ((dcrtc->irq_ena & mask) != mask) {
 427                 dcrtc->irq_ena |= mask;
 428                 writel(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA);
 429                 if (readl_relaxed(dcrtc->base + LCD_SPU_IRQ_ISR) & mask)
 430                         writel(0, dcrtc->base + LCD_SPU_IRQ_ISR);
 431         }
 432 }
 433
 434 static void armada_drm_crtc_irq(struct armada_crtc *dcrtc, u32 stat)
 435 {
 436         void __iomem *base = dcrtc->base;
 437         struct drm_plane *ovl_plane;
 438
 439         if (stat & DMA_FF_UNDERFLOW)
 440                 DRM_ERROR("video underflow on crtc %u\n", dcrtc->num);
 441         if (stat & GRA_FF_UNDERFLOW)
 442                 DRM_ERROR("graphics underflow on crtc %u\n", dcrtc->num);
 443
 444         if (stat & VSYNC_IRQ)
 445                 drm_crtc_handle_vblank(&dcrtc->crtc);
 446
 447         ovl_plane = dcrtc->plane;
 448         if (ovl_plane)
 449                 armada_drm_plane_work_run(dcrtc, ovl_plane);
 450
 451         spin_lock(&dcrtc->irq_lock);
 452         if (stat & GRA_FRAME_IRQ && dcrtc->interlaced) {
 453                 int i = stat & GRA_FRAME_IRQ0 ? 0 : 1;
 454                 uint32_t val;
 455
 456                 writel_relaxed(dcrtc->v[i].spu_v_porch, base + LCD_SPU_V_PORCH);
 457                 writel_relaxed(dcrtc->v[i].spu_v_h_total,
 458                                base + LCD_SPUT_V_H_TOTAL);
 459
 460                 val = readl_relaxed(base + LCD_SPU_ADV_REG);
 461                 val &= ~(ADV_VSYNC_L_OFF | ADV_VSYNC_H_OFF | ADV_VSYNCOFFEN);
 462                 val |= dcrtc->v[i].spu_adv_reg;
 463                 writel_relaxed(val, base + LCD_SPU_ADV_REG);
 464         }
 465
 466         if (stat & DUMB_FRAMEDONE && dcrtc->cursor_update) {
 467                 writel_relaxed(dcrtc->cursor_hw_pos,
 468                                base + LCD_SPU_HWC_OVSA_HPXL_VLN);
 469                 writel_relaxed(dcrtc->cursor_hw_sz,
 470                                base + LCD_SPU_HWC_HPXL_VLN);
 471                 armada_updatel(CFG_HWC_ENA,
 472                                CFG_HWC_ENA | CFG_HWC_1BITMOD | CFG_HWC_1BITENA,
 473                                base + LCD_SPU_DMA_CTRL0);
 474                 dcrtc->cursor_update = false;
 475                 armada_drm_crtc_disable_irq(dcrtc, DUMB_FRAMEDONE_ENA);
 476         }
 477
 478         spin_unlock(&dcrtc->irq_lock);
 479
 480         if (stat & GRA_FRAME_IRQ)
 481                 armada_drm_plane_work_run(dcrtc, dcrtc->crtc.primary);
 482 }
 483
 484 static irqreturn_t armada_drm_irq(int irq, void *arg)
 485 {
 486         struct armada_crtc *dcrtc = arg;
 487         u32 v, stat = readl_relaxed(dcrtc->base + LCD_SPU_IRQ_ISR);
 488
 489         /*
 490          * Reading the ISR appears to clear bits provided CLEAN_SPU_IRQ_ISR
 491          * is set.  Writing has some other effect to acknowledge the IRQ -
 492          * without this, we only get a single IRQ.
 493          */
 494         writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ISR);
 495
 496         trace_armada_drm_irq(&dcrtc->crtc, stat);
 497
 498         /* Mask out those interrupts we haven't enabled */
 499         v = stat & dcrtc->irq_ena;
 500
 501         if (v & (VSYNC_IRQ|GRA_FRAME_IRQ|DUMB_FRAMEDONE)) {
 502                 armada_drm_crtc_irq(dcrtc, stat);
 503                 return IRQ_HANDLED;
 504         }
 505         return IRQ_NONE;
 506 }
 507
 508 static uint32_t armada_drm_crtc_calculate_csc(struct armada_crtc *dcrtc)
 509 {
 510         struct drm_display_mode *adj = &dcrtc->crtc.mode;
 511         uint32_t val = 0;
 512
 513         if (dcrtc->csc_yuv_mode == CSC_YUV_CCIR709)
 514                 val |= CFG_CSC_YUV_CCIR709;
 515         if (dcrtc->csc_rgb_mode == CSC_RGB_STUDIO)
 516                 val |= CFG_CSC_RGB_STUDIO;
 517
 518         /*
 519          * In auto mode, set the colorimetry, based upon the HDMI spec.
 520          * 1280x720p, 1920x1080p and 1920x1080i use ITU709, others use
 521          * ITU601.  It may be more appropriate to set this depending on
 522          * the source - but what if the graphic frame is YUV and the
 523          * video frame is RGB?
 524          */
 525         if ((adj->hdisplay == 1280 && adj->vdisplay == 720 &&
 526              !(adj->flags & DRM_MODE_FLAG_INTERLACE)) ||
 527             (adj->hdisplay == 1920 && adj->vdisplay == 1080)) {
 528                 if (dcrtc->csc_yuv_mode == CSC_AUTO)
 529                         val |= CFG_CSC_YUV_CCIR709;
 530         }
 531
 532         /*
 533          * We assume we're connected to a TV-like device, so the YUV->RGB
 534          * conversion should produce a limited range.  We should set this
 535          * depending on the connectors attached to this CRTC, and what
 536          * kind of device they report being connected.
 537          */
 538         if (dcrtc->csc_rgb_mode == CSC_AUTO)
 539                 val |= CFG_CSC_RGB_STUDIO;
 540
 541         return val;
 542 }
 543
 544 /* The mode_config.mutex will be held for this call */
 545 static void armada_drm_crtc_mode_set_nofb(struct drm_crtc *crtc)
 546 {
 547         struct drm_display_mode *adj = &crtc->state->adjusted_mode;
 548         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 549         struct armada_regs regs[17];
 550         uint32_t lm, rm, tm, bm, val, sclk;
 551         unsigned long flags;
 552         unsigned i;
 553         bool interlaced = !!(adj->flags & DRM_MODE_FLAG_INTERLACE);
 554
 555         i = 0;
 556         rm = adj->crtc_hsync_start - adj->crtc_hdisplay;
 557         lm = adj->crtc_htotal - adj->crtc_hsync_end;
 558         bm = adj->crtc_vsync_start - adj->crtc_vdisplay;
 559         tm = adj->crtc_vtotal - adj->crtc_vsync_end;
 560
 561         DRM_DEBUG_DRIVER("H: %d %d %d %d lm %d rm %d\n",
 562                 adj->crtc_hdisplay,
 563                 adj->crtc_hsync_start,
 564                 adj->crtc_hsync_end,
 565                 adj->crtc_htotal, lm, rm);
 566         DRM_DEBUG_DRIVER("V: %d %d %d %d tm %d bm %d\n",
 567                 adj->crtc_vdisplay,
 568                 adj->crtc_vsync_start,
 569                 adj->crtc_vsync_end,
 570                 adj->crtc_vtotal, tm, bm);
 571
 572         /*
 573          * If we are blanked, we would have disabled the clock.  Re-enable
 574          * it so that compute_clock() does the right thing.
 575          */
 576         if (!IS_ERR(dcrtc->clk) && dpms_blanked(dcrtc->dpms))
 577                 WARN_ON(clk_prepare_enable(dcrtc->clk));
 578
 579         /* Now compute the divider for real */
 580         dcrtc->variant->compute_clock(dcrtc, adj, &sclk);
 581
 582         armada_reg_queue_set(regs, i, sclk, LCD_CFG_SCLK_DIV);
 583
 584         if (interlaced ^ dcrtc->interlaced) {
 585                 if (adj->flags & DRM_MODE_FLAG_INTERLACE)
 586                         drm_crtc_vblank_get(&dcrtc->crtc);
 587                 else
 588                         drm_crtc_vblank_put(&dcrtc->crtc);
 589                 dcrtc->interlaced = interlaced;
 590         }
 591
 592         spin_lock_irqsave(&dcrtc->irq_lock, flags);
 593
 594         /* Even interlaced/progressive frame */
 595         dcrtc->v[1].spu_v_h_total = adj->crtc_vtotal << 16 |
 596                                     adj->crtc_htotal;
 597         dcrtc->v[1].spu_v_porch = tm << 16 | bm;
 598         val = adj->crtc_hsync_start;
 599         dcrtc->v[1].spu_adv_reg = val << 20 | val | ADV_VSYNCOFFEN |
 600                 dcrtc->variant->spu_adv_reg;
 601
 602         if (interlaced) {
 603                 /* Odd interlaced frame */
 604                 dcrtc->v[0].spu_v_h_total = dcrtc->v[1].spu_v_h_total +
 605                                                 (1 << 16);
 606                 dcrtc->v[0].spu_v_porch = dcrtc->v[1].spu_v_porch + 1;
 607                 val = adj->crtc_hsync_start - adj->crtc_htotal / 2;
 608                 dcrtc->v[0].spu_adv_reg = val << 20 | val | ADV_VSYNCOFFEN |
 609                         dcrtc->variant->spu_adv_reg;
 610         } else {
 611                 dcrtc->v[0] = dcrtc->v[1];
 612         }
 613
 614         val = adj->crtc_vdisplay << 16 | adj->crtc_hdisplay;
 615
 616         armada_reg_queue_set(regs, i, val, LCD_SPU_V_H_ACTIVE);
 617         armada_reg_queue_set(regs, i, (lm << 16) | rm, LCD_SPU_H_PORCH);
 618         armada_reg_queue_set(regs, i, dcrtc->v[0].spu_v_porch, LCD_SPU_V_PORCH);
 619         armada_reg_queue_set(regs, i, dcrtc->v[0].spu_v_h_total,
 620                            LCD_SPUT_V_H_TOTAL);
 621
 622         if (dcrtc->variant->has_spu_adv_reg) {
 623                 armada_reg_queue_mod(regs, i, dcrtc->v[0].spu_adv_reg,
 624                                      ADV_VSYNC_L_OFF | ADV_VSYNC_H_OFF |
 625                                      ADV_VSYNCOFFEN, LCD_SPU_ADV_REG);
 626         }
 627
 628         val = adj->flags & DRM_MODE_FLAG_NVSYNC ? CFG_VSYNC_INV : 0;
 629         armada_reg_queue_mod(regs, i, val, CFG_VSYNC_INV, LCD_SPU_DMA_CTRL1);
 630
 631         val = dcrtc->spu_iopad_ctrl | armada_drm_crtc_calculate_csc(dcrtc);
 632         armada_reg_queue_set(regs, i, val, LCD_SPU_IOPAD_CONTROL);
 633         armada_reg_queue_end(regs, i);
 634
 635         armada_drm_crtc_update_regs(dcrtc, regs);
 636         spin_unlock_irqrestore(&dcrtc->irq_lock, flags);
 637 }
 638
 639 /* The mode_config.mutex will be held for this call */
 640 static void armada_drm_crtc_disable(struct drm_crtc *crtc)
 641 {
 642         armada_drm_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
 643
 644         /* Disable our primary plane when we disable the CRTC. */
 645         crtc->primary->funcs->disable_plane(crtc->primary, NULL);
 646 }
 647
 648 static void armada_drm_crtc_atomic_begin(struct drm_crtc *crtc,
 649                                          struct drm_crtc_state *old_crtc_state)
 650 {
 651         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 652         struct armada_plane *dplane;
 653
 654         DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
 655
 656         /* Wait 100ms for any plane works to complete */
 657         dplane = drm_to_armada_plane(crtc->primary);
 658         if (WARN_ON(armada_drm_plane_work_wait(dplane, HZ / 10) == 0))
 659                 armada_drm_plane_work_cancel(dcrtc, dplane);
 660
 661         dcrtc->regs_idx = 0;
 662         dcrtc->regs = dcrtc->atomic_regs;
 663 }
 664
 665 static void armada_drm_crtc_atomic_flush(struct drm_crtc *crtc,
 666                                          struct drm_crtc_state *old_crtc_state)
 667 {
 668         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 669         unsigned long flags;
 670
 671         DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
 672
 673         armada_reg_queue_end(dcrtc->regs, dcrtc->regs_idx);
 674
 675         spin_lock_irqsave(&dcrtc->irq_lock, flags);
 676         armada_drm_crtc_update_regs(dcrtc, dcrtc->regs);
 677         spin_unlock_irqrestore(&dcrtc->irq_lock, flags);
 678 }
 679
 680 static const struct drm_crtc_helper_funcs armada_crtc_helper_funcs = {
 681         .dpms           = armada_drm_crtc_dpms,
 682         .prepare        = armada_drm_crtc_prepare,
 683         .commit         = armada_drm_crtc_commit,
 684         .mode_fixup     = armada_drm_crtc_mode_fixup,
 685         .mode_set       = drm_helper_crtc_mode_set,
 686         .mode_set_nofb  = armada_drm_crtc_mode_set_nofb,
 687         .mode_set_base  = drm_helper_crtc_mode_set_base,
 688         .disable        = armada_drm_crtc_disable,
 689         .atomic_begin   = armada_drm_crtc_atomic_begin,
 690         .atomic_flush   = armada_drm_crtc_atomic_flush,
 691 };
 692
 693 static void armada_load_cursor_argb(void __iomem *base, uint32_t *pix,
 694         unsigned stride, unsigned width, unsigned height)
 695 {
 696         uint32_t addr;
 697         unsigned y;
 698
 699         addr = SRAM_HWC32_RAM1;
 700         for (y = 0; y < height; y++) {
 701                 uint32_t *p = &pix[y * stride];
 702                 unsigned x;
 703
 704                 for (x = 0; x < width; x++, p++) {
 705                         uint32_t val = *p;
 706
 707                         val = (val & 0xff00ff00) |
 708                               (val & 0x000000ff) << 16 |
 709                               (val & 0x00ff0000) >> 16;
 710
 711                         writel_relaxed(val,
 712                                        base + LCD_SPU_SRAM_WRDAT);
 713                         writel_relaxed(addr | SRAM_WRITE,
 714                                        base + LCD_SPU_SRAM_CTRL);
 715                         readl_relaxed(base + LCD_SPU_HWC_OVSA_HPXL_VLN);
 716                         addr += 1;
 717                         if ((addr & 0x00ff) == 0)
 718                                 addr += 0xf00;
 719                         if ((addr & 0x30ff) == 0)
 720                                 addr = SRAM_HWC32_RAM2;
 721                 }
 722         }
 723 }
 724
 725 static void armada_drm_crtc_cursor_tran(void __iomem *base)
 726 {
 727         unsigned addr;
 728
 729         for (addr = 0; addr < 256; addr++) {
 730                 /* write the default value */
 731                 writel_relaxed(0x55555555, base + LCD_SPU_SRAM_WRDAT);
 732                 writel_relaxed(addr | SRAM_WRITE | SRAM_HWC32_TRAN,
 733                                base + LCD_SPU_SRAM_CTRL);
 734         }
 735 }
 736
 737 static int armada_drm_crtc_cursor_update(struct armada_crtc *dcrtc, bool reload)
 738 {
 739         uint32_t xoff, xscr, w = dcrtc->cursor_w, s;
 740         uint32_t yoff, yscr, h = dcrtc->cursor_h;
 741         uint32_t para1;
 742
 743         /*
 744          * Calculate the visible width and height of the cursor,
 745          * screen position, and the position in the cursor bitmap.
 746          */
 747         if (dcrtc->cursor_x < 0) {
 748                 xoff = -dcrtc->cursor_x;
 749                 xscr = 0;
 750                 w -= min(xoff, w);
 751         } else if (dcrtc->cursor_x + w > dcrtc->crtc.mode.hdisplay) {
 752                 xoff = 0;
 753                 xscr = dcrtc->cursor_x;
 754                 w = max_t(int, dcrtc->crtc.mode.hdisplay - dcrtc->cursor_x, 0);
 755         } else {
 756                 xoff = 0;
 757                 xscr = dcrtc->cursor_x;
 758         }
 759
 760         if (dcrtc->cursor_y < 0) {
 761                 yoff = -dcrtc->cursor_y;
 762                 yscr = 0;
 763                 h -= min(yoff, h);
 764         } else if (dcrtc->cursor_y + h > dcrtc->crtc.mode.vdisplay) {
 765                 yoff = 0;
 766                 yscr = dcrtc->cursor_y;
 767                 h = max_t(int, dcrtc->crtc.mode.vdisplay - dcrtc->cursor_y, 0);
 768         } else {
 769                 yoff = 0;
 770                 yscr = dcrtc->cursor_y;
 771         }
 772
 773         /* On interlaced modes, the vertical cursor size must be halved */
 774         s = dcrtc->cursor_w;
 775         if (dcrtc->interlaced) {
 776                 s *= 2;
 777                 yscr /= 2;
 778                 h /= 2;
 779         }
 780
 781         if (!dcrtc->cursor_obj || !h || !w) {
 782                 spin_lock_irq(&dcrtc->irq_lock);
 783                 armada_drm_crtc_disable_irq(dcrtc, DUMB_FRAMEDONE_ENA);
 784                 dcrtc->cursor_update = false;
 785                 armada_updatel(0, CFG_HWC_ENA, dcrtc->base + LCD_SPU_DMA_CTRL0);
 786                 spin_unlock_irq(&dcrtc->irq_lock);
 787                 return 0;
 788         }
 789
 790         spin_lock_irq(&dcrtc->irq_lock);
 791         para1 = readl_relaxed(dcrtc->base + LCD_SPU_SRAM_PARA1);
 792         armada_updatel(CFG_CSB_256x32, CFG_CSB_256x32 | CFG_PDWN256x32,
 793                        dcrtc->base + LCD_SPU_SRAM_PARA1);
 794         spin_unlock_irq(&dcrtc->irq_lock);
 795
 796         /*
 797          * Initialize the transparency if the SRAM was powered down.
 798          * We must also reload the cursor data as well.
 799          */
 800         if (!(para1 & CFG_CSB_256x32)) {
 801                 armada_drm_crtc_cursor_tran(dcrtc->base);
 802                 reload = true;
 803         }
 804
 805         if (dcrtc->cursor_hw_sz != (h << 16 | w)) {
 806                 spin_lock_irq(&dcrtc->irq_lock);
 807                 armada_drm_crtc_disable_irq(dcrtc, DUMB_FRAMEDONE_ENA);
 808                 dcrtc->cursor_update = false;
 809                 armada_updatel(0, CFG_HWC_ENA, dcrtc->base + LCD_SPU_DMA_CTRL0);
 810                 spin_unlock_irq(&dcrtc->irq_lock);
 811                 reload = true;
 812         }
 813         if (reload) {
 814                 struct armada_gem_object *obj = dcrtc->cursor_obj;
 815                 uint32_t *pix;
 816                 /* Set the top-left corner of the cursor image */
 817                 pix = obj->addr;
 818                 pix += yoff * s + xoff;
 819                 armada_load_cursor_argb(dcrtc->base, pix, s, w, h);
 820         }
 821
 822         /* Reload the cursor position, size and enable in the IRQ handler */
 823         spin_lock_irq(&dcrtc->irq_lock);
 824         dcrtc->cursor_hw_pos = yscr << 16 | xscr;
 825         dcrtc->cursor_hw_sz = h << 16 | w;
 826         dcrtc->cursor_update = true;
 827         armada_drm_crtc_enable_irq(dcrtc, DUMB_FRAMEDONE_ENA);
 828         spin_unlock_irq(&dcrtc->irq_lock);
 829
 830         return 0;
 831 }
 832
 833 static void cursor_update(void *data)
 834 {
 835         armada_drm_crtc_cursor_update(data, true);
 836 }
 837
 838 static int armada_drm_crtc_cursor_set(struct drm_crtc *crtc,
 839         struct drm_file *file, uint32_t handle, uint32_t w, uint32_t h)
 840 {
 841         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 842         struct armada_gem_object *obj = NULL;
 843         int ret;
 844
 845         /* If no cursor support, replicate drm's return value */
 846         if (!dcrtc->variant->has_spu_adv_reg)
 847                 return -ENXIO;
 848
 849         if (handle && w > 0 && h > 0) {
 850                 /* maximum size is 64x32 or 32x64 */
 851                 if (w > 64 || h > 64 || (w > 32 && h > 32))
 852                         return -ENOMEM;
 853
 854                 obj = armada_gem_object_lookup(file, handle);
 855                 if (!obj)
 856                         return -ENOENT;
 857
 858                 /* Must be a kernel-mapped object */
 859                 if (!obj->addr) {
 860                         drm_gem_object_put_unlocked(&obj->obj);
 861                         return -EINVAL;
 862                 }
 863
 864                 if (obj->obj.size < w * h * 4) {
 865                         DRM_ERROR("buffer is too small\n");
 866                         drm_gem_object_put_unlocked(&obj->obj);
 867                         return -ENOMEM;
 868                 }
 869         }
 870
 871         if (dcrtc->cursor_obj) {
 872                 dcrtc->cursor_obj->update = NULL;
 873                 dcrtc->cursor_obj->update_data = NULL;
 874                 drm_gem_object_put_unlocked(&dcrtc->cursor_obj->obj);
 875         }
 876         dcrtc->cursor_obj = obj;
 877         dcrtc->cursor_w = w;
 878         dcrtc->cursor_h = h;
 879         ret = armada_drm_crtc_cursor_update(dcrtc, true);
 880         if (obj) {
 881                 obj->update_data = dcrtc;
 882                 obj->update = cursor_update;
 883         }
 884
 885         return ret;
 886 }
 887
 888 static int armada_drm_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
 889 {
 890         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 891         int ret;
 892
 893         /* If no cursor support, replicate drm's return value */
 894         if (!dcrtc->variant->has_spu_adv_reg)
 895                 return -EFAULT;
 896
 897         dcrtc->cursor_x = x;
 898         dcrtc->cursor_y = y;
 899         ret = armada_drm_crtc_cursor_update(dcrtc, false);
 900
 901         return ret;
 902 }
 903
 904 static void armada_drm_crtc_destroy(struct drm_crtc *crtc)
 905 {
 906         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 907         struct armada_private *priv = crtc->dev->dev_private;
 908
 909         if (dcrtc->cursor_obj)
 910                 drm_gem_object_put_unlocked(&dcrtc->cursor_obj->obj);
 911
 912         priv->dcrtc[dcrtc->num] = NULL;
 913         drm_crtc_cleanup(&dcrtc->crtc);
 914
 915         if (!IS_ERR(dcrtc->clk))
 916                 clk_disable_unprepare(dcrtc->clk);
 917
 918         writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ENA);
 919
 920         of_node_put(dcrtc->crtc.port);
 921
 922         kfree(dcrtc);
 923 }
 924
 925 /*
 926  * The mode_config lock is held here, to prevent races between this
 927  * and a mode_set.
 928  */
 929 static int armada_drm_crtc_page_flip(struct drm_crtc *crtc,
 930         struct drm_framebuffer *fb, struct drm_pending_vblank_event *event,
 931         uint32_t page_flip_flags, struct drm_modeset_acquire_ctx *ctx)
 932 {
 933         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 934         struct drm_plane *plane = crtc->primary;
 935         const struct drm_plane_helper_funcs *plane_funcs;
 936         struct drm_plane_state *state;
 937         struct armada_plane_work *work;
 938         int ret;
 939
 940         /* Construct new state for the primary plane */
 941         state = drm_atomic_helper_plane_duplicate_state(plane);
 942         if (!state)
 943                 return -ENOMEM;
 944
 945         drm_atomic_set_fb_for_plane(state, fb);
 946
 947         work = armada_drm_crtc_alloc_plane_work(plane);
 948         if (!work) {
 949                 ret = -ENOMEM;
 950                 goto put_state;
 951         }
 952
 953         /* Make sure we can get vblank interrupts */
 954         ret = drm_crtc_vblank_get(crtc);
 955         if (ret)
 956                 goto put_work;
 957
 958         /*
 959          * If we have another work pending, we can't process this flip.
 960          * The modeset locks protect us from another user queuing a work
 961          * while we're setting up.
 962          */
 963         if (drm_to_armada_plane(plane)->work) {
 964                 ret = -EBUSY;
 965                 goto put_vblank;
 966         }
 967
 968         work->event = event;
 969         work->old_fb = plane->state->fb;
 970
 971         /*
 972          * Hold a ref on the new fb while it's being displayed by the
 973          * hardware. The old fb refcount will be released in the worker.
 974          */
 975         drm_framebuffer_get(state->fb);
 976
 977         /* Point of no return */
 978         swap(plane->state, state);
 979
 980         dcrtc->regs_idx = 0;
 981         dcrtc->regs = work->regs;
 982
 983         plane_funcs = plane->helper_private;
 984         plane_funcs->atomic_update(plane, state);
 985         armada_reg_queue_end(dcrtc->regs, dcrtc->regs_idx);
 986
 987         /* Queue the work - this should never fail */
 988         WARN_ON(armada_drm_plane_work_queue(dcrtc, work));
 989         work = NULL;
 990
 991         /*
 992          * Finally, if the display is blanked, we won't receive an
 993          * interrupt, so complete it now.
 994          */
 995         if (dpms_blanked(dcrtc->dpms))
 996                 armada_drm_plane_work_run(dcrtc, plane);
 997
 998 put_vblank:
 999         drm_crtc_vblank_put(crtc);
1000 put_work:
1001         kfree(work);
1002 put_state:
1003         drm_atomic_helper_plane_destroy_state(plane, state);
1004         return ret;
1005 }
1006
1007 static int
1008 armada_drm_crtc_set_property(struct drm_crtc *crtc,
1009         struct drm_property *property, uint64_t val)
1010 {
1011         struct armada_private *priv = crtc->dev->dev_private;
1012         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
1013         bool update_csc = false;
1014
1015         if (property == priv->csc_yuv_prop) {
1016                 dcrtc->csc_yuv_mode = val;
1017                 update_csc = true;
1018         } else if (property == priv->csc_rgb_prop) {
1019                 dcrtc->csc_rgb_mode = val;
1020                 update_csc = true;
1021         }
1022
1023         if (update_csc) {
1024                 uint32_t val;
1025
1026                 val = dcrtc->spu_iopad_ctrl |
1027                       armada_drm_crtc_calculate_csc(dcrtc);
1028                 writel_relaxed(val, dcrtc->base + LCD_SPU_IOPAD_CONTROL);
1029         }
1030
1031         return 0;
1032 }
1033
1034 /* These are called under the vbl_lock. */
1035 static int armada_drm_crtc_enable_vblank(struct drm_crtc *crtc)
1036 {
1037         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
1038         unsigned long flags;
1039
1040         spin_lock_irqsave(&dcrtc->irq_lock, flags);
1041         armada_drm_crtc_enable_irq(dcrtc, VSYNC_IRQ_ENA);
1042         spin_unlock_irqrestore(&dcrtc->irq_lock, flags);
1043         return 0;
1044 }
1045
1046 static void armada_drm_crtc_disable_vblank(struct drm_crtc *crtc)
1047 {
1048         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
1049         unsigned long flags;
1050
1051         spin_lock_irqsave(&dcrtc->irq_lock, flags);
1052         armada_drm_crtc_disable_irq(dcrtc, VSYNC_IRQ_ENA);
1053         spin_unlock_irqrestore(&dcrtc->irq_lock, flags);
1054 }
1055
1056 static const struct drm_crtc_funcs armada_crtc_funcs = {
1057         .reset          = drm_atomic_helper_crtc_reset,
1058         .cursor_set     = armada_drm_crtc_cursor_set,
1059         .cursor_move    = armada_drm_crtc_cursor_move,
1060         .destroy        = armada_drm_crtc_destroy,
1061         .set_config     = drm_crtc_helper_set_config,
1062         .page_flip      = armada_drm_crtc_page_flip,
1063         .set_property   = armada_drm_crtc_set_property,
1064         .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
1065         .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
1066         .enable_vblank  = armada_drm_crtc_enable_vblank,
1067         .disable_vblank = armada_drm_crtc_disable_vblank,
1068 };
1069
1070 int armada_drm_plane_prepare_fb(struct drm_plane *plane,
1071         struct drm_plane_state *state)
1072 {
1073         DRM_DEBUG_KMS("[PLANE:%d:%s] [FB:%d]\n",
1074                 plane->base.id, plane->name,
1075                 state->fb ? state->fb->base.id : 0);
1076
1077         /*
1078          * Take a reference on the new framebuffer - we want to
1079          * hold on to it while the hardware is displaying it.
1080          */
1081         if (state->fb)
1082                 drm_framebuffer_get(state->fb);
1083         return 0;
1084 }
1085
1086 void armada_drm_plane_cleanup_fb(struct drm_plane *plane,
1087         struct drm_plane_state *old_state)
1088 {
1089         DRM_DEBUG_KMS("[PLANE:%d:%s] [FB:%d]\n",
1090                 plane->base.id, plane->name,
1091                 old_state->fb ? old_state->fb->base.id : 0);
1092
1093         if (old_state->fb)
1094                 drm_framebuffer_put(old_state->fb);
1095 }
1096
1097 int armada_drm_plane_atomic_check(struct drm_plane *plane,
1098         struct drm_plane_state *state)
1099 {
1100         if (state->fb && !WARN_ON(!state->crtc)) {
1101                 struct drm_crtc *crtc = state->crtc;
1102                 struct drm_crtc_state crtc_state = {
1103                         .crtc = crtc,
1104                         .enable = crtc->enabled,
1105                         .mode = crtc->mode,
1106                 };
1107
1108                 return drm_atomic_helper_check_plane_state(state, &crtc_state,
1109                                                            0, INT_MAX,
1110                                                            true, false);
1111         } else {
1112                 state->visible = false;
1113         }
1114         return 0;
1115 }
1116
1117 static unsigned int armada_drm_primary_update_state(
1118         struct drm_plane_state *state, struct armada_regs *regs)
1119 {
1120         struct armada_plane *dplane = drm_to_armada_plane(state->plane);
1121         struct armada_crtc *dcrtc = drm_to_armada_crtc(state->crtc);
1122         struct armada_framebuffer *dfb = drm_fb_to_armada_fb(state->fb);
1123         bool was_disabled;
1124         unsigned int idx = 0;
1125         u32 val;
1126
1127         val = CFG_GRA_FMT(dfb->fmt) | CFG_GRA_MOD(dfb->mod);
1128         if (dfb->fmt > CFG_420)
1129                 val |= CFG_PALETTE_ENA;
1130         if (state->visible)
1131                 val |= CFG_GRA_ENA;
1132         if (drm_rect_width(&state->src) >> 16 != drm_rect_width(&state->dst))
1133                 val |= CFG_GRA_HSMOOTH;
1134         if (dcrtc->interlaced)
1135                 val |= CFG_GRA_FTOGGLE;
1136
1137         was_disabled = !(dplane->state.ctrl0 & CFG_GRA_ENA);
1138         if (was_disabled)
1139                 armada_reg_queue_mod(regs, idx,
1140                                      0, CFG_PDWN64x66, LCD_SPU_SRAM_PARA1);
1141
1142         dplane->state.ctrl0 = val;
1143         dplane->state.src_hw = armada_rect_hw_fp(&state->src);
1144         dplane->state.dst_hw = armada_rect_hw(&state->dst);
1145         dplane->state.dst_yx = armada_rect_yx(&state->dst);
1146
1147         idx += armada_drm_crtc_calc_fb(&dfb->fb, state->src.x1 >> 16,
1148                                        state->src.y1 >> 16, regs + idx,
1149                                        dcrtc->interlaced);
1150         armada_reg_queue_set(regs, idx, dplane->state.dst_yx,
1151                              LCD_SPU_GRA_OVSA_HPXL_VLN);
1152         armada_reg_queue_set(regs, idx, dplane->state.src_hw,
1153                              LCD_SPU_GRA_HPXL_VLN);
1154         armada_reg_queue_set(regs, idx, dplane->state.dst_hw,
1155                              LCD_SPU_GZM_HPXL_VLN);
1156         armada_reg_queue_mod(regs, idx, dplane->state.ctrl0, CFG_GRAFORMAT |
1157                              CFG_GRA_MOD(CFG_SWAPRB | CFG_SWAPUV |
1158                                          CFG_SWAPYU | CFG_YUV2RGB) |
1159                              CFG_PALETTE_ENA | CFG_GRA_FTOGGLE |
1160                              CFG_GRA_HSMOOTH | CFG_GRA_ENA,
1161                              LCD_SPU_DMA_CTRL0);
1162
1163         dplane->state.vsync_update = !was_disabled;
1164         dplane->state.changed = true;
1165
1166         return idx;
1167 }
1168
1169 static void armada_drm_primary_plane_atomic_update(struct drm_plane *plane,
1170         struct drm_plane_state *old_state)
1171 {
1172         struct drm_plane_state *state = plane->state;
1173         struct armada_crtc *dcrtc;
1174         struct armada_regs *regs;
1175
1176         DRM_DEBUG_KMS("[PLANE:%d:%s]\n", plane->base.id, plane->name);
1177
1178         if (!state->fb || WARN_ON(!state->crtc))
1179                 return;
1180
1181         DRM_DEBUG_KMS("[PLANE:%d:%s] is on [CRTC:%d:%s] with [FB:%d] visible %u->%u\n",
1182                 plane->base.id, plane->name,
1183                 state->crtc->base.id, state->crtc->name,
1184                 state->fb->base.id,
1185                 old_state->visible, state->visible);
1186
1187         dcrtc = drm_to_armada_crtc(state->crtc);
1188         regs = dcrtc->regs + dcrtc->regs_idx;
1189
1190         dcrtc->regs_idx += armada_drm_primary_update_state(state, regs);
1191 }
1192
1193 static void armada_drm_primary_plane_atomic_disable(struct drm_plane *plane,
1194         struct drm_plane_state *old_state)
1195 {
1196         struct armada_plane *dplane = drm_to_armada_plane(plane);
1197         struct armada_crtc *dcrtc;
1198         struct armada_regs *regs;
1199         unsigned int idx = 0;
1200
1201         DRM_DEBUG_KMS("[PLANE:%d:%s]\n", plane->base.id, plane->name);
1202
1203         if (!old_state->crtc)
1204                 return;
1205
1206         DRM_DEBUG_KMS("[PLANE:%d:%s] was on [CRTC:%d:%s] with [FB:%d]\n",
1207                 plane->base.id, plane->name,
1208                 old_state->crtc->base.id, old_state->crtc->name,
1209                 old_state->fb->base.id);
1210
1211         dplane->state.ctrl0 &= ~CFG_GRA_ENA;
1212
1213         dcrtc = drm_to_armada_crtc(old_state->crtc);
1214         regs = dcrtc->regs + dcrtc->regs_idx;
1215
1216         /* Disable plane and power down most RAMs and FIFOs */
1217         armada_reg_queue_mod(regs, idx, 0, CFG_GRA_ENA, LCD_SPU_DMA_CTRL0);
1218         armada_reg_queue_mod(regs, idx, CFG_PDWN256x32 | CFG_PDWN256x24 |
1219                              CFG_PDWN256x8 | CFG_PDWN32x32 | CFG_PDWN64x66,
1220                              0, LCD_SPU_SRAM_PARA1);
1221
1222         dcrtc->regs_idx += idx;
1223 }
1224
1225 static const struct drm_plane_helper_funcs armada_primary_plane_helper_funcs = {
1226         .prepare_fb     = armada_drm_plane_prepare_fb,
1227         .cleanup_fb     = armada_drm_plane_cleanup_fb,
1228         .atomic_check   = armada_drm_plane_atomic_check,
1229         .atomic_update  = armada_drm_primary_plane_atomic_update,
1230         .atomic_disable = armada_drm_primary_plane_atomic_disable,
1231 };
1232
1233 static const struct drm_plane_funcs armada_primary_plane_funcs = {
1234         .update_plane   = drm_plane_helper_update,
1235         .disable_plane  = drm_plane_helper_disable,
1236         .destroy        = drm_primary_helper_destroy,
1237         .reset          = drm_atomic_helper_plane_reset,
1238         .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
1239         .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
1240 };
1241
1242 int armada_drm_plane_init(struct armada_plane *plane)
1243 {
1244         unsigned int i;
1245
1246         for (i = 0; i < ARRAY_SIZE(plane->works); i++)
1247                 plane->works[i].plane = &plane->base;
1248
1249         init_waitqueue_head(&plane->frame_wait);
1250
1251         return 0;
1252 }
1253
1254 static const struct drm_prop_enum_list armada_drm_csc_yuv_enum_list[] = {
1255         { CSC_AUTO,        "Auto" },
1256         { CSC_YUV_CCIR601, "CCIR601" },
1257         { CSC_YUV_CCIR709, "CCIR709" },
1258 };
1259
1260 static const struct drm_prop_enum_list armada_drm_csc_rgb_enum_list[] = {
1261         { CSC_AUTO,         "Auto" },
1262         { CSC_RGB_COMPUTER, "Computer system" },
1263         { CSC_RGB_STUDIO,   "Studio" },
1264 };
1265
1266 static int armada_drm_crtc_create_properties(struct drm_device *dev)
1267 {
1268         struct armada_private *priv = dev->dev_private;
1269
1270         if (priv->csc_yuv_prop)
1271                 return 0;
1272
1273         priv->csc_yuv_prop = drm_property_create_enum(dev, 0,
1274                                 "CSC_YUV", armada_drm_csc_yuv_enum_list,
1275                                 ARRAY_SIZE(armada_drm_csc_yuv_enum_list));
1276         priv->csc_rgb_prop = drm_property_create_enum(dev, 0,
1277                                 "CSC_RGB", armada_drm_csc_rgb_enum_list,
1278                                 ARRAY_SIZE(armada_drm_csc_rgb_enum_list));
1279
1280         if (!priv->csc_yuv_prop || !priv->csc_rgb_prop)
1281                 return -ENOMEM;
1282
1283         return 0;
1284 }
1285
1286 static int armada_drm_crtc_create(struct drm_device *drm, struct device *dev,
1287         struct resource *res, int irq, const struct armada_variant *variant,
1288         struct device_node *port)
1289 {
1290         struct armada_private *priv = drm->dev_private;
1291         struct armada_crtc *dcrtc;
1292         struct armada_plane *primary;
1293         void __iomem *base;
1294         int ret;
1295
1296         ret = armada_drm_crtc_create_properties(drm);
1297         if (ret)
1298                 return ret;
1299
1300         base = devm_ioremap_resource(dev, res);
1301         if (IS_ERR(base))
1302                 return PTR_ERR(base);
1303
1304         dcrtc = kzalloc(sizeof(*dcrtc), GFP_KERNEL);
1305         if (!dcrtc) {
1306                 DRM_ERROR("failed to allocate Armada crtc\n");
1307                 return -ENOMEM;
1308         }
1309
1310         if (dev != drm->dev)
1311                 dev_set_drvdata(dev, dcrtc);
1312
1313         dcrtc->variant = variant;
1314         dcrtc->base = base;
1315         dcrtc->num = drm->mode_config.num_crtc;
1316         dcrtc->clk = ERR_PTR(-EINVAL);
1317         dcrtc->csc_yuv_mode = CSC_AUTO;
1318         dcrtc->csc_rgb_mode = CSC_AUTO;
1319         dcrtc->cfg_dumb_ctrl = DUMB24_RGB888_0;
1320         dcrtc->spu_iopad_ctrl = CFG_VSCALE_LN_EN | CFG_IOPAD_DUMB24;
1321         spin_lock_init(&dcrtc->irq_lock);
1322         dcrtc->irq_ena = CLEAN_SPU_IRQ_ISR;
1323
1324         /* Initialize some registers which we don't otherwise set */
1325         writel_relaxed(0x00000001, dcrtc->base + LCD_CFG_SCLK_DIV);
1326         writel_relaxed(0x00000000, dcrtc->base + LCD_SPU_BLANKCOLOR);
1327         writel_relaxed(dcrtc->spu_iopad_ctrl,
1328                        dcrtc->base + LCD_SPU_IOPAD_CONTROL);
1329         writel_relaxed(0x00000000, dcrtc->base + LCD_SPU_SRAM_PARA0);
1330         writel_relaxed(CFG_PDWN256x32 | CFG_PDWN256x24 | CFG_PDWN256x8 |
1331                        CFG_PDWN32x32 | CFG_PDWN16x66 | CFG_PDWN32x66 |
1332                        CFG_PDWN64x66, dcrtc->base + LCD_SPU_SRAM_PARA1);
1333         writel_relaxed(0x2032ff81, dcrtc->base + LCD_SPU_DMA_CTRL1);
1334         writel_relaxed(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA);
1335         readl_relaxed(dcrtc->base + LCD_SPU_IRQ_ISR);
1336         writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ISR);
1337
1338         ret = devm_request_irq(dev, irq, armada_drm_irq, 0, "armada_drm_crtc",
1339                                dcrtc);
1340         if (ret < 0)
1341                 goto err_crtc;
1342
1343         if (dcrtc->variant->init) {
1344                 ret = dcrtc->variant->init(dcrtc, dev);
1345                 if (ret)
1346                         goto err_crtc;
1347         }
1348
1349         /* Ensure AXI pipeline is enabled */
1350         armada_updatel(CFG_ARBFAST_ENA, 0, dcrtc->base + LCD_SPU_DMA_CTRL0);
1351
1352         priv->dcrtc[dcrtc->num] = dcrtc;
1353
1354         dcrtc->crtc.port = port;
1355
1356         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
1357         if (!primary) {
1358                 ret = -ENOMEM;
1359                 goto err_crtc;
1360         }
1361
1362         ret = armada_drm_plane_init(primary);
1363         if (ret) {
1364                 kfree(primary);
1365                 goto err_crtc;
1366         }
1367
1368         drm_plane_helper_add(&primary->base,
1369                              &armada_primary_plane_helper_funcs);
1370
1371         ret = drm_universal_plane_init(drm, &primary->base, 0,
1372                                        &armada_primary_plane_funcs,
1373                                        armada_primary_formats,
1374                                        ARRAY_SIZE(armada_primary_formats),
1375                                        NULL,
1376                                        DRM_PLANE_TYPE_PRIMARY, NULL);
1377         if (ret) {
1378                 kfree(primary);
1379                 goto err_crtc;
1380         }
1381
1382         ret = drm_crtc_init_with_planes(drm, &dcrtc->crtc, &primary->base, NULL,
1383                                         &armada_crtc_funcs, NULL);
1384         if (ret)
1385                 goto err_crtc_init;
1386
1387         drm_crtc_helper_add(&dcrtc->crtc, &armada_crtc_helper_funcs);
1388
1389         drm_object_attach_property(&dcrtc->crtc.base, priv->csc_yuv_prop,
1390                                    dcrtc->csc_yuv_mode);
1391         drm_object_attach_property(&dcrtc->crtc.base, priv->csc_rgb_prop,
1392                                    dcrtc->csc_rgb_mode);
1393
1394         return armada_overlay_plane_create(drm, 1 << dcrtc->num);
1395
1396 err_crtc_init:
1397         primary->base.funcs->destroy(&primary->base);
1398 err_crtc:
1399         kfree(dcrtc);
1400
1401         return ret;
1402 }
1403
1404 static int
1405 armada_lcd_bind(struct device *dev, struct device *master, void *data)
1406 {
1407         struct platform_device *pdev = to_platform_device(dev);
1408         struct drm_device *drm = data;
1409         struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1410         int irq = platform_get_irq(pdev, 0);
1411         const struct armada_variant *variant;
1412         struct device_node *port = NULL;
1413
1414         if (irq < 0)
1415                 return irq;
1416
1417         if (!dev->of_node) {
1418                 const struct platform_device_id *id;
1419
1420                 id = platform_get_device_id(pdev);
1421                 if (!id)
1422                         return -ENXIO;
1423
1424                 variant = (const struct armada_variant *)id->driver_data;
1425         } else {
1426                 const struct of_device_id *match;
1427                 struct device_node *np, *parent = dev->of_node;
1428
1429                 match = of_match_device(dev->driver->of_match_table, dev);
1430                 if (!match)
1431                         return -ENXIO;
1432
1433                 np = of_get_child_by_name(parent, "ports");
1434                 if (np)
1435                         parent = np;
1436                 port = of_get_child_by_name(parent, "port");
1437                 of_node_put(np);
1438                 if (!port) {
1439                         dev_err(dev, "no port node found in %pOF\n", parent);
1440                         return -ENXIO;
1441                 }
1442
1443                 variant = match->data;
1444         }
1445
1446         return armada_drm_crtc_create(drm, dev, res, irq, variant, port);
1447 }
1448
1449 static void
1450 armada_lcd_unbind(struct device *dev, struct device *master, void *data)
1451 {
1452         struct armada_crtc *dcrtc = dev_get_drvdata(dev);
1453
1454         armada_drm_crtc_destroy(&dcrtc->crtc);
1455 }
1456
1457 static const struct component_ops armada_lcd_ops = {
1458         .bind = armada_lcd_bind,
1459         .unbind = armada_lcd_unbind,
1460 };
1461
1462 static int armada_lcd_probe(struct platform_device *pdev)
1463 {
1464         return component_add(&pdev->dev, &armada_lcd_ops);
1465 }
1466
1467 static int armada_lcd_remove(struct platform_device *pdev)
1468 {
1469         component_del(&pdev->dev, &armada_lcd_ops);
1470         return 0;
1471 }
1472
1473 static const struct of_device_id armada_lcd_of_match[] = {
1474         {
1475                 .compatible     = "marvell,dove-lcd",
1476                 .data           = &armada510_ops,
1477         },
1478         {}
1479 };
1480 MODULE_DEVICE_TABLE(of, armada_lcd_of_match);
1481
1482 static const struct platform_device_id armada_lcd_platform_ids[] = {
1483         {
1484                 .name           = "armada-lcd",
1485                 .driver_data    = (unsigned long)&armada510_ops,
1486         }, {
1487                 .name           = "armada-510-lcd",
1488                 .driver_data    = (unsigned long)&armada510_ops,
1489         },
1490         { },
1491 };
1492 MODULE_DEVICE_TABLE(platform, armada_lcd_platform_ids);
1493
1494 struct platform_driver armada_lcd_platform_driver = {
1495         .probe  = armada_lcd_probe,
1496         .remove = armada_lcd_remove,
1497         .driver = {
1498                 .name   = "armada-lcd",
1499                 .owner  =  THIS_MODULE,
1500                 .of_match_table = armada_lcd_of_match,
1501         },
1502         .id_table = armada_lcd_platform_ids,
1503 };