2 * Copyright (C) 2012 Russell King
3 * Rewritten from the dovefb driver, and Armada510 manuals.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
10 #include <linux/component.h>
11 #include <linux/of_device.h>
12 #include <linux/platform_device.h>
14 #include <drm/drm_crtc_helper.h>
15 #include <drm/drm_plane_helper.h>
16 #include <drm/drm_atomic_helper.h>
17 #include "armada_crtc.h"
18 #include "armada_drm.h"
19 #include "armada_fb.h"
20 #include "armada_gem.h"
21 #include "armada_hw.h"
22 #include "armada_trace.h"
32 static const uint32_t armada_primary_formats[] = {
50 * A note about interlacing. Let's consider HDMI 1920x1080i.
51 * The timing parameters we have from X are:
52 * Hact HsyA HsyI Htot Vact VsyA VsyI Vtot
53 * 1920 2448 2492 2640 1080 1084 1094 1125
54 * Which get translated to:
55 * Hact HsyA HsyI Htot Vact VsyA VsyI Vtot
56 * 1920 2448 2492 2640 540 542 547 562
58 * This is how it is defined by CEA-861-D - line and pixel numbers are
59 * referenced to the rising edge of VSYNC and HSYNC. Total clocks per
60 * line: 2640. The odd frame, the first active line is at line 21, and
61 * the even frame, the first active line is 584.
63 * LN: 560 561 562 563 567 568 569
64 * DE: ~~~|____________________________//__________________________
65 * HSYNC: ____|~|_____|~|_____|~|_____|~|_//__|~|_____|~|_____|~|_____
66 * VSYNC: _________________________|~~~~~~//~~~~~~~~~~~~~~~|__________
67 * 22 blanking lines. VSYNC at 1320 (referenced to the HSYNC rising edge).
69 * LN: 1123 1124 1125 1 5 6 7
70 * DE: ~~~|____________________________//__________________________
71 * HSYNC: ____|~|_____|~|_____|~|_____|~|_//__|~|_____|~|_____|~|_____
72 * VSYNC: ____________________|~~~~~~~~~~~//~~~~~~~~~~|_______________
75 * The Armada LCD Controller line and pixel numbers are, like X timings,
76 * referenced to the top left of the active frame.
78 * So, translating these to our LCD controller:
79 * Odd frame, 563 total lines, VSYNC at line 543-548, pixel 1128.
80 * Even frame, 562 total lines, VSYNC at line 542-547, pixel 2448.
81 * Note: Vsync front porch remains constant!
84 * vtotal = mode->crtc_vtotal + 1;
85 * vbackporch = mode->crtc_vsync_start - mode->crtc_vdisplay + 1;
86 * vhorizpos = mode->crtc_hsync_start - mode->crtc_htotal / 2
88 * vtotal = mode->crtc_vtotal;
89 * vbackporch = mode->crtc_vsync_start - mode->crtc_vdisplay;
90 * vhorizpos = mode->crtc_hsync_start;
92 * vfrontporch = mode->crtc_vtotal - mode->crtc_vsync_end;
94 * So, we need to reprogram these registers on each vsync event:
95 * LCD_SPU_V_PORCH, LCD_SPU_ADV_REG, LCD_SPUT_V_H_TOTAL
97 * Note: we do not use the frame done interrupts because these appear
98 * to happen too early, and lead to jitter on the display (presumably
99 * they occur at the end of the last active line, before the vsync back
100 * porch, which we're reprogramming.)
104 armada_drm_crtc_update_regs(struct armada_crtc *dcrtc, struct armada_regs *regs)
106 while (regs->offset != ~0) {
107 void __iomem *reg = dcrtc->base + regs->offset;
112 val &= readl_relaxed(reg);
113 writel_relaxed(val | regs->val, reg);
118 #define dpms_blanked(dpms) ((dpms) != DRM_MODE_DPMS_ON)
120 static void armada_drm_crtc_update(struct armada_crtc *dcrtc)
124 dumb_ctrl = dcrtc->cfg_dumb_ctrl;
126 if (!dpms_blanked(dcrtc->dpms))
127 dumb_ctrl |= CFG_DUMB_ENA;
130 * When the dumb interface isn't in DUMB24_RGB888_0 mode, it might
131 * be using SPI or GPIO. If we set this to DUMB_BLANK, we will
132 * force LCD_D[23:0] to output blank color, overriding the GPIO or
133 * SPI usage. So leave it as-is unless in DUMB24_RGB888_0 mode.
135 if (dpms_blanked(dcrtc->dpms) &&
136 (dumb_ctrl & DUMB_MASK) == DUMB24_RGB888_0) {
137 dumb_ctrl &= ~DUMB_MASK;
138 dumb_ctrl |= DUMB_BLANK;
142 * The documentation doesn't indicate what the normal state of
143 * the sync signals are. Sebastian Hesselbart kindly probed
144 * these signals on his board to determine their state.
146 * The non-inverted state of the sync signals is active high.
147 * Setting these bits makes the appropriate signal active low.
149 if (dcrtc->crtc.mode.flags & DRM_MODE_FLAG_NCSYNC)
150 dumb_ctrl |= CFG_INV_CSYNC;
151 if (dcrtc->crtc.mode.flags & DRM_MODE_FLAG_NHSYNC)
152 dumb_ctrl |= CFG_INV_HSYNC;
153 if (dcrtc->crtc.mode.flags & DRM_MODE_FLAG_NVSYNC)
154 dumb_ctrl |= CFG_INV_VSYNC;
156 if (dcrtc->dumb_ctrl != dumb_ctrl) {
157 dcrtc->dumb_ctrl = dumb_ctrl;
158 writel_relaxed(dumb_ctrl, dcrtc->base + LCD_SPU_DUMB_CTRL);
162 void armada_drm_plane_calc_addrs(u32 *addrs, struct drm_framebuffer *fb,
165 const struct drm_format_info *format = fb->format;
166 unsigned int num_planes = format->num_planes;
167 u32 addr = drm_fb_obj(fb)->dev_addr;
173 addrs[0] = addr + fb->offsets[0] + y * fb->pitches[0] +
179 for (i = 1; i < num_planes; i++)
180 addrs[i] = addr + fb->offsets[i] + y * fb->pitches[i] +
186 static unsigned armada_drm_crtc_calc_fb(struct drm_framebuffer *fb,
187 int x, int y, struct armada_regs *regs, bool interlaced)
189 unsigned pitch = fb->pitches[0];
190 u32 addrs[3], addr_odd, addr_even;
193 DRM_DEBUG_DRIVER("pitch %u x %d y %d bpp %d\n",
194 pitch, x, y, fb->format->cpp[0] * 8);
196 armada_drm_plane_calc_addrs(addrs, fb, x, y);
198 addr_odd = addr_even = addrs[0];
205 /* write offset, base, and pitch */
206 armada_reg_queue_set(regs, i, addr_odd, LCD_CFG_GRA_START_ADDR0);
207 armada_reg_queue_set(regs, i, addr_even, LCD_CFG_GRA_START_ADDR1);
208 armada_reg_queue_mod(regs, i, pitch, 0xffff, LCD_CFG_GRA_PITCH);
213 static void armada_drm_plane_work_call(struct armada_crtc *dcrtc,
214 struct armada_plane_work *work,
215 void (*fn)(struct armada_crtc *, struct armada_plane_work *))
217 struct armada_plane *dplane = drm_to_armada_plane(work->plane);
218 struct drm_pending_vblank_event *event;
219 struct drm_framebuffer *fb;
223 drm_crtc_vblank_put(&dcrtc->crtc);
228 struct drm_device *dev = dcrtc->crtc.dev;
231 spin_lock_irqsave(&dev->event_lock, flags);
233 drm_crtc_send_vblank_event(&dcrtc->crtc, event);
235 __armada_drm_queue_unref_work(dev, fb);
236 spin_unlock_irqrestore(&dev->event_lock, flags);
239 if (work->need_kfree)
242 wake_up(&dplane->frame_wait);
245 static void armada_drm_plane_work_run(struct armada_crtc *dcrtc,
246 struct drm_plane *plane)
248 struct armada_plane *dplane = drm_to_armada_plane(plane);
249 struct armada_plane_work *work = xchg(&dplane->work, NULL);
251 /* Handle any pending frame work. */
253 armada_drm_plane_work_call(dcrtc, work, work->fn);
256 int armada_drm_plane_work_queue(struct armada_crtc *dcrtc,
257 struct armada_plane_work *work)
259 struct armada_plane *plane = drm_to_armada_plane(work->plane);
262 ret = drm_crtc_vblank_get(&dcrtc->crtc);
266 ret = cmpxchg(&plane->work, NULL, work) ? -EBUSY : 0;
268 drm_crtc_vblank_put(&dcrtc->crtc);
273 int armada_drm_plane_work_wait(struct armada_plane *plane, long timeout)
275 return wait_event_timeout(plane->frame_wait, !plane->work, timeout);
278 void armada_drm_plane_work_cancel(struct armada_crtc *dcrtc,
279 struct armada_plane *dplane)
281 struct armada_plane_work *work = xchg(&dplane->work, NULL);
284 armada_drm_plane_work_call(dcrtc, work, work->cancel);
287 static void armada_drm_crtc_complete_frame_work(struct armada_crtc *dcrtc,
288 struct armada_plane_work *work)
292 spin_lock_irqsave(&dcrtc->irq_lock, flags);
293 armada_drm_crtc_update_regs(dcrtc, work->regs);
294 spin_unlock_irqrestore(&dcrtc->irq_lock, flags);
297 static void armada_drm_crtc_complete_disable_work(struct armada_crtc *dcrtc,
298 struct armada_plane_work *work)
302 if (dcrtc->plane == work->plane)
305 spin_lock_irqsave(&dcrtc->irq_lock, flags);
306 armada_drm_crtc_update_regs(dcrtc, work->regs);
307 spin_unlock_irqrestore(&dcrtc->irq_lock, flags);
310 static struct armada_plane_work *
311 armada_drm_crtc_alloc_plane_work(struct drm_plane *plane)
313 struct armada_plane_work *work;
316 work = kzalloc(sizeof(*work), GFP_KERNEL);
321 work->fn = armada_drm_crtc_complete_frame_work;
322 work->need_kfree = true;
323 armada_reg_queue_end(work->regs, i);
328 static void armada_drm_crtc_finish_fb(struct armada_crtc *dcrtc,
329 struct drm_framebuffer *fb, bool force)
331 struct armada_plane_work *work;
337 /* Display is disabled, so just drop the old fb */
338 drm_framebuffer_put(fb);
342 work = armada_drm_crtc_alloc_plane_work(dcrtc->crtc.primary);
346 if (armada_drm_plane_work_queue(dcrtc, work) == 0)
353 * Oops - just drop the reference immediately and hope for
354 * the best. The worst that will happen is the buffer gets
355 * reused before it has finished being displayed.
357 drm_framebuffer_put(fb);
360 static void armada_drm_vblank_off(struct armada_crtc *dcrtc)
363 * Tell the DRM core that vblank IRQs aren't going to happen for
364 * a while. This cleans up any pending vblank events for us.
366 drm_crtc_vblank_off(&dcrtc->crtc);
367 armada_drm_plane_work_run(dcrtc, dcrtc->crtc.primary);
370 /* The mode_config.mutex will be held for this call */
371 static void armada_drm_crtc_dpms(struct drm_crtc *crtc, int dpms)
373 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
375 if (dpms_blanked(dcrtc->dpms) != dpms_blanked(dpms)) {
376 if (dpms_blanked(dpms))
377 armada_drm_vblank_off(dcrtc);
378 else if (!IS_ERR(dcrtc->clk))
379 WARN_ON(clk_prepare_enable(dcrtc->clk));
381 armada_drm_crtc_update(dcrtc);
382 if (!dpms_blanked(dpms))
383 drm_crtc_vblank_on(&dcrtc->crtc);
384 else if (!IS_ERR(dcrtc->clk))
385 clk_disable_unprepare(dcrtc->clk);
386 } else if (dcrtc->dpms != dpms) {
392 * Prepare for a mode set. Turn off overlay to ensure that we don't end
393 * up with the overlay size being bigger than the active screen size.
394 * We rely upon X refreshing this state after the mode set has completed.
396 * The mode_config.mutex will be held for this call
398 static void armada_drm_crtc_prepare(struct drm_crtc *crtc)
400 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
401 struct drm_plane *plane;
404 * If we have an overlay plane associated with this CRTC, disable
405 * it before the modeset to avoid its coordinates being outside
406 * the new mode parameters.
408 plane = dcrtc->plane;
410 drm_plane_force_disable(plane);
411 WARN_ON(!armada_drm_plane_work_wait(drm_to_armada_plane(plane),
416 /* The mode_config.mutex will be held for this call */
417 static void armada_drm_crtc_commit(struct drm_crtc *crtc)
419 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
421 if (dcrtc->dpms != DRM_MODE_DPMS_ON) {
422 dcrtc->dpms = DRM_MODE_DPMS_ON;
423 armada_drm_crtc_update(dcrtc);
427 /* The mode_config.mutex will be held for this call */
428 static bool armada_drm_crtc_mode_fixup(struct drm_crtc *crtc,
429 const struct drm_display_mode *mode, struct drm_display_mode *adj)
431 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
434 /* We can't do interlaced modes if we don't have the SPU_ADV_REG */
435 if (!dcrtc->variant->has_spu_adv_reg &&
436 adj->flags & DRM_MODE_FLAG_INTERLACE)
439 /* Check whether the display mode is possible */
440 ret = dcrtc->variant->compute_clock(dcrtc, adj, NULL);
447 /* These are locked by dev->vbl_lock */
448 static void armada_drm_crtc_disable_irq(struct armada_crtc *dcrtc, u32 mask)
450 if (dcrtc->irq_ena & mask) {
451 dcrtc->irq_ena &= ~mask;
452 writel(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA);
456 static void armada_drm_crtc_enable_irq(struct armada_crtc *dcrtc, u32 mask)
458 if ((dcrtc->irq_ena & mask) != mask) {
459 dcrtc->irq_ena |= mask;
460 writel(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA);
461 if (readl_relaxed(dcrtc->base + LCD_SPU_IRQ_ISR) & mask)
462 writel(0, dcrtc->base + LCD_SPU_IRQ_ISR);
466 static void armada_drm_crtc_irq(struct armada_crtc *dcrtc, u32 stat)
468 void __iomem *base = dcrtc->base;
469 struct drm_plane *ovl_plane;
471 if (stat & DMA_FF_UNDERFLOW)
472 DRM_ERROR("video underflow on crtc %u\n", dcrtc->num);
473 if (stat & GRA_FF_UNDERFLOW)
474 DRM_ERROR("graphics underflow on crtc %u\n", dcrtc->num);
476 if (stat & VSYNC_IRQ)
477 drm_crtc_handle_vblank(&dcrtc->crtc);
479 ovl_plane = dcrtc->plane;
481 armada_drm_plane_work_run(dcrtc, ovl_plane);
483 spin_lock(&dcrtc->irq_lock);
484 if (stat & GRA_FRAME_IRQ && dcrtc->interlaced) {
485 int i = stat & GRA_FRAME_IRQ0 ? 0 : 1;
488 writel_relaxed(dcrtc->v[i].spu_v_porch, base + LCD_SPU_V_PORCH);
489 writel_relaxed(dcrtc->v[i].spu_v_h_total,
490 base + LCD_SPUT_V_H_TOTAL);
492 val = readl_relaxed(base + LCD_SPU_ADV_REG);
493 val &= ~(ADV_VSYNC_L_OFF | ADV_VSYNC_H_OFF | ADV_VSYNCOFFEN);
494 val |= dcrtc->v[i].spu_adv_reg;
495 writel_relaxed(val, base + LCD_SPU_ADV_REG);
498 if (stat & DUMB_FRAMEDONE && dcrtc->cursor_update) {
499 writel_relaxed(dcrtc->cursor_hw_pos,
500 base + LCD_SPU_HWC_OVSA_HPXL_VLN);
501 writel_relaxed(dcrtc->cursor_hw_sz,
502 base + LCD_SPU_HWC_HPXL_VLN);
503 armada_updatel(CFG_HWC_ENA,
504 CFG_HWC_ENA | CFG_HWC_1BITMOD | CFG_HWC_1BITENA,
505 base + LCD_SPU_DMA_CTRL0);
506 dcrtc->cursor_update = false;
507 armada_drm_crtc_disable_irq(dcrtc, DUMB_FRAMEDONE_ENA);
510 spin_unlock(&dcrtc->irq_lock);
512 if (stat & GRA_FRAME_IRQ)
513 armada_drm_plane_work_run(dcrtc, dcrtc->crtc.primary);
516 static irqreturn_t armada_drm_irq(int irq, void *arg)
518 struct armada_crtc *dcrtc = arg;
519 u32 v, stat = readl_relaxed(dcrtc->base + LCD_SPU_IRQ_ISR);
522 * Reading the ISR appears to clear bits provided CLEAN_SPU_IRQ_ISR
523 * is set. Writing has some other effect to acknowledge the IRQ -
524 * without this, we only get a single IRQ.
526 writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ISR);
528 trace_armada_drm_irq(&dcrtc->crtc, stat);
530 /* Mask out those interrupts we haven't enabled */
531 v = stat & dcrtc->irq_ena;
533 if (v & (VSYNC_IRQ|GRA_FRAME_IRQ|DUMB_FRAMEDONE)) {
534 armada_drm_crtc_irq(dcrtc, stat);
540 static uint32_t armada_drm_crtc_calculate_csc(struct armada_crtc *dcrtc)
542 struct drm_display_mode *adj = &dcrtc->crtc.mode;
545 if (dcrtc->csc_yuv_mode == CSC_YUV_CCIR709)
546 val |= CFG_CSC_YUV_CCIR709;
547 if (dcrtc->csc_rgb_mode == CSC_RGB_STUDIO)
548 val |= CFG_CSC_RGB_STUDIO;
551 * In auto mode, set the colorimetry, based upon the HDMI spec.
552 * 1280x720p, 1920x1080p and 1920x1080i use ITU709, others use
553 * ITU601. It may be more appropriate to set this depending on
554 * the source - but what if the graphic frame is YUV and the
555 * video frame is RGB?
557 if ((adj->hdisplay == 1280 && adj->vdisplay == 720 &&
558 !(adj->flags & DRM_MODE_FLAG_INTERLACE)) ||
559 (adj->hdisplay == 1920 && adj->vdisplay == 1080)) {
560 if (dcrtc->csc_yuv_mode == CSC_AUTO)
561 val |= CFG_CSC_YUV_CCIR709;
565 * We assume we're connected to a TV-like device, so the YUV->RGB
566 * conversion should produce a limited range. We should set this
567 * depending on the connectors attached to this CRTC, and what
568 * kind of device they report being connected.
570 if (dcrtc->csc_rgb_mode == CSC_AUTO)
571 val |= CFG_CSC_RGB_STUDIO;
576 static void armada_drm_gra_plane_regs(struct armada_regs *regs,
577 struct drm_framebuffer *fb, struct armada_plane_state *state,
578 int x, int y, bool interlaced)
583 i = armada_drm_crtc_calc_fb(fb, x, y, regs, interlaced);
584 armada_reg_queue_set(regs, i, state->dst_yx, LCD_SPU_GRA_OVSA_HPXL_VLN);
585 armada_reg_queue_set(regs, i, state->src_hw, LCD_SPU_GRA_HPXL_VLN);
586 armada_reg_queue_set(regs, i, state->dst_hw, LCD_SPU_GZM_HPXL_VLN);
588 ctrl0 = state->ctrl0;
590 ctrl0 |= CFG_GRA_FTOGGLE;
592 armada_reg_queue_mod(regs, i, ctrl0, CFG_GRAFORMAT |
593 CFG_GRA_MOD(CFG_SWAPRB | CFG_SWAPUV |
594 CFG_SWAPYU | CFG_YUV2RGB) |
595 CFG_PALETTE_ENA | CFG_GRA_FTOGGLE |
596 CFG_GRA_HSMOOTH | CFG_GRA_ENA,
598 armada_reg_queue_end(regs, i);
601 static void armada_drm_primary_set(struct drm_crtc *crtc,
602 struct drm_plane *plane, int x, int y)
604 struct armada_plane_state *state = &drm_to_armada_plane(plane)->state;
605 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
606 struct armada_regs regs[8];
607 bool interlaced = dcrtc->interlaced;
609 armada_drm_gra_plane_regs(regs, plane->fb, state, x, y, interlaced);
610 armada_drm_crtc_update_regs(dcrtc, regs);
613 /* The mode_config.mutex will be held for this call */
614 static int armada_drm_crtc_mode_set(struct drm_crtc *crtc,
615 struct drm_display_mode *mode, struct drm_display_mode *adj,
616 int x, int y, struct drm_framebuffer *old_fb)
618 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
619 struct armada_regs regs[17];
620 uint32_t lm, rm, tm, bm, val, sclk;
625 drm_framebuffer_get(crtc->primary->fb);
627 interlaced = !!(adj->flags & DRM_MODE_FLAG_INTERLACE);
630 val |= CFG_GRA_FMT(drm_fb_to_armada_fb(dcrtc->crtc.primary->fb)->fmt);
631 val |= CFG_GRA_MOD(drm_fb_to_armada_fb(dcrtc->crtc.primary->fb)->mod);
633 if (drm_fb_to_armada_fb(dcrtc->crtc.primary->fb)->fmt > CFG_420)
634 val |= CFG_PALETTE_ENA;
636 drm_to_armada_plane(crtc->primary)->state.ctrl0 = val;
637 drm_to_armada_plane(crtc->primary)->state.src_hw =
638 drm_to_armada_plane(crtc->primary)->state.dst_hw =
639 adj->crtc_vdisplay << 16 | adj->crtc_hdisplay;
640 drm_to_armada_plane(crtc->primary)->state.dst_yx = 0;
643 rm = adj->crtc_hsync_start - adj->crtc_hdisplay;
644 lm = adj->crtc_htotal - adj->crtc_hsync_end;
645 bm = adj->crtc_vsync_start - adj->crtc_vdisplay;
646 tm = adj->crtc_vtotal - adj->crtc_vsync_end;
648 DRM_DEBUG_DRIVER("H: %d %d %d %d lm %d rm %d\n",
650 adj->crtc_hsync_start,
652 adj->crtc_htotal, lm, rm);
653 DRM_DEBUG_DRIVER("V: %d %d %d %d tm %d bm %d\n",
655 adj->crtc_vsync_start,
657 adj->crtc_vtotal, tm, bm);
659 /* Wait for pending flips to complete */
660 armada_drm_plane_work_wait(drm_to_armada_plane(dcrtc->crtc.primary),
661 MAX_SCHEDULE_TIMEOUT);
663 drm_crtc_vblank_off(crtc);
665 val = dcrtc->dumb_ctrl & ~CFG_DUMB_ENA;
666 if (val != dcrtc->dumb_ctrl) {
667 dcrtc->dumb_ctrl = val;
668 writel_relaxed(val, dcrtc->base + LCD_SPU_DUMB_CTRL);
672 * If we are blanked, we would have disabled the clock. Re-enable
673 * it so that compute_clock() does the right thing.
675 if (!IS_ERR(dcrtc->clk) && dpms_blanked(dcrtc->dpms))
676 WARN_ON(clk_prepare_enable(dcrtc->clk));
678 /* Now compute the divider for real */
679 dcrtc->variant->compute_clock(dcrtc, adj, &sclk);
681 armada_reg_queue_set(regs, i, sclk, LCD_CFG_SCLK_DIV);
683 if (interlaced ^ dcrtc->interlaced) {
684 if (adj->flags & DRM_MODE_FLAG_INTERLACE)
685 drm_crtc_vblank_get(&dcrtc->crtc);
687 drm_crtc_vblank_put(&dcrtc->crtc);
688 dcrtc->interlaced = interlaced;
691 spin_lock_irqsave(&dcrtc->irq_lock, flags);
693 /* Ensure graphic fifo is enabled */
694 armada_reg_queue_mod(regs, i, 0, CFG_PDWN64x66, LCD_SPU_SRAM_PARA1);
696 /* Even interlaced/progressive frame */
697 dcrtc->v[1].spu_v_h_total = adj->crtc_vtotal << 16 |
699 dcrtc->v[1].spu_v_porch = tm << 16 | bm;
700 val = adj->crtc_hsync_start;
701 dcrtc->v[1].spu_adv_reg = val << 20 | val | ADV_VSYNCOFFEN |
702 dcrtc->variant->spu_adv_reg;
705 /* Odd interlaced frame */
706 dcrtc->v[0].spu_v_h_total = dcrtc->v[1].spu_v_h_total +
708 dcrtc->v[0].spu_v_porch = dcrtc->v[1].spu_v_porch + 1;
709 val = adj->crtc_hsync_start - adj->crtc_htotal / 2;
710 dcrtc->v[0].spu_adv_reg = val << 20 | val | ADV_VSYNCOFFEN |
711 dcrtc->variant->spu_adv_reg;
713 dcrtc->v[0] = dcrtc->v[1];
716 val = adj->crtc_vdisplay << 16 | adj->crtc_hdisplay;
718 armada_reg_queue_set(regs, i, val, LCD_SPU_V_H_ACTIVE);
719 armada_reg_queue_set(regs, i, (lm << 16) | rm, LCD_SPU_H_PORCH);
720 armada_reg_queue_set(regs, i, dcrtc->v[0].spu_v_porch, LCD_SPU_V_PORCH);
721 armada_reg_queue_set(regs, i, dcrtc->v[0].spu_v_h_total,
724 if (dcrtc->variant->has_spu_adv_reg) {
725 armada_reg_queue_mod(regs, i, dcrtc->v[0].spu_adv_reg,
726 ADV_VSYNC_L_OFF | ADV_VSYNC_H_OFF |
727 ADV_VSYNCOFFEN, LCD_SPU_ADV_REG);
730 val = adj->flags & DRM_MODE_FLAG_NVSYNC ? CFG_VSYNC_INV : 0;
731 armada_reg_queue_mod(regs, i, val, CFG_VSYNC_INV, LCD_SPU_DMA_CTRL1);
733 val = dcrtc->spu_iopad_ctrl | armada_drm_crtc_calculate_csc(dcrtc);
734 armada_reg_queue_set(regs, i, val, LCD_SPU_IOPAD_CONTROL);
735 armada_reg_queue_end(regs, i);
737 armada_drm_crtc_update_regs(dcrtc, regs);
739 armada_drm_primary_set(crtc, crtc->primary, x, y);
740 spin_unlock_irqrestore(&dcrtc->irq_lock, flags);
742 armada_drm_crtc_update(dcrtc);
744 drm_crtc_vblank_on(crtc);
745 armada_drm_crtc_finish_fb(dcrtc, old_fb, dpms_blanked(dcrtc->dpms));
750 /* The mode_config.mutex will be held for this call */
751 static int armada_drm_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
752 struct drm_framebuffer *old_fb)
754 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
755 struct armada_regs regs[4];
758 i = armada_drm_crtc_calc_fb(crtc->primary->fb, crtc->x, crtc->y, regs,
760 armada_reg_queue_end(regs, i);
762 /* Wait for pending flips to complete */
763 armada_drm_plane_work_wait(drm_to_armada_plane(dcrtc->crtc.primary),
764 MAX_SCHEDULE_TIMEOUT);
766 /* Take a reference to the new fb as we're using it */
767 drm_framebuffer_get(crtc->primary->fb);
769 /* Update the base in the CRTC */
770 armada_drm_crtc_update_regs(dcrtc, regs);
772 /* Drop our previously held reference */
773 armada_drm_crtc_finish_fb(dcrtc, old_fb, dpms_blanked(dcrtc->dpms));
778 /* The mode_config.mutex will be held for this call */
779 static void armada_drm_crtc_disable(struct drm_crtc *crtc)
781 armada_drm_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
783 /* Disable our primary plane when we disable the CRTC. */
784 crtc->primary->funcs->disable_plane(crtc->primary, NULL);
787 static const struct drm_crtc_helper_funcs armada_crtc_helper_funcs = {
788 .dpms = armada_drm_crtc_dpms,
789 .prepare = armada_drm_crtc_prepare,
790 .commit = armada_drm_crtc_commit,
791 .mode_fixup = armada_drm_crtc_mode_fixup,
792 .mode_set = armada_drm_crtc_mode_set,
793 .mode_set_base = armada_drm_crtc_mode_set_base,
794 .disable = armada_drm_crtc_disable,
797 static void armada_load_cursor_argb(void __iomem *base, uint32_t *pix,
798 unsigned stride, unsigned width, unsigned height)
803 addr = SRAM_HWC32_RAM1;
804 for (y = 0; y < height; y++) {
805 uint32_t *p = &pix[y * stride];
808 for (x = 0; x < width; x++, p++) {
811 val = (val & 0xff00ff00) |
812 (val & 0x000000ff) << 16 |
813 (val & 0x00ff0000) >> 16;
816 base + LCD_SPU_SRAM_WRDAT);
817 writel_relaxed(addr | SRAM_WRITE,
818 base + LCD_SPU_SRAM_CTRL);
819 readl_relaxed(base + LCD_SPU_HWC_OVSA_HPXL_VLN);
821 if ((addr & 0x00ff) == 0)
823 if ((addr & 0x30ff) == 0)
824 addr = SRAM_HWC32_RAM2;
829 static void armada_drm_crtc_cursor_tran(void __iomem *base)
833 for (addr = 0; addr < 256; addr++) {
834 /* write the default value */
835 writel_relaxed(0x55555555, base + LCD_SPU_SRAM_WRDAT);
836 writel_relaxed(addr | SRAM_WRITE | SRAM_HWC32_TRAN,
837 base + LCD_SPU_SRAM_CTRL);
841 static int armada_drm_crtc_cursor_update(struct armada_crtc *dcrtc, bool reload)
843 uint32_t xoff, xscr, w = dcrtc->cursor_w, s;
844 uint32_t yoff, yscr, h = dcrtc->cursor_h;
848 * Calculate the visible width and height of the cursor,
849 * screen position, and the position in the cursor bitmap.
851 if (dcrtc->cursor_x < 0) {
852 xoff = -dcrtc->cursor_x;
855 } else if (dcrtc->cursor_x + w > dcrtc->crtc.mode.hdisplay) {
857 xscr = dcrtc->cursor_x;
858 w = max_t(int, dcrtc->crtc.mode.hdisplay - dcrtc->cursor_x, 0);
861 xscr = dcrtc->cursor_x;
864 if (dcrtc->cursor_y < 0) {
865 yoff = -dcrtc->cursor_y;
868 } else if (dcrtc->cursor_y + h > dcrtc->crtc.mode.vdisplay) {
870 yscr = dcrtc->cursor_y;
871 h = max_t(int, dcrtc->crtc.mode.vdisplay - dcrtc->cursor_y, 0);
874 yscr = dcrtc->cursor_y;
877 /* On interlaced modes, the vertical cursor size must be halved */
879 if (dcrtc->interlaced) {
885 if (!dcrtc->cursor_obj || !h || !w) {
886 spin_lock_irq(&dcrtc->irq_lock);
887 armada_drm_crtc_disable_irq(dcrtc, DUMB_FRAMEDONE_ENA);
888 dcrtc->cursor_update = false;
889 armada_updatel(0, CFG_HWC_ENA, dcrtc->base + LCD_SPU_DMA_CTRL0);
890 spin_unlock_irq(&dcrtc->irq_lock);
894 spin_lock_irq(&dcrtc->irq_lock);
895 para1 = readl_relaxed(dcrtc->base + LCD_SPU_SRAM_PARA1);
896 armada_updatel(CFG_CSB_256x32, CFG_CSB_256x32 | CFG_PDWN256x32,
897 dcrtc->base + LCD_SPU_SRAM_PARA1);
898 spin_unlock_irq(&dcrtc->irq_lock);
901 * Initialize the transparency if the SRAM was powered down.
902 * We must also reload the cursor data as well.
904 if (!(para1 & CFG_CSB_256x32)) {
905 armada_drm_crtc_cursor_tran(dcrtc->base);
909 if (dcrtc->cursor_hw_sz != (h << 16 | w)) {
910 spin_lock_irq(&dcrtc->irq_lock);
911 armada_drm_crtc_disable_irq(dcrtc, DUMB_FRAMEDONE_ENA);
912 dcrtc->cursor_update = false;
913 armada_updatel(0, CFG_HWC_ENA, dcrtc->base + LCD_SPU_DMA_CTRL0);
914 spin_unlock_irq(&dcrtc->irq_lock);
918 struct armada_gem_object *obj = dcrtc->cursor_obj;
920 /* Set the top-left corner of the cursor image */
922 pix += yoff * s + xoff;
923 armada_load_cursor_argb(dcrtc->base, pix, s, w, h);
926 /* Reload the cursor position, size and enable in the IRQ handler */
927 spin_lock_irq(&dcrtc->irq_lock);
928 dcrtc->cursor_hw_pos = yscr << 16 | xscr;
929 dcrtc->cursor_hw_sz = h << 16 | w;
930 dcrtc->cursor_update = true;
931 armada_drm_crtc_enable_irq(dcrtc, DUMB_FRAMEDONE_ENA);
932 spin_unlock_irq(&dcrtc->irq_lock);
937 static void cursor_update(void *data)
939 armada_drm_crtc_cursor_update(data, true);
942 static int armada_drm_crtc_cursor_set(struct drm_crtc *crtc,
943 struct drm_file *file, uint32_t handle, uint32_t w, uint32_t h)
945 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
946 struct armada_gem_object *obj = NULL;
949 /* If no cursor support, replicate drm's return value */
950 if (!dcrtc->variant->has_spu_adv_reg)
953 if (handle && w > 0 && h > 0) {
954 /* maximum size is 64x32 or 32x64 */
955 if (w > 64 || h > 64 || (w > 32 && h > 32))
958 obj = armada_gem_object_lookup(file, handle);
962 /* Must be a kernel-mapped object */
964 drm_gem_object_put_unlocked(&obj->obj);
968 if (obj->obj.size < w * h * 4) {
969 DRM_ERROR("buffer is too small\n");
970 drm_gem_object_put_unlocked(&obj->obj);
975 if (dcrtc->cursor_obj) {
976 dcrtc->cursor_obj->update = NULL;
977 dcrtc->cursor_obj->update_data = NULL;
978 drm_gem_object_put_unlocked(&dcrtc->cursor_obj->obj);
980 dcrtc->cursor_obj = obj;
983 ret = armada_drm_crtc_cursor_update(dcrtc, true);
985 obj->update_data = dcrtc;
986 obj->update = cursor_update;
992 static int armada_drm_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
994 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
997 /* If no cursor support, replicate drm's return value */
998 if (!dcrtc->variant->has_spu_adv_reg)
1001 dcrtc->cursor_x = x;
1002 dcrtc->cursor_y = y;
1003 ret = armada_drm_crtc_cursor_update(dcrtc, false);
1008 static void armada_drm_crtc_destroy(struct drm_crtc *crtc)
1010 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
1011 struct armada_private *priv = crtc->dev->dev_private;
1013 if (dcrtc->cursor_obj)
1014 drm_gem_object_put_unlocked(&dcrtc->cursor_obj->obj);
1016 priv->dcrtc[dcrtc->num] = NULL;
1017 drm_crtc_cleanup(&dcrtc->crtc);
1019 if (!IS_ERR(dcrtc->clk))
1020 clk_disable_unprepare(dcrtc->clk);
1022 writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ENA);
1024 of_node_put(dcrtc->crtc.port);
1030 * The mode_config lock is held here, to prevent races between this
1033 static int armada_drm_crtc_page_flip(struct drm_crtc *crtc,
1034 struct drm_framebuffer *fb, struct drm_pending_vblank_event *event, uint32_t page_flip_flags,
1035 struct drm_modeset_acquire_ctx *ctx)
1037 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
1038 struct armada_plane_work *work;
1042 work = armada_drm_crtc_alloc_plane_work(dcrtc->crtc.primary);
1046 work->event = event;
1047 work->old_fb = dcrtc->crtc.primary->fb;
1049 i = armada_drm_crtc_calc_fb(fb, crtc->x, crtc->y, work->regs,
1051 armada_reg_queue_end(work->regs, i);
1054 * Ensure that we hold a reference on the new framebuffer.
1055 * This has to match the behaviour in mode_set.
1057 drm_framebuffer_get(fb);
1059 ret = armada_drm_plane_work_queue(dcrtc, work);
1061 /* Undo our reference above */
1062 drm_framebuffer_put(fb);
1068 * Finally, if the display is blanked, we won't receive an
1069 * interrupt, so complete it now.
1071 if (dpms_blanked(dcrtc->dpms))
1072 armada_drm_plane_work_run(dcrtc, dcrtc->crtc.primary);
1078 armada_drm_crtc_set_property(struct drm_crtc *crtc,
1079 struct drm_property *property, uint64_t val)
1081 struct armada_private *priv = crtc->dev->dev_private;
1082 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
1083 bool update_csc = false;
1085 if (property == priv->csc_yuv_prop) {
1086 dcrtc->csc_yuv_mode = val;
1088 } else if (property == priv->csc_rgb_prop) {
1089 dcrtc->csc_rgb_mode = val;
1096 val = dcrtc->spu_iopad_ctrl |
1097 armada_drm_crtc_calculate_csc(dcrtc);
1098 writel_relaxed(val, dcrtc->base + LCD_SPU_IOPAD_CONTROL);
1104 /* These are called under the vbl_lock. */
1105 static int armada_drm_crtc_enable_vblank(struct drm_crtc *crtc)
1107 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
1108 unsigned long flags;
1110 spin_lock_irqsave(&dcrtc->irq_lock, flags);
1111 armada_drm_crtc_enable_irq(dcrtc, VSYNC_IRQ_ENA);
1112 spin_unlock_irqrestore(&dcrtc->irq_lock, flags);
1116 static void armada_drm_crtc_disable_vblank(struct drm_crtc *crtc)
1118 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
1119 unsigned long flags;
1121 spin_lock_irqsave(&dcrtc->irq_lock, flags);
1122 armada_drm_crtc_disable_irq(dcrtc, VSYNC_IRQ_ENA);
1123 spin_unlock_irqrestore(&dcrtc->irq_lock, flags);
1126 static const struct drm_crtc_funcs armada_crtc_funcs = {
1127 .cursor_set = armada_drm_crtc_cursor_set,
1128 .cursor_move = armada_drm_crtc_cursor_move,
1129 .destroy = armada_drm_crtc_destroy,
1130 .set_config = drm_crtc_helper_set_config,
1131 .page_flip = armada_drm_crtc_page_flip,
1132 .set_property = armada_drm_crtc_set_property,
1133 .enable_vblank = armada_drm_crtc_enable_vblank,
1134 .disable_vblank = armada_drm_crtc_disable_vblank,
1137 static void armada_drm_primary_update_state(struct drm_plane_state *state,
1138 struct armada_regs *regs)
1140 struct armada_plane *dplane = drm_to_armada_plane(state->plane);
1141 struct armada_crtc *dcrtc = drm_to_armada_crtc(state->crtc);
1142 struct armada_framebuffer *dfb = drm_fb_to_armada_fb(state->fb);
1144 unsigned int idx = 0;
1147 val = CFG_GRA_FMT(dfb->fmt) | CFG_GRA_MOD(dfb->mod);
1148 if (dfb->fmt > CFG_420)
1149 val |= CFG_PALETTE_ENA;
1152 if (drm_rect_width(&state->src) >> 16 != drm_rect_width(&state->dst))
1153 val |= CFG_GRA_HSMOOTH;
1155 was_disabled = !(dplane->state.ctrl0 & CFG_GRA_ENA);
1157 armada_reg_queue_mod(regs, idx,
1158 0, CFG_PDWN64x66, LCD_SPU_SRAM_PARA1);
1160 dplane->state.ctrl0 = val;
1161 dplane->state.src_hw = armada_rect_hw_fp(&state->src);
1162 dplane->state.dst_hw = armada_rect_hw(&state->dst);
1163 dplane->state.dst_yx = armada_rect_yx(&state->dst);
1165 armada_drm_gra_plane_regs(regs + idx, &dfb->fb, &dplane->state,
1166 state->src.x1 >> 16, state->src.y1 >> 16,
1169 dplane->state.vsync_update = !was_disabled;
1170 dplane->state.changed = true;
1173 static int armada_drm_primary_update(struct drm_plane *plane,
1174 struct drm_crtc *crtc, struct drm_framebuffer *fb,
1175 int crtc_x, int crtc_y, unsigned int crtc_w, unsigned int crtc_h,
1176 uint32_t src_x, uint32_t src_y, uint32_t src_w, uint32_t src_h,
1177 struct drm_modeset_acquire_ctx *ctx)
1179 struct armada_plane *dplane = drm_to_armada_plane(plane);
1180 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
1181 struct armada_plane_work *work;
1182 struct drm_plane_state state = {
1194 .rotation = DRM_MODE_ROTATE_0,
1196 struct drm_crtc_state crtc_state = {
1198 .enable = crtc->enabled,
1203 ret = drm_atomic_helper_check_plane_state(&state, &crtc_state, 0,
1204 INT_MAX, true, false);
1208 work = &dplane->works[dplane->next_work];
1209 work->fn = armada_drm_crtc_complete_frame_work;
1211 if (plane->fb != fb) {
1213 * Take a reference on the new framebuffer - we want to
1214 * hold on to it while the hardware is displaying it.
1216 drm_framebuffer_reference(fb);
1218 work->old_fb = plane->fb;
1220 work->old_fb = NULL;
1223 armada_drm_primary_update_state(&state, work->regs);
1225 if (!dplane->state.changed)
1228 /* Wait for pending work to complete */
1229 if (armada_drm_plane_work_wait(dplane, HZ / 10) == 0)
1230 armada_drm_plane_work_cancel(dcrtc, dplane);
1232 if (!dplane->state.vsync_update) {
1233 work->fn(dcrtc, work);
1235 drm_framebuffer_unreference(work->old_fb);
1239 /* Queue it for update on the next interrupt if we are enabled */
1240 ret = armada_drm_plane_work_queue(dcrtc, work);
1242 work->fn(dcrtc, work);
1244 drm_framebuffer_unreference(work->old_fb);
1247 dplane->next_work = !dplane->next_work;
1252 int armada_drm_plane_disable(struct drm_plane *plane,
1253 struct drm_modeset_acquire_ctx *ctx)
1255 struct armada_plane *dplane = drm_to_armada_plane(plane);
1256 struct armada_crtc *dcrtc;
1257 struct armada_plane_work *work;
1258 unsigned int idx = 0;
1259 u32 sram_para1, enable_mask;
1265 * Arrange to power down most RAMs and FIFOs if this is the primary
1266 * plane, otherwise just the YUV FIFOs for the overlay plane.
1268 if (plane->type == DRM_PLANE_TYPE_PRIMARY) {
1269 sram_para1 = CFG_PDWN256x32 | CFG_PDWN256x24 | CFG_PDWN256x8 |
1270 CFG_PDWN32x32 | CFG_PDWN64x66;
1271 enable_mask = CFG_GRA_ENA;
1273 sram_para1 = CFG_PDWN16x66 | CFG_PDWN32x66;
1274 enable_mask = CFG_DMA_ENA;
1277 dplane->state.ctrl0 &= ~enable_mask;
1279 dcrtc = drm_to_armada_crtc(plane->crtc);
1282 * Try to disable the plane and drop our ref on the framebuffer
1283 * at the next frame update. If we fail for any reason, disable
1284 * the plane immediately.
1286 work = &dplane->works[dplane->next_work];
1287 work->fn = armada_drm_crtc_complete_disable_work;
1288 work->cancel = armada_drm_crtc_complete_disable_work;
1289 work->old_fb = plane->fb;
1291 armada_reg_queue_mod(work->regs, idx,
1292 0, enable_mask, LCD_SPU_DMA_CTRL0);
1293 armada_reg_queue_mod(work->regs, idx,
1294 sram_para1, 0, LCD_SPU_SRAM_PARA1);
1295 armada_reg_queue_end(work->regs, idx);
1297 /* Wait for any preceding work to complete, but don't wedge */
1298 if (WARN_ON(!armada_drm_plane_work_wait(dplane, HZ)))
1299 armada_drm_plane_work_cancel(dcrtc, dplane);
1301 if (armada_drm_plane_work_queue(dcrtc, work)) {
1302 work->fn(dcrtc, work);
1304 drm_framebuffer_unreference(work->old_fb);
1307 dplane->next_work = !dplane->next_work;
1312 static const struct drm_plane_funcs armada_primary_plane_funcs = {
1313 .update_plane = armada_drm_primary_update,
1314 .disable_plane = armada_drm_plane_disable,
1315 .destroy = drm_primary_helper_destroy,
1318 int armada_drm_plane_init(struct armada_plane *plane)
1322 for (i = 0; i < ARRAY_SIZE(plane->works); i++)
1323 plane->works[i].plane = &plane->base;
1325 init_waitqueue_head(&plane->frame_wait);
1330 static const struct drm_prop_enum_list armada_drm_csc_yuv_enum_list[] = {
1331 { CSC_AUTO, "Auto" },
1332 { CSC_YUV_CCIR601, "CCIR601" },
1333 { CSC_YUV_CCIR709, "CCIR709" },
1336 static const struct drm_prop_enum_list armada_drm_csc_rgb_enum_list[] = {
1337 { CSC_AUTO, "Auto" },
1338 { CSC_RGB_COMPUTER, "Computer system" },
1339 { CSC_RGB_STUDIO, "Studio" },
1342 static int armada_drm_crtc_create_properties(struct drm_device *dev)
1344 struct armada_private *priv = dev->dev_private;
1346 if (priv->csc_yuv_prop)
1349 priv->csc_yuv_prop = drm_property_create_enum(dev, 0,
1350 "CSC_YUV", armada_drm_csc_yuv_enum_list,
1351 ARRAY_SIZE(armada_drm_csc_yuv_enum_list));
1352 priv->csc_rgb_prop = drm_property_create_enum(dev, 0,
1353 "CSC_RGB", armada_drm_csc_rgb_enum_list,
1354 ARRAY_SIZE(armada_drm_csc_rgb_enum_list));
1356 if (!priv->csc_yuv_prop || !priv->csc_rgb_prop)
1362 static int armada_drm_crtc_create(struct drm_device *drm, struct device *dev,
1363 struct resource *res, int irq, const struct armada_variant *variant,
1364 struct device_node *port)
1366 struct armada_private *priv = drm->dev_private;
1367 struct armada_crtc *dcrtc;
1368 struct armada_plane *primary;
1372 ret = armada_drm_crtc_create_properties(drm);
1376 base = devm_ioremap_resource(dev, res);
1378 return PTR_ERR(base);
1380 dcrtc = kzalloc(sizeof(*dcrtc), GFP_KERNEL);
1382 DRM_ERROR("failed to allocate Armada crtc\n");
1386 if (dev != drm->dev)
1387 dev_set_drvdata(dev, dcrtc);
1389 dcrtc->variant = variant;
1391 dcrtc->num = drm->mode_config.num_crtc;
1392 dcrtc->clk = ERR_PTR(-EINVAL);
1393 dcrtc->csc_yuv_mode = CSC_AUTO;
1394 dcrtc->csc_rgb_mode = CSC_AUTO;
1395 dcrtc->cfg_dumb_ctrl = DUMB24_RGB888_0;
1396 dcrtc->spu_iopad_ctrl = CFG_VSCALE_LN_EN | CFG_IOPAD_DUMB24;
1397 spin_lock_init(&dcrtc->irq_lock);
1398 dcrtc->irq_ena = CLEAN_SPU_IRQ_ISR;
1400 /* Initialize some registers which we don't otherwise set */
1401 writel_relaxed(0x00000001, dcrtc->base + LCD_CFG_SCLK_DIV);
1402 writel_relaxed(0x00000000, dcrtc->base + LCD_SPU_BLANKCOLOR);
1403 writel_relaxed(dcrtc->spu_iopad_ctrl,
1404 dcrtc->base + LCD_SPU_IOPAD_CONTROL);
1405 writel_relaxed(0x00000000, dcrtc->base + LCD_SPU_SRAM_PARA0);
1406 writel_relaxed(CFG_PDWN256x32 | CFG_PDWN256x24 | CFG_PDWN256x8 |
1407 CFG_PDWN32x32 | CFG_PDWN16x66 | CFG_PDWN32x66 |
1408 CFG_PDWN64x66, dcrtc->base + LCD_SPU_SRAM_PARA1);
1409 writel_relaxed(0x2032ff81, dcrtc->base + LCD_SPU_DMA_CTRL1);
1410 writel_relaxed(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA);
1411 readl_relaxed(dcrtc->base + LCD_SPU_IRQ_ISR);
1412 writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ISR);
1414 ret = devm_request_irq(dev, irq, armada_drm_irq, 0, "armada_drm_crtc",
1419 if (dcrtc->variant->init) {
1420 ret = dcrtc->variant->init(dcrtc, dev);
1425 /* Ensure AXI pipeline is enabled */
1426 armada_updatel(CFG_ARBFAST_ENA, 0, dcrtc->base + LCD_SPU_DMA_CTRL0);
1428 priv->dcrtc[dcrtc->num] = dcrtc;
1430 dcrtc->crtc.port = port;
1432 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
1438 ret = armada_drm_plane_init(primary);
1444 ret = drm_universal_plane_init(drm, &primary->base, 0,
1445 &armada_primary_plane_funcs,
1446 armada_primary_formats,
1447 ARRAY_SIZE(armada_primary_formats),
1449 DRM_PLANE_TYPE_PRIMARY, NULL);
1455 ret = drm_crtc_init_with_planes(drm, &dcrtc->crtc, &primary->base, NULL,
1456 &armada_crtc_funcs, NULL);
1460 drm_crtc_helper_add(&dcrtc->crtc, &armada_crtc_helper_funcs);
1462 drm_object_attach_property(&dcrtc->crtc.base, priv->csc_yuv_prop,
1463 dcrtc->csc_yuv_mode);
1464 drm_object_attach_property(&dcrtc->crtc.base, priv->csc_rgb_prop,
1465 dcrtc->csc_rgb_mode);
1467 return armada_overlay_plane_create(drm, 1 << dcrtc->num);
1470 primary->base.funcs->destroy(&primary->base);
1478 armada_lcd_bind(struct device *dev, struct device *master, void *data)
1480 struct platform_device *pdev = to_platform_device(dev);
1481 struct drm_device *drm = data;
1482 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1483 int irq = platform_get_irq(pdev, 0);
1484 const struct armada_variant *variant;
1485 struct device_node *port = NULL;
1490 if (!dev->of_node) {
1491 const struct platform_device_id *id;
1493 id = platform_get_device_id(pdev);
1497 variant = (const struct armada_variant *)id->driver_data;
1499 const struct of_device_id *match;
1500 struct device_node *np, *parent = dev->of_node;
1502 match = of_match_device(dev->driver->of_match_table, dev);
1506 np = of_get_child_by_name(parent, "ports");
1509 port = of_get_child_by_name(parent, "port");
1512 dev_err(dev, "no port node found in %pOF\n", parent);
1516 variant = match->data;
1519 return armada_drm_crtc_create(drm, dev, res, irq, variant, port);
1523 armada_lcd_unbind(struct device *dev, struct device *master, void *data)
1525 struct armada_crtc *dcrtc = dev_get_drvdata(dev);
1527 armada_drm_crtc_destroy(&dcrtc->crtc);
1530 static const struct component_ops armada_lcd_ops = {
1531 .bind = armada_lcd_bind,
1532 .unbind = armada_lcd_unbind,
1535 static int armada_lcd_probe(struct platform_device *pdev)
1537 return component_add(&pdev->dev, &armada_lcd_ops);
1540 static int armada_lcd_remove(struct platform_device *pdev)
1542 component_del(&pdev->dev, &armada_lcd_ops);
1546 static const struct of_device_id armada_lcd_of_match[] = {
1548 .compatible = "marvell,dove-lcd",
1549 .data = &armada510_ops,
1553 MODULE_DEVICE_TABLE(of, armada_lcd_of_match);
1555 static const struct platform_device_id armada_lcd_platform_ids[] = {
1557 .name = "armada-lcd",
1558 .driver_data = (unsigned long)&armada510_ops,
1560 .name = "armada-510-lcd",
1561 .driver_data = (unsigned long)&armada510_ops,
1565 MODULE_DEVICE_TABLE(platform, armada_lcd_platform_ids);
1567 struct platform_driver armada_lcd_platform_driver = {
1568 .probe = armada_lcd_probe,
1569 .remove = armada_lcd_remove,
1571 .name = "armada-lcd",
1572 .owner = THIS_MODULE,
1573 .of_match_table = armada_lcd_of_match,
1575 .id_table = armada_lcd_platform_ids,