drivers/gpu/drm/bridge/ti-sn65dsi86.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2018, The Linux Foundation. All rights reserved.
   4  * datasheet: https://www.ti.com/lit/ds/symlink/sn65dsi86.pdf
   5  */
   6
   7 #include <linux/atomic.h>
   8 #include <linux/auxiliary_bus.h>
   9 #include <linux/bitfield.h>
  10 #include <linux/bits.h>
  11 #include <linux/clk.h>
  12 #include <linux/debugfs.h>
  13 #include <linux/gpio/consumer.h>
  14 #include <linux/gpio/driver.h>
  15 #include <linux/i2c.h>
  16 #include <linux/iopoll.h>
  17 #include <linux/module.h>
  18 #include <linux/of_graph.h>
  19 #include <linux/pm_runtime.h>
  20 #include <linux/pwm.h>
  21 #include <linux/regmap.h>
  22 #include <linux/regulator/consumer.h>
  23
  24 #include <asm/unaligned.h>
  25
  26 #include <drm/drm_atomic.h>
  27 #include <drm/drm_atomic_helper.h>
  28 #include <drm/drm_bridge.h>
  29 #include <drm/drm_dp_aux_bus.h>
  30 #include <drm/drm_dp_helper.h>
  31 #include <drm/drm_mipi_dsi.h>
  32 #include <drm/drm_of.h>
  33 #include <drm/drm_panel.h>
  34 #include <drm/drm_print.h>
  35 #include <drm/drm_probe_helper.h>
  36
  37 #define SN_DEVICE_REV_REG                       0x08
  38 #define SN_DPPLL_SRC_REG                        0x0A
  39 #define  DPPLL_CLK_SRC_DSICLK                   BIT(0)
  40 #define  REFCLK_FREQ_MASK                       GENMASK(3, 1)
  41 #define  REFCLK_FREQ(x)                         ((x) << 1)
  42 #define  DPPLL_SRC_DP_PLL_LOCK                  BIT(7)
  43 #define SN_PLL_ENABLE_REG                       0x0D
  44 #define SN_DSI_LANES_REG                        0x10
  45 #define  CHA_DSI_LANES_MASK                     GENMASK(4, 3)
  46 #define  CHA_DSI_LANES(x)                       ((x) << 3)
  47 #define SN_DSIA_CLK_FREQ_REG                    0x12
  48 #define SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG       0x20
  49 #define SN_CHA_VERTICAL_DISPLAY_SIZE_LOW_REG    0x24
  50 #define SN_CHA_HSYNC_PULSE_WIDTH_LOW_REG        0x2C
  51 #define SN_CHA_HSYNC_PULSE_WIDTH_HIGH_REG       0x2D
  52 #define  CHA_HSYNC_POLARITY                     BIT(7)
  53 #define SN_CHA_VSYNC_PULSE_WIDTH_LOW_REG        0x30
  54 #define SN_CHA_VSYNC_PULSE_WIDTH_HIGH_REG       0x31
  55 #define  CHA_VSYNC_POLARITY                     BIT(7)
  56 #define SN_CHA_HORIZONTAL_BACK_PORCH_REG        0x34
  57 #define SN_CHA_VERTICAL_BACK_PORCH_REG          0x36
  58 #define SN_CHA_HORIZONTAL_FRONT_PORCH_REG       0x38
  59 #define SN_CHA_VERTICAL_FRONT_PORCH_REG         0x3A
  60 #define SN_LN_ASSIGN_REG                        0x59
  61 #define  LN_ASSIGN_WIDTH                        2
  62 #define SN_ENH_FRAME_REG                        0x5A
  63 #define  VSTREAM_ENABLE                         BIT(3)
  64 #define  LN_POLRS_OFFSET                        4
  65 #define  LN_POLRS_MASK                          0xf0
  66 #define SN_DATA_FORMAT_REG                      0x5B
  67 #define  BPP_18_RGB                             BIT(0)
  68 #define SN_HPD_DISABLE_REG                      0x5C
  69 #define  HPD_DISABLE                            BIT(0)
  70 #define SN_GPIO_IO_REG                          0x5E
  71 #define  SN_GPIO_INPUT_SHIFT                    4
  72 #define  SN_GPIO_OUTPUT_SHIFT                   0
  73 #define SN_GPIO_CTRL_REG                        0x5F
  74 #define  SN_GPIO_MUX_INPUT                      0
  75 #define  SN_GPIO_MUX_OUTPUT                     1
  76 #define  SN_GPIO_MUX_SPECIAL                    2
  77 #define  SN_GPIO_MUX_MASK                       0x3
  78 #define SN_AUX_WDATA_REG(x)                     (0x64 + (x))
  79 #define SN_AUX_ADDR_19_16_REG                   0x74
  80 #define SN_AUX_ADDR_15_8_REG                    0x75
  81 #define SN_AUX_ADDR_7_0_REG                     0x76
  82 #define SN_AUX_ADDR_MASK                        GENMASK(19, 0)
  83 #define SN_AUX_LENGTH_REG                       0x77
  84 #define SN_AUX_CMD_REG                          0x78
  85 #define  AUX_CMD_SEND                           BIT(0)
  86 #define  AUX_CMD_REQ(x)                         ((x) << 4)
  87 #define SN_AUX_RDATA_REG(x)                     (0x79 + (x))
  88 #define SN_SSC_CONFIG_REG                       0x93
  89 #define  DP_NUM_LANES_MASK                      GENMASK(5, 4)
  90 #define  DP_NUM_LANES(x)                        ((x) << 4)
  91 #define SN_DATARATE_CONFIG_REG                  0x94
  92 #define  DP_DATARATE_MASK                       GENMASK(7, 5)
  93 #define  DP_DATARATE(x)                         ((x) << 5)
  94 #define SN_ML_TX_MODE_REG                       0x96
  95 #define  ML_TX_MAIN_LINK_OFF                    0
  96 #define  ML_TX_NORMAL_MODE                      BIT(0)
  97 #define SN_PWM_PRE_DIV_REG                      0xA0
  98 #define SN_BACKLIGHT_SCALE_REG                  0xA1
  99 #define  BACKLIGHT_SCALE_MAX                    0xFFFF
 100 #define SN_BACKLIGHT_REG                        0xA3
 101 #define SN_PWM_EN_INV_REG                       0xA5
 102 #define  SN_PWM_INV_MASK                        BIT(0)
 103 #define  SN_PWM_EN_MASK                         BIT(1)
 104 #define SN_AUX_CMD_STATUS_REG                   0xF4
 105 #define  AUX_IRQ_STATUS_AUX_RPLY_TOUT           BIT(3)
 106 #define  AUX_IRQ_STATUS_AUX_SHORT               BIT(5)
 107 #define  AUX_IRQ_STATUS_NAT_I2C_FAIL            BIT(6)
 108
 109 #define MIN_DSI_CLK_FREQ_MHZ    40
 110
 111 /* fudge factor required to account for 8b/10b encoding */
 112 #define DP_CLK_FUDGE_NUM        10
 113 #define DP_CLK_FUDGE_DEN        8
 114
 115 /* Matches DP_AUX_MAX_PAYLOAD_BYTES (for now) */
 116 #define SN_AUX_MAX_PAYLOAD_BYTES        16
 117
 118 #define SN_REGULATOR_SUPPLY_NUM         4
 119
 120 #define SN_MAX_DP_LANES                 4
 121 #define SN_NUM_GPIOS                    4
 122 #define SN_GPIO_PHYSICAL_OFFSET         1
 123
 124 #define SN_LINK_TRAINING_TRIES          10
 125
 126 #define SN_PWM_GPIO_IDX                 3 /* 4th GPIO */
 127
 128 /**
 129  * struct ti_sn65dsi86 - Platform data for ti-sn65dsi86 driver.
 130  * @bridge_aux:   AUX-bus sub device for MIPI-to-eDP bridge functionality.
 131  * @gpio_aux:     AUX-bus sub device for GPIO controller functionality.
 132  * @aux_aux:      AUX-bus sub device for eDP AUX channel functionality.
 133  * @pwm_aux:      AUX-bus sub device for PWM controller functionality.
 134  *
 135  * @dev:          Pointer to the top level (i2c) device.
 136  * @regmap:       Regmap for accessing i2c.
 137  * @aux:          Our aux channel.
 138  * @bridge:       Our bridge.
 139  * @connector:    Our connector.
 140  * @host_node:    Remote DSI node.
 141  * @dsi:          Our MIPI DSI source.
 142  * @refclk:       Our reference clock.
 143  * @next_bridge:  The bridge on the eDP side.
 144  * @enable_gpio:  The GPIO we toggle to enable the bridge.
 145  * @supplies:     Data for bulk enabling/disabling our regulators.
 146  * @dp_lanes:     Count of dp_lanes we're using.
 147  * @ln_assign:    Value to program to the LN_ASSIGN register.
 148  * @ln_polrs:     Value for the 4-bit LN_POLRS field of SN_ENH_FRAME_REG.
 149  * @comms_enabled: If true then communication over the aux channel is enabled.
 150  * @comms_mutex:   Protects modification of comms_enabled.
 151  *
 152  * @gchip:        If we expose our GPIOs, this is used.
 153  * @gchip_output: A cache of whether we've set GPIOs to output.  This
 154  *                serves double-duty of keeping track of the direction and
 155  *                also keeping track of whether we've incremented the
 156  *                pm_runtime reference count for this pin, which we do
 157  *                whenever a pin is configured as an output.  This is a
 158  *                bitmap so we can do atomic ops on it without an extra
 159  *                lock so concurrent users of our 4 GPIOs don't stomp on
 160  *                each other's read-modify-write.
 161  *
 162  * @pchip:        pwm_chip if the PWM is exposed.
 163  * @pwm_enabled:  Used to track if the PWM signal is currently enabled.
 164  * @pwm_pin_busy: Track if GPIO4 is currently requested for GPIO or PWM.
 165  * @pwm_refclk_freq: Cache for the reference clock input to the PWM.
 166  */
 167 struct ti_sn65dsi86 {
 168         struct auxiliary_device         bridge_aux;
 169         struct auxiliary_device         gpio_aux;
 170         struct auxiliary_device         aux_aux;
 171         struct auxiliary_device         pwm_aux;
 172
 173         struct device                   *dev;
 174         struct regmap                   *regmap;
 175         struct drm_dp_aux               aux;
 176         struct drm_bridge               bridge;
 177         struct drm_connector            connector;
 178         struct device_node              *host_node;
 179         struct mipi_dsi_device          *dsi;
 180         struct clk                      *refclk;
 181         struct drm_bridge               *next_bridge;
 182         struct gpio_desc                *enable_gpio;
 183         struct regulator_bulk_data      supplies[SN_REGULATOR_SUPPLY_NUM];
 184         int                             dp_lanes;
 185         u8                              ln_assign;
 186         u8                              ln_polrs;
 187         bool                            comms_enabled;
 188         struct mutex                    comms_mutex;
 189
 190 #if defined(CONFIG_OF_GPIO)
 191         struct gpio_chip                gchip;
 192         DECLARE_BITMAP(gchip_output, SN_NUM_GPIOS);
 193 #endif
 194 #if defined(CONFIG_PWM)
 195         struct pwm_chip                 pchip;
 196         bool                            pwm_enabled;
 197         atomic_t                        pwm_pin_busy;
 198 #endif
 199         unsigned int                    pwm_refclk_freq;
 200 };
 201
 202 static const struct regmap_range ti_sn65dsi86_volatile_ranges[] = {
 203         { .range_min = 0, .range_max = 0xFF },
 204 };
 205
 206 static const struct regmap_access_table ti_sn_bridge_volatile_table = {
 207         .yes_ranges = ti_sn65dsi86_volatile_ranges,
 208         .n_yes_ranges = ARRAY_SIZE(ti_sn65dsi86_volatile_ranges),
 209 };
 210
 211 static const struct regmap_config ti_sn65dsi86_regmap_config = {
 212         .reg_bits = 8,
 213         .val_bits = 8,
 214         .volatile_table = &ti_sn_bridge_volatile_table,
 215         .cache_type = REGCACHE_NONE,
 216         .max_register = 0xFF,
 217 };
 218
 219 static int __maybe_unused ti_sn65dsi86_read_u16(struct ti_sn65dsi86 *pdata,
 220                                                 unsigned int reg, u16 *val)
 221 {
 222         u8 buf[2];
 223         int ret;
 224
 225         ret = regmap_bulk_read(pdata->regmap, reg, buf, ARRAY_SIZE(buf));
 226         if (ret)
 227                 return ret;
 228
 229         *val = buf[0] | (buf[1] << 8);
 230
 231         return 0;
 232 }
 233
 234 static void ti_sn65dsi86_write_u16(struct ti_sn65dsi86 *pdata,
 235                                    unsigned int reg, u16 val)
 236 {
 237         u8 buf[2] = { val & 0xff, val >> 8 };
 238
 239         regmap_bulk_write(pdata->regmap, reg, buf, ARRAY_SIZE(buf));
 240 }
 241
 242 static u32 ti_sn_bridge_get_dsi_freq(struct ti_sn65dsi86 *pdata)
 243 {
 244         u32 bit_rate_khz, clk_freq_khz;
 245         struct drm_display_mode *mode =
 246                 &pdata->bridge.encoder->crtc->state->adjusted_mode;
 247
 248         bit_rate_khz = mode->clock *
 249                         mipi_dsi_pixel_format_to_bpp(pdata->dsi->format);
 250         clk_freq_khz = bit_rate_khz / (pdata->dsi->lanes * 2);
 251
 252         return clk_freq_khz;
 253 }
 254
 255 /* clk frequencies supported by bridge in Hz in case derived from REFCLK pin */
 256 static const u32 ti_sn_bridge_refclk_lut[] = {
 257         12000000,
 258         19200000,
 259         26000000,
 260         27000000,
 261         38400000,
 262 };
 263
 264 /* clk frequencies supported by bridge in Hz in case derived from DACP/N pin */
 265 static const u32 ti_sn_bridge_dsiclk_lut[] = {
 266         468000000,
 267         384000000,
 268         416000000,
 269         486000000,
 270         460800000,
 271 };
 272
 273 static void ti_sn_bridge_set_refclk_freq(struct ti_sn65dsi86 *pdata)
 274 {
 275         int i;
 276         u32 refclk_rate;
 277         const u32 *refclk_lut;
 278         size_t refclk_lut_size;
 279
 280         if (pdata->refclk) {
 281                 refclk_rate = clk_get_rate(pdata->refclk);
 282                 refclk_lut = ti_sn_bridge_refclk_lut;
 283                 refclk_lut_size = ARRAY_SIZE(ti_sn_bridge_refclk_lut);
 284                 clk_prepare_enable(pdata->refclk);
 285         } else {
 286                 refclk_rate = ti_sn_bridge_get_dsi_freq(pdata) * 1000;
 287                 refclk_lut = ti_sn_bridge_dsiclk_lut;
 288                 refclk_lut_size = ARRAY_SIZE(ti_sn_bridge_dsiclk_lut);
 289         }
 290
 291         /* for i equals to refclk_lut_size means default frequency */
 292         for (i = 0; i < refclk_lut_size; i++)
 293                 if (refclk_lut[i] == refclk_rate)
 294                         break;
 295
 296         regmap_update_bits(pdata->regmap, SN_DPPLL_SRC_REG, REFCLK_FREQ_MASK,
 297                            REFCLK_FREQ(i));
 298
 299         /*
 300          * The PWM refclk is based on the value written to SN_DPPLL_SRC_REG,
 301          * regardless of its actual sourcing.
 302          */
 303         pdata->pwm_refclk_freq = ti_sn_bridge_refclk_lut[i];
 304 }
 305
 306 static void ti_sn65dsi86_enable_comms(struct ti_sn65dsi86 *pdata)
 307 {
 308         mutex_lock(&pdata->comms_mutex);
 309
 310         /* configure bridge ref_clk */
 311         ti_sn_bridge_set_refclk_freq(pdata);
 312
 313         /*
 314          * HPD on this bridge chip is a bit useless.  This is an eDP bridge
 315          * so the HPD is an internal signal that's only there to signal that
 316          * the panel is done powering up.  ...but the bridge chip debounces
 317          * this signal by between 100 ms and 400 ms (depending on process,
 318          * voltage, and temperate--I measured it at about 200 ms).  One
 319          * particular panel asserted HPD 84 ms after it was powered on meaning
 320          * that we saw HPD 284 ms after power on.  ...but the same panel said
 321          * that instead of looking at HPD you could just hardcode a delay of
 322          * 200 ms.  We'll assume that the panel driver will have the hardcoded
 323          * delay in its prepare and always disable HPD.
 324          *
 325          * If HPD somehow makes sense on some future panel we'll have to
 326          * change this to be conditional on someone specifying that HPD should
 327          * be used.
 328          */
 329         regmap_update_bits(pdata->regmap, SN_HPD_DISABLE_REG, HPD_DISABLE,
 330                            HPD_DISABLE);
 331
 332         pdata->comms_enabled = true;
 333
 334         mutex_unlock(&pdata->comms_mutex);
 335 }
 336
 337 static void ti_sn65dsi86_disable_comms(struct ti_sn65dsi86 *pdata)
 338 {
 339         mutex_lock(&pdata->comms_mutex);
 340
 341         pdata->comms_enabled = false;
 342         clk_disable_unprepare(pdata->refclk);
 343
 344         mutex_unlock(&pdata->comms_mutex);
 345 }
 346
 347 static int __maybe_unused ti_sn65dsi86_resume(struct device *dev)
 348 {
 349         struct ti_sn65dsi86 *pdata = dev_get_drvdata(dev);
 350         int ret;
 351
 352         ret = regulator_bulk_enable(SN_REGULATOR_SUPPLY_NUM, pdata->supplies);
 353         if (ret) {
 354                 DRM_ERROR("failed to enable supplies %d\n", ret);
 355                 return ret;
 356         }
 357
 358         /* td2: min 100 us after regulators before enabling the GPIO */
 359         usleep_range(100, 110);
 360
 361         gpiod_set_value(pdata->enable_gpio, 1);
 362
 363         /*
 364          * If we have a reference clock we can enable communication w/ the
 365          * panel (including the aux channel) w/out any need for an input clock
 366          * so we can do it in resume which lets us read the EDID before
 367          * pre_enable(). Without a reference clock we need the MIPI reference
 368          * clock so reading early doesn't work.
 369          */
 370         if (pdata->refclk)
 371                 ti_sn65dsi86_enable_comms(pdata);
 372
 373         return ret;
 374 }
 375
 376 static int __maybe_unused ti_sn65dsi86_suspend(struct device *dev)
 377 {
 378         struct ti_sn65dsi86 *pdata = dev_get_drvdata(dev);
 379         int ret;
 380
 381         if (pdata->refclk)
 382                 ti_sn65dsi86_disable_comms(pdata);
 383
 384         gpiod_set_value(pdata->enable_gpio, 0);
 385
 386         ret = regulator_bulk_disable(SN_REGULATOR_SUPPLY_NUM, pdata->supplies);
 387         if (ret)
 388                 DRM_ERROR("failed to disable supplies %d\n", ret);
 389
 390         return ret;
 391 }
 392
 393 static const struct dev_pm_ops ti_sn65dsi86_pm_ops = {
 394         SET_RUNTIME_PM_OPS(ti_sn65dsi86_suspend, ti_sn65dsi86_resume, NULL)
 395         SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
 396                                 pm_runtime_force_resume)
 397 };
 398
 399 static int status_show(struct seq_file *s, void *data)
 400 {
 401         struct ti_sn65dsi86 *pdata = s->private;
 402         unsigned int reg, val;
 403
 404         seq_puts(s, "STATUS REGISTERS:\n");
 405
 406         pm_runtime_get_sync(pdata->dev);
 407
 408         /* IRQ Status Registers, see Table 31 in datasheet */
 409         for (reg = 0xf0; reg <= 0xf8; reg++) {
 410                 regmap_read(pdata->regmap, reg, &val);
 411                 seq_printf(s, "[0x%02x] = 0x%08x\n", reg, val);
 412         }
 413
 414         pm_runtime_put_autosuspend(pdata->dev);
 415
 416         return 0;
 417 }
 418
 419 DEFINE_SHOW_ATTRIBUTE(status);
 420
 421 static void ti_sn65dsi86_debugfs_remove(void *data)
 422 {
 423         debugfs_remove_recursive(data);
 424 }
 425
 426 static void ti_sn65dsi86_debugfs_init(struct ti_sn65dsi86 *pdata)
 427 {
 428         struct device *dev = pdata->dev;
 429         struct dentry *debugfs;
 430         int ret;
 431
 432         debugfs = debugfs_create_dir(dev_name(dev), NULL);
 433
 434         /*
 435          * We might get an error back if debugfs wasn't enabled in the kernel
 436          * so let's just silently return upon failure.
 437          */
 438         if (IS_ERR_OR_NULL(debugfs))
 439                 return;
 440
 441         ret = devm_add_action_or_reset(dev, ti_sn65dsi86_debugfs_remove, debugfs);
 442         if (ret)
 443                 return;
 444
 445         debugfs_create_file("status", 0600, debugfs, pdata, &status_fops);
 446 }
 447
 448 /* -----------------------------------------------------------------------------
 449  * Auxiliary Devices (*not* AUX)
 450  */
 451
 452 static void ti_sn65dsi86_uninit_aux(void *data)
 453 {
 454         auxiliary_device_uninit(data);
 455 }
 456
 457 static void ti_sn65dsi86_delete_aux(void *data)
 458 {
 459         auxiliary_device_delete(data);
 460 }
 461
 462 /*
 463  * AUX bus docs say that a non-NULL release is mandatory, but it makes no
 464  * sense for the model used here where all of the aux devices are allocated
 465  * in the single shared structure. We'll use this noop as a workaround.
 466  */
 467 static void ti_sn65dsi86_noop(struct device *dev) {}
 468
 469 static int ti_sn65dsi86_add_aux_device(struct ti_sn65dsi86 *pdata,
 470                                        struct auxiliary_device *aux,
 471                                        const char *name)
 472 {
 473         struct device *dev = pdata->dev;
 474         int ret;
 475
 476         aux->name = name;
 477         aux->dev.parent = dev;
 478         aux->dev.release = ti_sn65dsi86_noop;
 479         device_set_of_node_from_dev(&aux->dev, dev);
 480         ret = auxiliary_device_init(aux);
 481         if (ret)
 482                 return ret;
 483         ret = devm_add_action_or_reset(dev, ti_sn65dsi86_uninit_aux, aux);
 484         if (ret)
 485                 return ret;
 486
 487         ret = auxiliary_device_add(aux);
 488         if (ret)
 489                 return ret;
 490         ret = devm_add_action_or_reset(dev, ti_sn65dsi86_delete_aux, aux);
 491
 492         return ret;
 493 }
 494
 495 /* -----------------------------------------------------------------------------
 496  * AUX Adapter
 497  */
 498
 499 static struct ti_sn65dsi86 *aux_to_ti_sn65dsi86(struct drm_dp_aux *aux)
 500 {
 501         return container_of(aux, struct ti_sn65dsi86, aux);
 502 }
 503
 504 static ssize_t ti_sn_aux_transfer(struct drm_dp_aux *aux,
 505                                   struct drm_dp_aux_msg *msg)
 506 {
 507         struct ti_sn65dsi86 *pdata = aux_to_ti_sn65dsi86(aux);
 508         u32 request = msg->request & ~(DP_AUX_I2C_MOT | DP_AUX_I2C_WRITE_STATUS_UPDATE);
 509         u32 request_val = AUX_CMD_REQ(msg->request);
 510         u8 *buf = msg->buffer;
 511         unsigned int len = msg->size;
 512         unsigned int val;
 513         int ret;
 514         u8 addr_len[SN_AUX_LENGTH_REG + 1 - SN_AUX_ADDR_19_16_REG];
 515
 516         if (len > SN_AUX_MAX_PAYLOAD_BYTES)
 517                 return -EINVAL;
 518
 519         pm_runtime_get_sync(pdata->dev);
 520         mutex_lock(&pdata->comms_mutex);
 521
 522         /*
 523          * If someone tries to do a DDC over AUX transaction before pre_enable()
 524          * on a device without a dedicated reference clock then we just can't
 525          * do it. Fail right away. This prevents non-refclk users from reading
 526          * the EDID before enabling the panel but such is life.
 527          */
 528         if (!pdata->comms_enabled) {
 529                 ret = -EIO;
 530                 goto exit;
 531         }
 532
 533         switch (request) {
 534         case DP_AUX_NATIVE_WRITE:
 535         case DP_AUX_I2C_WRITE:
 536         case DP_AUX_NATIVE_READ:
 537         case DP_AUX_I2C_READ:
 538                 regmap_write(pdata->regmap, SN_AUX_CMD_REG, request_val);
 539                 /* Assume it's good */
 540                 msg->reply = 0;
 541                 break;
 542         default:
 543                 ret = -EINVAL;
 544                 goto exit;
 545         }
 546
 547         BUILD_BUG_ON(sizeof(addr_len) != sizeof(__be32));
 548         put_unaligned_be32((msg->address & SN_AUX_ADDR_MASK) << 8 | len,
 549                            addr_len);
 550         regmap_bulk_write(pdata->regmap, SN_AUX_ADDR_19_16_REG, addr_len,
 551                           ARRAY_SIZE(addr_len));
 552
 553         if (request == DP_AUX_NATIVE_WRITE || request == DP_AUX_I2C_WRITE)
 554                 regmap_bulk_write(pdata->regmap, SN_AUX_WDATA_REG(0), buf, len);
 555
 556         /* Clear old status bits before start so we don't get confused */
 557         regmap_write(pdata->regmap, SN_AUX_CMD_STATUS_REG,
 558                      AUX_IRQ_STATUS_NAT_I2C_FAIL |
 559                      AUX_IRQ_STATUS_AUX_RPLY_TOUT |
 560                      AUX_IRQ_STATUS_AUX_SHORT);
 561
 562         regmap_write(pdata->regmap, SN_AUX_CMD_REG, request_val | AUX_CMD_SEND);
 563
 564         /* Zero delay loop because i2c transactions are slow already */
 565         ret = regmap_read_poll_timeout(pdata->regmap, SN_AUX_CMD_REG, val,
 566                                        !(val & AUX_CMD_SEND), 0, 50 * 1000);
 567         if (ret)
 568                 goto exit;
 569
 570         ret = regmap_read(pdata->regmap, SN_AUX_CMD_STATUS_REG, &val);
 571         if (ret)
 572                 goto exit;
 573
 574         if (val & AUX_IRQ_STATUS_AUX_RPLY_TOUT) {
 575                 /*
 576                  * The hardware tried the message seven times per the DP spec
 577                  * but it hit a timeout. We ignore defers here because they're
 578                  * handled in hardware.
 579                  */
 580                 ret = -ETIMEDOUT;
 581                 goto exit;
 582         }
 583
 584         if (val & AUX_IRQ_STATUS_AUX_SHORT) {
 585                 ret = regmap_read(pdata->regmap, SN_AUX_LENGTH_REG, &len);
 586                 if (ret)
 587                         goto exit;
 588         } else if (val & AUX_IRQ_STATUS_NAT_I2C_FAIL) {
 589                 switch (request) {
 590                 case DP_AUX_I2C_WRITE:
 591                 case DP_AUX_I2C_READ:
 592                         msg->reply |= DP_AUX_I2C_REPLY_NACK;
 593                         break;
 594                 case DP_AUX_NATIVE_READ:
 595                 case DP_AUX_NATIVE_WRITE:
 596                         msg->reply |= DP_AUX_NATIVE_REPLY_NACK;
 597                         break;
 598                 }
 599                 len = 0;
 600                 goto exit;
 601         }
 602
 603         if (request != DP_AUX_NATIVE_WRITE && request != DP_AUX_I2C_WRITE && len != 0)
 604                 ret = regmap_bulk_read(pdata->regmap, SN_AUX_RDATA_REG(0), buf, len);
 605
 606 exit:
 607         mutex_unlock(&pdata->comms_mutex);
 608         pm_runtime_mark_last_busy(pdata->dev);
 609         pm_runtime_put_autosuspend(pdata->dev);
 610
 611         if (ret)
 612                 return ret;
 613         return len;
 614 }
 615
 616 static int ti_sn_aux_probe(struct auxiliary_device *adev,
 617                            const struct auxiliary_device_id *id)
 618 {
 619         struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent);
 620         int ret;
 621
 622         pdata->aux.name = "ti-sn65dsi86-aux";
 623         pdata->aux.dev = &adev->dev;
 624         pdata->aux.transfer = ti_sn_aux_transfer;
 625         drm_dp_aux_init(&pdata->aux);
 626
 627         ret = devm_of_dp_aux_populate_ep_devices(&pdata->aux);
 628         if (ret)
 629                 return ret;
 630
 631         /*
 632          * The eDP to MIPI bridge parts don't work until the AUX channel is
 633          * setup so we don't add it in the main driver probe, we add it now.
 634          */
 635         return ti_sn65dsi86_add_aux_device(pdata, &pdata->bridge_aux, "bridge");
 636 }
 637
 638 static const struct auxiliary_device_id ti_sn_aux_id_table[] = {
 639         { .name = "ti_sn65dsi86.aux", },
 640         {},
 641 };
 642
 643 static struct auxiliary_driver ti_sn_aux_driver = {
 644         .name = "aux",
 645         .probe = ti_sn_aux_probe,
 646         .id_table = ti_sn_aux_id_table,
 647 };
 648
 649 /* -----------------------------------------------------------------------------
 650  * DRM Connector Operations
 651  */
 652
 653 static struct ti_sn65dsi86 *
 654 connector_to_ti_sn65dsi86(struct drm_connector *connector)
 655 {
 656         return container_of(connector, struct ti_sn65dsi86, connector);
 657 }
 658
 659 static int ti_sn_bridge_connector_get_modes(struct drm_connector *connector)
 660 {
 661         struct ti_sn65dsi86 *pdata = connector_to_ti_sn65dsi86(connector);
 662
 663         return drm_bridge_get_modes(pdata->next_bridge, connector);
 664 }
 665
 666 static struct drm_connector_helper_funcs ti_sn_bridge_connector_helper_funcs = {
 667         .get_modes = ti_sn_bridge_connector_get_modes,
 668 };
 669
 670 static const struct drm_connector_funcs ti_sn_bridge_connector_funcs = {
 671         .fill_modes = drm_helper_probe_single_connector_modes,
 672         .destroy = drm_connector_cleanup,
 673         .reset = drm_atomic_helper_connector_reset,
 674         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
 675         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 676 };
 677
 678 static int ti_sn_bridge_connector_init(struct ti_sn65dsi86 *pdata)
 679 {
 680         int ret;
 681
 682         ret = drm_connector_init(pdata->bridge.dev, &pdata->connector,
 683                                  &ti_sn_bridge_connector_funcs,
 684                                  DRM_MODE_CONNECTOR_eDP);
 685         if (ret) {
 686                 DRM_ERROR("Failed to initialize connector with drm\n");
 687                 return ret;
 688         }
 689
 690         drm_connector_helper_add(&pdata->connector,
 691                                  &ti_sn_bridge_connector_helper_funcs);
 692         drm_connector_attach_encoder(&pdata->connector, pdata->bridge.encoder);
 693
 694         return 0;
 695 }
 696
 697 /*------------------------------------------------------------------------------
 698  * DRM Bridge
 699  */
 700
 701 static struct ti_sn65dsi86 *bridge_to_ti_sn65dsi86(struct drm_bridge *bridge)
 702 {
 703         return container_of(bridge, struct ti_sn65dsi86, bridge);
 704 }
 705
 706 static int ti_sn_attach_host(struct ti_sn65dsi86 *pdata)
 707 {
 708         int val;
 709         struct mipi_dsi_host *host;
 710         struct mipi_dsi_device *dsi;
 711         struct device *dev = pdata->dev;
 712         const struct mipi_dsi_device_info info = { .type = "ti_sn_bridge",
 713                                                    .channel = 0,
 714                                                    .node = NULL,
 715         };
 716
 717         host = of_find_mipi_dsi_host_by_node(pdata->host_node);
 718         if (!host)
 719                 return -EPROBE_DEFER;
 720
 721         dsi = devm_mipi_dsi_device_register_full(dev, host, &info);
 722         if (IS_ERR(dsi))
 723                 return PTR_ERR(dsi);
 724
 725         /* TODO: setting to 4 MIPI lanes always for now */
 726         dsi->lanes = 4;
 727         dsi->format = MIPI_DSI_FMT_RGB888;
 728         dsi->mode_flags = MIPI_DSI_MODE_VIDEO;
 729
 730         /* check if continuous dsi clock is required or not */
 731         pm_runtime_get_sync(dev);
 732         regmap_read(pdata->regmap, SN_DPPLL_SRC_REG, &val);
 733         pm_runtime_put_autosuspend(dev);
 734         if (!(val & DPPLL_CLK_SRC_DSICLK))
 735                 dsi->mode_flags |= MIPI_DSI_CLOCK_NON_CONTINUOUS;
 736
 737         pdata->dsi = dsi;
 738
 739         return devm_mipi_dsi_attach(dev, dsi);
 740 }
 741
 742 static int ti_sn_bridge_attach(struct drm_bridge *bridge,
 743                                enum drm_bridge_attach_flags flags)
 744 {
 745         struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
 746         int ret;
 747
 748         if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR) {
 749                 DRM_ERROR("Fix bridge driver to make connector optional!");
 750                 return -EINVAL;
 751         }
 752
 753         pdata->aux.drm_dev = bridge->dev;
 754         ret = drm_dp_aux_register(&pdata->aux);
 755         if (ret < 0) {
 756                 drm_err(bridge->dev, "Failed to register DP AUX channel: %d\n", ret);
 757                 return ret;
 758         }
 759
 760         ret = ti_sn_bridge_connector_init(pdata);
 761         if (ret < 0)
 762                 goto err_conn_init;
 763
 764         /* We never want the next bridge to *also* create a connector: */
 765         flags |= DRM_BRIDGE_ATTACH_NO_CONNECTOR;
 766
 767         /* Attach the next bridge */
 768         ret = drm_bridge_attach(bridge->encoder, pdata->next_bridge,
 769                                 &pdata->bridge, flags);
 770         if (ret < 0)
 771                 goto err_dsi_host;
 772
 773         return 0;
 774
 775 err_dsi_host:
 776         drm_connector_cleanup(&pdata->connector);
 777 err_conn_init:
 778         drm_dp_aux_unregister(&pdata->aux);
 779         return ret;
 780 }
 781
 782 static void ti_sn_bridge_detach(struct drm_bridge *bridge)
 783 {
 784         drm_dp_aux_unregister(&bridge_to_ti_sn65dsi86(bridge)->aux);
 785 }
 786
 787 static enum drm_mode_status
 788 ti_sn_bridge_mode_valid(struct drm_bridge *bridge,
 789                         const struct drm_display_info *info,
 790                         const struct drm_display_mode *mode)
 791 {
 792         /* maximum supported resolution is 4K at 60 fps */
 793         if (mode->clock > 594000)
 794                 return MODE_CLOCK_HIGH;
 795
 796         return MODE_OK;
 797 }
 798
 799 static void ti_sn_bridge_disable(struct drm_bridge *bridge)
 800 {
 801         struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
 802
 803         /* disable video stream */
 804         regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, VSTREAM_ENABLE, 0);
 805 }
 806
 807 static void ti_sn_bridge_set_dsi_rate(struct ti_sn65dsi86 *pdata)
 808 {
 809         unsigned int bit_rate_mhz, clk_freq_mhz;
 810         unsigned int val;
 811         struct drm_display_mode *mode =
 812                 &pdata->bridge.encoder->crtc->state->adjusted_mode;
 813
 814         /* set DSIA clk frequency */
 815         bit_rate_mhz = (mode->clock / 1000) *
 816                         mipi_dsi_pixel_format_to_bpp(pdata->dsi->format);
 817         clk_freq_mhz = bit_rate_mhz / (pdata->dsi->lanes * 2);
 818
 819         /* for each increment in val, frequency increases by 5MHz */
 820         val = (MIN_DSI_CLK_FREQ_MHZ / 5) +
 821                 (((clk_freq_mhz - MIN_DSI_CLK_FREQ_MHZ) / 5) & 0xFF);
 822         regmap_write(pdata->regmap, SN_DSIA_CLK_FREQ_REG, val);
 823 }
 824
 825 static unsigned int ti_sn_bridge_get_bpp(struct ti_sn65dsi86 *pdata)
 826 {
 827         if (pdata->connector.display_info.bpc <= 6)
 828                 return 18;
 829         else
 830                 return 24;
 831 }
 832
 833 /*
 834  * LUT index corresponds to register value and
 835  * LUT values corresponds to dp data rate supported
 836  * by the bridge in Mbps unit.
 837  */
 838 static const unsigned int ti_sn_bridge_dp_rate_lut[] = {
 839         0, 1620, 2160, 2430, 2700, 3240, 4320, 5400
 840 };
 841
 842 static int ti_sn_bridge_calc_min_dp_rate_idx(struct ti_sn65dsi86 *pdata)
 843 {
 844         unsigned int bit_rate_khz, dp_rate_mhz;
 845         unsigned int i;
 846         struct drm_display_mode *mode =
 847                 &pdata->bridge.encoder->crtc->state->adjusted_mode;
 848
 849         /* Calculate minimum bit rate based on our pixel clock. */
 850         bit_rate_khz = mode->clock * ti_sn_bridge_get_bpp(pdata);
 851
 852         /* Calculate minimum DP data rate, taking 80% as per DP spec */
 853         dp_rate_mhz = DIV_ROUND_UP(bit_rate_khz * DP_CLK_FUDGE_NUM,
 854                                    1000 * pdata->dp_lanes * DP_CLK_FUDGE_DEN);
 855
 856         for (i = 1; i < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut) - 1; i++)
 857                 if (ti_sn_bridge_dp_rate_lut[i] >= dp_rate_mhz)
 858                         break;
 859
 860         return i;
 861 }
 862
 863 static unsigned int ti_sn_bridge_read_valid_rates(struct ti_sn65dsi86 *pdata)
 864 {
 865         unsigned int valid_rates = 0;
 866         unsigned int rate_per_200khz;
 867         unsigned int rate_mhz;
 868         u8 dpcd_val;
 869         int ret;
 870         int i, j;
 871
 872         ret = drm_dp_dpcd_readb(&pdata->aux, DP_EDP_DPCD_REV, &dpcd_val);
 873         if (ret != 1) {
 874                 DRM_DEV_ERROR(pdata->dev,
 875                               "Can't read eDP rev (%d), assuming 1.1\n", ret);
 876                 dpcd_val = DP_EDP_11;
 877         }
 878
 879         if (dpcd_val >= DP_EDP_14) {
 880                 /* eDP 1.4 devices must provide a custom table */
 881                 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
 882
 883                 ret = drm_dp_dpcd_read(&pdata->aux, DP_SUPPORTED_LINK_RATES,
 884                                        sink_rates, sizeof(sink_rates));
 885
 886                 if (ret != sizeof(sink_rates)) {
 887                         DRM_DEV_ERROR(pdata->dev,
 888                                 "Can't read supported rate table (%d)\n", ret);
 889
 890                         /* By zeroing we'll fall back to DP_MAX_LINK_RATE. */
 891                         memset(sink_rates, 0, sizeof(sink_rates));
 892                 }
 893
 894                 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
 895                         rate_per_200khz = le16_to_cpu(sink_rates[i]);
 896
 897                         if (!rate_per_200khz)
 898                                 break;
 899
 900                         rate_mhz = rate_per_200khz * 200 / 1000;
 901                         for (j = 0;
 902                              j < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut);
 903                              j++) {
 904                                 if (ti_sn_bridge_dp_rate_lut[j] == rate_mhz)
 905                                         valid_rates |= BIT(j);
 906                         }
 907                 }
 908
 909                 for (i = 0; i < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut); i++) {
 910                         if (valid_rates & BIT(i))
 911                                 return valid_rates;
 912                 }
 913                 DRM_DEV_ERROR(pdata->dev,
 914                               "No matching eDP rates in table; falling back\n");
 915         }
 916
 917         /* On older versions best we can do is use DP_MAX_LINK_RATE */
 918         ret = drm_dp_dpcd_readb(&pdata->aux, DP_MAX_LINK_RATE, &dpcd_val);
 919         if (ret != 1) {
 920                 DRM_DEV_ERROR(pdata->dev,
 921                               "Can't read max rate (%d); assuming 5.4 GHz\n",
 922                               ret);
 923                 dpcd_val = DP_LINK_BW_5_4;
 924         }
 925
 926         switch (dpcd_val) {
 927         default:
 928                 DRM_DEV_ERROR(pdata->dev,
 929                               "Unexpected max rate (%#x); assuming 5.4 GHz\n",
 930                               (int)dpcd_val);
 931                 fallthrough;
 932         case DP_LINK_BW_5_4:
 933                 valid_rates |= BIT(7);
 934                 fallthrough;
 935         case DP_LINK_BW_2_7:
 936                 valid_rates |= BIT(4);
 937                 fallthrough;
 938         case DP_LINK_BW_1_62:
 939                 valid_rates |= BIT(1);
 940                 break;
 941         }
 942
 943         return valid_rates;
 944 }
 945
 946 static void ti_sn_bridge_set_video_timings(struct ti_sn65dsi86 *pdata)
 947 {
 948         struct drm_display_mode *mode =
 949                 &pdata->bridge.encoder->crtc->state->adjusted_mode;
 950         u8 hsync_polarity = 0, vsync_polarity = 0;
 951
 952         if (mode->flags & DRM_MODE_FLAG_PHSYNC)
 953                 hsync_polarity = CHA_HSYNC_POLARITY;
 954         if (mode->flags & DRM_MODE_FLAG_PVSYNC)
 955                 vsync_polarity = CHA_VSYNC_POLARITY;
 956
 957         ti_sn65dsi86_write_u16(pdata, SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG,
 958                                mode->hdisplay);
 959         ti_sn65dsi86_write_u16(pdata, SN_CHA_VERTICAL_DISPLAY_SIZE_LOW_REG,
 960                                mode->vdisplay);
 961         regmap_write(pdata->regmap, SN_CHA_HSYNC_PULSE_WIDTH_LOW_REG,
 962                      (mode->hsync_end - mode->hsync_start) & 0xFF);
 963         regmap_write(pdata->regmap, SN_CHA_HSYNC_PULSE_WIDTH_HIGH_REG,
 964                      (((mode->hsync_end - mode->hsync_start) >> 8) & 0x7F) |
 965                      hsync_polarity);
 966         regmap_write(pdata->regmap, SN_CHA_VSYNC_PULSE_WIDTH_LOW_REG,
 967                      (mode->vsync_end - mode->vsync_start) & 0xFF);
 968         regmap_write(pdata->regmap, SN_CHA_VSYNC_PULSE_WIDTH_HIGH_REG,
 969                      (((mode->vsync_end - mode->vsync_start) >> 8) & 0x7F) |
 970                      vsync_polarity);
 971
 972         regmap_write(pdata->regmap, SN_CHA_HORIZONTAL_BACK_PORCH_REG,
 973                      (mode->htotal - mode->hsync_end) & 0xFF);
 974         regmap_write(pdata->regmap, SN_CHA_VERTICAL_BACK_PORCH_REG,
 975                      (mode->vtotal - mode->vsync_end) & 0xFF);
 976
 977         regmap_write(pdata->regmap, SN_CHA_HORIZONTAL_FRONT_PORCH_REG,
 978                      (mode->hsync_start - mode->hdisplay) & 0xFF);
 979         regmap_write(pdata->regmap, SN_CHA_VERTICAL_FRONT_PORCH_REG,
 980                      (mode->vsync_start - mode->vdisplay) & 0xFF);
 981
 982         usleep_range(10000, 10500); /* 10ms delay recommended by spec */
 983 }
 984
 985 static unsigned int ti_sn_get_max_lanes(struct ti_sn65dsi86 *pdata)
 986 {
 987         u8 data;
 988         int ret;
 989
 990         ret = drm_dp_dpcd_readb(&pdata->aux, DP_MAX_LANE_COUNT, &data);
 991         if (ret != 1) {
 992                 DRM_DEV_ERROR(pdata->dev,
 993                               "Can't read lane count (%d); assuming 4\n", ret);
 994                 return 4;
 995         }
 996
 997         return data & DP_LANE_COUNT_MASK;
 998 }
 999
1000 static int ti_sn_link_training(struct ti_sn65dsi86 *pdata, int dp_rate_idx,
1001                                const char **last_err_str)
1002 {
1003         unsigned int val;
1004         int ret;
1005         int i;
1006
1007         /* set dp clk frequency value */
1008         regmap_update_bits(pdata->regmap, SN_DATARATE_CONFIG_REG,
1009                            DP_DATARATE_MASK, DP_DATARATE(dp_rate_idx));
1010
1011         /* enable DP PLL */
1012         regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 1);
1013
1014         ret = regmap_read_poll_timeout(pdata->regmap, SN_DPPLL_SRC_REG, val,
1015                                        val & DPPLL_SRC_DP_PLL_LOCK, 1000,
1016                                        50 * 1000);
1017         if (ret) {
1018                 *last_err_str = "DP_PLL_LOCK polling failed";
1019                 goto exit;
1020         }
1021
1022         /*
1023          * We'll try to link train several times.  As part of link training
1024          * the bridge chip will write DP_SET_POWER_D0 to DP_SET_POWER.  If
1025          * the panel isn't ready quite it might respond NAK here which means
1026          * we need to try again.
1027          */
1028         for (i = 0; i < SN_LINK_TRAINING_TRIES; i++) {
1029                 /* Semi auto link training mode */
1030                 regmap_write(pdata->regmap, SN_ML_TX_MODE_REG, 0x0A);
1031                 ret = regmap_read_poll_timeout(pdata->regmap, SN_ML_TX_MODE_REG, val,
1032                                                val == ML_TX_MAIN_LINK_OFF ||
1033                                                val == ML_TX_NORMAL_MODE, 1000,
1034                                                500 * 1000);
1035                 if (ret) {
1036                         *last_err_str = "Training complete polling failed";
1037                 } else if (val == ML_TX_MAIN_LINK_OFF) {
1038                         *last_err_str = "Link training failed, link is off";
1039                         ret = -EIO;
1040                         continue;
1041                 }
1042
1043                 break;
1044         }
1045
1046         /* If we saw quite a few retries, add a note about it */
1047         if (!ret && i > SN_LINK_TRAINING_TRIES / 2)
1048                 DRM_DEV_INFO(pdata->dev, "Link training needed %d retries\n", i);
1049
1050 exit:
1051         /* Disable the PLL if we failed */
1052         if (ret)
1053                 regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 0);
1054
1055         return ret;
1056 }
1057
1058 static void ti_sn_bridge_enable(struct drm_bridge *bridge)
1059 {
1060         struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
1061         const char *last_err_str = "No supported DP rate";
1062         unsigned int valid_rates;
1063         int dp_rate_idx;
1064         unsigned int val;
1065         int ret = -EINVAL;
1066         int max_dp_lanes;
1067
1068         max_dp_lanes = ti_sn_get_max_lanes(pdata);
1069         pdata->dp_lanes = min(pdata->dp_lanes, max_dp_lanes);
1070
1071         /* DSI_A lane config */
1072         val = CHA_DSI_LANES(SN_MAX_DP_LANES - pdata->dsi->lanes);
1073         regmap_update_bits(pdata->regmap, SN_DSI_LANES_REG,
1074                            CHA_DSI_LANES_MASK, val);
1075
1076         regmap_write(pdata->regmap, SN_LN_ASSIGN_REG, pdata->ln_assign);
1077         regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, LN_POLRS_MASK,
1078                            pdata->ln_polrs << LN_POLRS_OFFSET);
1079
1080         /* set dsi clk frequency value */
1081         ti_sn_bridge_set_dsi_rate(pdata);
1082
1083         /*
1084          * The SN65DSI86 only supports ASSR Display Authentication method and
1085          * this method is enabled by default. An eDP panel must support this
1086          * authentication method. We need to enable this method in the eDP panel
1087          * at DisplayPort address 0x0010A prior to link training.
1088          */
1089         drm_dp_dpcd_writeb(&pdata->aux, DP_EDP_CONFIGURATION_SET,
1090                            DP_ALTERNATE_SCRAMBLER_RESET_ENABLE);
1091
1092         /* Set the DP output format (18 bpp or 24 bpp) */
1093         val = (ti_sn_bridge_get_bpp(pdata) == 18) ? BPP_18_RGB : 0;
1094         regmap_update_bits(pdata->regmap, SN_DATA_FORMAT_REG, BPP_18_RGB, val);
1095
1096         /* DP lane config */
1097         val = DP_NUM_LANES(min(pdata->dp_lanes, 3));
1098         regmap_update_bits(pdata->regmap, SN_SSC_CONFIG_REG, DP_NUM_LANES_MASK,
1099                            val);
1100
1101         valid_rates = ti_sn_bridge_read_valid_rates(pdata);
1102
1103         /* Train until we run out of rates */
1104         for (dp_rate_idx = ti_sn_bridge_calc_min_dp_rate_idx(pdata);
1105              dp_rate_idx < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut);
1106              dp_rate_idx++) {
1107                 if (!(valid_rates & BIT(dp_rate_idx)))
1108                         continue;
1109
1110                 ret = ti_sn_link_training(pdata, dp_rate_idx, &last_err_str);
1111                 if (!ret)
1112                         break;
1113         }
1114         if (ret) {
1115                 DRM_DEV_ERROR(pdata->dev, "%s (%d)\n", last_err_str, ret);
1116                 return;
1117         }
1118
1119         /* config video parameters */
1120         ti_sn_bridge_set_video_timings(pdata);
1121
1122         /* enable video stream */
1123         regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, VSTREAM_ENABLE,
1124                            VSTREAM_ENABLE);
1125 }
1126
1127 static void ti_sn_bridge_pre_enable(struct drm_bridge *bridge)
1128 {
1129         struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
1130
1131         pm_runtime_get_sync(pdata->dev);
1132
1133         if (!pdata->refclk)
1134                 ti_sn65dsi86_enable_comms(pdata);
1135
1136         /* td7: min 100 us after enable before DSI data */
1137         usleep_range(100, 110);
1138 }
1139
1140 static void ti_sn_bridge_post_disable(struct drm_bridge *bridge)
1141 {
1142         struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
1143
1144         /* semi auto link training mode OFF */
1145         regmap_write(pdata->regmap, SN_ML_TX_MODE_REG, 0);
1146         /* Num lanes to 0 as per power sequencing in data sheet */
1147         regmap_update_bits(pdata->regmap, SN_SSC_CONFIG_REG, DP_NUM_LANES_MASK, 0);
1148         /* disable DP PLL */
1149         regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 0);
1150
1151         if (!pdata->refclk)
1152                 ti_sn65dsi86_disable_comms(pdata);
1153
1154         pm_runtime_put_sync(pdata->dev);
1155 }
1156
1157 static const struct drm_bridge_funcs ti_sn_bridge_funcs = {
1158         .attach = ti_sn_bridge_attach,
1159         .detach = ti_sn_bridge_detach,
1160         .mode_valid = ti_sn_bridge_mode_valid,
1161         .pre_enable = ti_sn_bridge_pre_enable,
1162         .enable = ti_sn_bridge_enable,
1163         .disable = ti_sn_bridge_disable,
1164         .post_disable = ti_sn_bridge_post_disable,
1165 };
1166
1167 static void ti_sn_bridge_parse_lanes(struct ti_sn65dsi86 *pdata,
1168                                      struct device_node *np)
1169 {
1170         u32 lane_assignments[SN_MAX_DP_LANES] = { 0, 1, 2, 3 };
1171         u32 lane_polarities[SN_MAX_DP_LANES] = { };
1172         struct device_node *endpoint;
1173         u8 ln_assign = 0;
1174         u8 ln_polrs = 0;
1175         int dp_lanes;
1176         int i;
1177
1178         /*
1179          * Read config from the device tree about lane remapping and lane
1180          * polarities.  These are optional and we assume identity map and
1181          * normal polarity if nothing is specified.  It's OK to specify just
1182          * data-lanes but not lane-polarities but not vice versa.
1183          *
1184          * Error checking is light (we just make sure we don't crash or
1185          * buffer overrun) and we assume dts is well formed and specifying
1186          * mappings that the hardware supports.
1187          */
1188         endpoint = of_graph_get_endpoint_by_regs(np, 1, -1);
1189         dp_lanes = of_property_count_u32_elems(endpoint, "data-lanes");
1190         if (dp_lanes > 0 && dp_lanes <= SN_MAX_DP_LANES) {
1191                 of_property_read_u32_array(endpoint, "data-lanes",
1192                                            lane_assignments, dp_lanes);
1193                 of_property_read_u32_array(endpoint, "lane-polarities",
1194                                            lane_polarities, dp_lanes);
1195         } else {
1196                 dp_lanes = SN_MAX_DP_LANES;
1197         }
1198         of_node_put(endpoint);
1199
1200         /*
1201          * Convert into register format.  Loop over all lanes even if
1202          * data-lanes had fewer elements so that we nicely initialize
1203          * the LN_ASSIGN register.
1204          */
1205         for (i = SN_MAX_DP_LANES - 1; i >= 0; i--) {
1206                 ln_assign = ln_assign << LN_ASSIGN_WIDTH | lane_assignments[i];
1207                 ln_polrs = ln_polrs << 1 | lane_polarities[i];
1208         }
1209
1210         /* Stash in our struct for when we power on */
1211         pdata->dp_lanes = dp_lanes;
1212         pdata->ln_assign = ln_assign;
1213         pdata->ln_polrs = ln_polrs;
1214 }
1215
1216 static int ti_sn_bridge_parse_dsi_host(struct ti_sn65dsi86 *pdata)
1217 {
1218         struct device_node *np = pdata->dev->of_node;
1219
1220         pdata->host_node = of_graph_get_remote_node(np, 0, 0);
1221
1222         if (!pdata->host_node) {
1223                 DRM_ERROR("remote dsi host node not found\n");
1224                 return -ENODEV;
1225         }
1226
1227         return 0;
1228 }
1229
1230 static int ti_sn_bridge_probe(struct auxiliary_device *adev,
1231                               const struct auxiliary_device_id *id)
1232 {
1233         struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent);
1234         struct device_node *np = pdata->dev->of_node;
1235         struct drm_panel *panel;
1236         int ret;
1237
1238         ret = drm_of_find_panel_or_bridge(np, 1, 0, &panel, NULL);
1239         if (ret)
1240                 return dev_err_probe(&adev->dev, ret,
1241                                      "could not find any panel node\n");
1242
1243         pdata->next_bridge = devm_drm_panel_bridge_add(pdata->dev, panel);
1244         if (IS_ERR(pdata->next_bridge)) {
1245                 DRM_ERROR("failed to create panel bridge\n");
1246                 return PTR_ERR(pdata->next_bridge);
1247         }
1248
1249         ti_sn_bridge_parse_lanes(pdata, np);
1250
1251         ret = ti_sn_bridge_parse_dsi_host(pdata);
1252         if (ret)
1253                 return ret;
1254
1255         pdata->bridge.funcs = &ti_sn_bridge_funcs;
1256         pdata->bridge.of_node = np;
1257
1258         drm_bridge_add(&pdata->bridge);
1259
1260         ret = ti_sn_attach_host(pdata);
1261         if (ret) {
1262                 dev_err_probe(pdata->dev, ret, "failed to attach dsi host\n");
1263                 goto err_remove_bridge;
1264         }
1265
1266         return 0;
1267
1268 err_remove_bridge:
1269         drm_bridge_remove(&pdata->bridge);
1270         return ret;
1271 }
1272
1273 static void ti_sn_bridge_remove(struct auxiliary_device *adev)
1274 {
1275         struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent);
1276
1277         if (!pdata)
1278                 return;
1279
1280         drm_bridge_remove(&pdata->bridge);
1281
1282         of_node_put(pdata->host_node);
1283 }
1284
1285 static const struct auxiliary_device_id ti_sn_bridge_id_table[] = {
1286         { .name = "ti_sn65dsi86.bridge", },
1287         {},
1288 };
1289
1290 static struct auxiliary_driver ti_sn_bridge_driver = {
1291         .name = "bridge",
1292         .probe = ti_sn_bridge_probe,
1293         .remove = ti_sn_bridge_remove,
1294         .id_table = ti_sn_bridge_id_table,
1295 };
1296
1297 /* -----------------------------------------------------------------------------
1298  * PWM Controller
1299  */
1300 #if defined(CONFIG_PWM)
1301 static int ti_sn_pwm_pin_request(struct ti_sn65dsi86 *pdata)
1302 {
1303         return atomic_xchg(&pdata->pwm_pin_busy, 1) ? -EBUSY : 0;
1304 }
1305
1306 static void ti_sn_pwm_pin_release(struct ti_sn65dsi86 *pdata)
1307 {
1308         atomic_set(&pdata->pwm_pin_busy, 0);
1309 }
1310
1311 static struct ti_sn65dsi86 *pwm_chip_to_ti_sn_bridge(struct pwm_chip *chip)
1312 {
1313         return container_of(chip, struct ti_sn65dsi86, pchip);
1314 }
1315
1316 static int ti_sn_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
1317 {
1318         struct ti_sn65dsi86 *pdata = pwm_chip_to_ti_sn_bridge(chip);
1319
1320         return ti_sn_pwm_pin_request(pdata);
1321 }
1322
1323 static void ti_sn_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
1324 {
1325         struct ti_sn65dsi86 *pdata = pwm_chip_to_ti_sn_bridge(chip);
1326
1327         ti_sn_pwm_pin_release(pdata);
1328 }
1329
1330 /*
1331  * Limitations:
1332  * - The PWM signal is not driven when the chip is powered down, or in its
1333  *   reset state and the driver does not implement the "suspend state"
1334  *   described in the documentation. In order to save power, state->enabled is
1335  *   interpreted as denoting if the signal is expected to be valid, and is used
1336  *   to determine if the chip needs to be kept powered.
1337  * - Changing both period and duty_cycle is not done atomically, neither is the
1338  *   multi-byte register updates, so the output might briefly be undefined
1339  *   during update.
1340  */
1341 static int ti_sn_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
1342                            const struct pwm_state *state)
1343 {
1344         struct ti_sn65dsi86 *pdata = pwm_chip_to_ti_sn_bridge(chip);
1345         unsigned int pwm_en_inv;
1346         unsigned int backlight;
1347         unsigned int pre_div;
1348         unsigned int scale;
1349         u64 period_max;
1350         u64 period;
1351         int ret;
1352
1353         if (!pdata->pwm_enabled) {
1354                 ret = pm_runtime_get_sync(pdata->dev);
1355                 if (ret < 0) {
1356                         pm_runtime_put_sync(pdata->dev);
1357                         return ret;
1358                 }
1359         }
1360
1361         if (state->enabled) {
1362                 if (!pdata->pwm_enabled) {
1363                         /*
1364                          * The chip might have been powered down while we
1365                          * didn't hold a PM runtime reference, so mux in the
1366                          * PWM function on the GPIO pin again.
1367                          */
1368                         ret = regmap_update_bits(pdata->regmap, SN_GPIO_CTRL_REG,
1369                                                  SN_GPIO_MUX_MASK << (2 * SN_PWM_GPIO_IDX),
1370                                                  SN_GPIO_MUX_SPECIAL << (2 * SN_PWM_GPIO_IDX));
1371                         if (ret) {
1372                                 dev_err(pdata->dev, "failed to mux in PWM function\n");
1373                                 goto out;
1374                         }
1375                 }
1376
1377                 /*
1378                  * Per the datasheet the PWM frequency is given by:
1379                  *
1380                  *                          REFCLK_FREQ
1381                  *   PWM_FREQ = -----------------------------------
1382                  *               PWM_PRE_DIV * BACKLIGHT_SCALE + 1
1383                  *
1384                  * However, after careful review the author is convinced that
1385                  * the documentation has lost some parenthesis around
1386                  * "BACKLIGHT_SCALE + 1".
1387                  *
1388                  * With the period T_pwm = 1/PWM_FREQ this can be written:
1389                  *
1390                  *   T_pwm * REFCLK_FREQ = PWM_PRE_DIV * (BACKLIGHT_SCALE + 1)
1391                  *
1392                  * In order to keep BACKLIGHT_SCALE within its 16 bits,
1393                  * PWM_PRE_DIV must be:
1394                  *
1395                  *                     T_pwm * REFCLK_FREQ
1396                  *   PWM_PRE_DIV >= -------------------------
1397                  *                   BACKLIGHT_SCALE_MAX + 1
1398                  *
1399                  * To simplify the search and to favour higher resolution of
1400                  * the duty cycle over accuracy of the period, the lowest
1401                  * possible PWM_PRE_DIV is used. Finally the scale is
1402                  * calculated as:
1403                  *
1404                  *                      T_pwm * REFCLK_FREQ
1405                  *   BACKLIGHT_SCALE = ---------------------- - 1
1406                  *                          PWM_PRE_DIV
1407                  *
1408                  * Here T_pwm is represented in seconds, so appropriate scaling
1409                  * to nanoseconds is necessary.
1410                  */
1411
1412                 /* Minimum T_pwm is 1 / REFCLK_FREQ */
1413                 if (state->period <= NSEC_PER_SEC / pdata->pwm_refclk_freq) {
1414                         ret = -EINVAL;
1415                         goto out;
1416                 }
1417
1418                 /*
1419                  * Maximum T_pwm is 255 * (65535 + 1) / REFCLK_FREQ
1420                  * Limit period to this to avoid overflows
1421                  */
1422                 period_max = div_u64((u64)NSEC_PER_SEC * 255 * (65535 + 1),
1423                                      pdata->pwm_refclk_freq);
1424                 period = min(state->period, period_max);
1425
1426                 pre_div = DIV64_U64_ROUND_UP(period * pdata->pwm_refclk_freq,
1427                                              (u64)NSEC_PER_SEC * (BACKLIGHT_SCALE_MAX + 1));
1428                 scale = div64_u64(period * pdata->pwm_refclk_freq, (u64)NSEC_PER_SEC * pre_div) - 1;
1429
1430                 /*
1431                  * The documentation has the duty ratio given as:
1432                  *
1433                  *     duty          BACKLIGHT
1434                  *   ------- = ---------------------
1435                  *    period    BACKLIGHT_SCALE + 1
1436                  *
1437                  * Solve for BACKLIGHT, substituting BACKLIGHT_SCALE according
1438                  * to definition above and adjusting for nanosecond
1439                  * representation of duty cycle gives us:
1440                  */
1441                 backlight = div64_u64(state->duty_cycle * pdata->pwm_refclk_freq,
1442                                       (u64)NSEC_PER_SEC * pre_div);
1443                 if (backlight > scale)
1444                         backlight = scale;
1445
1446                 ret = regmap_write(pdata->regmap, SN_PWM_PRE_DIV_REG, pre_div);
1447                 if (ret) {
1448                         dev_err(pdata->dev, "failed to update PWM_PRE_DIV\n");
1449                         goto out;
1450                 }
1451
1452                 ti_sn65dsi86_write_u16(pdata, SN_BACKLIGHT_SCALE_REG, scale);
1453                 ti_sn65dsi86_write_u16(pdata, SN_BACKLIGHT_REG, backlight);
1454         }
1455
1456         pwm_en_inv = FIELD_PREP(SN_PWM_EN_MASK, state->enabled) |
1457                      FIELD_PREP(SN_PWM_INV_MASK, state->polarity == PWM_POLARITY_INVERSED);
1458         ret = regmap_write(pdata->regmap, SN_PWM_EN_INV_REG, pwm_en_inv);
1459         if (ret) {
1460                 dev_err(pdata->dev, "failed to update PWM_EN/PWM_INV\n");
1461                 goto out;
1462         }
1463
1464         pdata->pwm_enabled = state->enabled;
1465 out:
1466
1467         if (!pdata->pwm_enabled)
1468                 pm_runtime_put_sync(pdata->dev);
1469
1470         return ret;
1471 }
1472
1473 static void ti_sn_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
1474                                 struct pwm_state *state)
1475 {
1476         struct ti_sn65dsi86 *pdata = pwm_chip_to_ti_sn_bridge(chip);
1477         unsigned int pwm_en_inv;
1478         unsigned int pre_div;
1479         u16 backlight;
1480         u16 scale;
1481         int ret;
1482
1483         ret = regmap_read(pdata->regmap, SN_PWM_EN_INV_REG, &pwm_en_inv);
1484         if (ret)
1485                 return;
1486
1487         ret = ti_sn65dsi86_read_u16(pdata, SN_BACKLIGHT_SCALE_REG, &scale);
1488         if (ret)
1489                 return;
1490
1491         ret = ti_sn65dsi86_read_u16(pdata, SN_BACKLIGHT_REG, &backlight);
1492         if (ret)
1493                 return;
1494
1495         ret = regmap_read(pdata->regmap, SN_PWM_PRE_DIV_REG, &pre_div);
1496         if (ret)
1497                 return;
1498
1499         state->enabled = FIELD_GET(SN_PWM_EN_MASK, pwm_en_inv);
1500         if (FIELD_GET(SN_PWM_INV_MASK, pwm_en_inv))
1501                 state->polarity = PWM_POLARITY_INVERSED;
1502         else
1503                 state->polarity = PWM_POLARITY_NORMAL;
1504
1505         state->period = DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC * pre_div * (scale + 1),
1506                                          pdata->pwm_refclk_freq);
1507         state->duty_cycle = DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC * pre_div * backlight,
1508                                              pdata->pwm_refclk_freq);
1509
1510         if (state->duty_cycle > state->period)
1511                 state->duty_cycle = state->period;
1512 }
1513
1514 static const struct pwm_ops ti_sn_pwm_ops = {
1515         .request = ti_sn_pwm_request,
1516         .free = ti_sn_pwm_free,
1517         .apply = ti_sn_pwm_apply,
1518         .get_state = ti_sn_pwm_get_state,
1519         .owner = THIS_MODULE,
1520 };
1521
1522 static int ti_sn_pwm_probe(struct auxiliary_device *adev,
1523                            const struct auxiliary_device_id *id)
1524 {
1525         struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent);
1526
1527         pdata->pchip.dev = pdata->dev;
1528         pdata->pchip.ops = &ti_sn_pwm_ops;
1529         pdata->pchip.npwm = 1;
1530         pdata->pchip.of_xlate = of_pwm_single_xlate;
1531         pdata->pchip.of_pwm_n_cells = 1;
1532
1533         return pwmchip_add(&pdata->pchip);
1534 }
1535
1536 static void ti_sn_pwm_remove(struct auxiliary_device *adev)
1537 {
1538         struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent);
1539
1540         pwmchip_remove(&pdata->pchip);
1541
1542         if (pdata->pwm_enabled)
1543                 pm_runtime_put_sync(pdata->dev);
1544 }
1545
1546 static const struct auxiliary_device_id ti_sn_pwm_id_table[] = {
1547         { .name = "ti_sn65dsi86.pwm", },
1548         {},
1549 };
1550
1551 static struct auxiliary_driver ti_sn_pwm_driver = {
1552         .name = "pwm",
1553         .probe = ti_sn_pwm_probe,
1554         .remove = ti_sn_pwm_remove,
1555         .id_table = ti_sn_pwm_id_table,
1556 };
1557
1558 static int __init ti_sn_pwm_register(void)
1559 {
1560         return auxiliary_driver_register(&ti_sn_pwm_driver);
1561 }
1562
1563 static void ti_sn_pwm_unregister(void)
1564 {
1565         auxiliary_driver_unregister(&ti_sn_pwm_driver);
1566 }
1567
1568 #else
1569 static inline int ti_sn_pwm_pin_request(struct ti_sn65dsi86 *pdata) { return 0; }
1570 static inline void ti_sn_pwm_pin_release(struct ti_sn65dsi86 *pdata) {}
1571
1572 static inline int ti_sn_pwm_register(void) { return 0; }
1573 static inline void ti_sn_pwm_unregister(void) {}
1574 #endif
1575
1576 /* -----------------------------------------------------------------------------
1577  * GPIO Controller
1578  */
1579 #if defined(CONFIG_OF_GPIO)
1580
1581 static int tn_sn_bridge_of_xlate(struct gpio_chip *chip,
1582                                  const struct of_phandle_args *gpiospec,
1583                                  u32 *flags)
1584 {
1585         if (WARN_ON(gpiospec->args_count < chip->of_gpio_n_cells))
1586                 return -EINVAL;
1587
1588         if (gpiospec->args[0] > chip->ngpio || gpiospec->args[0] < 1)
1589                 return -EINVAL;
1590
1591         if (flags)
1592                 *flags = gpiospec->args[1];
1593
1594         return gpiospec->args[0] - SN_GPIO_PHYSICAL_OFFSET;
1595 }
1596
1597 static int ti_sn_bridge_gpio_get_direction(struct gpio_chip *chip,
1598                                            unsigned int offset)
1599 {
1600         struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip);
1601
1602         /*
1603          * We already have to keep track of the direction because we use
1604          * that to figure out whether we've powered the device.  We can
1605          * just return that rather than (maybe) powering up the device
1606          * to ask its direction.
1607          */
1608         return test_bit(offset, pdata->gchip_output) ?
1609                 GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN;
1610 }
1611
1612 static int ti_sn_bridge_gpio_get(struct gpio_chip *chip, unsigned int offset)
1613 {
1614         struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip);
1615         unsigned int val;
1616         int ret;
1617
1618         /*
1619          * When the pin is an input we don't forcibly keep the bridge
1620          * powered--we just power it on to read the pin.  NOTE: part of
1621          * the reason this works is that the bridge defaults (when
1622          * powered back on) to all 4 GPIOs being configured as GPIO input.
1623          * Also note that if something else is keeping the chip powered the
1624          * pm_runtime functions are lightweight increments of a refcount.
1625          */
1626         pm_runtime_get_sync(pdata->dev);
1627         ret = regmap_read(pdata->regmap, SN_GPIO_IO_REG, &val);
1628         pm_runtime_put_autosuspend(pdata->dev);
1629
1630         if (ret)
1631                 return ret;
1632
1633         return !!(val & BIT(SN_GPIO_INPUT_SHIFT + offset));
1634 }
1635
1636 static void ti_sn_bridge_gpio_set(struct gpio_chip *chip, unsigned int offset,
1637                                   int val)
1638 {
1639         struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip);
1640         int ret;
1641
1642         if (!test_bit(offset, pdata->gchip_output)) {
1643                 dev_err(pdata->dev, "Ignoring GPIO set while input\n");
1644                 return;
1645         }
1646
1647         val &= 1;
1648         ret = regmap_update_bits(pdata->regmap, SN_GPIO_IO_REG,
1649                                  BIT(SN_GPIO_OUTPUT_SHIFT + offset),
1650                                  val << (SN_GPIO_OUTPUT_SHIFT + offset));
1651         if (ret)
1652                 dev_warn(pdata->dev,
1653                          "Failed to set bridge GPIO %u: %d\n", offset, ret);
1654 }
1655
1656 static int ti_sn_bridge_gpio_direction_input(struct gpio_chip *chip,
1657                                              unsigned int offset)
1658 {
1659         struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip);
1660         int shift = offset * 2;
1661         int ret;
1662
1663         if (!test_and_clear_bit(offset, pdata->gchip_output))
1664                 return 0;
1665
1666         ret = regmap_update_bits(pdata->regmap, SN_GPIO_CTRL_REG,
1667                                  SN_GPIO_MUX_MASK << shift,
1668                                  SN_GPIO_MUX_INPUT << shift);
1669         if (ret) {
1670                 set_bit(offset, pdata->gchip_output);
1671                 return ret;
1672         }
1673
1674         /*
1675          * NOTE: if nobody else is powering the device this may fully power
1676          * it off and when it comes back it will have lost all state, but
1677          * that's OK because the default is input and we're now an input.
1678          */
1679         pm_runtime_put_autosuspend(pdata->dev);
1680
1681         return 0;
1682 }
1683
1684 static int ti_sn_bridge_gpio_direction_output(struct gpio_chip *chip,
1685                                               unsigned int offset, int val)
1686 {
1687         struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip);
1688         int shift = offset * 2;
1689         int ret;
1690
1691         if (test_and_set_bit(offset, pdata->gchip_output))
1692                 return 0;
1693
1694         pm_runtime_get_sync(pdata->dev);
1695
1696         /* Set value first to avoid glitching */
1697         ti_sn_bridge_gpio_set(chip, offset, val);
1698
1699         /* Set direction */
1700         ret = regmap_update_bits(pdata->regmap, SN_GPIO_CTRL_REG,
1701                                  SN_GPIO_MUX_MASK << shift,
1702                                  SN_GPIO_MUX_OUTPUT << shift);
1703         if (ret) {
1704                 clear_bit(offset, pdata->gchip_output);
1705                 pm_runtime_put_autosuspend(pdata->dev);
1706         }
1707
1708         return ret;
1709 }
1710
1711 static int ti_sn_bridge_gpio_request(struct gpio_chip *chip, unsigned int offset)
1712 {
1713         struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip);
1714
1715         if (offset == SN_PWM_GPIO_IDX)
1716                 return ti_sn_pwm_pin_request(pdata);
1717
1718         return 0;
1719 }
1720
1721 static void ti_sn_bridge_gpio_free(struct gpio_chip *chip, unsigned int offset)
1722 {
1723         struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip);
1724
1725         /* We won't keep pm_runtime if we're input, so switch there on free */
1726         ti_sn_bridge_gpio_direction_input(chip, offset);
1727
1728         if (offset == SN_PWM_GPIO_IDX)
1729                 ti_sn_pwm_pin_release(pdata);
1730 }
1731
1732 static const char * const ti_sn_bridge_gpio_names[SN_NUM_GPIOS] = {
1733         "GPIO1", "GPIO2", "GPIO3", "GPIO4"
1734 };
1735
1736 static int ti_sn_gpio_probe(struct auxiliary_device *adev,
1737                             const struct auxiliary_device_id *id)
1738 {
1739         struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent);
1740         int ret;
1741
1742         /* Only init if someone is going to use us as a GPIO controller */
1743         if (!of_property_read_bool(pdata->dev->of_node, "gpio-controller"))
1744                 return 0;
1745
1746         pdata->gchip.label = dev_name(pdata->dev);
1747         pdata->gchip.parent = pdata->dev;
1748         pdata->gchip.owner = THIS_MODULE;
1749         pdata->gchip.of_xlate = tn_sn_bridge_of_xlate;
1750         pdata->gchip.of_gpio_n_cells = 2;
1751         pdata->gchip.request = ti_sn_bridge_gpio_request;
1752         pdata->gchip.free = ti_sn_bridge_gpio_free;
1753         pdata->gchip.get_direction = ti_sn_bridge_gpio_get_direction;
1754         pdata->gchip.direction_input = ti_sn_bridge_gpio_direction_input;
1755         pdata->gchip.direction_output = ti_sn_bridge_gpio_direction_output;
1756         pdata->gchip.get = ti_sn_bridge_gpio_get;
1757         pdata->gchip.set = ti_sn_bridge_gpio_set;
1758         pdata->gchip.can_sleep = true;
1759         pdata->gchip.names = ti_sn_bridge_gpio_names;
1760         pdata->gchip.ngpio = SN_NUM_GPIOS;
1761         pdata->gchip.base = -1;
1762         ret = devm_gpiochip_add_data(&adev->dev, &pdata->gchip, pdata);
1763         if (ret)
1764                 dev_err(pdata->dev, "can't add gpio chip\n");
1765
1766         return ret;
1767 }
1768
1769 static const struct auxiliary_device_id ti_sn_gpio_id_table[] = {
1770         { .name = "ti_sn65dsi86.gpio", },
1771         {},
1772 };
1773
1774 MODULE_DEVICE_TABLE(auxiliary, ti_sn_gpio_id_table);
1775
1776 static struct auxiliary_driver ti_sn_gpio_driver = {
1777         .name = "gpio",
1778         .probe = ti_sn_gpio_probe,
1779         .id_table = ti_sn_gpio_id_table,
1780 };
1781
1782 static int __init ti_sn_gpio_register(void)
1783 {
1784         return auxiliary_driver_register(&ti_sn_gpio_driver);
1785 }
1786
1787 static void ti_sn_gpio_unregister(void)
1788 {
1789         auxiliary_driver_unregister(&ti_sn_gpio_driver);
1790 }
1791
1792 #else
1793
1794 static inline int ti_sn_gpio_register(void) { return 0; }
1795 static inline void ti_sn_gpio_unregister(void) {}
1796
1797 #endif
1798
1799 /* -----------------------------------------------------------------------------
1800  * Probe & Remove
1801  */
1802
1803 static void ti_sn65dsi86_runtime_disable(void *data)
1804 {
1805         pm_runtime_dont_use_autosuspend(data);
1806         pm_runtime_disable(data);
1807 }
1808
1809 static int ti_sn65dsi86_parse_regulators(struct ti_sn65dsi86 *pdata)
1810 {
1811         unsigned int i;
1812         const char * const ti_sn_bridge_supply_names[] = {
1813                 "vcca", "vcc", "vccio", "vpll",
1814         };
1815
1816         for (i = 0; i < SN_REGULATOR_SUPPLY_NUM; i++)
1817                 pdata->supplies[i].supply = ti_sn_bridge_supply_names[i];
1818
1819         return devm_regulator_bulk_get(pdata->dev, SN_REGULATOR_SUPPLY_NUM,
1820                                        pdata->supplies);
1821 }
1822
1823 static int ti_sn65dsi86_probe(struct i2c_client *client,
1824                               const struct i2c_device_id *id)
1825 {
1826         struct device *dev = &client->dev;
1827         struct ti_sn65dsi86 *pdata;
1828         int ret;
1829
1830         if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
1831                 DRM_ERROR("device doesn't support I2C\n");
1832                 return -ENODEV;
1833         }
1834
1835         pdata = devm_kzalloc(dev, sizeof(struct ti_sn65dsi86), GFP_KERNEL);
1836         if (!pdata)
1837                 return -ENOMEM;
1838         dev_set_drvdata(dev, pdata);
1839         pdata->dev = dev;
1840
1841         mutex_init(&pdata->comms_mutex);
1842
1843         pdata->regmap = devm_regmap_init_i2c(client,
1844                                              &ti_sn65dsi86_regmap_config);
1845         if (IS_ERR(pdata->regmap))
1846                 return dev_err_probe(dev, PTR_ERR(pdata->regmap),
1847                                      "regmap i2c init failed\n");
1848
1849         pdata->enable_gpio = devm_gpiod_get_optional(dev, "enable",
1850                                                      GPIOD_OUT_LOW);
1851         if (IS_ERR(pdata->enable_gpio))
1852                 return dev_err_probe(dev, PTR_ERR(pdata->enable_gpio),
1853                                      "failed to get enable gpio from DT\n");
1854
1855         ret = ti_sn65dsi86_parse_regulators(pdata);
1856         if (ret)
1857                 return dev_err_probe(dev, ret, "failed to parse regulators\n");
1858
1859         pdata->refclk = devm_clk_get_optional(dev, "refclk");
1860         if (IS_ERR(pdata->refclk))
1861                 return dev_err_probe(dev, PTR_ERR(pdata->refclk),
1862                                      "failed to get reference clock\n");
1863
1864         pm_runtime_enable(dev);
1865         pm_runtime_set_autosuspend_delay(pdata->dev, 500);
1866         pm_runtime_use_autosuspend(pdata->dev);
1867         ret = devm_add_action_or_reset(dev, ti_sn65dsi86_runtime_disable, dev);
1868         if (ret)
1869                 return ret;
1870
1871         ti_sn65dsi86_debugfs_init(pdata);
1872
1873         /*
1874          * Break ourselves up into a collection of aux devices. The only real
1875          * motiviation here is to solve the chicken-and-egg problem of probe
1876          * ordering. The bridge wants the panel to be there when it probes.
1877          * The panel wants its HPD GPIO (provided by sn65dsi86 on some boards)
1878          * when it probes. The panel and maybe backlight might want the DDC
1879          * bus or the pwm_chip. Having sub-devices allows the some sub devices
1880          * to finish probing even if others return -EPROBE_DEFER and gets us
1881          * around the problems.
1882          */
1883
1884         if (IS_ENABLED(CONFIG_OF_GPIO)) {
1885                 ret = ti_sn65dsi86_add_aux_device(pdata, &pdata->gpio_aux, "gpio");
1886                 if (ret)
1887                         return ret;
1888         }
1889
1890         if (IS_ENABLED(CONFIG_PWM)) {
1891                 ret = ti_sn65dsi86_add_aux_device(pdata, &pdata->pwm_aux, "pwm");
1892                 if (ret)
1893                         return ret;
1894         }
1895
1896         /*
1897          * NOTE: At the end of the AUX channel probe we'll add the aux device
1898          * for the bridge. This is because the bridge can't be used until the
1899          * AUX channel is there and this is a very simple solution to the
1900          * dependency problem.
1901          */
1902         return ti_sn65dsi86_add_aux_device(pdata, &pdata->aux_aux, "aux");
1903 }
1904
1905 static struct i2c_device_id ti_sn65dsi86_id[] = {
1906         { "ti,sn65dsi86", 0},
1907         {},
1908 };
1909 MODULE_DEVICE_TABLE(i2c, ti_sn65dsi86_id);
1910
1911 static const struct of_device_id ti_sn65dsi86_match_table[] = {
1912         {.compatible = "ti,sn65dsi86"},
1913         {},
1914 };
1915 MODULE_DEVICE_TABLE(of, ti_sn65dsi86_match_table);
1916
1917 static struct i2c_driver ti_sn65dsi86_driver = {
1918         .driver = {
1919                 .name = "ti_sn65dsi86",
1920                 .of_match_table = ti_sn65dsi86_match_table,
1921                 .pm = &ti_sn65dsi86_pm_ops,
1922         },
1923         .probe = ti_sn65dsi86_probe,
1924         .id_table = ti_sn65dsi86_id,
1925 };
1926
1927 static int __init ti_sn65dsi86_init(void)
1928 {
1929         int ret;
1930
1931         ret = i2c_add_driver(&ti_sn65dsi86_driver);
1932         if (ret)
1933                 return ret;
1934
1935         ret = ti_sn_gpio_register();
1936         if (ret)
1937                 goto err_main_was_registered;
1938
1939         ret = ti_sn_pwm_register();
1940         if (ret)
1941                 goto err_gpio_was_registered;
1942
1943         ret = auxiliary_driver_register(&ti_sn_aux_driver);
1944         if (ret)
1945                 goto err_pwm_was_registered;
1946
1947         ret = auxiliary_driver_register(&ti_sn_bridge_driver);
1948         if (ret)
1949                 goto err_aux_was_registered;
1950
1951         return 0;
1952
1953 err_aux_was_registered:
1954         auxiliary_driver_unregister(&ti_sn_aux_driver);
1955 err_pwm_was_registered:
1956         ti_sn_pwm_unregister();
1957 err_gpio_was_registered:
1958         ti_sn_gpio_unregister();
1959 err_main_was_registered:
1960         i2c_del_driver(&ti_sn65dsi86_driver);
1961
1962         return ret;
1963 }
1964 module_init(ti_sn65dsi86_init);
1965
1966 static void __exit ti_sn65dsi86_exit(void)
1967 {
1968         auxiliary_driver_unregister(&ti_sn_bridge_driver);
1969         auxiliary_driver_unregister(&ti_sn_aux_driver);
1970         ti_sn_pwm_unregister();
1971         ti_sn_gpio_unregister();
1972         i2c_del_driver(&ti_sn65dsi86_driver);
1973 }
1974 module_exit(ti_sn65dsi86_exit);
1975
1976 MODULE_AUTHOR("Sandeep Panda <spanda@codeaurora.org>");
1977 MODULE_DESCRIPTION("sn65dsi86 DSI to eDP bridge driver");
1978 MODULE_LICENSE("GPL v2");