drivers/gpu/drm/i915/display/intel_atomic.c

   1 /*
   2  * Copyright © 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 /**
  25  * DOC: atomic modeset support
  26  *
  27  * The functions here implement the state management and hardware programming
  28  * dispatch required by the atomic modeset infrastructure.
  29  * See intel_atomic_plane.c for the plane-specific atomic functionality.
  30  */
  31
  32 #include <drm/drm_atomic.h>
  33 #include <drm/drm_atomic_helper.h>
  34 #include <drm/drm_fourcc.h>
  35 #include <drm/drm_plane_helper.h>
  36
  37 #include "intel_atomic.h"
  38 #include "intel_display_types.h"
  39 #include "intel_hdcp.h"
  40 #include "intel_sprite.h"
  41
  42 /**
  43  * intel_digital_connector_atomic_get_property - hook for connector->atomic_get_property.
  44  * @connector: Connector to get the property for.
  45  * @state: Connector state to retrieve the property from.
  46  * @property: Property to retrieve.
  47  * @val: Return value for the property.
  48  *
  49  * Returns the atomic property value for a digital connector.
  50  */
  51 int intel_digital_connector_atomic_get_property(struct drm_connector *connector,
  52                                                 const struct drm_connector_state *state,
  53                                                 struct drm_property *property,
  54                                                 u64 *val)
  55 {
  56         struct drm_device *dev = connector->dev;
  57         struct drm_i915_private *dev_priv = to_i915(dev);
  58         struct intel_digital_connector_state *intel_conn_state =
  59                 to_intel_digital_connector_state(state);
  60
  61         if (property == dev_priv->force_audio_property)
  62                 *val = intel_conn_state->force_audio;
  63         else if (property == dev_priv->broadcast_rgb_property)
  64                 *val = intel_conn_state->broadcast_rgb;
  65         else {
  66                 DRM_DEBUG_ATOMIC("Unknown property [PROP:%d:%s]\n",
  67                                  property->base.id, property->name);
  68                 return -EINVAL;
  69         }
  70
  71         return 0;
  72 }
  73
  74 /**
  75  * intel_digital_connector_atomic_set_property - hook for connector->atomic_set_property.
  76  * @connector: Connector to set the property for.
  77  * @state: Connector state to set the property on.
  78  * @property: Property to set.
  79  * @val: New value for the property.
  80  *
  81  * Sets the atomic property value for a digital connector.
  82  */
  83 int intel_digital_connector_atomic_set_property(struct drm_connector *connector,
  84                                                 struct drm_connector_state *state,
  85                                                 struct drm_property *property,
  86                                                 u64 val)
  87 {
  88         struct drm_device *dev = connector->dev;
  89         struct drm_i915_private *dev_priv = to_i915(dev);
  90         struct intel_digital_connector_state *intel_conn_state =
  91                 to_intel_digital_connector_state(state);
  92
  93         if (property == dev_priv->force_audio_property) {
  94                 intel_conn_state->force_audio = val;
  95                 return 0;
  96         }
  97
  98         if (property == dev_priv->broadcast_rgb_property) {
  99                 intel_conn_state->broadcast_rgb = val;
 100                 return 0;
 101         }
 102
 103         DRM_DEBUG_ATOMIC("Unknown property [PROP:%d:%s]\n",
 104                          property->base.id, property->name);
 105         return -EINVAL;
 106 }
 107
 108 static bool blob_equal(const struct drm_property_blob *a,
 109                        const struct drm_property_blob *b)
 110 {
 111         if (a && b)
 112                 return a->length == b->length &&
 113                         !memcmp(a->data, b->data, a->length);
 114
 115         return !a == !b;
 116 }
 117
 118 int intel_digital_connector_atomic_check(struct drm_connector *conn,
 119                                          struct drm_atomic_state *state)
 120 {
 121         struct drm_connector_state *new_state =
 122                 drm_atomic_get_new_connector_state(state, conn);
 123         struct intel_digital_connector_state *new_conn_state =
 124                 to_intel_digital_connector_state(new_state);
 125         struct drm_connector_state *old_state =
 126                 drm_atomic_get_old_connector_state(state, conn);
 127         struct intel_digital_connector_state *old_conn_state =
 128                 to_intel_digital_connector_state(old_state);
 129         struct drm_crtc_state *crtc_state;
 130
 131         intel_hdcp_atomic_check(conn, old_state, new_state);
 132
 133         if (!new_state->crtc)
 134                 return 0;
 135
 136         crtc_state = drm_atomic_get_new_crtc_state(state, new_state->crtc);
 137
 138         /*
 139          * These properties are handled by fastset, and might not end
 140          * up in a modeset.
 141          */
 142         if (new_conn_state->force_audio != old_conn_state->force_audio ||
 143             new_conn_state->broadcast_rgb != old_conn_state->broadcast_rgb ||
 144             new_conn_state->base.colorspace != old_conn_state->base.colorspace ||
 145             new_conn_state->base.picture_aspect_ratio != old_conn_state->base.picture_aspect_ratio ||
 146             new_conn_state->base.content_type != old_conn_state->base.content_type ||
 147             new_conn_state->base.scaling_mode != old_conn_state->base.scaling_mode ||
 148             !blob_equal(new_conn_state->base.hdr_output_metadata,
 149                         old_conn_state->base.hdr_output_metadata))
 150                 crtc_state->mode_changed = true;
 151
 152         return 0;
 153 }
 154
 155 /**
 156  * intel_digital_connector_duplicate_state - duplicate connector state
 157  * @connector: digital connector
 158  *
 159  * Allocates and returns a copy of the connector state (both common and
 160  * digital connector specific) for the specified connector.
 161  *
 162  * Returns: The newly allocated connector state, or NULL on failure.
 163  */
 164 struct drm_connector_state *
 165 intel_digital_connector_duplicate_state(struct drm_connector *connector)
 166 {
 167         struct intel_digital_connector_state *state;
 168
 169         state = kmemdup(connector->state, sizeof(*state), GFP_KERNEL);
 170         if (!state)
 171                 return NULL;
 172
 173         __drm_atomic_helper_connector_duplicate_state(connector, &state->base);
 174         return &state->base;
 175 }
 176
 177 /**
 178  * intel_crtc_duplicate_state - duplicate crtc state
 179  * @crtc: drm crtc
 180  *
 181  * Allocates and returns a copy of the crtc state (both common and
 182  * Intel-specific) for the specified crtc.
 183  *
 184  * Returns: The newly allocated crtc state, or NULL on failure.
 185  */
 186 struct drm_crtc_state *
 187 intel_crtc_duplicate_state(struct drm_crtc *crtc)
 188 {
 189         const struct intel_crtc_state *old_crtc_state = to_intel_crtc_state(crtc->state);
 190         struct intel_crtc_state *crtc_state;
 191
 192         crtc_state = kmemdup(old_crtc_state, sizeof(*crtc_state), GFP_KERNEL);
 193         if (!crtc_state)
 194                 return NULL;
 195
 196         __drm_atomic_helper_crtc_duplicate_state(crtc, &crtc_state->base);
 197
 198         crtc_state->update_pipe = false;
 199         crtc_state->disable_lp_wm = false;
 200         crtc_state->disable_cxsr = false;
 201         crtc_state->update_wm_pre = false;
 202         crtc_state->update_wm_post = false;
 203         crtc_state->fifo_changed = false;
 204         crtc_state->wm.need_postvbl_update = false;
 205         crtc_state->fb_bits = 0;
 206         crtc_state->update_planes = 0;
 207
 208         return &crtc_state->base;
 209 }
 210
 211 /**
 212  * intel_crtc_destroy_state - destroy crtc state
 213  * @crtc: drm crtc
 214  * @state: the state to destroy
 215  *
 216  * Destroys the crtc state (both common and Intel-specific) for the
 217  * specified crtc.
 218  */
 219 void
 220 intel_crtc_destroy_state(struct drm_crtc *crtc,
 221                          struct drm_crtc_state *state)
 222 {
 223         struct intel_crtc_state *crtc_state = to_intel_crtc_state(state);
 224
 225         __drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
 226         kfree(crtc_state);
 227 }
 228
 229 static void intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_state,
 230                                       int num_scalers_need, struct intel_crtc *intel_crtc,
 231                                       const char *name, int idx,
 232                                       struct intel_plane_state *plane_state,
 233                                       int *scaler_id)
 234 {
 235         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
 236         int j;
 237         u32 mode;
 238
 239         if (*scaler_id < 0) {
 240                 /* find a free scaler */
 241                 for (j = 0; j < intel_crtc->num_scalers; j++) {
 242                         if (scaler_state->scalers[j].in_use)
 243                                 continue;
 244
 245                         *scaler_id = j;
 246                         scaler_state->scalers[*scaler_id].in_use = 1;
 247                         break;
 248                 }
 249         }
 250
 251         if (WARN(*scaler_id < 0, "Cannot find scaler for %s:%d\n", name, idx))
 252                 return;
 253
 254         /* set scaler mode */
 255         if (plane_state && plane_state->base.fb &&
 256             plane_state->base.fb->format->is_yuv &&
 257             plane_state->base.fb->format->num_planes > 1) {
 258                 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
 259                 if (IS_GEN(dev_priv, 9) &&
 260                     !IS_GEMINILAKE(dev_priv)) {
 261                         mode = SKL_PS_SCALER_MODE_NV12;
 262                 } else if (icl_is_hdr_plane(dev_priv, plane->id)) {
 263                         /*
 264                          * On gen11+'s HDR planes we only use the scaler for
 265                          * scaling. They have a dedicated chroma upsampler, so
 266                          * we don't need the scaler to upsample the UV plane.
 267                          */
 268                         mode = PS_SCALER_MODE_NORMAL;
 269                 } else {
 270                         struct intel_plane *linked =
 271                                 plane_state->planar_linked_plane;
 272
 273                         mode = PS_SCALER_MODE_PLANAR;
 274
 275                         if (linked)
 276                                 mode |= PS_PLANE_Y_SEL(linked->id);
 277                 }
 278         } else if (INTEL_GEN(dev_priv) > 9 || IS_GEMINILAKE(dev_priv)) {
 279                 mode = PS_SCALER_MODE_NORMAL;
 280         } else if (num_scalers_need == 1 && intel_crtc->num_scalers > 1) {
 281                 /*
 282                  * when only 1 scaler is in use on a pipe with 2 scalers
 283                  * scaler 0 operates in high quality (HQ) mode.
 284                  * In this case use scaler 0 to take advantage of HQ mode
 285                  */
 286                 scaler_state->scalers[*scaler_id].in_use = 0;
 287                 *scaler_id = 0;
 288                 scaler_state->scalers[0].in_use = 1;
 289                 mode = SKL_PS_SCALER_MODE_HQ;
 290         } else {
 291                 mode = SKL_PS_SCALER_MODE_DYN;
 292         }
 293
 294         DRM_DEBUG_KMS("Attached scaler id %u.%u to %s:%d\n",
 295                       intel_crtc->pipe, *scaler_id, name, idx);
 296         scaler_state->scalers[*scaler_id].mode = mode;
 297 }
 298
 299 /**
 300  * intel_atomic_setup_scalers() - setup scalers for crtc per staged requests
 301  * @dev_priv: i915 device
 302  * @intel_crtc: intel crtc
 303  * @crtc_state: incoming crtc_state to validate and setup scalers
 304  *
 305  * This function sets up scalers based on staged scaling requests for
 306  * a @crtc and its planes. It is called from crtc level check path. If request
 307  * is a supportable request, it attaches scalers to requested planes and crtc.
 308  *
 309  * This function takes into account the current scaler(s) in use by any planes
 310  * not being part of this atomic state
 311  *
 312  *  Returns:
 313  *         0 - scalers were setup succesfully
 314  *         error code - otherwise
 315  */
 316 int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
 317                                struct intel_crtc *intel_crtc,
 318                                struct intel_crtc_state *crtc_state)
 319 {
 320         struct drm_plane *plane = NULL;
 321         struct intel_plane *intel_plane;
 322         struct intel_plane_state *plane_state = NULL;
 323         struct intel_crtc_scaler_state *scaler_state =
 324                 &crtc_state->scaler_state;
 325         struct drm_atomic_state *drm_state = crtc_state->base.state;
 326         struct intel_atomic_state *intel_state = to_intel_atomic_state(drm_state);
 327         int num_scalers_need;
 328         int i;
 329
 330         num_scalers_need = hweight32(scaler_state->scaler_users);
 331
 332         /*
 333          * High level flow:
 334          * - staged scaler requests are already in scaler_state->scaler_users
 335          * - check whether staged scaling requests can be supported
 336          * - add planes using scalers that aren't in current transaction
 337          * - assign scalers to requested users
 338          * - as part of plane commit, scalers will be committed
 339          *   (i.e., either attached or detached) to respective planes in hw
 340          * - as part of crtc_commit, scaler will be either attached or detached
 341          *   to crtc in hw
 342          */
 343
 344         /* fail if required scalers > available scalers */
 345         if (num_scalers_need > intel_crtc->num_scalers){
 346                 DRM_DEBUG_KMS("Too many scaling requests %d > %d\n",
 347                         num_scalers_need, intel_crtc->num_scalers);
 348                 return -EINVAL;
 349         }
 350
 351         /* walkthrough scaler_users bits and start assigning scalers */
 352         for (i = 0; i < sizeof(scaler_state->scaler_users) * 8; i++) {
 353                 int *scaler_id;
 354                 const char *name;
 355                 int idx;
 356
 357                 /* skip if scaler not required */
 358                 if (!(scaler_state->scaler_users & (1 << i)))
 359                         continue;
 360
 361                 if (i == SKL_CRTC_INDEX) {
 362                         name = "CRTC";
 363                         idx = intel_crtc->base.base.id;
 364
 365                         /* panel fitter case: assign as a crtc scaler */
 366                         scaler_id = &scaler_state->scaler_id;
 367                 } else {
 368                         name = "PLANE";
 369
 370                         /* plane scaler case: assign as a plane scaler */
 371                         /* find the plane that set the bit as scaler_user */
 372                         plane = drm_state->planes[i].ptr;
 373
 374                         /*
 375                          * to enable/disable hq mode, add planes that are using scaler
 376                          * into this transaction
 377                          */
 378                         if (!plane) {
 379                                 struct drm_plane_state *state;
 380
 381                                 /*
 382                                  * GLK+ scalers don't have a HQ mode so it
 383                                  * isn't necessary to change between HQ and dyn mode
 384                                  * on those platforms.
 385                                  */
 386                                 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
 387                                         continue;
 388
 389                                 plane = drm_plane_from_index(&dev_priv->drm, i);
 390                                 state = drm_atomic_get_plane_state(drm_state, plane);
 391                                 if (IS_ERR(state)) {
 392                                         DRM_DEBUG_KMS("Failed to add [PLANE:%d] to drm_state\n",
 393                                                 plane->base.id);
 394                                         return PTR_ERR(state);
 395                                 }
 396                         }
 397
 398                         intel_plane = to_intel_plane(plane);
 399                         idx = plane->base.id;
 400
 401                         /* plane on different crtc cannot be a scaler user of this crtc */
 402                         if (WARN_ON(intel_plane->pipe != intel_crtc->pipe))
 403                                 continue;
 404
 405                         plane_state = intel_atomic_get_new_plane_state(intel_state,
 406                                                                        intel_plane);
 407                         scaler_id = &plane_state->scaler_id;
 408                 }
 409
 410                 intel_atomic_setup_scaler(scaler_state, num_scalers_need,
 411                                           intel_crtc, name, idx,
 412                                           plane_state, scaler_id);
 413         }
 414
 415         return 0;
 416 }
 417
 418 struct drm_atomic_state *
 419 intel_atomic_state_alloc(struct drm_device *dev)
 420 {
 421         struct intel_atomic_state *state = kzalloc(sizeof(*state), GFP_KERNEL);
 422
 423         if (!state || drm_atomic_state_init(dev, &state->base) < 0) {
 424                 kfree(state);
 425                 return NULL;
 426         }
 427
 428         return &state->base;
 429 }
 430
 431 void intel_atomic_state_clear(struct drm_atomic_state *s)
 432 {
 433         struct intel_atomic_state *state = to_intel_atomic_state(s);
 434         drm_atomic_state_default_clear(&state->base);
 435         state->dpll_set = state->modeset = false;
 436         state->global_state_changed = false;
 437         state->active_pipes = 0;
 438         memset(&state->min_cdclk, 0, sizeof(state->min_cdclk));
 439         memset(&state->min_voltage_level, 0, sizeof(state->min_voltage_level));
 440         memset(&state->cdclk.logical, 0, sizeof(state->cdclk.logical));
 441         memset(&state->cdclk.actual, 0, sizeof(state->cdclk.actual));
 442         state->cdclk.pipe = INVALID_PIPE;
 443 }
 444
 445 struct intel_crtc_state *
 446 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
 447                             struct intel_crtc *crtc)
 448 {
 449         struct drm_crtc_state *crtc_state;
 450         crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
 451         if (IS_ERR(crtc_state))
 452                 return ERR_CAST(crtc_state);
 453
 454         return to_intel_crtc_state(crtc_state);
 455 }
 456
 457 int intel_atomic_lock_global_state(struct intel_atomic_state *state)
 458 {
 459         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
 460         struct intel_crtc *crtc;
 461
 462         state->global_state_changed = true;
 463
 464         for_each_intel_crtc(&dev_priv->drm, crtc) {
 465                 int ret;
 466
 467                 ret = drm_modeset_lock(&crtc->base.mutex,
 468                                        state->base.acquire_ctx);
 469                 if (ret)
 470                         return ret;
 471         }
 472
 473         return 0;
 474 }
 475
 476 int intel_atomic_serialize_global_state(struct intel_atomic_state *state)
 477 {
 478         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
 479         struct intel_crtc *crtc;
 480
 481         state->global_state_changed = true;
 482
 483         for_each_intel_crtc(&dev_priv->drm, crtc) {
 484                 struct intel_crtc_state *crtc_state;
 485
 486                 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
 487                 if (IS_ERR(crtc_state))
 488                         return PTR_ERR(crtc_state);
 489         }
 490
 491         return 0;
 492 }