2 * Copyright © 2016-2019 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
25 * Please use intel_vbt_defs.h for VBT private data, to hide and abstract away
26 * the VBT from the rest of the driver. Add the parsed, clean data to struct
27 * intel_vbt_data within struct drm_i915_private.
30 #ifndef _INTEL_BIOS_H_
31 #define _INTEL_BIOS_H_
33 #include <linux/types.h>
35 #include <drm/i915_drm.h>
37 struct drm_i915_private;
38 struct intel_crtc_state;
42 enum intel_backlight_type {
45 INTEL_BACKLIGHT_DISPLAY_DDI,
46 INTEL_BACKLIGHT_DSI_DCS,
47 INTEL_BACKLIGHT_PANEL_DRIVER_INTERFACE,
48 INTEL_BACKLIGHT_VESA_EDP_AUX_INTERFACE,
51 struct edp_power_seq {
60 * MIPI Sequence Block definitions
62 * Note the VBT spec has AssertReset / DeassertReset swapped from their
63 * usual naming, we use the proper names here to avoid confusion when
68 MIPI_SEQ_DEASSERT_RESET, /* Spec says MipiAssertResetPin */
72 MIPI_SEQ_ASSERT_RESET, /* Spec says MipiDeassertResetPin */
73 MIPI_SEQ_BACKLIGHT_ON, /* sequence block v2+ */
74 MIPI_SEQ_BACKLIGHT_OFF, /* sequence block v2+ */
75 MIPI_SEQ_TEAR_ON, /* sequence block v2+ */
76 MIPI_SEQ_TEAR_OFF, /* sequence block v3+ */
77 MIPI_SEQ_POWER_ON, /* sequence block v3+ */
78 MIPI_SEQ_POWER_OFF, /* sequence block v3+ */
82 enum mipi_seq_element {
83 MIPI_SEQ_ELEM_END = 0,
84 MIPI_SEQ_ELEM_SEND_PKT,
87 MIPI_SEQ_ELEM_I2C, /* sequence block v2+ */
88 MIPI_SEQ_ELEM_SPI, /* sequence block v3+ */
89 MIPI_SEQ_ELEM_PMIC, /* sequence block v3+ */
93 #define MIPI_DSI_UNDEFINED_PANEL_ID 0
94 #define MIPI_DSI_GENERIC_PANEL_ID 1
100 u32 enable_dithering:1;
104 u32 panel_arch_type:2;
107 #define NON_BURST_SYNC_PULSE 0x1
108 #define NON_BURST_SYNC_EVENTS 0x2
109 #define BURST_MODE 0x3
110 u32 video_transfer_mode:2;
112 u32 cabc_supported:1;
113 #define PPS_BLC_PMIC 0
114 #define PPS_BLC_SOC 1
118 #define PIXEL_FORMAT_RGB565 0x1
119 #define PIXEL_FORMAT_RGB666 0x2
120 #define PIXEL_FORMAT_RGB666_LOOSELY_PACKED 0x3
121 #define PIXEL_FORMAT_RGB888 0x4
122 u32 videomode_color_format:4;
125 #define ENABLE_ROTATION_0 0x0
126 #define ENABLE_ROTATION_90 0x1
127 #define ENABLE_ROTATION_180 0x2
128 #define ENABLE_ROTATION_270 0x3
133 /* 2 byte Port Description */
134 #define DUAL_LINK_NOT_SUPPORTED 0
135 #define DUAL_LINK_FRONT_BACK 1
136 #define DUAL_LINK_PIXEL_ALT 2
141 #define DL_DCS_PORT_A 0x00
142 #define DL_DCS_PORT_C 0x01
143 #define DL_DCS_PORT_A_AND_C 0x02
144 u16 dl_dcs_cabc_ports:2;
145 u16 dl_dcs_backlight_ports:2;
151 u32 target_burst_mode_freq;
155 #define BYTE_CLK_SEL_20MHZ 0
156 #define BYTE_CLK_SEL_10MHZ 1
157 #define BYTE_CLK_SEL_5MHZ 2
163 u16 dphy_param_valid:1;
164 u16 eot_pkt_disabled:1;
165 u16 enable_clk_stop:1;
170 u32 turn_around_timeout;
171 u32 device_reset_timer;
172 u32 master_init_timer;
176 /* 4 byte Dphy Params */
185 u32 clk_lane_switch_cnt;
190 /* timings based on dphy spec */
199 u16 tclk_prepare_clkzero;
205 u16 ths_prepare_hszero;
224 /* all delays have a unit of 100us */
225 struct mipi_pps_data {
228 u16 bl_disable_delay;
230 u16 panel_power_cycle_delay;
233 void intel_bios_init(struct drm_i915_private *dev_priv);
234 void intel_bios_driver_remove(struct drm_i915_private *dev_priv);
235 bool intel_bios_is_valid_vbt(const void *buf, size_t size);
236 bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv);
237 bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin);
238 bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port);
239 bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
240 bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv, enum port port);
241 bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, enum port *port);
242 bool intel_bios_is_port_hpd_inverted(const struct drm_i915_private *i915,
244 bool intel_bios_is_lspcon_present(const struct drm_i915_private *i915,
246 enum aux_ch intel_bios_port_aux_ch(struct drm_i915_private *dev_priv, enum port port);
247 bool intel_bios_get_dsc_params(struct intel_encoder *encoder,
248 struct intel_crtc_state *crtc_state,
250 int intel_bios_max_tmds_clock(struct intel_encoder *encoder);
251 int intel_bios_hdmi_level_shift(struct intel_encoder *encoder);
252 int intel_bios_dp_boost_level(struct intel_encoder *encoder);
253 int intel_bios_hdmi_boost_level(struct intel_encoder *encoder);
254 int intel_bios_dp_max_link_rate(struct intel_encoder *encoder);
255 int intel_bios_alternate_ddc_pin(struct intel_encoder *encoder);
256 bool intel_bios_port_supports_dvi(struct drm_i915_private *i915, enum port port);
257 bool intel_bios_port_supports_hdmi(struct drm_i915_private *i915, enum port port);
258 bool intel_bios_port_supports_dp(struct drm_i915_private *i915, enum port port);
259 bool intel_bios_port_supports_typec_usb(struct drm_i915_private *i915, enum port port);
260 bool intel_bios_port_supports_tbt(struct drm_i915_private *i915, enum port port);
262 #endif /* _INTEL_BIOS_H_ */