drivers/gpu/drm/i915/display/intel_cdclk.c

   1 /*
   2  * Copyright © 2006-2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "intel_cdclk.h"
  25 #include "intel_display_types.h"
  26 #include "intel_sideband.h"
  27
  28 /**
  29  * DOC: CDCLK / RAWCLK
  30  *
  31  * The display engine uses several different clocks to do its work. There
  32  * are two main clocks involved that aren't directly related to the actual
  33  * pixel clock or any symbol/bit clock of the actual output port. These
  34  * are the core display clock (CDCLK) and RAWCLK.
  35  *
  36  * CDCLK clocks most of the display pipe logic, and thus its frequency
  37  * must be high enough to support the rate at which pixels are flowing
  38  * through the pipes. Downscaling must also be accounted as that increases
  39  * the effective pixel rate.
  40  *
  41  * On several platforms the CDCLK frequency can be changed dynamically
  42  * to minimize power consumption for a given display configuration.
  43  * Typically changes to the CDCLK frequency require all the display pipes
  44  * to be shut down while the frequency is being changed.
  45  *
  46  * On SKL+ the DMC will toggle the CDCLK off/on during DC5/6 entry/exit.
  47  * DMC will not change the active CDCLK frequency however, so that part
  48  * will still be performed by the driver directly.
  49  *
  50  * RAWCLK is a fixed frequency clock, often used by various auxiliary
  51  * blocks such as AUX CH or backlight PWM. Hence the only thing we
  52  * really need to know about RAWCLK is its frequency so that various
  53  * dividers can be programmed correctly.
  54  */
  55
  56 static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv,
  57                                    struct intel_cdclk_state *cdclk_state)
  58 {
  59         cdclk_state->cdclk = 133333;
  60 }
  61
  62 static void fixed_200mhz_get_cdclk(struct drm_i915_private *dev_priv,
  63                                    struct intel_cdclk_state *cdclk_state)
  64 {
  65         cdclk_state->cdclk = 200000;
  66 }
  67
  68 static void fixed_266mhz_get_cdclk(struct drm_i915_private *dev_priv,
  69                                    struct intel_cdclk_state *cdclk_state)
  70 {
  71         cdclk_state->cdclk = 266667;
  72 }
  73
  74 static void fixed_333mhz_get_cdclk(struct drm_i915_private *dev_priv,
  75                                    struct intel_cdclk_state *cdclk_state)
  76 {
  77         cdclk_state->cdclk = 333333;
  78 }
  79
  80 static void fixed_400mhz_get_cdclk(struct drm_i915_private *dev_priv,
  81                                    struct intel_cdclk_state *cdclk_state)
  82 {
  83         cdclk_state->cdclk = 400000;
  84 }
  85
  86 static void fixed_450mhz_get_cdclk(struct drm_i915_private *dev_priv,
  87                                    struct intel_cdclk_state *cdclk_state)
  88 {
  89         cdclk_state->cdclk = 450000;
  90 }
  91
  92 static void i85x_get_cdclk(struct drm_i915_private *dev_priv,
  93                            struct intel_cdclk_state *cdclk_state)
  94 {
  95         struct pci_dev *pdev = dev_priv->drm.pdev;
  96         u16 hpllcc = 0;
  97
  98         /*
  99          * 852GM/852GMV only supports 133 MHz and the HPLLCC
 100          * encoding is different :(
 101          * FIXME is this the right way to detect 852GM/852GMV?
 102          */
 103         if (pdev->revision == 0x1) {
 104                 cdclk_state->cdclk = 133333;
 105                 return;
 106         }
 107
 108         pci_bus_read_config_word(pdev->bus,
 109                                  PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
 110
 111         /* Assume that the hardware is in the high speed state.  This
 112          * should be the default.
 113          */
 114         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
 115         case GC_CLOCK_133_200:
 116         case GC_CLOCK_133_200_2:
 117         case GC_CLOCK_100_200:
 118                 cdclk_state->cdclk = 200000;
 119                 break;
 120         case GC_CLOCK_166_250:
 121                 cdclk_state->cdclk = 250000;
 122                 break;
 123         case GC_CLOCK_100_133:
 124                 cdclk_state->cdclk = 133333;
 125                 break;
 126         case GC_CLOCK_133_266:
 127         case GC_CLOCK_133_266_2:
 128         case GC_CLOCK_166_266:
 129                 cdclk_state->cdclk = 266667;
 130                 break;
 131         }
 132 }
 133
 134 static void i915gm_get_cdclk(struct drm_i915_private *dev_priv,
 135                              struct intel_cdclk_state *cdclk_state)
 136 {
 137         struct pci_dev *pdev = dev_priv->drm.pdev;
 138         u16 gcfgc = 0;
 139
 140         pci_read_config_word(pdev, GCFGC, &gcfgc);
 141
 142         if (gcfgc & GC_LOW_FREQUENCY_ENABLE) {
 143                 cdclk_state->cdclk = 133333;
 144                 return;
 145         }
 146
 147         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
 148         case GC_DISPLAY_CLOCK_333_320_MHZ:
 149                 cdclk_state->cdclk = 333333;
 150                 break;
 151         default:
 152         case GC_DISPLAY_CLOCK_190_200_MHZ:
 153                 cdclk_state->cdclk = 190000;
 154                 break;
 155         }
 156 }
 157
 158 static void i945gm_get_cdclk(struct drm_i915_private *dev_priv,
 159                              struct intel_cdclk_state *cdclk_state)
 160 {
 161         struct pci_dev *pdev = dev_priv->drm.pdev;
 162         u16 gcfgc = 0;
 163
 164         pci_read_config_word(pdev, GCFGC, &gcfgc);
 165
 166         if (gcfgc & GC_LOW_FREQUENCY_ENABLE) {
 167                 cdclk_state->cdclk = 133333;
 168                 return;
 169         }
 170
 171         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
 172         case GC_DISPLAY_CLOCK_333_320_MHZ:
 173                 cdclk_state->cdclk = 320000;
 174                 break;
 175         default:
 176         case GC_DISPLAY_CLOCK_190_200_MHZ:
 177                 cdclk_state->cdclk = 200000;
 178                 break;
 179         }
 180 }
 181
 182 static unsigned int intel_hpll_vco(struct drm_i915_private *dev_priv)
 183 {
 184         static const unsigned int blb_vco[8] = {
 185                 [0] = 3200000,
 186                 [1] = 4000000,
 187                 [2] = 5333333,
 188                 [3] = 4800000,
 189                 [4] = 6400000,
 190         };
 191         static const unsigned int pnv_vco[8] = {
 192                 [0] = 3200000,
 193                 [1] = 4000000,
 194                 [2] = 5333333,
 195                 [3] = 4800000,
 196                 [4] = 2666667,
 197         };
 198         static const unsigned int cl_vco[8] = {
 199                 [0] = 3200000,
 200                 [1] = 4000000,
 201                 [2] = 5333333,
 202                 [3] = 6400000,
 203                 [4] = 3333333,
 204                 [5] = 3566667,
 205                 [6] = 4266667,
 206         };
 207         static const unsigned int elk_vco[8] = {
 208                 [0] = 3200000,
 209                 [1] = 4000000,
 210                 [2] = 5333333,
 211                 [3] = 4800000,
 212         };
 213         static const unsigned int ctg_vco[8] = {
 214                 [0] = 3200000,
 215                 [1] = 4000000,
 216                 [2] = 5333333,
 217                 [3] = 6400000,
 218                 [4] = 2666667,
 219                 [5] = 4266667,
 220         };
 221         const unsigned int *vco_table;
 222         unsigned int vco;
 223         u8 tmp = 0;
 224
 225         /* FIXME other chipsets? */
 226         if (IS_GM45(dev_priv))
 227                 vco_table = ctg_vco;
 228         else if (IS_G45(dev_priv))
 229                 vco_table = elk_vco;
 230         else if (IS_I965GM(dev_priv))
 231                 vco_table = cl_vco;
 232         else if (IS_PINEVIEW(dev_priv))
 233                 vco_table = pnv_vco;
 234         else if (IS_G33(dev_priv))
 235                 vco_table = blb_vco;
 236         else
 237                 return 0;
 238
 239         tmp = I915_READ(IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv) ?
 240                         HPLLVCO_MOBILE : HPLLVCO);
 241
 242         vco = vco_table[tmp & 0x7];
 243         if (vco == 0)
 244                 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
 245         else
 246                 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
 247
 248         return vco;
 249 }
 250
 251 static void g33_get_cdclk(struct drm_i915_private *dev_priv,
 252                           struct intel_cdclk_state *cdclk_state)
 253 {
 254         struct pci_dev *pdev = dev_priv->drm.pdev;
 255         static const u8 div_3200[] = { 12, 10,  8,  7, 5, 16 };
 256         static const u8 div_4000[] = { 14, 12, 10,  8, 6, 20 };
 257         static const u8 div_4800[] = { 20, 14, 12, 10, 8, 24 };
 258         static const u8 div_5333[] = { 20, 16, 12, 12, 8, 28 };
 259         const u8 *div_table;
 260         unsigned int cdclk_sel;
 261         u16 tmp = 0;
 262
 263         cdclk_state->vco = intel_hpll_vco(dev_priv);
 264
 265         pci_read_config_word(pdev, GCFGC, &tmp);
 266
 267         cdclk_sel = (tmp >> 4) & 0x7;
 268
 269         if (cdclk_sel >= ARRAY_SIZE(div_3200))
 270                 goto fail;
 271
 272         switch (cdclk_state->vco) {
 273         case 3200000:
 274                 div_table = div_3200;
 275                 break;
 276         case 4000000:
 277                 div_table = div_4000;
 278                 break;
 279         case 4800000:
 280                 div_table = div_4800;
 281                 break;
 282         case 5333333:
 283                 div_table = div_5333;
 284                 break;
 285         default:
 286                 goto fail;
 287         }
 288
 289         cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco,
 290                                                div_table[cdclk_sel]);
 291         return;
 292
 293 fail:
 294         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n",
 295                   cdclk_state->vco, tmp);
 296         cdclk_state->cdclk = 190476;
 297 }
 298
 299 static void pnv_get_cdclk(struct drm_i915_private *dev_priv,
 300                           struct intel_cdclk_state *cdclk_state)
 301 {
 302         struct pci_dev *pdev = dev_priv->drm.pdev;
 303         u16 gcfgc = 0;
 304
 305         pci_read_config_word(pdev, GCFGC, &gcfgc);
 306
 307         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
 308         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
 309                 cdclk_state->cdclk = 266667;
 310                 break;
 311         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
 312                 cdclk_state->cdclk = 333333;
 313                 break;
 314         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
 315                 cdclk_state->cdclk = 444444;
 316                 break;
 317         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
 318                 cdclk_state->cdclk = 200000;
 319                 break;
 320         default:
 321                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
 322                 /* fall through */
 323         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
 324                 cdclk_state->cdclk = 133333;
 325                 break;
 326         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
 327                 cdclk_state->cdclk = 166667;
 328                 break;
 329         }
 330 }
 331
 332 static void i965gm_get_cdclk(struct drm_i915_private *dev_priv,
 333                              struct intel_cdclk_state *cdclk_state)
 334 {
 335         struct pci_dev *pdev = dev_priv->drm.pdev;
 336         static const u8 div_3200[] = { 16, 10,  8 };
 337         static const u8 div_4000[] = { 20, 12, 10 };
 338         static const u8 div_5333[] = { 24, 16, 14 };
 339         const u8 *div_table;
 340         unsigned int cdclk_sel;
 341         u16 tmp = 0;
 342
 343         cdclk_state->vco = intel_hpll_vco(dev_priv);
 344
 345         pci_read_config_word(pdev, GCFGC, &tmp);
 346
 347         cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
 348
 349         if (cdclk_sel >= ARRAY_SIZE(div_3200))
 350                 goto fail;
 351
 352         switch (cdclk_state->vco) {
 353         case 3200000:
 354                 div_table = div_3200;
 355                 break;
 356         case 4000000:
 357                 div_table = div_4000;
 358                 break;
 359         case 5333333:
 360                 div_table = div_5333;
 361                 break;
 362         default:
 363                 goto fail;
 364         }
 365
 366         cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco,
 367                                                div_table[cdclk_sel]);
 368         return;
 369
 370 fail:
 371         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n",
 372                   cdclk_state->vco, tmp);
 373         cdclk_state->cdclk = 200000;
 374 }
 375
 376 static void gm45_get_cdclk(struct drm_i915_private *dev_priv,
 377                            struct intel_cdclk_state *cdclk_state)
 378 {
 379         struct pci_dev *pdev = dev_priv->drm.pdev;
 380         unsigned int cdclk_sel;
 381         u16 tmp = 0;
 382
 383         cdclk_state->vco = intel_hpll_vco(dev_priv);
 384
 385         pci_read_config_word(pdev, GCFGC, &tmp);
 386
 387         cdclk_sel = (tmp >> 12) & 0x1;
 388
 389         switch (cdclk_state->vco) {
 390         case 2666667:
 391         case 4000000:
 392         case 5333333:
 393                 cdclk_state->cdclk = cdclk_sel ? 333333 : 222222;
 394                 break;
 395         case 3200000:
 396                 cdclk_state->cdclk = cdclk_sel ? 320000 : 228571;
 397                 break;
 398         default:
 399                 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n",
 400                           cdclk_state->vco, tmp);
 401                 cdclk_state->cdclk = 222222;
 402                 break;
 403         }
 404 }
 405
 406 static void hsw_get_cdclk(struct drm_i915_private *dev_priv,
 407                           struct intel_cdclk_state *cdclk_state)
 408 {
 409         u32 lcpll = I915_READ(LCPLL_CTL);
 410         u32 freq = lcpll & LCPLL_CLK_FREQ_MASK;
 411
 412         if (lcpll & LCPLL_CD_SOURCE_FCLK)
 413                 cdclk_state->cdclk = 800000;
 414         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
 415                 cdclk_state->cdclk = 450000;
 416         else if (freq == LCPLL_CLK_FREQ_450)
 417                 cdclk_state->cdclk = 450000;
 418         else if (IS_HSW_ULT(dev_priv))
 419                 cdclk_state->cdclk = 337500;
 420         else
 421                 cdclk_state->cdclk = 540000;
 422 }
 423
 424 static int vlv_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
 425 {
 426         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ?
 427                 333333 : 320000;
 428
 429         /*
 430          * We seem to get an unstable or solid color picture at 200MHz.
 431          * Not sure what's wrong. For now use 200MHz only when all pipes
 432          * are off.
 433          */
 434         if (IS_VALLEYVIEW(dev_priv) && min_cdclk > freq_320)
 435                 return 400000;
 436         else if (min_cdclk > 266667)
 437                 return freq_320;
 438         else if (min_cdclk > 0)
 439                 return 266667;
 440         else
 441                 return 200000;
 442 }
 443
 444 static u8 vlv_calc_voltage_level(struct drm_i915_private *dev_priv, int cdclk)
 445 {
 446         if (IS_VALLEYVIEW(dev_priv)) {
 447                 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
 448                         return 2;
 449                 else if (cdclk >= 266667)
 450                         return 1;
 451                 else
 452                         return 0;
 453         } else {
 454                 /*
 455                  * Specs are full of misinformation, but testing on actual
 456                  * hardware has shown that we just need to write the desired
 457                  * CCK divider into the Punit register.
 458                  */
 459                 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
 460         }
 461 }
 462
 463 static void vlv_get_cdclk(struct drm_i915_private *dev_priv,
 464                           struct intel_cdclk_state *cdclk_state)
 465 {
 466         u32 val;
 467
 468         vlv_iosf_sb_get(dev_priv,
 469                         BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT));
 470
 471         cdclk_state->vco = vlv_get_hpll_vco(dev_priv);
 472         cdclk_state->cdclk = vlv_get_cck_clock(dev_priv, "cdclk",
 473                                                CCK_DISPLAY_CLOCK_CONTROL,
 474                                                cdclk_state->vco);
 475
 476         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
 477
 478         vlv_iosf_sb_put(dev_priv,
 479                         BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT));
 480
 481         if (IS_VALLEYVIEW(dev_priv))
 482                 cdclk_state->voltage_level = (val & DSPFREQGUAR_MASK) >>
 483                         DSPFREQGUAR_SHIFT;
 484         else
 485                 cdclk_state->voltage_level = (val & DSPFREQGUAR_MASK_CHV) >>
 486                         DSPFREQGUAR_SHIFT_CHV;
 487 }
 488
 489 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
 490 {
 491         unsigned int credits, default_credits;
 492
 493         if (IS_CHERRYVIEW(dev_priv))
 494                 default_credits = PFI_CREDIT(12);
 495         else
 496                 default_credits = PFI_CREDIT(8);
 497
 498         if (dev_priv->cdclk.hw.cdclk >= dev_priv->czclk_freq) {
 499                 /* CHV suggested value is 31 or 63 */
 500                 if (IS_CHERRYVIEW(dev_priv))
 501                         credits = PFI_CREDIT_63;
 502                 else
 503                         credits = PFI_CREDIT(15);
 504         } else {
 505                 credits = default_credits;
 506         }
 507
 508         /*
 509          * WA - write default credits before re-programming
 510          * FIXME: should we also set the resend bit here?
 511          */
 512         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
 513                    default_credits);
 514
 515         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
 516                    credits | PFI_CREDIT_RESEND);
 517
 518         /*
 519          * FIXME is this guaranteed to clear
 520          * immediately or should we poll for it?
 521          */
 522         WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
 523 }
 524
 525 static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
 526                           const struct intel_cdclk_state *cdclk_state,
 527                           enum pipe pipe)
 528 {
 529         int cdclk = cdclk_state->cdclk;
 530         u32 val, cmd = cdclk_state->voltage_level;
 531         intel_wakeref_t wakeref;
 532
 533         switch (cdclk) {
 534         case 400000:
 535         case 333333:
 536         case 320000:
 537         case 266667:
 538         case 200000:
 539                 break;
 540         default:
 541                 MISSING_CASE(cdclk);
 542                 return;
 543         }
 544
 545         /* There are cases where we can end up here with power domains
 546          * off and a CDCLK frequency other than the minimum, like when
 547          * issuing a modeset without actually changing any display after
 548          * a system suspend.  So grab the display core domain, which covers
 549          * the HW blocks needed for the following programming.
 550          */
 551         wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE);
 552
 553         vlv_iosf_sb_get(dev_priv,
 554                         BIT(VLV_IOSF_SB_CCK) |
 555                         BIT(VLV_IOSF_SB_BUNIT) |
 556                         BIT(VLV_IOSF_SB_PUNIT));
 557
 558         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
 559         val &= ~DSPFREQGUAR_MASK;
 560         val |= (cmd << DSPFREQGUAR_SHIFT);
 561         vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val);
 562         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) &
 563                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
 564                      50)) {
 565                 DRM_ERROR("timed out waiting for CDclk change\n");
 566         }
 567
 568         if (cdclk == 400000) {
 569                 u32 divider;
 570
 571                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1,
 572                                             cdclk) - 1;
 573
 574                 /* adjust cdclk divider */
 575                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
 576                 val &= ~CCK_FREQUENCY_VALUES;
 577                 val |= divider;
 578                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
 579
 580                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
 581                               CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
 582                              50))
 583                         DRM_ERROR("timed out waiting for CDclk change\n");
 584         }
 585
 586         /* adjust self-refresh exit latency value */
 587         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
 588         val &= ~0x7f;
 589
 590         /*
 591          * For high bandwidth configs, we set a higher latency in the bunit
 592          * so that the core display fetch happens in time to avoid underruns.
 593          */
 594         if (cdclk == 400000)
 595                 val |= 4500 / 250; /* 4.5 usec */
 596         else
 597                 val |= 3000 / 250; /* 3.0 usec */
 598         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
 599
 600         vlv_iosf_sb_put(dev_priv,
 601                         BIT(VLV_IOSF_SB_CCK) |
 602                         BIT(VLV_IOSF_SB_BUNIT) |
 603                         BIT(VLV_IOSF_SB_PUNIT));
 604
 605         intel_update_cdclk(dev_priv);
 606
 607         vlv_program_pfi_credits(dev_priv);
 608
 609         intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
 610 }
 611
 612 static void chv_set_cdclk(struct drm_i915_private *dev_priv,
 613                           const struct intel_cdclk_state *cdclk_state,
 614                           enum pipe pipe)
 615 {
 616         int cdclk = cdclk_state->cdclk;
 617         u32 val, cmd = cdclk_state->voltage_level;
 618         intel_wakeref_t wakeref;
 619
 620         switch (cdclk) {
 621         case 333333:
 622         case 320000:
 623         case 266667:
 624         case 200000:
 625                 break;
 626         default:
 627                 MISSING_CASE(cdclk);
 628                 return;
 629         }
 630
 631         /* There are cases where we can end up here with power domains
 632          * off and a CDCLK frequency other than the minimum, like when
 633          * issuing a modeset without actually changing any display after
 634          * a system suspend.  So grab the display core domain, which covers
 635          * the HW blocks needed for the following programming.
 636          */
 637         wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE);
 638
 639         vlv_punit_get(dev_priv);
 640         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
 641         val &= ~DSPFREQGUAR_MASK_CHV;
 642         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
 643         vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val);
 644         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) &
 645                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
 646                      50)) {
 647                 DRM_ERROR("timed out waiting for CDclk change\n");
 648         }
 649
 650         vlv_punit_put(dev_priv);
 651
 652         intel_update_cdclk(dev_priv);
 653
 654         vlv_program_pfi_credits(dev_priv);
 655
 656         intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
 657 }
 658
 659 static int bdw_calc_cdclk(int min_cdclk)
 660 {
 661         if (min_cdclk > 540000)
 662                 return 675000;
 663         else if (min_cdclk > 450000)
 664                 return 540000;
 665         else if (min_cdclk > 337500)
 666                 return 450000;
 667         else
 668                 return 337500;
 669 }
 670
 671 static u8 bdw_calc_voltage_level(int cdclk)
 672 {
 673         switch (cdclk) {
 674         default:
 675         case 337500:
 676                 return 2;
 677         case 450000:
 678                 return 0;
 679         case 540000:
 680                 return 1;
 681         case 675000:
 682                 return 3;
 683         }
 684 }
 685
 686 static void bdw_get_cdclk(struct drm_i915_private *dev_priv,
 687                           struct intel_cdclk_state *cdclk_state)
 688 {
 689         u32 lcpll = I915_READ(LCPLL_CTL);
 690         u32 freq = lcpll & LCPLL_CLK_FREQ_MASK;
 691
 692         if (lcpll & LCPLL_CD_SOURCE_FCLK)
 693                 cdclk_state->cdclk = 800000;
 694         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
 695                 cdclk_state->cdclk = 450000;
 696         else if (freq == LCPLL_CLK_FREQ_450)
 697                 cdclk_state->cdclk = 450000;
 698         else if (freq == LCPLL_CLK_FREQ_54O_BDW)
 699                 cdclk_state->cdclk = 540000;
 700         else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
 701                 cdclk_state->cdclk = 337500;
 702         else
 703                 cdclk_state->cdclk = 675000;
 704
 705         /*
 706          * Can't read this out :( Let's assume it's
 707          * at least what the CDCLK frequency requires.
 708          */
 709         cdclk_state->voltage_level =
 710                 bdw_calc_voltage_level(cdclk_state->cdclk);
 711 }
 712
 713 static void bdw_set_cdclk(struct drm_i915_private *dev_priv,
 714                           const struct intel_cdclk_state *cdclk_state,
 715                           enum pipe pipe)
 716 {
 717         int cdclk = cdclk_state->cdclk;
 718         u32 val;
 719         int ret;
 720
 721         if (WARN((I915_READ(LCPLL_CTL) &
 722                   (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
 723                    LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
 724                    LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
 725                    LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
 726                  "trying to change cdclk frequency with cdclk not enabled\n"))
 727                 return;
 728
 729         ret = sandybridge_pcode_write(dev_priv,
 730                                       BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
 731         if (ret) {
 732                 DRM_ERROR("failed to inform pcode about cdclk change\n");
 733                 return;
 734         }
 735
 736         val = I915_READ(LCPLL_CTL);
 737         val |= LCPLL_CD_SOURCE_FCLK;
 738         I915_WRITE(LCPLL_CTL, val);
 739
 740         /*
 741          * According to the spec, it should be enough to poll for this 1 us.
 742          * However, extensive testing shows that this can take longer.
 743          */
 744         if (wait_for_us(I915_READ(LCPLL_CTL) &
 745                         LCPLL_CD_SOURCE_FCLK_DONE, 100))
 746                 DRM_ERROR("Switching to FCLK failed\n");
 747
 748         val = I915_READ(LCPLL_CTL);
 749         val &= ~LCPLL_CLK_FREQ_MASK;
 750
 751         switch (cdclk) {
 752         default:
 753                 MISSING_CASE(cdclk);
 754                 /* fall through */
 755         case 337500:
 756                 val |= LCPLL_CLK_FREQ_337_5_BDW;
 757                 break;
 758         case 450000:
 759                 val |= LCPLL_CLK_FREQ_450;
 760                 break;
 761         case 540000:
 762                 val |= LCPLL_CLK_FREQ_54O_BDW;
 763                 break;
 764         case 675000:
 765                 val |= LCPLL_CLK_FREQ_675_BDW;
 766                 break;
 767         }
 768
 769         I915_WRITE(LCPLL_CTL, val);
 770
 771         val = I915_READ(LCPLL_CTL);
 772         val &= ~LCPLL_CD_SOURCE_FCLK;
 773         I915_WRITE(LCPLL_CTL, val);
 774
 775         if (wait_for_us((I915_READ(LCPLL_CTL) &
 776                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
 777                 DRM_ERROR("Switching back to LCPLL failed\n");
 778
 779         sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
 780                                 cdclk_state->voltage_level);
 781
 782         I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
 783
 784         intel_update_cdclk(dev_priv);
 785 }
 786
 787 static int skl_calc_cdclk(int min_cdclk, int vco)
 788 {
 789         if (vco == 8640000) {
 790                 if (min_cdclk > 540000)
 791                         return 617143;
 792                 else if (min_cdclk > 432000)
 793                         return 540000;
 794                 else if (min_cdclk > 308571)
 795                         return 432000;
 796                 else
 797                         return 308571;
 798         } else {
 799                 if (min_cdclk > 540000)
 800                         return 675000;
 801                 else if (min_cdclk > 450000)
 802                         return 540000;
 803                 else if (min_cdclk > 337500)
 804                         return 450000;
 805                 else
 806                         return 337500;
 807         }
 808 }
 809
 810 static u8 skl_calc_voltage_level(int cdclk)
 811 {
 812         if (cdclk > 540000)
 813                 return 3;
 814         else if (cdclk > 450000)
 815                 return 2;
 816         else if (cdclk > 337500)
 817                 return 1;
 818         else
 819                 return 0;
 820 }
 821
 822 static void skl_dpll0_update(struct drm_i915_private *dev_priv,
 823                              struct intel_cdclk_state *cdclk_state)
 824 {
 825         u32 val;
 826
 827         cdclk_state->ref = 24000;
 828         cdclk_state->vco = 0;
 829
 830         val = I915_READ(LCPLL1_CTL);
 831         if ((val & LCPLL_PLL_ENABLE) == 0)
 832                 return;
 833
 834         if (WARN_ON((val & LCPLL_PLL_LOCK) == 0))
 835                 return;
 836
 837         val = I915_READ(DPLL_CTRL1);
 838
 839         if (WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
 840                             DPLL_CTRL1_SSC(SKL_DPLL0) |
 841                             DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=
 842                     DPLL_CTRL1_OVERRIDE(SKL_DPLL0)))
 843                 return;
 844
 845         switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) {
 846         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0):
 847         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0):
 848         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0):
 849         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0):
 850                 cdclk_state->vco = 8100000;
 851                 break;
 852         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0):
 853         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0):
 854                 cdclk_state->vco = 8640000;
 855                 break;
 856         default:
 857                 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
 858                 break;
 859         }
 860 }
 861
 862 static void skl_get_cdclk(struct drm_i915_private *dev_priv,
 863                           struct intel_cdclk_state *cdclk_state)
 864 {
 865         u32 cdctl;
 866
 867         skl_dpll0_update(dev_priv, cdclk_state);
 868
 869         cdclk_state->cdclk = cdclk_state->bypass = cdclk_state->ref;
 870
 871         if (cdclk_state->vco == 0)
 872                 goto out;
 873
 874         cdctl = I915_READ(CDCLK_CTL);
 875
 876         if (cdclk_state->vco == 8640000) {
 877                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
 878                 case CDCLK_FREQ_450_432:
 879                         cdclk_state->cdclk = 432000;
 880                         break;
 881                 case CDCLK_FREQ_337_308:
 882                         cdclk_state->cdclk = 308571;
 883                         break;
 884                 case CDCLK_FREQ_540:
 885                         cdclk_state->cdclk = 540000;
 886                         break;
 887                 case CDCLK_FREQ_675_617:
 888                         cdclk_state->cdclk = 617143;
 889                         break;
 890                 default:
 891                         MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
 892                         break;
 893                 }
 894         } else {
 895                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
 896                 case CDCLK_FREQ_450_432:
 897                         cdclk_state->cdclk = 450000;
 898                         break;
 899                 case CDCLK_FREQ_337_308:
 900                         cdclk_state->cdclk = 337500;
 901                         break;
 902                 case CDCLK_FREQ_540:
 903                         cdclk_state->cdclk = 540000;
 904                         break;
 905                 case CDCLK_FREQ_675_617:
 906                         cdclk_state->cdclk = 675000;
 907                         break;
 908                 default:
 909                         MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
 910                         break;
 911                 }
 912         }
 913
 914  out:
 915         /*
 916          * Can't read this out :( Let's assume it's
 917          * at least what the CDCLK frequency requires.
 918          */
 919         cdclk_state->voltage_level =
 920                 skl_calc_voltage_level(cdclk_state->cdclk);
 921 }
 922
 923 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
 924 static int skl_cdclk_decimal(int cdclk)
 925 {
 926         return DIV_ROUND_CLOSEST(cdclk - 1000, 500);
 927 }
 928
 929 static void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv,
 930                                         int vco)
 931 {
 932         bool changed = dev_priv->skl_preferred_vco_freq != vco;
 933
 934         dev_priv->skl_preferred_vco_freq = vco;
 935
 936         if (changed)
 937                 intel_update_max_cdclk(dev_priv);
 938 }
 939
 940 static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
 941 {
 942         u32 val;
 943
 944         WARN_ON(vco != 8100000 && vco != 8640000);
 945
 946         /*
 947          * We always enable DPLL0 with the lowest link rate possible, but still
 948          * taking into account the VCO required to operate the eDP panel at the
 949          * desired frequency. The usual DP link rates operate with a VCO of
 950          * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
 951          * The modeset code is responsible for the selection of the exact link
 952          * rate later on, with the constraint of choosing a frequency that
 953          * works with vco.
 954          */
 955         val = I915_READ(DPLL_CTRL1);
 956
 957         val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
 958                  DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
 959         val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
 960         if (vco == 8640000)
 961                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
 962                                             SKL_DPLL0);
 963         else
 964                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
 965                                             SKL_DPLL0);
 966
 967         I915_WRITE(DPLL_CTRL1, val);
 968         POSTING_READ(DPLL_CTRL1);
 969
 970         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
 971
 972         if (intel_de_wait_for_set(dev_priv, LCPLL1_CTL, LCPLL_PLL_LOCK, 5))
 973                 DRM_ERROR("DPLL0 not locked\n");
 974
 975         dev_priv->cdclk.hw.vco = vco;
 976
 977         /* We'll want to keep using the current vco from now on. */
 978         skl_set_preferred_cdclk_vco(dev_priv, vco);
 979 }
 980
 981 static void skl_dpll0_disable(struct drm_i915_private *dev_priv)
 982 {
 983         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
 984         if (intel_de_wait_for_clear(dev_priv, LCPLL1_CTL, LCPLL_PLL_LOCK, 1))
 985                 DRM_ERROR("Couldn't disable DPLL0\n");
 986
 987         dev_priv->cdclk.hw.vco = 0;
 988 }
 989
 990 static void skl_set_cdclk(struct drm_i915_private *dev_priv,
 991                           const struct intel_cdclk_state *cdclk_state,
 992                           enum pipe pipe)
 993 {
 994         int cdclk = cdclk_state->cdclk;
 995         int vco = cdclk_state->vco;
 996         u32 freq_select, cdclk_ctl;
 997         int ret;
 998
 999         /*
1000          * Based on WA#1183 CDCLK rates 308 and 617MHz CDCLK rates are
1001          * unsupported on SKL. In theory this should never happen since only
1002          * the eDP1.4 2.16 and 4.32Gbps rates require it, but eDP1.4 is not
1003          * supported on SKL either, see the above WA. WARN whenever trying to
1004          * use the corresponding VCO freq as that always leads to using the
1005          * minimum 308MHz CDCLK.
1006          */
1007         WARN_ON_ONCE(IS_SKYLAKE(dev_priv) && vco == 8640000);
1008
1009         ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
1010                                 SKL_CDCLK_PREPARE_FOR_CHANGE,
1011                                 SKL_CDCLK_READY_FOR_CHANGE,
1012                                 SKL_CDCLK_READY_FOR_CHANGE, 3);
1013         if (ret) {
1014                 DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n",
1015                           ret);
1016                 return;
1017         }
1018
1019         /* Choose frequency for this cdclk */
1020         switch (cdclk) {
1021         default:
1022                 WARN_ON(cdclk != dev_priv->cdclk.hw.bypass);
1023                 WARN_ON(vco != 0);
1024                 /* fall through */
1025         case 308571:
1026         case 337500:
1027                 freq_select = CDCLK_FREQ_337_308;
1028                 break;
1029         case 450000:
1030         case 432000:
1031                 freq_select = CDCLK_FREQ_450_432;
1032                 break;
1033         case 540000:
1034                 freq_select = CDCLK_FREQ_540;
1035                 break;
1036         case 617143:
1037         case 675000:
1038                 freq_select = CDCLK_FREQ_675_617;
1039                 break;
1040         }
1041
1042         if (dev_priv->cdclk.hw.vco != 0 &&
1043             dev_priv->cdclk.hw.vco != vco)
1044                 skl_dpll0_disable(dev_priv);
1045
1046         cdclk_ctl = I915_READ(CDCLK_CTL);
1047
1048         if (dev_priv->cdclk.hw.vco != vco) {
1049                 /* Wa Display #1183: skl,kbl,cfl */
1050                 cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
1051                 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
1052                 I915_WRITE(CDCLK_CTL, cdclk_ctl);
1053         }
1054
1055         /* Wa Display #1183: skl,kbl,cfl */
1056         cdclk_ctl |= CDCLK_DIVMUX_CD_OVERRIDE;
1057         I915_WRITE(CDCLK_CTL, cdclk_ctl);
1058         POSTING_READ(CDCLK_CTL);
1059
1060         if (dev_priv->cdclk.hw.vco != vco)
1061                 skl_dpll0_enable(dev_priv, vco);
1062
1063         /* Wa Display #1183: skl,kbl,cfl */
1064         cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
1065         I915_WRITE(CDCLK_CTL, cdclk_ctl);
1066
1067         cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
1068         I915_WRITE(CDCLK_CTL, cdclk_ctl);
1069
1070         /* Wa Display #1183: skl,kbl,cfl */
1071         cdclk_ctl &= ~CDCLK_DIVMUX_CD_OVERRIDE;
1072         I915_WRITE(CDCLK_CTL, cdclk_ctl);
1073         POSTING_READ(CDCLK_CTL);
1074
1075         /* inform PCU of the change */
1076         sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
1077                                 cdclk_state->voltage_level);
1078
1079         intel_update_cdclk(dev_priv);
1080 }
1081
1082 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
1083 {
1084         u32 cdctl, expected;
1085
1086         /*
1087          * check if the pre-os initialized the display
1088          * There is SWF18 scratchpad register defined which is set by the
1089          * pre-os which can be used by the OS drivers to check the status
1090          */
1091         if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
1092                 goto sanitize;
1093
1094         intel_update_cdclk(dev_priv);
1095         intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
1096
1097         /* Is PLL enabled and locked ? */
1098         if (dev_priv->cdclk.hw.vco == 0 ||
1099             dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass)
1100                 goto sanitize;
1101
1102         /* DPLL okay; verify the cdclock
1103          *
1104          * Noticed in some instances that the freq selection is correct but
1105          * decimal part is programmed wrong from BIOS where pre-os does not
1106          * enable display. Verify the same as well.
1107          */
1108         cdctl = I915_READ(CDCLK_CTL);
1109         expected = (cdctl & CDCLK_FREQ_SEL_MASK) |
1110                 skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk);
1111         if (cdctl == expected)
1112                 /* All well; nothing to sanitize */
1113                 return;
1114
1115 sanitize:
1116         DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
1117
1118         /* force cdclk programming */
1119         dev_priv->cdclk.hw.cdclk = 0;
1120         /* force full PLL disable + enable */
1121         dev_priv->cdclk.hw.vco = -1;
1122 }
1123
1124 static void skl_init_cdclk(struct drm_i915_private *dev_priv)
1125 {
1126         struct intel_cdclk_state cdclk_state;
1127
1128         skl_sanitize_cdclk(dev_priv);
1129
1130         if (dev_priv->cdclk.hw.cdclk != 0 &&
1131             dev_priv->cdclk.hw.vco != 0) {
1132                 /*
1133                  * Use the current vco as our initial
1134                  * guess as to what the preferred vco is.
1135                  */
1136                 if (dev_priv->skl_preferred_vco_freq == 0)
1137                         skl_set_preferred_cdclk_vco(dev_priv,
1138                                                     dev_priv->cdclk.hw.vco);
1139                 return;
1140         }
1141
1142         cdclk_state = dev_priv->cdclk.hw;
1143
1144         cdclk_state.vco = dev_priv->skl_preferred_vco_freq;
1145         if (cdclk_state.vco == 0)
1146                 cdclk_state.vco = 8100000;
1147         cdclk_state.cdclk = skl_calc_cdclk(0, cdclk_state.vco);
1148         cdclk_state.voltage_level = skl_calc_voltage_level(cdclk_state.cdclk);
1149
1150         skl_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
1151 }
1152
1153 static void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
1154 {
1155         struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
1156
1157         cdclk_state.cdclk = cdclk_state.bypass;
1158         cdclk_state.vco = 0;
1159         cdclk_state.voltage_level = skl_calc_voltage_level(cdclk_state.cdclk);
1160
1161         skl_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
1162 }
1163
1164 static int bxt_calc_cdclk(int min_cdclk)
1165 {
1166         if (min_cdclk > 576000)
1167                 return 624000;
1168         else if (min_cdclk > 384000)
1169                 return 576000;
1170         else if (min_cdclk > 288000)
1171                 return 384000;
1172         else if (min_cdclk > 144000)
1173                 return 288000;
1174         else
1175                 return 144000;
1176 }
1177
1178 static int glk_calc_cdclk(int min_cdclk)
1179 {
1180         if (min_cdclk > 158400)
1181                 return 316800;
1182         else if (min_cdclk > 79200)
1183                 return 158400;
1184         else
1185                 return 79200;
1186 }
1187
1188 static u8 bxt_calc_voltage_level(int cdclk)
1189 {
1190         return DIV_ROUND_UP(cdclk, 25000);
1191 }
1192
1193 static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
1194 {
1195         int ratio;
1196
1197         if (cdclk == dev_priv->cdclk.hw.bypass)
1198                 return 0;
1199
1200         switch (cdclk) {
1201         default:
1202                 MISSING_CASE(cdclk);
1203                 /* fall through */
1204         case 144000:
1205         case 288000:
1206         case 384000:
1207         case 576000:
1208                 ratio = 60;
1209                 break;
1210         case 624000:
1211                 ratio = 65;
1212                 break;
1213         }
1214
1215         return dev_priv->cdclk.hw.ref * ratio;
1216 }
1217
1218 static int glk_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
1219 {
1220         int ratio;
1221
1222         if (cdclk == dev_priv->cdclk.hw.bypass)
1223                 return 0;
1224
1225         switch (cdclk) {
1226         default:
1227                 MISSING_CASE(cdclk);
1228                 /* fall through */
1229         case  79200:
1230         case 158400:
1231         case 316800:
1232                 ratio = 33;
1233                 break;
1234         }
1235
1236         return dev_priv->cdclk.hw.ref * ratio;
1237 }
1238
1239 static void bxt_de_pll_update(struct drm_i915_private *dev_priv,
1240                               struct intel_cdclk_state *cdclk_state)
1241 {
1242         u32 val;
1243
1244         cdclk_state->ref = 19200;
1245         cdclk_state->vco = 0;
1246
1247         val = I915_READ(BXT_DE_PLL_ENABLE);
1248         if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
1249                 return;
1250
1251         if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
1252                 return;
1253
1254         val = I915_READ(BXT_DE_PLL_CTL);
1255         cdclk_state->vco = (val & BXT_DE_PLL_RATIO_MASK) * cdclk_state->ref;
1256 }
1257
1258 static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
1259                           struct intel_cdclk_state *cdclk_state)
1260 {
1261         u32 divider;
1262         int div;
1263
1264         bxt_de_pll_update(dev_priv, cdclk_state);
1265
1266         cdclk_state->cdclk = cdclk_state->bypass = cdclk_state->ref;
1267
1268         if (cdclk_state->vco == 0)
1269                 goto out;
1270
1271         divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
1272
1273         switch (divider) {
1274         case BXT_CDCLK_CD2X_DIV_SEL_1:
1275                 div = 2;
1276                 break;
1277         case BXT_CDCLK_CD2X_DIV_SEL_1_5:
1278                 WARN(IS_GEMINILAKE(dev_priv), "Unsupported divider\n");
1279                 div = 3;
1280                 break;
1281         case BXT_CDCLK_CD2X_DIV_SEL_2:
1282                 div = 4;
1283                 break;
1284         case BXT_CDCLK_CD2X_DIV_SEL_4:
1285                 div = 8;
1286                 break;
1287         default:
1288                 MISSING_CASE(divider);
1289                 return;
1290         }
1291
1292         cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, div);
1293
1294  out:
1295         /*
1296          * Can't read this out :( Let's assume it's
1297          * at least what the CDCLK frequency requires.
1298          */
1299         cdclk_state->voltage_level =
1300                 bxt_calc_voltage_level(cdclk_state->cdclk);
1301 }
1302
1303 static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
1304 {
1305         I915_WRITE(BXT_DE_PLL_ENABLE, 0);
1306
1307         /* Timeout 200us */
1308         if (intel_de_wait_for_clear(dev_priv,
1309                                     BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
1310                 DRM_ERROR("timeout waiting for DE PLL unlock\n");
1311
1312         dev_priv->cdclk.hw.vco = 0;
1313 }
1314
1315 static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)
1316 {
1317         int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);
1318         u32 val;
1319
1320         val = I915_READ(BXT_DE_PLL_CTL);
1321         val &= ~BXT_DE_PLL_RATIO_MASK;
1322         val |= BXT_DE_PLL_RATIO(ratio);
1323         I915_WRITE(BXT_DE_PLL_CTL, val);
1324
1325         I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
1326
1327         /* Timeout 200us */
1328         if (intel_de_wait_for_set(dev_priv,
1329                                   BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
1330                 DRM_ERROR("timeout waiting for DE PLL lock\n");
1331
1332         dev_priv->cdclk.hw.vco = vco;
1333 }
1334
1335 static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
1336                           const struct intel_cdclk_state *cdclk_state,
1337                           enum pipe pipe)
1338 {
1339         int cdclk = cdclk_state->cdclk;
1340         int vco = cdclk_state->vco;
1341         u32 val, divider;
1342         int ret;
1343
1344         /* cdclk = vco / 2 / div{1,1.5,2,4} */
1345         switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
1346         default:
1347                 WARN_ON(cdclk != dev_priv->cdclk.hw.bypass);
1348                 WARN_ON(vco != 0);
1349                 /* fall through */
1350         case 2:
1351                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
1352                 break;
1353         case 3:
1354                 WARN(IS_GEMINILAKE(dev_priv), "Unsupported divider\n");
1355                 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
1356                 break;
1357         case 4:
1358                 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
1359                 break;
1360         case 8:
1361                 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
1362                 break;
1363         }
1364
1365         /*
1366          * Inform power controller of upcoming frequency change. BSpec
1367          * requires us to wait up to 150usec, but that leads to timeouts;
1368          * the 2ms used here is based on experiment.
1369          */
1370         ret = sandybridge_pcode_write_timeout(dev_priv,
1371                                               HSW_PCODE_DE_WRITE_FREQ_REQ,
1372                                               0x80000000, 150, 2);
1373         if (ret) {
1374                 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
1375                           ret, cdclk);
1376                 return;
1377         }
1378
1379         if (dev_priv->cdclk.hw.vco != 0 &&
1380             dev_priv->cdclk.hw.vco != vco)
1381                 bxt_de_pll_disable(dev_priv);
1382
1383         if (dev_priv->cdclk.hw.vco != vco)
1384                 bxt_de_pll_enable(dev_priv, vco);
1385
1386         val = divider | skl_cdclk_decimal(cdclk);
1387         if (pipe == INVALID_PIPE)
1388                 val |= BXT_CDCLK_CD2X_PIPE_NONE;
1389         else
1390                 val |= BXT_CDCLK_CD2X_PIPE(pipe);
1391         /*
1392          * Disable SSA Precharge when CD clock frequency < 500 MHz,
1393          * enable otherwise.
1394          */
1395         if (cdclk >= 500000)
1396                 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
1397         I915_WRITE(CDCLK_CTL, val);
1398
1399         if (pipe != INVALID_PIPE)
1400                 intel_wait_for_vblank(dev_priv, pipe);
1401
1402         /*
1403          * The timeout isn't specified, the 2ms used here is based on
1404          * experiment.
1405          * FIXME: Waiting for the request completion could be delayed until
1406          * the next PCODE request based on BSpec.
1407          */
1408         ret = sandybridge_pcode_write_timeout(dev_priv,
1409                                               HSW_PCODE_DE_WRITE_FREQ_REQ,
1410                                               cdclk_state->voltage_level, 150, 2);
1411         if (ret) {
1412                 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
1413                           ret, cdclk);
1414                 return;
1415         }
1416
1417         intel_update_cdclk(dev_priv);
1418 }
1419
1420 static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
1421 {
1422         u32 cdctl, expected;
1423
1424         intel_update_cdclk(dev_priv);
1425         intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
1426
1427         if (dev_priv->cdclk.hw.vco == 0 ||
1428             dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass)
1429                 goto sanitize;
1430
1431         /* DPLL okay; verify the cdclock
1432          *
1433          * Some BIOS versions leave an incorrect decimal frequency value and
1434          * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
1435          * so sanitize this register.
1436          */
1437         cdctl = I915_READ(CDCLK_CTL);
1438         /*
1439          * Let's ignore the pipe field, since BIOS could have configured the
1440          * dividers both synching to an active pipe, or asynchronously
1441          * (PIPE_NONE).
1442          */
1443         cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
1444
1445         expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) |
1446                 skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk);
1447         /*
1448          * Disable SSA Precharge when CD clock frequency < 500 MHz,
1449          * enable otherwise.
1450          */
1451         if (dev_priv->cdclk.hw.cdclk >= 500000)
1452                 expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
1453
1454         if (cdctl == expected)
1455                 /* All well; nothing to sanitize */
1456                 return;
1457
1458 sanitize:
1459         DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
1460
1461         /* force cdclk programming */
1462         dev_priv->cdclk.hw.cdclk = 0;
1463
1464         /* force full PLL disable + enable */
1465         dev_priv->cdclk.hw.vco = -1;
1466 }
1467
1468 static void bxt_init_cdclk(struct drm_i915_private *dev_priv)
1469 {
1470         struct intel_cdclk_state cdclk_state;
1471
1472         bxt_sanitize_cdclk(dev_priv);
1473
1474         if (dev_priv->cdclk.hw.cdclk != 0 &&
1475             dev_priv->cdclk.hw.vco != 0)
1476                 return;
1477
1478         cdclk_state = dev_priv->cdclk.hw;
1479
1480         /*
1481          * FIXME:
1482          * - The initial CDCLK needs to be read from VBT.
1483          *   Need to make this change after VBT has changes for BXT.
1484          */
1485         if (IS_GEMINILAKE(dev_priv)) {
1486                 cdclk_state.cdclk = glk_calc_cdclk(0);
1487                 cdclk_state.vco = glk_de_pll_vco(dev_priv, cdclk_state.cdclk);
1488         } else {
1489                 cdclk_state.cdclk = bxt_calc_cdclk(0);
1490                 cdclk_state.vco = bxt_de_pll_vco(dev_priv, cdclk_state.cdclk);
1491         }
1492         cdclk_state.voltage_level = bxt_calc_voltage_level(cdclk_state.cdclk);
1493
1494         bxt_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
1495 }
1496
1497 static void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
1498 {
1499         struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
1500
1501         cdclk_state.cdclk = cdclk_state.bypass;
1502         cdclk_state.vco = 0;
1503         cdclk_state.voltage_level = bxt_calc_voltage_level(cdclk_state.cdclk);
1504
1505         bxt_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
1506 }
1507
1508 static int cnl_calc_cdclk(int min_cdclk)
1509 {
1510         if (min_cdclk > 336000)
1511                 return 528000;
1512         else if (min_cdclk > 168000)
1513                 return 336000;
1514         else
1515                 return 168000;
1516 }
1517
1518 static u8 cnl_calc_voltage_level(int cdclk)
1519 {
1520         if (cdclk > 336000)
1521                 return 2;
1522         else if (cdclk > 168000)
1523                 return 1;
1524         else
1525                 return 0;
1526 }
1527
1528 static void cnl_cdclk_pll_update(struct drm_i915_private *dev_priv,
1529                                  struct intel_cdclk_state *cdclk_state)
1530 {
1531         u32 val;
1532
1533         if (I915_READ(SKL_DSSM) & CNL_DSSM_CDCLK_PLL_REFCLK_24MHz)
1534                 cdclk_state->ref = 24000;
1535         else
1536                 cdclk_state->ref = 19200;
1537
1538         cdclk_state->vco = 0;
1539
1540         val = I915_READ(BXT_DE_PLL_ENABLE);
1541         if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
1542                 return;
1543
1544         if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
1545                 return;
1546
1547         cdclk_state->vco = (val & CNL_CDCLK_PLL_RATIO_MASK) * cdclk_state->ref;
1548 }
1549
1550 static void cnl_get_cdclk(struct drm_i915_private *dev_priv,
1551                          struct intel_cdclk_state *cdclk_state)
1552 {
1553         u32 divider;
1554         int div;
1555
1556         cnl_cdclk_pll_update(dev_priv, cdclk_state);
1557
1558         cdclk_state->cdclk = cdclk_state->bypass = cdclk_state->ref;
1559
1560         if (cdclk_state->vco == 0)
1561                 goto out;
1562
1563         divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
1564
1565         switch (divider) {
1566         case BXT_CDCLK_CD2X_DIV_SEL_1:
1567                 div = 2;
1568                 break;
1569         case BXT_CDCLK_CD2X_DIV_SEL_2:
1570                 div = 4;
1571                 break;
1572         default:
1573                 MISSING_CASE(divider);
1574                 return;
1575         }
1576
1577         cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, div);
1578
1579  out:
1580         /*
1581          * Can't read this out :( Let's assume it's
1582          * at least what the CDCLK frequency requires.
1583          */
1584         cdclk_state->voltage_level =
1585                 cnl_calc_voltage_level(cdclk_state->cdclk);
1586 }
1587
1588 static void cnl_cdclk_pll_disable(struct drm_i915_private *dev_priv)
1589 {
1590         u32 val;
1591
1592         val = I915_READ(BXT_DE_PLL_ENABLE);
1593         val &= ~BXT_DE_PLL_PLL_ENABLE;
1594         I915_WRITE(BXT_DE_PLL_ENABLE, val);
1595
1596         /* Timeout 200us */
1597         if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) == 0, 1))
1598                 DRM_ERROR("timeout waiting for CDCLK PLL unlock\n");
1599
1600         dev_priv->cdclk.hw.vco = 0;
1601 }
1602
1603 static void cnl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco)
1604 {
1605         int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);
1606         u32 val;
1607
1608         val = CNL_CDCLK_PLL_RATIO(ratio);
1609         I915_WRITE(BXT_DE_PLL_ENABLE, val);
1610
1611         val |= BXT_DE_PLL_PLL_ENABLE;
1612         I915_WRITE(BXT_DE_PLL_ENABLE, val);
1613
1614         /* Timeout 200us */
1615         if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) != 0, 1))
1616                 DRM_ERROR("timeout waiting for CDCLK PLL lock\n");
1617
1618         dev_priv->cdclk.hw.vco = vco;
1619 }
1620
1621 static void cnl_set_cdclk(struct drm_i915_private *dev_priv,
1622                           const struct intel_cdclk_state *cdclk_state,
1623                           enum pipe pipe)
1624 {
1625         int cdclk = cdclk_state->cdclk;
1626         int vco = cdclk_state->vco;
1627         u32 val, divider;
1628         int ret;
1629
1630         ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
1631                                 SKL_CDCLK_PREPARE_FOR_CHANGE,
1632                                 SKL_CDCLK_READY_FOR_CHANGE,
1633                                 SKL_CDCLK_READY_FOR_CHANGE, 3);
1634         if (ret) {
1635                 DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n",
1636                           ret);
1637                 return;
1638         }
1639
1640         /* cdclk = vco / 2 / div{1,2} */
1641         switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
1642         default:
1643                 WARN_ON(cdclk != dev_priv->cdclk.hw.bypass);
1644                 WARN_ON(vco != 0);
1645                 /* fall through */
1646         case 2:
1647                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
1648                 break;
1649         case 4:
1650                 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
1651                 break;
1652         }
1653
1654         if (dev_priv->cdclk.hw.vco != 0 &&
1655             dev_priv->cdclk.hw.vco != vco)
1656                 cnl_cdclk_pll_disable(dev_priv);
1657
1658         if (dev_priv->cdclk.hw.vco != vco)
1659                 cnl_cdclk_pll_enable(dev_priv, vco);
1660
1661         val = divider | skl_cdclk_decimal(cdclk);
1662
1663         if (INTEL_GEN(dev_priv) >= 12) {
1664                 if (pipe == INVALID_PIPE)
1665                         val |= TGL_CDCLK_CD2X_PIPE_NONE;
1666                 else
1667                         val |= TGL_CDCLK_CD2X_PIPE(pipe);
1668         } else if (INTEL_GEN(dev_priv) >= 11) {
1669                 if (pipe == INVALID_PIPE)
1670                         val |= ICL_CDCLK_CD2X_PIPE_NONE;
1671                 else
1672                         val |= ICL_CDCLK_CD2X_PIPE(pipe);
1673         } else {
1674                 if (pipe == INVALID_PIPE)
1675                         val |= BXT_CDCLK_CD2X_PIPE_NONE;
1676                 else
1677                         val |= BXT_CDCLK_CD2X_PIPE(pipe);
1678         }
1679         I915_WRITE(CDCLK_CTL, val);
1680
1681         if (pipe != INVALID_PIPE)
1682                 intel_wait_for_vblank(dev_priv, pipe);
1683
1684         /* inform PCU of the change */
1685         sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
1686                                 cdclk_state->voltage_level);
1687
1688         intel_update_cdclk(dev_priv);
1689
1690         /*
1691          * Can't read out the voltage level :(
1692          * Let's just assume everything is as expected.
1693          */
1694         dev_priv->cdclk.hw.voltage_level = cdclk_state->voltage_level;
1695 }
1696
1697 static int cnl_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
1698 {
1699         int ratio;
1700
1701         if (cdclk == dev_priv->cdclk.hw.bypass)
1702                 return 0;
1703
1704         switch (cdclk) {
1705         default:
1706                 MISSING_CASE(cdclk);
1707                 /* fall through */
1708         case 168000:
1709         case 336000:
1710                 ratio = dev_priv->cdclk.hw.ref == 19200 ? 35 : 28;
1711                 break;
1712         case 528000:
1713                 ratio = dev_priv->cdclk.hw.ref == 19200 ? 55 : 44;
1714                 break;
1715         }
1716
1717         return dev_priv->cdclk.hw.ref * ratio;
1718 }
1719
1720 static void cnl_sanitize_cdclk(struct drm_i915_private *dev_priv)
1721 {
1722         u32 cdctl, expected;
1723
1724         intel_update_cdclk(dev_priv);
1725         intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
1726
1727         if (dev_priv->cdclk.hw.vco == 0 ||
1728             dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass)
1729                 goto sanitize;
1730
1731         /* DPLL okay; verify the cdclock
1732          *
1733          * Some BIOS versions leave an incorrect decimal frequency value and
1734          * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
1735          * so sanitize this register.
1736          */
1737         cdctl = I915_READ(CDCLK_CTL);
1738         /*
1739          * Let's ignore the pipe field, since BIOS could have configured the
1740          * dividers both synching to an active pipe, or asynchronously
1741          * (PIPE_NONE).
1742          */
1743         cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
1744
1745         expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) |
1746                    skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk);
1747
1748         if (cdctl == expected)
1749                 /* All well; nothing to sanitize */
1750                 return;
1751
1752 sanitize:
1753         DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
1754
1755         /* force cdclk programming */
1756         dev_priv->cdclk.hw.cdclk = 0;
1757
1758         /* force full PLL disable + enable */
1759         dev_priv->cdclk.hw.vco = -1;
1760 }
1761
1762 static int icl_calc_cdclk(int min_cdclk, unsigned int ref)
1763 {
1764         static const int ranges_24[] = { 180000, 192000, 312000, 552000, 648000 };
1765         static const int ranges_19_38[] = { 172800, 192000, 307200, 556800, 652800 };
1766         const int *ranges;
1767         int len, i;
1768
1769         switch (ref) {
1770         default:
1771                 MISSING_CASE(ref);
1772                 /* fall through */
1773         case 24000:
1774                 ranges = ranges_24;
1775                 len = ARRAY_SIZE(ranges_24);
1776                 break;
1777         case 19200:
1778         case 38400:
1779                 ranges = ranges_19_38;
1780                 len = ARRAY_SIZE(ranges_19_38);
1781                 break;
1782         }
1783
1784         for (i = 0; i < len; i++) {
1785                 if (min_cdclk <= ranges[i])
1786                         return ranges[i];
1787         }
1788
1789         WARN_ON(min_cdclk > ranges[len - 1]);
1790         return ranges[len - 1];
1791 }
1792
1793 static int icl_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
1794 {
1795         int ratio;
1796
1797         if (cdclk == dev_priv->cdclk.hw.bypass)
1798                 return 0;
1799
1800         switch (cdclk) {
1801         default:
1802                 MISSING_CASE(cdclk);
1803                 /* fall through */
1804         case 172800:
1805         case 307200:
1806         case 556800:
1807         case 652800:
1808                 WARN_ON(dev_priv->cdclk.hw.ref != 19200 &&
1809                         dev_priv->cdclk.hw.ref != 38400);
1810                 break;
1811         case 180000:
1812         case 312000:
1813         case 552000:
1814         case 648000:
1815                 WARN_ON(dev_priv->cdclk.hw.ref != 24000);
1816                 break;
1817         case 192000:
1818                 WARN_ON(dev_priv->cdclk.hw.ref != 19200 &&
1819                         dev_priv->cdclk.hw.ref != 38400 &&
1820                         dev_priv->cdclk.hw.ref != 24000);
1821                 break;
1822         }
1823
1824         ratio = cdclk / (dev_priv->cdclk.hw.ref / 2);
1825
1826         return dev_priv->cdclk.hw.ref * ratio;
1827 }
1828
1829 static u8 icl_calc_voltage_level(struct drm_i915_private *dev_priv, int cdclk)
1830 {
1831         if (IS_ELKHARTLAKE(dev_priv)) {
1832                 if (cdclk > 312000)
1833                         return 2;
1834                 else if (cdclk > 180000)
1835                         return 1;
1836                 else
1837                         return 0;
1838         } else {
1839                 if (cdclk > 556800)
1840                         return 2;
1841                 else if (cdclk > 312000)
1842                         return 1;
1843                 else
1844                         return 0;
1845         }
1846 }
1847
1848 static void icl_get_cdclk(struct drm_i915_private *dev_priv,
1849                           struct intel_cdclk_state *cdclk_state)
1850 {
1851         u32 val;
1852         int div;
1853
1854         cdclk_state->bypass = 50000;
1855
1856         val = I915_READ(SKL_DSSM);
1857         switch (val & ICL_DSSM_CDCLK_PLL_REFCLK_MASK) {
1858         default:
1859                 MISSING_CASE(val);
1860                 /* fall through */
1861         case ICL_DSSM_CDCLK_PLL_REFCLK_24MHz:
1862                 cdclk_state->ref = 24000;
1863                 break;
1864         case ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz:
1865                 cdclk_state->ref = 19200;
1866                 break;
1867         case ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz:
1868                 cdclk_state->ref = 38400;
1869                 break;
1870         }
1871
1872         val = I915_READ(BXT_DE_PLL_ENABLE);
1873         if ((val & BXT_DE_PLL_PLL_ENABLE) == 0 ||
1874             (val & BXT_DE_PLL_LOCK) == 0) {
1875                 /*
1876                  * CDCLK PLL is disabled, the VCO/ratio doesn't matter, but
1877                  * setting it to zero is a way to signal that.
1878                  */
1879                 cdclk_state->vco = 0;
1880                 cdclk_state->cdclk = cdclk_state->bypass;
1881                 goto out;
1882         }
1883
1884         cdclk_state->vco = (val & BXT_DE_PLL_RATIO_MASK) * cdclk_state->ref;
1885
1886         val = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
1887         switch (val) {
1888         case BXT_CDCLK_CD2X_DIV_SEL_1:
1889                 div = 2;
1890                 break;
1891         case BXT_CDCLK_CD2X_DIV_SEL_2:
1892                 div = 4;
1893                 break;
1894         default:
1895                 MISSING_CASE(val);
1896                 div = 2;
1897                 break;
1898         }
1899
1900         cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, div);
1901
1902 out:
1903         /*
1904          * Can't read this out :( Let's assume it's
1905          * at least what the CDCLK frequency requires.
1906          */
1907         cdclk_state->voltage_level =
1908                 icl_calc_voltage_level(dev_priv, cdclk_state->cdclk);
1909 }
1910
1911 static void icl_init_cdclk(struct drm_i915_private *dev_priv)
1912 {
1913         struct intel_cdclk_state sanitized_state;
1914         u32 val;
1915
1916         /* This sets dev_priv->cdclk.hw. */
1917         intel_update_cdclk(dev_priv);
1918         intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
1919
1920         /* This means CDCLK disabled. */
1921         if (dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass)
1922                 goto sanitize;
1923
1924         val = I915_READ(CDCLK_CTL);
1925
1926         if ((val & BXT_CDCLK_CD2X_DIV_SEL_MASK) != 0)
1927                 goto sanitize;
1928
1929         if ((val & CDCLK_FREQ_DECIMAL_MASK) !=
1930             skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk))
1931                 goto sanitize;
1932
1933         return;
1934
1935 sanitize:
1936         DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
1937
1938         sanitized_state.ref = dev_priv->cdclk.hw.ref;
1939         sanitized_state.cdclk = icl_calc_cdclk(0, sanitized_state.ref);
1940         sanitized_state.vco = icl_calc_cdclk_pll_vco(dev_priv,
1941                                                      sanitized_state.cdclk);
1942         sanitized_state.voltage_level =
1943                                 icl_calc_voltage_level(dev_priv,
1944                                                        sanitized_state.cdclk);
1945
1946         cnl_set_cdclk(dev_priv, &sanitized_state, INVALID_PIPE);
1947 }
1948
1949 static void icl_uninit_cdclk(struct drm_i915_private *dev_priv)
1950 {
1951         struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
1952
1953         cdclk_state.cdclk = cdclk_state.bypass;
1954         cdclk_state.vco = 0;
1955         cdclk_state.voltage_level = icl_calc_voltage_level(dev_priv,
1956                                                            cdclk_state.cdclk);
1957
1958         cnl_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
1959 }
1960
1961 static void cnl_init_cdclk(struct drm_i915_private *dev_priv)
1962 {
1963         struct intel_cdclk_state cdclk_state;
1964
1965         cnl_sanitize_cdclk(dev_priv);
1966
1967         if (dev_priv->cdclk.hw.cdclk != 0 &&
1968             dev_priv->cdclk.hw.vco != 0)
1969                 return;
1970
1971         cdclk_state = dev_priv->cdclk.hw;
1972
1973         cdclk_state.cdclk = cnl_calc_cdclk(0);
1974         cdclk_state.vco = cnl_cdclk_pll_vco(dev_priv, cdclk_state.cdclk);
1975         cdclk_state.voltage_level = cnl_calc_voltage_level(cdclk_state.cdclk);
1976
1977         cnl_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
1978 }
1979
1980 static void cnl_uninit_cdclk(struct drm_i915_private *dev_priv)
1981 {
1982         struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
1983
1984         cdclk_state.cdclk = cdclk_state.bypass;
1985         cdclk_state.vco = 0;
1986         cdclk_state.voltage_level = cnl_calc_voltage_level(cdclk_state.cdclk);
1987
1988         cnl_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
1989 }
1990
1991 /**
1992  * intel_cdclk_init - Initialize CDCLK
1993  * @i915: i915 device
1994  *
1995  * Initialize CDCLK. This consists mainly of initializing dev_priv->cdclk.hw and
1996  * sanitizing the state of the hardware if needed. This is generally done only
1997  * during the display core initialization sequence, after which the DMC will
1998  * take care of turning CDCLK off/on as needed.
1999  */
2000 void intel_cdclk_init(struct drm_i915_private *i915)
2001 {
2002         if (INTEL_GEN(i915) >= 11)
2003                 icl_init_cdclk(i915);
2004         else if (IS_CANNONLAKE(i915))
2005                 cnl_init_cdclk(i915);
2006         else if (IS_GEN9_BC(i915))
2007                 skl_init_cdclk(i915);
2008         else if (IS_GEN9_LP(i915))
2009                 bxt_init_cdclk(i915);
2010 }
2011
2012 /**
2013  * intel_cdclk_uninit - Uninitialize CDCLK
2014  * @i915: i915 device
2015  *
2016  * Uninitialize CDCLK. This is done only during the display core
2017  * uninitialization sequence.
2018  */
2019 void intel_cdclk_uninit(struct drm_i915_private *i915)
2020 {
2021         if (INTEL_GEN(i915) >= 11)
2022                 icl_uninit_cdclk(i915);
2023         else if (IS_CANNONLAKE(i915))
2024                 cnl_uninit_cdclk(i915);
2025         else if (IS_GEN9_BC(i915))
2026                 skl_uninit_cdclk(i915);
2027         else if (IS_GEN9_LP(i915))
2028                 bxt_uninit_cdclk(i915);
2029 }
2030
2031 /**
2032  * intel_cdclk_needs_modeset - Determine if two CDCLK states require a modeset on all pipes
2033  * @a: first CDCLK state
2034  * @b: second CDCLK state
2035  *
2036  * Returns:
2037  * True if the CDCLK states require pipes to be off during reprogramming, false if not.
2038  */
2039 bool intel_cdclk_needs_modeset(const struct intel_cdclk_state *a,
2040                                const struct intel_cdclk_state *b)
2041 {
2042         return a->cdclk != b->cdclk ||
2043                 a->vco != b->vco ||
2044                 a->ref != b->ref;
2045 }
2046
2047 /**
2048  * intel_cdclk_needs_cd2x_update - Determine if two CDCLK states require a cd2x divider update
2049  * @dev_priv: Not a CDCLK state, it's the drm_i915_private!
2050  * @a: first CDCLK state
2051  * @b: second CDCLK state
2052  *
2053  * Returns:
2054  * True if the CDCLK states require just a cd2x divider update, false if not.
2055  */
2056 bool intel_cdclk_needs_cd2x_update(struct drm_i915_private *dev_priv,
2057                                    const struct intel_cdclk_state *a,
2058                                    const struct intel_cdclk_state *b)
2059 {
2060         /* Older hw doesn't have the capability */
2061         if (INTEL_GEN(dev_priv) < 10 && !IS_GEN9_LP(dev_priv))
2062                 return false;
2063
2064         return a->cdclk != b->cdclk &&
2065                 a->vco == b->vco &&
2066                 a->ref == b->ref;
2067 }
2068
2069 /**
2070  * intel_cdclk_changed - Determine if two CDCLK states are different
2071  * @a: first CDCLK state
2072  * @b: second CDCLK state
2073  *
2074  * Returns:
2075  * True if the CDCLK states don't match, false if they do.
2076  */
2077 bool intel_cdclk_changed(const struct intel_cdclk_state *a,
2078                          const struct intel_cdclk_state *b)
2079 {
2080         return intel_cdclk_needs_modeset(a, b) ||
2081                 a->voltage_level != b->voltage_level;
2082 }
2083
2084 /**
2085  * intel_cdclk_swap_state - make atomic CDCLK configuration effective
2086  * @state: atomic state
2087  *
2088  * This is the CDCLK version of drm_atomic_helper_swap_state() since the
2089  * helper does not handle driver-specific global state.
2090  *
2091  * Similarly to the atomic helpers this function does a complete swap,
2092  * i.e. it also puts the old state into @state. This is used by the commit
2093  * code to determine how CDCLK has changed (for instance did it increase or
2094  * decrease).
2095  */
2096 void intel_cdclk_swap_state(struct intel_atomic_state *state)
2097 {
2098         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2099
2100         swap(state->cdclk.logical, dev_priv->cdclk.logical);
2101         swap(state->cdclk.actual, dev_priv->cdclk.actual);
2102 }
2103
2104 void intel_dump_cdclk_state(const struct intel_cdclk_state *cdclk_state,
2105                             const char *context)
2106 {
2107         DRM_DEBUG_DRIVER("%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz, voltage level %d\n",
2108                          context, cdclk_state->cdclk, cdclk_state->vco,
2109                          cdclk_state->ref, cdclk_state->bypass,
2110                          cdclk_state->voltage_level);
2111 }
2112
2113 /**
2114  * intel_set_cdclk - Push the CDCLK state to the hardware
2115  * @dev_priv: i915 device
2116  * @cdclk_state: new CDCLK state
2117  * @pipe: pipe with which to synchronize the update
2118  *
2119  * Program the hardware based on the passed in CDCLK state,
2120  * if necessary.
2121  */
2122 static void intel_set_cdclk(struct drm_i915_private *dev_priv,
2123                             const struct intel_cdclk_state *cdclk_state,
2124                             enum pipe pipe)
2125 {
2126         if (!intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_state))
2127                 return;
2128
2129         if (WARN_ON_ONCE(!dev_priv->display.set_cdclk))
2130                 return;
2131
2132         intel_dump_cdclk_state(cdclk_state, "Changing CDCLK to");
2133
2134         dev_priv->display.set_cdclk(dev_priv, cdclk_state, pipe);
2135
2136         if (WARN(intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_state),
2137                  "cdclk state doesn't match!\n")) {
2138                 intel_dump_cdclk_state(&dev_priv->cdclk.hw, "[hw state]");
2139                 intel_dump_cdclk_state(cdclk_state, "[sw state]");
2140         }
2141 }
2142
2143 /**
2144  * intel_set_cdclk_pre_plane_update - Push the CDCLK state to the hardware
2145  * @dev_priv: i915 device
2146  * @old_state: old CDCLK state
2147  * @new_state: new CDCLK state
2148  * @pipe: pipe with which to synchronize the update
2149  *
2150  * Program the hardware before updating the HW plane state based on the passed
2151  * in CDCLK state, if necessary.
2152  */
2153 void
2154 intel_set_cdclk_pre_plane_update(struct drm_i915_private *dev_priv,
2155                                  const struct intel_cdclk_state *old_state,
2156                                  const struct intel_cdclk_state *new_state,
2157                                  enum pipe pipe)
2158 {
2159         if (pipe == INVALID_PIPE || old_state->cdclk <= new_state->cdclk)
2160                 intel_set_cdclk(dev_priv, new_state, pipe);
2161 }
2162
2163 /**
2164  * intel_set_cdclk_post_plane_update - Push the CDCLK state to the hardware
2165  * @dev_priv: i915 device
2166  * @old_state: old CDCLK state
2167  * @new_state: new CDCLK state
2168  * @pipe: pipe with which to synchronize the update
2169  *
2170  * Program the hardware after updating the HW plane state based on the passed
2171  * in CDCLK state, if necessary.
2172  */
2173 void
2174 intel_set_cdclk_post_plane_update(struct drm_i915_private *dev_priv,
2175                                   const struct intel_cdclk_state *old_state,
2176                                   const struct intel_cdclk_state *new_state,
2177                                   enum pipe pipe)
2178 {
2179         if (pipe != INVALID_PIPE && old_state->cdclk > new_state->cdclk)
2180                 intel_set_cdclk(dev_priv, new_state, pipe);
2181 }
2182
2183 static int intel_pixel_rate_to_cdclk(struct drm_i915_private *dev_priv,
2184                                      int pixel_rate)
2185 {
2186         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
2187                 return DIV_ROUND_UP(pixel_rate, 2);
2188         else if (IS_GEN(dev_priv, 9) ||
2189                  IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
2190                 return pixel_rate;
2191         else if (IS_CHERRYVIEW(dev_priv))
2192                 return DIV_ROUND_UP(pixel_rate * 100, 95);
2193         else
2194                 return DIV_ROUND_UP(pixel_rate * 100, 90);
2195 }
2196
2197 int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
2198 {
2199         struct drm_i915_private *dev_priv =
2200                 to_i915(crtc_state->base.crtc->dev);
2201         int min_cdclk;
2202
2203         if (!crtc_state->base.enable)
2204                 return 0;
2205
2206         min_cdclk = intel_pixel_rate_to_cdclk(dev_priv, crtc_state->pixel_rate);
2207
2208         /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
2209         if (IS_BROADWELL(dev_priv) && hsw_crtc_state_ips_capable(crtc_state))
2210                 min_cdclk = DIV_ROUND_UP(min_cdclk * 100, 95);
2211
2212         /* BSpec says "Do not use DisplayPort with CDCLK less than 432 MHz,
2213          * audio enabled, port width x4, and link rate HBR2 (5.4 GHz), or else
2214          * there may be audio corruption or screen corruption." This cdclk
2215          * restriction for GLK is 316.8 MHz.
2216          */
2217         if (intel_crtc_has_dp_encoder(crtc_state) &&
2218             crtc_state->has_audio &&
2219             crtc_state->port_clock >= 540000 &&
2220             crtc_state->lane_count == 4) {
2221                 if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) {
2222                         /* Display WA #1145: glk,cnl */
2223                         min_cdclk = max(316800, min_cdclk);
2224                 } else if (IS_GEN(dev_priv, 9) || IS_BROADWELL(dev_priv)) {
2225                         /* Display WA #1144: skl,bxt */
2226                         min_cdclk = max(432000, min_cdclk);
2227                 }
2228         }
2229
2230         /*
2231          * According to BSpec, "The CD clock frequency must be at least twice
2232          * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default.
2233          */
2234         if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9)
2235                 min_cdclk = max(2 * 96000, min_cdclk);
2236
2237         /*
2238          * "For DP audio configuration, cdclk frequency shall be set to
2239          *  meet the following requirements:
2240          *  DP Link Frequency(MHz) | Cdclk frequency(MHz)
2241          *  270                    | 320 or higher
2242          *  162                    | 200 or higher"
2243          */
2244         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
2245             intel_crtc_has_dp_encoder(crtc_state) && crtc_state->has_audio)
2246                 min_cdclk = max(crtc_state->port_clock, min_cdclk);
2247
2248         /*
2249          * On Valleyview some DSI panels lose (v|h)sync when the clock is lower
2250          * than 320000KHz.
2251          */
2252         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) &&
2253             IS_VALLEYVIEW(dev_priv))
2254                 min_cdclk = max(320000, min_cdclk);
2255
2256         /*
2257          * On Geminilake once the CDCLK gets as low as 79200
2258          * picture gets unstable, despite that values are
2259          * correct for DSI PLL and DE PLL.
2260          */
2261         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) &&
2262             IS_GEMINILAKE(dev_priv))
2263                 min_cdclk = max(158400, min_cdclk);
2264
2265         if (min_cdclk > dev_priv->max_cdclk_freq) {
2266                 DRM_DEBUG_KMS("required cdclk (%d kHz) exceeds max (%d kHz)\n",
2267                               min_cdclk, dev_priv->max_cdclk_freq);
2268                 return -EINVAL;
2269         }
2270
2271         return min_cdclk;
2272 }
2273
2274 static int intel_compute_min_cdclk(struct intel_atomic_state *state)
2275 {
2276         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2277         struct intel_crtc *crtc;
2278         struct intel_crtc_state *crtc_state;
2279         int min_cdclk, i;
2280         enum pipe pipe;
2281
2282         memcpy(state->min_cdclk, dev_priv->min_cdclk,
2283                sizeof(state->min_cdclk));
2284
2285         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
2286                 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
2287                 if (min_cdclk < 0)
2288                         return min_cdclk;
2289
2290                 state->min_cdclk[i] = min_cdclk;
2291         }
2292
2293         min_cdclk = state->cdclk.force_min_cdclk;
2294         for_each_pipe(dev_priv, pipe)
2295                 min_cdclk = max(state->min_cdclk[pipe], min_cdclk);
2296
2297         return min_cdclk;
2298 }
2299
2300 /*
2301  * Note that this functions assumes that 0 is
2302  * the lowest voltage value, and higher values
2303  * correspond to increasingly higher voltages.
2304  *
2305  * Should that relationship no longer hold on
2306  * future platforms this code will need to be
2307  * adjusted.
2308  */
2309 static u8 cnl_compute_min_voltage_level(struct intel_atomic_state *state)
2310 {
2311         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2312         struct intel_crtc *crtc;
2313         struct intel_crtc_state *crtc_state;
2314         u8 min_voltage_level;
2315         int i;
2316         enum pipe pipe;
2317
2318         memcpy(state->min_voltage_level, dev_priv->min_voltage_level,
2319                sizeof(state->min_voltage_level));
2320
2321         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
2322                 if (crtc_state->base.enable)
2323                         state->min_voltage_level[i] =
2324                                 crtc_state->min_voltage_level;
2325                 else
2326                         state->min_voltage_level[i] = 0;
2327         }
2328
2329         min_voltage_level = 0;
2330         for_each_pipe(dev_priv, pipe)
2331                 min_voltage_level = max(state->min_voltage_level[pipe],
2332                                         min_voltage_level);
2333
2334         return min_voltage_level;
2335 }
2336
2337 static int vlv_modeset_calc_cdclk(struct intel_atomic_state *state)
2338 {
2339         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2340         int min_cdclk, cdclk;
2341
2342         min_cdclk = intel_compute_min_cdclk(state);
2343         if (min_cdclk < 0)
2344                 return min_cdclk;
2345
2346         cdclk = vlv_calc_cdclk(dev_priv, min_cdclk);
2347
2348         state->cdclk.logical.cdclk = cdclk;
2349         state->cdclk.logical.voltage_level =
2350                 vlv_calc_voltage_level(dev_priv, cdclk);
2351
2352         if (!state->active_pipes) {
2353                 cdclk = vlv_calc_cdclk(dev_priv, state->cdclk.force_min_cdclk);
2354
2355                 state->cdclk.actual.cdclk = cdclk;
2356                 state->cdclk.actual.voltage_level =
2357                         vlv_calc_voltage_level(dev_priv, cdclk);
2358         } else {
2359                 state->cdclk.actual = state->cdclk.logical;
2360         }
2361
2362         return 0;
2363 }
2364
2365 static int bdw_modeset_calc_cdclk(struct intel_atomic_state *state)
2366 {
2367         int min_cdclk, cdclk;
2368
2369         min_cdclk = intel_compute_min_cdclk(state);
2370         if (min_cdclk < 0)
2371                 return min_cdclk;
2372
2373         /*
2374          * FIXME should also account for plane ratio
2375          * once 64bpp pixel formats are supported.
2376          */
2377         cdclk = bdw_calc_cdclk(min_cdclk);
2378
2379         state->cdclk.logical.cdclk = cdclk;
2380         state->cdclk.logical.voltage_level =
2381                 bdw_calc_voltage_level(cdclk);
2382
2383         if (!state->active_pipes) {
2384                 cdclk = bdw_calc_cdclk(state->cdclk.force_min_cdclk);
2385
2386                 state->cdclk.actual.cdclk = cdclk;
2387                 state->cdclk.actual.voltage_level =
2388                         bdw_calc_voltage_level(cdclk);
2389         } else {
2390                 state->cdclk.actual = state->cdclk.logical;
2391         }
2392
2393         return 0;
2394 }
2395
2396 static int skl_dpll0_vco(struct intel_atomic_state *state)
2397 {
2398         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2399         struct intel_crtc *crtc;
2400         struct intel_crtc_state *crtc_state;
2401         int vco, i;
2402
2403         vco = state->cdclk.logical.vco;
2404         if (!vco)
2405                 vco = dev_priv->skl_preferred_vco_freq;
2406
2407         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
2408                 if (!crtc_state->base.enable)
2409                         continue;
2410
2411                 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
2412                         continue;
2413
2414                 /*
2415                  * DPLL0 VCO may need to be adjusted to get the correct
2416                  * clock for eDP. This will affect cdclk as well.
2417                  */
2418                 switch (crtc_state->port_clock / 2) {
2419                 case 108000:
2420                 case 216000:
2421                         vco = 8640000;
2422                         break;
2423                 default:
2424                         vco = 8100000;
2425                         break;
2426                 }
2427         }
2428
2429         return vco;
2430 }
2431
2432 static int skl_modeset_calc_cdclk(struct intel_atomic_state *state)
2433 {
2434         int min_cdclk, cdclk, vco;
2435
2436         min_cdclk = intel_compute_min_cdclk(state);
2437         if (min_cdclk < 0)
2438                 return min_cdclk;
2439
2440         vco = skl_dpll0_vco(state);
2441
2442         /*
2443          * FIXME should also account for plane ratio
2444          * once 64bpp pixel formats are supported.
2445          */
2446         cdclk = skl_calc_cdclk(min_cdclk, vco);
2447
2448         state->cdclk.logical.vco = vco;
2449         state->cdclk.logical.cdclk = cdclk;
2450         state->cdclk.logical.voltage_level =
2451                 skl_calc_voltage_level(cdclk);
2452
2453         if (!state->active_pipes) {
2454                 cdclk = skl_calc_cdclk(state->cdclk.force_min_cdclk, vco);
2455
2456                 state->cdclk.actual.vco = vco;
2457                 state->cdclk.actual.cdclk = cdclk;
2458                 state->cdclk.actual.voltage_level =
2459                         skl_calc_voltage_level(cdclk);
2460         } else {
2461                 state->cdclk.actual = state->cdclk.logical;
2462         }
2463
2464         return 0;
2465 }
2466
2467 static int bxt_modeset_calc_cdclk(struct intel_atomic_state *state)
2468 {
2469         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2470         int min_cdclk, cdclk, vco;
2471
2472         min_cdclk = intel_compute_min_cdclk(state);
2473         if (min_cdclk < 0)
2474                 return min_cdclk;
2475
2476         if (IS_GEMINILAKE(dev_priv)) {
2477                 cdclk = glk_calc_cdclk(min_cdclk);
2478                 vco = glk_de_pll_vco(dev_priv, cdclk);
2479         } else {
2480                 cdclk = bxt_calc_cdclk(min_cdclk);
2481                 vco = bxt_de_pll_vco(dev_priv, cdclk);
2482         }
2483
2484         state->cdclk.logical.vco = vco;
2485         state->cdclk.logical.cdclk = cdclk;
2486         state->cdclk.logical.voltage_level =
2487                 bxt_calc_voltage_level(cdclk);
2488
2489         if (!state->active_pipes) {
2490                 if (IS_GEMINILAKE(dev_priv)) {
2491                         cdclk = glk_calc_cdclk(state->cdclk.force_min_cdclk);
2492                         vco = glk_de_pll_vco(dev_priv, cdclk);
2493                 } else {
2494                         cdclk = bxt_calc_cdclk(state->cdclk.force_min_cdclk);
2495                         vco = bxt_de_pll_vco(dev_priv, cdclk);
2496                 }
2497
2498                 state->cdclk.actual.vco = vco;
2499                 state->cdclk.actual.cdclk = cdclk;
2500                 state->cdclk.actual.voltage_level =
2501                         bxt_calc_voltage_level(cdclk);
2502         } else {
2503                 state->cdclk.actual = state->cdclk.logical;
2504         }
2505
2506         return 0;
2507 }
2508
2509 static int cnl_modeset_calc_cdclk(struct intel_atomic_state *state)
2510 {
2511         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2512         int min_cdclk, cdclk, vco;
2513
2514         min_cdclk = intel_compute_min_cdclk(state);
2515         if (min_cdclk < 0)
2516                 return min_cdclk;
2517
2518         cdclk = cnl_calc_cdclk(min_cdclk);
2519         vco = cnl_cdclk_pll_vco(dev_priv, cdclk);
2520
2521         state->cdclk.logical.vco = vco;
2522         state->cdclk.logical.cdclk = cdclk;
2523         state->cdclk.logical.voltage_level =
2524                 max(cnl_calc_voltage_level(cdclk),
2525                     cnl_compute_min_voltage_level(state));
2526
2527         if (!state->active_pipes) {
2528                 cdclk = cnl_calc_cdclk(state->cdclk.force_min_cdclk);
2529                 vco = cnl_cdclk_pll_vco(dev_priv, cdclk);
2530
2531                 state->cdclk.actual.vco = vco;
2532                 state->cdclk.actual.cdclk = cdclk;
2533                 state->cdclk.actual.voltage_level =
2534                         cnl_calc_voltage_level(cdclk);
2535         } else {
2536                 state->cdclk.actual = state->cdclk.logical;
2537         }
2538
2539         return 0;
2540 }
2541
2542 static int icl_modeset_calc_cdclk(struct intel_atomic_state *state)
2543 {
2544         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2545         unsigned int ref = state->cdclk.logical.ref;
2546         int min_cdclk, cdclk, vco;
2547
2548         min_cdclk = intel_compute_min_cdclk(state);
2549         if (min_cdclk < 0)
2550                 return min_cdclk;
2551
2552         cdclk = icl_calc_cdclk(min_cdclk, ref);
2553         vco = icl_calc_cdclk_pll_vco(dev_priv, cdclk);
2554
2555         state->cdclk.logical.vco = vco;
2556         state->cdclk.logical.cdclk = cdclk;
2557         state->cdclk.logical.voltage_level =
2558                 max(icl_calc_voltage_level(dev_priv, cdclk),
2559                     cnl_compute_min_voltage_level(state));
2560
2561         if (!state->active_pipes) {
2562                 cdclk = icl_calc_cdclk(state->cdclk.force_min_cdclk, ref);
2563                 vco = icl_calc_cdclk_pll_vco(dev_priv, cdclk);
2564
2565                 state->cdclk.actual.vco = vco;
2566                 state->cdclk.actual.cdclk = cdclk;
2567                 state->cdclk.actual.voltage_level =
2568                         icl_calc_voltage_level(dev_priv, cdclk);
2569         } else {
2570                 state->cdclk.actual = state->cdclk.logical;
2571         }
2572
2573         return 0;
2574 }
2575
2576 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
2577 {
2578         int max_cdclk_freq = dev_priv->max_cdclk_freq;
2579
2580         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
2581                 return 2 * max_cdclk_freq;
2582         else if (IS_GEN(dev_priv, 9) ||
2583                  IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
2584                 return max_cdclk_freq;
2585         else if (IS_CHERRYVIEW(dev_priv))
2586                 return max_cdclk_freq*95/100;
2587         else if (INTEL_GEN(dev_priv) < 4)
2588                 return 2*max_cdclk_freq*90/100;
2589         else
2590                 return max_cdclk_freq*90/100;
2591 }
2592
2593 /**
2594  * intel_update_max_cdclk - Determine the maximum support CDCLK frequency
2595  * @dev_priv: i915 device
2596  *
2597  * Determine the maximum CDCLK frequency the platform supports, and also
2598  * derive the maximum dot clock frequency the maximum CDCLK frequency
2599  * allows.
2600  */
2601 void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
2602 {
2603         if (IS_ELKHARTLAKE(dev_priv)) {
2604                 if (dev_priv->cdclk.hw.ref == 24000)
2605                         dev_priv->max_cdclk_freq = 552000;
2606                 else
2607                         dev_priv->max_cdclk_freq = 556800;
2608         } else if (INTEL_GEN(dev_priv) >= 11) {
2609                 if (dev_priv->cdclk.hw.ref == 24000)
2610                         dev_priv->max_cdclk_freq = 648000;
2611                 else
2612                         dev_priv->max_cdclk_freq = 652800;
2613         } else if (IS_CANNONLAKE(dev_priv)) {
2614                 dev_priv->max_cdclk_freq = 528000;
2615         } else if (IS_GEN9_BC(dev_priv)) {
2616                 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
2617                 int max_cdclk, vco;
2618
2619                 vco = dev_priv->skl_preferred_vco_freq;
2620                 WARN_ON(vco != 8100000 && vco != 8640000);
2621
2622                 /*
2623                  * Use the lower (vco 8640) cdclk values as a
2624                  * first guess. skl_calc_cdclk() will correct it
2625                  * if the preferred vco is 8100 instead.
2626                  */
2627                 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
2628                         max_cdclk = 617143;
2629                 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
2630                         max_cdclk = 540000;
2631                 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
2632                         max_cdclk = 432000;
2633                 else
2634                         max_cdclk = 308571;
2635
2636                 dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
2637         } else if (IS_GEMINILAKE(dev_priv)) {
2638                 dev_priv->max_cdclk_freq = 316800;
2639         } else if (IS_BROXTON(dev_priv)) {
2640                 dev_priv->max_cdclk_freq = 624000;
2641         } else if (IS_BROADWELL(dev_priv))  {
2642                 /*
2643                  * FIXME with extra cooling we can allow
2644                  * 540 MHz for ULX and 675 Mhz for ULT.
2645                  * How can we know if extra cooling is
2646                  * available? PCI ID, VTB, something else?
2647                  */
2648                 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
2649                         dev_priv->max_cdclk_freq = 450000;
2650                 else if (IS_BDW_ULX(dev_priv))
2651                         dev_priv->max_cdclk_freq = 450000;
2652                 else if (IS_BDW_ULT(dev_priv))
2653                         dev_priv->max_cdclk_freq = 540000;
2654                 else
2655                         dev_priv->max_cdclk_freq = 675000;
2656         } else if (IS_CHERRYVIEW(dev_priv)) {
2657                 dev_priv->max_cdclk_freq = 320000;
2658         } else if (IS_VALLEYVIEW(dev_priv)) {
2659                 dev_priv->max_cdclk_freq = 400000;
2660         } else {
2661                 /* otherwise assume cdclk is fixed */
2662                 dev_priv->max_cdclk_freq = dev_priv->cdclk.hw.cdclk;
2663         }
2664
2665         dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
2666
2667         DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
2668                          dev_priv->max_cdclk_freq);
2669
2670         DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
2671                          dev_priv->max_dotclk_freq);
2672 }
2673
2674 /**
2675  * intel_update_cdclk - Determine the current CDCLK frequency
2676  * @dev_priv: i915 device
2677  *
2678  * Determine the current CDCLK frequency.
2679  */
2680 void intel_update_cdclk(struct drm_i915_private *dev_priv)
2681 {
2682         dev_priv->display.get_cdclk(dev_priv, &dev_priv->cdclk.hw);
2683
2684         /*
2685          * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
2686          * Programmng [sic] note: bit[9:2] should be programmed to the number
2687          * of cdclk that generates 4MHz reference clock freq which is used to
2688          * generate GMBus clock. This will vary with the cdclk freq.
2689          */
2690         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2691                 I915_WRITE(GMBUSFREQ_VLV,
2692                            DIV_ROUND_UP(dev_priv->cdclk.hw.cdclk, 1000));
2693 }
2694
2695 static int cnp_rawclk(struct drm_i915_private *dev_priv)
2696 {
2697         u32 rawclk;
2698         int divider, fraction;
2699
2700         if (I915_READ(SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) {
2701                 /* 24 MHz */
2702                 divider = 24000;
2703                 fraction = 0;
2704         } else {
2705                 /* 19.2 MHz */
2706                 divider = 19000;
2707                 fraction = 200;
2708         }
2709
2710         rawclk = CNP_RAWCLK_DIV(divider / 1000);
2711         if (fraction) {
2712                 int numerator = 1;
2713
2714                 rawclk |= CNP_RAWCLK_DEN(DIV_ROUND_CLOSEST(numerator * 1000,
2715                                                            fraction) - 1);
2716                 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
2717                         rawclk |= ICP_RAWCLK_NUM(numerator);
2718         }
2719
2720         I915_WRITE(PCH_RAWCLK_FREQ, rawclk);
2721         return divider + fraction;
2722 }
2723
2724 static int pch_rawclk(struct drm_i915_private *dev_priv)
2725 {
2726         return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
2727 }
2728
2729 static int vlv_hrawclk(struct drm_i915_private *dev_priv)
2730 {
2731         /* RAWCLK_FREQ_VLV register updated from power well code */
2732         return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
2733                                       CCK_DISPLAY_REF_CLOCK_CONTROL);
2734 }
2735
2736 static int g4x_hrawclk(struct drm_i915_private *dev_priv)
2737 {
2738         u32 clkcfg;
2739
2740         /* hrawclock is 1/4 the FSB frequency */
2741         clkcfg = I915_READ(CLKCFG);
2742         switch (clkcfg & CLKCFG_FSB_MASK) {
2743         case CLKCFG_FSB_400:
2744                 return 100000;
2745         case CLKCFG_FSB_533:
2746                 return 133333;
2747         case CLKCFG_FSB_667:
2748                 return 166667;
2749         case CLKCFG_FSB_800:
2750                 return 200000;
2751         case CLKCFG_FSB_1067:
2752         case CLKCFG_FSB_1067_ALT:
2753                 return 266667;
2754         case CLKCFG_FSB_1333:
2755         case CLKCFG_FSB_1333_ALT:
2756                 return 333333;
2757         default:
2758                 return 133333;
2759         }
2760 }
2761
2762 /**
2763  * intel_update_rawclk - Determine the current RAWCLK frequency
2764  * @dev_priv: i915 device
2765  *
2766  * Determine the current RAWCLK frequency. RAWCLK is a fixed
2767  * frequency clock so this needs to done only once.
2768  */
2769 void intel_update_rawclk(struct drm_i915_private *dev_priv)
2770 {
2771         if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
2772                 dev_priv->rawclk_freq = cnp_rawclk(dev_priv);
2773         else if (HAS_PCH_SPLIT(dev_priv))
2774                 dev_priv->rawclk_freq = pch_rawclk(dev_priv);
2775         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2776                 dev_priv->rawclk_freq = vlv_hrawclk(dev_priv);
2777         else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv))
2778                 dev_priv->rawclk_freq = g4x_hrawclk(dev_priv);
2779         else
2780                 /* no rawclk on other platforms, or no need to know it */
2781                 return;
2782
2783         DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq);
2784 }
2785
2786 /**
2787  * intel_init_cdclk_hooks - Initialize CDCLK related modesetting hooks
2788  * @dev_priv: i915 device
2789  */
2790 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
2791 {
2792         if (INTEL_GEN(dev_priv) >= 11) {
2793                 dev_priv->display.set_cdclk = cnl_set_cdclk;
2794                 dev_priv->display.modeset_calc_cdclk = icl_modeset_calc_cdclk;
2795         } else if (IS_CANNONLAKE(dev_priv)) {
2796                 dev_priv->display.set_cdclk = cnl_set_cdclk;
2797                 dev_priv->display.modeset_calc_cdclk = cnl_modeset_calc_cdclk;
2798         } else if (IS_GEN9_LP(dev_priv)) {
2799                 dev_priv->display.set_cdclk = bxt_set_cdclk;
2800                 dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
2801         } else if (IS_GEN9_BC(dev_priv)) {
2802                 dev_priv->display.set_cdclk = skl_set_cdclk;
2803                 dev_priv->display.modeset_calc_cdclk = skl_modeset_calc_cdclk;
2804         } else if (IS_BROADWELL(dev_priv)) {
2805                 dev_priv->display.set_cdclk = bdw_set_cdclk;
2806                 dev_priv->display.modeset_calc_cdclk = bdw_modeset_calc_cdclk;
2807         } else if (IS_CHERRYVIEW(dev_priv)) {
2808                 dev_priv->display.set_cdclk = chv_set_cdclk;
2809                 dev_priv->display.modeset_calc_cdclk = vlv_modeset_calc_cdclk;
2810         } else if (IS_VALLEYVIEW(dev_priv)) {
2811                 dev_priv->display.set_cdclk = vlv_set_cdclk;
2812                 dev_priv->display.modeset_calc_cdclk = vlv_modeset_calc_cdclk;
2813         }
2814
2815         if (INTEL_GEN(dev_priv) >= 11)
2816                 dev_priv->display.get_cdclk = icl_get_cdclk;
2817         else if (IS_CANNONLAKE(dev_priv))
2818                 dev_priv->display.get_cdclk = cnl_get_cdclk;
2819         else if (IS_GEN9_LP(dev_priv))
2820                 dev_priv->display.get_cdclk = bxt_get_cdclk;
2821         else if (IS_GEN9_BC(dev_priv))
2822                 dev_priv->display.get_cdclk = skl_get_cdclk;
2823         else if (IS_BROADWELL(dev_priv))
2824                 dev_priv->display.get_cdclk = bdw_get_cdclk;
2825         else if (IS_HASWELL(dev_priv))
2826                 dev_priv->display.get_cdclk = hsw_get_cdclk;
2827         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2828                 dev_priv->display.get_cdclk = vlv_get_cdclk;
2829         else if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
2830                 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
2831         else if (IS_GEN(dev_priv, 5))
2832                 dev_priv->display.get_cdclk = fixed_450mhz_get_cdclk;
2833         else if (IS_GM45(dev_priv))
2834                 dev_priv->display.get_cdclk = gm45_get_cdclk;
2835         else if (IS_G45(dev_priv))
2836                 dev_priv->display.get_cdclk = g33_get_cdclk;
2837         else if (IS_I965GM(dev_priv))
2838                 dev_priv->display.get_cdclk = i965gm_get_cdclk;
2839         else if (IS_I965G(dev_priv))
2840                 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
2841         else if (IS_PINEVIEW(dev_priv))
2842                 dev_priv->display.get_cdclk = pnv_get_cdclk;
2843         else if (IS_G33(dev_priv))
2844                 dev_priv->display.get_cdclk = g33_get_cdclk;
2845         else if (IS_I945GM(dev_priv))
2846                 dev_priv->display.get_cdclk = i945gm_get_cdclk;
2847         else if (IS_I945G(dev_priv))
2848                 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
2849         else if (IS_I915GM(dev_priv))
2850                 dev_priv->display.get_cdclk = i915gm_get_cdclk;
2851         else if (IS_I915G(dev_priv))
2852                 dev_priv->display.get_cdclk = fixed_333mhz_get_cdclk;
2853         else if (IS_I865G(dev_priv))
2854                 dev_priv->display.get_cdclk = fixed_266mhz_get_cdclk;
2855         else if (IS_I85X(dev_priv))
2856                 dev_priv->display.get_cdclk = i85x_get_cdclk;
2857         else if (IS_I845G(dev_priv))
2858                 dev_priv->display.get_cdclk = fixed_200mhz_get_cdclk;
2859         else { /* 830 */
2860                 WARN(!IS_I830(dev_priv),
2861                      "Unknown platform. Assuming 133 MHz CDCLK\n");
2862                 dev_priv->display.get_cdclk = fixed_133mhz_get_cdclk;
2863         }
2864 }