2 * Copyright © 2006-2019 Intel Corporation
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5 * copy of this software and associated documentation files (the "Software"),
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #ifndef _INTEL_DISPLAY_H_
26 #define _INTEL_DISPLAY_H_
28 #include <drm/drm_util.h>
29 #include <drm/i915_drm.h>
35 struct drm_display_mode;
38 struct drm_format_info;
39 struct drm_framebuffer;
40 struct drm_i915_error_state_buf;
41 struct drm_i915_gem_object;
42 struct drm_i915_private;
43 struct drm_modeset_acquire_ctx;
45 struct drm_plane_state;
46 struct i915_ggtt_view;
47 struct intel_atomic_state;
49 struct intel_crtc_state;
50 struct intel_digital_port;
53 struct intel_load_detect_pipe;
55 struct intel_plane_state;
56 struct intel_remapped_info;
57 struct intel_rotation_info;
58 struct intel_crtc_state;
79 * Keep the pipe enum values fixed: the code assumes that PIPE_A=0, the
80 * rest have consecutive values and match the enum values of transcoders
81 * with a 1:1 transcoder -> pipe mapping.
92 I915_MAX_PIPES = _PIPE_EDP
95 #define pipe_name(p) ((p) + 'A')
98 INVALID_TRANSCODER = -1,
100 * The following transcoders have a 1:1 transcoder -> pipe mapping,
101 * keep their values fixed: the code assumes that TRANSCODER_A=0, the
102 * rest have consecutive values and match the enum values of the pipes
105 TRANSCODER_A = PIPE_A,
106 TRANSCODER_B = PIPE_B,
107 TRANSCODER_C = PIPE_C,
108 TRANSCODER_D = PIPE_D,
111 * The following transcoders can map to any pipe, their enum value
112 * doesn't need to stay fixed.
117 TRANSCODER_DSI_A = TRANSCODER_DSI_0, /* legacy DSI */
118 TRANSCODER_DSI_C = TRANSCODER_DSI_1, /* legacy DSI */
123 static inline const char *transcoder_name(enum transcoder transcoder)
125 switch (transcoder) {
136 case TRANSCODER_DSI_A:
138 case TRANSCODER_DSI_C:
145 static inline bool transcoder_is_dsi(enum transcoder transcoder)
147 return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C;
151 * Global legacy plane identifier. Valid only for primary/sprite
152 * planes on pre-g4x, and only for primary planes on g4x-bdw.
160 #define plane_name(p) ((p) + 'A')
161 #define sprite_name(p, s) ((p) * RUNTIME_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
164 * Per-pipe plane identifier.
165 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
166 * number of planes per CRTC. Not all platforms really have this many planes,
167 * which means some arrays of size I915_MAX_PLANES may have unused entries
168 * between the topmost sprite plane and the cursor plane.
170 * This is expected to be passed to various register macros
171 * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care.
186 #define for_each_plane_id_on_crtc(__crtc, __p) \
187 for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \
188 for_each_if((__crtc)->plane_ids_mask & BIT(__p))
206 #define port_name(p) ((p) + 'A')
209 * Ports identifier referenced from other drivers.
210 * Expected to remain stable over time
212 static inline const char *port_identifier(enum port port)
268 #define I915_NUM_PHYS_VLV 2
280 #define aux_ch_name(a) ((a) + 'A')
282 /* Used by dp and fdi links */
283 struct intel_link_m_n {
307 #define phy_name(a) ((a) + 'A')
315 #define for_each_pipe(__dev_priv, __p) \
316 for ((__p) = 0; (__p) < INTEL_NUM_PIPES(__dev_priv); (__p)++)
318 #define for_each_pipe_masked(__dev_priv, __p, __mask) \
319 for ((__p) = 0; (__p) < INTEL_NUM_PIPES(__dev_priv); (__p)++) \
320 for_each_if((__mask) & BIT(__p))
322 #define for_each_cpu_transcoder_masked(__dev_priv, __t, __mask) \
323 for ((__t) = 0; (__t) < I915_MAX_TRANSCODERS; (__t)++) \
324 for_each_if ((__mask) & (1 << (__t)))
326 #define for_each_universal_plane(__dev_priv, __pipe, __p) \
328 (__p) < RUNTIME_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
331 #define for_each_sprite(__dev_priv, __p, __s) \
333 (__s) < RUNTIME_INFO(__dev_priv)->num_sprites[(__p)]; \
336 #define for_each_port(__port) \
337 for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++)
339 #define for_each_port_masked(__port, __ports_mask) \
340 for_each_port(__port) \
341 for_each_if((__ports_mask) & BIT(__port))
343 #define for_each_phy_masked(__phy, __phys_mask) \
344 for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++) \
345 for_each_if((__phys_mask) & BIT(__phy))
347 #define for_each_crtc(dev, crtc) \
348 list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
350 #define for_each_intel_plane(dev, intel_plane) \
351 list_for_each_entry(intel_plane, \
352 &(dev)->mode_config.plane_list, \
355 #define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \
356 list_for_each_entry(intel_plane, \
357 &(dev)->mode_config.plane_list, \
359 for_each_if((plane_mask) & \
360 drm_plane_mask(&intel_plane->base))
362 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
363 list_for_each_entry(intel_plane, \
364 &(dev)->mode_config.plane_list, \
366 for_each_if((intel_plane)->pipe == (intel_crtc)->pipe)
368 #define for_each_intel_crtc(dev, intel_crtc) \
369 list_for_each_entry(intel_crtc, \
370 &(dev)->mode_config.crtc_list, \
373 #define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask) \
374 list_for_each_entry(intel_crtc, \
375 &(dev)->mode_config.crtc_list, \
377 for_each_if((crtc_mask) & drm_crtc_mask(&intel_crtc->base))
379 #define for_each_intel_encoder(dev, intel_encoder) \
380 list_for_each_entry(intel_encoder, \
381 &(dev)->mode_config.encoder_list, \
384 #define for_each_intel_encoder_mask(dev, intel_encoder, encoder_mask) \
385 list_for_each_entry(intel_encoder, \
386 &(dev)->mode_config.encoder_list, \
388 for_each_if((encoder_mask) & \
389 drm_encoder_mask(&intel_encoder->base))
391 #define for_each_intel_dp(dev, intel_encoder) \
392 for_each_intel_encoder(dev, intel_encoder) \
393 for_each_if(intel_encoder_is_dp(intel_encoder))
395 #define for_each_intel_connector_iter(intel_connector, iter) \
396 while ((intel_connector = to_intel_connector(drm_connector_list_iter_next(iter))))
398 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
399 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
400 for_each_if((intel_encoder)->base.crtc == (__crtc))
402 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
403 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
404 for_each_if((intel_connector)->base.encoder == (__encoder))
406 #define for_each_old_intel_plane_in_state(__state, plane, old_plane_state, __i) \
408 (__i) < (__state)->base.dev->mode_config.num_total_plane && \
409 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
410 (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), 1); \
414 #define for_each_new_intel_plane_in_state(__state, plane, new_plane_state, __i) \
416 (__i) < (__state)->base.dev->mode_config.num_total_plane && \
417 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
418 (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
422 #define for_each_new_intel_crtc_in_state(__state, crtc, new_crtc_state, __i) \
424 (__i) < (__state)->base.dev->mode_config.num_crtc && \
425 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
426 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
430 #define for_each_oldnew_intel_plane_in_state(__state, plane, old_plane_state, new_plane_state, __i) \
432 (__i) < (__state)->base.dev->mode_config.num_total_plane && \
433 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
434 (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), \
435 (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
439 #define for_each_oldnew_intel_crtc_in_state(__state, crtc, old_crtc_state, new_crtc_state, __i) \
441 (__i) < (__state)->base.dev->mode_config.num_crtc && \
442 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
443 (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
444 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
448 #define for_each_oldnew_intel_crtc_in_state_reverse(__state, crtc, old_crtc_state, new_crtc_state, __i) \
449 for ((__i) = (__state)->base.dev->mode_config.num_crtc - 1; \
451 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
452 (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
453 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
457 #define intel_atomic_crtc_state_for_each_plane_state( \
458 plane, plane_state, \
460 for_each_intel_plane_mask(((crtc_state)->uapi.state->dev), (plane), \
461 ((crtc_state)->uapi.plane_mask)) \
462 for_each_if ((plane_state = \
463 to_intel_plane_state(__drm_atomic_get_current_plane_state((crtc_state)->uapi.state, &plane->base))))
465 #define for_each_new_intel_connector_in_state(__state, connector, new_connector_state, __i) \
467 (__i) < (__state)->base.num_connector; \
469 for_each_if ((__state)->base.connectors[__i].ptr && \
470 ((connector) = to_intel_connector((__state)->base.connectors[__i].ptr), \
471 (new_connector_state) = to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1))
473 u8 intel_calc_active_pipes(struct intel_atomic_state *state,
475 void intel_link_compute_m_n(u16 bpp, int nlanes,
476 int pixel_clock, int link_clock,
477 struct intel_link_m_n *m_n,
478 bool constant_n, bool fec_enable);
479 bool is_ccs_modifier(u64 modifier);
480 int intel_main_to_aux_plane(const struct drm_framebuffer *fb, int main_plane);
481 void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv);
482 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
483 u32 pixel_format, u64 modifier);
484 bool intel_plane_can_remap(const struct intel_plane_state *plane_state);
486 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
487 const struct drm_display_mode *mode);
488 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port);
489 bool is_trans_port_sync_mode(const struct intel_crtc_state *state);
491 void intel_plane_destroy(struct drm_plane *plane);
492 void intel_enable_pipe(const struct intel_crtc_state *new_crtc_state);
493 void intel_disable_pipe(const struct intel_crtc_state *old_crtc_state);
494 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
495 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
496 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc);
497 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv);
498 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
499 const char *name, u32 reg, int ref_freq);
500 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
501 const char *name, u32 reg);
502 void lpt_pch_enable(const struct intel_crtc_state *crtc_state);
503 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv);
504 void lpt_disable_iclkip(struct drm_i915_private *dev_priv);
505 void intel_init_display_hooks(struct drm_i915_private *dev_priv);
506 unsigned int intel_fb_xy_to_linear(int x, int y,
507 const struct intel_plane_state *state,
509 unsigned int intel_fb_align_height(const struct drm_framebuffer *fb,
510 int color_plane, unsigned int height);
511 void intel_add_fb_offsets(int *x, int *y,
512 const struct intel_plane_state *state, int plane);
513 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
514 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info);
515 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv);
516 int intel_display_suspend(struct drm_device *dev);
517 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv);
518 void intel_encoder_destroy(struct drm_encoder *encoder);
519 struct drm_display_mode *
520 intel_encoder_current_mode(struct intel_encoder *encoder);
521 bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy);
522 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy);
523 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
525 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
526 struct drm_file *file_priv);
527 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
528 void intel_crtc_vblank_on(const struct intel_crtc_state *crtc_state);
529 void intel_crtc_vblank_off(const struct intel_crtc_state *crtc_state);
531 int ilk_get_lanes_required(int target_clock, int link_bw, int bpp);
532 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
533 struct intel_digital_port *dport,
534 unsigned int expected_mask);
535 int intel_get_load_detect_pipe(struct drm_connector *connector,
536 struct intel_load_detect_pipe *old,
537 struct drm_modeset_acquire_ctx *ctx);
538 void intel_release_load_detect_pipe(struct drm_connector *connector,
539 struct intel_load_detect_pipe *old,
540 struct drm_modeset_acquire_ctx *ctx);
542 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
543 const struct i915_ggtt_view *view,
545 unsigned long *out_flags);
546 void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags);
547 struct drm_framebuffer *
548 intel_framebuffer_create(struct drm_i915_gem_object *obj,
549 struct drm_mode_fb_cmd2 *mode_cmd);
550 int intel_prepare_plane_fb(struct drm_plane *plane,
551 struct drm_plane_state *new_state);
552 void intel_cleanup_plane_fb(struct drm_plane *plane,
553 struct drm_plane_state *old_state);
555 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
558 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
559 const struct dpll *dpll);
560 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe);
561 int lpt_get_iclkip(struct drm_i915_private *dev_priv);
562 bool intel_fuzzy_clock_check(int clock1, int clock2);
564 void intel_prepare_reset(struct drm_i915_private *dev_priv);
565 void intel_finish_reset(struct drm_i915_private *dev_priv);
566 void intel_dp_get_m_n(struct intel_crtc *crtc,
567 struct intel_crtc_state *pipe_config);
568 void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state,
569 enum link_m_n_set m_n);
570 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
571 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state,
572 struct dpll *best_clock);
573 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
575 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state);
576 void hsw_enable_ips(const struct intel_crtc_state *crtc_state);
577 void hsw_disable_ips(const struct intel_crtc_state *crtc_state);
578 enum intel_display_power_domain intel_port_to_power_domain(enum port port);
579 enum intel_display_power_domain
580 intel_aux_power_domain(struct intel_digital_port *dig_port);
581 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
582 struct intel_crtc_state *pipe_config);
583 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
584 struct intel_crtc_state *crtc_state);
586 u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_center);
587 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
588 void skl_scaler_disable(const struct intel_crtc_state *old_crtc_state);
589 void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state);
590 u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
591 const struct intel_plane_state *plane_state);
592 u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state);
593 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
594 const struct intel_plane_state *plane_state);
595 u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state);
596 u32 skl_plane_stride(const struct intel_plane_state *plane_state,
598 int skl_check_plane_surface(struct intel_plane_state *plane_state);
599 int i9xx_check_plane_surface(struct intel_plane_state *plane_state);
600 int skl_format_to_fourcc(int format, bool rgb_order, bool alpha);
601 unsigned int i9xx_plane_max_stride(struct intel_plane *plane,
602 u32 pixel_format, u64 modifier,
603 unsigned int rotation);
604 int bdw_get_pipemisc_bpp(struct intel_crtc *crtc);
606 struct intel_display_error_state *
607 intel_display_capture_error_state(struct drm_i915_private *dev_priv);
608 void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
609 struct intel_display_error_state *error);
612 intel_format_info_is_yuv_semiplanar(const struct drm_format_info *info,
616 void intel_modeset_init_hw(struct drm_i915_private *i915);
617 int intel_modeset_init(struct drm_i915_private *i915);
618 void intel_modeset_driver_remove(struct drm_i915_private *i915);
619 void intel_modeset_driver_remove_noirq(struct drm_i915_private *i915);
620 void intel_display_resume(struct drm_device *dev);
621 void intel_init_pch_refclk(struct drm_i915_private *dev_priv);
623 /* modesetting asserts */
624 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
626 void assert_pll(struct drm_i915_private *dev_priv,
627 enum pipe pipe, bool state);
628 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
629 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
630 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state);
631 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
632 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
633 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
634 enum pipe pipe, bool state);
635 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
636 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
637 void assert_pipe(struct drm_i915_private *dev_priv,
638 enum transcoder cpu_transcoder, bool state);
639 #define assert_pipe_enabled(d, t) assert_pipe(d, t, true)
640 #define assert_pipe_disabled(d, t) assert_pipe(d, t, false)
642 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
643 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
644 * which may not necessarily be a user visible problem. This will either
645 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
646 * enable distros and users to tailor their preferred amount of i915 abrt
649 #define I915_STATE_WARN(condition, format...) ({ \
650 int __ret_warn_on = !!(condition); \
651 if (unlikely(__ret_warn_on)) \
652 if (!WARN(i915_modparams.verbose_state_checks, format)) \
654 unlikely(__ret_warn_on); \
657 #define I915_STATE_WARN_ON(x) \
658 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")