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25 #ifndef _INTEL_DISPLAY_H_
26 #define _INTEL_DISPLAY_H_
28 #include <drm/drm_util.h>
29 #include <drm/i915_drm.h>
31 struct drm_i915_private;
32 struct intel_plane_state;
51 * Keep the pipe enum values fixed: the code assumes that PIPE_A=0, the
52 * rest have consecutive values and match the enum values of transcoders
53 * with a 1:1 transcoder -> pipe mapping.
63 I915_MAX_PIPES = _PIPE_EDP
66 #define pipe_name(p) ((p) + 'A')
70 * The following transcoders have a 1:1 transcoder -> pipe mapping,
71 * keep their values fixed: the code assumes that TRANSCODER_A=0, the
72 * rest have consecutive values and match the enum values of the pipes
75 TRANSCODER_A = PIPE_A,
76 TRANSCODER_B = PIPE_B,
77 TRANSCODER_C = PIPE_C,
80 * The following transcoders can map to any pipe, their enum value
81 * doesn't need to stay fixed.
86 TRANSCODER_DSI_A = TRANSCODER_DSI_0, /* legacy DSI */
87 TRANSCODER_DSI_C = TRANSCODER_DSI_1, /* legacy DSI */
92 static inline const char *transcoder_name(enum transcoder transcoder)
103 case TRANSCODER_DSI_A:
105 case TRANSCODER_DSI_C:
112 static inline bool transcoder_is_dsi(enum transcoder transcoder)
114 return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C;
118 * Global legacy plane identifier. Valid only for primary/sprite
119 * planes on pre-g4x, and only for primary planes on g4x-bdw.
127 #define plane_name(p) ((p) + 'A')
128 #define sprite_name(p, s) ((p) * RUNTIME_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
131 * Per-pipe plane identifier.
132 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
133 * number of planes per CRTC. Not all platforms really have this many planes,
134 * which means some arrays of size I915_MAX_PLANES may have unused entries
135 * between the topmost sprite plane and the cursor plane.
137 * This is expected to be passed to various register macros
138 * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care.
153 #define for_each_plane_id_on_crtc(__crtc, __p) \
154 for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \
155 for_each_if((__crtc)->plane_ids_mask & BIT(__p))
158 * Ports identifier referenced from other drivers.
159 * Expected to remain stable over time
161 static inline const char *port_identifier(enum port port)
210 #define I915_NUM_PHYS_VLV 2
221 #define aux_ch_name(a) ((a) + 'A')
223 /* Used by dp and fdi links */
224 struct intel_link_m_n {
232 #define for_each_pipe(__dev_priv, __p) \
233 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
235 #define for_each_pipe_masked(__dev_priv, __p, __mask) \
236 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
237 for_each_if((__mask) & BIT(__p))
239 #define for_each_cpu_transcoder_masked(__dev_priv, __t, __mask) \
240 for ((__t) = 0; (__t) < I915_MAX_TRANSCODERS; (__t)++) \
241 for_each_if ((__mask) & (1 << (__t)))
243 #define for_each_universal_plane(__dev_priv, __pipe, __p) \
245 (__p) < RUNTIME_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
248 #define for_each_sprite(__dev_priv, __p, __s) \
250 (__s) < RUNTIME_INFO(__dev_priv)->num_sprites[(__p)]; \
253 #define for_each_port_masked(__port, __ports_mask) \
254 for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \
255 for_each_if((__ports_mask) & BIT(__port))
257 #define for_each_crtc(dev, crtc) \
258 list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
260 #define for_each_intel_plane(dev, intel_plane) \
261 list_for_each_entry(intel_plane, \
262 &(dev)->mode_config.plane_list, \
265 #define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \
266 list_for_each_entry(intel_plane, \
267 &(dev)->mode_config.plane_list, \
269 for_each_if((plane_mask) & \
270 drm_plane_mask(&intel_plane->base)))
272 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
273 list_for_each_entry(intel_plane, \
274 &(dev)->mode_config.plane_list, \
276 for_each_if((intel_plane)->pipe == (intel_crtc)->pipe)
278 #define for_each_intel_crtc(dev, intel_crtc) \
279 list_for_each_entry(intel_crtc, \
280 &(dev)->mode_config.crtc_list, \
283 #define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask) \
284 list_for_each_entry(intel_crtc, \
285 &(dev)->mode_config.crtc_list, \
287 for_each_if((crtc_mask) & drm_crtc_mask(&intel_crtc->base))
289 #define for_each_intel_encoder(dev, intel_encoder) \
290 list_for_each_entry(intel_encoder, \
291 &(dev)->mode_config.encoder_list, \
294 #define for_each_intel_dp(dev, intel_encoder) \
295 for_each_intel_encoder(dev, intel_encoder) \
296 for_each_if(intel_encoder_is_dp(intel_encoder))
298 #define for_each_intel_connector_iter(intel_connector, iter) \
299 while ((intel_connector = to_intel_connector(drm_connector_list_iter_next(iter))))
301 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
302 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
303 for_each_if((intel_encoder)->base.crtc == (__crtc))
305 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
306 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
307 for_each_if((intel_connector)->base.encoder == (__encoder))
309 #define for_each_old_intel_plane_in_state(__state, plane, old_plane_state, __i) \
311 (__i) < (__state)->base.dev->mode_config.num_total_plane && \
312 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
313 (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), 1); \
317 #define for_each_new_intel_plane_in_state(__state, plane, new_plane_state, __i) \
319 (__i) < (__state)->base.dev->mode_config.num_total_plane && \
320 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
321 (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
325 #define for_each_new_intel_crtc_in_state(__state, crtc, new_crtc_state, __i) \
327 (__i) < (__state)->base.dev->mode_config.num_crtc && \
328 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
329 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
333 #define for_each_oldnew_intel_plane_in_state(__state, plane, old_plane_state, new_plane_state, __i) \
335 (__i) < (__state)->base.dev->mode_config.num_total_plane && \
336 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
337 (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), \
338 (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
342 #define for_each_oldnew_intel_crtc_in_state(__state, crtc, old_crtc_state, new_crtc_state, __i) \
344 (__i) < (__state)->base.dev->mode_config.num_crtc && \
345 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
346 (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
347 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
351 void intel_link_compute_m_n(u16 bpp, int nlanes,
352 int pixel_clock, int link_clock,
353 struct intel_link_m_n *m_n,
355 bool is_ccs_modifier(u64 modifier);
356 void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv);
357 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
358 u32 pixel_format, u64 modifier);
359 bool intel_plane_can_remap(const struct intel_plane_state *plane_state);