drivers/gpu/drm/i915/display/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/export.h>
  29 #include <linux/i2c.h>
  30 #include <linux/notifier.h>
  31 #include <linux/reboot.h>
  32 #include <linux/slab.h>
  33 #include <linux/types.h>
  34
  35 #include <asm/byteorder.h>
  36
  37 #include <drm/drm_atomic_helper.h>
  38 #include <drm/drm_crtc.h>
  39 #include <drm/drm_dp_helper.h>
  40 #include <drm/drm_edid.h>
  41 #include <drm/drm_hdcp.h>
  42 #include <drm/drm_probe_helper.h>
  43 #include <drm/i915_drm.h>
  44
  45 #include "i915_debugfs.h"
  46 #include "i915_drv.h"
  47 #include "i915_trace.h"
  48 #include "intel_atomic.h"
  49 #include "intel_audio.h"
  50 #include "intel_connector.h"
  51 #include "intel_ddi.h"
  52 #include "intel_display_debugfs.h"
  53 #include "intel_display_types.h"
  54 #include "intel_dp.h"
  55 #include "intel_dp_link_training.h"
  56 #include "intel_dp_mst.h"
  57 #include "intel_dpio_phy.h"
  58 #include "intel_fifo_underrun.h"
  59 #include "intel_hdcp.h"
  60 #include "intel_hdmi.h"
  61 #include "intel_hotplug.h"
  62 #include "intel_lspcon.h"
  63 #include "intel_lvds.h"
  64 #include "intel_panel.h"
  65 #include "intel_psr.h"
  66 #include "intel_sideband.h"
  67 #include "intel_tc.h"
  68 #include "intel_vdsc.h"
  69
  70 #define DP_DPRX_ESI_LEN 14
  71
  72 /* DP DSC throughput values used for slice count calculations KPixels/s */
  73 #define DP_DSC_PEAK_PIXEL_RATE                  2720000
  74 #define DP_DSC_MAX_ENC_THROUGHPUT_0             340000
  75 #define DP_DSC_MAX_ENC_THROUGHPUT_1             400000
  76
  77 /* DP DSC FEC Overhead factor = 1/(0.972261) */
  78 #define DP_DSC_FEC_OVERHEAD_FACTOR              972261
  79
  80 /* Compliance test status bits  */
  81 #define INTEL_DP_RESOLUTION_SHIFT_MASK  0
  82 #define INTEL_DP_RESOLUTION_PREFERRED   (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  83 #define INTEL_DP_RESOLUTION_STANDARD    (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  84 #define INTEL_DP_RESOLUTION_FAILSAFE    (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  85
  86 struct dp_link_dpll {
  87         int clock;
  88         struct dpll dpll;
  89 };
  90
  91 static const struct dp_link_dpll g4x_dpll[] = {
  92         { 162000,
  93                 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
  94         { 270000,
  95                 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
  96 };
  97
  98 static const struct dp_link_dpll pch_dpll[] = {
  99         { 162000,
 100                 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
 101         { 270000,
 102                 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
 103 };
 104
 105 static const struct dp_link_dpll vlv_dpll[] = {
 106         { 162000,
 107                 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
 108         { 270000,
 109                 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
 110 };
 111
 112 /*
 113  * CHV supports eDP 1.4 that have  more link rates.
 114  * Below only provides the fixed rate but exclude variable rate.
 115  */
 116 static const struct dp_link_dpll chv_dpll[] = {
 117         /*
 118          * CHV requires to program fractional division for m2.
 119          * m2 is stored in fixed point format using formula below
 120          * (m2_int << 22) | m2_fraction
 121          */
 122         { 162000,       /* m2_int = 32, m2_fraction = 1677722 */
 123                 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
 124         { 270000,       /* m2_int = 27, m2_fraction = 0 */
 125                 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
 126 };
 127
 128 /* Constants for DP DSC configurations */
 129 static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};
 130
 131 /* With Single pipe configuration, HW is capable of supporting maximum
 132  * of 4 slices per line.
 133  */
 134 static const u8 valid_dsc_slicecount[] = {1, 2, 4};
 135
 136 /**
 137  * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
 138  * @intel_dp: DP struct
 139  *
 140  * If a CPU or PCH DP output is attached to an eDP panel, this function
 141  * will return true, and false otherwise.
 142  */
 143 bool intel_dp_is_edp(struct intel_dp *intel_dp)
 144 {
 145         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 146
 147         return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
 148 }
 149
 150 static void intel_dp_link_down(struct intel_encoder *encoder,
 151                                const struct intel_crtc_state *old_crtc_state);
 152 static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
 153 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 154 static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
 155                                            const struct intel_crtc_state *crtc_state);
 156 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
 157                                       enum pipe pipe);
 158 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
 159
 160 /* update sink rates from dpcd */
 161 static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
 162 {
 163         static const int dp_rates[] = {
 164                 162000, 270000, 540000, 810000
 165         };
 166         int i, max_rate;
 167
 168         max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
 169
 170         for (i = 0; i < ARRAY_SIZE(dp_rates); i++) {
 171                 if (dp_rates[i] > max_rate)
 172                         break;
 173                 intel_dp->sink_rates[i] = dp_rates[i];
 174         }
 175
 176         intel_dp->num_sink_rates = i;
 177 }
 178
 179 /* Get length of rates array potentially limited by max_rate. */
 180 static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate)
 181 {
 182         int i;
 183
 184         /* Limit results by potentially reduced max rate */
 185         for (i = 0; i < len; i++) {
 186                 if (rates[len - i - 1] <= max_rate)
 187                         return len - i;
 188         }
 189
 190         return 0;
 191 }
 192
 193 /* Get length of common rates array potentially limited by max_rate. */
 194 static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp,
 195                                           int max_rate)
 196 {
 197         return intel_dp_rate_limit_len(intel_dp->common_rates,
 198                                        intel_dp->num_common_rates, max_rate);
 199 }
 200
 201 /* Theoretical max between source and sink */
 202 static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
 203 {
 204         return intel_dp->common_rates[intel_dp->num_common_rates - 1];
 205 }
 206
 207 /* Theoretical max between source and sink */
 208 static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
 209 {
 210         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 211         int source_max = intel_dig_port->max_lanes;
 212         int sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
 213         int fia_max = intel_tc_port_fia_max_lane_count(intel_dig_port);
 214
 215         return min3(source_max, sink_max, fia_max);
 216 }
 217
 218 int intel_dp_max_lane_count(struct intel_dp *intel_dp)
 219 {
 220         return intel_dp->max_link_lane_count;
 221 }
 222
 223 int
 224 intel_dp_link_required(int pixel_clock, int bpp)
 225 {
 226         /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
 227         return DIV_ROUND_UP(pixel_clock * bpp, 8);
 228 }
 229
 230 int
 231 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 232 {
 233         /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the
 234          * link rate that is generally expressed in Gbps. Since, 8 bits of data
 235          * is transmitted every LS_Clk per lane, there is no need to account for
 236          * the channel encoding that is done in the PHY layer here.
 237          */
 238
 239         return max_link_clock * max_lanes;
 240 }
 241
 242 static int
 243 intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
 244 {
 245         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 246         struct intel_encoder *encoder = &intel_dig_port->base;
 247         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 248         int max_dotclk = dev_priv->max_dotclk_freq;
 249         int ds_max_dotclk;
 250
 251         int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
 252
 253         if (type != DP_DS_PORT_TYPE_VGA)
 254                 return max_dotclk;
 255
 256         ds_max_dotclk = drm_dp_downstream_max_clock(intel_dp->dpcd,
 257                                                     intel_dp->downstream_ports);
 258
 259         if (ds_max_dotclk != 0)
 260                 max_dotclk = min(max_dotclk, ds_max_dotclk);
 261
 262         return max_dotclk;
 263 }
 264
 265 static int cnl_max_source_rate(struct intel_dp *intel_dp)
 266 {
 267         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 268         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 269         enum port port = dig_port->base.port;
 270
 271         u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 272
 273         /* Low voltage SKUs are limited to max of 5.4G */
 274         if (voltage == VOLTAGE_INFO_0_85V)
 275                 return 540000;
 276
 277         /* For this SKU 8.1G is supported in all ports */
 278         if (IS_CNL_WITH_PORT_F(dev_priv))
 279                 return 810000;
 280
 281         /* For other SKUs, max rate on ports A and D is 5.4G */
 282         if (port == PORT_A || port == PORT_D)
 283                 return 540000;
 284
 285         return 810000;
 286 }
 287
 288 static int icl_max_source_rate(struct intel_dp *intel_dp)
 289 {
 290         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 291         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 292         enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
 293
 294         if (intel_phy_is_combo(dev_priv, phy) &&
 295             !IS_ELKHARTLAKE(dev_priv) &&
 296             !intel_dp_is_edp(intel_dp))
 297                 return 540000;
 298
 299         return 810000;
 300 }
 301
 302 static void
 303 intel_dp_set_source_rates(struct intel_dp *intel_dp)
 304 {
 305         /* The values must be in increasing order */
 306         static const int cnl_rates[] = {
 307                 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000
 308         };
 309         static const int bxt_rates[] = {
 310                 162000, 216000, 243000, 270000, 324000, 432000, 540000
 311         };
 312         static const int skl_rates[] = {
 313                 162000, 216000, 270000, 324000, 432000, 540000
 314         };
 315         static const int hsw_rates[] = {
 316                 162000, 270000, 540000
 317         };
 318         static const int g4x_rates[] = {
 319                 162000, 270000
 320         };
 321         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 322         struct intel_encoder *encoder = &dig_port->base;
 323         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 324         const int *source_rates;
 325         int size, max_rate = 0, vbt_max_rate;
 326
 327         /* This should only be done once */
 328         WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates);
 329
 330         if (INTEL_GEN(dev_priv) >= 10) {
 331                 source_rates = cnl_rates;
 332                 size = ARRAY_SIZE(cnl_rates);
 333                 if (IS_GEN(dev_priv, 10))
 334                         max_rate = cnl_max_source_rate(intel_dp);
 335                 else
 336                         max_rate = icl_max_source_rate(intel_dp);
 337         } else if (IS_GEN9_LP(dev_priv)) {
 338                 source_rates = bxt_rates;
 339                 size = ARRAY_SIZE(bxt_rates);
 340         } else if (IS_GEN9_BC(dev_priv)) {
 341                 source_rates = skl_rates;
 342                 size = ARRAY_SIZE(skl_rates);
 343         } else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
 344                    IS_BROADWELL(dev_priv)) {
 345                 source_rates = hsw_rates;
 346                 size = ARRAY_SIZE(hsw_rates);
 347         } else {
 348                 source_rates = g4x_rates;
 349                 size = ARRAY_SIZE(g4x_rates);
 350         }
 351
 352         vbt_max_rate = intel_bios_dp_max_link_rate(encoder);
 353         if (max_rate && vbt_max_rate)
 354                 max_rate = min(max_rate, vbt_max_rate);
 355         else if (vbt_max_rate)
 356                 max_rate = vbt_max_rate;
 357
 358         if (max_rate)
 359                 size = intel_dp_rate_limit_len(source_rates, size, max_rate);
 360
 361         intel_dp->source_rates = source_rates;
 362         intel_dp->num_source_rates = size;
 363 }
 364
 365 static int intersect_rates(const int *source_rates, int source_len,
 366                            const int *sink_rates, int sink_len,
 367                            int *common_rates)
 368 {
 369         int i = 0, j = 0, k = 0;
 370
 371         while (i < source_len && j < sink_len) {
 372                 if (source_rates[i] == sink_rates[j]) {
 373                         if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
 374                                 return k;
 375                         common_rates[k] = source_rates[i];
 376                         ++k;
 377                         ++i;
 378                         ++j;
 379                 } else if (source_rates[i] < sink_rates[j]) {
 380                         ++i;
 381                 } else {
 382                         ++j;
 383                 }
 384         }
 385         return k;
 386 }
 387
 388 /* return index of rate in rates array, or -1 if not found */
 389 static int intel_dp_rate_index(const int *rates, int len, int rate)
 390 {
 391         int i;
 392
 393         for (i = 0; i < len; i++)
 394                 if (rate == rates[i])
 395                         return i;
 396
 397         return -1;
 398 }
 399
 400 static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
 401 {
 402         WARN_ON(!intel_dp->num_source_rates || !intel_dp->num_sink_rates);
 403
 404         intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
 405                                                      intel_dp->num_source_rates,
 406                                                      intel_dp->sink_rates,
 407                                                      intel_dp->num_sink_rates,
 408                                                      intel_dp->common_rates);
 409
 410         /* Paranoia, there should always be something in common. */
 411         if (WARN_ON(intel_dp->num_common_rates == 0)) {
 412                 intel_dp->common_rates[0] = 162000;
 413                 intel_dp->num_common_rates = 1;
 414         }
 415 }
 416
 417 static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
 418                                        u8 lane_count)
 419 {
 420         /*
 421          * FIXME: we need to synchronize the current link parameters with
 422          * hardware readout. Currently fast link training doesn't work on
 423          * boot-up.
 424          */
 425         if (link_rate == 0 ||
 426             link_rate > intel_dp->max_link_rate)
 427                 return false;
 428
 429         if (lane_count == 0 ||
 430             lane_count > intel_dp_max_lane_count(intel_dp))
 431                 return false;
 432
 433         return true;
 434 }
 435
 436 static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp,
 437                                                      int link_rate,
 438                                                      u8 lane_count)
 439 {
 440         const struct drm_display_mode *fixed_mode =
 441                 intel_dp->attached_connector->panel.fixed_mode;
 442         int mode_rate, max_rate;
 443
 444         mode_rate = intel_dp_link_required(fixed_mode->clock, 18);
 445         max_rate = intel_dp_max_data_rate(link_rate, lane_count);
 446         if (mode_rate > max_rate)
 447                 return false;
 448
 449         return true;
 450 }
 451
 452 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
 453                                             int link_rate, u8 lane_count)
 454 {
 455         int index;
 456
 457         index = intel_dp_rate_index(intel_dp->common_rates,
 458                                     intel_dp->num_common_rates,
 459                                     link_rate);
 460         if (index > 0) {
 461                 if (intel_dp_is_edp(intel_dp) &&
 462                     !intel_dp_can_link_train_fallback_for_edp(intel_dp,
 463                                                               intel_dp->common_rates[index - 1],
 464                                                               lane_count)) {
 465                         DRM_DEBUG_KMS("Retrying Link training for eDP with same parameters\n");
 466                         return 0;
 467                 }
 468                 intel_dp->max_link_rate = intel_dp->common_rates[index - 1];
 469                 intel_dp->max_link_lane_count = lane_count;
 470         } else if (lane_count > 1) {
 471                 if (intel_dp_is_edp(intel_dp) &&
 472                     !intel_dp_can_link_train_fallback_for_edp(intel_dp,
 473                                                               intel_dp_max_common_rate(intel_dp),
 474                                                               lane_count >> 1)) {
 475                         DRM_DEBUG_KMS("Retrying Link training for eDP with same parameters\n");
 476                         return 0;
 477                 }
 478                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
 479                 intel_dp->max_link_lane_count = lane_count >> 1;
 480         } else {
 481                 DRM_ERROR("Link Training Unsuccessful\n");
 482                 return -1;
 483         }
 484
 485         return 0;
 486 }
 487
 488 u32 intel_dp_mode_to_fec_clock(u32 mode_clock)
 489 {
 490         return div_u64(mul_u32_u32(mode_clock, 1000000U),
 491                        DP_DSC_FEC_OVERHEAD_FACTOR);
 492 }
 493
 494 static int
 495 small_joiner_ram_size_bits(struct drm_i915_private *i915)
 496 {
 497         if (INTEL_GEN(i915) >= 11)
 498                 return 7680 * 8;
 499         else
 500                 return 6144 * 8;
 501 }
 502
 503 static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
 504                                        u32 link_clock, u32 lane_count,
 505                                        u32 mode_clock, u32 mode_hdisplay)
 506 {
 507         u32 bits_per_pixel, max_bpp_small_joiner_ram;
 508         int i;
 509
 510         /*
 511          * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)*
 512          * (LinkSymbolClock)* 8 * (TimeSlotsPerMTP)
 513          * for SST -> TimeSlotsPerMTP is 1,
 514          * for MST -> TimeSlotsPerMTP has to be calculated
 515          */
 516         bits_per_pixel = (link_clock * lane_count * 8) /
 517                          intel_dp_mode_to_fec_clock(mode_clock);
 518         drm_dbg_kms(&i915->drm, "Max link bpp: %u\n", bits_per_pixel);
 519
 520         /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
 521         max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) /
 522                 mode_hdisplay;
 523         drm_dbg_kms(&i915->drm, "Max small joiner bpp: %u\n",
 524                     max_bpp_small_joiner_ram);
 525
 526         /*
 527          * Greatest allowed DSC BPP = MIN (output BPP from available Link BW
 528          * check, output bpp from small joiner RAM check)
 529          */
 530         bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
 531
 532         /* Error out if the max bpp is less than smallest allowed valid bpp */
 533         if (bits_per_pixel < valid_dsc_bpp[0]) {
 534                 drm_dbg_kms(&i915->drm, "Unsupported BPP %u, min %u\n",
 535                             bits_per_pixel, valid_dsc_bpp[0]);
 536                 return 0;
 537         }
 538
 539         /* Find the nearest match in the array of known BPPs from VESA */
 540         for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) {
 541                 if (bits_per_pixel < valid_dsc_bpp[i + 1])
 542                         break;
 543         }
 544         bits_per_pixel = valid_dsc_bpp[i];
 545
 546         /*
 547          * Compressed BPP in U6.4 format so multiply by 16, for Gen 11,
 548          * fractional part is 0
 549          */
 550         return bits_per_pixel << 4;
 551 }
 552
 553 static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
 554                                        int mode_clock, int mode_hdisplay)
 555 {
 556         u8 min_slice_count, i;
 557         int max_slice_width;
 558
 559         if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE)
 560                 min_slice_count = DIV_ROUND_UP(mode_clock,
 561                                                DP_DSC_MAX_ENC_THROUGHPUT_0);
 562         else
 563                 min_slice_count = DIV_ROUND_UP(mode_clock,
 564                                                DP_DSC_MAX_ENC_THROUGHPUT_1);
 565
 566         max_slice_width = drm_dp_dsc_sink_max_slice_width(intel_dp->dsc_dpcd);
 567         if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) {
 568                 DRM_DEBUG_KMS("Unsupported slice width %d by DP DSC Sink device\n",
 569                               max_slice_width);
 570                 return 0;
 571         }
 572         /* Also take into account max slice width */
 573         min_slice_count = min_t(u8, min_slice_count,
 574                                 DIV_ROUND_UP(mode_hdisplay,
 575                                              max_slice_width));
 576
 577         /* Find the closest match to the valid slice count values */
 578         for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) {
 579                 if (valid_dsc_slicecount[i] >
 580                     drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
 581                                                     false))
 582                         break;
 583                 if (min_slice_count  <= valid_dsc_slicecount[i])
 584                         return valid_dsc_slicecount[i];
 585         }
 586
 587         DRM_DEBUG_KMS("Unsupported Slice Count %d\n", min_slice_count);
 588         return 0;
 589 }
 590
 591 static bool intel_dp_hdisplay_bad(struct drm_i915_private *dev_priv,
 592                                   int hdisplay)
 593 {
 594         /*
 595          * Older platforms don't like hdisplay==4096 with DP.
 596          *
 597          * On ILK/SNB/IVB the pipe seems to be somewhat running (scanline
 598          * and frame counter increment), but we don't get vblank interrupts,
 599          * and the pipe underruns immediately. The link also doesn't seem
 600          * to get trained properly.
 601          *
 602          * On CHV the vblank interrupts don't seem to disappear but
 603          * otherwise the symptoms are similar.
 604          *
 605          * TODO: confirm the behaviour on HSW+
 606          */
 607         return hdisplay == 4096 && !HAS_DDI(dev_priv);
 608 }
 609
 610 static enum drm_mode_status
 611 intel_dp_mode_valid(struct drm_connector *connector,
 612                     struct drm_display_mode *mode)
 613 {
 614         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
 615         struct intel_connector *intel_connector = to_intel_connector(connector);
 616         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 617         struct drm_i915_private *dev_priv = to_i915(connector->dev);
 618         int target_clock = mode->clock;
 619         int max_rate, mode_rate, max_lanes, max_link_clock;
 620         int max_dotclk;
 621         u16 dsc_max_output_bpp = 0;
 622         u8 dsc_slice_count = 0;
 623
 624         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 625                 return MODE_NO_DBLESCAN;
 626
 627         max_dotclk = intel_dp_downstream_max_dotclock(intel_dp);
 628
 629         if (intel_dp_is_edp(intel_dp) && fixed_mode) {
 630                 if (mode->hdisplay > fixed_mode->hdisplay)
 631                         return MODE_PANEL;
 632
 633                 if (mode->vdisplay > fixed_mode->vdisplay)
 634                         return MODE_PANEL;
 635
 636                 target_clock = fixed_mode->clock;
 637         }
 638
 639         max_link_clock = intel_dp_max_link_rate(intel_dp);
 640         max_lanes = intel_dp_max_lane_count(intel_dp);
 641
 642         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 643         mode_rate = intel_dp_link_required(target_clock, 18);
 644
 645         if (intel_dp_hdisplay_bad(dev_priv, mode->hdisplay))
 646                 return MODE_H_ILLEGAL;
 647
 648         /*
 649          * Output bpp is stored in 6.4 format so right shift by 4 to get the
 650          * integer value since we support only integer values of bpp.
 651          */
 652         if ((INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) &&
 653             drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
 654                 if (intel_dp_is_edp(intel_dp)) {
 655                         dsc_max_output_bpp =
 656                                 drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4;
 657                         dsc_slice_count =
 658                                 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
 659                                                                 true);
 660                 } else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
 661                         dsc_max_output_bpp =
 662                                 intel_dp_dsc_get_output_bpp(dev_priv,
 663                                                             max_link_clock,
 664                                                             max_lanes,
 665                                                             target_clock,
 666                                                             mode->hdisplay) >> 4;
 667                         dsc_slice_count =
 668                                 intel_dp_dsc_get_slice_count(intel_dp,
 669                                                              target_clock,
 670                                                              mode->hdisplay);
 671                 }
 672         }
 673
 674         if ((mode_rate > max_rate && !(dsc_max_output_bpp && dsc_slice_count)) ||
 675             target_clock > max_dotclk)
 676                 return MODE_CLOCK_HIGH;
 677
 678         if (mode->clock < 10000)
 679                 return MODE_CLOCK_LOW;
 680
 681         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 682                 return MODE_H_ILLEGAL;
 683
 684         return intel_mode_valid_max_plane_size(dev_priv, mode);
 685 }
 686
 687 u32 intel_dp_pack_aux(const u8 *src, int src_bytes)
 688 {
 689         int i;
 690         u32 v = 0;
 691
 692         if (src_bytes > 4)
 693                 src_bytes = 4;
 694         for (i = 0; i < src_bytes; i++)
 695                 v |= ((u32)src[i]) << ((3 - i) * 8);
 696         return v;
 697 }
 698
 699 static void intel_dp_unpack_aux(u32 src, u8 *dst, int dst_bytes)
 700 {
 701         int i;
 702         if (dst_bytes > 4)
 703                 dst_bytes = 4;
 704         for (i = 0; i < dst_bytes; i++)
 705                 dst[i] = src >> ((3-i) * 8);
 706 }
 707
 708 static void
 709 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp);
 710 static void
 711 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
 712                                               bool force_disable_vdd);
 713 static void
 714 intel_dp_pps_init(struct intel_dp *intel_dp);
 715
 716 static intel_wakeref_t
 717 pps_lock(struct intel_dp *intel_dp)
 718 {
 719         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 720         intel_wakeref_t wakeref;
 721
 722         /*
 723          * See intel_power_sequencer_reset() why we need
 724          * a power domain reference here.
 725          */
 726         wakeref = intel_display_power_get(dev_priv,
 727                                           intel_aux_power_domain(dp_to_dig_port(intel_dp)));
 728
 729         mutex_lock(&dev_priv->pps_mutex);
 730
 731         return wakeref;
 732 }
 733
 734 static intel_wakeref_t
 735 pps_unlock(struct intel_dp *intel_dp, intel_wakeref_t wakeref)
 736 {
 737         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 738
 739         mutex_unlock(&dev_priv->pps_mutex);
 740         intel_display_power_put(dev_priv,
 741                                 intel_aux_power_domain(dp_to_dig_port(intel_dp)),
 742                                 wakeref);
 743         return 0;
 744 }
 745
 746 #define with_pps_lock(dp, wf) \
 747         for ((wf) = pps_lock(dp); (wf); (wf) = pps_unlock((dp), (wf)))
 748
 749 static void
 750 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
 751 {
 752         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 753         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 754         enum pipe pipe = intel_dp->pps_pipe;
 755         bool pll_enabled, release_cl_override = false;
 756         enum dpio_phy phy = DPIO_PHY(pipe);
 757         enum dpio_channel ch = vlv_pipe_to_channel(pipe);
 758         u32 DP;
 759
 760         if (WARN(intel_de_read(dev_priv, intel_dp->output_reg) & DP_PORT_EN,
 761                  "skipping pipe %c power sequencer kick due to [ENCODER:%d:%s] being active\n",
 762                  pipe_name(pipe), intel_dig_port->base.base.base.id,
 763                  intel_dig_port->base.base.name))
 764                 return;
 765
 766         drm_dbg_kms(&dev_priv->drm,
 767                     "kicking pipe %c power sequencer for [ENCODER:%d:%s]\n",
 768                     pipe_name(pipe), intel_dig_port->base.base.base.id,
 769                     intel_dig_port->base.base.name);
 770
 771         /* Preserve the BIOS-computed detected bit. This is
 772          * supposed to be read-only.
 773          */
 774         DP = intel_de_read(dev_priv, intel_dp->output_reg) & DP_DETECTED;
 775         DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 776         DP |= DP_PORT_WIDTH(1);
 777         DP |= DP_LINK_TRAIN_PAT_1;
 778
 779         if (IS_CHERRYVIEW(dev_priv))
 780                 DP |= DP_PIPE_SEL_CHV(pipe);
 781         else
 782                 DP |= DP_PIPE_SEL(pipe);
 783
 784         pll_enabled = intel_de_read(dev_priv, DPLL(pipe)) & DPLL_VCO_ENABLE;
 785
 786         /*
 787          * The DPLL for the pipe must be enabled for this to work.
 788          * So enable temporarily it if it's not already enabled.
 789          */
 790         if (!pll_enabled) {
 791                 release_cl_override = IS_CHERRYVIEW(dev_priv) &&
 792                         !chv_phy_powergate_ch(dev_priv, phy, ch, true);
 793
 794                 if (vlv_force_pll_on(dev_priv, pipe, IS_CHERRYVIEW(dev_priv) ?
 795                                      &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
 796                         drm_err(&dev_priv->drm,
 797                                 "Failed to force on pll for pipe %c!\n",
 798                                 pipe_name(pipe));
 799                         return;
 800                 }
 801         }
 802
 803         /*
 804          * Similar magic as in intel_dp_enable_port().
 805          * We _must_ do this port enable + disable trick
 806          * to make this power sequencer lock onto the port.
 807          * Otherwise even VDD force bit won't work.
 808          */
 809         intel_de_write(dev_priv, intel_dp->output_reg, DP);
 810         intel_de_posting_read(dev_priv, intel_dp->output_reg);
 811
 812         intel_de_write(dev_priv, intel_dp->output_reg, DP | DP_PORT_EN);
 813         intel_de_posting_read(dev_priv, intel_dp->output_reg);
 814
 815         intel_de_write(dev_priv, intel_dp->output_reg, DP & ~DP_PORT_EN);
 816         intel_de_posting_read(dev_priv, intel_dp->output_reg);
 817
 818         if (!pll_enabled) {
 819                 vlv_force_pll_off(dev_priv, pipe);
 820
 821                 if (release_cl_override)
 822                         chv_phy_powergate_ch(dev_priv, phy, ch, false);
 823         }
 824 }
 825
 826 static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
 827 {
 828         struct intel_encoder *encoder;
 829         unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
 830
 831         /*
 832          * We don't have power sequencer currently.
 833          * Pick one that's not used by other ports.
 834          */
 835         for_each_intel_dp(&dev_priv->drm, encoder) {
 836                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 837
 838                 if (encoder->type == INTEL_OUTPUT_EDP) {
 839                         WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
 840                                 intel_dp->active_pipe != intel_dp->pps_pipe);
 841
 842                         if (intel_dp->pps_pipe != INVALID_PIPE)
 843                                 pipes &= ~(1 << intel_dp->pps_pipe);
 844                 } else {
 845                         WARN_ON(intel_dp->pps_pipe != INVALID_PIPE);
 846
 847                         if (intel_dp->active_pipe != INVALID_PIPE)
 848                                 pipes &= ~(1 << intel_dp->active_pipe);
 849                 }
 850         }
 851
 852         if (pipes == 0)
 853                 return INVALID_PIPE;
 854
 855         return ffs(pipes) - 1;
 856 }
 857
 858 static enum pipe
 859 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
 860 {
 861         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 862         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 863         enum pipe pipe;
 864
 865         lockdep_assert_held(&dev_priv->pps_mutex);
 866
 867         /* We should never land here with regular DP ports */
 868         WARN_ON(!intel_dp_is_edp(intel_dp));
 869
 870         WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
 871                 intel_dp->active_pipe != intel_dp->pps_pipe);
 872
 873         if (intel_dp->pps_pipe != INVALID_PIPE)
 874                 return intel_dp->pps_pipe;
 875
 876         pipe = vlv_find_free_pps(dev_priv);
 877
 878         /*
 879          * Didn't find one. This should not happen since there
 880          * are two power sequencers and up to two eDP ports.
 881          */
 882         if (WARN_ON(pipe == INVALID_PIPE))
 883                 pipe = PIPE_A;
 884
 885         vlv_steal_power_sequencer(dev_priv, pipe);
 886         intel_dp->pps_pipe = pipe;
 887
 888         drm_dbg_kms(&dev_priv->drm,
 889                     "picked pipe %c power sequencer for [ENCODER:%d:%s]\n",
 890                     pipe_name(intel_dp->pps_pipe),
 891                     intel_dig_port->base.base.base.id,
 892                     intel_dig_port->base.base.name);
 893
 894         /* init power sequencer on this pipe and port */
 895         intel_dp_init_panel_power_sequencer(intel_dp);
 896         intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
 897
 898         /*
 899          * Even vdd force doesn't work until we've made
 900          * the power sequencer lock in on the port.
 901          */
 902         vlv_power_sequencer_kick(intel_dp);
 903
 904         return intel_dp->pps_pipe;
 905 }
 906
 907 static int
 908 bxt_power_sequencer_idx(struct intel_dp *intel_dp)
 909 {
 910         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 911         int backlight_controller = dev_priv->vbt.backlight.controller;
 912
 913         lockdep_assert_held(&dev_priv->pps_mutex);
 914
 915         /* We should never land here with regular DP ports */
 916         WARN_ON(!intel_dp_is_edp(intel_dp));
 917
 918         if (!intel_dp->pps_reset)
 919                 return backlight_controller;
 920
 921         intel_dp->pps_reset = false;
 922
 923         /*
 924          * Only the HW needs to be reprogrammed, the SW state is fixed and
 925          * has been setup during connector init.
 926          */
 927         intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
 928
 929         return backlight_controller;
 930 }
 931
 932 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
 933                                enum pipe pipe);
 934
 935 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
 936                                enum pipe pipe)
 937 {
 938         return intel_de_read(dev_priv, PP_STATUS(pipe)) & PP_ON;
 939 }
 940
 941 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
 942                                 enum pipe pipe)
 943 {
 944         return intel_de_read(dev_priv, PP_CONTROL(pipe)) & EDP_FORCE_VDD;
 945 }
 946
 947 static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
 948                          enum pipe pipe)
 949 {
 950         return true;
 951 }
 952
 953 static enum pipe
 954 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
 955                      enum port port,
 956                      vlv_pipe_check pipe_check)
 957 {
 958         enum pipe pipe;
 959
 960         for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
 961                 u32 port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(pipe)) &
 962                         PANEL_PORT_SELECT_MASK;
 963
 964                 if (port_sel != PANEL_PORT_SELECT_VLV(port))
 965                         continue;
 966
 967                 if (!pipe_check(dev_priv, pipe))
 968                         continue;
 969
 970                 return pipe;
 971         }
 972
 973         return INVALID_PIPE;
 974 }
 975
 976 static void
 977 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
 978 {
 979         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 980         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 981         enum port port = intel_dig_port->base.port;
 982
 983         lockdep_assert_held(&dev_priv->pps_mutex);
 984
 985         /* try to find a pipe with this port selected */
 986         /* first pick one where the panel is on */
 987         intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 988                                                   vlv_pipe_has_pp_on);
 989         /* didn't find one? pick one where vdd is on */
 990         if (intel_dp->pps_pipe == INVALID_PIPE)
 991                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 992                                                           vlv_pipe_has_vdd_on);
 993         /* didn't find one? pick one with just the correct port */
 994         if (intel_dp->pps_pipe == INVALID_PIPE)
 995                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 996                                                           vlv_pipe_any);
 997
 998         /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
 999         if (intel_dp->pps_pipe == INVALID_PIPE) {
1000                 drm_dbg_kms(&dev_priv->drm,
1001                             "no initial power sequencer for [ENCODER:%d:%s]\n",
1002                             intel_dig_port->base.base.base.id,
1003                             intel_dig_port->base.base.name);
1004                 return;
1005         }
1006
1007         drm_dbg_kms(&dev_priv->drm,
1008                     "initial power sequencer for [ENCODER:%d:%s]: pipe %c\n",
1009                     intel_dig_port->base.base.base.id,
1010                     intel_dig_port->base.base.name,
1011                     pipe_name(intel_dp->pps_pipe));
1012
1013         intel_dp_init_panel_power_sequencer(intel_dp);
1014         intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
1015 }
1016
1017 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
1018 {
1019         struct intel_encoder *encoder;
1020
1021         if (WARN_ON(!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
1022                     !IS_GEN9_LP(dev_priv)))
1023                 return;
1024
1025         /*
1026          * We can't grab pps_mutex here due to deadlock with power_domain
1027          * mutex when power_domain functions are called while holding pps_mutex.
1028          * That also means that in order to use pps_pipe the code needs to
1029          * hold both a power domain reference and pps_mutex, and the power domain
1030          * reference get/put must be done while _not_ holding pps_mutex.
1031          * pps_{lock,unlock}() do these steps in the correct order, so one
1032          * should use them always.
1033          */
1034
1035         for_each_intel_dp(&dev_priv->drm, encoder) {
1036                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1037
1038                 WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
1039
1040                 if (encoder->type != INTEL_OUTPUT_EDP)
1041                         continue;
1042
1043                 if (IS_GEN9_LP(dev_priv))
1044                         intel_dp->pps_reset = true;
1045                 else
1046                         intel_dp->pps_pipe = INVALID_PIPE;
1047         }
1048 }
1049
1050 struct pps_registers {
1051         i915_reg_t pp_ctrl;
1052         i915_reg_t pp_stat;
1053         i915_reg_t pp_on;
1054         i915_reg_t pp_off;
1055         i915_reg_t pp_div;
1056 };
1057
1058 static void intel_pps_get_registers(struct intel_dp *intel_dp,
1059                                     struct pps_registers *regs)
1060 {
1061         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1062         int pps_idx = 0;
1063
1064         memset(regs, 0, sizeof(*regs));
1065
1066         if (IS_GEN9_LP(dev_priv))
1067                 pps_idx = bxt_power_sequencer_idx(intel_dp);
1068         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1069                 pps_idx = vlv_power_sequencer_pipe(intel_dp);
1070
1071         regs->pp_ctrl = PP_CONTROL(pps_idx);
1072         regs->pp_stat = PP_STATUS(pps_idx);
1073         regs->pp_on = PP_ON_DELAYS(pps_idx);
1074         regs->pp_off = PP_OFF_DELAYS(pps_idx);
1075
1076         /* Cycle delay moved from PP_DIVISOR to PP_CONTROL */
1077         if (IS_GEN9_LP(dev_priv) || INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
1078                 regs->pp_div = INVALID_MMIO_REG;
1079         else
1080                 regs->pp_div = PP_DIVISOR(pps_idx);
1081 }
1082
1083 static i915_reg_t
1084 _pp_ctrl_reg(struct intel_dp *intel_dp)
1085 {
1086         struct pps_registers regs;
1087
1088         intel_pps_get_registers(intel_dp, &regs);
1089
1090         return regs.pp_ctrl;
1091 }
1092
1093 static i915_reg_t
1094 _pp_stat_reg(struct intel_dp *intel_dp)
1095 {
1096         struct pps_registers regs;
1097
1098         intel_pps_get_registers(intel_dp, &regs);
1099
1100         return regs.pp_stat;
1101 }
1102
1103 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
1104    This function only applicable when panel PM state is not to be tracked */
1105 static int edp_notify_handler(struct notifier_block *this, unsigned long code,
1106                               void *unused)
1107 {
1108         struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
1109                                                  edp_notifier);
1110         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1111         intel_wakeref_t wakeref;
1112
1113         if (!intel_dp_is_edp(intel_dp) || code != SYS_RESTART)
1114                 return 0;
1115
1116         with_pps_lock(intel_dp, wakeref) {
1117                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1118                         enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
1119                         i915_reg_t pp_ctrl_reg, pp_div_reg;
1120                         u32 pp_div;
1121
1122                         pp_ctrl_reg = PP_CONTROL(pipe);
1123                         pp_div_reg  = PP_DIVISOR(pipe);
1124                         pp_div = intel_de_read(dev_priv, pp_div_reg);
1125                         pp_div &= PP_REFERENCE_DIVIDER_MASK;
1126
1127                         /* 0x1F write to PP_DIV_REG sets max cycle delay */
1128                         intel_de_write(dev_priv, pp_div_reg, pp_div | 0x1F);
1129                         intel_de_write(dev_priv, pp_ctrl_reg,
1130                                        PANEL_UNLOCK_REGS);
1131                         msleep(intel_dp->panel_power_cycle_delay);
1132                 }
1133         }
1134
1135         return 0;
1136 }
1137
1138 static bool edp_have_panel_power(struct intel_dp *intel_dp)
1139 {
1140         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1141
1142         lockdep_assert_held(&dev_priv->pps_mutex);
1143
1144         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1145             intel_dp->pps_pipe == INVALID_PIPE)
1146                 return false;
1147
1148         return (intel_de_read(dev_priv, _pp_stat_reg(intel_dp)) & PP_ON) != 0;
1149 }
1150
1151 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
1152 {
1153         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1154
1155         lockdep_assert_held(&dev_priv->pps_mutex);
1156
1157         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1158             intel_dp->pps_pipe == INVALID_PIPE)
1159                 return false;
1160
1161         return intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
1162 }
1163
1164 static void
1165 intel_dp_check_edp(struct intel_dp *intel_dp)
1166 {
1167         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1168
1169         if (!intel_dp_is_edp(intel_dp))
1170                 return;
1171
1172         if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
1173                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
1174                 drm_dbg_kms(&dev_priv->drm, "Status 0x%08x Control 0x%08x\n",
1175                             intel_de_read(dev_priv, _pp_stat_reg(intel_dp)),
1176                             intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp)));
1177         }
1178 }
1179
1180 static u32
1181 intel_dp_aux_wait_done(struct intel_dp *intel_dp)
1182 {
1183         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1184         i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
1185         const unsigned int timeout_ms = 10;
1186         u32 status;
1187         bool done;
1188
1189 #define C (((status = intel_uncore_read_notrace(&i915->uncore, ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1190         done = wait_event_timeout(i915->gmbus_wait_queue, C,
1191                                   msecs_to_jiffies_timeout(timeout_ms));
1192
1193         /* just trace the final value */
1194         trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true);
1195
1196         if (!done)
1197                 drm_err(&i915->drm,
1198                         "%s: did not complete or timeout within %ums (status 0x%08x)\n",
1199                         intel_dp->aux.name, timeout_ms, status);
1200 #undef C
1201
1202         return status;
1203 }
1204
1205 static u32 g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1206 {
1207         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1208
1209         if (index)
1210                 return 0;
1211
1212         /*
1213          * The clock divider is based off the hrawclk, and would like to run at
1214          * 2MHz.  So, take the hrawclk value and divide by 2000 and use that
1215          */
1216         return DIV_ROUND_CLOSEST(RUNTIME_INFO(dev_priv)->rawclk_freq, 2000);
1217 }
1218
1219 static u32 ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1220 {
1221         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1222         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1223         u32 freq;
1224
1225         if (index)
1226                 return 0;
1227
1228         /*
1229          * The clock divider is based off the cdclk or PCH rawclk, and would
1230          * like to run at 2MHz.  So, take the cdclk or PCH rawclk value and
1231          * divide by 2000 and use that
1232          */
1233         if (dig_port->aux_ch == AUX_CH_A)
1234                 freq = dev_priv->cdclk.hw.cdclk;
1235         else
1236                 freq = RUNTIME_INFO(dev_priv)->rawclk_freq;
1237         return DIV_ROUND_CLOSEST(freq, 2000);
1238 }
1239
1240 static u32 hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1241 {
1242         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1243         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1244
1245         if (dig_port->aux_ch != AUX_CH_A && HAS_PCH_LPT_H(dev_priv)) {
1246                 /* Workaround for non-ULT HSW */
1247                 switch (index) {
1248                 case 0: return 63;
1249                 case 1: return 72;
1250                 default: return 0;
1251                 }
1252         }
1253
1254         return ilk_get_aux_clock_divider(intel_dp, index);
1255 }
1256
1257 static u32 skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1258 {
1259         /*
1260          * SKL doesn't need us to program the AUX clock divider (Hardware will
1261          * derive the clock from CDCLK automatically). We still implement the
1262          * get_aux_clock_divider vfunc to plug-in into the existing code.
1263          */
1264         return index ? 0 : 1;
1265 }
1266
1267 static u32 g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
1268                                 int send_bytes,
1269                                 u32 aux_clock_divider)
1270 {
1271         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1272         struct drm_i915_private *dev_priv =
1273                         to_i915(intel_dig_port->base.base.dev);
1274         u32 precharge, timeout;
1275
1276         if (IS_GEN(dev_priv, 6))
1277                 precharge = 3;
1278         else
1279                 precharge = 5;
1280
1281         if (IS_BROADWELL(dev_priv))
1282                 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
1283         else
1284                 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
1285
1286         return DP_AUX_CH_CTL_SEND_BUSY |
1287                DP_AUX_CH_CTL_DONE |
1288                DP_AUX_CH_CTL_INTERRUPT |
1289                DP_AUX_CH_CTL_TIME_OUT_ERROR |
1290                timeout |
1291                DP_AUX_CH_CTL_RECEIVE_ERROR |
1292                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1293                (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1294                (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
1295 }
1296
1297 static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp,
1298                                 int send_bytes,
1299                                 u32 unused)
1300 {
1301         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1302         struct drm_i915_private *i915 =
1303                         to_i915(intel_dig_port->base.base.dev);
1304         enum phy phy = intel_port_to_phy(i915, intel_dig_port->base.port);
1305         u32 ret;
1306
1307         ret = DP_AUX_CH_CTL_SEND_BUSY |
1308               DP_AUX_CH_CTL_DONE |
1309               DP_AUX_CH_CTL_INTERRUPT |
1310               DP_AUX_CH_CTL_TIME_OUT_ERROR |
1311               DP_AUX_CH_CTL_TIME_OUT_MAX |
1312               DP_AUX_CH_CTL_RECEIVE_ERROR |
1313               (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1314               DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
1315               DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
1316
1317         if (intel_phy_is_tc(i915, phy) &&
1318             intel_dig_port->tc_mode == TC_PORT_TBT_ALT)
1319                 ret |= DP_AUX_CH_CTL_TBT_IO;
1320
1321         return ret;
1322 }
1323
1324 static int
1325 intel_dp_aux_xfer(struct intel_dp *intel_dp,
1326                   const u8 *send, int send_bytes,
1327                   u8 *recv, int recv_size,
1328                   u32 aux_send_ctl_flags)
1329 {
1330         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1331         struct drm_i915_private *i915 =
1332                         to_i915(intel_dig_port->base.base.dev);
1333         struct intel_uncore *uncore = &i915->uncore;
1334         enum phy phy = intel_port_to_phy(i915, intel_dig_port->base.port);
1335         bool is_tc_port = intel_phy_is_tc(i915, phy);
1336         i915_reg_t ch_ctl, ch_data[5];
1337         u32 aux_clock_divider;
1338         enum intel_display_power_domain aux_domain =
1339                 intel_aux_power_domain(intel_dig_port);
1340         intel_wakeref_t aux_wakeref;
1341         intel_wakeref_t pps_wakeref;
1342         int i, ret, recv_bytes;
1343         int try, clock = 0;
1344         u32 status;
1345         bool vdd;
1346
1347         ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
1348         for (i = 0; i < ARRAY_SIZE(ch_data); i++)
1349                 ch_data[i] = intel_dp->aux_ch_data_reg(intel_dp, i);
1350
1351         if (is_tc_port)
1352                 intel_tc_port_lock(intel_dig_port);
1353
1354         aux_wakeref = intel_display_power_get(i915, aux_domain);
1355         pps_wakeref = pps_lock(intel_dp);
1356
1357         /*
1358          * We will be called with VDD already enabled for dpcd/edid/oui reads.
1359          * In such cases we want to leave VDD enabled and it's up to upper layers
1360          * to turn it off. But for eg. i2c-dev access we need to turn it on/off
1361          * ourselves.
1362          */
1363         vdd = edp_panel_vdd_on(intel_dp);
1364
1365         /* dp aux is extremely sensitive to irq latency, hence request the
1366          * lowest possible wakeup latency and so prevent the cpu from going into
1367          * deep sleep states.
1368          */
1369         pm_qos_update_request(&i915->pm_qos, 0);
1370
1371         intel_dp_check_edp(intel_dp);
1372
1373         /* Try to wait for any previous AUX channel activity */
1374         for (try = 0; try < 3; try++) {
1375                 status = intel_uncore_read_notrace(uncore, ch_ctl);
1376                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1377                         break;
1378                 msleep(1);
1379         }
1380         /* just trace the final value */
1381         trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true);
1382
1383         if (try == 3) {
1384                 const u32 status = intel_uncore_read(uncore, ch_ctl);
1385
1386                 if (status != intel_dp->aux_busy_last_status) {
1387                         WARN(1, "%s: not started (status 0x%08x)\n",
1388                              intel_dp->aux.name, status);
1389                         intel_dp->aux_busy_last_status = status;
1390                 }
1391
1392                 ret = -EBUSY;
1393                 goto out;
1394         }
1395
1396         /* Only 5 data registers! */
1397         if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
1398                 ret = -E2BIG;
1399                 goto out;
1400         }
1401
1402         while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
1403                 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
1404                                                           send_bytes,
1405                                                           aux_clock_divider);
1406
1407                 send_ctl |= aux_send_ctl_flags;
1408
1409                 /* Must try at least 3 times according to DP spec */
1410                 for (try = 0; try < 5; try++) {
1411                         /* Load the send data into the aux channel data registers */
1412                         for (i = 0; i < send_bytes; i += 4)
1413                                 intel_uncore_write(uncore,
1414                                                    ch_data[i >> 2],
1415                                                    intel_dp_pack_aux(send + i,
1416                                                                      send_bytes - i));
1417
1418                         /* Send the command and wait for it to complete */
1419                         intel_uncore_write(uncore, ch_ctl, send_ctl);
1420
1421                         status = intel_dp_aux_wait_done(intel_dp);
1422
1423                         /* Clear done status and any errors */
1424                         intel_uncore_write(uncore,
1425                                            ch_ctl,
1426                                            status |
1427                                            DP_AUX_CH_CTL_DONE |
1428                                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
1429                                            DP_AUX_CH_CTL_RECEIVE_ERROR);
1430
1431                         /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
1432                          *   400us delay required for errors and timeouts
1433                          *   Timeout errors from the HW already meet this
1434                          *   requirement so skip to next iteration
1435                          */
1436                         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
1437                                 continue;
1438
1439                         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1440                                 usleep_range(400, 500);
1441                                 continue;
1442                         }
1443                         if (status & DP_AUX_CH_CTL_DONE)
1444                                 goto done;
1445                 }
1446         }
1447
1448         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1449                 drm_err(&i915->drm, "%s: not done (status 0x%08x)\n",
1450                         intel_dp->aux.name, status);
1451                 ret = -EBUSY;
1452                 goto out;
1453         }
1454
1455 done:
1456         /* Check for timeout or receive error.
1457          * Timeouts occur when the sink is not connected
1458          */
1459         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1460                 drm_err(&i915->drm, "%s: receive error (status 0x%08x)\n",
1461                         intel_dp->aux.name, status);
1462                 ret = -EIO;
1463                 goto out;
1464         }
1465
1466         /* Timeouts occur when the device isn't connected, so they're
1467          * "normal" -- don't fill the kernel log with these */
1468         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
1469                 drm_dbg_kms(&i915->drm, "%s: timeout (status 0x%08x)\n",
1470                             intel_dp->aux.name, status);
1471                 ret = -ETIMEDOUT;
1472                 goto out;
1473         }
1474
1475         /* Unload any bytes sent back from the other side */
1476         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
1477                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
1478
1479         /*
1480          * By BSpec: "Message sizes of 0 or >20 are not allowed."
1481          * We have no idea of what happened so we return -EBUSY so
1482          * drm layer takes care for the necessary retries.
1483          */
1484         if (recv_bytes == 0 || recv_bytes > 20) {
1485                 drm_dbg_kms(&i915->drm,
1486                             "%s: Forbidden recv_bytes = %d on aux transaction\n",
1487                             intel_dp->aux.name, recv_bytes);
1488                 ret = -EBUSY;
1489                 goto out;
1490         }
1491
1492         if (recv_bytes > recv_size)
1493                 recv_bytes = recv_size;
1494
1495         for (i = 0; i < recv_bytes; i += 4)
1496                 intel_dp_unpack_aux(intel_uncore_read(uncore, ch_data[i >> 2]),
1497                                     recv + i, recv_bytes - i);
1498
1499         ret = recv_bytes;
1500 out:
1501         pm_qos_update_request(&i915->pm_qos, PM_QOS_DEFAULT_VALUE);
1502
1503         if (vdd)
1504                 edp_panel_vdd_off(intel_dp, false);
1505
1506         pps_unlock(intel_dp, pps_wakeref);
1507         intel_display_power_put_async(i915, aux_domain, aux_wakeref);
1508
1509         if (is_tc_port)
1510                 intel_tc_port_unlock(intel_dig_port);
1511
1512         return ret;
1513 }
1514
1515 #define BARE_ADDRESS_SIZE       3
1516 #define HEADER_SIZE             (BARE_ADDRESS_SIZE + 1)
1517
1518 static void
1519 intel_dp_aux_header(u8 txbuf[HEADER_SIZE],
1520                     const struct drm_dp_aux_msg *msg)
1521 {
1522         txbuf[0] = (msg->request << 4) | ((msg->address >> 16) & 0xf);
1523         txbuf[1] = (msg->address >> 8) & 0xff;
1524         txbuf[2] = msg->address & 0xff;
1525         txbuf[3] = msg->size - 1;
1526 }
1527
1528 static ssize_t
1529 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
1530 {
1531         struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
1532         u8 txbuf[20], rxbuf[20];
1533         size_t txsize, rxsize;
1534         int ret;
1535
1536         intel_dp_aux_header(txbuf, msg);
1537
1538         switch (msg->request & ~DP_AUX_I2C_MOT) {
1539         case DP_AUX_NATIVE_WRITE:
1540         case DP_AUX_I2C_WRITE:
1541         case DP_AUX_I2C_WRITE_STATUS_UPDATE:
1542                 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
1543                 rxsize = 2; /* 0 or 1 data bytes */
1544
1545                 if (WARN_ON(txsize > 20))
1546                         return -E2BIG;
1547
1548                 WARN_ON(!msg->buffer != !msg->size);
1549
1550                 if (msg->buffer)
1551                         memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
1552
1553                 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
1554                                         rxbuf, rxsize, 0);
1555                 if (ret > 0) {
1556                         msg->reply = rxbuf[0] >> 4;
1557
1558                         if (ret > 1) {
1559                                 /* Number of bytes written in a short write. */
1560                                 ret = clamp_t(int, rxbuf[1], 0, msg->size);
1561                         } else {
1562                                 /* Return payload size. */
1563                                 ret = msg->size;
1564                         }
1565                 }
1566                 break;
1567
1568         case DP_AUX_NATIVE_READ:
1569         case DP_AUX_I2C_READ:
1570                 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
1571                 rxsize = msg->size + 1;
1572
1573                 if (WARN_ON(rxsize > 20))
1574                         return -E2BIG;
1575
1576                 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
1577                                         rxbuf, rxsize, 0);
1578                 if (ret > 0) {
1579                         msg->reply = rxbuf[0] >> 4;
1580                         /*
1581                          * Assume happy day, and copy the data. The caller is
1582                          * expected to check msg->reply before touching it.
1583                          *
1584                          * Return payload size.
1585                          */
1586                         ret--;
1587                         memcpy(msg->buffer, rxbuf + 1, ret);
1588                 }
1589                 break;
1590
1591         default:
1592                 ret = -EINVAL;
1593                 break;
1594         }
1595
1596         return ret;
1597 }
1598
1599
1600 static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp)
1601 {
1602         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1603         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1604         enum aux_ch aux_ch = dig_port->aux_ch;
1605
1606         switch (aux_ch) {
1607         case AUX_CH_B:
1608         case AUX_CH_C:
1609         case AUX_CH_D:
1610                 return DP_AUX_CH_CTL(aux_ch);
1611         default:
1612                 MISSING_CASE(aux_ch);
1613                 return DP_AUX_CH_CTL(AUX_CH_B);
1614         }
1615 }
1616
1617 static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index)
1618 {
1619         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1620         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1621         enum aux_ch aux_ch = dig_port->aux_ch;
1622
1623         switch (aux_ch) {
1624         case AUX_CH_B:
1625         case AUX_CH_C:
1626         case AUX_CH_D:
1627                 return DP_AUX_CH_DATA(aux_ch, index);
1628         default:
1629                 MISSING_CASE(aux_ch);
1630                 return DP_AUX_CH_DATA(AUX_CH_B, index);
1631         }
1632 }
1633
1634 static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp)
1635 {
1636         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1637         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1638         enum aux_ch aux_ch = dig_port->aux_ch;
1639
1640         switch (aux_ch) {
1641         case AUX_CH_A:
1642                 return DP_AUX_CH_CTL(aux_ch);
1643         case AUX_CH_B:
1644         case AUX_CH_C:
1645         case AUX_CH_D:
1646                 return PCH_DP_AUX_CH_CTL(aux_ch);
1647         default:
1648                 MISSING_CASE(aux_ch);
1649                 return DP_AUX_CH_CTL(AUX_CH_A);
1650         }
1651 }
1652
1653 static i915_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index)
1654 {
1655         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1656         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1657         enum aux_ch aux_ch = dig_port->aux_ch;
1658
1659         switch (aux_ch) {
1660         case AUX_CH_A:
1661                 return DP_AUX_CH_DATA(aux_ch, index);
1662         case AUX_CH_B:
1663         case AUX_CH_C:
1664         case AUX_CH_D:
1665                 return PCH_DP_AUX_CH_DATA(aux_ch, index);
1666         default:
1667                 MISSING_CASE(aux_ch);
1668                 return DP_AUX_CH_DATA(AUX_CH_A, index);
1669         }
1670 }
1671
1672 static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp)
1673 {
1674         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1675         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1676         enum aux_ch aux_ch = dig_port->aux_ch;
1677
1678         switch (aux_ch) {
1679         case AUX_CH_A:
1680         case AUX_CH_B:
1681         case AUX_CH_C:
1682         case AUX_CH_D:
1683         case AUX_CH_E:
1684         case AUX_CH_F:
1685         case AUX_CH_G:
1686                 return DP_AUX_CH_CTL(aux_ch);
1687         default:
1688                 MISSING_CASE(aux_ch);
1689                 return DP_AUX_CH_CTL(AUX_CH_A);
1690         }
1691 }
1692
1693 static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index)
1694 {
1695         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1696         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1697         enum aux_ch aux_ch = dig_port->aux_ch;
1698
1699         switch (aux_ch) {
1700         case AUX_CH_A:
1701         case AUX_CH_B:
1702         case AUX_CH_C:
1703         case AUX_CH_D:
1704         case AUX_CH_E:
1705         case AUX_CH_F:
1706         case AUX_CH_G:
1707                 return DP_AUX_CH_DATA(aux_ch, index);
1708         default:
1709                 MISSING_CASE(aux_ch);
1710                 return DP_AUX_CH_DATA(AUX_CH_A, index);
1711         }
1712 }
1713
1714 static void
1715 intel_dp_aux_fini(struct intel_dp *intel_dp)
1716 {
1717         kfree(intel_dp->aux.name);
1718 }
1719
1720 static void
1721 intel_dp_aux_init(struct intel_dp *intel_dp)
1722 {
1723         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1724         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1725         struct intel_encoder *encoder = &dig_port->base;
1726
1727         if (INTEL_GEN(dev_priv) >= 9) {
1728                 intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg;
1729                 intel_dp->aux_ch_data_reg = skl_aux_data_reg;
1730         } else if (HAS_PCH_SPLIT(dev_priv)) {
1731                 intel_dp->aux_ch_ctl_reg = ilk_aux_ctl_reg;
1732                 intel_dp->aux_ch_data_reg = ilk_aux_data_reg;
1733         } else {
1734                 intel_dp->aux_ch_ctl_reg = g4x_aux_ctl_reg;
1735                 intel_dp->aux_ch_data_reg = g4x_aux_data_reg;
1736         }
1737
1738         if (INTEL_GEN(dev_priv) >= 9)
1739                 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
1740         else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
1741                 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
1742         else if (HAS_PCH_SPLIT(dev_priv))
1743                 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
1744         else
1745                 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
1746
1747         if (INTEL_GEN(dev_priv) >= 9)
1748                 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
1749         else
1750                 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
1751
1752         drm_dp_aux_init(&intel_dp->aux);
1753
1754         /* Failure to allocate our preferred name is not critical */
1755         intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX %c/port %c",
1756                                        aux_ch_name(dig_port->aux_ch),
1757                                        port_name(encoder->port));
1758         intel_dp->aux.transfer = intel_dp_aux_transfer;
1759 }
1760
1761 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
1762 {
1763         int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
1764
1765         return max_rate >= 540000;
1766 }
1767
1768 bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp)
1769 {
1770         int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
1771
1772         return max_rate >= 810000;
1773 }
1774
1775 static void
1776 intel_dp_set_clock(struct intel_encoder *encoder,
1777                    struct intel_crtc_state *pipe_config)
1778 {
1779         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1780         const struct dp_link_dpll *divisor = NULL;
1781         int i, count = 0;
1782
1783         if (IS_G4X(dev_priv)) {
1784                 divisor = g4x_dpll;
1785                 count = ARRAY_SIZE(g4x_dpll);
1786         } else if (HAS_PCH_SPLIT(dev_priv)) {
1787                 divisor = pch_dpll;
1788                 count = ARRAY_SIZE(pch_dpll);
1789         } else if (IS_CHERRYVIEW(dev_priv)) {
1790                 divisor = chv_dpll;
1791                 count = ARRAY_SIZE(chv_dpll);
1792         } else if (IS_VALLEYVIEW(dev_priv)) {
1793                 divisor = vlv_dpll;
1794                 count = ARRAY_SIZE(vlv_dpll);
1795         }
1796
1797         if (divisor && count) {
1798                 for (i = 0; i < count; i++) {
1799                         if (pipe_config->port_clock == divisor[i].clock) {
1800                                 pipe_config->dpll = divisor[i].dpll;
1801                                 pipe_config->clock_set = true;
1802                                 break;
1803                         }
1804                 }
1805         }
1806 }
1807
1808 static void snprintf_int_array(char *str, size_t len,
1809                                const int *array, int nelem)
1810 {
1811         int i;
1812
1813         str[0] = '\0';
1814
1815         for (i = 0; i < nelem; i++) {
1816                 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1817                 if (r >= len)
1818                         return;
1819                 str += r;
1820                 len -= r;
1821         }
1822 }
1823
1824 static void intel_dp_print_rates(struct intel_dp *intel_dp)
1825 {
1826         char str[128]; /* FIXME: too big for stack? */
1827
1828         if (!drm_debug_enabled(DRM_UT_KMS))
1829                 return;
1830
1831         snprintf_int_array(str, sizeof(str),
1832                            intel_dp->source_rates, intel_dp->num_source_rates);
1833         DRM_DEBUG_KMS("source rates: %s\n", str);
1834
1835         snprintf_int_array(str, sizeof(str),
1836                            intel_dp->sink_rates, intel_dp->num_sink_rates);
1837         DRM_DEBUG_KMS("sink rates: %s\n", str);
1838
1839         snprintf_int_array(str, sizeof(str),
1840                            intel_dp->common_rates, intel_dp->num_common_rates);
1841         DRM_DEBUG_KMS("common rates: %s\n", str);
1842 }
1843
1844 int
1845 intel_dp_max_link_rate(struct intel_dp *intel_dp)
1846 {
1847         int len;
1848
1849         len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
1850         if (WARN_ON(len <= 0))
1851                 return 162000;
1852
1853         return intel_dp->common_rates[len - 1];
1854 }
1855
1856 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1857 {
1858         int i = intel_dp_rate_index(intel_dp->sink_rates,
1859                                     intel_dp->num_sink_rates, rate);
1860
1861         if (WARN_ON(i < 0))
1862                 i = 0;
1863
1864         return i;
1865 }
1866
1867 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1868                            u8 *link_bw, u8 *rate_select)
1869 {
1870         /* eDP 1.4 rate select method. */
1871         if (intel_dp->use_rate_select) {
1872                 *link_bw = 0;
1873                 *rate_select =
1874                         intel_dp_rate_select(intel_dp, port_clock);
1875         } else {
1876                 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1877                 *rate_select = 0;
1878         }
1879 }
1880
1881 static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
1882                                          const struct intel_crtc_state *pipe_config)
1883 {
1884         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1885
1886         /* On TGL, FEC is supported on all Pipes */
1887         if (INTEL_GEN(dev_priv) >= 12)
1888                 return true;
1889
1890         if (IS_GEN(dev_priv, 11) && pipe_config->cpu_transcoder != TRANSCODER_A)
1891                 return true;
1892
1893         return false;
1894 }
1895
1896 static bool intel_dp_supports_fec(struct intel_dp *intel_dp,
1897                                   const struct intel_crtc_state *pipe_config)
1898 {
1899         return intel_dp_source_supports_fec(intel_dp, pipe_config) &&
1900                 drm_dp_sink_supports_fec(intel_dp->fec_capable);
1901 }
1902
1903 static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
1904                                   const struct intel_crtc_state *crtc_state)
1905 {
1906         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1907
1908         if (!intel_dp_is_edp(intel_dp) && !crtc_state->fec_enable)
1909                 return false;
1910
1911         return intel_dsc_source_support(encoder, crtc_state) &&
1912                 drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd);
1913 }
1914
1915 static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
1916                                 struct intel_crtc_state *pipe_config)
1917 {
1918         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1919         struct intel_connector *intel_connector = intel_dp->attached_connector;
1920         int bpp, bpc;
1921
1922         bpp = pipe_config->pipe_bpp;
1923         bpc = drm_dp_downstream_max_bpc(intel_dp->dpcd, intel_dp->downstream_ports);
1924
1925         if (bpc > 0)
1926                 bpp = min(bpp, 3*bpc);
1927
1928         if (intel_dp_is_edp(intel_dp)) {
1929                 /* Get bpp from vbt only for panels that dont have bpp in edid */
1930                 if (intel_connector->base.display_info.bpc == 0 &&
1931                     dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp) {
1932                         drm_dbg_kms(&dev_priv->drm,
1933                                     "clamping bpp for eDP panel to BIOS-provided %i\n",
1934                                     dev_priv->vbt.edp.bpp);
1935                         bpp = dev_priv->vbt.edp.bpp;
1936                 }
1937         }
1938
1939         return bpp;
1940 }
1941
1942 /* Adjust link config limits based on compliance test requests. */
1943 void
1944 intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
1945                                   struct intel_crtc_state *pipe_config,
1946                                   struct link_config_limits *limits)
1947 {
1948         /* For DP Compliance we override the computed bpp for the pipe */
1949         if (intel_dp->compliance.test_data.bpc != 0) {
1950                 int bpp = 3 * intel_dp->compliance.test_data.bpc;
1951
1952                 limits->min_bpp = limits->max_bpp = bpp;
1953                 pipe_config->dither_force_disable = bpp == 6 * 3;
1954
1955                 DRM_DEBUG_KMS("Setting pipe_bpp to %d\n", bpp);
1956         }
1957
1958         /* Use values requested by Compliance Test Request */
1959         if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
1960                 int index;
1961
1962                 /* Validate the compliance test data since max values
1963                  * might have changed due to link train fallback.
1964                  */
1965                 if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate,
1966                                                intel_dp->compliance.test_lane_count)) {
1967                         index = intel_dp_rate_index(intel_dp->common_rates,
1968                                                     intel_dp->num_common_rates,
1969                                                     intel_dp->compliance.test_link_rate);
1970                         if (index >= 0)
1971                                 limits->min_clock = limits->max_clock = index;
1972                         limits->min_lane_count = limits->max_lane_count =
1973                                 intel_dp->compliance.test_lane_count;
1974                 }
1975         }
1976 }
1977
1978 static int intel_dp_output_bpp(const struct intel_crtc_state *crtc_state, int bpp)
1979 {
1980         /*
1981          * bpp value was assumed to RGB format. And YCbCr 4:2:0 output
1982          * format of the number of bytes per pixel will be half the number
1983          * of bytes of RGB pixel.
1984          */
1985         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
1986                 bpp /= 2;
1987
1988         return bpp;
1989 }
1990
1991 /* Optimize link config in order: max bpp, min clock, min lanes */
1992 static int
1993 intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
1994                                   struct intel_crtc_state *pipe_config,
1995                                   const struct link_config_limits *limits)
1996 {
1997         struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
1998         int bpp, clock, lane_count;
1999         int mode_rate, link_clock, link_avail;
2000
2001         for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
2002                 int output_bpp = intel_dp_output_bpp(pipe_config, bpp);
2003
2004                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
2005                                                    output_bpp);
2006
2007                 for (clock = limits->min_clock; clock <= limits->max_clock; clock++) {
2008                         for (lane_count = limits->min_lane_count;
2009                              lane_count <= limits->max_lane_count;
2010                              lane_count <<= 1) {
2011                                 link_clock = intel_dp->common_rates[clock];
2012                                 link_avail = intel_dp_max_data_rate(link_clock,
2013                                                                     lane_count);
2014
2015                                 if (mode_rate <= link_avail) {
2016                                         pipe_config->lane_count = lane_count;
2017                                         pipe_config->pipe_bpp = bpp;
2018                                         pipe_config->port_clock = link_clock;
2019
2020                                         return 0;
2021                                 }
2022                         }
2023                 }
2024         }
2025
2026         return -EINVAL;
2027 }
2028
2029 static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc)
2030 {
2031         int i, num_bpc;
2032         u8 dsc_bpc[3] = {0};
2033
2034         num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
2035                                                        dsc_bpc);
2036         for (i = 0; i < num_bpc; i++) {
2037                 if (dsc_max_bpc >= dsc_bpc[i])
2038                         return dsc_bpc[i] * 3;
2039         }
2040
2041         return 0;
2042 }
2043
2044 #define DSC_SUPPORTED_VERSION_MIN               1
2045
2046 static int intel_dp_dsc_compute_params(struct intel_encoder *encoder,
2047                                        struct intel_crtc_state *crtc_state)
2048 {
2049         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2050         struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
2051         u8 line_buf_depth;
2052         int ret;
2053
2054         ret = intel_dsc_compute_params(encoder, crtc_state);
2055         if (ret)
2056                 return ret;
2057
2058         /*
2059          * Slice Height of 8 works for all currently available panels. So start
2060          * with that if pic_height is an integral multiple of 8. Eventually add
2061          * logic to try multiple slice heights.
2062          */
2063         if (vdsc_cfg->pic_height % 8 == 0)
2064                 vdsc_cfg->slice_height = 8;
2065         else if (vdsc_cfg->pic_height % 4 == 0)
2066                 vdsc_cfg->slice_height = 4;
2067         else
2068                 vdsc_cfg->slice_height = 2;
2069
2070         vdsc_cfg->dsc_version_major =
2071                 (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
2072                  DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT;
2073         vdsc_cfg->dsc_version_minor =
2074                 min(DSC_SUPPORTED_VERSION_MIN,
2075                     (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
2076                      DP_DSC_MINOR_MASK) >> DP_DSC_MINOR_SHIFT);
2077
2078         vdsc_cfg->convert_rgb = intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &
2079                 DP_DSC_RGB;
2080
2081         line_buf_depth = drm_dp_dsc_sink_line_buf_depth(intel_dp->dsc_dpcd);
2082         if (!line_buf_depth) {
2083                 DRM_DEBUG_KMS("DSC Sink Line Buffer Depth invalid\n");
2084                 return -EINVAL;
2085         }
2086
2087         if (vdsc_cfg->dsc_version_minor == 2)
2088                 vdsc_cfg->line_buf_depth = (line_buf_depth == DSC_1_2_MAX_LINEBUF_DEPTH_BITS) ?
2089                         DSC_1_2_MAX_LINEBUF_DEPTH_VAL : line_buf_depth;
2090         else
2091                 vdsc_cfg->line_buf_depth = (line_buf_depth > DSC_1_1_MAX_LINEBUF_DEPTH_BITS) ?
2092                         DSC_1_1_MAX_LINEBUF_DEPTH_BITS : line_buf_depth;
2093
2094         vdsc_cfg->block_pred_enable =
2095                 intel_dp->dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] &
2096                 DP_DSC_BLK_PREDICTION_IS_SUPPORTED;
2097
2098         return drm_dsc_compute_rc_parameters(vdsc_cfg);
2099 }
2100
2101 static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
2102                                        struct intel_crtc_state *pipe_config,
2103                                        struct drm_connector_state *conn_state,
2104                                        struct link_config_limits *limits)
2105 {
2106         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2107         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2108         struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2109         u8 dsc_max_bpc;
2110         int pipe_bpp;
2111         int ret;
2112
2113         pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
2114                 intel_dp_supports_fec(intel_dp, pipe_config);
2115
2116         if (!intel_dp_supports_dsc(intel_dp, pipe_config))
2117                 return -EINVAL;
2118
2119         /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
2120         if (INTEL_GEN(dev_priv) >= 12)
2121                 dsc_max_bpc = min_t(u8, 12, conn_state->max_requested_bpc);
2122         else
2123                 dsc_max_bpc = min_t(u8, 10,
2124                                     conn_state->max_requested_bpc);
2125
2126         pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, dsc_max_bpc);
2127
2128         /* Min Input BPC for ICL+ is 8 */
2129         if (pipe_bpp < 8 * 3) {
2130                 drm_dbg_kms(&dev_priv->drm,
2131                             "No DSC support for less than 8bpc\n");
2132                 return -EINVAL;
2133         }
2134
2135         /*
2136          * For now enable DSC for max bpp, max link rate, max lane count.
2137          * Optimize this later for the minimum possible link rate/lane count
2138          * with DSC enabled for the requested mode.
2139          */
2140         pipe_config->pipe_bpp = pipe_bpp;
2141         pipe_config->port_clock = intel_dp->common_rates[limits->max_clock];
2142         pipe_config->lane_count = limits->max_lane_count;
2143
2144         if (intel_dp_is_edp(intel_dp)) {
2145                 pipe_config->dsc.compressed_bpp =
2146                         min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4,
2147                               pipe_config->pipe_bpp);
2148                 pipe_config->dsc.slice_count =
2149                         drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
2150                                                         true);
2151         } else {
2152                 u16 dsc_max_output_bpp;
2153                 u8 dsc_dp_slice_count;
2154
2155                 dsc_max_output_bpp =
2156                         intel_dp_dsc_get_output_bpp(dev_priv,
2157                                                     pipe_config->port_clock,
2158                                                     pipe_config->lane_count,
2159                                                     adjusted_mode->crtc_clock,
2160                                                     adjusted_mode->crtc_hdisplay);
2161                 dsc_dp_slice_count =
2162                         intel_dp_dsc_get_slice_count(intel_dp,
2163                                                      adjusted_mode->crtc_clock,
2164                                                      adjusted_mode->crtc_hdisplay);
2165                 if (!dsc_max_output_bpp || !dsc_dp_slice_count) {
2166                         drm_dbg_kms(&dev_priv->drm,
2167                                     "Compressed BPP/Slice Count not supported\n");
2168                         return -EINVAL;
2169                 }
2170                 pipe_config->dsc.compressed_bpp = min_t(u16,
2171                                                                dsc_max_output_bpp >> 4,
2172                                                                pipe_config->pipe_bpp);
2173                 pipe_config->dsc.slice_count = dsc_dp_slice_count;
2174         }
2175         /*
2176          * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
2177          * is greater than the maximum Cdclock and if slice count is even
2178          * then we need to use 2 VDSC instances.
2179          */
2180         if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq) {
2181                 if (pipe_config->dsc.slice_count > 1) {
2182                         pipe_config->dsc.dsc_split = true;
2183                 } else {
2184                         drm_dbg_kms(&dev_priv->drm,
2185                                     "Cannot split stream to use 2 VDSC instances\n");
2186                         return -EINVAL;
2187                 }
2188         }
2189
2190         ret = intel_dp_dsc_compute_params(&dig_port->base, pipe_config);
2191         if (ret < 0) {
2192                 drm_dbg_kms(&dev_priv->drm,
2193                             "Cannot compute valid DSC parameters for Input Bpp = %d "
2194                             "Compressed BPP = %d\n",
2195                             pipe_config->pipe_bpp,
2196                             pipe_config->dsc.compressed_bpp);
2197                 return ret;
2198         }
2199
2200         pipe_config->dsc.compression_enable = true;
2201         drm_dbg_kms(&dev_priv->drm, "DP DSC computed with Input Bpp = %d "
2202                     "Compressed Bpp = %d Slice Count = %d\n",
2203                     pipe_config->pipe_bpp,
2204                     pipe_config->dsc.compressed_bpp,
2205                     pipe_config->dsc.slice_count);
2206
2207         return 0;
2208 }
2209
2210 int intel_dp_min_bpp(const struct intel_crtc_state *crtc_state)
2211 {
2212         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB)
2213                 return 6 * 3;
2214         else
2215                 return 8 * 3;
2216 }
2217
2218 static int
2219 intel_dp_compute_link_config(struct intel_encoder *encoder,
2220                              struct intel_crtc_state *pipe_config,
2221                              struct drm_connector_state *conn_state)
2222 {
2223         struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2224         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2225         struct link_config_limits limits;
2226         int common_len;
2227         int ret;
2228
2229         common_len = intel_dp_common_len_rate_limit(intel_dp,
2230                                                     intel_dp->max_link_rate);
2231
2232         /* No common link rates between source and sink */
2233         drm_WARN_ON(encoder->base.dev, common_len <= 0);
2234
2235         limits.min_clock = 0;
2236         limits.max_clock = common_len - 1;
2237
2238         limits.min_lane_count = 1;
2239         limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
2240
2241         limits.min_bpp = intel_dp_min_bpp(pipe_config);
2242         limits.max_bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
2243
2244         if (intel_dp_is_edp(intel_dp)) {
2245                 /*
2246                  * Use the maximum clock and number of lanes the eDP panel
2247                  * advertizes being capable of. The panels are generally
2248                  * designed to support only a single clock and lane
2249                  * configuration, and typically these values correspond to the
2250                  * native resolution of the panel.
2251                  */
2252                 limits.min_lane_count = limits.max_lane_count;
2253                 limits.min_clock = limits.max_clock;
2254         }
2255
2256         intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);
2257
2258         DRM_DEBUG_KMS("DP link computation with max lane count %i "
2259                       "max rate %d max bpp %d pixel clock %iKHz\n",
2260                       limits.max_lane_count,
2261                       intel_dp->common_rates[limits.max_clock],
2262                       limits.max_bpp, adjusted_mode->crtc_clock);
2263
2264         /*
2265          * Optimize for slow and wide. This is the place to add alternative
2266          * optimization policy.
2267          */
2268         ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config, &limits);
2269
2270         /* enable compression if the mode doesn't fit available BW */
2271         DRM_DEBUG_KMS("Force DSC en = %d\n", intel_dp->force_dsc_en);
2272         if (ret || intel_dp->force_dsc_en) {
2273                 ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,
2274                                                   conn_state, &limits);
2275                 if (ret < 0)
2276                         return ret;
2277         }
2278
2279         if (pipe_config->dsc.compression_enable) {
2280                 DRM_DEBUG_KMS("DP lane count %d clock %d Input bpp %d Compressed bpp %d\n",
2281                               pipe_config->lane_count, pipe_config->port_clock,
2282                               pipe_config->pipe_bpp,
2283                               pipe_config->dsc.compressed_bpp);
2284
2285                 DRM_DEBUG_KMS("DP link rate required %i available %i\n",
2286                               intel_dp_link_required(adjusted_mode->crtc_clock,
2287                                                      pipe_config->dsc.compressed_bpp),
2288                               intel_dp_max_data_rate(pipe_config->port_clock,
2289                                                      pipe_config->lane_count));
2290         } else {
2291                 DRM_DEBUG_KMS("DP lane count %d clock %d bpp %d\n",
2292                               pipe_config->lane_count, pipe_config->port_clock,
2293                               pipe_config->pipe_bpp);
2294
2295                 DRM_DEBUG_KMS("DP link rate required %i available %i\n",
2296                               intel_dp_link_required(adjusted_mode->crtc_clock,
2297                                                      pipe_config->pipe_bpp),
2298                               intel_dp_max_data_rate(pipe_config->port_clock,
2299                                                      pipe_config->lane_count));
2300         }
2301         return 0;
2302 }
2303
2304 static int
2305 intel_dp_ycbcr420_config(struct intel_dp *intel_dp,
2306                          struct drm_connector *connector,
2307                          struct intel_crtc_state *crtc_state)
2308 {
2309         const struct drm_display_info *info = &connector->display_info;
2310         const struct drm_display_mode *adjusted_mode =
2311                 &crtc_state->hw.adjusted_mode;
2312         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2313         int ret;
2314
2315         if (!drm_mode_is_420_only(info, adjusted_mode) ||
2316             !intel_dp_get_colorimetry_status(intel_dp) ||
2317             !connector->ycbcr_420_allowed)
2318                 return 0;
2319
2320         crtc_state->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
2321
2322         /* YCBCR 420 output conversion needs a scaler */
2323         ret = skl_update_scaler_crtc(crtc_state);
2324         if (ret) {
2325                 DRM_DEBUG_KMS("Scaler allocation for output failed\n");
2326                 return ret;
2327         }
2328
2329         intel_pch_panel_fitting(crtc, crtc_state, DRM_MODE_SCALE_FULLSCREEN);
2330
2331         return 0;
2332 }
2333
2334 bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
2335                                   const struct drm_connector_state *conn_state)
2336 {
2337         const struct intel_digital_connector_state *intel_conn_state =
2338                 to_intel_digital_connector_state(conn_state);
2339         const struct drm_display_mode *adjusted_mode =
2340                 &crtc_state->hw.adjusted_mode;
2341
2342         /*
2343          * Our YCbCr output is always limited range.
2344          * crtc_state->limited_color_range only applies to RGB,
2345          * and it must never be set for YCbCr or we risk setting
2346          * some conflicting bits in PIPECONF which will mess up
2347          * the colors on the monitor.
2348          */
2349         if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
2350                 return false;
2351
2352         if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
2353                 /*
2354                  * See:
2355                  * CEA-861-E - 5.1 Default Encoding Parameters
2356                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
2357                  */
2358                 return crtc_state->pipe_bpp != 18 &&
2359                         drm_default_rgb_quant_range(adjusted_mode) ==
2360                         HDMI_QUANTIZATION_RANGE_LIMITED;
2361         } else {
2362                 return intel_conn_state->broadcast_rgb ==
2363                         INTEL_BROADCAST_RGB_LIMITED;
2364         }
2365 }
2366
2367 static bool intel_dp_port_has_audio(struct drm_i915_private *dev_priv,
2368                                     enum port port)
2369 {
2370         if (IS_G4X(dev_priv))
2371                 return false;
2372         if (INTEL_GEN(dev_priv) < 12 && port == PORT_A)
2373                 return false;
2374
2375         return true;
2376 }
2377
2378 int
2379 intel_dp_compute_config(struct intel_encoder *encoder,
2380                         struct intel_crtc_state *pipe_config,
2381                         struct drm_connector_state *conn_state)
2382 {
2383         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2384         struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2385         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2386         struct intel_lspcon *lspcon = enc_to_intel_lspcon(encoder);
2387         enum port port = encoder->port;
2388         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
2389         struct intel_connector *intel_connector = intel_dp->attached_connector;
2390         struct intel_digital_connector_state *intel_conn_state =
2391                 to_intel_digital_connector_state(conn_state);
2392         bool constant_n = drm_dp_has_quirk(&intel_dp->desc,
2393                                            DP_DPCD_QUIRK_CONSTANT_N);
2394         int ret = 0, output_bpp;
2395
2396         if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
2397                 pipe_config->has_pch_encoder = true;
2398
2399         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
2400
2401         if (lspcon->active)
2402                 lspcon_ycbcr420_config(&intel_connector->base, pipe_config);
2403         else
2404                 ret = intel_dp_ycbcr420_config(intel_dp, &intel_connector->base,
2405                                                pipe_config);
2406
2407         if (ret)
2408                 return ret;
2409
2410         pipe_config->has_drrs = false;
2411         if (!intel_dp_port_has_audio(dev_priv, port))
2412                 pipe_config->has_audio = false;
2413         else if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
2414                 pipe_config->has_audio = intel_dp->has_audio;
2415         else
2416                 pipe_config->has_audio = intel_conn_state->force_audio == HDMI_AUDIO_ON;
2417
2418         if (intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
2419                 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
2420                                        adjusted_mode);
2421
2422                 if (INTEL_GEN(dev_priv) >= 9) {
2423                         ret = skl_update_scaler_crtc(pipe_config);
2424                         if (ret)
2425                                 return ret;
2426                 }
2427
2428                 if (HAS_GMCH(dev_priv))
2429                         intel_gmch_panel_fitting(intel_crtc, pipe_config,
2430                                                  conn_state->scaling_mode);
2431                 else
2432                         intel_pch_panel_fitting(intel_crtc, pipe_config,
2433                                                 conn_state->scaling_mode);
2434         }
2435
2436         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
2437                 return -EINVAL;
2438
2439         if (HAS_GMCH(dev_priv) &&
2440             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
2441                 return -EINVAL;
2442
2443         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2444                 return -EINVAL;
2445
2446         if (intel_dp_hdisplay_bad(dev_priv, adjusted_mode->crtc_hdisplay))
2447                 return -EINVAL;
2448
2449         ret = intel_dp_compute_link_config(encoder, pipe_config, conn_state);
2450         if (ret < 0)
2451                 return ret;
2452
2453         pipe_config->limited_color_range =
2454                 intel_dp_limited_color_range(pipe_config, conn_state);
2455
2456         if (pipe_config->dsc.compression_enable)
2457                 output_bpp = pipe_config->dsc.compressed_bpp;
2458         else
2459                 output_bpp = intel_dp_output_bpp(pipe_config, pipe_config->pipe_bpp);
2460
2461         intel_link_compute_m_n(output_bpp,
2462                                pipe_config->lane_count,
2463                                adjusted_mode->crtc_clock,
2464                                pipe_config->port_clock,
2465                                &pipe_config->dp_m_n,
2466                                constant_n, pipe_config->fec_enable);
2467
2468         if (intel_connector->panel.downclock_mode != NULL &&
2469                 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
2470                         pipe_config->has_drrs = true;
2471                         intel_link_compute_m_n(output_bpp,
2472                                                pipe_config->lane_count,
2473                                                intel_connector->panel.downclock_mode->clock,
2474                                                pipe_config->port_clock,
2475                                                &pipe_config->dp_m2_n2,
2476                                                constant_n, pipe_config->fec_enable);
2477         }
2478
2479         if (!HAS_DDI(dev_priv))
2480                 intel_dp_set_clock(encoder, pipe_config);
2481
2482         intel_psr_compute_config(intel_dp, pipe_config);
2483
2484         return 0;
2485 }
2486
2487 void intel_dp_set_link_params(struct intel_dp *intel_dp,
2488                               int link_rate, u8 lane_count,
2489                               bool link_mst)
2490 {
2491         intel_dp->link_trained = false;
2492         intel_dp->link_rate = link_rate;
2493         intel_dp->lane_count = lane_count;
2494         intel_dp->link_mst = link_mst;
2495 }
2496
2497 static void intel_dp_prepare(struct intel_encoder *encoder,
2498                              const struct intel_crtc_state *pipe_config)
2499 {
2500         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2501         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2502         enum port port = encoder->port;
2503         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
2504         const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2505
2506         intel_dp_set_link_params(intel_dp, pipe_config->port_clock,
2507                                  pipe_config->lane_count,
2508                                  intel_crtc_has_type(pipe_config,
2509                                                      INTEL_OUTPUT_DP_MST));
2510
2511         intel_dp->regs.dp_tp_ctl = DP_TP_CTL(port);
2512         intel_dp->regs.dp_tp_status = DP_TP_STATUS(port);
2513
2514         /*
2515          * There are four kinds of DP registers:
2516          *
2517          *      IBX PCH
2518          *      SNB CPU
2519          *      IVB CPU
2520          *      CPT PCH
2521          *
2522          * IBX PCH and CPU are the same for almost everything,
2523          * except that the CPU DP PLL is configured in this
2524          * register
2525          *
2526          * CPT PCH is quite different, having many bits moved
2527          * to the TRANS_DP_CTL register instead. That
2528          * configuration happens (oddly) in ilk_pch_enable
2529          */
2530
2531         /* Preserve the BIOS-computed detected bit. This is
2532          * supposed to be read-only.
2533          */
2534         intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg) & DP_DETECTED;
2535
2536         /* Handle DP bits in common between all three register formats */
2537         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
2538         intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count);
2539
2540         /* Split out the IBX/CPU vs CPT settings */
2541
2542         if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
2543                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
2544                         intel_dp->DP |= DP_SYNC_HS_HIGH;
2545                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
2546                         intel_dp->DP |= DP_SYNC_VS_HIGH;
2547                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
2548
2549                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2550                         intel_dp->DP |= DP_ENHANCED_FRAMING;
2551
2552                 intel_dp->DP |= DP_PIPE_SEL_IVB(crtc->pipe);
2553         } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2554                 u32 trans_dp;
2555
2556                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
2557
2558                 trans_dp = intel_de_read(dev_priv, TRANS_DP_CTL(crtc->pipe));
2559                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2560                         trans_dp |= TRANS_DP_ENH_FRAMING;
2561                 else
2562                         trans_dp &= ~TRANS_DP_ENH_FRAMING;
2563                 intel_de_write(dev_priv, TRANS_DP_CTL(crtc->pipe), trans_dp);
2564         } else {
2565                 if (IS_G4X(dev_priv) && pipe_config->limited_color_range)
2566                         intel_dp->DP |= DP_COLOR_RANGE_16_235;
2567
2568                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
2569                         intel_dp->DP |= DP_SYNC_HS_HIGH;
2570                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
2571                         intel_dp->DP |= DP_SYNC_VS_HIGH;
2572                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
2573
2574                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2575                         intel_dp->DP |= DP_ENHANCED_FRAMING;
2576
2577                 if (IS_CHERRYVIEW(dev_priv))
2578                         intel_dp->DP |= DP_PIPE_SEL_CHV(crtc->pipe);
2579                 else
2580                         intel_dp->DP |= DP_PIPE_SEL(crtc->pipe);
2581         }
2582 }
2583
2584 #define IDLE_ON_MASK            (PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
2585 #define IDLE_ON_VALUE           (PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
2586
2587 #define IDLE_OFF_MASK           (PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
2588 #define IDLE_OFF_VALUE          (0     | PP_SEQUENCE_NONE | 0                     | 0)
2589
2590 #define IDLE_CYCLE_MASK         (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
2591 #define IDLE_CYCLE_VALUE        (0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
2592
2593 static void intel_pps_verify_state(struct intel_dp *intel_dp);
2594
2595 static void wait_panel_status(struct intel_dp *intel_dp,
2596                                        u32 mask,
2597                                        u32 value)
2598 {
2599         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2600         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2601
2602         lockdep_assert_held(&dev_priv->pps_mutex);
2603
2604         intel_pps_verify_state(intel_dp);
2605
2606         pp_stat_reg = _pp_stat_reg(intel_dp);
2607         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2608
2609         drm_dbg_kms(&dev_priv->drm,
2610                     "mask %08x value %08x status %08x control %08x\n",
2611                     mask, value,
2612                     intel_de_read(dev_priv, pp_stat_reg),
2613                     intel_de_read(dev_priv, pp_ctrl_reg));
2614
2615         if (intel_de_wait_for_register(dev_priv, pp_stat_reg,
2616                                        mask, value, 5000))
2617                 drm_err(&dev_priv->drm,
2618                         "Panel status timeout: status %08x control %08x\n",
2619                         intel_de_read(dev_priv, pp_stat_reg),
2620                         intel_de_read(dev_priv, pp_ctrl_reg));
2621
2622         drm_dbg_kms(&dev_priv->drm, "Wait complete\n");
2623 }
2624
2625 static void wait_panel_on(struct intel_dp *intel_dp)
2626 {
2627         DRM_DEBUG_KMS("Wait for panel power on\n");
2628         wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
2629 }
2630
2631 static void wait_panel_off(struct intel_dp *intel_dp)
2632 {
2633         DRM_DEBUG_KMS("Wait for panel power off time\n");
2634         wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
2635 }
2636
2637 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
2638 {
2639         ktime_t panel_power_on_time;
2640         s64 panel_power_off_duration;
2641
2642         DRM_DEBUG_KMS("Wait for panel power cycle\n");
2643
2644         /* take the difference of currrent time and panel power off time
2645          * and then make panel wait for t11_t12 if needed. */
2646         panel_power_on_time = ktime_get_boottime();
2647         panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
2648
2649         /* When we disable the VDD override bit last we have to do the manual
2650          * wait. */
2651         if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
2652                 wait_remaining_ms_from_jiffies(jiffies,
2653                                        intel_dp->panel_power_cycle_delay - panel_power_off_duration);
2654
2655         wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
2656 }
2657
2658 static void wait_backlight_on(struct intel_dp *intel_dp)
2659 {
2660         wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
2661                                        intel_dp->backlight_on_delay);
2662 }
2663
2664 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
2665 {
2666         wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
2667                                        intel_dp->backlight_off_delay);
2668 }
2669
2670 /* Read the current pp_control value, unlocking the register if it
2671  * is locked
2672  */
2673
2674 static  u32 ilk_get_pp_control(struct intel_dp *intel_dp)
2675 {
2676         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2677         u32 control;
2678
2679         lockdep_assert_held(&dev_priv->pps_mutex);
2680
2681         control = intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp));
2682         if (WARN_ON(!HAS_DDI(dev_priv) &&
2683                     (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) {
2684                 control &= ~PANEL_UNLOCK_MASK;
2685                 control |= PANEL_UNLOCK_REGS;
2686         }
2687         return control;
2688 }
2689
2690 /*
2691  * Must be paired with edp_panel_vdd_off().
2692  * Must hold pps_mutex around the whole on/off sequence.
2693  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2694  */
2695 static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
2696 {
2697         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2698         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2699         u32 pp;
2700         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2701         bool need_to_disable = !intel_dp->want_panel_vdd;
2702
2703         lockdep_assert_held(&dev_priv->pps_mutex);
2704
2705         if (!intel_dp_is_edp(intel_dp))
2706                 return false;
2707
2708         cancel_delayed_work(&intel_dp->panel_vdd_work);
2709         intel_dp->want_panel_vdd = true;
2710
2711         if (edp_have_panel_vdd(intel_dp))
2712                 return need_to_disable;
2713
2714         intel_display_power_get(dev_priv,
2715                                 intel_aux_power_domain(intel_dig_port));
2716
2717         drm_dbg_kms(&dev_priv->drm, "Turning [ENCODER:%d:%s] VDD on\n",
2718                     intel_dig_port->base.base.base.id,
2719                     intel_dig_port->base.base.name);
2720
2721         if (!edp_have_panel_power(intel_dp))
2722                 wait_panel_power_cycle(intel_dp);
2723
2724         pp = ilk_get_pp_control(intel_dp);
2725         pp |= EDP_FORCE_VDD;
2726
2727         pp_stat_reg = _pp_stat_reg(intel_dp);
2728         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2729
2730         intel_de_write(dev_priv, pp_ctrl_reg, pp);
2731         intel_de_posting_read(dev_priv, pp_ctrl_reg);
2732         drm_dbg_kms(&dev_priv->drm, "PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2733                     intel_de_read(dev_priv, pp_stat_reg),
2734                     intel_de_read(dev_priv, pp_ctrl_reg));
2735         /*
2736          * If the panel wasn't on, delay before accessing aux channel
2737          */
2738         if (!edp_have_panel_power(intel_dp)) {
2739                 drm_dbg_kms(&dev_priv->drm,
2740                             "[ENCODER:%d:%s] panel power wasn't enabled\n",
2741                             intel_dig_port->base.base.base.id,
2742                             intel_dig_port->base.base.name);
2743                 msleep(intel_dp->panel_power_up_delay);
2744         }
2745
2746         return need_to_disable;
2747 }
2748
2749 /*
2750  * Must be paired with intel_edp_panel_vdd_off() or
2751  * intel_edp_panel_off().
2752  * Nested calls to these functions are not allowed since
2753  * we drop the lock. Caller must use some higher level
2754  * locking to prevent nested calls from other threads.
2755  */
2756 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
2757 {
2758         intel_wakeref_t wakeref;
2759         bool vdd;
2760
2761         if (!intel_dp_is_edp(intel_dp))
2762                 return;
2763
2764         vdd = false;
2765         with_pps_lock(intel_dp, wakeref)
2766                 vdd = edp_panel_vdd_on(intel_dp);
2767         I915_STATE_WARN(!vdd, "[ENCODER:%d:%s] VDD already requested on\n",
2768                         dp_to_dig_port(intel_dp)->base.base.base.id,
2769                         dp_to_dig_port(intel_dp)->base.base.name);
2770 }
2771
2772 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
2773 {
2774         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2775         struct intel_digital_port *intel_dig_port =
2776                 dp_to_dig_port(intel_dp);
2777         u32 pp;
2778         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2779
2780         lockdep_assert_held(&dev_priv->pps_mutex);
2781
2782         WARN_ON(intel_dp->want_panel_vdd);
2783
2784         if (!edp_have_panel_vdd(intel_dp))
2785                 return;
2786
2787         drm_dbg_kms(&dev_priv->drm, "Turning [ENCODER:%d:%s] VDD off\n",
2788                     intel_dig_port->base.base.base.id,
2789                     intel_dig_port->base.base.name);
2790
2791         pp = ilk_get_pp_control(intel_dp);
2792         pp &= ~EDP_FORCE_VDD;
2793
2794         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2795         pp_stat_reg = _pp_stat_reg(intel_dp);
2796
2797         intel_de_write(dev_priv, pp_ctrl_reg, pp);
2798         intel_de_posting_read(dev_priv, pp_ctrl_reg);
2799
2800         /* Make sure sequencer is idle before allowing subsequent activity */
2801         drm_dbg_kms(&dev_priv->drm, "PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2802                     intel_de_read(dev_priv, pp_stat_reg),
2803                     intel_de_read(dev_priv, pp_ctrl_reg));
2804
2805         if ((pp & PANEL_POWER_ON) == 0)
2806                 intel_dp->panel_power_off_time = ktime_get_boottime();
2807
2808         intel_display_power_put_unchecked(dev_priv,
2809                                           intel_aux_power_domain(intel_dig_port));
2810 }
2811
2812 static void edp_panel_vdd_work(struct work_struct *__work)
2813 {
2814         struct intel_dp *intel_dp =
2815                 container_of(to_delayed_work(__work),
2816                              struct intel_dp, panel_vdd_work);
2817         intel_wakeref_t wakeref;
2818
2819         with_pps_lock(intel_dp, wakeref) {
2820                 if (!intel_dp->want_panel_vdd)
2821                         edp_panel_vdd_off_sync(intel_dp);
2822         }
2823 }
2824
2825 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
2826 {
2827         unsigned long delay;
2828
2829         /*
2830          * Queue the timer to fire a long time from now (relative to the power
2831          * down delay) to keep the panel power up across a sequence of
2832          * operations.
2833          */
2834         delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
2835         schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
2836 }
2837
2838 /*
2839  * Must be paired with edp_panel_vdd_on().
2840  * Must hold pps_mutex around the whole on/off sequence.
2841  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2842  */
2843 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
2844 {
2845         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2846
2847         lockdep_assert_held(&dev_priv->pps_mutex);
2848
2849         if (!intel_dp_is_edp(intel_dp))
2850                 return;
2851
2852         I915_STATE_WARN(!intel_dp->want_panel_vdd, "[ENCODER:%d:%s] VDD not forced on",
2853                         dp_to_dig_port(intel_dp)->base.base.base.id,
2854                         dp_to_dig_port(intel_dp)->base.base.name);
2855
2856         intel_dp->want_panel_vdd = false;
2857
2858         if (sync)
2859                 edp_panel_vdd_off_sync(intel_dp);
2860         else
2861                 edp_panel_vdd_schedule_off(intel_dp);
2862 }
2863
2864 static void edp_panel_on(struct intel_dp *intel_dp)
2865 {
2866         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2867         u32 pp;
2868         i915_reg_t pp_ctrl_reg;
2869
2870         lockdep_assert_held(&dev_priv->pps_mutex);
2871
2872         if (!intel_dp_is_edp(intel_dp))
2873                 return;
2874
2875         drm_dbg_kms(&dev_priv->drm, "Turn [ENCODER:%d:%s] panel power on\n",
2876                     dp_to_dig_port(intel_dp)->base.base.base.id,
2877                     dp_to_dig_port(intel_dp)->base.base.name);
2878
2879         if (WARN(edp_have_panel_power(intel_dp),
2880                  "[ENCODER:%d:%s] panel power already on\n",
2881                  dp_to_dig_port(intel_dp)->base.base.base.id,
2882                  dp_to_dig_port(intel_dp)->base.base.name))
2883                 return;
2884
2885         wait_panel_power_cycle(intel_dp);
2886
2887         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2888         pp = ilk_get_pp_control(intel_dp);
2889         if (IS_GEN(dev_priv, 5)) {
2890                 /* ILK workaround: disable reset around power sequence */
2891                 pp &= ~PANEL_POWER_RESET;
2892                 intel_de_write(dev_priv, pp_ctrl_reg, pp);
2893                 intel_de_posting_read(dev_priv, pp_ctrl_reg);
2894         }
2895
2896         pp |= PANEL_POWER_ON;
2897         if (!IS_GEN(dev_priv, 5))
2898                 pp |= PANEL_POWER_RESET;
2899
2900         intel_de_write(dev_priv, pp_ctrl_reg, pp);
2901         intel_de_posting_read(dev_priv, pp_ctrl_reg);
2902
2903         wait_panel_on(intel_dp);
2904         intel_dp->last_power_on = jiffies;
2905
2906         if (IS_GEN(dev_priv, 5)) {
2907                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
2908                 intel_de_write(dev_priv, pp_ctrl_reg, pp);
2909                 intel_de_posting_read(dev_priv, pp_ctrl_reg);
2910         }
2911 }
2912
2913 void intel_edp_panel_on(struct intel_dp *intel_dp)
2914 {
2915         intel_wakeref_t wakeref;
2916
2917         if (!intel_dp_is_edp(intel_dp))
2918                 return;
2919
2920         with_pps_lock(intel_dp, wakeref)
2921                 edp_panel_on(intel_dp);
2922 }
2923
2924
2925 static void edp_panel_off(struct intel_dp *intel_dp)
2926 {
2927         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2928         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2929         u32 pp;
2930         i915_reg_t pp_ctrl_reg;
2931
2932         lockdep_assert_held(&dev_priv->pps_mutex);
2933
2934         if (!intel_dp_is_edp(intel_dp))
2935                 return;
2936
2937         drm_dbg_kms(&dev_priv->drm, "Turn [ENCODER:%d:%s] panel power off\n",
2938                     dig_port->base.base.base.id, dig_port->base.base.name);
2939
2940         WARN(!intel_dp->want_panel_vdd, "Need [ENCODER:%d:%s] VDD to turn off panel\n",
2941              dig_port->base.base.base.id, dig_port->base.base.name);
2942
2943         pp = ilk_get_pp_control(intel_dp);
2944         /* We need to switch off panel power _and_ force vdd, for otherwise some
2945          * panels get very unhappy and cease to work. */
2946         pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
2947                 EDP_BLC_ENABLE);
2948
2949         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2950
2951         intel_dp->want_panel_vdd = false;
2952
2953         intel_de_write(dev_priv, pp_ctrl_reg, pp);
2954         intel_de_posting_read(dev_priv, pp_ctrl_reg);
2955
2956         wait_panel_off(intel_dp);
2957         intel_dp->panel_power_off_time = ktime_get_boottime();
2958
2959         /* We got a reference when we enabled the VDD. */
2960         intel_display_power_put_unchecked(dev_priv, intel_aux_power_domain(dig_port));
2961 }
2962
2963 void intel_edp_panel_off(struct intel_dp *intel_dp)
2964 {
2965         intel_wakeref_t wakeref;
2966
2967         if (!intel_dp_is_edp(intel_dp))
2968                 return;
2969
2970         with_pps_lock(intel_dp, wakeref)
2971                 edp_panel_off(intel_dp);
2972 }
2973
2974 /* Enable backlight in the panel power control. */
2975 static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
2976 {
2977         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2978         intel_wakeref_t wakeref;
2979
2980         /*
2981          * If we enable the backlight right away following a panel power
2982          * on, we may see slight flicker as the panel syncs with the eDP
2983          * link.  So delay a bit to make sure the image is solid before
2984          * allowing it to appear.
2985          */
2986         wait_backlight_on(intel_dp);
2987
2988         with_pps_lock(intel_dp, wakeref) {
2989                 i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2990                 u32 pp;
2991
2992                 pp = ilk_get_pp_control(intel_dp);
2993                 pp |= EDP_BLC_ENABLE;
2994
2995                 intel_de_write(dev_priv, pp_ctrl_reg, pp);
2996                 intel_de_posting_read(dev_priv, pp_ctrl_reg);
2997         }
2998 }
2999
3000 /* Enable backlight PWM and backlight PP control. */
3001 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
3002                             const struct drm_connector_state *conn_state)
3003 {
3004         struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(conn_state->best_encoder));
3005
3006         if (!intel_dp_is_edp(intel_dp))
3007                 return;
3008
3009         DRM_DEBUG_KMS("\n");
3010
3011         intel_panel_enable_backlight(crtc_state, conn_state);
3012         _intel_edp_backlight_on(intel_dp);
3013 }
3014
3015 /* Disable backlight in the panel power control. */
3016 static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
3017 {
3018         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3019         intel_wakeref_t wakeref;
3020
3021         if (!intel_dp_is_edp(intel_dp))
3022                 return;
3023
3024         with_pps_lock(intel_dp, wakeref) {
3025                 i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
3026                 u32 pp;
3027
3028                 pp = ilk_get_pp_control(intel_dp);
3029                 pp &= ~EDP_BLC_ENABLE;
3030
3031                 intel_de_write(dev_priv, pp_ctrl_reg, pp);
3032                 intel_de_posting_read(dev_priv, pp_ctrl_reg);
3033         }
3034
3035         intel_dp->last_backlight_off = jiffies;
3036         edp_wait_backlight_off(intel_dp);
3037 }
3038
3039 /* Disable backlight PP control and backlight PWM. */
3040 void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
3041 {
3042         struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(old_conn_state->best_encoder));
3043
3044         if (!intel_dp_is_edp(intel_dp))
3045                 return;
3046
3047         DRM_DEBUG_KMS("\n");
3048
3049         _intel_edp_backlight_off(intel_dp);
3050         intel_panel_disable_backlight(old_conn_state);
3051 }
3052
3053 /*
3054  * Hook for controlling the panel power control backlight through the bl_power
3055  * sysfs attribute. Take care to handle multiple calls.
3056  */
3057 static void intel_edp_backlight_power(struct intel_connector *connector,
3058                                       bool enable)
3059 {
3060         struct intel_dp *intel_dp = intel_attached_dp(connector);
3061         intel_wakeref_t wakeref;
3062         bool is_enabled;
3063
3064         is_enabled = false;
3065         with_pps_lock(intel_dp, wakeref)
3066                 is_enabled = ilk_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
3067         if (is_enabled == enable)
3068                 return;
3069
3070         DRM_DEBUG_KMS("panel power control backlight %s\n",
3071                       enable ? "enable" : "disable");
3072
3073         if (enable)
3074                 _intel_edp_backlight_on(intel_dp);
3075         else
3076                 _intel_edp_backlight_off(intel_dp);
3077 }
3078
3079 static void assert_dp_port(struct intel_dp *intel_dp, bool state)
3080 {
3081         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3082         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3083         bool cur_state = intel_de_read(dev_priv, intel_dp->output_reg) & DP_PORT_EN;
3084
3085         I915_STATE_WARN(cur_state != state,
3086                         "[ENCODER:%d:%s] state assertion failure (expected %s, current %s)\n",
3087                         dig_port->base.base.base.id, dig_port->base.base.name,
3088                         onoff(state), onoff(cur_state));
3089 }
3090 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
3091
3092 static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
3093 {
3094         bool cur_state = intel_de_read(dev_priv, DP_A) & DP_PLL_ENABLE;
3095
3096         I915_STATE_WARN(cur_state != state,
3097                         "eDP PLL state assertion failure (expected %s, current %s)\n",
3098                         onoff(state), onoff(cur_state));
3099 }
3100 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
3101 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
3102
3103 static void ilk_edp_pll_on(struct intel_dp *intel_dp,
3104                            const struct intel_crtc_state *pipe_config)
3105 {
3106         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
3107         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3108
3109         assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder);
3110         assert_dp_port_disabled(intel_dp);
3111         assert_edp_pll_disabled(dev_priv);
3112
3113         drm_dbg_kms(&dev_priv->drm, "enabling eDP PLL for clock %d\n",
3114                     pipe_config->port_clock);
3115
3116         intel_dp->DP &= ~DP_PLL_FREQ_MASK;
3117
3118         if (pipe_config->port_clock == 162000)
3119                 intel_dp->DP |= DP_PLL_FREQ_162MHZ;
3120         else
3121                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
3122
3123         intel_de_write(dev_priv, DP_A, intel_dp->DP);
3124         intel_de_posting_read(dev_priv, DP_A);
3125         udelay(500);
3126
3127         /*
3128          * [DevILK] Work around required when enabling DP PLL
3129          * while a pipe is enabled going to FDI:
3130          * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
3131          * 2. Program DP PLL enable
3132          */
3133         if (IS_GEN(dev_priv, 5))
3134                 intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe);
3135
3136         intel_dp->DP |= DP_PLL_ENABLE;
3137
3138         intel_de_write(dev_priv, DP_A, intel_dp->DP);
3139         intel_de_posting_read(dev_priv, DP_A);
3140         udelay(200);
3141 }
3142
3143 static void ilk_edp_pll_off(struct intel_dp *intel_dp,
3144                             const struct intel_crtc_state *old_crtc_state)
3145 {
3146         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
3147         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3148
3149         assert_pipe_disabled(dev_priv, old_crtc_state->cpu_transcoder);
3150         assert_dp_port_disabled(intel_dp);
3151         assert_edp_pll_enabled(dev_priv);
3152
3153         drm_dbg_kms(&dev_priv->drm, "disabling eDP PLL\n");
3154
3155         intel_dp->DP &= ~DP_PLL_ENABLE;
3156
3157         intel_de_write(dev_priv, DP_A, intel_dp->DP);
3158         intel_de_posting_read(dev_priv, DP_A);
3159         udelay(200);
3160 }
3161
3162 static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)
3163 {
3164         /*
3165          * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus
3166          * be capable of signalling downstream hpd with a long pulse.
3167          * Whether or not that means D3 is safe to use is not clear,
3168          * but let's assume so until proven otherwise.
3169          *
3170          * FIXME should really check all downstream ports...
3171          */
3172         return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&
3173                 intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT &&
3174                 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
3175 }
3176
3177 void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
3178                                            const struct intel_crtc_state *crtc_state,
3179                                            bool enable)
3180 {
3181         int ret;
3182
3183         if (!crtc_state->dsc.compression_enable)
3184                 return;
3185
3186         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_DSC_ENABLE,
3187                                  enable ? DP_DECOMPRESSION_EN : 0);
3188         if (ret < 0)
3189                 DRM_DEBUG_KMS("Failed to %s sink decompression state\n",
3190                               enable ? "enable" : "disable");
3191 }
3192
3193 /* If the sink supports it, try to set the power state appropriately */
3194 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
3195 {
3196         int ret, i;
3197
3198         /* Should have a valid DPCD by this point */
3199         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
3200                 return;
3201
3202         if (mode != DRM_MODE_DPMS_ON) {
3203                 if (downstream_hpd_needs_d0(intel_dp))
3204                         return;
3205
3206                 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
3207                                          DP_SET_POWER_D3);
3208         } else {
3209                 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
3210
3211                 /*
3212                  * When turning on, we need to retry for 1ms to give the sink
3213                  * time to wake up.
3214                  */
3215                 for (i = 0; i < 3; i++) {
3216                         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
3217                                                  DP_SET_POWER_D0);
3218                         if (ret == 1)
3219                                 break;
3220                         msleep(1);
3221                 }
3222
3223                 if (ret == 1 && lspcon->active)
3224                         lspcon_wait_pcon_mode(lspcon);
3225         }
3226
3227         if (ret != 1)
3228                 DRM_DEBUG_KMS("failed to %s sink power state\n",
3229                               mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
3230 }
3231
3232 static bool cpt_dp_port_selected(struct drm_i915_private *dev_priv,
3233                                  enum port port, enum pipe *pipe)
3234 {
3235         enum pipe p;
3236
3237         for_each_pipe(dev_priv, p) {
3238                 u32 val = intel_de_read(dev_priv, TRANS_DP_CTL(p));
3239
3240                 if ((val & TRANS_DP_PORT_SEL_MASK) == TRANS_DP_PORT_SEL(port)) {
3241                         *pipe = p;
3242                         return true;
3243                 }
3244         }
3245
3246         drm_dbg_kms(&dev_priv->drm, "No pipe for DP port %c found\n",
3247                     port_name(port));
3248
3249         /* must initialize pipe to something for the asserts */
3250         *pipe = PIPE_A;
3251
3252         return false;
3253 }
3254
3255 bool intel_dp_port_enabled(struct drm_i915_private *dev_priv,
3256                            i915_reg_t dp_reg, enum port port,
3257                            enum pipe *pipe)
3258 {
3259         bool ret;
3260         u32 val;
3261
3262         val = intel_de_read(dev_priv, dp_reg);
3263
3264         ret = val & DP_PORT_EN;
3265
3266         /* asserts want to know the pipe even if the port is disabled */
3267         if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
3268                 *pipe = (val & DP_PIPE_SEL_MASK_IVB) >> DP_PIPE_SEL_SHIFT_IVB;
3269         else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
3270                 ret &= cpt_dp_port_selected(dev_priv, port, pipe);
3271         else if (IS_CHERRYVIEW(dev_priv))
3272                 *pipe = (val & DP_PIPE_SEL_MASK_CHV) >> DP_PIPE_SEL_SHIFT_CHV;
3273         else
3274                 *pipe = (val & DP_PIPE_SEL_MASK) >> DP_PIPE_SEL_SHIFT;
3275
3276         return ret;
3277 }
3278
3279 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
3280                                   enum pipe *pipe)
3281 {
3282         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3283         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3284         intel_wakeref_t wakeref;
3285         bool ret;
3286
3287         wakeref = intel_display_power_get_if_enabled(dev_priv,
3288                                                      encoder->power_domain);
3289         if (!wakeref)
3290                 return false;
3291
3292         ret = intel_dp_port_enabled(dev_priv, intel_dp->output_reg,
3293                                     encoder->port, pipe);
3294
3295         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
3296
3297         return ret;
3298 }
3299
3300 static void intel_dp_get_config(struct intel_encoder *encoder,
3301                                 struct intel_crtc_state *pipe_config)
3302 {
3303         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3304         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3305         u32 tmp, flags = 0;
3306         enum port port = encoder->port;
3307         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
3308
3309         if (encoder->type == INTEL_OUTPUT_EDP)
3310                 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
3311         else
3312                 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
3313
3314         tmp = intel_de_read(dev_priv, intel_dp->output_reg);
3315
3316         pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
3317
3318         if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
3319                 u32 trans_dp = intel_de_read(dev_priv,
3320                                              TRANS_DP_CTL(crtc->pipe));
3321
3322                 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
3323                         flags |= DRM_MODE_FLAG_PHSYNC;
3324                 else
3325                         flags |= DRM_MODE_FLAG_NHSYNC;
3326
3327                 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
3328                         flags |= DRM_MODE_FLAG_PVSYNC;
3329                 else
3330                         flags |= DRM_MODE_FLAG_NVSYNC;
3331         } else {
3332                 if (tmp & DP_SYNC_HS_HIGH)
3333                         flags |= DRM_MODE_FLAG_PHSYNC;
3334                 else
3335                         flags |= DRM_MODE_FLAG_NHSYNC;
3336
3337                 if (tmp & DP_SYNC_VS_HIGH)
3338                         flags |= DRM_MODE_FLAG_PVSYNC;
3339                 else
3340                         flags |= DRM_MODE_FLAG_NVSYNC;
3341         }
3342
3343         pipe_config->hw.adjusted_mode.flags |= flags;
3344
3345         if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235)
3346                 pipe_config->limited_color_range = true;
3347
3348         pipe_config->lane_count =
3349                 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
3350
3351         intel_dp_get_m_n(crtc, pipe_config);
3352
3353         if (port == PORT_A) {
3354                 if ((intel_de_read(dev_priv, DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
3355                         pipe_config->port_clock = 162000;
3356                 else
3357                         pipe_config->port_clock = 270000;
3358         }
3359
3360         pipe_config->hw.adjusted_mode.crtc_clock =
3361                 intel_dotclock_calculate(pipe_config->port_clock,
3362                                          &pipe_config->dp_m_n);
3363
3364         if (intel_dp_is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
3365             pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
3366                 /*
3367                  * This is a big fat ugly hack.
3368                  *
3369                  * Some machines in UEFI boot mode provide us a VBT that has 18
3370                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3371                  * unknown we fail to light up. Yet the same BIOS boots up with
3372                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3373                  * max, not what it tells us to use.
3374                  *
3375                  * Note: This will still be broken if the eDP panel is not lit
3376                  * up by the BIOS, and thus we can't get the mode at module
3377                  * load.
3378                  */
3379                 drm_dbg_kms(&dev_priv->drm,
3380                             "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3381                             pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
3382                 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
3383         }
3384 }
3385
3386 static void intel_disable_dp(struct intel_encoder *encoder,
3387                              const struct intel_crtc_state *old_crtc_state,
3388                              const struct drm_connector_state *old_conn_state)
3389 {
3390         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3391
3392         intel_dp->link_trained = false;
3393
3394         if (old_crtc_state->has_audio)
3395                 intel_audio_codec_disable(encoder,
3396                                           old_crtc_state, old_conn_state);
3397
3398         /* Make sure the panel is off before trying to change the mode. But also
3399          * ensure that we have vdd while we switch off the panel. */
3400         intel_edp_panel_vdd_on(intel_dp);
3401         intel_edp_backlight_off(old_conn_state);
3402         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
3403         intel_edp_panel_off(intel_dp);
3404 }
3405
3406 static void g4x_disable_dp(struct intel_encoder *encoder,
3407                            const struct intel_crtc_state *old_crtc_state,
3408                            const struct drm_connector_state *old_conn_state)
3409 {
3410         intel_disable_dp(encoder, old_crtc_state, old_conn_state);
3411 }
3412
3413 static void vlv_disable_dp(struct intel_encoder *encoder,
3414                            const struct intel_crtc_state *old_crtc_state,
3415                            const struct drm_connector_state *old_conn_state)
3416 {
3417         intel_disable_dp(encoder, old_crtc_state, old_conn_state);
3418 }
3419
3420 static void g4x_post_disable_dp(struct intel_encoder *encoder,
3421                                 const struct intel_crtc_state *old_crtc_state,
3422                                 const struct drm_connector_state *old_conn_state)
3423 {
3424         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3425         enum port port = encoder->port;
3426
3427         /*
3428          * Bspec does not list a specific disable sequence for g4x DP.
3429          * Follow the ilk+ sequence (disable pipe before the port) for
3430          * g4x DP as it does not suffer from underruns like the normal
3431          * g4x modeset sequence (disable pipe after the port).
3432          */
3433         intel_dp_link_down(encoder, old_crtc_state);
3434
3435         /* Only ilk+ has port A */
3436         if (port == PORT_A)
3437                 ilk_edp_pll_off(intel_dp, old_crtc_state);
3438 }
3439
3440 static void vlv_post_disable_dp(struct intel_encoder *encoder,
3441                                 const struct intel_crtc_state *old_crtc_state,
3442                                 const struct drm_connector_state *old_conn_state)
3443 {
3444         intel_dp_link_down(encoder, old_crtc_state);
3445 }
3446
3447 static void chv_post_disable_dp(struct intel_encoder *encoder,
3448                                 const struct intel_crtc_state *old_crtc_state,
3449                                 const struct drm_connector_state *old_conn_state)
3450 {
3451         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3452
3453         intel_dp_link_down(encoder, old_crtc_state);
3454
3455         vlv_dpio_get(dev_priv);
3456
3457         /* Assert data lane reset */
3458         chv_data_lane_soft_reset(encoder, old_crtc_state, true);
3459
3460         vlv_dpio_put(dev_priv);
3461 }
3462
3463 static void
3464 _intel_dp_set_link_train(struct intel_dp *intel_dp,
3465                          u32 *DP,
3466                          u8 dp_train_pat)
3467 {
3468         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3469         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3470         enum port port = intel_dig_port->base.port;
3471         u8 train_pat_mask = drm_dp_training_pattern_mask(intel_dp->dpcd);
3472
3473         if (dp_train_pat & train_pat_mask)
3474                 drm_dbg_kms(&dev_priv->drm,
3475                             "Using DP training pattern TPS%d\n",
3476                             dp_train_pat & train_pat_mask);
3477
3478         if (HAS_DDI(dev_priv)) {
3479                 u32 temp = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl);
3480
3481                 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
3482                         temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
3483                 else
3484                         temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
3485
3486                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3487                 switch (dp_train_pat & train_pat_mask) {
3488                 case DP_TRAINING_PATTERN_DISABLE:
3489                         temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
3490
3491                         break;
3492                 case DP_TRAINING_PATTERN_1:
3493                         temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
3494                         break;
3495                 case DP_TRAINING_PATTERN_2:
3496                         temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
3497                         break;
3498                 case DP_TRAINING_PATTERN_3:
3499                         temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
3500                         break;
3501                 case DP_TRAINING_PATTERN_4:
3502                         temp |= DP_TP_CTL_LINK_TRAIN_PAT4;
3503                         break;
3504                 }
3505                 intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, temp);
3506
3507         } else if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
3508                    (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
3509                 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
3510
3511                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
3512                 case DP_TRAINING_PATTERN_DISABLE:
3513                         *DP |= DP_LINK_TRAIN_OFF_CPT;
3514                         break;
3515                 case DP_TRAINING_PATTERN_1:
3516                         *DP |= DP_LINK_TRAIN_PAT_1_CPT;
3517                         break;
3518                 case DP_TRAINING_PATTERN_2:
3519                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
3520                         break;
3521                 case DP_TRAINING_PATTERN_3:
3522                         drm_dbg_kms(&dev_priv->drm,
3523                                     "TPS3 not supported, using TPS2 instead\n");
3524                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
3525                         break;
3526                 }
3527
3528         } else {
3529                 *DP &= ~DP_LINK_TRAIN_MASK;
3530
3531                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
3532                 case DP_TRAINING_PATTERN_DISABLE:
3533                         *DP |= DP_LINK_TRAIN_OFF;
3534                         break;
3535                 case DP_TRAINING_PATTERN_1:
3536                         *DP |= DP_LINK_TRAIN_PAT_1;
3537                         break;
3538                 case DP_TRAINING_PATTERN_2:
3539                         *DP |= DP_LINK_TRAIN_PAT_2;
3540                         break;
3541                 case DP_TRAINING_PATTERN_3:
3542                         drm_dbg_kms(&dev_priv->drm,
3543                                     "TPS3 not supported, using TPS2 instead\n");
3544                         *DP |= DP_LINK_TRAIN_PAT_2;
3545                         break;
3546                 }
3547         }
3548 }
3549
3550 static void intel_dp_enable_port(struct intel_dp *intel_dp,
3551                                  const struct intel_crtc_state *old_crtc_state)
3552 {
3553         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3554
3555         /* enable with pattern 1 (as per spec) */
3556
3557         intel_dp_program_link_training_pattern(intel_dp, DP_TRAINING_PATTERN_1);
3558
3559         /*
3560          * Magic for VLV/CHV. We _must_ first set up the register
3561          * without actually enabling the port, and then do another
3562          * write to enable the port. Otherwise link training will
3563          * fail when the power sequencer is freshly used for this port.
3564          */
3565         intel_dp->DP |= DP_PORT_EN;
3566         if (old_crtc_state->has_audio)
3567                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
3568
3569         intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
3570         intel_de_posting_read(dev_priv, intel_dp->output_reg);
3571 }
3572
3573 static void intel_enable_dp(struct intel_encoder *encoder,
3574                             const struct intel_crtc_state *pipe_config,
3575                             const struct drm_connector_state *conn_state)
3576 {
3577         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3578         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3579         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
3580         u32 dp_reg = intel_de_read(dev_priv, intel_dp->output_reg);
3581         enum pipe pipe = crtc->pipe;
3582         intel_wakeref_t wakeref;
3583
3584         if (WARN_ON(dp_reg & DP_PORT_EN))
3585                 return;
3586
3587         with_pps_lock(intel_dp, wakeref) {
3588                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3589                         vlv_init_panel_power_sequencer(encoder, pipe_config);
3590
3591                 intel_dp_enable_port(intel_dp, pipe_config);
3592
3593                 edp_panel_vdd_on(intel_dp);
3594                 edp_panel_on(intel_dp);
3595                 edp_panel_vdd_off(intel_dp, true);
3596         }
3597
3598         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3599                 unsigned int lane_mask = 0x0;
3600
3601                 if (IS_CHERRYVIEW(dev_priv))
3602                         lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count);
3603
3604                 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
3605                                     lane_mask);
3606         }
3607
3608         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
3609         intel_dp_start_link_train(intel_dp);
3610         intel_dp_stop_link_train(intel_dp);
3611
3612         if (pipe_config->has_audio) {
3613                 drm_dbg(&dev_priv->drm, "Enabling DP audio on pipe %c\n",
3614                         pipe_name(pipe));
3615                 intel_audio_codec_enable(encoder, pipe_config, conn_state);
3616         }
3617 }
3618
3619 static void g4x_enable_dp(struct intel_encoder *encoder,
3620                           const struct intel_crtc_state *pipe_config,
3621                           const struct drm_connector_state *conn_state)
3622 {
3623         intel_enable_dp(encoder, pipe_config, conn_state);
3624         intel_edp_backlight_on(pipe_config, conn_state);
3625 }
3626
3627 static void vlv_enable_dp(struct intel_encoder *encoder,
3628                           const struct intel_crtc_state *pipe_config,
3629                           const struct drm_connector_state *conn_state)
3630 {
3631         intel_edp_backlight_on(pipe_config, conn_state);
3632 }
3633
3634 static void g4x_pre_enable_dp(struct intel_encoder *encoder,
3635                               const struct intel_crtc_state *pipe_config,
3636                               const struct drm_connector_state *conn_state)
3637 {
3638         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3639         enum port port = encoder->port;
3640
3641         intel_dp_prepare(encoder, pipe_config);
3642
3643         /* Only ilk+ has port A */
3644         if (port == PORT_A)
3645                 ilk_edp_pll_on(intel_dp, pipe_config);
3646 }
3647
3648 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
3649 {
3650         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3651         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
3652         enum pipe pipe = intel_dp->pps_pipe;
3653         i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe);
3654
3655         WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
3656
3657         if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
3658                 return;
3659
3660         edp_panel_vdd_off_sync(intel_dp);
3661
3662         /*
3663          * VLV seems to get confused when multiple power sequencers
3664          * have the same port selected (even if only one has power/vdd
3665          * enabled). The failure manifests as vlv_wait_port_ready() failing
3666          * CHV on the other hand doesn't seem to mind having the same port
3667          * selected in multiple power sequencers, but let's clear the
3668          * port select always when logically disconnecting a power sequencer
3669          * from a port.
3670          */
3671         drm_dbg_kms(&dev_priv->drm,
3672                     "detaching pipe %c power sequencer from [ENCODER:%d:%s]\n",
3673                     pipe_name(pipe), intel_dig_port->base.base.base.id,
3674                     intel_dig_port->base.base.name);
3675         intel_de_write(dev_priv, pp_on_reg, 0);
3676         intel_de_posting_read(dev_priv, pp_on_reg);
3677
3678         intel_dp->pps_pipe = INVALID_PIPE;
3679 }
3680
3681 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
3682                                       enum pipe pipe)
3683 {
3684         struct intel_encoder *encoder;
3685
3686         lockdep_assert_held(&dev_priv->pps_mutex);
3687
3688         for_each_intel_dp(&dev_priv->drm, encoder) {
3689                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3690
3691                 WARN(intel_dp->active_pipe == pipe,
3692                      "stealing pipe %c power sequencer from active [ENCODER:%d:%s]\n",
3693                      pipe_name(pipe), encoder->base.base.id,
3694                      encoder->base.name);
3695
3696                 if (intel_dp->pps_pipe != pipe)
3697                         continue;
3698
3699                 drm_dbg_kms(&dev_priv->drm,
3700                             "stealing pipe %c power sequencer from [ENCODER:%d:%s]\n",
3701                             pipe_name(pipe), encoder->base.base.id,
3702                             encoder->base.name);
3703
3704                 /* make sure vdd is off before we steal it */
3705                 vlv_detach_power_sequencer(intel_dp);
3706         }
3707 }
3708
3709 static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
3710                                            const struct intel_crtc_state *crtc_state)
3711 {
3712         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3713         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3714         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3715
3716         lockdep_assert_held(&dev_priv->pps_mutex);
3717
3718         WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
3719
3720         if (intel_dp->pps_pipe != INVALID_PIPE &&
3721             intel_dp->pps_pipe != crtc->pipe) {
3722                 /*
3723                  * If another power sequencer was being used on this
3724                  * port previously make sure to turn off vdd there while
3725                  * we still have control of it.
3726                  */
3727                 vlv_detach_power_sequencer(intel_dp);
3728         }
3729
3730         /*
3731          * We may be stealing the power
3732          * sequencer from another port.
3733          */
3734         vlv_steal_power_sequencer(dev_priv, crtc->pipe);
3735
3736         intel_dp->active_pipe = crtc->pipe;
3737
3738         if (!intel_dp_is_edp(intel_dp))
3739                 return;
3740
3741         /* now it's all ours */
3742         intel_dp->pps_pipe = crtc->pipe;
3743
3744         drm_dbg_kms(&dev_priv->drm,
3745                     "initializing pipe %c power sequencer for [ENCODER:%d:%s]\n",
3746                     pipe_name(intel_dp->pps_pipe), encoder->base.base.id,
3747                     encoder->base.name);
3748
3749         /* init power sequencer on this pipe and port */
3750         intel_dp_init_panel_power_sequencer(intel_dp);
3751         intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
3752 }
3753
3754 static void vlv_pre_enable_dp(struct intel_encoder *encoder,
3755                               const struct intel_crtc_state *pipe_config,
3756                               const struct drm_connector_state *conn_state)
3757 {
3758         vlv_phy_pre_encoder_enable(encoder, pipe_config);
3759
3760         intel_enable_dp(encoder, pipe_config, conn_state);
3761 }
3762
3763 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder,
3764                                   const struct intel_crtc_state *pipe_config,
3765                                   const struct drm_connector_state *conn_state)
3766 {
3767         intel_dp_prepare(encoder, pipe_config);
3768
3769         vlv_phy_pre_pll_enable(encoder, pipe_config);
3770 }
3771
3772 static void chv_pre_enable_dp(struct intel_encoder *encoder,
3773                               const struct intel_crtc_state *pipe_config,
3774                               const struct drm_connector_state *conn_state)
3775 {
3776         chv_phy_pre_encoder_enable(encoder, pipe_config);
3777
3778         intel_enable_dp(encoder, pipe_config, conn_state);
3779
3780         /* Second common lane will stay alive on its own now */
3781         chv_phy_release_cl2_override(encoder);
3782 }
3783
3784 static void chv_dp_pre_pll_enable(struct intel_encoder *encoder,
3785                                   const struct intel_crtc_state *pipe_config,
3786                                   const struct drm_connector_state *conn_state)
3787 {
3788         intel_dp_prepare(encoder, pipe_config);
3789
3790         chv_phy_pre_pll_enable(encoder, pipe_config);
3791 }
3792
3793 static void chv_dp_post_pll_disable(struct intel_encoder *encoder,
3794                                     const struct intel_crtc_state *old_crtc_state,
3795                                     const struct drm_connector_state *old_conn_state)
3796 {
3797         chv_phy_post_pll_disable(encoder, old_crtc_state);
3798 }
3799
3800 /*
3801  * Fetch AUX CH registers 0x202 - 0x207 which contain
3802  * link status information
3803  */
3804 bool
3805 intel_dp_get_link_status(struct intel_dp *intel_dp, u8 link_status[DP_LINK_STATUS_SIZE])
3806 {
3807         return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status,
3808                                 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
3809 }
3810
3811 /* These are source-specific values. */
3812 u8
3813 intel_dp_voltage_max(struct intel_dp *intel_dp)
3814 {
3815         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3816         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3817         enum port port = encoder->port;
3818
3819         if (HAS_DDI(dev_priv))
3820                 return intel_ddi_dp_voltage_max(encoder);
3821         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3822                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3823         else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
3824                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3825         else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
3826                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3827         else
3828                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3829 }
3830
3831 u8
3832 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, u8 voltage_swing)
3833 {
3834         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3835         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3836         enum port port = encoder->port;
3837
3838         if (HAS_DDI(dev_priv)) {
3839                 return intel_ddi_dp_pre_emphasis_max(encoder, voltage_swing);
3840         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3841                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3842                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3843                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
3844                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3845                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3846                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3847                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3848                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3849                 default:
3850                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3851                 }
3852         } else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
3853                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3854                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3855                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3856                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3857                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3858                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3859                 default:
3860                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3861                 }
3862         } else {
3863                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3864                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3865                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3866                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3867                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3868                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3869                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3870                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3871                 default:
3872                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3873                 }
3874         }
3875 }
3876
3877 static u32 vlv_signal_levels(struct intel_dp *intel_dp)
3878 {
3879         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3880         unsigned long demph_reg_value, preemph_reg_value,
3881                 uniqtranscale_reg_value;
3882         u8 train_set = intel_dp->train_set[0];
3883
3884         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3885         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3886                 preemph_reg_value = 0x0004000;
3887                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3888                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3889                         demph_reg_value = 0x2B405555;
3890                         uniqtranscale_reg_value = 0x552AB83A;
3891                         break;
3892                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3893                         demph_reg_value = 0x2B404040;
3894                         uniqtranscale_reg_value = 0x5548B83A;
3895                         break;
3896                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3897                         demph_reg_value = 0x2B245555;
3898                         uniqtranscale_reg_value = 0x5560B83A;
3899                         break;
3900                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3901                         demph_reg_value = 0x2B405555;
3902                         uniqtranscale_reg_value = 0x5598DA3A;
3903                         break;
3904                 default:
3905                         return 0;
3906                 }
3907                 break;
3908         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3909                 preemph_reg_value = 0x0002000;
3910                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3911                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3912                         demph_reg_value = 0x2B404040;
3913                         uniqtranscale_reg_value = 0x5552B83A;
3914                         break;
3915                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3916                         demph_reg_value = 0x2B404848;
3917                         uniqtranscale_reg_value = 0x5580B83A;
3918                         break;
3919                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3920                         demph_reg_value = 0x2B404040;
3921                         uniqtranscale_reg_value = 0x55ADDA3A;
3922                         break;
3923                 default:
3924                         return 0;
3925                 }
3926                 break;
3927         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3928                 preemph_reg_value = 0x0000000;
3929                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3930                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3931                         demph_reg_value = 0x2B305555;
3932                         uniqtranscale_reg_value = 0x5570B83A;
3933                         break;
3934                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3935                         demph_reg_value = 0x2B2B4040;
3936                         uniqtranscale_reg_value = 0x55ADDA3A;
3937                         break;
3938                 default:
3939                         return 0;
3940                 }
3941                 break;
3942         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3943                 preemph_reg_value = 0x0006000;
3944                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3945                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3946                         demph_reg_value = 0x1B405555;
3947                         uniqtranscale_reg_value = 0x55ADDA3A;
3948                         break;
3949                 default:
3950                         return 0;
3951                 }
3952                 break;
3953         default:
3954                 return 0;
3955         }
3956
3957         vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value,
3958                                  uniqtranscale_reg_value, 0);
3959
3960         return 0;
3961 }
3962
3963 static u32 chv_signal_levels(struct intel_dp *intel_dp)
3964 {
3965         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3966         u32 deemph_reg_value, margin_reg_value;
3967         bool uniq_trans_scale = false;
3968         u8 train_set = intel_dp->train_set[0];
3969
3970         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3971         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3972                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3973                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3974                         deemph_reg_value = 128;
3975                         margin_reg_value = 52;
3976                         break;
3977                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3978                         deemph_reg_value = 128;
3979                         margin_reg_value = 77;
3980                         break;
3981                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3982                         deemph_reg_value = 128;
3983                         margin_reg_value = 102;
3984                         break;
3985                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3986                         deemph_reg_value = 128;
3987                         margin_reg_value = 154;
3988                         uniq_trans_scale = true;
3989                         break;
3990                 default:
3991                         return 0;
3992                 }
3993                 break;
3994         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3995                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3996                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3997                         deemph_reg_value = 85;
3998                         margin_reg_value = 78;
3999                         break;
4000                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4001                         deemph_reg_value = 85;
4002                         margin_reg_value = 116;
4003                         break;
4004                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
4005                         deemph_reg_value = 85;
4006                         margin_reg_value = 154;
4007                         break;
4008                 default:
4009                         return 0;
4010                 }
4011                 break;
4012         case DP_TRAIN_PRE_EMPH_LEVEL_2:
4013                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4014                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4015                         deemph_reg_value = 64;
4016                         margin_reg_value = 104;
4017                         break;
4018                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4019                         deemph_reg_value = 64;
4020                         margin_reg_value = 154;
4021                         break;
4022                 default:
4023                         return 0;
4024                 }
4025                 break;
4026         case DP_TRAIN_PRE_EMPH_LEVEL_3:
4027                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4028                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4029                         deemph_reg_value = 43;
4030                         margin_reg_value = 154;
4031                         break;
4032                 default:
4033                         return 0;
4034                 }
4035                 break;
4036         default:
4037                 return 0;
4038         }
4039
4040         chv_set_phy_signal_level(encoder, deemph_reg_value,
4041                                  margin_reg_value, uniq_trans_scale);
4042
4043         return 0;
4044 }
4045
4046 static u32
4047 g4x_signal_levels(u8 train_set)
4048 {
4049         u32 signal_levels = 0;
4050
4051         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4052         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4053         default:
4054                 signal_levels |= DP_VOLTAGE_0_4;
4055                 break;
4056         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4057                 signal_levels |= DP_VOLTAGE_0_6;
4058                 break;
4059         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
4060                 signal_levels |= DP_VOLTAGE_0_8;
4061                 break;
4062         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
4063                 signal_levels |= DP_VOLTAGE_1_2;
4064                 break;
4065         }
4066         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
4067         case DP_TRAIN_PRE_EMPH_LEVEL_0:
4068         default:
4069                 signal_levels |= DP_PRE_EMPHASIS_0;
4070                 break;
4071         case DP_TRAIN_PRE_EMPH_LEVEL_1:
4072                 signal_levels |= DP_PRE_EMPHASIS_3_5;
4073                 break;
4074         case DP_TRAIN_PRE_EMPH_LEVEL_2:
4075                 signal_levels |= DP_PRE_EMPHASIS_6;
4076                 break;
4077         case DP_TRAIN_PRE_EMPH_LEVEL_3:
4078                 signal_levels |= DP_PRE_EMPHASIS_9_5;
4079                 break;
4080         }
4081         return signal_levels;
4082 }
4083
4084 /* SNB CPU eDP voltage swing and pre-emphasis control */
4085 static u32
4086 snb_cpu_edp_signal_levels(u8 train_set)
4087 {
4088         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
4089                                          DP_TRAIN_PRE_EMPHASIS_MASK);
4090         switch (signal_levels) {
4091         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4092         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4093                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
4094         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4095                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
4096         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
4097         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
4098                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
4099         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4100         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4101                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
4102         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4103         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4104                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
4105         default:
4106                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
4107                               "0x%x\n", signal_levels);
4108                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
4109         }
4110 }
4111
4112 /* IVB CPU eDP voltage swing and pre-emphasis control */
4113 static u32
4114 ivb_cpu_edp_signal_levels(u8 train_set)
4115 {
4116         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
4117                                          DP_TRAIN_PRE_EMPHASIS_MASK);
4118         switch (signal_levels) {
4119         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4120                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
4121         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4122                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
4123         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
4124                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
4125
4126         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4127                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
4128         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4129                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
4130
4131         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4132                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
4133         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4134                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
4135
4136         default:
4137                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
4138                               "0x%x\n", signal_levels);
4139                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
4140         }
4141 }
4142
4143 void
4144 intel_dp_set_signal_levels(struct intel_dp *intel_dp)
4145 {
4146         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4147         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4148         enum port port = intel_dig_port->base.port;
4149         u32 signal_levels, mask = 0;
4150         u8 train_set = intel_dp->train_set[0];
4151
4152         if (IS_GEN9_LP(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
4153                 signal_levels = bxt_signal_levels(intel_dp);
4154         } else if (HAS_DDI(dev_priv)) {
4155                 signal_levels = ddi_signal_levels(intel_dp);
4156                 mask = DDI_BUF_EMP_MASK;
4157         } else if (IS_CHERRYVIEW(dev_priv)) {
4158                 signal_levels = chv_signal_levels(intel_dp);
4159         } else if (IS_VALLEYVIEW(dev_priv)) {
4160                 signal_levels = vlv_signal_levels(intel_dp);
4161         } else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
4162                 signal_levels = ivb_cpu_edp_signal_levels(train_set);
4163                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
4164         } else if (IS_GEN(dev_priv, 6) && port == PORT_A) {
4165                 signal_levels = snb_cpu_edp_signal_levels(train_set);
4166                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
4167         } else {
4168                 signal_levels = g4x_signal_levels(train_set);
4169                 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
4170         }
4171
4172         if (mask)
4173                 drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n",
4174                             signal_levels);
4175
4176         drm_dbg_kms(&dev_priv->drm, "Using vswing level %d%s\n",
4177                     train_set & DP_TRAIN_VOLTAGE_SWING_MASK,
4178                     train_set & DP_TRAIN_MAX_SWING_REACHED ? " (max)" : "");
4179         drm_dbg_kms(&dev_priv->drm, "Using pre-emphasis level %d%s\n",
4180                     (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
4181                     DP_TRAIN_PRE_EMPHASIS_SHIFT,
4182                     train_set & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED ?
4183                     " (max)" : "");
4184
4185         intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels;
4186
4187         intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
4188         intel_de_posting_read(dev_priv, intel_dp->output_reg);
4189 }
4190
4191 void
4192 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
4193                                        u8 dp_train_pat)
4194 {
4195         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4196         struct drm_i915_private *dev_priv =
4197                 to_i915(intel_dig_port->base.base.dev);
4198
4199         _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat);
4200
4201         intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
4202         intel_de_posting_read(dev_priv, intel_dp->output_reg);
4203 }
4204
4205 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
4206 {
4207         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4208         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4209         enum port port = intel_dig_port->base.port;
4210         u32 val;
4211
4212         if (!HAS_DDI(dev_priv))
4213                 return;
4214
4215         val = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl);
4216         val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
4217         val |= DP_TP_CTL_LINK_TRAIN_IDLE;
4218         intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, val);
4219
4220         /*
4221          * Until TGL on PORT_A we can have only eDP in SST mode. There the only
4222          * reason we need to set idle transmission mode is to work around a HW
4223          * issue where we enable the pipe while not in idle link-training mode.
4224          * In this case there is requirement to wait for a minimum number of
4225          * idle patterns to be sent.
4226          */
4227         if (port == PORT_A && INTEL_GEN(dev_priv) < 12)
4228                 return;
4229
4230         if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status,
4231                                   DP_TP_STATUS_IDLE_DONE, 1))
4232                 drm_err(&dev_priv->drm,
4233                         "Timed out waiting for DP idle patterns\n");
4234 }
4235
4236 static void
4237 intel_dp_link_down(struct intel_encoder *encoder,
4238                    const struct intel_crtc_state *old_crtc_state)
4239 {
4240         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4241         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4242         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
4243         enum port port = encoder->port;
4244         u32 DP = intel_dp->DP;
4245
4246         if (WARN_ON((intel_de_read(dev_priv, intel_dp->output_reg) & DP_PORT_EN) == 0))
4247                 return;
4248
4249         drm_dbg_kms(&dev_priv->drm, "\n");
4250
4251         if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
4252             (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
4253                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
4254                 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
4255         } else {
4256                 DP &= ~DP_LINK_TRAIN_MASK;
4257                 DP |= DP_LINK_TRAIN_PAT_IDLE;
4258         }
4259         intel_de_write(dev_priv, intel_dp->output_reg, DP);
4260         intel_de_posting_read(dev_priv, intel_dp->output_reg);
4261
4262         DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
4263         intel_de_write(dev_priv, intel_dp->output_reg, DP);
4264         intel_de_posting_read(dev_priv, intel_dp->output_reg);
4265
4266         /*
4267          * HW workaround for IBX, we need to move the port
4268          * to transcoder A after disabling it to allow the
4269          * matching HDMI port to be enabled on transcoder A.
4270          */
4271         if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) {
4272                 /*
4273                  * We get CPU/PCH FIFO underruns on the other pipe when
4274                  * doing the workaround. Sweep them under the rug.
4275                  */
4276                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
4277                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
4278
4279                 /* always enable with pattern 1 (as per spec) */
4280                 DP &= ~(DP_PIPE_SEL_MASK | DP_LINK_TRAIN_MASK);
4281                 DP |= DP_PORT_EN | DP_PIPE_SEL(PIPE_A) |
4282                         DP_LINK_TRAIN_PAT_1;
4283                 intel_de_write(dev_priv, intel_dp->output_reg, DP);
4284                 intel_de_posting_read(dev_priv, intel_dp->output_reg);
4285
4286                 DP &= ~DP_PORT_EN;
4287                 intel_de_write(dev_priv, intel_dp->output_reg, DP);
4288                 intel_de_posting_read(dev_priv, intel_dp->output_reg);
4289
4290                 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
4291                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
4292                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
4293         }
4294
4295         msleep(intel_dp->panel_power_down_delay);
4296
4297         intel_dp->DP = DP;
4298
4299         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
4300                 intel_wakeref_t wakeref;
4301
4302                 with_pps_lock(intel_dp, wakeref)
4303                         intel_dp->active_pipe = INVALID_PIPE;
4304         }
4305 }
4306
4307 static void
4308 intel_dp_extended_receiver_capabilities(struct intel_dp *intel_dp)
4309 {
4310         u8 dpcd_ext[6];
4311
4312         /*
4313          * Prior to DP1.3 the bit represented by
4314          * DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT was reserved.
4315          * if it is set DP_DPCD_REV at 0000h could be at a value less than
4316          * the true capability of the panel. The only way to check is to
4317          * then compare 0000h and 2200h.
4318          */
4319         if (!(intel_dp->dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
4320               DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT))
4321                 return;
4322
4323         if (drm_dp_dpcd_read(&intel_dp->aux, DP_DP13_DPCD_REV,
4324                              &dpcd_ext, sizeof(dpcd_ext)) != sizeof(dpcd_ext)) {
4325                 DRM_ERROR("DPCD failed read at extended capabilities\n");
4326                 return;
4327         }
4328
4329         if (intel_dp->dpcd[DP_DPCD_REV] > dpcd_ext[DP_DPCD_REV]) {
4330                 DRM_DEBUG_KMS("DPCD extended DPCD rev less than base DPCD rev\n");
4331                 return;
4332         }
4333
4334         if (!memcmp(intel_dp->dpcd, dpcd_ext, sizeof(dpcd_ext)))
4335                 return;
4336
4337         DRM_DEBUG_KMS("Base DPCD: %*ph\n",
4338                       (int)sizeof(intel_dp->dpcd), intel_dp->dpcd);
4339
4340         memcpy(intel_dp->dpcd, dpcd_ext, sizeof(dpcd_ext));
4341 }
4342
4343 bool
4344 intel_dp_read_dpcd(struct intel_dp *intel_dp)
4345 {
4346         if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd,
4347                              sizeof(intel_dp->dpcd)) < 0)
4348                 return false; /* aux transfer failed */
4349
4350         intel_dp_extended_receiver_capabilities(intel_dp);
4351
4352         DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
4353
4354         return intel_dp->dpcd[DP_DPCD_REV] != 0;
4355 }
4356
4357 bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
4358 {
4359         u8 dprx = 0;
4360
4361         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST,
4362                               &dprx) != 1)
4363                 return false;
4364         return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED;
4365 }
4366
4367 static void intel_dp_get_dsc_sink_cap(struct intel_dp *intel_dp)
4368 {
4369         /*
4370          * Clear the cached register set to avoid using stale values
4371          * for the sinks that do not support DSC.
4372          */
4373         memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
4374
4375         /* Clear fec_capable to avoid using stale values */
4376         intel_dp->fec_capable = 0;
4377
4378         /* Cache the DSC DPCD if eDP or DP rev >= 1.4 */
4379         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x14 ||
4380             intel_dp->edp_dpcd[0] >= DP_EDP_14) {
4381                 if (drm_dp_dpcd_read(&intel_dp->aux, DP_DSC_SUPPORT,
4382                                      intel_dp->dsc_dpcd,
4383                                      sizeof(intel_dp->dsc_dpcd)) < 0)
4384                         DRM_ERROR("Failed to read DPCD register 0x%x\n",
4385                                   DP_DSC_SUPPORT);
4386
4387                 DRM_DEBUG_KMS("DSC DPCD: %*ph\n",
4388                               (int)sizeof(intel_dp->dsc_dpcd),
4389                               intel_dp->dsc_dpcd);
4390
4391                 /* FEC is supported only on DP 1.4 */
4392                 if (!intel_dp_is_edp(intel_dp) &&
4393                     drm_dp_dpcd_readb(&intel_dp->aux, DP_FEC_CAPABILITY,
4394                                       &intel_dp->fec_capable) < 0)
4395                         DRM_ERROR("Failed to read FEC DPCD register\n");
4396
4397                 DRM_DEBUG_KMS("FEC CAPABILITY: %x\n", intel_dp->fec_capable);
4398         }
4399 }
4400
4401 static bool
4402 intel_edp_init_dpcd(struct intel_dp *intel_dp)
4403 {
4404         struct drm_i915_private *dev_priv =
4405                 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
4406
4407         /* this function is meant to be called only once */
4408         WARN_ON(intel_dp->dpcd[DP_DPCD_REV] != 0);
4409
4410         if (!intel_dp_read_dpcd(intel_dp))
4411                 return false;
4412
4413         drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
4414                          drm_dp_is_branch(intel_dp->dpcd));
4415
4416         /*
4417          * Read the eDP display control registers.
4418          *
4419          * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in
4420          * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it
4421          * set, but require eDP 1.4+ detection (e.g. for supported link rates
4422          * method). The display control registers should read zero if they're
4423          * not supported anyway.
4424          */
4425         if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
4426                              intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
4427                              sizeof(intel_dp->edp_dpcd))
4428                 drm_dbg_kms(&dev_priv->drm, "eDP DPCD: %*ph\n",
4429                             (int)sizeof(intel_dp->edp_dpcd),
4430                             intel_dp->edp_dpcd);
4431
4432         /*
4433          * This has to be called after intel_dp->edp_dpcd is filled, PSR checks
4434          * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1]
4435          */
4436         intel_psr_init_dpcd(intel_dp);
4437
4438         /* Read the eDP 1.4+ supported link rates. */
4439         if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
4440                 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
4441                 int i;
4442
4443                 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
4444                                 sink_rates, sizeof(sink_rates));
4445
4446                 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
4447                         int val = le16_to_cpu(sink_rates[i]);
4448
4449                         if (val == 0)
4450                                 break;
4451
4452                         /* Value read multiplied by 200kHz gives the per-lane
4453                          * link rate in kHz. The source rates are, however,
4454                          * stored in terms of LS_Clk kHz. The full conversion
4455                          * back to symbols is
4456                          * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
4457                          */
4458                         intel_dp->sink_rates[i] = (val * 200) / 10;
4459                 }
4460                 intel_dp->num_sink_rates = i;
4461         }
4462
4463         /*
4464          * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available,
4465          * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise.
4466          */
4467         if (intel_dp->num_sink_rates)
4468                 intel_dp->use_rate_select = true;
4469         else
4470                 intel_dp_set_sink_rates(intel_dp);
4471
4472         intel_dp_set_common_rates(intel_dp);
4473
4474         /* Read the eDP DSC DPCD registers */
4475         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
4476                 intel_dp_get_dsc_sink_cap(intel_dp);
4477
4478         return true;
4479 }
4480
4481
4482 static bool
4483 intel_dp_get_dpcd(struct intel_dp *intel_dp)
4484 {
4485         if (!intel_dp_read_dpcd(intel_dp))
4486                 return false;
4487
4488         /*
4489          * Don't clobber cached eDP rates. Also skip re-reading
4490          * the OUI/ID since we know it won't change.
4491          */
4492         if (!intel_dp_is_edp(intel_dp)) {
4493                 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
4494                                  drm_dp_is_branch(intel_dp->dpcd));
4495
4496                 intel_dp_set_sink_rates(intel_dp);
4497                 intel_dp_set_common_rates(intel_dp);
4498         }
4499
4500         /*
4501          * Some eDP panels do not set a valid value for sink count, that is why
4502          * it don't care about read it here and in intel_edp_init_dpcd().
4503          */
4504         if (!intel_dp_is_edp(intel_dp) &&
4505             !drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_NO_SINK_COUNT)) {
4506                 u8 count;
4507                 ssize_t r;
4508
4509                 r = drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_COUNT, &count);
4510                 if (r < 1)
4511                         return false;
4512
4513                 /*
4514                  * Sink count can change between short pulse hpd hence
4515                  * a member variable in intel_dp will track any changes
4516                  * between short pulse interrupts.
4517                  */
4518                 intel_dp->sink_count = DP_GET_SINK_COUNT(count);
4519
4520                 /*
4521                  * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
4522                  * a dongle is present but no display. Unless we require to know
4523                  * if a dongle is present or not, we don't need to update
4524                  * downstream port information. So, an early return here saves
4525                  * time from performing other operations which are not required.
4526                  */
4527                 if (!intel_dp->sink_count)
4528                         return false;
4529         }
4530
4531         if (!drm_dp_is_branch(intel_dp->dpcd))
4532                 return true; /* native DP sink */
4533
4534         if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
4535                 return true; /* no per-port downstream info */
4536
4537         if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
4538                              intel_dp->downstream_ports,
4539                              DP_MAX_DOWNSTREAM_PORTS) < 0)
4540                 return false; /* downstream port status fetch failed */
4541
4542         return true;
4543 }
4544
4545 static bool
4546 intel_dp_sink_can_mst(struct intel_dp *intel_dp)
4547 {
4548         u8 mstm_cap;
4549
4550         if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
4551                 return false;
4552
4553         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_MSTM_CAP, &mstm_cap) != 1)
4554                 return false;
4555
4556         return mstm_cap & DP_MST_CAP;
4557 }
4558
4559 static bool
4560 intel_dp_can_mst(struct intel_dp *intel_dp)
4561 {
4562         return i915_modparams.enable_dp_mst &&
4563                 intel_dp->can_mst &&
4564                 intel_dp_sink_can_mst(intel_dp);
4565 }
4566
4567 static void
4568 intel_dp_configure_mst(struct intel_dp *intel_dp)
4569 {
4570         struct intel_encoder *encoder =
4571                 &dp_to_dig_port(intel_dp)->base;
4572         bool sink_can_mst = intel_dp_sink_can_mst(intel_dp);
4573
4574         DRM_DEBUG_KMS("[ENCODER:%d:%s] MST support: port: %s, sink: %s, modparam: %s\n",
4575                       encoder->base.base.id, encoder->base.name,
4576                       yesno(intel_dp->can_mst), yesno(sink_can_mst),
4577                       yesno(i915_modparams.enable_dp_mst));
4578
4579         if (!intel_dp->can_mst)
4580                 return;
4581
4582         intel_dp->is_mst = sink_can_mst &&
4583                 i915_modparams.enable_dp_mst;
4584
4585         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4586                                         intel_dp->is_mst);
4587 }
4588
4589 static bool
4590 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4591 {
4592         return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI,
4593                                 sink_irq_vector, DP_DPRX_ESI_LEN) ==
4594                 DP_DPRX_ESI_LEN;
4595 }
4596
4597 bool
4598 intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
4599                        const struct drm_connector_state *conn_state)
4600 {
4601         /*
4602          * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
4603          * of Color Encoding Format and Content Color Gamut], in order to
4604          * sending YCBCR 420 or HDR BT.2020 signals we should use DP VSC SDP.
4605          */
4606         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
4607                 return true;
4608
4609         switch (conn_state->colorspace) {
4610         case DRM_MODE_COLORIMETRY_SYCC_601:
4611         case DRM_MODE_COLORIMETRY_OPYCC_601:
4612         case DRM_MODE_COLORIMETRY_BT2020_YCC:
4613         case DRM_MODE_COLORIMETRY_BT2020_RGB:
4614         case DRM_MODE_COLORIMETRY_BT2020_CYCC:
4615                 return true;
4616         default:
4617                 break;
4618         }
4619
4620         return false;
4621 }
4622
4623 static void
4624 intel_dp_setup_vsc_sdp(struct intel_dp *intel_dp,
4625                        const struct intel_crtc_state *crtc_state,
4626                        const struct drm_connector_state *conn_state)
4627 {
4628         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4629         struct dp_sdp vsc_sdp = {};
4630
4631         /* Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119 */
4632         vsc_sdp.sdp_header.HB0 = 0;
4633         vsc_sdp.sdp_header.HB1 = 0x7;
4634
4635         /*
4636          * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
4637          * Colorimetry Format indication.
4638          */
4639         vsc_sdp.sdp_header.HB2 = 0x5;
4640
4641         /*
4642          * VSC SDP supporting 3D stereo, + PSR2, + Pixel Encoding/
4643          * Colorimetry Format indication (HB2 = 05h).
4644          */
4645         vsc_sdp.sdp_header.HB3 = 0x13;
4646
4647         /* DP 1.4a spec, Table 2-120 */
4648         switch (crtc_state->output_format) {
4649         case INTEL_OUTPUT_FORMAT_YCBCR444:
4650                 vsc_sdp.db[16] = 0x1 << 4; /* YCbCr 444 : DB16[7:4] = 1h */
4651                 break;
4652         case INTEL_OUTPUT_FORMAT_YCBCR420:
4653                 vsc_sdp.db[16] = 0x3 << 4; /* YCbCr 420 : DB16[7:4] = 3h */
4654                 break;
4655         case INTEL_OUTPUT_FORMAT_RGB:
4656         default:
4657                 /* RGB: DB16[7:4] = 0h */
4658                 break;
4659         }
4660
4661         switch (conn_state->colorspace) {
4662         case DRM_MODE_COLORIMETRY_BT709_YCC:
4663                 vsc_sdp.db[16] |= 0x1;
4664                 break;
4665         case DRM_MODE_COLORIMETRY_XVYCC_601:
4666                 vsc_sdp.db[16] |= 0x2;
4667                 break;
4668         case DRM_MODE_COLORIMETRY_XVYCC_709:
4669                 vsc_sdp.db[16] |= 0x3;
4670                 break;
4671         case DRM_MODE_COLORIMETRY_SYCC_601:
4672                 vsc_sdp.db[16] |= 0x4;
4673                 break;
4674         case DRM_MODE_COLORIMETRY_OPYCC_601:
4675                 vsc_sdp.db[16] |= 0x5;
4676                 break;
4677         case DRM_MODE_COLORIMETRY_BT2020_CYCC:
4678         case DRM_MODE_COLORIMETRY_BT2020_RGB:
4679                 vsc_sdp.db[16] |= 0x6;
4680                 break;
4681         case DRM_MODE_COLORIMETRY_BT2020_YCC:
4682                 vsc_sdp.db[16] |= 0x7;
4683                 break;
4684         case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
4685         case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
4686                 vsc_sdp.db[16] |= 0x4; /* DCI-P3 (SMPTE RP 431-2) */
4687                 break;
4688         default:
4689                 /* sRGB (IEC 61966-2-1) / ITU-R BT.601: DB16[0:3] = 0h */
4690
4691                 /* RGB->YCBCR color conversion uses the BT.709 color space. */
4692                 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
4693                         vsc_sdp.db[16] |= 0x1; /* 0x1, ITU-R BT.709 */
4694                 break;
4695         }
4696
4697         /*
4698          * For pixel encoding formats YCbCr444, YCbCr422, YCbCr420, and Y Only,
4699          * the following Component Bit Depth values are defined:
4700          * 001b = 8bpc.
4701          * 010b = 10bpc.
4702          * 011b = 12bpc.
4703          * 100b = 16bpc.
4704          */
4705         switch (crtc_state->pipe_bpp) {
4706         case 24: /* 8bpc */
4707                 vsc_sdp.db[17] = 0x1;
4708                 break;
4709         case 30: /* 10bpc */
4710                 vsc_sdp.db[17] = 0x2;
4711                 break;
4712         case 36: /* 12bpc */
4713                 vsc_sdp.db[17] = 0x3;
4714                 break;
4715         case 48: /* 16bpc */
4716                 vsc_sdp.db[17] = 0x4;
4717                 break;
4718         default:
4719                 MISSING_CASE(crtc_state->pipe_bpp);
4720                 break;
4721         }
4722
4723         /*
4724          * Dynamic Range (Bit 7)
4725          * 0 = VESA range, 1 = CTA range.
4726          * all YCbCr are always limited range
4727          */
4728         vsc_sdp.db[17] |= 0x80;
4729
4730         /*
4731          * Content Type (Bits 2:0)
4732          * 000b = Not defined.
4733          * 001b = Graphics.
4734          * 010b = Photo.
4735          * 011b = Video.
4736          * 100b = Game
4737          * All other values are RESERVED.
4738          * Note: See CTA-861-G for the definition and expected
4739          * processing by a stream sink for the above contect types.
4740          */
4741         vsc_sdp.db[18] = 0;
4742
4743         intel_dig_port->write_infoframe(&intel_dig_port->base,
4744                         crtc_state, DP_SDP_VSC, &vsc_sdp, sizeof(vsc_sdp));
4745 }
4746
4747 static void
4748 intel_dp_setup_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
4749                                           const struct intel_crtc_state *crtc_state,
4750                                           const struct drm_connector_state *conn_state)
4751 {
4752         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4753         struct dp_sdp infoframe_sdp = {};
4754         struct hdmi_drm_infoframe drm_infoframe = {};
4755         const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE;
4756         unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE];
4757         ssize_t len;
4758         int ret;
4759
4760         ret = drm_hdmi_infoframe_set_hdr_metadata(&drm_infoframe, conn_state);
4761         if (ret) {
4762                 DRM_DEBUG_KMS("couldn't set HDR metadata in infoframe\n");
4763                 return;
4764         }
4765
4766         len = hdmi_drm_infoframe_pack_only(&drm_infoframe, buf, sizeof(buf));
4767         if (len < 0) {
4768                 DRM_DEBUG_KMS("buffer size is smaller than hdr metadata infoframe\n");
4769                 return;
4770         }
4771
4772         if (len != infoframe_size) {
4773                 DRM_DEBUG_KMS("wrong static hdr metadata size\n");
4774                 return;
4775         }
4776
4777         /*
4778          * Set up the infoframe sdp packet for HDR static metadata.
4779          * Prepare VSC Header for SU as per DP 1.4a spec,
4780          * Table 2-100 and Table 2-101
4781          */
4782
4783         /* Packet ID, 00h for non-Audio INFOFRAME */
4784         infoframe_sdp.sdp_header.HB0 = 0;
4785         /*
4786          * Packet Type 80h + Non-audio INFOFRAME Type value
4787          * HDMI_INFOFRAME_TYPE_DRM: 0x87,
4788          */
4789         infoframe_sdp.sdp_header.HB1 = drm_infoframe.type;
4790         /*
4791          * Least Significant Eight Bits of (Data Byte Count – 1)
4792          * infoframe_size - 1,
4793          */
4794         infoframe_sdp.sdp_header.HB2 = 0x1D;
4795         /* INFOFRAME SDP Version Number */
4796         infoframe_sdp.sdp_header.HB3 = (0x13 << 2);
4797         /* CTA Header Byte 2 (INFOFRAME Version Number) */
4798         infoframe_sdp.db[0] = drm_infoframe.version;
4799         /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
4800         infoframe_sdp.db[1] = drm_infoframe.length;
4801         /*
4802          * Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after
4803          * HDMI_INFOFRAME_HEADER_SIZE
4804          */
4805         BUILD_BUG_ON(sizeof(infoframe_sdp.db) < HDMI_DRM_INFOFRAME_SIZE + 2);
4806         memcpy(&infoframe_sdp.db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE],
4807                HDMI_DRM_INFOFRAME_SIZE);
4808
4809         /*
4810          * Size of DP infoframe sdp packet for HDR static metadata is consist of
4811          * - DP SDP Header(struct dp_sdp_header): 4 bytes
4812          * - Two Data Blocks: 2 bytes
4813          *    CTA Header Byte2 (INFOFRAME Version Number)
4814          *    CTA Header Byte3 (Length of INFOFRAME)
4815          * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes
4816          *
4817          * Prior to GEN11's GMP register size is identical to DP HDR static metadata
4818          * infoframe size. But GEN11+ has larger than that size, write_infoframe
4819          * will pad rest of the size.
4820          */
4821         intel_dig_port->write_infoframe(&intel_dig_port->base, crtc_state,
4822                                         HDMI_PACKET_TYPE_GAMUT_METADATA,
4823                                         &infoframe_sdp,
4824                                         sizeof(struct dp_sdp_header) + 2 + HDMI_DRM_INFOFRAME_SIZE);
4825 }
4826
4827 void intel_dp_vsc_enable(struct intel_dp *intel_dp,
4828                          const struct intel_crtc_state *crtc_state,
4829                          const struct drm_connector_state *conn_state)
4830 {
4831         if (!intel_dp_needs_vsc_sdp(crtc_state, conn_state))
4832                 return;
4833
4834         intel_dp_setup_vsc_sdp(intel_dp, crtc_state, conn_state);
4835 }
4836
4837 void intel_dp_hdr_metadata_enable(struct intel_dp *intel_dp,
4838                                   const struct intel_crtc_state *crtc_state,
4839                                   const struct drm_connector_state *conn_state)
4840 {
4841         if (!conn_state->hdr_output_metadata)
4842                 return;
4843
4844         intel_dp_setup_hdr_metadata_infoframe_sdp(intel_dp,
4845                                                   crtc_state,
4846                                                   conn_state);
4847 }
4848
4849 static u8 intel_dp_autotest_link_training(struct intel_dp *intel_dp)
4850 {
4851         int status = 0;
4852         int test_link_rate;
4853         u8 test_lane_count, test_link_bw;
4854         /* (DP CTS 1.2)
4855          * 4.3.1.11
4856          */
4857         /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
4858         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,
4859                                    &test_lane_count);
4860
4861         if (status <= 0) {
4862                 DRM_DEBUG_KMS("Lane count read failed\n");
4863                 return DP_TEST_NAK;
4864         }
4865         test_lane_count &= DP_MAX_LANE_COUNT_MASK;
4866
4867         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
4868                                    &test_link_bw);
4869         if (status <= 0) {
4870                 DRM_DEBUG_KMS("Link Rate read failed\n");
4871                 return DP_TEST_NAK;
4872         }
4873         test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw);
4874
4875         /* Validate the requested link rate and lane count */
4876         if (!intel_dp_link_params_valid(intel_dp, test_link_rate,
4877                                         test_lane_count))
4878                 return DP_TEST_NAK;
4879
4880         intel_dp->compliance.test_lane_count = test_lane_count;
4881         intel_dp->compliance.test_link_rate = test_link_rate;
4882
4883         return DP_TEST_ACK;
4884 }
4885
4886 static u8 intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
4887 {
4888         u8 test_pattern;
4889         u8 test_misc;
4890         __be16 h_width, v_height;
4891         int status = 0;
4892
4893         /* Read the TEST_PATTERN (DP CTS 3.1.5) */
4894         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN,
4895                                    &test_pattern);
4896         if (status <= 0) {
4897                 DRM_DEBUG_KMS("Test pattern read failed\n");
4898                 return DP_TEST_NAK;
4899         }
4900         if (test_pattern != DP_COLOR_RAMP)
4901                 return DP_TEST_NAK;
4902
4903         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI,
4904                                   &h_width, 2);
4905         if (status <= 0) {
4906                 DRM_DEBUG_KMS("H Width read failed\n");
4907                 return DP_TEST_NAK;
4908         }
4909
4910         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI,
4911                                   &v_height, 2);
4912         if (status <= 0) {
4913                 DRM_DEBUG_KMS("V Height read failed\n");
4914                 return DP_TEST_NAK;
4915         }
4916
4917         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0,
4918                                    &test_misc);
4919         if (status <= 0) {
4920                 DRM_DEBUG_KMS("TEST MISC read failed\n");
4921                 return DP_TEST_NAK;
4922         }
4923         if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB)
4924                 return DP_TEST_NAK;
4925         if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA)
4926                 return DP_TEST_NAK;
4927         switch (test_misc & DP_TEST_BIT_DEPTH_MASK) {
4928         case DP_TEST_BIT_DEPTH_6:
4929                 intel_dp->compliance.test_data.bpc = 6;
4930                 break;
4931         case DP_TEST_BIT_DEPTH_8:
4932                 intel_dp->compliance.test_data.bpc = 8;
4933                 break;
4934         default:
4935                 return DP_TEST_NAK;
4936         }
4937
4938         intel_dp->compliance.test_data.video_pattern = test_pattern;
4939         intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width);
4940         intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height);
4941         /* Set test active flag here so userspace doesn't interrupt things */
4942         intel_dp->compliance.test_active = true;
4943
4944         return DP_TEST_ACK;
4945 }
4946
4947 static u8 intel_dp_autotest_edid(struct intel_dp *intel_dp)
4948 {
4949         u8 test_result = DP_TEST_ACK;
4950         struct intel_connector *intel_connector = intel_dp->attached_connector;
4951         struct drm_connector *connector = &intel_connector->base;
4952
4953         if (intel_connector->detect_edid == NULL ||
4954             connector->edid_corrupt ||
4955             intel_dp->aux.i2c_defer_count > 6) {
4956                 /* Check EDID read for NACKs, DEFERs and corruption
4957                  * (DP CTS 1.2 Core r1.1)
4958                  *    4.2.2.4 : Failed EDID read, I2C_NAK
4959                  *    4.2.2.5 : Failed EDID read, I2C_DEFER
4960                  *    4.2.2.6 : EDID corruption detected
4961                  * Use failsafe mode for all cases
4962                  */
4963                 if (intel_dp->aux.i2c_nack_count > 0 ||
4964                         intel_dp->aux.i2c_defer_count > 0)
4965                         DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
4966                                       intel_dp->aux.i2c_nack_count,
4967                                       intel_dp->aux.i2c_defer_count);
4968                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE;
4969         } else {
4970                 struct edid *block = intel_connector->detect_edid;
4971
4972                 /* We have to write the checksum
4973                  * of the last block read
4974                  */
4975                 block += intel_connector->detect_edid->extensions;
4976
4977                 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM,
4978                                        block->checksum) <= 0)
4979                         DRM_DEBUG_KMS("Failed to write EDID checksum\n");
4980
4981                 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
4982                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED;
4983         }
4984
4985         /* Set test active flag here so userspace doesn't interrupt things */
4986         intel_dp->compliance.test_active = true;
4987
4988         return test_result;
4989 }
4990
4991 static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
4992 {
4993         u8 test_result = DP_TEST_NAK;
4994         return test_result;
4995 }
4996
4997 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
4998 {
4999         u8 response = DP_TEST_NAK;
5000         u8 request = 0;
5001         int status;
5002
5003         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request);
5004         if (status <= 0) {
5005                 DRM_DEBUG_KMS("Could not read test request from sink\n");
5006                 goto update_status;
5007         }
5008
5009         switch (request) {
5010         case DP_TEST_LINK_TRAINING:
5011                 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
5012                 response = intel_dp_autotest_link_training(intel_dp);
5013                 break;
5014         case DP_TEST_LINK_VIDEO_PATTERN:
5015                 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
5016                 response = intel_dp_autotest_video_pattern(intel_dp);
5017                 break;
5018         case DP_TEST_LINK_EDID_READ:
5019                 DRM_DEBUG_KMS("EDID test requested\n");
5020                 response = intel_dp_autotest_edid(intel_dp);
5021                 break;
5022         case DP_TEST_LINK_PHY_TEST_PATTERN:
5023                 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
5024                 response = intel_dp_autotest_phy_pattern(intel_dp);
5025                 break;
5026         default:
5027                 DRM_DEBUG_KMS("Invalid test request '%02x'\n", request);
5028                 break;
5029         }
5030
5031         if (response & DP_TEST_ACK)
5032                 intel_dp->compliance.test_type = request;
5033
5034 update_status:
5035         status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response);
5036         if (status <= 0)
5037                 DRM_DEBUG_KMS("Could not write test response to sink\n");
5038 }
5039
5040 static int
5041 intel_dp_check_mst_status(struct intel_dp *intel_dp)
5042 {
5043         bool bret;
5044
5045         if (intel_dp->is_mst) {
5046                 u8 esi[DP_DPRX_ESI_LEN] = { 0 };
5047                 int ret = 0;
5048                 int retry;
5049                 bool handled;
5050
5051                 WARN_ON_ONCE(intel_dp->active_mst_links < 0);
5052                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
5053 go_again:
5054                 if (bret == true) {
5055
5056                         /* check link status - esi[10] = 0x200c */
5057                         if (intel_dp->active_mst_links > 0 &&
5058                             !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
5059                                 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
5060                                 intel_dp_start_link_train(intel_dp);
5061                                 intel_dp_stop_link_train(intel_dp);
5062                         }
5063
5064                         DRM_DEBUG_KMS("got esi %3ph\n", esi);
5065                         ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
5066
5067                         if (handled) {
5068                                 for (retry = 0; retry < 3; retry++) {
5069                                         int wret;
5070                                         wret = drm_dp_dpcd_write(&intel_dp->aux,
5071                                                                  DP_SINK_COUNT_ESI+1,
5072                                                                  &esi[1], 3);
5073                                         if (wret == 3) {
5074                                                 break;
5075                                         }
5076                                 }
5077
5078                                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
5079                                 if (bret == true) {
5080                                         DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
5081                                         goto go_again;
5082                                 }
5083                         } else
5084                                 ret = 0;
5085
5086                         return ret;
5087                 } else {
5088                         DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
5089                         intel_dp->is_mst = false;
5090                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
5091                                                         intel_dp->is_mst);
5092                 }
5093         }
5094         return -EINVAL;
5095 }
5096
5097 static bool
5098 intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
5099 {
5100         u8 link_status[DP_LINK_STATUS_SIZE];
5101
5102         if (!intel_dp->link_trained)
5103                 return false;
5104
5105         /*
5106          * While PSR source HW is enabled, it will control main-link sending
5107          * frames, enabling and disabling it so trying to do a retrain will fail
5108          * as the link would or not be on or it could mix training patterns
5109          * and frame data at the same time causing retrain to fail.
5110          * Also when exiting PSR, HW will retrain the link anyways fixing
5111          * any link status error.
5112          */
5113         if (intel_psr_enabled(intel_dp))
5114                 return false;
5115
5116         if (!intel_dp_get_link_status(intel_dp, link_status))
5117                 return false;
5118
5119         /*
5120          * Validate the cached values of intel_dp->link_rate and
5121          * intel_dp->lane_count before attempting to retrain.
5122          */
5123         if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,
5124                                         intel_dp->lane_count))
5125                 return false;
5126
5127         /* Retrain if Channel EQ or CR not ok */
5128         return !drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);
5129 }
5130
5131 int intel_dp_retrain_link(struct intel_encoder *encoder,
5132                           struct drm_modeset_acquire_ctx *ctx)
5133 {
5134         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5135         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
5136         struct intel_connector *connector = intel_dp->attached_connector;
5137         struct drm_connector_state *conn_state;
5138         struct intel_crtc_state *crtc_state;
5139         struct intel_crtc *crtc;
5140         int ret;
5141
5142         /* FIXME handle the MST connectors as well */
5143
5144         if (!connector || connector->base.status != connector_status_connected)
5145                 return 0;
5146
5147         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
5148                                ctx);
5149         if (ret)
5150                 return ret;
5151
5152         conn_state = connector->base.state;
5153
5154         crtc = to_intel_crtc(conn_state->crtc);
5155         if (!crtc)
5156                 return 0;
5157
5158         ret = drm_modeset_lock(&crtc->base.mutex, ctx);
5159         if (ret)
5160                 return ret;
5161
5162         crtc_state = to_intel_crtc_state(crtc->base.state);
5163
5164         WARN_ON(!intel_crtc_has_dp_encoder(crtc_state));
5165
5166         if (!crtc_state->hw.active)
5167                 return 0;
5168
5169         if (conn_state->commit &&
5170             !try_wait_for_completion(&conn_state->commit->hw_done))
5171                 return 0;
5172
5173         if (!intel_dp_needs_link_retrain(intel_dp))
5174                 return 0;
5175
5176         /* Suppress underruns caused by re-training */
5177         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
5178         if (crtc_state->has_pch_encoder)
5179                 intel_set_pch_fifo_underrun_reporting(dev_priv,
5180                                                       intel_crtc_pch_transcoder(crtc), false);
5181
5182         intel_dp_start_link_train(intel_dp);
5183         intel_dp_stop_link_train(intel_dp);
5184
5185         /* Keep underrun reporting disabled until things are stable */
5186         intel_wait_for_vblank(dev_priv, crtc->pipe);
5187
5188         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
5189         if (crtc_state->has_pch_encoder)
5190                 intel_set_pch_fifo_underrun_reporting(dev_priv,
5191                                                       intel_crtc_pch_transcoder(crtc), true);
5192
5193         return 0;
5194 }
5195
5196 /*
5197  * If display is now connected check links status,
5198  * there has been known issues of link loss triggering
5199  * long pulse.
5200  *
5201  * Some sinks (eg. ASUS PB287Q) seem to perform some
5202  * weird HPD ping pong during modesets. So we can apparently
5203  * end up with HPD going low during a modeset, and then
5204  * going back up soon after. And once that happens we must
5205  * retrain the link to get a picture. That's in case no
5206  * userspace component reacted to intermittent HPD dip.
5207  */
5208 static enum intel_hotplug_state
5209 intel_dp_hotplug(struct intel_encoder *encoder,
5210                  struct intel_connector *connector,
5211                  bool irq_received)
5212 {
5213         struct drm_modeset_acquire_ctx ctx;
5214         enum intel_hotplug_state state;
5215         int ret;
5216
5217         state = intel_encoder_hotplug(encoder, connector, irq_received);
5218
5219         drm_modeset_acquire_init(&ctx, 0);
5220
5221         for (;;) {
5222                 ret = intel_dp_retrain_link(encoder, &ctx);
5223
5224                 if (ret == -EDEADLK) {
5225                         drm_modeset_backoff(&ctx);
5226                         continue;
5227                 }
5228
5229                 break;
5230         }
5231
5232         drm_modeset_drop_locks(&ctx);
5233         drm_modeset_acquire_fini(&ctx);
5234         drm_WARN(encoder->base.dev, ret,
5235                  "Acquiring modeset locks failed with %i\n", ret);
5236
5237         /*
5238          * Keeping it consistent with intel_ddi_hotplug() and
5239          * intel_hdmi_hotplug().
5240          */
5241         if (state == INTEL_HOTPLUG_UNCHANGED && irq_received)
5242                 state = INTEL_HOTPLUG_RETRY;
5243
5244         return state;
5245 }
5246
5247 static void intel_dp_check_service_irq(struct intel_dp *intel_dp)
5248 {
5249         u8 val;
5250
5251         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
5252                 return;
5253
5254         if (drm_dp_dpcd_readb(&intel_dp->aux,
5255                               DP_DEVICE_SERVICE_IRQ_VECTOR, &val) != 1 || !val)
5256                 return;
5257
5258         drm_dp_dpcd_writeb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, val);
5259
5260         if (val & DP_AUTOMATED_TEST_REQUEST)
5261                 intel_dp_handle_test_request(intel_dp);
5262
5263         if (val & DP_CP_IRQ)
5264                 intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
5265
5266         if (val & DP_SINK_SPECIFIC_IRQ)
5267                 DRM_DEBUG_DRIVER("Sink specific irq unhandled\n");
5268 }
5269
5270 /*
5271  * According to DP spec
5272  * 5.1.2:
5273  *  1. Read DPCD
5274  *  2. Configure link according to Receiver Capabilities
5275  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
5276  *  4. Check link status on receipt of hot-plug interrupt
5277  *
5278  * intel_dp_short_pulse -  handles short pulse interrupts
5279  * when full detection is not required.
5280  * Returns %true if short pulse is handled and full detection
5281  * is NOT required and %false otherwise.
5282  */
5283 static bool
5284 intel_dp_short_pulse(struct intel_dp *intel_dp)
5285 {
5286         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
5287         u8 old_sink_count = intel_dp->sink_count;
5288         bool ret;
5289
5290         /*
5291          * Clearing compliance test variables to allow capturing
5292          * of values for next automated test request.
5293          */
5294         memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
5295
5296         /*
5297          * Now read the DPCD to see if it's actually running
5298          * If the current value of sink count doesn't match with
5299          * the value that was stored earlier or dpcd read failed
5300          * we need to do full detection
5301          */
5302         ret = intel_dp_get_dpcd(intel_dp);
5303
5304         if ((old_sink_count != intel_dp->sink_count) || !ret) {
5305                 /* No need to proceed if we are going to do full detect */
5306                 return false;
5307         }
5308
5309         intel_dp_check_service_irq(intel_dp);
5310
5311         /* Handle CEC interrupts, if any */
5312         drm_dp_cec_irq(&intel_dp->aux);
5313
5314         /* defer to the hotplug work for link retraining if needed */
5315         if (intel_dp_needs_link_retrain(intel_dp))
5316                 return false;
5317
5318         intel_psr_short_pulse(intel_dp);
5319
5320         if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
5321                 drm_dbg_kms(&dev_priv->drm,
5322                             "Link Training Compliance Test requested\n");
5323                 /* Send a Hotplug Uevent to userspace to start modeset */
5324                 drm_kms_helper_hotplug_event(&dev_priv->drm);
5325         }
5326
5327         return true;
5328 }
5329
5330 /* XXX this is probably wrong for multiple downstream ports */
5331 static enum drm_connector_status
5332 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
5333 {
5334         struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
5335         u8 *dpcd = intel_dp->dpcd;
5336         u8 type;
5337
5338         if (WARN_ON(intel_dp_is_edp(intel_dp)))
5339                 return connector_status_connected;
5340
5341         if (lspcon->active)
5342                 lspcon_resume(lspcon);
5343
5344         if (!intel_dp_get_dpcd(intel_dp))
5345                 return connector_status_disconnected;
5346
5347         /* if there's no downstream port, we're done */
5348         if (!drm_dp_is_branch(dpcd))
5349                 return connector_status_connected;
5350
5351         /* If we're HPD-aware, SINK_COUNT changes dynamically */
5352         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
5353             intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
5354
5355                 return intel_dp->sink_count ?
5356                 connector_status_connected : connector_status_disconnected;
5357         }
5358
5359         if (intel_dp_can_mst(intel_dp))
5360                 return connector_status_connected;
5361
5362         /* If no HPD, poke DDC gently */
5363         if (drm_probe_ddc(&intel_dp->aux.ddc))
5364                 return connector_status_connected;
5365
5366         /* Well we tried, say unknown for unreliable port types */
5367         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
5368                 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
5369                 if (type == DP_DS_PORT_TYPE_VGA ||
5370                     type == DP_DS_PORT_TYPE_NON_EDID)
5371                         return connector_status_unknown;
5372         } else {
5373                 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
5374                         DP_DWN_STRM_PORT_TYPE_MASK;
5375                 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
5376                     type == DP_DWN_STRM_PORT_TYPE_OTHER)
5377                         return connector_status_unknown;
5378         }
5379
5380         /* Anything else is out of spec, warn and ignore */
5381         DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
5382         return connector_status_disconnected;
5383 }
5384
5385 static enum drm_connector_status
5386 edp_detect(struct intel_dp *intel_dp)
5387 {
5388         return connector_status_connected;
5389 }
5390
5391 static bool ibx_digital_port_connected(struct intel_encoder *encoder)
5392 {
5393         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5394         u32 bit;
5395
5396         switch (encoder->hpd_pin) {
5397         case HPD_PORT_B:
5398                 bit = SDE_PORTB_HOTPLUG;
5399                 break;
5400         case HPD_PORT_C:
5401                 bit = SDE_PORTC_HOTPLUG;
5402                 break;
5403         case HPD_PORT_D:
5404                 bit = SDE_PORTD_HOTPLUG;
5405                 break;
5406         default:
5407                 MISSING_CASE(encoder->hpd_pin);
5408                 return false;
5409         }
5410
5411         return intel_de_read(dev_priv, SDEISR) & bit;
5412 }
5413
5414 static bool cpt_digital_port_connected(struct intel_encoder *encoder)
5415 {
5416         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5417         u32 bit;
5418
5419         switch (encoder->hpd_pin) {
5420         case HPD_PORT_B:
5421                 bit = SDE_PORTB_HOTPLUG_CPT;
5422                 break;
5423         case HPD_PORT_C:
5424                 bit = SDE_PORTC_HOTPLUG_CPT;
5425                 break;
5426         case HPD_PORT_D:
5427                 bit = SDE_PORTD_HOTPLUG_CPT;
5428                 break;
5429         default:
5430                 MISSING_CASE(encoder->hpd_pin);
5431                 return false;
5432         }
5433
5434         return intel_de_read(dev_priv, SDEISR) & bit;
5435 }
5436
5437 static bool spt_digital_port_connected(struct intel_encoder *encoder)
5438 {
5439         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5440         u32 bit;
5441
5442         switch (encoder->hpd_pin) {
5443         case HPD_PORT_A:
5444                 bit = SDE_PORTA_HOTPLUG_SPT;
5445                 break;
5446         case HPD_PORT_E:
5447                 bit = SDE_PORTE_HOTPLUG_SPT;
5448                 break;
5449         default:
5450                 return cpt_digital_port_connected(encoder);
5451         }
5452
5453         return intel_de_read(dev_priv, SDEISR) & bit;
5454 }
5455
5456 static bool g4x_digital_port_connected(struct intel_encoder *encoder)
5457 {
5458         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5459         u32 bit;
5460
5461         switch (encoder->hpd_pin) {
5462         case HPD_PORT_B:
5463                 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
5464                 break;
5465         case HPD_PORT_C:
5466                 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
5467                 break;
5468         case HPD_PORT_D:
5469                 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
5470                 break;
5471         default:
5472                 MISSING_CASE(encoder->hpd_pin);
5473                 return false;
5474         }
5475
5476         return intel_de_read(dev_priv, PORT_HOTPLUG_STAT) & bit;
5477 }
5478
5479 static bool gm45_digital_port_connected(struct intel_encoder *encoder)
5480 {
5481         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5482         u32 bit;
5483
5484         switch (encoder->hpd_pin) {
5485         case HPD_PORT_B:
5486                 bit = PORTB_HOTPLUG_LIVE_STATUS_GM45;
5487                 break;
5488         case HPD_PORT_C:
5489                 bit = PORTC_HOTPLUG_LIVE_STATUS_GM45;
5490                 break;
5491         case HPD_PORT_D:
5492                 bit = PORTD_HOTPLUG_LIVE_STATUS_GM45;
5493                 break;
5494         default:
5495                 MISSING_CASE(encoder->hpd_pin);
5496                 return false;
5497         }
5498
5499         return intel_de_read(dev_priv, PORT_HOTPLUG_STAT) & bit;
5500 }
5501
5502 static bool ilk_digital_port_connected(struct intel_encoder *encoder)
5503 {
5504         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5505
5506         if (encoder->hpd_pin == HPD_PORT_A)
5507                 return intel_de_read(dev_priv, DEISR) & DE_DP_A_HOTPLUG;
5508         else
5509                 return ibx_digital_port_connected(encoder);
5510 }
5511
5512 static bool snb_digital_port_connected(struct intel_encoder *encoder)
5513 {
5514         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5515
5516         if (encoder->hpd_pin == HPD_PORT_A)
5517                 return intel_de_read(dev_priv, DEISR) & DE_DP_A_HOTPLUG;
5518         else
5519                 return cpt_digital_port_connected(encoder);
5520 }
5521
5522 static bool ivb_digital_port_connected(struct intel_encoder *encoder)
5523 {
5524         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5525
5526         if (encoder->hpd_pin == HPD_PORT_A)
5527                 return intel_de_read(dev_priv, DEISR) & DE_DP_A_HOTPLUG_IVB;
5528         else
5529                 return cpt_digital_port_connected(encoder);
5530 }
5531
5532 static bool bdw_digital_port_connected(struct intel_encoder *encoder)
5533 {
5534         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5535
5536         if (encoder->hpd_pin == HPD_PORT_A)
5537                 return intel_de_read(dev_priv, GEN8_DE_PORT_ISR) & GEN8_PORT_DP_A_HOTPLUG;
5538         else
5539                 return cpt_digital_port_connected(encoder);
5540 }
5541
5542 static bool bxt_digital_port_connected(struct intel_encoder *encoder)
5543 {
5544         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5545         u32 bit;
5546
5547         switch (encoder->hpd_pin) {
5548         case HPD_PORT_A:
5549                 bit = BXT_DE_PORT_HP_DDIA;
5550                 break;
5551         case HPD_PORT_B:
5552                 bit = BXT_DE_PORT_HP_DDIB;
5553                 break;
5554         case HPD_PORT_C:
5555                 bit = BXT_DE_PORT_HP_DDIC;
5556                 break;
5557         default:
5558                 MISSING_CASE(encoder->hpd_pin);
5559                 return false;
5560         }
5561
5562         return intel_de_read(dev_priv, GEN8_DE_PORT_ISR) & bit;
5563 }
5564
5565 static bool intel_combo_phy_connected(struct drm_i915_private *dev_priv,
5566                                       enum phy phy)
5567 {
5568         if (HAS_PCH_MCC(dev_priv) && phy == PHY_C)
5569                 return intel_de_read(dev_priv, SDEISR) & SDE_TC_HOTPLUG_ICP(PORT_TC1);
5570
5571         return intel_de_read(dev_priv, SDEISR) & SDE_DDI_HOTPLUG_ICP(phy);
5572 }
5573
5574 static bool icp_digital_port_connected(struct intel_encoder *encoder)
5575 {
5576         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5577         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
5578         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
5579
5580         if (intel_phy_is_combo(dev_priv, phy))
5581                 return intel_combo_phy_connected(dev_priv, phy);
5582         else if (intel_phy_is_tc(dev_priv, phy))
5583                 return intel_tc_port_connected(dig_port);
5584         else
5585                 MISSING_CASE(encoder->hpd_pin);
5586
5587         return false;
5588 }
5589
5590 /*
5591  * intel_digital_port_connected - is the specified port connected?
5592  * @encoder: intel_encoder
5593  *
5594  * In cases where there's a connector physically connected but it can't be used
5595  * by our hardware we also return false, since the rest of the driver should
5596  * pretty much treat the port as disconnected. This is relevant for type-C
5597  * (starting on ICL) where there's ownership involved.
5598  *
5599  * Return %true if port is connected, %false otherwise.
5600  */
5601 static bool __intel_digital_port_connected(struct intel_encoder *encoder)
5602 {
5603         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5604
5605         if (HAS_GMCH(dev_priv)) {
5606                 if (IS_GM45(dev_priv))
5607                         return gm45_digital_port_connected(encoder);
5608                 else
5609                         return g4x_digital_port_connected(encoder);
5610         }
5611
5612         if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
5613                 return icp_digital_port_connected(encoder);
5614         else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
5615                 return spt_digital_port_connected(encoder);
5616         else if (IS_GEN9_LP(dev_priv))
5617                 return bxt_digital_port_connected(encoder);
5618         else if (IS_GEN(dev_priv, 8))
5619                 return bdw_digital_port_connected(encoder);
5620         else if (IS_GEN(dev_priv, 7))
5621                 return ivb_digital_port_connected(encoder);
5622         else if (IS_GEN(dev_priv, 6))
5623                 return snb_digital_port_connected(encoder);
5624         else if (IS_GEN(dev_priv, 5))
5625                 return ilk_digital_port_connected(encoder);
5626
5627         MISSING_CASE(INTEL_GEN(dev_priv));
5628         return false;
5629 }
5630
5631 bool intel_digital_port_connected(struct intel_encoder *encoder)
5632 {
5633         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5634         bool is_connected = false;
5635         intel_wakeref_t wakeref;
5636
5637         with_intel_display_power(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref)
5638                 is_connected = __intel_digital_port_connected(encoder);
5639
5640         return is_connected;
5641 }
5642
5643 static struct edid *
5644 intel_dp_get_edid(struct intel_dp *intel_dp)
5645 {
5646         struct intel_connector *intel_connector = intel_dp->attached_connector;
5647
5648         /* use cached edid if we have one */
5649         if (intel_connector->edid) {
5650                 /* invalid edid */
5651                 if (IS_ERR(intel_connector->edid))
5652                         return NULL;
5653
5654                 return drm_edid_duplicate(intel_connector->edid);
5655         } else
5656                 return drm_get_edid(&intel_connector->base,
5657                                     &intel_dp->aux.ddc);
5658 }
5659
5660 static void
5661 intel_dp_set_edid(struct intel_dp *intel_dp)
5662 {
5663         struct intel_connector *intel_connector = intel_dp->attached_connector;
5664         struct edid *edid;
5665
5666         intel_dp_unset_edid(intel_dp);
5667         edid = intel_dp_get_edid(intel_dp);
5668         intel_connector->detect_edid = edid;
5669
5670         intel_dp->has_audio = drm_detect_monitor_audio(edid);
5671         drm_dp_cec_set_edid(&intel_dp->aux, edid);
5672 }
5673
5674 static void
5675 intel_dp_unset_edid(struct intel_dp *intel_dp)
5676 {
5677         struct intel_connector *intel_connector = intel_dp->attached_connector;
5678
5679         drm_dp_cec_unset_edid(&intel_dp->aux);
5680         kfree(intel_connector->detect_edid);
5681         intel_connector->detect_edid = NULL;
5682
5683         intel_dp->has_audio = false;
5684 }
5685
5686 static int
5687 intel_dp_detect(struct drm_connector *connector,
5688                 struct drm_modeset_acquire_ctx *ctx,
5689                 bool force)
5690 {
5691         struct drm_i915_private *dev_priv = to_i915(connector->dev);
5692         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
5693         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5694         struct intel_encoder *encoder = &dig_port->base;
5695         enum drm_connector_status status;
5696
5697         drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
5698                     connector->base.id, connector->name);
5699         WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
5700
5701         /* Can't disconnect eDP */
5702         if (intel_dp_is_edp(intel_dp))
5703                 status = edp_detect(intel_dp);
5704         else if (intel_digital_port_connected(encoder))
5705                 status = intel_dp_detect_dpcd(intel_dp);
5706         else
5707                 status = connector_status_disconnected;
5708
5709         if (status == connector_status_disconnected) {
5710                 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
5711                 memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
5712
5713                 if (intel_dp->is_mst) {
5714                         drm_dbg_kms(&dev_priv->drm,
5715                                     "MST device may have disappeared %d vs %d\n",
5716                                     intel_dp->is_mst,
5717                                     intel_dp->mst_mgr.mst_state);
5718                         intel_dp->is_mst = false;
5719                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
5720                                                         intel_dp->is_mst);
5721                 }
5722
5723                 goto out;
5724         }
5725
5726         if (intel_dp->reset_link_params) {
5727                 /* Initial max link lane count */
5728                 intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
5729
5730                 /* Initial max link rate */
5731                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
5732
5733                 intel_dp->reset_link_params = false;
5734         }
5735
5736         intel_dp_print_rates(intel_dp);
5737
5738         /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */
5739         if (INTEL_GEN(dev_priv) >= 11)
5740                 intel_dp_get_dsc_sink_cap(intel_dp);
5741
5742         intel_dp_configure_mst(intel_dp);
5743
5744         if (intel_dp->is_mst) {
5745                 /*
5746                  * If we are in MST mode then this connector
5747                  * won't appear connected or have anything
5748                  * with EDID on it
5749                  */
5750                 status = connector_status_disconnected;
5751                 goto out;
5752         }
5753
5754         /*
5755          * Some external monitors do not signal loss of link synchronization
5756          * with an IRQ_HPD, so force a link status check.
5757          */
5758         if (!intel_dp_is_edp(intel_dp)) {
5759                 int ret;
5760
5761                 ret = intel_dp_retrain_link(encoder, ctx);
5762                 if (ret)
5763                         return ret;
5764         }
5765
5766         /*
5767          * Clearing NACK and defer counts to get their exact values
5768          * while reading EDID which are required by Compliance tests
5769          * 4.2.2.4 and 4.2.2.5
5770          */
5771         intel_dp->aux.i2c_nack_count = 0;
5772         intel_dp->aux.i2c_defer_count = 0;
5773
5774         intel_dp_set_edid(intel_dp);
5775         if (intel_dp_is_edp(intel_dp) ||
5776             to_intel_connector(connector)->detect_edid)
5777                 status = connector_status_connected;
5778
5779         intel_dp_check_service_irq(intel_dp);
5780
5781 out:
5782         if (status != connector_status_connected && !intel_dp->is_mst)
5783                 intel_dp_unset_edid(intel_dp);
5784
5785         /*
5786          * Make sure the refs for power wells enabled during detect are
5787          * dropped to avoid a new detect cycle triggered by HPD polling.
5788          */
5789         intel_display_power_flush_work(dev_priv);
5790
5791         return status;
5792 }
5793
5794 static void
5795 intel_dp_force(struct drm_connector *connector)
5796 {
5797         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
5798         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5799         struct intel_encoder *intel_encoder = &dig_port->base;
5800         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
5801         enum intel_display_power_domain aux_domain =
5802                 intel_aux_power_domain(dig_port);
5803         intel_wakeref_t wakeref;
5804
5805         drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
5806                     connector->base.id, connector->name);
5807         intel_dp_unset_edid(intel_dp);
5808
5809         if (connector->status != connector_status_connected)
5810                 return;
5811
5812         wakeref = intel_display_power_get(dev_priv, aux_domain);
5813
5814         intel_dp_set_edid(intel_dp);
5815
5816         intel_display_power_put(dev_priv, aux_domain, wakeref);
5817 }
5818
5819 static int intel_dp_get_modes(struct drm_connector *connector)
5820 {
5821         struct intel_connector *intel_connector = to_intel_connector(connector);
5822         struct edid *edid;
5823
5824         edid = intel_connector->detect_edid;
5825         if (edid) {
5826                 int ret = intel_connector_update_modes(connector, edid);
5827                 if (ret)
5828                         return ret;
5829         }
5830
5831         /* if eDP has no EDID, fall back to fixed mode */
5832         if (intel_dp_is_edp(intel_attached_dp(to_intel_connector(connector))) &&
5833             intel_connector->panel.fixed_mode) {
5834                 struct drm_display_mode *mode;
5835
5836                 mode = drm_mode_duplicate(connector->dev,
5837                                           intel_connector->panel.fixed_mode);
5838                 if (mode) {
5839                         drm_mode_probed_add(connector, mode);
5840                         return 1;
5841                 }
5842         }
5843
5844         return 0;
5845 }
5846
5847 static int
5848 intel_dp_connector_register(struct drm_connector *connector)
5849 {
5850         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
5851         int ret;
5852
5853         ret = intel_connector_register(connector);
5854         if (ret)
5855                 return ret;
5856
5857         intel_connector_debugfs_add(connector);
5858
5859         DRM_DEBUG_KMS("registering %s bus for %s\n",
5860                       intel_dp->aux.name, connector->kdev->kobj.name);
5861
5862         intel_dp->aux.dev = connector->kdev;
5863         ret = drm_dp_aux_register(&intel_dp->aux);
5864         if (!ret)
5865                 drm_dp_cec_register_connector(&intel_dp->aux, connector);
5866         return ret;
5867 }
5868
5869 static void
5870 intel_dp_connector_unregister(struct drm_connector *connector)
5871 {
5872         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
5873
5874         drm_dp_cec_unregister_connector(&intel_dp->aux);
5875         drm_dp_aux_unregister(&intel_dp->aux);
5876         intel_connector_unregister(connector);
5877 }
5878
5879 void intel_dp_encoder_flush_work(struct drm_encoder *encoder)
5880 {
5881         struct intel_digital_port *intel_dig_port = enc_to_dig_port(to_intel_encoder(encoder));
5882         struct intel_dp *intel_dp = &intel_dig_port->dp;
5883
5884         intel_dp_mst_encoder_cleanup(intel_dig_port);
5885         if (intel_dp_is_edp(intel_dp)) {
5886                 intel_wakeref_t wakeref;
5887
5888                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5889                 /*
5890                  * vdd might still be enabled do to the delayed vdd off.
5891                  * Make sure vdd is actually turned off here.
5892                  */
5893                 with_pps_lock(intel_dp, wakeref)
5894                         edp_panel_vdd_off_sync(intel_dp);
5895
5896                 if (intel_dp->edp_notifier.notifier_call) {
5897                         unregister_reboot_notifier(&intel_dp->edp_notifier);
5898                         intel_dp->edp_notifier.notifier_call = NULL;
5899                 }
5900         }
5901
5902         intel_dp_aux_fini(intel_dp);
5903 }
5904
5905 static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
5906 {
5907         intel_dp_encoder_flush_work(encoder);
5908
5909         drm_encoder_cleanup(encoder);
5910         kfree(enc_to_dig_port(to_intel_encoder(encoder)));
5911 }
5912
5913 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
5914 {
5915         struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
5916         intel_wakeref_t wakeref;
5917
5918         if (!intel_dp_is_edp(intel_dp))
5919                 return;
5920
5921         /*
5922          * vdd might still be enabled do to the delayed vdd off.
5923          * Make sure vdd is actually turned off here.
5924          */
5925         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5926         with_pps_lock(intel_dp, wakeref)
5927                 edp_panel_vdd_off_sync(intel_dp);
5928 }
5929
5930 static void intel_dp_hdcp_wait_for_cp_irq(struct intel_hdcp *hdcp, int timeout)
5931 {
5932         long ret;
5933
5934 #define C (hdcp->cp_irq_count_cached != atomic_read(&hdcp->cp_irq_count))
5935         ret = wait_event_interruptible_timeout(hdcp->cp_irq_queue, C,
5936                                                msecs_to_jiffies(timeout));
5937
5938         if (!ret)
5939                 DRM_DEBUG_KMS("Timedout at waiting for CP_IRQ\n");
5940 }
5941
5942 static
5943 int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port,
5944                                 u8 *an)
5945 {
5946         struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(&intel_dig_port->base.base));
5947         static const struct drm_dp_aux_msg msg = {
5948                 .request = DP_AUX_NATIVE_WRITE,
5949                 .address = DP_AUX_HDCP_AKSV,
5950                 .size = DRM_HDCP_KSV_LEN,
5951         };
5952         u8 txbuf[HEADER_SIZE + DRM_HDCP_KSV_LEN] = {}, rxbuf[2], reply = 0;
5953         ssize_t dpcd_ret;
5954         int ret;
5955
5956         /* Output An first, that's easy */
5957         dpcd_ret = drm_dp_dpcd_write(&intel_dig_port->dp.aux, DP_AUX_HDCP_AN,
5958                                      an, DRM_HDCP_AN_LEN);
5959         if (dpcd_ret != DRM_HDCP_AN_LEN) {
5960                 DRM_DEBUG_KMS("Failed to write An over DP/AUX (%zd)\n",
5961                               dpcd_ret);
5962                 return dpcd_ret >= 0 ? -EIO : dpcd_ret;
5963         }
5964
5965         /*
5966          * Since Aksv is Oh-So-Secret, we can't access it in software. So in
5967          * order to get it on the wire, we need to create the AUX header as if
5968          * we were writing the data, and then tickle the hardware to output the
5969          * data once the header is sent out.
5970          */
5971         intel_dp_aux_header(txbuf, &msg);
5972
5973         ret = intel_dp_aux_xfer(intel_dp, txbuf, HEADER_SIZE + msg.size,
5974                                 rxbuf, sizeof(rxbuf),
5975                                 DP_AUX_CH_CTL_AUX_AKSV_SELECT);
5976         if (ret < 0) {
5977                 DRM_DEBUG_KMS("Write Aksv over DP/AUX failed (%d)\n", ret);
5978                 return ret;
5979         } else if (ret == 0) {
5980                 DRM_DEBUG_KMS("Aksv write over DP/AUX was empty\n");
5981                 return -EIO;
5982         }
5983
5984         reply = (rxbuf[0] >> 4) & DP_AUX_NATIVE_REPLY_MASK;
5985         if (reply != DP_AUX_NATIVE_REPLY_ACK) {
5986                 DRM_DEBUG_KMS("Aksv write: no DP_AUX_NATIVE_REPLY_ACK %x\n",
5987                               reply);
5988                 return -EIO;
5989         }
5990         return 0;
5991 }
5992
5993 static int intel_dp_hdcp_read_bksv(struct intel_digital_port *intel_dig_port,
5994                                    u8 *bksv)
5995 {
5996         ssize_t ret;
5997         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BKSV, bksv,
5998                                DRM_HDCP_KSV_LEN);
5999         if (ret != DRM_HDCP_KSV_LEN) {
6000                 DRM_DEBUG_KMS("Read Bksv from DP/AUX failed (%zd)\n", ret);
6001                 return ret >= 0 ? -EIO : ret;
6002         }
6003         return 0;
6004 }
6005
6006 static int intel_dp_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port,
6007                                       u8 *bstatus)
6008 {
6009         ssize_t ret;
6010         /*
6011          * For some reason the HDMI and DP HDCP specs call this register
6012          * definition by different names. In the HDMI spec, it's called BSTATUS,
6013          * but in DP it's called BINFO.
6014          */
6015         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BINFO,
6016                                bstatus, DRM_HDCP_BSTATUS_LEN);
6017         if (ret != DRM_HDCP_BSTATUS_LEN) {
6018                 DRM_DEBUG_KMS("Read bstatus from DP/AUX failed (%zd)\n", ret);
6019                 return ret >= 0 ? -EIO : ret;
6020         }
6021         return 0;
6022 }
6023
6024 static
6025 int intel_dp_hdcp_read_bcaps(struct intel_digital_port *intel_dig_port,
6026                              u8 *bcaps)
6027 {
6028         ssize_t ret;
6029
6030         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BCAPS,
6031                                bcaps, 1);
6032         if (ret != 1) {
6033                 DRM_DEBUG_KMS("Read bcaps from DP/AUX failed (%zd)\n", ret);
6034                 return ret >= 0 ? -EIO : ret;
6035         }
6036
6037         return 0;
6038 }
6039
6040 static
6041 int intel_dp_hdcp_repeater_present(struct intel_digital_port *intel_dig_port,
6042                                    bool *repeater_present)
6043 {
6044         ssize_t ret;
6045         u8 bcaps;
6046
6047         ret = intel_dp_hdcp_read_bcaps(intel_dig_port, &bcaps);
6048         if (ret)
6049                 return ret;
6050
6051         *repeater_present = bcaps & DP_BCAPS_REPEATER_PRESENT;
6052         return 0;
6053 }
6054
6055 static
6056 int intel_dp_hdcp_read_ri_prime(struct intel_digital_port *intel_dig_port,
6057                                 u8 *ri_prime)
6058 {
6059         ssize_t ret;
6060         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_RI_PRIME,
6061                                ri_prime, DRM_HDCP_RI_LEN);
6062         if (ret != DRM_HDCP_RI_LEN) {
6063                 DRM_DEBUG_KMS("Read Ri' from DP/AUX failed (%zd)\n", ret);
6064                 return ret >= 0 ? -EIO : ret;
6065         }
6066         return 0;
6067 }
6068
6069 static
6070 int intel_dp_hdcp_read_ksv_ready(struct intel_digital_port *intel_dig_port,
6071                                  bool *ksv_ready)
6072 {
6073         ssize_t ret;
6074         u8 bstatus;
6075         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
6076                                &bstatus, 1);
6077         if (ret != 1) {
6078                 DRM_DEBUG_KMS("Read bstatus from DP/AUX failed (%zd)\n", ret);
6079                 return ret >= 0 ? -EIO : ret;
6080         }
6081         *ksv_ready = bstatus & DP_BSTATUS_READY;
6082         return 0;
6083 }
6084
6085 static
6086 int intel_dp_hdcp_read_ksv_fifo(struct intel_digital_port *intel_dig_port,
6087                                 int num_downstream, u8 *ksv_fifo)
6088 {
6089         ssize_t ret;
6090         int i;
6091
6092         /* KSV list is read via 15 byte window (3 entries @ 5 bytes each) */
6093         for (i = 0; i < num_downstream; i += 3) {
6094                 size_t len = min(num_downstream - i, 3) * DRM_HDCP_KSV_LEN;
6095                 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
6096                                        DP_AUX_HDCP_KSV_FIFO,
6097                                        ksv_fifo + i * DRM_HDCP_KSV_LEN,
6098                                        len);
6099                 if (ret != len) {
6100                         DRM_DEBUG_KMS("Read ksv[%d] from DP/AUX failed (%zd)\n",
6101                                       i, ret);
6102                         return ret >= 0 ? -EIO : ret;
6103                 }
6104         }
6105         return 0;
6106 }
6107
6108 static
6109 int intel_dp_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port,
6110                                     int i, u32 *part)
6111 {
6112         ssize_t ret;
6113
6114         if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
6115                 return -EINVAL;
6116
6117         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
6118                                DP_AUX_HDCP_V_PRIME(i), part,
6119                                DRM_HDCP_V_PRIME_PART_LEN);
6120         if (ret != DRM_HDCP_V_PRIME_PART_LEN) {
6121                 DRM_DEBUG_KMS("Read v'[%d] from DP/AUX failed (%zd)\n", i, ret);
6122                 return ret >= 0 ? -EIO : ret;
6123         }
6124         return 0;
6125 }
6126
6127 static
6128 int intel_dp_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port,
6129                                     bool enable)
6130 {
6131         /* Not used for single stream DisplayPort setups */
6132         return 0;
6133 }
6134
6135 static
6136 bool intel_dp_hdcp_check_link(struct intel_digital_port *intel_dig_port)
6137 {
6138         ssize_t ret;
6139         u8 bstatus;
6140
6141         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
6142                                &bstatus, 1);
6143         if (ret != 1) {
6144                 DRM_DEBUG_KMS("Read bstatus from DP/AUX failed (%zd)\n", ret);
6145                 return false;
6146         }
6147
6148         return !(bstatus & (DP_BSTATUS_LINK_FAILURE | DP_BSTATUS_REAUTH_REQ));
6149 }
6150
6151 static
6152 int intel_dp_hdcp_capable(struct intel_digital_port *intel_dig_port,
6153                           bool *hdcp_capable)
6154 {
6155         ssize_t ret;
6156         u8 bcaps;
6157
6158         ret = intel_dp_hdcp_read_bcaps(intel_dig_port, &bcaps);
6159         if (ret)
6160                 return ret;
6161
6162         *hdcp_capable = bcaps & DP_BCAPS_HDCP_CAPABLE;
6163         return 0;
6164 }
6165
6166 struct hdcp2_dp_errata_stream_type {
6167         u8      msg_id;
6168         u8      stream_type;
6169 } __packed;
6170
6171 struct hdcp2_dp_msg_data {
6172         u8 msg_id;
6173         u32 offset;
6174         bool msg_detectable;
6175         u32 timeout;
6176         u32 timeout2; /* Added for non_paired situation */
6177 };
6178
6179 static const struct hdcp2_dp_msg_data hdcp2_dp_msg_data[] = {
6180         { HDCP_2_2_AKE_INIT, DP_HDCP_2_2_AKE_INIT_OFFSET, false, 0, 0 },
6181         { HDCP_2_2_AKE_SEND_CERT, DP_HDCP_2_2_AKE_SEND_CERT_OFFSET,
6182           false, HDCP_2_2_CERT_TIMEOUT_MS, 0 },
6183         { HDCP_2_2_AKE_NO_STORED_KM, DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET,
6184           false, 0, 0 },
6185         { HDCP_2_2_AKE_STORED_KM, DP_HDCP_2_2_AKE_STORED_KM_OFFSET,
6186           false, 0, 0 },
6187         { HDCP_2_2_AKE_SEND_HPRIME, DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET,
6188           true, HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS,
6189           HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS },
6190         { HDCP_2_2_AKE_SEND_PAIRING_INFO,
6191           DP_HDCP_2_2_AKE_SEND_PAIRING_INFO_OFFSET, true,
6192           HDCP_2_2_PAIRING_TIMEOUT_MS, 0 },
6193         { HDCP_2_2_LC_INIT, DP_HDCP_2_2_LC_INIT_OFFSET, false, 0, 0 },
6194         { HDCP_2_2_LC_SEND_LPRIME, DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET,
6195           false, HDCP_2_2_DP_LPRIME_TIMEOUT_MS, 0 },
6196         { HDCP_2_2_SKE_SEND_EKS, DP_HDCP_2_2_SKE_SEND_EKS_OFFSET, false,
6197           0, 0 },
6198         { HDCP_2_2_REP_SEND_RECVID_LIST,
6199           DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET, true,
6200           HDCP_2_2_RECVID_LIST_TIMEOUT_MS, 0 },
6201         { HDCP_2_2_REP_SEND_ACK, DP_HDCP_2_2_REP_SEND_ACK_OFFSET, false,
6202           0, 0 },
6203         { HDCP_2_2_REP_STREAM_MANAGE,
6204           DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET, false,
6205           0, 0 },
6206         { HDCP_2_2_REP_STREAM_READY, DP_HDCP_2_2_REP_STREAM_READY_OFFSET,
6207           false, HDCP_2_2_STREAM_READY_TIMEOUT_MS, 0 },
6208 /* local define to shovel this through the write_2_2 interface */
6209 #define HDCP_2_2_ERRATA_DP_STREAM_TYPE  50
6210         { HDCP_2_2_ERRATA_DP_STREAM_TYPE,
6211           DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET, false,
6212           0, 0 },
6213 };
6214
6215 static inline
6216 int intel_dp_hdcp2_read_rx_status(struct intel_digital_port *intel_dig_port,
6217                                   u8 *rx_status)
6218 {
6219         ssize_t ret;
6220
6221         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
6222                                DP_HDCP_2_2_REG_RXSTATUS_OFFSET, rx_status,
6223                                HDCP_2_2_DP_RXSTATUS_LEN);
6224         if (ret != HDCP_2_2_DP_RXSTATUS_LEN) {
6225                 DRM_DEBUG_KMS("Read bstatus from DP/AUX failed (%zd)\n", ret);
6226                 return ret >= 0 ? -EIO : ret;
6227         }
6228
6229         return 0;
6230 }
6231
6232 static
6233 int hdcp2_detect_msg_availability(struct intel_digital_port *intel_dig_port,
6234                                   u8 msg_id, bool *msg_ready)
6235 {
6236         u8 rx_status;
6237         int ret;
6238
6239         *msg_ready = false;
6240         ret = intel_dp_hdcp2_read_rx_status(intel_dig_port, &rx_status);
6241         if (ret < 0)
6242                 return ret;
6243
6244         switch (msg_id) {
6245         case HDCP_2_2_AKE_SEND_HPRIME:
6246                 if (HDCP_2_2_DP_RXSTATUS_H_PRIME(rx_status))
6247                         *msg_ready = true;
6248                 break;
6249         case HDCP_2_2_AKE_SEND_PAIRING_INFO:
6250                 if (HDCP_2_2_DP_RXSTATUS_PAIRING(rx_status))
6251                         *msg_ready = true;
6252                 break;
6253         case HDCP_2_2_REP_SEND_RECVID_LIST:
6254                 if (HDCP_2_2_DP_RXSTATUS_READY(rx_status))
6255                         *msg_ready = true;
6256                 break;
6257         default:
6258                 DRM_ERROR("Unidentified msg_id: %d\n", msg_id);
6259                 return -EINVAL;
6260         }
6261
6262         return 0;
6263 }
6264
6265 static ssize_t
6266 intel_dp_hdcp2_wait_for_msg(struct intel_digital_port *intel_dig_port,
6267                             const struct hdcp2_dp_msg_data *hdcp2_msg_data)
6268 {
6269         struct intel_dp *dp = &intel_dig_port->dp;
6270         struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
6271         u8 msg_id = hdcp2_msg_data->msg_id;
6272         int ret, timeout;
6273         bool msg_ready = false;
6274
6275         if (msg_id == HDCP_2_2_AKE_SEND_HPRIME && !hdcp->is_paired)
6276                 timeout = hdcp2_msg_data->timeout2;
6277         else
6278                 timeout = hdcp2_msg_data->timeout;
6279
6280         /*
6281          * There is no way to detect the CERT, LPRIME and STREAM_READY
6282          * availability. So Wait for timeout and read the msg.
6283          */
6284         if (!hdcp2_msg_data->msg_detectable) {
6285                 mdelay(timeout);
6286                 ret = 0;
6287         } else {
6288                 /*
6289                  * As we want to check the msg availability at timeout, Ignoring
6290                  * the timeout at wait for CP_IRQ.
6291                  */
6292                 intel_dp_hdcp_wait_for_cp_irq(hdcp, timeout);
6293                 ret = hdcp2_detect_msg_availability(intel_dig_port,
6294                                                     msg_id, &msg_ready);
6295                 if (!msg_ready)
6296                         ret = -ETIMEDOUT;
6297         }
6298
6299         if (ret)
6300                 DRM_DEBUG_KMS("msg_id %d, ret %d, timeout(mSec): %d\n",
6301                               hdcp2_msg_data->msg_id, ret, timeout);
6302
6303         return ret;
6304 }
6305
6306 static const struct hdcp2_dp_msg_data *get_hdcp2_dp_msg_data(u8 msg_id)
6307 {
6308         int i;
6309
6310         for (i = 0; i < ARRAY_SIZE(hdcp2_dp_msg_data); i++)
6311                 if (hdcp2_dp_msg_data[i].msg_id == msg_id)
6312                         return &hdcp2_dp_msg_data[i];
6313
6314         return NULL;
6315 }
6316
6317 static
6318 int intel_dp_hdcp2_write_msg(struct intel_digital_port *intel_dig_port,
6319                              void *buf, size_t size)
6320 {
6321         struct intel_dp *dp = &intel_dig_port->dp;
6322         struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
6323         unsigned int offset;
6324         u8 *byte = buf;
6325         ssize_t ret, bytes_to_write, len;
6326         const struct hdcp2_dp_msg_data *hdcp2_msg_data;
6327
6328         hdcp2_msg_data = get_hdcp2_dp_msg_data(*byte);
6329         if (!hdcp2_msg_data)
6330                 return -EINVAL;
6331
6332         offset = hdcp2_msg_data->offset;
6333
6334         /* No msg_id in DP HDCP2.2 msgs */
6335         bytes_to_write = size - 1;
6336         byte++;
6337
6338         hdcp->cp_irq_count_cached = atomic_read(&hdcp->cp_irq_count);
6339
6340         while (bytes_to_write) {
6341                 len = bytes_to_write > DP_AUX_MAX_PAYLOAD_BYTES ?
6342                                 DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_write;
6343
6344                 ret = drm_dp_dpcd_write(&intel_dig_port->dp.aux,
6345                                         offset, (void *)byte, len);
6346                 if (ret < 0)
6347                         return ret;
6348
6349                 bytes_to_write -= ret;
6350                 byte += ret;
6351                 offset += ret;
6352         }
6353
6354         return size;
6355 }
6356
6357 static
6358 ssize_t get_receiver_id_list_size(struct intel_digital_port *intel_dig_port)
6359 {
6360         u8 rx_info[HDCP_2_2_RXINFO_LEN];
6361         u32 dev_cnt;
6362         ssize_t ret;
6363
6364         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
6365                                DP_HDCP_2_2_REG_RXINFO_OFFSET,
6366                                (void *)rx_info, HDCP_2_2_RXINFO_LEN);
6367         if (ret != HDCP_2_2_RXINFO_LEN)
6368                 return ret >= 0 ? -EIO : ret;
6369
6370         dev_cnt = (HDCP_2_2_DEV_COUNT_HI(rx_info[0]) << 4 |
6371                    HDCP_2_2_DEV_COUNT_LO(rx_info[1]));
6372
6373         if (dev_cnt > HDCP_2_2_MAX_DEVICE_COUNT)
6374                 dev_cnt = HDCP_2_2_MAX_DEVICE_COUNT;
6375
6376         ret = sizeof(struct hdcp2_rep_send_receiverid_list) -
6377                 HDCP_2_2_RECEIVER_IDS_MAX_LEN +
6378                 (dev_cnt * HDCP_2_2_RECEIVER_ID_LEN);
6379
6380         return ret;
6381 }
6382
6383 static
6384 int intel_dp_hdcp2_read_msg(struct intel_digital_port *intel_dig_port,
6385                             u8 msg_id, void *buf, size_t size)
6386 {
6387         unsigned int offset;
6388         u8 *byte = buf;
6389         ssize_t ret, bytes_to_recv, len;
6390         const struct hdcp2_dp_msg_data *hdcp2_msg_data;
6391
6392         hdcp2_msg_data = get_hdcp2_dp_msg_data(msg_id);
6393         if (!hdcp2_msg_data)
6394                 return -EINVAL;
6395         offset = hdcp2_msg_data->offset;
6396
6397         ret = intel_dp_hdcp2_wait_for_msg(intel_dig_port, hdcp2_msg_data);
6398         if (ret < 0)
6399                 return ret;
6400
6401         if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST) {
6402                 ret = get_receiver_id_list_size(intel_dig_port);
6403                 if (ret < 0)
6404                         return ret;
6405
6406                 size = ret;
6407         }
6408         bytes_to_recv = size - 1;
6409
6410         /* DP adaptation msgs has no msg_id */
6411         byte++;
6412
6413         while (bytes_to_recv) {
6414                 len = bytes_to_recv > DP_AUX_MAX_PAYLOAD_BYTES ?
6415                       DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_recv;
6416
6417                 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, offset,
6418                                        (void *)byte, len);
6419                 if (ret < 0) {
6420                         DRM_DEBUG_KMS("msg_id %d, ret %zd\n", msg_id, ret);
6421                         return ret;
6422                 }
6423
6424                 bytes_to_recv -= ret;
6425                 byte += ret;
6426                 offset += ret;
6427         }
6428         byte = buf;
6429         *byte = msg_id;
6430
6431         return size;
6432 }
6433
6434 static
6435 int intel_dp_hdcp2_config_stream_type(struct intel_digital_port *intel_dig_port,
6436                                       bool is_repeater, u8 content_type)
6437 {
6438         struct hdcp2_dp_errata_stream_type stream_type_msg;
6439
6440         if (is_repeater)
6441                 return 0;
6442
6443         /*
6444          * Errata for DP: As Stream type is used for encryption, Receiver
6445          * should be communicated with stream type for the decryption of the
6446          * content.
6447          * Repeater will be communicated with stream type as a part of it's
6448          * auth later in time.
6449          */
6450         stream_type_msg.msg_id = HDCP_2_2_ERRATA_DP_STREAM_TYPE;
6451         stream_type_msg.stream_type = content_type;
6452
6453         return intel_dp_hdcp2_write_msg(intel_dig_port, &stream_type_msg,
6454                                         sizeof(stream_type_msg));
6455 }
6456
6457 static
6458 int intel_dp_hdcp2_check_link(struct intel_digital_port *intel_dig_port)
6459 {
6460         u8 rx_status;
6461         int ret;
6462
6463         ret = intel_dp_hdcp2_read_rx_status(intel_dig_port, &rx_status);
6464         if (ret)
6465                 return ret;
6466
6467         if (HDCP_2_2_DP_RXSTATUS_REAUTH_REQ(rx_status))
6468                 ret = HDCP_REAUTH_REQUEST;
6469         else if (HDCP_2_2_DP_RXSTATUS_LINK_FAILED(rx_status))
6470                 ret = HDCP_LINK_INTEGRITY_FAILURE;
6471         else if (HDCP_2_2_DP_RXSTATUS_READY(rx_status))
6472                 ret = HDCP_TOPOLOGY_CHANGE;
6473
6474         return ret;
6475 }
6476
6477 static
6478 int intel_dp_hdcp2_capable(struct intel_digital_port *intel_dig_port,
6479                            bool *capable)
6480 {
6481         u8 rx_caps[3];
6482         int ret;
6483
6484         *capable = false;
6485         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
6486                                DP_HDCP_2_2_REG_RX_CAPS_OFFSET,
6487                                rx_caps, HDCP_2_2_RXCAPS_LEN);
6488         if (ret != HDCP_2_2_RXCAPS_LEN)
6489                 return ret >= 0 ? -EIO : ret;
6490
6491         if (rx_caps[0] == HDCP_2_2_RX_CAPS_VERSION_VAL &&
6492             HDCP_2_2_DP_HDCP_CAPABLE(rx_caps[2]))
6493                 *capable = true;
6494
6495         return 0;
6496 }
6497
6498 static const struct intel_hdcp_shim intel_dp_hdcp_shim = {
6499         .write_an_aksv = intel_dp_hdcp_write_an_aksv,
6500         .read_bksv = intel_dp_hdcp_read_bksv,
6501         .read_bstatus = intel_dp_hdcp_read_bstatus,
6502         .repeater_present = intel_dp_hdcp_repeater_present,
6503         .read_ri_prime = intel_dp_hdcp_read_ri_prime,
6504         .read_ksv_ready = intel_dp_hdcp_read_ksv_ready,
6505         .read_ksv_fifo = intel_dp_hdcp_read_ksv_fifo,
6506         .read_v_prime_part = intel_dp_hdcp_read_v_prime_part,
6507         .toggle_signalling = intel_dp_hdcp_toggle_signalling,
6508         .check_link = intel_dp_hdcp_check_link,
6509         .hdcp_capable = intel_dp_hdcp_capable,
6510         .write_2_2_msg = intel_dp_hdcp2_write_msg,
6511         .read_2_2_msg = intel_dp_hdcp2_read_msg,
6512         .config_stream_type = intel_dp_hdcp2_config_stream_type,
6513         .check_2_2_link = intel_dp_hdcp2_check_link,
6514         .hdcp_2_2_capable = intel_dp_hdcp2_capable,
6515         .protocol = HDCP_PROTOCOL_DP,
6516 };
6517
6518 static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
6519 {
6520         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6521         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
6522
6523         lockdep_assert_held(&dev_priv->pps_mutex);
6524
6525         if (!edp_have_panel_vdd(intel_dp))
6526                 return;
6527
6528         /*
6529          * The VDD bit needs a power domain reference, so if the bit is
6530          * already enabled when we boot or resume, grab this reference and
6531          * schedule a vdd off, so we don't hold on to the reference
6532          * indefinitely.
6533          */
6534         drm_dbg_kms(&dev_priv->drm,
6535                     "VDD left on by BIOS, adjusting state tracking\n");
6536         intel_display_power_get(dev_priv, intel_aux_power_domain(dig_port));
6537
6538         edp_panel_vdd_schedule_off(intel_dp);
6539 }
6540
6541 static enum pipe vlv_active_pipe(struct intel_dp *intel_dp)
6542 {
6543         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6544         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
6545         enum pipe pipe;
6546
6547         if (intel_dp_port_enabled(dev_priv, intel_dp->output_reg,
6548                                   encoder->port, &pipe))
6549                 return pipe;
6550
6551         return INVALID_PIPE;
6552 }
6553
6554 void intel_dp_encoder_reset(struct drm_encoder *encoder)
6555 {
6556         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
6557         struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder));
6558         struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
6559         intel_wakeref_t wakeref;
6560
6561         if (!HAS_DDI(dev_priv))
6562                 intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
6563
6564         if (lspcon->active)
6565                 lspcon_resume(lspcon);
6566
6567         intel_dp->reset_link_params = true;
6568
6569         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
6570             !intel_dp_is_edp(intel_dp))
6571                 return;
6572
6573         with_pps_lock(intel_dp, wakeref) {
6574                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6575                         intel_dp->active_pipe = vlv_active_pipe(intel_dp);
6576
6577                 if (intel_dp_is_edp(intel_dp)) {
6578                         /*
6579                          * Reinit the power sequencer, in case BIOS did
6580                          * something nasty with it.
6581                          */
6582                         intel_dp_pps_init(intel_dp);
6583                         intel_edp_panel_vdd_sanitize(intel_dp);
6584                 }
6585         }
6586 }
6587
6588 static int intel_modeset_tile_group(struct intel_atomic_state *state,
6589                                     int tile_group_id)
6590 {
6591         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6592         struct drm_connector_list_iter conn_iter;
6593         struct drm_connector *connector;
6594         int ret = 0;
6595
6596         drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
6597         drm_for_each_connector_iter(connector, &conn_iter) {
6598                 struct drm_connector_state *conn_state;
6599                 struct intel_crtc_state *crtc_state;
6600                 struct intel_crtc *crtc;
6601
6602                 if (!connector->has_tile ||
6603                     connector->tile_group->id != tile_group_id)
6604                         continue;
6605
6606                 conn_state = drm_atomic_get_connector_state(&state->base,
6607                                                             connector);
6608                 if (IS_ERR(conn_state)) {
6609                         ret = PTR_ERR(conn_state);
6610                         break;
6611                 }
6612
6613                 crtc = to_intel_crtc(conn_state->crtc);
6614
6615                 if (!crtc)
6616                         continue;
6617
6618                 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
6619                 crtc_state->uapi.mode_changed = true;
6620
6621                 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
6622                 if (ret)
6623                         break;
6624         }
6625         drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
6626
6627         return ret;
6628 }
6629
6630 static int intel_modeset_affected_transcoders(struct intel_atomic_state *state, u8 transcoders)
6631 {
6632         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6633         struct intel_crtc *crtc;
6634
6635         if (transcoders == 0)
6636                 return 0;
6637
6638         for_each_intel_crtc(&dev_priv->drm, crtc) {
6639                 struct intel_crtc_state *crtc_state;
6640                 int ret;
6641
6642                 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
6643                 if (IS_ERR(crtc_state))
6644                         return PTR_ERR(crtc_state);
6645
6646                 if (!crtc_state->hw.enable)
6647                         continue;
6648
6649                 if (!(transcoders & BIT(crtc_state->cpu_transcoder)))
6650                         continue;
6651
6652                 crtc_state->uapi.mode_changed = true;
6653
6654                 ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base);
6655                 if (ret)
6656                         return ret;
6657
6658                 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
6659                 if (ret)
6660                         return ret;
6661
6662                 transcoders &= ~BIT(crtc_state->cpu_transcoder);
6663         }
6664
6665         WARN_ON(transcoders != 0);
6666
6667         return 0;
6668 }
6669
6670 static int intel_modeset_synced_crtcs(struct intel_atomic_state *state,
6671                                       struct drm_connector *connector)
6672 {
6673         const struct drm_connector_state *old_conn_state =
6674                 drm_atomic_get_old_connector_state(&state->base, connector);
6675         const struct intel_crtc_state *old_crtc_state;
6676         struct intel_crtc *crtc;
6677         u8 transcoders;
6678
6679         crtc = to_intel_crtc(old_conn_state->crtc);
6680         if (!crtc)
6681                 return 0;
6682
6683         old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
6684
6685         if (!old_crtc_state->hw.active)
6686                 return 0;
6687
6688         transcoders = old_crtc_state->sync_mode_slaves_mask;
6689         if (old_crtc_state->master_transcoder != INVALID_TRANSCODER)
6690                 transcoders |= BIT(old_crtc_state->master_transcoder);
6691
6692         return intel_modeset_affected_transcoders(state,
6693                                                   transcoders);
6694 }
6695
6696 static int intel_dp_connector_atomic_check(struct drm_connector *conn,
6697                                            struct drm_atomic_state *_state)
6698 {
6699         struct drm_i915_private *dev_priv = to_i915(conn->dev);
6700         struct intel_atomic_state *state = to_intel_atomic_state(_state);
6701         int ret;
6702
6703         ret = intel_digital_connector_atomic_check(conn, &state->base);
6704         if (ret)
6705                 return ret;
6706
6707         if (INTEL_GEN(dev_priv) < 11)
6708                 return 0;
6709
6710         if (!intel_connector_needs_modeset(state, conn))
6711                 return 0;
6712
6713         if (conn->has_tile) {
6714                 ret = intel_modeset_tile_group(state, conn->tile_group->id);
6715                 if (ret)
6716                         return ret;
6717         }
6718
6719         return intel_modeset_synced_crtcs(state, conn);
6720 }
6721
6722 static const struct drm_connector_funcs intel_dp_connector_funcs = {
6723         .force = intel_dp_force,
6724         .fill_modes = drm_helper_probe_single_connector_modes,
6725         .atomic_get_property = intel_digital_connector_atomic_get_property,
6726         .atomic_set_property = intel_digital_connector_atomic_set_property,
6727         .late_register = intel_dp_connector_register,
6728         .early_unregister = intel_dp_connector_unregister,
6729         .destroy = intel_connector_destroy,
6730         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
6731         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
6732 };
6733
6734 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
6735         .detect_ctx = intel_dp_detect,
6736         .get_modes = intel_dp_get_modes,
6737         .mode_valid = intel_dp_mode_valid,
6738         .atomic_check = intel_dp_connector_atomic_check,
6739 };
6740
6741 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
6742         .reset = intel_dp_encoder_reset,
6743         .destroy = intel_dp_encoder_destroy,
6744 };
6745
6746 enum irqreturn
6747 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
6748 {
6749         struct intel_dp *intel_dp = &intel_dig_port->dp;
6750
6751         if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
6752                 /*
6753                  * vdd off can generate a long pulse on eDP which
6754                  * would require vdd on to handle it, and thus we
6755                  * would end up in an endless cycle of
6756                  * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
6757                  */
6758                 DRM_DEBUG_KMS("ignoring long hpd on eDP [ENCODER:%d:%s]\n",
6759                               intel_dig_port->base.base.base.id,
6760                               intel_dig_port->base.base.name);
6761                 return IRQ_HANDLED;
6762         }
6763
6764         DRM_DEBUG_KMS("got hpd irq on [ENCODER:%d:%s] - %s\n",
6765                       intel_dig_port->base.base.base.id,
6766                       intel_dig_port->base.base.name,
6767                       long_hpd ? "long" : "short");
6768
6769         if (long_hpd) {
6770                 intel_dp->reset_link_params = true;
6771                 return IRQ_NONE;
6772         }
6773
6774         if (intel_dp->is_mst) {
6775                 if (intel_dp_check_mst_status(intel_dp) == -EINVAL) {
6776                         /*
6777                          * If we were in MST mode, and device is not
6778                          * there, get out of MST mode
6779                          */
6780                         DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
6781                                       intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
6782                         intel_dp->is_mst = false;
6783                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
6784                                                         intel_dp->is_mst);
6785
6786                         return IRQ_NONE;
6787                 }
6788         }
6789
6790         if (!intel_dp->is_mst) {
6791                 bool handled;
6792
6793                 handled = intel_dp_short_pulse(intel_dp);
6794
6795                 if (!handled)
6796                         return IRQ_NONE;
6797         }
6798
6799         return IRQ_HANDLED;
6800 }
6801
6802 /* check the VBT to see whether the eDP is on another port */
6803 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port)
6804 {
6805         /*
6806          * eDP not supported on g4x. so bail out early just
6807          * for a bit extra safety in case the VBT is bonkers.
6808          */
6809         if (INTEL_GEN(dev_priv) < 5)
6810                 return false;
6811
6812         if (INTEL_GEN(dev_priv) < 9 && port == PORT_A)
6813                 return true;
6814
6815         return intel_bios_is_port_edp(dev_priv, port);
6816 }
6817
6818 static void
6819 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
6820 {
6821         struct drm_i915_private *dev_priv = to_i915(connector->dev);
6822         enum port port = dp_to_dig_port(intel_dp)->base.port;
6823
6824         if (!IS_G4X(dev_priv) && port != PORT_A)
6825                 intel_attach_force_audio_property(connector);
6826
6827         intel_attach_broadcast_rgb_property(connector);
6828         if (HAS_GMCH(dev_priv))
6829                 drm_connector_attach_max_bpc_property(connector, 6, 10);
6830         else if (INTEL_GEN(dev_priv) >= 5)
6831                 drm_connector_attach_max_bpc_property(connector, 6, 12);
6832
6833         intel_attach_colorspace_property(connector);
6834
6835         if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 11)
6836                 drm_object_attach_property(&connector->base,
6837                                            connector->dev->mode_config.hdr_output_metadata_property,
6838                                            0);
6839
6840         if (intel_dp_is_edp(intel_dp)) {
6841                 u32 allowed_scalers;
6842
6843                 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN);
6844                 if (!HAS_GMCH(dev_priv))
6845                         allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);
6846
6847                 drm_connector_attach_scaling_mode_property(connector, allowed_scalers);
6848
6849                 connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT;
6850
6851         }
6852 }
6853
6854 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
6855 {
6856         intel_dp->panel_power_off_time = ktime_get_boottime();
6857         intel_dp->last_power_on = jiffies;
6858         intel_dp->last_backlight_off = jiffies;
6859 }
6860
6861 static void
6862 intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq)
6863 {
6864         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6865         u32 pp_on, pp_off, pp_ctl;
6866         struct pps_registers regs;
6867
6868         intel_pps_get_registers(intel_dp, &regs);
6869
6870         pp_ctl = ilk_get_pp_control(intel_dp);
6871
6872         /* Ensure PPS is unlocked */
6873         if (!HAS_DDI(dev_priv))
6874                 intel_de_write(dev_priv, regs.pp_ctrl, pp_ctl);
6875
6876         pp_on = intel_de_read(dev_priv, regs.pp_on);
6877         pp_off = intel_de_read(dev_priv, regs.pp_off);
6878
6879         /* Pull timing values out of registers */
6880         seq->t1_t3 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, pp_on);
6881         seq->t8 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, pp_on);
6882         seq->t9 = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, pp_off);
6883         seq->t10 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, pp_off);
6884
6885         if (i915_mmio_reg_valid(regs.pp_div)) {
6886                 u32 pp_div;
6887
6888                 pp_div = intel_de_read(dev_priv, regs.pp_div);
6889
6890                 seq->t11_t12 = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, pp_div) * 1000;
6891         } else {
6892                 seq->t11_t12 = REG_FIELD_GET(BXT_POWER_CYCLE_DELAY_MASK, pp_ctl) * 1000;
6893         }
6894 }
6895
6896 static void
6897 intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq)
6898 {
6899         DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
6900                       state_name,
6901                       seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12);
6902 }
6903
6904 static void
6905 intel_pps_verify_state(struct intel_dp *intel_dp)
6906 {
6907         struct edp_power_seq hw;
6908         struct edp_power_seq *sw = &intel_dp->pps_delays;
6909
6910         intel_pps_readout_hw_state(intel_dp, &hw);
6911
6912         if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 ||
6913             hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) {
6914                 DRM_ERROR("PPS state mismatch\n");
6915                 intel_pps_dump_state("sw", sw);
6916                 intel_pps_dump_state("hw", &hw);
6917         }
6918 }
6919
6920 static void
6921 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp)
6922 {
6923         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6924         struct edp_power_seq cur, vbt, spec,
6925                 *final = &intel_dp->pps_delays;
6926
6927         lockdep_assert_held(&dev_priv->pps_mutex);
6928
6929         /* already initialized? */
6930         if (final->t11_t12 != 0)
6931                 return;
6932
6933         intel_pps_readout_hw_state(intel_dp, &cur);
6934
6935         intel_pps_dump_state("cur", &cur);
6936
6937         vbt = dev_priv->vbt.edp.pps;
6938         /* On Toshiba Satellite P50-C-18C system the VBT T12 delay
6939          * of 500ms appears to be too short. Ocassionally the panel
6940          * just fails to power back on. Increasing the delay to 800ms
6941          * seems sufficient to avoid this problem.
6942          */
6943         if (dev_priv->quirks & QUIRK_INCREASE_T12_DELAY) {
6944                 vbt.t11_t12 = max_t(u16, vbt.t11_t12, 1300 * 10);
6945                 drm_dbg_kms(&dev_priv->drm,
6946                             "Increasing T12 panel delay as per the quirk to %d\n",
6947                             vbt.t11_t12);
6948         }
6949         /* T11_T12 delay is special and actually in units of 100ms, but zero
6950          * based in the hw (so we need to add 100 ms). But the sw vbt
6951          * table multiplies it with 1000 to make it in units of 100usec,
6952          * too. */
6953         vbt.t11_t12 += 100 * 10;
6954
6955         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
6956          * our hw here, which are all in 100usec. */
6957         spec.t1_t3 = 210 * 10;
6958         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
6959         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
6960         spec.t10 = 500 * 10;
6961         /* This one is special and actually in units of 100ms, but zero
6962          * based in the hw (so we need to add 100 ms). But the sw vbt
6963          * table multiplies it with 1000 to make it in units of 100usec,
6964          * too. */
6965         spec.t11_t12 = (510 + 100) * 10;
6966
6967         intel_pps_dump_state("vbt", &vbt);
6968
6969         /* Use the max of the register settings and vbt. If both are
6970          * unset, fall back to the spec limits. */
6971 #define assign_final(field)     final->field = (max(cur.field, vbt.field) == 0 ? \
6972                                        spec.field : \
6973                                        max(cur.field, vbt.field))
6974         assign_final(t1_t3);
6975         assign_final(t8);
6976         assign_final(t9);
6977         assign_final(t10);
6978         assign_final(t11_t12);
6979 #undef assign_final
6980
6981 #define get_delay(field)        (DIV_ROUND_UP(final->field, 10))
6982         intel_dp->panel_power_up_delay = get_delay(t1_t3);
6983         intel_dp->backlight_on_delay = get_delay(t8);
6984         intel_dp->backlight_off_delay = get_delay(t9);
6985         intel_dp->panel_power_down_delay = get_delay(t10);
6986         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
6987 #undef get_delay
6988
6989         drm_dbg_kms(&dev_priv->drm,
6990                     "panel power up delay %d, power down delay %d, power cycle delay %d\n",
6991                     intel_dp->panel_power_up_delay,
6992                     intel_dp->panel_power_down_delay,
6993                     intel_dp->panel_power_cycle_delay);
6994
6995         drm_dbg_kms(&dev_priv->drm, "backlight on delay %d, off delay %d\n",
6996                     intel_dp->backlight_on_delay,
6997                     intel_dp->backlight_off_delay);
6998
6999         /*
7000          * We override the HW backlight delays to 1 because we do manual waits
7001          * on them. For T8, even BSpec recommends doing it. For T9, if we
7002          * don't do this, we'll end up waiting for the backlight off delay
7003          * twice: once when we do the manual sleep, and once when we disable
7004          * the panel and wait for the PP_STATUS bit to become zero.
7005          */
7006         final->t8 = 1;
7007         final->t9 = 1;
7008
7009         /*
7010          * HW has only a 100msec granularity for t11_t12 so round it up
7011          * accordingly.
7012          */
7013         final->t11_t12 = roundup(final->t11_t12, 100 * 10);
7014 }
7015
7016 static void
7017 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
7018                                               bool force_disable_vdd)
7019 {
7020         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7021         u32 pp_on, pp_off, port_sel = 0;
7022         int div = RUNTIME_INFO(dev_priv)->rawclk_freq / 1000;
7023         struct pps_registers regs;
7024         enum port port = dp_to_dig_port(intel_dp)->base.port;
7025         const struct edp_power_seq *seq = &intel_dp->pps_delays;
7026
7027         lockdep_assert_held(&dev_priv->pps_mutex);
7028
7029         intel_pps_get_registers(intel_dp, &regs);
7030
7031         /*
7032          * On some VLV machines the BIOS can leave the VDD
7033          * enabled even on power sequencers which aren't
7034          * hooked up to any port. This would mess up the
7035          * power domain tracking the first time we pick
7036          * one of these power sequencers for use since
7037          * edp_panel_vdd_on() would notice that the VDD was
7038          * already on and therefore wouldn't grab the power
7039          * domain reference. Disable VDD first to avoid this.
7040          * This also avoids spuriously turning the VDD on as
7041          * soon as the new power sequencer gets initialized.
7042          */
7043         if (force_disable_vdd) {
7044                 u32 pp = ilk_get_pp_control(intel_dp);
7045
7046                 WARN(pp & PANEL_POWER_ON, "Panel power already on\n");
7047
7048                 if (pp & EDP_FORCE_VDD)
7049                         drm_dbg_kms(&dev_priv->drm,
7050                                     "VDD already on, disabling first\n");
7051
7052                 pp &= ~EDP_FORCE_VDD;
7053
7054                 intel_de_write(dev_priv, regs.pp_ctrl, pp);
7055         }
7056
7057         pp_on = REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, seq->t1_t3) |
7058                 REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, seq->t8);
7059         pp_off = REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, seq->t9) |
7060                 REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, seq->t10);
7061
7062         /* Haswell doesn't have any port selection bits for the panel
7063          * power sequencer any more. */
7064         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
7065                 port_sel = PANEL_PORT_SELECT_VLV(port);
7066         } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
7067                 switch (port) {
7068                 case PORT_A:
7069                         port_sel = PANEL_PORT_SELECT_DPA;
7070                         break;
7071                 case PORT_C:
7072                         port_sel = PANEL_PORT_SELECT_DPC;
7073                         break;
7074                 case PORT_D:
7075                         port_sel = PANEL_PORT_SELECT_DPD;
7076                         break;
7077                 default:
7078                         MISSING_CASE(port);
7079                         break;
7080                 }
7081         }
7082
7083         pp_on |= port_sel;
7084
7085         intel_de_write(dev_priv, regs.pp_on, pp_on);
7086         intel_de_write(dev_priv, regs.pp_off, pp_off);
7087
7088         /*
7089          * Compute the divisor for the pp clock, simply match the Bspec formula.
7090          */
7091         if (i915_mmio_reg_valid(regs.pp_div)) {
7092                 intel_de_write(dev_priv, regs.pp_div,
7093                                REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, (100 * div) / 2 - 1) | REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000)));
7094         } else {
7095                 u32 pp_ctl;
7096
7097                 pp_ctl = intel_de_read(dev_priv, regs.pp_ctrl);
7098                 pp_ctl &= ~BXT_POWER_CYCLE_DELAY_MASK;
7099                 pp_ctl |= REG_FIELD_PREP(BXT_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000));
7100                 intel_de_write(dev_priv, regs.pp_ctrl, pp_ctl);
7101         }
7102
7103         drm_dbg_kms(&dev_priv->drm,
7104                     "panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
7105                     intel_de_read(dev_priv, regs.pp_on),
7106                     intel_de_read(dev_priv, regs.pp_off),
7107                     i915_mmio_reg_valid(regs.pp_div) ?
7108                     intel_de_read(dev_priv, regs.pp_div) :
7109                     (intel_de_read(dev_priv, regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK));
7110 }
7111
7112 static void intel_dp_pps_init(struct intel_dp *intel_dp)
7113 {
7114         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7115
7116         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
7117                 vlv_initial_power_sequencer_setup(intel_dp);
7118         } else {
7119                 intel_dp_init_panel_power_sequencer(intel_dp);
7120                 intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
7121         }
7122 }
7123
7124 /**
7125  * intel_dp_set_drrs_state - program registers for RR switch to take effect
7126  * @dev_priv: i915 device
7127  * @crtc_state: a pointer to the active intel_crtc_state
7128  * @refresh_rate: RR to be programmed
7129  *
7130  * This function gets called when refresh rate (RR) has to be changed from
7131  * one frequency to another. Switches can be between high and low RR
7132  * supported by the panel or to any other RR based on media playback (in
7133  * this case, RR value needs to be passed from user space).
7134  *
7135  * The caller of this function needs to take a lock on dev_priv->drrs.
7136  */
7137 static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
7138                                     const struct intel_crtc_state *crtc_state,
7139                                     int refresh_rate)
7140 {
7141         struct intel_dp *intel_dp = dev_priv->drrs.dp;
7142         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
7143         enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
7144
7145         if (refresh_rate <= 0) {
7146                 drm_dbg_kms(&dev_priv->drm,
7147                             "Refresh rate should be positive non-zero.\n");
7148                 return;
7149         }
7150
7151         if (intel_dp == NULL) {
7152                 drm_dbg_kms(&dev_priv->drm, "DRRS not supported.\n");
7153                 return;
7154         }
7155
7156         if (!intel_crtc) {
7157                 drm_dbg_kms(&dev_priv->drm,
7158                             "DRRS: intel_crtc not initialized\n");
7159                 return;
7160         }
7161
7162         if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
7163                 drm_dbg_kms(&dev_priv->drm, "Only Seamless DRRS supported.\n");
7164                 return;
7165         }
7166
7167         if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
7168                         refresh_rate)
7169                 index = DRRS_LOW_RR;
7170
7171         if (index == dev_priv->drrs.refresh_rate_type) {
7172                 drm_dbg_kms(&dev_priv->drm,
7173                             "DRRS requested for previously set RR...ignoring\n");
7174                 return;
7175         }
7176
7177         if (!crtc_state->hw.active) {
7178                 drm_dbg_kms(&dev_priv->drm,
7179                             "eDP encoder disabled. CRTC not Active\n");
7180                 return;
7181         }
7182
7183         if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
7184                 switch (index) {
7185                 case DRRS_HIGH_RR:
7186                         intel_dp_set_m_n(crtc_state, M1_N1);
7187                         break;
7188                 case DRRS_LOW_RR:
7189                         intel_dp_set_m_n(crtc_state, M2_N2);
7190                         break;
7191                 case DRRS_MAX_RR:
7192                 default:
7193                         drm_err(&dev_priv->drm,
7194                                 "Unsupported refreshrate type\n");
7195                 }
7196         } else if (INTEL_GEN(dev_priv) > 6) {
7197                 i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);
7198                 u32 val;
7199
7200                 val = intel_de_read(dev_priv, reg);
7201                 if (index > DRRS_HIGH_RR) {
7202                         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
7203                                 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
7204                         else
7205                                 val |= PIPECONF_EDP_RR_MODE_SWITCH;
7206                 } else {
7207                         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
7208                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
7209                         else
7210                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
7211                 }
7212                 intel_de_write(dev_priv, reg, val);
7213         }
7214
7215         dev_priv->drrs.refresh_rate_type = index;
7216
7217         drm_dbg_kms(&dev_priv->drm, "eDP Refresh Rate set to : %dHz\n",
7218                     refresh_rate);
7219 }
7220
7221 /**
7222  * intel_edp_drrs_enable - init drrs struct if supported
7223  * @intel_dp: DP struct
7224  * @crtc_state: A pointer to the active crtc state.
7225  *
7226  * Initializes frontbuffer_bits and drrs.dp
7227  */
7228 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
7229                            const struct intel_crtc_state *crtc_state)
7230 {
7231         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7232
7233         if (!crtc_state->has_drrs) {
7234                 drm_dbg_kms(&dev_priv->drm, "Panel doesn't support DRRS\n");
7235                 return;
7236         }
7237
7238         if (dev_priv->psr.enabled) {
7239                 drm_dbg_kms(&dev_priv->drm,
7240                             "PSR enabled. Not enabling DRRS.\n");
7241                 return;
7242         }
7243
7244         mutex_lock(&dev_priv->drrs.mutex);
7245         if (dev_priv->drrs.dp) {
7246                 drm_dbg_kms(&dev_priv->drm, "DRRS already enabled\n");
7247                 goto unlock;
7248         }
7249
7250         dev_priv->drrs.busy_frontbuffer_bits = 0;
7251
7252         dev_priv->drrs.dp = intel_dp;
7253
7254 unlock:
7255         mutex_unlock(&dev_priv->drrs.mutex);
7256 }
7257
7258 /**
7259  * intel_edp_drrs_disable - Disable DRRS
7260  * @intel_dp: DP struct
7261  * @old_crtc_state: Pointer to old crtc_state.
7262  *
7263  */
7264 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
7265                             const struct intel_crtc_state *old_crtc_state)
7266 {
7267         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7268
7269         if (!old_crtc_state->has_drrs)
7270                 return;
7271
7272         mutex_lock(&dev_priv->drrs.mutex);
7273         if (!dev_priv->drrs.dp) {
7274                 mutex_unlock(&dev_priv->drrs.mutex);
7275                 return;
7276         }
7277
7278         if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
7279                 intel_dp_set_drrs_state(dev_priv, old_crtc_state,
7280                         intel_dp->attached_connector->panel.fixed_mode->vrefresh);
7281
7282         dev_priv->drrs.dp = NULL;
7283         mutex_unlock(&dev_priv->drrs.mutex);
7284
7285         cancel_delayed_work_sync(&dev_priv->drrs.work);
7286 }
7287
7288 static void intel_edp_drrs_downclock_work(struct work_struct *work)
7289 {
7290         struct drm_i915_private *dev_priv =
7291                 container_of(work, typeof(*dev_priv), drrs.work.work);
7292         struct intel_dp *intel_dp;
7293
7294         mutex_lock(&dev_priv->drrs.mutex);
7295
7296         intel_dp = dev_priv->drrs.dp;
7297
7298         if (!intel_dp)
7299                 goto unlock;
7300
7301         /*
7302          * The delayed work can race with an invalidate hence we need to
7303          * recheck.
7304          */
7305
7306         if (dev_priv->drrs.busy_frontbuffer_bits)
7307                 goto unlock;
7308
7309         if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) {
7310                 struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
7311
7312                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
7313                         intel_dp->attached_connector->panel.downclock_mode->vrefresh);
7314         }
7315
7316 unlock:
7317         mutex_unlock(&dev_priv->drrs.mutex);
7318 }
7319
7320 /**
7321  * intel_edp_drrs_invalidate - Disable Idleness DRRS
7322  * @dev_priv: i915 device
7323  * @frontbuffer_bits: frontbuffer plane tracking bits
7324  *
7325  * This function gets called everytime rendering on the given planes start.
7326  * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
7327  *
7328  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
7329  */
7330 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
7331                                unsigned int frontbuffer_bits)
7332 {
7333         struct drm_crtc *crtc;
7334         enum pipe pipe;
7335
7336         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
7337                 return;
7338
7339         cancel_delayed_work(&dev_priv->drrs.work);
7340
7341         mutex_lock(&dev_priv->drrs.mutex);
7342         if (!dev_priv->drrs.dp) {
7343                 mutex_unlock(&dev_priv->drrs.mutex);
7344                 return;
7345         }
7346
7347         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
7348         pipe = to_intel_crtc(crtc)->pipe;
7349
7350         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
7351         dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
7352
7353         /* invalidate means busy screen hence upclock */
7354         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
7355                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
7356                         dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
7357
7358         mutex_unlock(&dev_priv->drrs.mutex);
7359 }
7360
7361 /**
7362  * intel_edp_drrs_flush - Restart Idleness DRRS
7363  * @dev_priv: i915 device
7364  * @frontbuffer_bits: frontbuffer plane tracking bits
7365  *
7366  * This function gets called every time rendering on the given planes has
7367  * completed or flip on a crtc is completed. So DRRS should be upclocked
7368  * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
7369  * if no other planes are dirty.
7370  *
7371  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
7372  */
7373 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
7374                           unsigned int frontbuffer_bits)
7375 {
7376         struct drm_crtc *crtc;
7377         enum pipe pipe;
7378
7379         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
7380                 return;
7381
7382         cancel_delayed_work(&dev_priv->drrs.work);
7383
7384         mutex_lock(&dev_priv->drrs.mutex);
7385         if (!dev_priv->drrs.dp) {
7386                 mutex_unlock(&dev_priv->drrs.mutex);
7387                 return;
7388         }
7389
7390         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
7391         pipe = to_intel_crtc(crtc)->pipe;
7392
7393         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
7394         dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
7395
7396         /* flush means busy screen hence upclock */
7397         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
7398                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
7399                                 dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
7400
7401         /*
7402          * flush also means no more activity hence schedule downclock, if all
7403          * other fbs are quiescent too
7404          */
7405         if (!dev_priv->drrs.busy_frontbuffer_bits)
7406                 schedule_delayed_work(&dev_priv->drrs.work,
7407                                 msecs_to_jiffies(1000));
7408         mutex_unlock(&dev_priv->drrs.mutex);
7409 }
7410
7411 /**
7412  * DOC: Display Refresh Rate Switching (DRRS)
7413  *
7414  * Display Refresh Rate Switching (DRRS) is a power conservation feature
7415  * which enables swtching between low and high refresh rates,
7416  * dynamically, based on the usage scenario. This feature is applicable
7417  * for internal panels.
7418  *
7419  * Indication that the panel supports DRRS is given by the panel EDID, which
7420  * would list multiple refresh rates for one resolution.
7421  *
7422  * DRRS is of 2 types - static and seamless.
7423  * Static DRRS involves changing refresh rate (RR) by doing a full modeset
7424  * (may appear as a blink on screen) and is used in dock-undock scenario.
7425  * Seamless DRRS involves changing RR without any visual effect to the user
7426  * and can be used during normal system usage. This is done by programming
7427  * certain registers.
7428  *
7429  * Support for static/seamless DRRS may be indicated in the VBT based on
7430  * inputs from the panel spec.
7431  *
7432  * DRRS saves power by switching to low RR based on usage scenarios.
7433  *
7434  * The implementation is based on frontbuffer tracking implementation.  When
7435  * there is a disturbance on the screen triggered by user activity or a periodic
7436  * system activity, DRRS is disabled (RR is changed to high RR).  When there is
7437  * no movement on screen, after a timeout of 1 second, a switch to low RR is
7438  * made.
7439  *
7440  * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
7441  * and intel_edp_drrs_flush() are called.
7442  *
7443  * DRRS can be further extended to support other internal panels and also
7444  * the scenario of video playback wherein RR is set based on the rate
7445  * requested by userspace.
7446  */
7447
7448 /**
7449  * intel_dp_drrs_init - Init basic DRRS work and mutex.
7450  * @connector: eDP connector
7451  * @fixed_mode: preferred mode of panel
7452  *
7453  * This function is  called only once at driver load to initialize basic
7454  * DRRS stuff.
7455  *
7456  * Returns:
7457  * Downclock mode if panel supports it, else return NULL.
7458  * DRRS support is determined by the presence of downclock mode (apart
7459  * from VBT setting).
7460  */
7461 static struct drm_display_mode *
7462 intel_dp_drrs_init(struct intel_connector *connector,
7463                    struct drm_display_mode *fixed_mode)
7464 {
7465         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
7466         struct drm_display_mode *downclock_mode = NULL;
7467
7468         INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
7469         mutex_init(&dev_priv->drrs.mutex);
7470
7471         if (INTEL_GEN(dev_priv) <= 6) {
7472                 drm_dbg_kms(&dev_priv->drm,
7473                             "DRRS supported for Gen7 and above\n");
7474                 return NULL;
7475         }
7476
7477         if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
7478                 drm_dbg_kms(&dev_priv->drm, "VBT doesn't support DRRS\n");
7479                 return NULL;
7480         }
7481
7482         downclock_mode = intel_panel_edid_downclock_mode(connector, fixed_mode);
7483         if (!downclock_mode) {
7484                 drm_dbg_kms(&dev_priv->drm,
7485                             "Downclock mode is not found. DRRS not supported\n");
7486                 return NULL;
7487         }
7488
7489         dev_priv->drrs.type = dev_priv->vbt.drrs_type;
7490
7491         dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
7492         drm_dbg_kms(&dev_priv->drm,
7493                     "seamless DRRS supported for eDP panel.\n");
7494         return downclock_mode;
7495 }
7496
7497 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
7498                                      struct intel_connector *intel_connector)
7499 {
7500         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7501         struct drm_device *dev = &dev_priv->drm;
7502         struct drm_connector *connector = &intel_connector->base;
7503         struct drm_display_mode *fixed_mode = NULL;
7504         struct drm_display_mode *downclock_mode = NULL;
7505         bool has_dpcd;
7506         enum pipe pipe = INVALID_PIPE;
7507         intel_wakeref_t wakeref;
7508         struct edid *edid;
7509
7510         if (!intel_dp_is_edp(intel_dp))
7511                 return true;
7512
7513         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, edp_panel_vdd_work);
7514
7515         /*
7516          * On IBX/CPT we may get here with LVDS already registered. Since the
7517          * driver uses the only internal power sequencer available for both
7518          * eDP and LVDS bail out early in this case to prevent interfering
7519          * with an already powered-on LVDS power sequencer.
7520          */
7521         if (intel_get_lvds_encoder(dev_priv)) {
7522                 WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
7523                 drm_info(&dev_priv->drm,
7524                          "LVDS was detected, not registering eDP\n");
7525
7526                 return false;
7527         }
7528
7529         with_pps_lock(intel_dp, wakeref) {
7530                 intel_dp_init_panel_power_timestamps(intel_dp);
7531                 intel_dp_pps_init(intel_dp);
7532                 intel_edp_panel_vdd_sanitize(intel_dp);
7533         }
7534
7535         /* Cache DPCD and EDID for edp. */
7536         has_dpcd = intel_edp_init_dpcd(intel_dp);
7537
7538         if (!has_dpcd) {
7539                 /* if this fails, presume the device is a ghost */
7540                 drm_info(&dev_priv->drm,
7541                          "failed to retrieve link info, disabling eDP\n");
7542                 goto out_vdd_off;
7543         }
7544
7545         mutex_lock(&dev->mode_config.mutex);
7546         edid = drm_get_edid(connector, &intel_dp->aux.ddc);
7547         if (edid) {
7548                 if (drm_add_edid_modes(connector, edid)) {
7549                         drm_connector_update_edid_property(connector,
7550                                                                 edid);
7551                 } else {
7552                         kfree(edid);
7553                         edid = ERR_PTR(-EINVAL);
7554                 }
7555         } else {
7556                 edid = ERR_PTR(-ENOENT);
7557         }
7558         intel_connector->edid = edid;
7559
7560         fixed_mode = intel_panel_edid_fixed_mode(intel_connector);
7561         if (fixed_mode)
7562                 downclock_mode = intel_dp_drrs_init(intel_connector, fixed_mode);
7563
7564         /* fallback to VBT if available for eDP */
7565         if (!fixed_mode)
7566                 fixed_mode = intel_panel_vbt_fixed_mode(intel_connector);
7567         mutex_unlock(&dev->mode_config.mutex);
7568
7569         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
7570                 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
7571                 register_reboot_notifier(&intel_dp->edp_notifier);
7572
7573                 /*
7574                  * Figure out the current pipe for the initial backlight setup.
7575                  * If the current pipe isn't valid, try the PPS pipe, and if that
7576                  * fails just assume pipe A.
7577                  */
7578                 pipe = vlv_active_pipe(intel_dp);
7579
7580                 if (pipe != PIPE_A && pipe != PIPE_B)
7581                         pipe = intel_dp->pps_pipe;
7582
7583                 if (pipe != PIPE_A && pipe != PIPE_B)
7584                         pipe = PIPE_A;
7585
7586                 drm_dbg_kms(&dev_priv->drm,
7587                             "using pipe %c for initial backlight setup\n",
7588                             pipe_name(pipe));
7589         }
7590
7591         intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
7592         intel_connector->panel.backlight.power = intel_edp_backlight_power;
7593         intel_panel_setup_backlight(connector, pipe);
7594
7595         if (fixed_mode)
7596                 drm_connector_init_panel_orientation_property(
7597                         connector, fixed_mode->hdisplay, fixed_mode->vdisplay);
7598
7599         return true;
7600
7601 out_vdd_off:
7602         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
7603         /*
7604          * vdd might still be enabled do to the delayed vdd off.
7605          * Make sure vdd is actually turned off here.
7606          */
7607         with_pps_lock(intel_dp, wakeref)
7608                 edp_panel_vdd_off_sync(intel_dp);
7609
7610         return false;
7611 }
7612
7613 static void intel_dp_modeset_retry_work_fn(struct work_struct *work)
7614 {
7615         struct intel_connector *intel_connector;
7616         struct drm_connector *connector;
7617
7618         intel_connector = container_of(work, typeof(*intel_connector),
7619                                        modeset_retry_work);
7620         connector = &intel_connector->base;
7621         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector->base.id,
7622                       connector->name);
7623
7624         /* Grab the locks before changing connector property*/
7625         mutex_lock(&connector->dev->mode_config.mutex);
7626         /* Set connector link status to BAD and send a Uevent to notify
7627          * userspace to do a modeset.
7628          */
7629         drm_connector_set_link_status_property(connector,
7630                                                DRM_MODE_LINK_STATUS_BAD);
7631         mutex_unlock(&connector->dev->mode_config.mutex);
7632         /* Send Hotplug uevent so userspace can reprobe */
7633         drm_kms_helper_hotplug_event(connector->dev);
7634 }
7635
7636 bool
7637 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
7638                         struct intel_connector *intel_connector)
7639 {
7640         struct drm_connector *connector = &intel_connector->base;
7641         struct intel_dp *intel_dp = &intel_dig_port->dp;
7642         struct intel_encoder *intel_encoder = &intel_dig_port->base;
7643         struct drm_device *dev = intel_encoder->base.dev;
7644         struct drm_i915_private *dev_priv = to_i915(dev);
7645         enum port port = intel_encoder->port;
7646         enum phy phy = intel_port_to_phy(dev_priv, port);
7647         int type;
7648
7649         /* Initialize the work for modeset in case of link train failure */
7650         INIT_WORK(&intel_connector->modeset_retry_work,
7651                   intel_dp_modeset_retry_work_fn);
7652
7653         if (WARN(intel_dig_port->max_lanes < 1,
7654                  "Not enough lanes (%d) for DP on [ENCODER:%d:%s]\n",
7655                  intel_dig_port->max_lanes, intel_encoder->base.base.id,
7656                  intel_encoder->base.name))
7657                 return false;
7658
7659         intel_dp_set_source_rates(intel_dp);
7660
7661         intel_dp->reset_link_params = true;
7662         intel_dp->pps_pipe = INVALID_PIPE;
7663         intel_dp->active_pipe = INVALID_PIPE;
7664
7665         /* Preserve the current hw state. */
7666         intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
7667         intel_dp->attached_connector = intel_connector;
7668
7669         if (intel_dp_is_port_edp(dev_priv, port)) {
7670                 /*
7671                  * Currently we don't support eDP on TypeC ports, although in
7672                  * theory it could work on TypeC legacy ports.
7673                  */
7674                 WARN_ON(intel_phy_is_tc(dev_priv, phy));
7675                 type = DRM_MODE_CONNECTOR_eDP;
7676         } else {
7677                 type = DRM_MODE_CONNECTOR_DisplayPort;
7678         }
7679
7680         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
7681                 intel_dp->active_pipe = vlv_active_pipe(intel_dp);
7682
7683         /*
7684          * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
7685          * for DP the encoder type can be set by the caller to
7686          * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
7687          */
7688         if (type == DRM_MODE_CONNECTOR_eDP)
7689                 intel_encoder->type = INTEL_OUTPUT_EDP;
7690
7691         /* eDP only on port B and/or C on vlv/chv */
7692         if (WARN_ON((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7693                     intel_dp_is_edp(intel_dp) &&
7694                     port != PORT_B && port != PORT_C))
7695                 return false;
7696
7697         drm_dbg_kms(&dev_priv->drm,
7698                     "Adding %s connector on [ENCODER:%d:%s]\n",
7699                     type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
7700                     intel_encoder->base.base.id, intel_encoder->base.name);
7701
7702         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
7703         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
7704
7705         if (!HAS_GMCH(dev_priv))
7706                 connector->interlace_allowed = true;
7707         connector->doublescan_allowed = 0;
7708
7709         if (INTEL_GEN(dev_priv) >= 11)
7710                 connector->ycbcr_420_allowed = true;
7711
7712         intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
7713
7714         intel_dp_aux_init(intel_dp);
7715
7716         intel_connector_attach_encoder(intel_connector, intel_encoder);
7717
7718         if (HAS_DDI(dev_priv))
7719                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
7720         else
7721                 intel_connector->get_hw_state = intel_connector_get_hw_state;
7722
7723         /* init MST on ports that can support it */
7724         intel_dp_mst_encoder_init(intel_dig_port,
7725                                   intel_connector->base.base.id);
7726
7727         if (!intel_edp_init_connector(intel_dp, intel_connector)) {
7728                 intel_dp_aux_fini(intel_dp);
7729                 intel_dp_mst_encoder_cleanup(intel_dig_port);
7730                 goto fail;
7731         }
7732
7733         intel_dp_add_properties(intel_dp, connector);
7734
7735         if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) {
7736                 int ret = intel_hdcp_init(intel_connector, &intel_dp_hdcp_shim);
7737                 if (ret)
7738                         drm_dbg_kms(&dev_priv->drm,
7739                                     "HDCP init failed, skipping.\n");
7740         }
7741
7742         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
7743          * 0xd.  Failure to do so will result in spurious interrupts being
7744          * generated on the port when a cable is not attached.
7745          */
7746         if (IS_G45(dev_priv)) {
7747                 u32 temp = intel_de_read(dev_priv, PEG_BAND_GAP_DATA);
7748                 intel_de_write(dev_priv, PEG_BAND_GAP_DATA,
7749                                (temp & ~0xf) | 0xd);
7750         }
7751
7752         return true;
7753
7754 fail:
7755         drm_connector_cleanup(connector);
7756
7757         return false;
7758 }
7759
7760 bool intel_dp_init(struct drm_i915_private *dev_priv,
7761                    i915_reg_t output_reg,
7762                    enum port port)
7763 {
7764         struct intel_digital_port *intel_dig_port;
7765         struct intel_encoder *intel_encoder;
7766         struct drm_encoder *encoder;
7767         struct intel_connector *intel_connector;
7768
7769         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
7770         if (!intel_dig_port)
7771                 return false;
7772
7773         intel_connector = intel_connector_alloc();
7774         if (!intel_connector)
7775                 goto err_connector_alloc;
7776
7777         intel_encoder = &intel_dig_port->base;
7778         encoder = &intel_encoder->base;
7779
7780         if (drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
7781                              &intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS,
7782                              "DP %c", port_name(port)))
7783                 goto err_encoder_init;
7784
7785         intel_encoder->hotplug = intel_dp_hotplug;
7786         intel_encoder->compute_config = intel_dp_compute_config;
7787         intel_encoder->get_hw_state = intel_dp_get_hw_state;
7788         intel_encoder->get_config = intel_dp_get_config;
7789         intel_encoder->update_pipe = intel_panel_update_backlight;
7790         intel_encoder->suspend = intel_dp_encoder_suspend;
7791         if (IS_CHERRYVIEW(dev_priv)) {
7792                 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
7793                 intel_encoder->pre_enable = chv_pre_enable_dp;
7794                 intel_encoder->enable = vlv_enable_dp;
7795                 intel_encoder->disable = vlv_disable_dp;
7796                 intel_encoder->post_disable = chv_post_disable_dp;
7797                 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
7798         } else if (IS_VALLEYVIEW(dev_priv)) {
7799                 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
7800                 intel_encoder->pre_enable = vlv_pre_enable_dp;
7801                 intel_encoder->enable = vlv_enable_dp;
7802                 intel_encoder->disable = vlv_disable_dp;
7803                 intel_encoder->post_disable = vlv_post_disable_dp;
7804         } else {
7805                 intel_encoder->pre_enable = g4x_pre_enable_dp;
7806                 intel_encoder->enable = g4x_enable_dp;
7807                 intel_encoder->disable = g4x_disable_dp;
7808                 intel_encoder->post_disable = g4x_post_disable_dp;
7809         }
7810
7811         intel_dig_port->dp.output_reg = output_reg;
7812         intel_dig_port->max_lanes = 4;
7813
7814         intel_encoder->type = INTEL_OUTPUT_DP;
7815         intel_encoder->power_domain = intel_port_to_power_domain(port);
7816         if (IS_CHERRYVIEW(dev_priv)) {
7817                 if (port == PORT_D)
7818                         intel_encoder->pipe_mask = BIT(PIPE_C);
7819                 else
7820                         intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B);
7821         } else {
7822                 intel_encoder->pipe_mask = ~0;
7823         }
7824         intel_encoder->cloneable = 0;
7825         intel_encoder->port = port;
7826
7827         intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
7828
7829         if (port != PORT_A)
7830                 intel_infoframe_init(intel_dig_port);
7831
7832         intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
7833         if (!intel_dp_init_connector(intel_dig_port, intel_connector))
7834                 goto err_init_connector;
7835
7836         return true;
7837
7838 err_init_connector:
7839         drm_encoder_cleanup(encoder);
7840 err_encoder_init:
7841         kfree(intel_connector);
7842 err_connector_alloc:
7843         kfree(intel_dig_port);
7844         return false;
7845 }
7846
7847 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv)
7848 {
7849         struct intel_encoder *encoder;
7850
7851         for_each_intel_encoder(&dev_priv->drm, encoder) {
7852                 struct intel_dp *intel_dp;
7853
7854                 if (encoder->type != INTEL_OUTPUT_DDI)
7855                         continue;
7856
7857                 intel_dp = enc_to_intel_dp(encoder);
7858
7859                 if (!intel_dp->can_mst)
7860                         continue;
7861
7862                 if (intel_dp->is_mst)
7863                         drm_dp_mst_topology_mgr_suspend(&intel_dp->mst_mgr);
7864         }
7865 }
7866
7867 void intel_dp_mst_resume(struct drm_i915_private *dev_priv)
7868 {
7869         struct intel_encoder *encoder;
7870
7871         for_each_intel_encoder(&dev_priv->drm, encoder) {
7872                 struct intel_dp *intel_dp;
7873                 int ret;
7874
7875                 if (encoder->type != INTEL_OUTPUT_DDI)
7876                         continue;
7877
7878                 intel_dp = enc_to_intel_dp(encoder);
7879
7880                 if (!intel_dp->can_mst)
7881                         continue;
7882
7883                 ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst_mgr,
7884                                                      true);
7885                 if (ret) {
7886                         intel_dp->is_mst = false;
7887                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
7888                                                         false);
7889                 }
7890         }
7891 }