drivers/gpu/drm/i915/display/intel_fbc.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 /**
  25  * DOC: Frame Buffer Compression (FBC)
  26  *
  27  * FBC tries to save memory bandwidth (and so power consumption) by
  28  * compressing the amount of memory used by the display. It is total
  29  * transparent to user space and completely handled in the kernel.
  30  *
  31  * The benefits of FBC are mostly visible with solid backgrounds and
  32  * variation-less patterns. It comes from keeping the memory footprint small
  33  * and having fewer memory pages opened and accessed for refreshing the display.
  34  *
  35  * i915 is responsible to reserve stolen memory for FBC and configure its
  36  * offset on proper registers. The hardware takes care of all
  37  * compress/decompress. However there are many known cases where we have to
  38  * forcibly disable it to allow proper screen updates.
  39  */
  40
  41 #include <drm/drm_fourcc.h>
  42
  43 #include "i915_drv.h"
  44 #include "i915_trace.h"
  45 #include "i915_vgpu.h"
  46 #include "intel_display_types.h"
  47 #include "intel_fbc.h"
  48 #include "intel_frontbuffer.h"
  49
  50 /*
  51  * In some platforms where the CRTC's x:0/y:0 coordinates doesn't match the
  52  * frontbuffer's x:0/y:0 coordinates we lie to the hardware about the plane's
  53  * origin so the x and y offsets can actually fit the registers. As a
  54  * consequence, the fence doesn't really start exactly at the display plane
  55  * address we program because it starts at the real start of the buffer, so we
  56  * have to take this into consideration here.
  57  */
  58 static unsigned int get_crtc_fence_y_offset(struct intel_fbc *fbc)
  59 {
  60         return fbc->state_cache.plane.y - fbc->state_cache.plane.adjusted_y;
  61 }
  62
  63 /*
  64  * For SKL+, the plane source size used by the hardware is based on the value we
  65  * write to the PLANE_SIZE register. For BDW-, the hardware looks at the value
  66  * we wrote to PIPESRC.
  67  */
  68 static void intel_fbc_get_plane_source_size(const struct intel_fbc_state_cache *cache,
  69                                             int *width, int *height)
  70 {
  71         if (width)
  72                 *width = cache->plane.src_w;
  73         if (height)
  74                 *height = cache->plane.src_h;
  75 }
  76
  77 static int intel_fbc_calculate_cfb_size(struct drm_i915_private *dev_priv,
  78                                         const struct intel_fbc_state_cache *cache)
  79 {
  80         int lines;
  81
  82         intel_fbc_get_plane_source_size(cache, NULL, &lines);
  83         if (IS_GEN(dev_priv, 7))
  84                 lines = min(lines, 2048);
  85         else if (INTEL_GEN(dev_priv) >= 8)
  86                 lines = min(lines, 2560);
  87
  88         /* Hardware needs the full buffer stride, not just the active area. */
  89         return lines * cache->fb.stride;
  90 }
  91
  92 static void i8xx_fbc_deactivate(struct drm_i915_private *dev_priv)
  93 {
  94         u32 fbc_ctl;
  95
  96         /* Disable compression */
  97         fbc_ctl = intel_de_read(dev_priv, FBC_CONTROL);
  98         if ((fbc_ctl & FBC_CTL_EN) == 0)
  99                 return;
 100
 101         fbc_ctl &= ~FBC_CTL_EN;
 102         intel_de_write(dev_priv, FBC_CONTROL, fbc_ctl);
 103
 104         /* Wait for compressing bit to clear */
 105         if (intel_de_wait_for_clear(dev_priv, FBC_STATUS,
 106                                     FBC_STAT_COMPRESSING, 10)) {
 107                 drm_dbg_kms(&dev_priv->drm, "FBC idle timed out\n");
 108                 return;
 109         }
 110 }
 111
 112 static void i8xx_fbc_activate(struct drm_i915_private *dev_priv)
 113 {
 114         struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
 115         int cfb_pitch;
 116         int i;
 117         u32 fbc_ctl;
 118
 119         /* Note: fbc.threshold == 1 for i8xx */
 120         cfb_pitch = params->cfb_size / FBC_LL_SIZE;
 121         if (params->fb.stride < cfb_pitch)
 122                 cfb_pitch = params->fb.stride;
 123
 124         /* FBC_CTL wants 32B or 64B units */
 125         if (IS_GEN(dev_priv, 2))
 126                 cfb_pitch = (cfb_pitch / 32) - 1;
 127         else
 128                 cfb_pitch = (cfb_pitch / 64) - 1;
 129
 130         /* Clear old tags */
 131         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
 132                 intel_de_write(dev_priv, FBC_TAG(i), 0);
 133
 134         if (IS_GEN(dev_priv, 4)) {
 135                 u32 fbc_ctl2;
 136
 137                 /* Set it up... */
 138                 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM;
 139                 fbc_ctl2 |= FBC_CTL_PLANE(params->crtc.i9xx_plane);
 140                 if (params->fence_id >= 0)
 141                         fbc_ctl2 |= FBC_CTL_CPU_FENCE;
 142                 intel_de_write(dev_priv, FBC_CONTROL2, fbc_ctl2);
 143                 intel_de_write(dev_priv, FBC_FENCE_OFF,
 144                                params->crtc.fence_y_offset);
 145         }
 146
 147         /* enable it... */
 148         fbc_ctl = intel_de_read(dev_priv, FBC_CONTROL);
 149         fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT;
 150         fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC;
 151         if (IS_I945GM(dev_priv))
 152                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
 153         fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
 154         if (params->fence_id >= 0)
 155                 fbc_ctl |= params->fence_id;
 156         intel_de_write(dev_priv, FBC_CONTROL, fbc_ctl);
 157 }
 158
 159 static bool i8xx_fbc_is_active(struct drm_i915_private *dev_priv)
 160 {
 161         return intel_de_read(dev_priv, FBC_CONTROL) & FBC_CTL_EN;
 162 }
 163
 164 static void g4x_fbc_activate(struct drm_i915_private *dev_priv)
 165 {
 166         struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
 167         u32 dpfc_ctl;
 168
 169         dpfc_ctl = DPFC_CTL_PLANE(params->crtc.i9xx_plane) | DPFC_SR_EN;
 170         if (params->fb.format->cpp[0] == 2)
 171                 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 172         else
 173                 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 174
 175         if (params->fence_id >= 0) {
 176                 dpfc_ctl |= DPFC_CTL_FENCE_EN | params->fence_id;
 177                 intel_de_write(dev_priv, DPFC_FENCE_YOFF,
 178                                params->crtc.fence_y_offset);
 179         } else {
 180                 intel_de_write(dev_priv, DPFC_FENCE_YOFF, 0);
 181         }
 182
 183         /* enable it... */
 184         intel_de_write(dev_priv, DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 185 }
 186
 187 static void g4x_fbc_deactivate(struct drm_i915_private *dev_priv)
 188 {
 189         u32 dpfc_ctl;
 190
 191         /* Disable compression */
 192         dpfc_ctl = intel_de_read(dev_priv, DPFC_CONTROL);
 193         if (dpfc_ctl & DPFC_CTL_EN) {
 194                 dpfc_ctl &= ~DPFC_CTL_EN;
 195                 intel_de_write(dev_priv, DPFC_CONTROL, dpfc_ctl);
 196         }
 197 }
 198
 199 static bool g4x_fbc_is_active(struct drm_i915_private *dev_priv)
 200 {
 201         return intel_de_read(dev_priv, DPFC_CONTROL) & DPFC_CTL_EN;
 202 }
 203
 204 /* This function forces a CFB recompression through the nuke operation. */
 205 static void intel_fbc_recompress(struct drm_i915_private *dev_priv)
 206 {
 207         struct intel_fbc *fbc = &dev_priv->fbc;
 208
 209         trace_intel_fbc_nuke(fbc->crtc);
 210
 211         intel_de_write(dev_priv, MSG_FBC_REND_STATE, FBC_REND_NUKE);
 212         intel_de_posting_read(dev_priv, MSG_FBC_REND_STATE);
 213 }
 214
 215 static void ilk_fbc_activate(struct drm_i915_private *dev_priv)
 216 {
 217         struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
 218         u32 dpfc_ctl;
 219         int threshold = dev_priv->fbc.threshold;
 220
 221         dpfc_ctl = DPFC_CTL_PLANE(params->crtc.i9xx_plane);
 222         if (params->fb.format->cpp[0] == 2)
 223                 threshold++;
 224
 225         switch (threshold) {
 226         case 4:
 227         case 3:
 228                 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
 229                 break;
 230         case 2:
 231                 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 232                 break;
 233         case 1:
 234                 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 235                 break;
 236         }
 237
 238         if (params->fence_id >= 0) {
 239                 dpfc_ctl |= DPFC_CTL_FENCE_EN;
 240                 if (IS_GEN(dev_priv, 5))
 241                         dpfc_ctl |= params->fence_id;
 242                 if (IS_GEN(dev_priv, 6)) {
 243                         intel_de_write(dev_priv, SNB_DPFC_CTL_SA,
 244                                        SNB_CPU_FENCE_ENABLE | params->fence_id);
 245                         intel_de_write(dev_priv, DPFC_CPU_FENCE_OFFSET,
 246                                        params->crtc.fence_y_offset);
 247                 }
 248         } else {
 249                 if (IS_GEN(dev_priv, 6)) {
 250                         intel_de_write(dev_priv, SNB_DPFC_CTL_SA, 0);
 251                         intel_de_write(dev_priv, DPFC_CPU_FENCE_OFFSET, 0);
 252                 }
 253         }
 254
 255         intel_de_write(dev_priv, ILK_DPFC_FENCE_YOFF,
 256                        params->crtc.fence_y_offset);
 257         /* enable it... */
 258         intel_de_write(dev_priv, ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 259
 260         intel_fbc_recompress(dev_priv);
 261 }
 262
 263 static void ilk_fbc_deactivate(struct drm_i915_private *dev_priv)
 264 {
 265         u32 dpfc_ctl;
 266
 267         /* Disable compression */
 268         dpfc_ctl = intel_de_read(dev_priv, ILK_DPFC_CONTROL);
 269         if (dpfc_ctl & DPFC_CTL_EN) {
 270                 dpfc_ctl &= ~DPFC_CTL_EN;
 271                 intel_de_write(dev_priv, ILK_DPFC_CONTROL, dpfc_ctl);
 272         }
 273 }
 274
 275 static bool ilk_fbc_is_active(struct drm_i915_private *dev_priv)
 276 {
 277         return intel_de_read(dev_priv, ILK_DPFC_CONTROL) & DPFC_CTL_EN;
 278 }
 279
 280 static void gen7_fbc_activate(struct drm_i915_private *dev_priv)
 281 {
 282         struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
 283         u32 dpfc_ctl;
 284         int threshold = dev_priv->fbc.threshold;
 285
 286         /* Display WA #0529: skl, kbl, bxt. */
 287         if (IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv)) {
 288                 u32 val = intel_de_read(dev_priv, CHICKEN_MISC_4);
 289
 290                 val &= ~(FBC_STRIDE_OVERRIDE | FBC_STRIDE_MASK);
 291
 292                 if (params->gen9_wa_cfb_stride)
 293                         val |= FBC_STRIDE_OVERRIDE | params->gen9_wa_cfb_stride;
 294
 295                 intel_de_write(dev_priv, CHICKEN_MISC_4, val);
 296         }
 297
 298         dpfc_ctl = 0;
 299         if (IS_IVYBRIDGE(dev_priv))
 300                 dpfc_ctl |= IVB_DPFC_CTL_PLANE(params->crtc.i9xx_plane);
 301
 302         if (params->fb.format->cpp[0] == 2)
 303                 threshold++;
 304
 305         switch (threshold) {
 306         case 4:
 307         case 3:
 308                 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
 309                 break;
 310         case 2:
 311                 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 312                 break;
 313         case 1:
 314                 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 315                 break;
 316         }
 317
 318         if (params->fence_id >= 0) {
 319                 dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
 320                 intel_de_write(dev_priv, SNB_DPFC_CTL_SA,
 321                                SNB_CPU_FENCE_ENABLE | params->fence_id);
 322                 intel_de_write(dev_priv, DPFC_CPU_FENCE_OFFSET,
 323                                params->crtc.fence_y_offset);
 324         } else if (dev_priv->ggtt.num_fences) {
 325                 intel_de_write(dev_priv, SNB_DPFC_CTL_SA, 0);
 326                 intel_de_write(dev_priv, DPFC_CPU_FENCE_OFFSET, 0);
 327         }
 328
 329         if (dev_priv->fbc.false_color)
 330                 dpfc_ctl |= FBC_CTL_FALSE_COLOR;
 331
 332         if (IS_IVYBRIDGE(dev_priv)) {
 333                 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
 334                 intel_de_write(dev_priv, ILK_DISPLAY_CHICKEN1,
 335                                intel_de_read(dev_priv, ILK_DISPLAY_CHICKEN1) | ILK_FBCQ_DIS);
 336         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
 337                 /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
 338                 intel_de_write(dev_priv, CHICKEN_PIPESL_1(params->crtc.pipe),
 339                                intel_de_read(dev_priv, CHICKEN_PIPESL_1(params->crtc.pipe)) | HSW_FBCQ_DIS);
 340         }
 341
 342         if (INTEL_GEN(dev_priv) >= 11)
 343                 /* Wa_1409120013:icl,ehl,tgl */
 344                 intel_de_write(dev_priv, ILK_DPFC_CHICKEN,
 345                                ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL);
 346
 347         intel_de_write(dev_priv, ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 348
 349         intel_fbc_recompress(dev_priv);
 350 }
 351
 352 static bool intel_fbc_hw_is_active(struct drm_i915_private *dev_priv)
 353 {
 354         if (INTEL_GEN(dev_priv) >= 5)
 355                 return ilk_fbc_is_active(dev_priv);
 356         else if (IS_GM45(dev_priv))
 357                 return g4x_fbc_is_active(dev_priv);
 358         else
 359                 return i8xx_fbc_is_active(dev_priv);
 360 }
 361
 362 static void intel_fbc_hw_activate(struct drm_i915_private *dev_priv)
 363 {
 364         struct intel_fbc *fbc = &dev_priv->fbc;
 365
 366         trace_intel_fbc_activate(fbc->crtc);
 367
 368         fbc->active = true;
 369         fbc->activated = true;
 370
 371         if (INTEL_GEN(dev_priv) >= 7)
 372                 gen7_fbc_activate(dev_priv);
 373         else if (INTEL_GEN(dev_priv) >= 5)
 374                 ilk_fbc_activate(dev_priv);
 375         else if (IS_GM45(dev_priv))
 376                 g4x_fbc_activate(dev_priv);
 377         else
 378                 i8xx_fbc_activate(dev_priv);
 379 }
 380
 381 static void intel_fbc_hw_deactivate(struct drm_i915_private *dev_priv)
 382 {
 383         struct intel_fbc *fbc = &dev_priv->fbc;
 384
 385         trace_intel_fbc_deactivate(fbc->crtc);
 386
 387         fbc->active = false;
 388
 389         if (INTEL_GEN(dev_priv) >= 5)
 390                 ilk_fbc_deactivate(dev_priv);
 391         else if (IS_GM45(dev_priv))
 392                 g4x_fbc_deactivate(dev_priv);
 393         else
 394                 i8xx_fbc_deactivate(dev_priv);
 395 }
 396
 397 /**
 398  * intel_fbc_is_active - Is FBC active?
 399  * @dev_priv: i915 device instance
 400  *
 401  * This function is used to verify the current state of FBC.
 402  *
 403  * FIXME: This should be tracked in the plane config eventually
 404  * instead of queried at runtime for most callers.
 405  */
 406 bool intel_fbc_is_active(struct drm_i915_private *dev_priv)
 407 {
 408         return dev_priv->fbc.active;
 409 }
 410
 411 static void intel_fbc_deactivate(struct drm_i915_private *dev_priv,
 412                                  const char *reason)
 413 {
 414         struct intel_fbc *fbc = &dev_priv->fbc;
 415
 416         drm_WARN_ON(&dev_priv->drm, !mutex_is_locked(&fbc->lock));
 417
 418         if (fbc->active)
 419                 intel_fbc_hw_deactivate(dev_priv);
 420
 421         fbc->no_fbc_reason = reason;
 422 }
 423
 424 static int find_compression_threshold(struct drm_i915_private *dev_priv,
 425                                       struct drm_mm_node *node,
 426                                       unsigned int size,
 427                                       unsigned int fb_cpp)
 428 {
 429         int compression_threshold = 1;
 430         int ret;
 431         u64 end;
 432
 433         /* The FBC hardware for BDW/SKL doesn't have access to the stolen
 434          * reserved range size, so it always assumes the maximum (8mb) is used.
 435          * If we enable FBC using a CFB on that memory range we'll get FIFO
 436          * underruns, even if that range is not reserved by the BIOS. */
 437         if (IS_BROADWELL(dev_priv) || IS_GEN9_BC(dev_priv))
 438                 end = resource_size(&dev_priv->dsm) - 8 * 1024 * 1024;
 439         else
 440                 end = U64_MAX;
 441
 442         /* HACK: This code depends on what we will do in *_enable_fbc. If that
 443          * code changes, this code needs to change as well.
 444          *
 445          * The enable_fbc code will attempt to use one of our 2 compression
 446          * thresholds, therefore, in that case, we only have 1 resort.
 447          */
 448
 449         /* Try to over-allocate to reduce reallocations and fragmentation. */
 450         ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size <<= 1,
 451                                                    4096, 0, end);
 452         if (ret == 0)
 453                 return compression_threshold;
 454
 455 again:
 456         /* HW's ability to limit the CFB is 1:4 */
 457         if (compression_threshold > 4 ||
 458             (fb_cpp == 2 && compression_threshold == 2))
 459                 return 0;
 460
 461         ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size >>= 1,
 462                                                    4096, 0, end);
 463         if (ret && INTEL_GEN(dev_priv) <= 4) {
 464                 return 0;
 465         } else if (ret) {
 466                 compression_threshold <<= 1;
 467                 goto again;
 468         } else {
 469                 return compression_threshold;
 470         }
 471 }
 472
 473 static int intel_fbc_alloc_cfb(struct drm_i915_private *dev_priv,
 474                                unsigned int size, unsigned int fb_cpp)
 475 {
 476         struct intel_fbc *fbc = &dev_priv->fbc;
 477         struct drm_mm_node *uninitialized_var(compressed_llb);
 478         int ret;
 479
 480         drm_WARN_ON(&dev_priv->drm,
 481                     drm_mm_node_allocated(&fbc->compressed_fb));
 482
 483         ret = find_compression_threshold(dev_priv, &fbc->compressed_fb,
 484                                          size, fb_cpp);
 485         if (!ret)
 486                 goto err_llb;
 487         else if (ret > 1) {
 488                 drm_info_once(&dev_priv->drm,
 489                               "Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS.\n");
 490         }
 491
 492         fbc->threshold = ret;
 493
 494         if (INTEL_GEN(dev_priv) >= 5)
 495                 intel_de_write(dev_priv, ILK_DPFC_CB_BASE,
 496                                fbc->compressed_fb.start);
 497         else if (IS_GM45(dev_priv)) {
 498                 intel_de_write(dev_priv, DPFC_CB_BASE,
 499                                fbc->compressed_fb.start);
 500         } else {
 501                 compressed_llb = kzalloc(sizeof(*compressed_llb), GFP_KERNEL);
 502                 if (!compressed_llb)
 503                         goto err_fb;
 504
 505                 ret = i915_gem_stolen_insert_node(dev_priv, compressed_llb,
 506                                                   4096, 4096);
 507                 if (ret)
 508                         goto err_fb;
 509
 510                 fbc->compressed_llb = compressed_llb;
 511
 512                 GEM_BUG_ON(range_overflows_end_t(u64, dev_priv->dsm.start,
 513                                                  fbc->compressed_fb.start,
 514                                                  U32_MAX));
 515                 GEM_BUG_ON(range_overflows_end_t(u64, dev_priv->dsm.start,
 516                                                  fbc->compressed_llb->start,
 517                                                  U32_MAX));
 518                 intel_de_write(dev_priv, FBC_CFB_BASE,
 519                                dev_priv->dsm.start + fbc->compressed_fb.start);
 520                 intel_de_write(dev_priv, FBC_LL_BASE,
 521                                dev_priv->dsm.start + compressed_llb->start);
 522         }
 523
 524         drm_dbg_kms(&dev_priv->drm,
 525                     "reserved %llu bytes of contiguous stolen space for FBC, threshold: %d\n",
 526                     fbc->compressed_fb.size, fbc->threshold);
 527
 528         return 0;
 529
 530 err_fb:
 531         kfree(compressed_llb);
 532         i915_gem_stolen_remove_node(dev_priv, &fbc->compressed_fb);
 533 err_llb:
 534         if (drm_mm_initialized(&dev_priv->mm.stolen))
 535                 drm_info_once(&dev_priv->drm, "not enough stolen space for compressed buffer (need %d more bytes), disabling. Hint: you may be able to increase stolen memory size in the BIOS to avoid this.\n", size);
 536         return -ENOSPC;
 537 }
 538
 539 static void __intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv)
 540 {
 541         struct intel_fbc *fbc = &dev_priv->fbc;
 542
 543         if (!drm_mm_node_allocated(&fbc->compressed_fb))
 544                 return;
 545
 546         if (fbc->compressed_llb) {
 547                 i915_gem_stolen_remove_node(dev_priv, fbc->compressed_llb);
 548                 kfree(fbc->compressed_llb);
 549         }
 550
 551         i915_gem_stolen_remove_node(dev_priv, &fbc->compressed_fb);
 552 }
 553
 554 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv)
 555 {
 556         struct intel_fbc *fbc = &dev_priv->fbc;
 557
 558         if (!HAS_FBC(dev_priv))
 559                 return;
 560
 561         mutex_lock(&fbc->lock);
 562         __intel_fbc_cleanup_cfb(dev_priv);
 563         mutex_unlock(&fbc->lock);
 564 }
 565
 566 static bool stride_is_valid(struct drm_i915_private *dev_priv,
 567                             unsigned int stride)
 568 {
 569         /* This should have been caught earlier. */
 570         if (drm_WARN_ON_ONCE(&dev_priv->drm, (stride & (64 - 1)) != 0))
 571                 return false;
 572
 573         /* Below are the additional FBC restrictions. */
 574         if (stride < 512)
 575                 return false;
 576
 577         if (IS_GEN(dev_priv, 2) || IS_GEN(dev_priv, 3))
 578                 return stride == 4096 || stride == 8192;
 579
 580         if (IS_GEN(dev_priv, 4) && !IS_G4X(dev_priv) && stride < 2048)
 581                 return false;
 582
 583         if (stride > 16384)
 584                 return false;
 585
 586         return true;
 587 }
 588
 589 static bool pixel_format_is_valid(struct drm_i915_private *dev_priv,
 590                                   u32 pixel_format)
 591 {
 592         switch (pixel_format) {
 593         case DRM_FORMAT_XRGB8888:
 594         case DRM_FORMAT_XBGR8888:
 595                 return true;
 596         case DRM_FORMAT_XRGB1555:
 597         case DRM_FORMAT_RGB565:
 598                 /* 16bpp not supported on gen2 */
 599                 if (IS_GEN(dev_priv, 2))
 600                         return false;
 601                 /* WaFbcOnly1to1Ratio:ctg */
 602                 if (IS_G4X(dev_priv))
 603                         return false;
 604                 return true;
 605         default:
 606                 return false;
 607         }
 608 }
 609
 610 static bool rotation_is_valid(struct drm_i915_private *dev_priv,
 611                               u32 pixel_format, unsigned int rotation)
 612 {
 613         if (INTEL_GEN(dev_priv) >= 9 && pixel_format == DRM_FORMAT_RGB565 &&
 614             drm_rotation_90_or_270(rotation))
 615                 return false;
 616         else if (INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv) &&
 617                  rotation != DRM_MODE_ROTATE_0)
 618                 return false;
 619
 620         return true;
 621 }
 622
 623 /*
 624  * For some reason, the hardware tracking starts looking at whatever we
 625  * programmed as the display plane base address register. It does not look at
 626  * the X and Y offset registers. That's why we look at the crtc->adjusted{x,y}
 627  * variables instead of just looking at the pipe/plane size.
 628  */
 629 static bool intel_fbc_hw_tracking_covers_screen(struct intel_crtc *crtc)
 630 {
 631         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 632         struct intel_fbc *fbc = &dev_priv->fbc;
 633         unsigned int effective_w, effective_h, max_w, max_h;
 634
 635         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
 636                 max_w = 5120;
 637                 max_h = 4096;
 638         } else if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv)) {
 639                 max_w = 4096;
 640                 max_h = 4096;
 641         } else if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
 642                 max_w = 4096;
 643                 max_h = 2048;
 644         } else {
 645                 max_w = 2048;
 646                 max_h = 1536;
 647         }
 648
 649         intel_fbc_get_plane_source_size(&fbc->state_cache, &effective_w,
 650                                         &effective_h);
 651         effective_w += fbc->state_cache.plane.adjusted_x;
 652         effective_h += fbc->state_cache.plane.adjusted_y;
 653
 654         return effective_w <= max_w && effective_h <= max_h;
 655 }
 656
 657 static bool tiling_is_valid(struct drm_i915_private *dev_priv,
 658                             uint64_t modifier)
 659 {
 660         switch (modifier) {
 661         case DRM_FORMAT_MOD_LINEAR:
 662                 if (INTEL_GEN(dev_priv) >= 9)
 663                         return true;
 664                 return false;
 665         case I915_FORMAT_MOD_X_TILED:
 666         case I915_FORMAT_MOD_Y_TILED:
 667                 return true;
 668         default:
 669                 return false;
 670         }
 671 }
 672
 673 static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
 674                                          const struct intel_crtc_state *crtc_state,
 675                                          const struct intel_plane_state *plane_state)
 676 {
 677         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 678         struct intel_fbc *fbc = &dev_priv->fbc;
 679         struct intel_fbc_state_cache *cache = &fbc->state_cache;
 680         struct drm_framebuffer *fb = plane_state->hw.fb;
 681
 682         cache->plane.visible = plane_state->uapi.visible;
 683         if (!cache->plane.visible)
 684                 return;
 685
 686         cache->crtc.mode_flags = crtc_state->hw.adjusted_mode.flags;
 687         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 688                 cache->crtc.hsw_bdw_pixel_rate = crtc_state->pixel_rate;
 689
 690         cache->plane.rotation = plane_state->hw.rotation;
 691         /*
 692          * Src coordinates are already rotated by 270 degrees for
 693          * the 90/270 degree plane rotation cases (to match the
 694          * GTT mapping), hence no need to account for rotation here.
 695          */
 696         cache->plane.src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
 697         cache->plane.src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
 698         cache->plane.adjusted_x = plane_state->color_plane[0].x;
 699         cache->plane.adjusted_y = plane_state->color_plane[0].y;
 700         cache->plane.y = plane_state->uapi.src.y1 >> 16;
 701
 702         cache->plane.pixel_blend_mode = plane_state->hw.pixel_blend_mode;
 703
 704         cache->fb.format = fb->format;
 705         cache->fb.stride = fb->pitches[0];
 706         cache->fb.modifier = fb->modifier;
 707
 708         drm_WARN_ON(&dev_priv->drm, plane_state->flags & PLANE_HAS_FENCE &&
 709                     !plane_state->vma->fence);
 710
 711         if (plane_state->flags & PLANE_HAS_FENCE &&
 712             plane_state->vma->fence)
 713                 cache->fence_id = plane_state->vma->fence->id;
 714         else
 715                 cache->fence_id = -1;
 716 }
 717
 718 static bool intel_fbc_cfb_size_changed(struct drm_i915_private *dev_priv)
 719 {
 720         struct intel_fbc *fbc = &dev_priv->fbc;
 721
 722         return intel_fbc_calculate_cfb_size(dev_priv, &fbc->state_cache) >
 723                 fbc->compressed_fb.size * fbc->threshold;
 724 }
 725
 726 static bool intel_fbc_can_enable(struct drm_i915_private *dev_priv)
 727 {
 728         struct intel_fbc *fbc = &dev_priv->fbc;
 729
 730         if (intel_vgpu_active(dev_priv)) {
 731                 fbc->no_fbc_reason = "VGPU is active";
 732                 return false;
 733         }
 734
 735         if (!i915_modparams.enable_fbc) {
 736                 fbc->no_fbc_reason = "disabled per module param or by default";
 737                 return false;
 738         }
 739
 740         if (fbc->underrun_detected) {
 741                 fbc->no_fbc_reason = "underrun detected";
 742                 return false;
 743         }
 744
 745         return true;
 746 }
 747
 748 static bool intel_fbc_can_activate(struct intel_crtc *crtc)
 749 {
 750         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 751         struct intel_fbc *fbc = &dev_priv->fbc;
 752         struct intel_fbc_state_cache *cache = &fbc->state_cache;
 753
 754         if (!intel_fbc_can_enable(dev_priv))
 755                 return false;
 756
 757         if (!cache->plane.visible) {
 758                 fbc->no_fbc_reason = "primary plane not visible";
 759                 return false;
 760         }
 761
 762         /* We don't need to use a state cache here since this information is
 763          * global for all CRTC.
 764          */
 765         if (fbc->underrun_detected) {
 766                 fbc->no_fbc_reason = "underrun detected";
 767                 return false;
 768         }
 769
 770         if (cache->crtc.mode_flags & DRM_MODE_FLAG_INTERLACE) {
 771                 fbc->no_fbc_reason = "incompatible mode";
 772                 return false;
 773         }
 774
 775         if (!intel_fbc_hw_tracking_covers_screen(crtc)) {
 776                 fbc->no_fbc_reason = "mode too large for compression";
 777                 return false;
 778         }
 779
 780         /* The use of a CPU fence is one of two ways to detect writes by the
 781          * CPU to the scanout and trigger updates to the FBC.
 782          *
 783          * The other method is by software tracking (see
 784          * intel_fbc_invalidate/flush()), it will manually notify FBC and nuke
 785          * the current compressed buffer and recompress it.
 786          *
 787          * Note that is possible for a tiled surface to be unmappable (and
 788          * so have no fence associated with it) due to aperture constraints
 789          * at the time of pinning.
 790          *
 791          * FIXME with 90/270 degree rotation we should use the fence on
 792          * the normal GTT view (the rotated view doesn't even have a
 793          * fence). Would need changes to the FBC fence Y offset as well.
 794          * For now this will effectively disable FBC with 90/270 degree
 795          * rotation.
 796          */
 797         if (INTEL_GEN(dev_priv) < 9 && cache->fence_id < 0) {
 798                 fbc->no_fbc_reason = "framebuffer not tiled or fenced";
 799                 return false;
 800         }
 801
 802         if (!rotation_is_valid(dev_priv, cache->fb.format->format,
 803                                cache->plane.rotation)) {
 804                 fbc->no_fbc_reason = "rotation unsupported";
 805                 return false;
 806         }
 807
 808         if (!tiling_is_valid(dev_priv, cache->fb.modifier)) {
 809                 fbc->no_fbc_reason = "tiling unsupported";
 810                 return false;
 811         }
 812
 813         if (!stride_is_valid(dev_priv, cache->fb.stride)) {
 814                 fbc->no_fbc_reason = "framebuffer stride not supported";
 815                 return false;
 816         }
 817
 818         if (!pixel_format_is_valid(dev_priv, cache->fb.format->format)) {
 819                 fbc->no_fbc_reason = "pixel format is invalid";
 820                 return false;
 821         }
 822
 823         if (cache->plane.pixel_blend_mode != DRM_MODE_BLEND_PIXEL_NONE &&
 824             cache->fb.format->has_alpha) {
 825                 fbc->no_fbc_reason = "per-pixel alpha blending is incompatible with FBC";
 826                 return false;
 827         }
 828
 829         /* WaFbcExceedCdClockThreshold:hsw,bdw */
 830         if ((IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) &&
 831             cache->crtc.hsw_bdw_pixel_rate >= dev_priv->cdclk.hw.cdclk * 95 / 100) {
 832                 fbc->no_fbc_reason = "pixel rate is too big";
 833                 return false;
 834         }
 835
 836         /* It is possible for the required CFB size change without a
 837          * crtc->disable + crtc->enable since it is possible to change the
 838          * stride without triggering a full modeset. Since we try to
 839          * over-allocate the CFB, there's a chance we may keep FBC enabled even
 840          * if this happens, but if we exceed the current CFB size we'll have to
 841          * disable FBC. Notice that it would be possible to disable FBC, wait
 842          * for a frame, free the stolen node, then try to reenable FBC in case
 843          * we didn't get any invalidate/deactivate calls, but this would require
 844          * a lot of tracking just for a specific case. If we conclude it's an
 845          * important case, we can implement it later. */
 846         if (intel_fbc_cfb_size_changed(dev_priv)) {
 847                 fbc->no_fbc_reason = "CFB requirements changed";
 848                 return false;
 849         }
 850
 851         /*
 852          * Work around a problem on GEN9+ HW, where enabling FBC on a plane
 853          * having a Y offset that isn't divisible by 4 causes FIFO underrun
 854          * and screen flicker.
 855          */
 856         if (INTEL_GEN(dev_priv) >= 9 &&
 857             (fbc->state_cache.plane.adjusted_y & 3)) {
 858                 fbc->no_fbc_reason = "plane Y offset is misaligned";
 859                 return false;
 860         }
 861
 862         return true;
 863 }
 864
 865 static void intel_fbc_get_reg_params(struct intel_crtc *crtc,
 866                                      struct intel_fbc_reg_params *params)
 867 {
 868         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 869         struct intel_fbc *fbc = &dev_priv->fbc;
 870         struct intel_fbc_state_cache *cache = &fbc->state_cache;
 871
 872         /* Since all our fields are integer types, use memset here so the
 873          * comparison function can rely on memcmp because the padding will be
 874          * zero. */
 875         memset(params, 0, sizeof(*params));
 876
 877         params->fence_id = cache->fence_id;
 878
 879         params->crtc.pipe = crtc->pipe;
 880         params->crtc.i9xx_plane = to_intel_plane(crtc->base.primary)->i9xx_plane;
 881         params->crtc.fence_y_offset = get_crtc_fence_y_offset(fbc);
 882
 883         params->fb.format = cache->fb.format;
 884         params->fb.stride = cache->fb.stride;
 885
 886         params->cfb_size = intel_fbc_calculate_cfb_size(dev_priv, cache);
 887
 888         params->gen9_wa_cfb_stride = cache->gen9_wa_cfb_stride;
 889
 890         params->plane_visible = cache->plane.visible;
 891 }
 892
 893 static bool intel_fbc_can_flip_nuke(const struct intel_crtc_state *crtc_state)
 894 {
 895         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 896         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 897         const struct intel_fbc *fbc = &dev_priv->fbc;
 898         const struct intel_fbc_state_cache *cache = &fbc->state_cache;
 899         const struct intel_fbc_reg_params *params = &fbc->params;
 900
 901         if (drm_atomic_crtc_needs_modeset(&crtc_state->uapi))
 902                 return false;
 903
 904         if (!params->plane_visible)
 905                 return false;
 906
 907         if (!intel_fbc_can_activate(crtc))
 908                 return false;
 909
 910         if (params->fb.format != cache->fb.format)
 911                 return false;
 912
 913         if (params->fb.stride != cache->fb.stride)
 914                 return false;
 915
 916         if (params->cfb_size != intel_fbc_calculate_cfb_size(dev_priv, cache))
 917                 return false;
 918
 919         if (params->gen9_wa_cfb_stride != cache->gen9_wa_cfb_stride)
 920                 return false;
 921
 922         return true;
 923 }
 924
 925 bool intel_fbc_pre_update(struct intel_atomic_state *state,
 926                           struct intel_crtc *crtc)
 927 {
 928         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
 929         const struct intel_crtc_state *crtc_state =
 930                 intel_atomic_get_new_crtc_state(state, crtc);
 931         const struct intel_plane_state *plane_state =
 932                 intel_atomic_get_new_plane_state(state, plane);
 933         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 934         struct intel_fbc *fbc = &dev_priv->fbc;
 935         const char *reason = "update pending";
 936         bool need_vblank_wait = false;
 937
 938         if (!plane->has_fbc || !plane_state)
 939                 return need_vblank_wait;
 940
 941         mutex_lock(&fbc->lock);
 942
 943         if (fbc->crtc != crtc)
 944                 goto unlock;
 945
 946         intel_fbc_update_state_cache(crtc, crtc_state, plane_state);
 947         fbc->flip_pending = true;
 948
 949         if (!intel_fbc_can_flip_nuke(crtc_state)) {
 950                 intel_fbc_deactivate(dev_priv, reason);
 951
 952                 /*
 953                  * Display WA #1198: glk+
 954                  * Need an extra vblank wait between FBC disable and most plane
 955                  * updates. Bspec says this is only needed for plane disable, but
 956                  * that is not true. Touching most plane registers will cause the
 957                  * corruption to appear. Also SKL/derivatives do not seem to be
 958                  * affected.
 959                  *
 960                  * TODO: could optimize this a bit by sampling the frame
 961                  * counter when we disable FBC (if it was already done earlier)
 962                  * and skipping the extra vblank wait before the plane update
 963                  * if at least one frame has already passed.
 964                  */
 965                 if (fbc->activated &&
 966                     (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)))
 967                         need_vblank_wait = true;
 968                 fbc->activated = false;
 969         }
 970 unlock:
 971         mutex_unlock(&fbc->lock);
 972
 973         return need_vblank_wait;
 974 }
 975
 976 /**
 977  * __intel_fbc_disable - disable FBC
 978  * @dev_priv: i915 device instance
 979  *
 980  * This is the low level function that actually disables FBC. Callers should
 981  * grab the FBC lock.
 982  */
 983 static void __intel_fbc_disable(struct drm_i915_private *dev_priv)
 984 {
 985         struct intel_fbc *fbc = &dev_priv->fbc;
 986         struct intel_crtc *crtc = fbc->crtc;
 987
 988         drm_WARN_ON(&dev_priv->drm, !mutex_is_locked(&fbc->lock));
 989         drm_WARN_ON(&dev_priv->drm, !fbc->crtc);
 990         drm_WARN_ON(&dev_priv->drm, fbc->active);
 991
 992         drm_dbg_kms(&dev_priv->drm, "Disabling FBC on pipe %c\n",
 993                     pipe_name(crtc->pipe));
 994
 995         __intel_fbc_cleanup_cfb(dev_priv);
 996
 997         fbc->crtc = NULL;
 998 }
 999
1000 static void __intel_fbc_post_update(struct intel_crtc *crtc)
1001 {
1002         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1003         struct intel_fbc *fbc = &dev_priv->fbc;
1004
1005         drm_WARN_ON(&dev_priv->drm, !mutex_is_locked(&fbc->lock));
1006
1007         if (fbc->crtc != crtc)
1008                 return;
1009
1010         fbc->flip_pending = false;
1011
1012         if (!i915_modparams.enable_fbc) {
1013                 intel_fbc_deactivate(dev_priv, "disabled at runtime per module param");
1014                 __intel_fbc_disable(dev_priv);
1015
1016                 return;
1017         }
1018
1019         intel_fbc_get_reg_params(crtc, &fbc->params);
1020
1021         if (!intel_fbc_can_activate(crtc))
1022                 return;
1023
1024         if (!fbc->busy_bits)
1025                 intel_fbc_hw_activate(dev_priv);
1026         else
1027                 intel_fbc_deactivate(dev_priv, "frontbuffer write");
1028 }
1029
1030 void intel_fbc_post_update(struct intel_atomic_state *state,
1031                            struct intel_crtc *crtc)
1032 {
1033         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1034         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
1035         const struct intel_plane_state *plane_state =
1036                 intel_atomic_get_new_plane_state(state, plane);
1037         struct intel_fbc *fbc = &dev_priv->fbc;
1038
1039         if (!plane->has_fbc || !plane_state)
1040                 return;
1041
1042         mutex_lock(&fbc->lock);
1043         __intel_fbc_post_update(crtc);
1044         mutex_unlock(&fbc->lock);
1045 }
1046
1047 static unsigned int intel_fbc_get_frontbuffer_bit(struct intel_fbc *fbc)
1048 {
1049         if (fbc->crtc)
1050                 return to_intel_plane(fbc->crtc->base.primary)->frontbuffer_bit;
1051         else
1052                 return fbc->possible_framebuffer_bits;
1053 }
1054
1055 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1056                           unsigned int frontbuffer_bits,
1057                           enum fb_op_origin origin)
1058 {
1059         struct intel_fbc *fbc = &dev_priv->fbc;
1060
1061         if (!HAS_FBC(dev_priv))
1062                 return;
1063
1064         if (origin == ORIGIN_GTT || origin == ORIGIN_FLIP)
1065                 return;
1066
1067         mutex_lock(&fbc->lock);
1068
1069         fbc->busy_bits |= intel_fbc_get_frontbuffer_bit(fbc) & frontbuffer_bits;
1070
1071         if (fbc->crtc && fbc->busy_bits)
1072                 intel_fbc_deactivate(dev_priv, "frontbuffer write");
1073
1074         mutex_unlock(&fbc->lock);
1075 }
1076
1077 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1078                      unsigned int frontbuffer_bits, enum fb_op_origin origin)
1079 {
1080         struct intel_fbc *fbc = &dev_priv->fbc;
1081
1082         if (!HAS_FBC(dev_priv))
1083                 return;
1084
1085         mutex_lock(&fbc->lock);
1086
1087         fbc->busy_bits &= ~frontbuffer_bits;
1088
1089         if (origin == ORIGIN_GTT || origin == ORIGIN_FLIP)
1090                 goto out;
1091
1092         if (!fbc->busy_bits && fbc->crtc &&
1093             (frontbuffer_bits & intel_fbc_get_frontbuffer_bit(fbc))) {
1094                 if (fbc->active)
1095                         intel_fbc_recompress(dev_priv);
1096                 else if (!fbc->flip_pending)
1097                         __intel_fbc_post_update(fbc->crtc);
1098         }
1099
1100 out:
1101         mutex_unlock(&fbc->lock);
1102 }
1103
1104 /**
1105  * intel_fbc_choose_crtc - select a CRTC to enable FBC on
1106  * @dev_priv: i915 device instance
1107  * @state: the atomic state structure
1108  *
1109  * This function looks at the proposed state for CRTCs and planes, then chooses
1110  * which pipe is going to have FBC by setting intel_crtc_state->enable_fbc to
1111  * true.
1112  *
1113  * Later, intel_fbc_enable is going to look for state->enable_fbc and then maybe
1114  * enable FBC for the chosen CRTC. If it does, it will set dev_priv->fbc.crtc.
1115  */
1116 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1117                            struct intel_atomic_state *state)
1118 {
1119         struct intel_fbc *fbc = &dev_priv->fbc;
1120         struct intel_plane *plane;
1121         struct intel_plane_state *plane_state;
1122         bool crtc_chosen = false;
1123         int i;
1124
1125         mutex_lock(&fbc->lock);
1126
1127         /* Does this atomic commit involve the CRTC currently tied to FBC? */
1128         if (fbc->crtc &&
1129             !intel_atomic_get_new_crtc_state(state, fbc->crtc))
1130                 goto out;
1131
1132         if (!intel_fbc_can_enable(dev_priv))
1133                 goto out;
1134
1135         /* Simply choose the first CRTC that is compatible and has a visible
1136          * plane. We could go for fancier schemes such as checking the plane
1137          * size, but this would just affect the few platforms that don't tie FBC
1138          * to pipe or plane A. */
1139         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
1140                 struct intel_crtc_state *crtc_state;
1141                 struct intel_crtc *crtc = to_intel_crtc(plane_state->hw.crtc);
1142
1143                 if (!plane->has_fbc)
1144                         continue;
1145
1146                 if (!plane_state->uapi.visible)
1147                         continue;
1148
1149                 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
1150
1151                 crtc_state->enable_fbc = true;
1152                 crtc_chosen = true;
1153                 break;
1154         }
1155
1156         if (!crtc_chosen)
1157                 fbc->no_fbc_reason = "no suitable CRTC for FBC";
1158
1159 out:
1160         mutex_unlock(&fbc->lock);
1161 }
1162
1163 /**
1164  * intel_fbc_enable: tries to enable FBC on the CRTC
1165  * @crtc: the CRTC
1166  * @state: corresponding &drm_crtc_state for @crtc
1167  *
1168  * This function checks if the given CRTC was chosen for FBC, then enables it if
1169  * possible. Notice that it doesn't activate FBC. It is valid to call
1170  * intel_fbc_enable multiple times for the same pipe without an
1171  * intel_fbc_disable in the middle, as long as it is deactivated.
1172  */
1173 void intel_fbc_enable(struct intel_atomic_state *state,
1174                       struct intel_crtc *crtc)
1175 {
1176         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1177         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
1178         const struct intel_crtc_state *crtc_state =
1179                 intel_atomic_get_new_crtc_state(state, crtc);
1180         const struct intel_plane_state *plane_state =
1181                 intel_atomic_get_new_plane_state(state, plane);
1182         struct intel_fbc *fbc = &dev_priv->fbc;
1183         struct intel_fbc_state_cache *cache = &fbc->state_cache;
1184
1185         if (!plane->has_fbc || !plane_state)
1186                 return;
1187
1188         mutex_lock(&fbc->lock);
1189
1190         if (fbc->crtc) {
1191                 if (fbc->crtc != crtc ||
1192                     !intel_fbc_cfb_size_changed(dev_priv))
1193                         goto out;
1194
1195                 __intel_fbc_disable(dev_priv);
1196         }
1197
1198         drm_WARN_ON(&dev_priv->drm, fbc->active);
1199
1200         intel_fbc_update_state_cache(crtc, crtc_state, plane_state);
1201
1202         /* FIXME crtc_state->enable_fbc lies :( */
1203         if (!cache->plane.visible)
1204                 goto out;
1205
1206         if (intel_fbc_alloc_cfb(dev_priv,
1207                                 intel_fbc_calculate_cfb_size(dev_priv, cache),
1208                                 plane_state->hw.fb->format->cpp[0])) {
1209                 cache->plane.visible = false;
1210                 fbc->no_fbc_reason = "not enough stolen memory";
1211                 goto out;
1212         }
1213
1214         if ((IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv)) &&
1215             plane_state->hw.fb->modifier != I915_FORMAT_MOD_X_TILED)
1216                 cache->gen9_wa_cfb_stride =
1217                         DIV_ROUND_UP(cache->plane.src_w, 32 * fbc->threshold) * 8;
1218         else
1219                 cache->gen9_wa_cfb_stride = 0;
1220
1221         drm_dbg_kms(&dev_priv->drm, "Enabling FBC on pipe %c\n",
1222                     pipe_name(crtc->pipe));
1223         fbc->no_fbc_reason = "FBC enabled but not active yet\n";
1224
1225         fbc->crtc = crtc;
1226 out:
1227         mutex_unlock(&fbc->lock);
1228 }
1229
1230 /**
1231  * intel_fbc_disable - disable FBC if it's associated with crtc
1232  * @crtc: the CRTC
1233  *
1234  * This function disables FBC if it's associated with the provided CRTC.
1235  */
1236 void intel_fbc_disable(struct intel_crtc *crtc)
1237 {
1238         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1239         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
1240         struct intel_fbc *fbc = &dev_priv->fbc;
1241
1242         if (!plane->has_fbc)
1243                 return;
1244
1245         mutex_lock(&fbc->lock);
1246         if (fbc->crtc == crtc)
1247                 __intel_fbc_disable(dev_priv);
1248         mutex_unlock(&fbc->lock);
1249 }
1250
1251 /**
1252  * intel_fbc_global_disable - globally disable FBC
1253  * @dev_priv: i915 device instance
1254  *
1255  * This function disables FBC regardless of which CRTC is associated with it.
1256  */
1257 void intel_fbc_global_disable(struct drm_i915_private *dev_priv)
1258 {
1259         struct intel_fbc *fbc = &dev_priv->fbc;
1260
1261         if (!HAS_FBC(dev_priv))
1262                 return;
1263
1264         mutex_lock(&fbc->lock);
1265         if (fbc->crtc) {
1266                 drm_WARN_ON(&dev_priv->drm, fbc->crtc->active);
1267                 __intel_fbc_disable(dev_priv);
1268         }
1269         mutex_unlock(&fbc->lock);
1270 }
1271
1272 static void intel_fbc_underrun_work_fn(struct work_struct *work)
1273 {
1274         struct drm_i915_private *dev_priv =
1275                 container_of(work, struct drm_i915_private, fbc.underrun_work);
1276         struct intel_fbc *fbc = &dev_priv->fbc;
1277
1278         mutex_lock(&fbc->lock);
1279
1280         /* Maybe we were scheduled twice. */
1281         if (fbc->underrun_detected || !fbc->crtc)
1282                 goto out;
1283
1284         drm_dbg_kms(&dev_priv->drm, "Disabling FBC due to FIFO underrun.\n");
1285         fbc->underrun_detected = true;
1286
1287         intel_fbc_deactivate(dev_priv, "FIFO underrun");
1288 out:
1289         mutex_unlock(&fbc->lock);
1290 }
1291
1292 /*
1293  * intel_fbc_reset_underrun - reset FBC fifo underrun status.
1294  * @dev_priv: i915 device instance
1295  *
1296  * See intel_fbc_handle_fifo_underrun_irq(). For automated testing we
1297  * want to re-enable FBC after an underrun to increase test coverage.
1298  */
1299 int intel_fbc_reset_underrun(struct drm_i915_private *dev_priv)
1300 {
1301         int ret;
1302
1303         cancel_work_sync(&dev_priv->fbc.underrun_work);
1304
1305         ret = mutex_lock_interruptible(&dev_priv->fbc.lock);
1306         if (ret)
1307                 return ret;
1308
1309         if (dev_priv->fbc.underrun_detected) {
1310                 drm_dbg_kms(&dev_priv->drm,
1311                             "Re-allowing FBC after fifo underrun\n");
1312                 dev_priv->fbc.no_fbc_reason = "FIFO underrun cleared";
1313         }
1314
1315         dev_priv->fbc.underrun_detected = false;
1316         mutex_unlock(&dev_priv->fbc.lock);
1317
1318         return 0;
1319 }
1320
1321 /**
1322  * intel_fbc_handle_fifo_underrun_irq - disable FBC when we get a FIFO underrun
1323  * @dev_priv: i915 device instance
1324  *
1325  * Without FBC, most underruns are harmless and don't really cause too many
1326  * problems, except for an annoying message on dmesg. With FBC, underruns can
1327  * become black screens or even worse, especially when paired with bad
1328  * watermarks. So in order for us to be on the safe side, completely disable FBC
1329  * in case we ever detect a FIFO underrun on any pipe. An underrun on any pipe
1330  * already suggests that watermarks may be bad, so try to be as safe as
1331  * possible.
1332  *
1333  * This function is called from the IRQ handler.
1334  */
1335 void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv)
1336 {
1337         struct intel_fbc *fbc = &dev_priv->fbc;
1338
1339         if (!HAS_FBC(dev_priv))
1340                 return;
1341
1342         /* There's no guarantee that underrun_detected won't be set to true
1343          * right after this check and before the work is scheduled, but that's
1344          * not a problem since we'll check it again under the work function
1345          * while FBC is locked. This check here is just to prevent us from
1346          * unnecessarily scheduling the work, and it relies on the fact that we
1347          * never switch underrun_detect back to false after it's true. */
1348         if (READ_ONCE(fbc->underrun_detected))
1349                 return;
1350
1351         schedule_work(&fbc->underrun_work);
1352 }
1353
1354 /*
1355  * The DDX driver changes its behavior depending on the value it reads from
1356  * i915.enable_fbc, so sanitize it by translating the default value into either
1357  * 0 or 1 in order to allow it to know what's going on.
1358  *
1359  * Notice that this is done at driver initialization and we still allow user
1360  * space to change the value during runtime without sanitizing it again. IGT
1361  * relies on being able to change i915.enable_fbc at runtime.
1362  */
1363 static int intel_sanitize_fbc_option(struct drm_i915_private *dev_priv)
1364 {
1365         if (i915_modparams.enable_fbc >= 0)
1366                 return !!i915_modparams.enable_fbc;
1367
1368         if (!HAS_FBC(dev_priv))
1369                 return 0;
1370
1371         if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9)
1372                 return 1;
1373
1374         return 0;
1375 }
1376
1377 static bool need_fbc_vtd_wa(struct drm_i915_private *dev_priv)
1378 {
1379         /* WaFbcTurnOffFbcWhenHyperVisorIsUsed:skl,bxt */
1380         if (intel_vtd_active() &&
1381             (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))) {
1382                 drm_info(&dev_priv->drm,
1383                          "Disabling framebuffer compression (FBC) to prevent screen flicker with VT-d enabled\n");
1384                 return true;
1385         }
1386
1387         return false;
1388 }
1389
1390 /**
1391  * intel_fbc_init - Initialize FBC
1392  * @dev_priv: the i915 device
1393  *
1394  * This function might be called during PM init process.
1395  */
1396 void intel_fbc_init(struct drm_i915_private *dev_priv)
1397 {
1398         struct intel_fbc *fbc = &dev_priv->fbc;
1399
1400         INIT_WORK(&fbc->underrun_work, intel_fbc_underrun_work_fn);
1401         mutex_init(&fbc->lock);
1402         fbc->active = false;
1403
1404         if (!drm_mm_initialized(&dev_priv->mm.stolen))
1405                 mkwrite_device_info(dev_priv)->display.has_fbc = false;
1406
1407         if (need_fbc_vtd_wa(dev_priv))
1408                 mkwrite_device_info(dev_priv)->display.has_fbc = false;
1409
1410         i915_modparams.enable_fbc = intel_sanitize_fbc_option(dev_priv);
1411         drm_dbg_kms(&dev_priv->drm, "Sanitized enable_fbc value: %d\n",
1412                     i915_modparams.enable_fbc);
1413
1414         if (!HAS_FBC(dev_priv)) {
1415                 fbc->no_fbc_reason = "unsupported by this chipset";
1416                 return;
1417         }
1418
1419         /* This value was pulled out of someone's hat */
1420         if (INTEL_GEN(dev_priv) <= 4 && !IS_GM45(dev_priv))
1421                 intel_de_write(dev_priv, FBC_CONTROL,
1422                                500 << FBC_CTL_INTERVAL_SHIFT);
1423
1424         /* We still don't have any sort of hardware state readout for FBC, so
1425          * deactivate it in case the BIOS activated it to make sure software
1426          * matches the hardware state. */
1427         if (intel_fbc_hw_is_active(dev_priv))
1428                 intel_fbc_hw_deactivate(dev_priv);
1429 }